Substrate bias generator for semiconductor devices

Abstract: A substrate bias generator for supplying a predetermined substrate bias voltage to a semiconductor device includes a charge pumping circuit (41) in which there is provided a rectifying pMOS transistor formed in an n-well . The n-well is maintained at a negative voltage level during the pumping operation. As a result, the threshold voltage of the rectifying pMOS transistor is prevented from increasing to enable the bias voltage to be supplied at a higher efficiency.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a substrate bias generator in accordance with the precharacterizing part of claim 1. Such a substrate bias generator is known from EP-A-0 215 429. Description of the Prior Art In a semiconductor integrated circuit device, such as a memory, a substrate voltage V BB in the order of -2 to -3.5 V is supplied to a semiconductor substrate for effectively retaining data stored in memory cells. This substrate voltage V BB is set so as to be at a value lower than the ground voltage (OV) and is supplied to the substrate by a pumping operation by capacitors, as disclosed for example in the Japanese Patent KOKAI (laid-open) Publication No. 1-154395 (1989). Fig. 1 shows an example of the conventional substrate bias generator. An oscillator, not shown, supplies antiphase clock pulses by means of inverters 7 and 9 to a pair of capacitors 1 and 2, each formed by a pMOS transistor, so that these capacitors 1 and 2 will perform alternate charge-pumping operations. Rectifying pMOS transistors 3 and 4 are connected to a terminal P0 of the capacitor 1 and a terminal Q0 of the capacitor 2, respectively, while being connected in common to a node 9 from which the substrate voltage V BB is outputted. A pair of pMOS transistors 5 and 6 for discharging to a grounding line, which is at 0V or at the GND level, are connected to the terminal P 0 and Q 0 , respectively. The operation of the above described circuit is hereinafter explained briefly. It is first assumed that, with the level of the terminal R 0 of the capacitor 1 at the "H" level, or at 5V, and with the terminal P 0 of the capacitor 1 at the GND level due to discharging by means of the pMOS transistor 5, the voltage level at the terminal R 0 has been shifted by the inverter 7 from the "H" level to the "L" level or to 0V. The voltage level at the terminal P 0 of the capacitor 1 is lowered at this time from approximately 0V to close to -5V. However, when the voltage level exceeds the threshold voltage Vth of the pMOS transistor 3, the pMOS transistor 3 is turned on. Simultaneously, the gate voltage of the pMOS transistor 5 is at the voltage level at the terminal Q 0 , so that the transistor 4 is turned off. Thus the voltage level at the terminal P 0 is raised by the current from the node 9 to a value in the vicinity of the substrate voltage V BB plus threshold voltage (V BB + Vth). When the voltage at the terminal R 0 shifts to the "H" level, the voltage level at the terminal P 0 is also raised so as to follow the voltage shift at the terminal R 0 . Thus the pMOS transistor 3 is turned off, while the pMOS transistor 5 is turned on, as a result of which the voltage at the terminal P 0 is again reset to close to the ground level. Such charge pumping operation occurs simultaneously with the capacitor 2 and the pMOS transistors 5 and 6, so that substrate charges are drained alternately from the node 9 by means of pMOS transistors 5 and 6 to maintain a predetermine value of the substrate voltage V BB . However, the conventional circuit shown in Fig. 1 is inconvenient in that its pumping efficiency can not be raised sufficiently. That is, while the pMOS transistor 3 is formed in an n-well on the p-type semiconductor substrate, the n-well is connected to the terminal R 0 , as shown in Fig. 1, and is alternately supplied with the source voltage Vcc and the ground voltage GND. However, if our attention is directed to the pMOS transistor 3, the voltage level at the node 9 is approximately -2 to -3V almost steadfastly, so that, during the turn-on period of the transistor 3, the N-well voltage becomes higher about 2 to 3V than the source voltage. As a result, the threshold voltage Vth of the pMOS transistor 3 is raised. Referring to Fig. 2, which is a waveform diagram of the circuit shown in Fig. 1, while the voltage at the terminal P 0 becomes fixed at a level lower than the substrate voltage V BB by the threshold voltage Vth 0 for the low voltage level at the terminal R 0 , the larger the threshold voltage Vth 0 , the higher becomes the rate of decrease of the amount of charges passing through the pMOS transistor 3, so that the charge draining efficiency at they node 9 is correspondingly lowered. The same also applies to the pMOS transistor 4. A further known substrate bias generator of this kind is disclosed in the above mentioned EP-A-0 215 429 which is in correspondence with the precharacterizing part of claim 1. The last mentioned substrate bias generator includes in its pumping circuit a first and a second rectifying pMOS transistor and a first and a second resetting transistor, which transistors are formed altogether in an n-well within a p-substrate. This known substrate bias generator does not include a substrate level detector and means for driving an oscillator responsive to the results of detection by said substrate level detector. EP-A-0 051 532 describes a regulated MOS substrate bias generator comprising a substrate level detector detecting a voltage level of substrate and an oscillator which is controlled by the detection result of said substrate level detector. The circuit arrangement of the pumping circuit of the last mentioned known MOS substrate bias generator is different from that of the present substrate bias generator. Object and Summary of the Invention It is an object of the present invention to provide a substrate bias generator capable of performing a pumping operation at a higher efficiency. The above object is solved by a substrate bias generator as set out in claim 1. Depending claims 2 to 5 are each specifying advantageous developments thereof. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram of a pumping circuit in a conventional substrate bias circuit. Fig. 2 is a waveform diagram for illustrating the pumping operation by the circuit shown in Fig. 1. Fig. 3 is a block diagram showing an embodiment of an overall substrate bias circuit according to the present invention. Fig. 4 is a circuit diagram showing a concrete circuit arrangement of a pumping circuit of the substrate bias circuit shown in Fig. 3. Fig. 5 is a cross-sectional view of the portion of a semiconductor chip mounting rectifying pMOS transistors for illustrating the relation of the n-well and the rectifying pMOS transistors according to the present invention. Fig. 6 is a waveform diagram for illustrating the pumping operation performed by the substrate bias circuit shown in Fig. 4. Detailed Description of Preferred Embodiment A substrate bias generator according to a preferred embodiment of the present invention, employed in a dynamic RAM, is hereinafter explained by referring to Fig. 3. Referring to Fig. 3, the substrate bias generator is constituted by a pumping circuit 41 for supplying a substrate voltage V BB by a charge pumping operation, a substrate level detector 42 for detecting whether the substrate voltage V BB is a predetermined voltage, a delay circuit 43 for delaying the signal indicating the result of detection, and an oscillator 43 adapted for starting its oscillation by a signal from the delay circuit 43. With the present substrate bias generator, when the substrate voltage V BB has been raised to higher than a predetermined voltage, the substrate level detector 42 outputs a signal conforming to the result of detection. This signal is supplied by means of the delay circuit 43 composed by a multistage inverter to the oscillator 44 where rectangular wave signals of a predetermined frequency are generated. These rectangular wave signals are amplified and transmitted to a pumping circuit 41 as later described. By the operation of the pumping circuit 41, the substrate voltage V BB at a predetermined voltage value is supplied to a substrate, not shown, on which a memory core of a dynamic memory and peripheral circuits are formed. When the substrate voltage V BB falls to lower than the predetermined voltage, the substrate level detector 42 detects such voltage decrease, so that oscillation at the oscillator 44 is brought to a stop by the signal from the detector 42. The circuit arrangement of the pumping circuit 41, which is essential to the present embodiment, is explained by referring to Fig. 4. In this figure, the pumping circuit 41 includes capacitors 11 and 12, each formed by a pMOS transistor. These capacitors are formed by connecting the source, drain and channels regions of the pMOS transistors connected in common to form nodes R 1 and S 1 as one terminals, with gate side nodes P 1 and Q 1 as the other terminals. Rectangular wave signals, produced by the oscillator 44, are supplied to the nodes R 1 and S 1 of the capacitors 11 and 12 by means of amplifier-inverters. Thus the rectangular wave signals are supplied to the node R 1 of the capacitor 11 by means of a two-stage inverter consisting of an inverter composed of a pMOS transistor 17 and an nMOS transistor 18, and an inverter composed of a pMOS transistor 19 and an nMOS transistor 20. The rectangular wave signals are supplied to the node S 1 of the capacitor 12 by means of a single-stage inverter consisting of an inverter composed of a pMOS transistor 21 and an nMOS transistor 22. Because of the difference in the number of inverter stages, rectangular wave signals which are antiphase with respect to each other are supplied to the nodes R 1 and S 1 of the capacitors 11 and 12, respectively. Rectifying pMOS transistor 13 and 14 are provided between the node P 1 of the capacitor 11 and the node 27 outputting the substrate voltage V BB and between the node Q 1 of the capacitor 12 and the node 27, respectively. One of the source or the drain of the pMOS transistor 13 is connected to the node P 1 of the capacitor 11 and the other of the source or the drain of the transistor 13 is connected to the node 27. One of the source or the drain of the pMOS transistor 14 is connected to the node Q 1 of the capacitor 12 and the other of the source or the drain of the transistor 14 is connected to the node 27. The gate of the pMOS transistor 13 is connected to the node P 1 and to the gate of the pMOS transistor 16. The gate of the pMOS transistor 14 is connected to the node Q 1 and to the gate of the pMOS transistor 15. Since the gates of the pMOS transistors 13 and 14 are connected to their drains, the transistors 13 and 14 act as rectifiers. It is noted that these pMOS transistors 13 and 14 are each formed in an n-well. Due to the parasitic capacity C S as later described, the n-well is maintained at a negative voltage to prevent the threshold voltage from increasing. One of the source or the drain of the pMOS transistor 15 is connected to the node P 1 , while the gate of the pMOS transistor 15 is connected to the node Q 1 . One of the source or the drain of the pMOS transistor 16 is connected to the node Q 1 , while the gate of the pMOS transistor 16 is connected to the node P 1 . The other of the source or the drain of each of the pMOS transistors 15 and 16 is supplied with the ground voltage GND. The voltages at the nodes R 1 and S 1 are supplied to the wells of the pMOS transistors 15 and 16. The pMOS transistor 15 and 16 function as resetting transistors for discharging the electrical charges at the nodes P 1 and Q 1 to grounding lines supplying the grounding voltage GND to clamp or reset the nodes P 1 and Q 1 at the grounding voltage GND. In the present pumping circuit, pMOS transistors 23 to 26 are connected to n-wells X 1 and Y 1 of the pMOS transistors 13 and 14, so that the n-wells X 1 and Y 1 are maintained at the negative voltage by these pMOS transistors 23 to 26. The grounding voltage GND is supplied to one of the source or the drain of each of the pMOS transistors 23 to 26. To the n-well X 1 of the pMOS transistor 13 are connected the other of the source or the drain of the pMOS transistor 23, the gate of the pMOS transistor 24 and the gate as well as the other of the source or the drain of the pMOS transistor 25. To the n-well Y 1 of the pMOS transistor 14 are connected the other of the source or the drain of the pMOS transistor 24, the gate of the pMOS transistor 23 and the gate as well as the other of the source or the drain of the pMOS transistor 26. The well or the substrate, in which the channel of the pMOS transistor 23 is formed, is supplied with the voltage at the node R 1 , whereas the well or substrate, in which the channel of the pMOS transistor 24 is formed, is supplied with the voltage at the node S 1 . With the above described circuit, a highly efficient pumping operation may be realized because the n-wells X 1 and Y 1 are maintained at the negative voltages due to the parasitic capacities C S proper to these n-wells. Turning to Fig. 5 for illustrating the parasitic capacity C S , an n-well 32 is formed on the n-type semiconductor substrate 31, and p-type impurity diffusion regions 33 and 34 are formed on the n-well 32 in isolation from each other. A gate electrode 35 in formed on a region between these p-type impurity diffusion regions 33 and 34 by the interposition of a gate insulating film, not shown. When these impurity diffusion regions 33 and 34 and the gate electrode 35 constitute the pMOS transistor 13 or 14 in the circuit of Fig. 1, the n-well 32 becomes the n-well X 1 or Y 1 in Fig. 4. The parasitic capacity is formed at the junction between the n-well and each of the p type impurity diffusion regions 33 and 34. Above all, when the impurity diffusion region 33 is connected to the nodes P 1 and Q 1 in Fig. 4, the n-well 32 is affected by voltage changes at the nodes P 1 and Q 1 , due to capacitive coupling by the parasitic capacity C S between the region 33 and the n-well 32. More specifically, as a result of the coupling by the parasitic capacity C S , the n-well 32 acts as if it were driven by signals from the oscillator 44. Then, turning to Fig. 6, the operation of the pumping circuit shown in Fig. 4, above all, the operation of holding the negative voltage of the n-wells X 1 and Y 1 by the pMOS transistors 23 to 26, will be explained. At time t 0 , the node R 1 is at the "H" level which is the Vcc level approximately equal to 5V, while the node P 1 of the capacitor 11 is approximately at the grounding voltage GND, because the pMOS transistor 15 is in the current-conducting state. It is noted that the node S 1 on the opposite side is at the "L" level or GND level approximately equal to 0V, whereas the node Q 1 is at a level lower than the GND level, such as at -V BB -Vth 1 , where Vth 1 is the threshold voltage of each of the pMOS transistors 13 and 14. At this time, the n-well X 1 is at a level close to the GND level. At time t 1 , the voltage level at node R 1 shifts from the "H" level to the "L" level or GND level, approximately equal to 0V, by the signal from the oscillator 44. Then, by the capacitive coupling of the capacitor 11 by the pMOS transistor, the voltage level at the node P 1 is lowered from the level of the grounding voltage GND, such that, at time t 2 , the voltage level at the node P 1 falls to a level close to, for example, -5V. Turning to the voltage level of the n-well X 1 , the n-well X 1 follows the voltage level decrease at the node P 1 , on account of the capacitive coupling due to the parasitic capacity C S between the n-well and the node P 1 . Thus the voltage level at the n-well X 1 shifts from the level close to the GND level to the negative level, as shown by a dotted line in Fig. 6. With the n-well X 1 thus shifted to the negative voltage level, the pMOS transistor 24 is in the current-conducting state, while the voltage level at the opposite side n-well Y 1 is clamped or reset to the grounding voltage GND, even though it is raised under the influence of the parasitic capacity C S of the pMOS transistor 14. Since the gate voltage of the pMOS transistor 23 is not in excess of the threshold voltage Vth, the pMOS transistor 23 is in the turn-off state, so that the grounding voltage GND is not supplied at this stage to the n-well X 1 by means of the pMOS transistor 23. Thus the n-well X 1 is maintained at the negative voltage level. The pMOS transistor 25, acting as a diode, is in the current-conducting state when the voltage level at the n-well X 1 exceeds the threshold voltage Vth of the pMOS transistor 25. Thus the pMOS transistor 25 functions to prevent the voltage level at the n-well X 1 from decreasing excessively to prevent the forward current from flowing from the p-type semiconductor substrate towards the n-well X 1 as a consequence of the excessive decrease of the voltage level at the n-well X 1 . It will be noted that the forward current tends to destruct DRAM data. When the n-well X 1 is maintained in this manner at the negative voltage level within a range in which the forward current is not generated with respect to the substrate, the threshold voltage Vth 1 of the pMOS transistor 13 is decreased in a manner as will be explained subsequently. Turning to the state of the pMOS transistor 13 at time t 2 , when the voltage level at the node P 1 is lowered to a level close to -5V, the voltage level at the node P 1 is supplied to the gate of the transistor 13, so that the transistor is turned on and hence the current may flow from the node 27 towards the node P 1 . When the circuit operates in this manner, the substrate voltage V BB is lowered. With the current flowing towards the node P 1 , the voltage level at the node P 1 is raised. When the voltage level at the node P 1 becomes higher than the substrate voltage V BB or the source voltage less the threshold voltage Vth 1 of the pMOS transistor 13, the state of the pMOS transistor 13 is changed from the current-conducting or turn-on state to the turn-off state. It is noted that the threshold voltage Vth 1 of the pMOS transistor 13 has a small value, because the n-well X 1 is maintained at the negative voltage, as explained hereinabove. That is, since the voltage difference between the level at the n-well X 1 and the substrate voltage V BB is small, it becomes possible to prevent the threshold voltage from increasing. Thus, for the same voltage level at the node P 1 , a larger current is allowed to flow through the pMOS transistor 13 and more charges may be carried off from the node 27 in proportion to the reduction in the threshold voltage Vth 1 . It is noted that, at time t 2 , since the voltage level at the node Q 1 or the gate of the pMOS transistor 14 is raised to a positive value, the pMOS transistor 14 is not rendered current conductive and, conversely, the pMOS transistor 16 is rendered current conductive, so that the current is allowed to flow from the mode Q 1 to the grounding voltage GND by means of the pMOS transistor 16. After the pMOS transistor 13 is rendered non-conductive, the voltage level at the node R 1 shifts at the next time t 3 from the "L" level to the "H" level. The voltage level at the node P 1 capacitively coupled to the node R 1 also shifts by a value equal to the source voltage Vcc from the negative level which is equal to the substrate voltage V BB less the threshold voltage Vth 1 or -(V BB + Vth 1 ). As a result, the pMOS transistor 13 continues to be turned off and the pMOS transistor 15 is turned on, so that the voltage level at the node P 1 is changed towards the grounding level GND until it is reset to the state shown at time t 0 . Turning to the pMOS transistors 23 to 26, the potential at the n-well X 1 is slightly raised to the positive side, with rise in voltage level at the node P 1 , due to the capacitive coupling in the pMOS transistor 13. However, the n-well Y 1 is maintained at this time at the negative voltage due to the capacitive coupling of the pMOS transistor 14. Thus the pMOS transistor 23, the gate voltage of which is the voltage level at the n-well Y 1 , is rendered conductive, so that the n-well X 1 is discharged immediately so as to be maintained at or near the grounding voltage GND. The pumping circuit repeats the above described sequence of operations to supply the predetermined substrate voltage V BB from the node 27. Above all, with the present substrate bias generator, the n-well of the rectifying pMOS transistor is maintained during its operation at the negative voltage, the threshold voltage Vth of the transistor may be lowered for improving the pumping efficiency of the pumping circuit. Or in other words, the substrate voltage V BB may be at a lower value in proportion to the reduction of the threshold voltage of the rectifying pMOS transistor to improve data retention properties. It is noted that, if a sufficient capacity can not be obtained with the parasitic capacity between the source-drain and the well of the pMOS transistors 13 or 14, it is possible to provide capacitors formed by pMOS transistors 28 and 29 between the node S 1 and the n-well Y 1 and between the node R 1 and the n-well X 1 , respectively.

Claims: A substrate bias generator for generating a predetermined substrate bias voltage (V BB ) as required for a semiconductor device comprising an oscillator (44) for generating signals of a certain predetermined frequency, a charge pumping circuit (41) operated by said signals from said oscillator for supplying said substrate bias voltage (V BB ) through a pair of rectifying pMOS transistors (13, 14) each formed in a respective n-well (32, X 1 , Y 1 ), a substrate bias terminal (27) provided at a junction point between one of the source or drain of each of said pMOS transistors (13, 14), a pair of capacitors (11, 12) connected between said other of the source or drain of each of said pMOS transistors (13, 14) and an input supplied with signals from said oscillator (44), and a pair of resetting transistors (15, 16) connected to the other of the source or the drain of each of said rectifying pMOS transistors (13, 14) not connected to said junction point, the sources or the drains of each resetting transistor (15, 16) being respectively connected to ground and their gates being cross-coupled to the gates of the rectifying pMOS transistors (14, 13) connected to the other resetting transistor, characterized by a substrate level detector (42) for detecting the voltage level of a substrate (31) of said semiconductor device, said oscillator (44) being responsive to the results of detection by said substrate level detector (42), and a pair of pMOS transistors (23, 24), the drains of which are connected to ground, the sources of which are connected to the n-wells (X 1 , Y 1 ) of the rectifying pMOS transistors (13, 14) and the gates of which are cross-coupled to the n-wells (Y 1 , X 1 ) of the rectifying pMOS transistors. The substrate bias generator according to claim 1, characterised in that said charge pumping circuit (41) further comprises capacitances (C s , 28, 29) formed between the source or drain and said n-well (x 1 , Y 1 ) of each rectifying pMOS transistor (13, 14). The substrate bias generator according to claim 2, wherein said capacitances (C s ) are the parasitic capacitances between said n-well and the source or drain of each rectifying pMOS transistor (13, 14). The substrate bias generator according to claim 2, wherein said capacitances are formed of a respective MOS transistor provided between the respective n-well of the rectifying pMOS transistors and an input (R 1 , S 1 ) of said signals from said oscillator (44). The substrate bias generator according to claim 1, wherein said resetting transistors (15, 16) are performing voltage resetting to the ground level by having their wells biased by said signals from said oscillator (44).

Inventors: MATSUMURA YOUICHI C O SONY COR, MATSUMURA, YOUICHI, Matsumura, Youichi, c/o Sony Corporation
Applicants: SONY CORP, SONY CORPORATION
Application year: 1991
Main classification: G11C5
IPC codes: G11C11, H01L27, G11C5, H01L21