An electrically-erasable, electrically-programmable read-only memory cell with a selectable threshold voltage and methods for its use

Abstract: A field effect transistor memory cell having a selectable threshold voltage is formed in a semiconductor layer (18). An n-channel electrically-erasable, electrically-programmable read-only memory cell (12) is formed and includes a source (14) and a drain (16) separated by a channel (20), a tunneling window (22) adjacent drain (16), a floating gate (24) and a control gate (26) capacitively coupled to channel (20). N-channel memory cell (12) is operable to charge and discharge floating gate (24) by Fowler-Nordheim tunneling upon the application of voltages to control gate (26) and drain (16). A p-channel field effect transistor (30) is formed and includes a source (34) in a drain (36) spaced by a channel (38). Floating gate (24) is insulatively disposed adjacent channel (38) such that the conductance of channel (38) is controlled by floating gate (24). A threshold control circuit (76) is provided for biasing channel (38) of p-channel field effect transistor (30) in relationship to control gate (26). A monitoring circuit (90) controls the application of voltage to control gate (26) in response to conduction between source (34) and drain (36) of p-channel field effect transistor (30).

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates generally to memory devices, and more particularly to electrically-erasable, electrically-programmable read-only memories with a selectable threshold voltage and methods for use of such memories. BACKGROUND OF THE INVENTION The most widely used electrically-erasable, electrically-programmable, read-only cell is an n-channel field effect transistor with an additional floating gate structure disposed between the channel and the control gate. By charging the floating gate with electrons, a logic "zero" can be programmed into the cell, while allowing the floating gate to remain uncharged programs a logic "one." This is due to the fact that the charge on the floating gate controls the conductance of the underlying channel area, thereby determining whether a current will be sensed between the source and the drain when reading voltages are applied therebetween. As in the case of the conventional field effect transistor, the channel of a EEPROM cell with an uncharged floating gate (a non-programmed cell) has a threshold voltage V t . This threshold voltage V t is primarily a function of the material used to form the channel and can be controlled within limits by the implantation of dopants in the channel during the fabrication of the cell. During the read operation, the control gate must be brought to a potential in excess of the threshold voltage V t , as determined by the capacitive coupling between the control gate and the floating gate and floating gate and the channel, in order for current to flow between the source and the drain when a voltage potential is created between them. By charging the floating gate with electrons, however, the threshold voltage V t can be raised. One means of effecting the charging of the floating gate is through Fowler-Nordheim tunneling. In the n-channel EEPROM, when the control gate is brought to a sufficiently high potential in relationship to the drain, electrons can be made to tunnel through a thin oxide tunneling region adjacent the drain to the floating gate, thereby charging it. By raising the threshold voltage by charging the floating gate, a logic "zero" is programmed into the cell due to the fact that the normal reading voltage applied to the control gate will not exceed the potential necessary to allow the current flow in the channel as raised by the charged floating gate, and therefore no current can be sensed when proper source and drain reading voltages are applied. In principle, it is possible to set the threshold voltage of a EEPROM to any value by varying the amount of charge residing on the floating gate. This may be done, for instance, by varying the pulse height, duration and/or the number of pulses used in creating the voltage potential between the control gate and the drain. In practice, however, this is not an easy task. First, the threshold voltage has a logarithmic dependency on pulse duration. Further, this process is very slow, requiring unacceptable expenditures of time to program the cell to extreme values. Additionally, variations from cell to cell, especially due to differences in the tunnel oxides used for Fowler-Nordheim tunneling, create consistency problems during array operation. Finally, trapping of materials in the oxide will change the current-voltage (I-V) characteristics of the tunnel diode over time, which may require frequent calibration cycles to determine the write/erase characteristics of the EEPROM cell. A self-limiting erase scheme for an EEPROM cell is disclosed in United States Patent No. 4,797,856. The cell includes drain and source regions formed on a substrate and separated by a channel region. An oxide layer is formed over the channel region, and a floating gate and a control gate respectively are formed over the oxide layer. Fowler-Nordheim tunneling is utilized for discharging the floating gate to erase the memory cell by causing the electrons to tunnel across the oxide layer. This device will allow the floating gate of an EEPROM cell to be erased to a predetermined value, thus controlling the threshold voltage of the cell. This device has a major disadvantage if it is ever desired to set the threshold voltage of an unprogrammed cell. In this case, the floating gate would have to be completely charged, and then erased back to a point where the charge remaining on the floating gate set the threshold voltage of the cell to the desired value. Thus, a need has arisen for an electrically-erasable read only memory cell in which the threshold voltage of the channel can be set either during the write cycle or the erase cycle. Such a device would be self-controlling, and would minimize the need for precise controlling of the voltage application during the write and erase cycles. Further, this device should be capable of fabrication into an integrated circuit form using conventional techniques. Finally, the device should be compatible with the peripheral devices currently used with EEPROM cells. SUMMARY OF THE INVENTION According to the present invention as specified in claim 1 there is provided an electrically-erasable, electrically-programmable read only memory (EEPROM) cell formed in a semiconductor layer of a first conductivity type and including circuitry for controlling the threshold voltage of the memory cell, the memory cell comprising, a first transistor formed in the semiconductor layer and having a source region and a drain region of a second conductivity type, said source and drain regions being separated by a channel region, a second transistor formed in the semiconductor layer and having a source region and a drain region of the first conductivity type, said source and drain regions being separated by a channel region, the drain region of the second transistor being connected to a ground terminal, a floating gate having a first portion insulatively adjacent the channel region of the first transistor and a second portion insulatively adjacent the channel region of the second transistor, a control gate insulatively disposed adjacent the floating gate, and characterised in that the memory cell further comprises, a tank region of the second conductivity type formed in the semiconductor layer such that it is spaced from the first transistor, the second transistor being located in the tank region, the threshold voltage control circuitry coupled to the tank region and operable to bias the tank region to a predetermined threshold potential relative to the control gate such that the cell is self-controlling, monitoring circuitry responsive to a change in potential of the source region of the second transistor to control the application of potential on the control gate such that the charge on the floating gate stops increasing when a selected threshold potential is obtained. The present invention provides significant advantages over the prior art. A memory cell with an uncharged floating gate may have its threshold voltage set to a predetermined value without having to completely charge the floating gate and then erasing back to the desired value. The present device employs the standard voltages used during the operation of the widely used n-channel EEPROM cells. Consistency problems with attempts to adjust the threshold value by changing the characteristics of the voltage pulses used to program a memory cell are eliminated. The present cell uses structure and materials readily used in conventional EEPROM fabrication techniques. Finally, the ability to set the threshold voltage to any value within a specific range will allow the EEPROM cell to be used in various analog applications. Potential analog applications of the EEPROM cell with a write/erase mechanism to set the threshold voltage of the cell to a predetermined value include resistive ladders in a-d converters, and neural networks. BRIEF DESCRIPTION OF THE DRAWINGS Other advantages of the invention will be discerned when one refers to the following detailed description as taken in conjunction with the drawings, in which: FIGURE 1 is a schematic plan view of an electrically-erasable, electrically-programmable read-only memory (EEPROM) cell with a selectable threshold voltage according to the invention; FIGURE 2 is a greatly enlarged schematic elevational sectional view of an EEPROM cell with a selectable threshold voltage according to the invention taken substantially along line 2-2 of FIGURE 1; FIGURE 3 is a schematic sectional view of an EEPROM cell according to the invention taken substantially along line 3-3 of FIGURE 1; FIGURE 4 is a schematic sectional view of an EEPROM according to the invention taken substantially along line 4-4 of FIGURE 1; FIGURE 5 is a detailed electrical schematic diagram of a first monitoring circuit portion as used in the embodiment shown in FIGURE 1; FIGURE 6 is a detailed electrical schematic diagram of a second monitoring circuit portion as used in the embodiment shown in FIGURE 1; and FIGURE 7 is an electrical schematic diagram of a circuit portion of an EEPROM cell according to the invention. DETAILED DESCRIPTION OF THE INVENTION The preferred embodiment of the present invention is best understood by referring to FIGURES 1 through 7 of the drawings, like numerals being used for like and corresponding parts of the various drawings. A plan view of an electrically-erasable, electrically-programmable read only memory cell with a controlled write/erase mechanism to set the threshold voltage to a desired value is shown generally at 10 in FIGURE 1. An n-channel EEPROM cell 12 is formed by the diffusion of an n+ source region 14 and an n+ drain region 16 into an epitaxial layer 18. Source region 14 and drain region 16 are spaced by a channel area 20 (shown by diagonal hatching from the upper left to the lower right) of epitaxial layer 18. A thin oxide tunneling window 22 (illustrated by double crosshatching) is formed overlying channel region 20 adjacent drain region 16. A floating gate 24, the outline of which is indicated by a dotted line, is insulatively disposed over channel area 20 and disposed over tunneling window 22. A control gate 26 is insulatively disposed over floating gate 24. In a preferred embodiment shown in FIGURE 1, floating gate 24 and control gate 26 extend over a thick oxide region 28 to increase the capacitive coupling area between floating gate 24 and control gate 26. (Lateral boundaries of control gate and floating gate are coextensive; shown offset only for clarity.) A p-channel field effect transistor 30 is formed in a tank 32 of n-type material diffused into epitaxial layer 18. P-channel transistor 30 is formed by the diffusion of a p-type material into a source region 34 and a drain region 36. Source region 34 and drain region 36 are separated by a channel region 38 of n-tank 32. Floating gate 24 extends from n-channel EEPROM cell 12 to insulatively overlie and control channel area 38 of p-channel field effect transistor 30. A first feedback circuit is shown generally by dotted lines at 40 in FIGURE 1 for setting the threshold voltage V t of EEPROM cell 12 during an erase cycle. Output 42 of a drain voltage control circuit 44 is coupled by a contact to drain 16 of EEPROM cell 12 by a resistor 45 and a conductor 46. Source 14 of EEPROM cell 12 is coupled by a contact and conductor 48 to a non-inverting input 50 of an erase monitoring circuit 52. An inverting input 54 of erase monitoring circuit 52 is coupled to a reference voltage V ref , while the output 56 is connected to output 42 of drain voltage control circuit 44. A second feedback loop is shown by a dotted line generally at 58 for setting the threshold voltage of EEPROM cell 12 during a write (programming) cycle. Output 60 of gate voltage control circuitry 62 is coupled to control gate 26 by conductor 64. Output 60 of gate voltage control circuitry 62 is also connected to the non-inverting input 66 of a subtraction circuit 68 by conductor 70. The inverting input 72 of subtraction circuit 68 is connected to the output 74 of a threshold variation voltage control 76 by a conductor 78. Output 80 of subtraction circuit 68 is coupled to an n+ diffusion region 82 in tank 32 by conductor 84 and a contact. Output 80 of subtraction circuit 68 is also coupled by conductor 86 to the non-inverting input 88 of a write monitoring circuit 90. The inverting input 92 of monitoring circuit 90 is coupled by a conductor 94 and a contact to source region 34 of transistor 30. Output 96 is coupled by conductor 98 to output 60 of gate voltage control circuitry 62. FIGURE 2 shows a schematic cross-sectional view of EEPROM cell 12 as taken substantially along line 2-2 in FIGURE 1. In FIGURE 2, floating gate 24 is separated from channel region 20 by a gate oxide 100, and is adjacent thin oxide tunneling window 22. Floating gate 24 is insulated from the overlying control gate 26 by oxide layer 102. FIGURE 3 is a schematic cross-sectional view of field effect transistor 30 taken substantially along line 3-3 in FIGURE 1. In FIGURE 3, floating gate 24 is separated from channel region 38 by a gate oxide layer 104. Control gate 26 is separated from floating gate 24 by an oxide layer 102. FIGURE 4 depicts a schematic sectional elevational view taken substantially along line 4-4 of FIGURE 1. FIGURE 4 depicts oxide region 28 which is grown on substrate 18 using any one of a number of conventional methods. Oxide region 28 provides additional surface area over which control gate 26 and floating gate 24 can capacitively couple, and additionally, provides electrical isolation between transistor 12 and transistor 30. Oxide region 28 can be grown as a field oxide and used as a mask to self-align the implantation of n+ source/drain regions 14 and 16. The improved capacitive coupling allows a greater portion of the voltage applied to the control gate to be coupled onto the floating gate. The voltage applied to the control gate can thereby be reduced while retaining the same ability to control channel 20. FIGURE 5 is a schematic diagram of erase monitoring circuit 52 as shown in FIGURE 1. Input 50 is coupled by a conductor 108 to non-inverting input 110 of an operational amplifier 112. A resistor 113 provides a current path between non-inverting input 110 and ground. Input 54 is coupled by a conductor 114 to inverting input 116 of operational amplifier 112. Output 118 of operational amplifier 112 is coupled through a resistor 119 a conductor 120 to the drain 122 of transistor 124, the drain 126 of transistor 128 and the gate 130 of transistor 132. Transistor 124 provides for resetting erase monitoring circuitry 58. The gate 134 of transistor 124 is coupled to signal RESET, while the source 136 is grounded. Transistors 128 and 132 form a latch. Source 138 of transistor 128 is grounded while the gate 140 is coupled by conductor 141 to drain 142 of transistor 132. Source 144 of transistor 132 is grounded. A resistor 146 couples drain 126 of transistor 128 and gate 130 of transistor 132 to V dd . A resistor 148 couples gate 140 of transistor 128 and drain 142 of transistor 132 to V dd . Output 118 of operational amplifier 112 is additionally coupled by conductor 149 to gate 150 of output transistor 152. The source 154 of transistor 152 is grounded while the drain 156 is coupled to output 56 of erase monitoring circuitry 52. Output transistor provides a gate to selectively ground the output of drain voltage control circuitry 44, thereby controlling the voltage applied to drain 16. FIGURE 6 depicts a preferred embodiment of the subtraction circuitry 68 shown in FIGURE 1. Input 66 is coupled to a resistor 160 which is in turn coupled to a resistor 162 to form a voltage divider between input 66 and ground. The divided voltage is then provided to the non-inverting input 164 of an operational amplifier 166. Input 72 is coupled through a resistor 168 to the non-inverting input 170 of operational amplifier 166. The output of operational amplifier 166 represents the output of subtractor circuitry 68. Resistor 172 provides feedback from output 80 to inverting input 170 of 166. FIGURE 7 is an expanded schematic diagram of write monitoring circuitry 90 shown in FIGURE 1. Input 88 represents the non-inverting input 174 of an operational amplifier 176. Input 92 represents the inverting input 178 of operational amplifier 176. Output 180 of operational amplifier 176 is coupled by a conductor 182 to the drain 184 of a transistor 186, the drain 188 of a transistor 190 and the gate 192 of a transistor 194. Transistor 186 provides a reset means for write monitoring circuitry 90. Gate 196 of transistor 186 is tied to a reset signal RESET. The source 198 of transistor 186 is grounded. Transistors 190 and 194 form a latch. The source 200 of transistor 190 is grounded while the gate 202 of transistor 190 is coupled by a conductor 203 to the drain 204 of transistor 194. Source 206 of transistor 194 is grounded. Drain 188 of transistor 190 is tied to V dd through a pull-up resistor 208 while the drain 204 of transistor 194 is tied to V dd through a pull-up resistor 210. A conductor 212 couples the output 180 of operational amplifier 176 to gate 214 of an output transistor 216. The source 218 of transistor 216 is grounded while the drain 220 provides the output 96 for write monitoring circuitry 90. The operation of the present invention can now be described in detail using FIGURES 1, 2 and 5 for reference. For convenience, the setting of the threshold voltage will first be described in the case when EEPROM cell 12 is already programmed to a logic "0", i.e., electrons are already residing on floating gate 24. The floating gate potential V F for a single conventional nonvolatile memory cell having a floating gate can be expressed as: Equation 1: V F = C pp V q + C t (V d -  n ) + C d (V d - n' ) + C c  p + C s V s + Q f Σ C i where: Σ C i = C pp + C t + C d + C c + C sub + C s C pp = capacitance between floating gate 24 and control gate 26; C t = capacitance between floating gate 24 and tunnel 22; C d = capacitance between floating gate 24 and drain 16; C sub = capacitance between floating gate 24 and substrate 18; C c = capacitance between floating gate 24 and channel 20; C s = capacitance between floating gate 24 and source 14;  p = surface potential of channel 20;  n = surface potential of tunnel 22;  n' = surface potential of drain 16; Q F = charge on the floating gate 24; V g = voltage applied to control gate 26; V d = voltage applied to drain 16; and V s = voltage applied to source 14. the surface potential of channel 20 will be determined by the floating gate potential V F . During a standard erase operation, control gate 26 of EEPROM cell 12 would be grounded, source 14 would be allowed to float, and drain 16 would be pulsed with an erase signal of about 16 volts for about 1-100 milliseconds by drain voltage control circuitry 44. At the beginning, the surface under the floating gate 24 would be in accumulation, such that the surface potential  p of channel 20 and the voltage on source 14, V s , will be approximately zero volts. As electrons are pulled out of floating gate 24, via Fowler-Nordheim tunneling through tunneling window 22, the floating gate potential V F will go up. The surface of channel region 20 will gradually come out of accumulation and go into depletion. Once the floating gate potential V F is high enough to deplete the silicon, the surface potential  p will start to rise as will the potential of source 14 which has been allowed to float. When the increase in potential of source 14 is detected in relation to the reference voltage V ref by monitoring circuitry 52, the voltage applied to drain 16 may be shunted by erase monitoring circuitry 52 to ground, preventing further erase. At this point, the voltage of floating gate 24 is approximately: V F ≈ C t (V d -  n ) + C d (V d -  n' ) + Q F C pp + C F + C d + C sub + C s + C c ≈ 0 therefore, the charge on floating gate 24 is approximately: Q F = - C t (V d -  n ) - C d (V d -n') The threshold voltage V t will be: V t = V tn - Q F C pp where V tn is the threshold voltage of the cell in a neutral (completely uncharged) state. To erase the EEPROM cell to a different threshold voltage V' t where V' t equals V t +ΔV t, a gate bias voltage V g can be applied during erase using gate voltage control circuitry 62, where V g = ΔV t . When the potential on source 14 starts to rise, the floating gate potential V' F will be: V' F = C pp V q + C t (V d -  n ) + C d (V d - n' ) + Q F' C pp + C t + C d + C sub + C s + C c Therefore, the charge on floating gate 24 will now become: Q F' = - C t (V d -  n ) + C d (V d -  n' ) - C pp V g or: Q F' = Q F = C pp V g The threshold voltage V t' will become: V t' = V tn - Q F' C pp = V tn - Q F C pp + V g or: V t' = V t + V g = V t + ΔV t Thus, equation 10 shows that an EEPROM cell can be erased to any threshold voltage V t , by applying an appropriate gate bias approximating the desired increase in threshold voltage ΔV t to control gate 26 during the erase operation, using gate voltage control circuitry 62. When the potential source 14 beings to rise, monitoring circuitry 52 halts the application of voltage to drain 16, stopping erase with floating gate 24 partially charged, thereby leaving the threshold voltage at V t '. The main disadvantages of setting the threshold voltage during the erase cycle are slow speed and increased costs. When a positive gate bias is used the erase operation is slowed considerably. This speed disadvantage can be overcome by using a negative gate bias, however, generating the required negative voltages on the chip is significantly expensive. The disadvantages of setting the threshold voltage of EEPROM cell 12 during the erase operation can be overcome by setting the threshold voltage during the write (programming) cycle. In this instance, transistor 30 operates cooperatively with EEPROM cell 12. In this case, during the write operation, while the floating gate 24 is being charged with electrons, the potential on floating gate 24 will be: V F = C pp V q + C NT (V TANK ) + Q F Σ C i + C NT where, C NT = capacitance between floating gate 24 and tank 32; V TANK = potential of tank 32. When the potential of source 34 goes down as the floating gate 24 becomes charged: V F ≈ V TANK ≈ C pp V q + C NT (V TANK ) Q f Σ C i + C NT therefore, the charge on the floating gate 24 becomes: Q F = V TANK ΣC i - V g C pp The threshold voltage can now be represented as: V t = V tN - Q f C pp = V tN - V TANK ΣC i C pp + V g where V tN is the threshold voltage of p-channel 38. If the coupling of control gate 26 and floating gate 24 is improved by increasing the coupling area over oxide layer 28, then C pp ≈ ΣC i . The threshold voltage becomes: V t ≈ C tN - V TANK + V g If the voltage on tank 32 approximates the difference between the control gate voltage V g and the desired change in threshold voltage ΔV t , i.e. V TANK ≈ V g -ΔV t , then: V t ≈ V tN + ΔV t Thus, by properly biasing the n-tank 32 of transistor 30 with respect to control gate 26, the threshold voltage of EEPROM cell 12 can be set as follows during the write cycle. Drain 16 of EEPROM cell 12 is grounded, while the source 14 is allowed to float. A high voltage of approximately 17 volts is applied to control gate 26, creating a high voltage differential between control gate 26 and drain 16. The voltage differential allows electrons to tunnel from drain 16 to floating gate 24 through tunneling window 22. As the electrons begin to reside on floating gate 24, the potential of floating gate 24 begins to go down. Tank 32 of field transistor 30 has been biased to a voltage equal to the control gate voltage less the desired change in threshold voltage (V g - ΔV t ) through the application of gate voltage V g by gate voltage control circuitry 62 and a threshold variation voltage ΔV t by threshold variation circuitry 76 to subtraction circuit 68. Drain 34 of field effect transistor 30 has been grounded while source 36 has been allowed to float. Since transistor 30 is a p-channel device, while the potential of floating gate 24 remains sufficiently positive, i.e., the potential of the floating gate remains above the threshold voltage of the field effect transistor 30 as biased by the application of the bias voltage to tank 32, there is no conductance between drain 34 and source 36. When, however, a sufficient number of electrons have tunneled on to floating gate 24 and the potential of floating gate 24 has gone sufficiently negative, field effect transistor 30 turns on and a conductance path is created between drain 34 and source 36. Source 36 is thus clamped to the voltage on drain 34, which in this case is ground. When monitor circuit 90 detects the decrease in the potential on source 36 in relation to the voltage V g - V t applied to tank 32, it shunts output 60 of gate voltage control circuitry 62 to ground, such that no voltage is applied to control gate 26. The charging of floating gate 24 is stopped at that point, effectively setting the threshold voltage of EEPROM cell 12 to a voltage proportionate to the amount of charge already allowed to tunnel to floating gate 24. The threshold voltage of EEPROM cell 12 can thus be set to any value within the range defined by the threshold voltage when floating gate 24 is not charged, and a voltage proportionate to the maximum charge which can be accumulated on floating gate 24. The disadvantages of setting the threshold voltage during the erase cycle are thereby eliminated. Further, in the present invention, the threshold voltage may optionally be applied during the erase or the write cycle, such that the user may start the operation of setting the threshold with either a charged or uncharged floating gate. Although the present invention has been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the scope of the invention as defined by the appended claims.

Claims: An electrically-erasable, electrically-programmable read only memory (EEPROM) cell (10) formed in a semiconductor layer of a first conductivity type and including circuitry (76) for controlling the threshold voltage of the memory cell (10), the memory cell (10) comprising; a first transistor (12) formed in the semiconductor layer and having a source region (14) and a drain region (16) of a second conductivity type, said source and drain regions (14, 16) being separated by a channel region (20); a second transistor (30) formed in the semiconductor layer and having a source region (34) and a drain region (36) of the first conductivity type, said source and drain regions (34, 36) being separated by a channel region (38), the drain region (36) of the second transistor (30) being connected to a ground terminal; a floating gate (24) having a first portion insulatively adjacent the channel region (20) of the first transistor (12) and a second portion insulatively adjacent the channel region (38) of the second transistor (30); a control gate (26) insulatively disposed adjacent the floating gate (24); and characterized in that the memory cell (10) further comprises; a tank region (32) of the second conductivity type formed in the semiconductor layer such that it is spaced from the first transistor (12), the second transistor (30) being located in the tank region (32); the threshold control circuitry (76) coupled to the tank region (32) and operable to bias the tank region (32) to a predetermined threshold potential relative to the control gate (26) such that the cell (10) is self-controlling, monitoring circuitry (58) responsive to a change in potential of the source region (34) of the second transistor (30) to control the application of potential on the control gate (26) such that the charge on the floating gate (24) stops increasing when a selected threshold potential is obtained. The memory cell according to claim 1, wherein the memory cell (10) includes circuitry operable during an erase cycle to control the discharge of the floating gate comprising: a drain voltage control circuit (44) operable to apply a potential to the drain region (16) of the first transistor (12); an erase monitor circuit (52) for monitoring the potential of the source region (14) of the first transistor (12), the first monitoring circuit (52) being responsive to a change in the potential of the source region (14) of the first transistor to halt the application of potential by drain voltage control circuitry (42) to the drain region (16) of the first transistor (12). The memory cell according to claim 2, further comprising; gate voltage control circuitry (62) operable to apply a potential to the control gate (26); and wherein the monitoring circuit (58) is coupled to the gate voltage control circuitry (62) for monitoring the potential of the source region (34) of the second transistor (30) relative to the tank region (32), the monitoring circuit (58) being responsive to a change in potential of the source region (34) relative to the control gate (26) to halt the application of potential to the control gate (26) by the gate voltage control circuitry (62). The memory cell according to claims 1-3, wherein the drain region (16) and the source region (14) of the first transistor (12) are formed from an n-type material, and the drain region (36) and source region (34) of the second transistor (30) are formed from a p-type material. The memory cell according to any preceding claim further comprising; a thick oxide region formed such that it separates the first transistor (12) and the second transistor (30). The memory cell according to any preceding claim further comprising; a thin oxide tunneling window (22) formed overlying the channel region (20) of the first transistor (12) and adjacent the drain region (16) thereof. The memory cell according to claim 6, wherein the window (22) is a Fowler-Nordheim tunneling window. The memory cell according to claim 7, wherein the control gate (26) is operable to charge and discharge the floating gate (24) by Fowler-Nordheim tunneling through said tunneling window (22) upon application of a predetermined potential to the control gate (26) and to the drain region (16) of the first transistor (12). The memory cell according to any preceding claim, wherein the floating gate (24) has a third portion having a relatively large surface area which capacitively couples with a co-extensive portion of the control gate (26). The memory cell according to claims 5 to 9, wherein the control gate (26) and the floating gate (24) are coupled in a region substantially overlying the thick oxide region. The memory cell according to any preceding claim, wherein said monitoring circuit (58) comprises a differential amplifier circuit (90) which is operable to measure the potential difference between the tank region (32) and the source region (34) of the second transistor (30). The memory cell according to any preceding claim, wherein the threshold control circuitry (76) is operable to bias the tank region (32) to a potential equal to the control gate (26) potential less a pre-determined change in the threshold potential of the memory cell (10). The memory cell according to any preceding claim further comprising; means coupled to the floating gate (24) for incrementally increasing charge stored on the floating gate (24) until a first predetermined threshold potential is achieved. The memory cell according to any preceding claim further comprising; means coupled to the floating gate (24) for incrementally decreasing charge stored on the floating gate (24) until a second predetermined threshold potential is achieved. The memory cell according to any preceding claim, wherein the monitoring circuitry (58) is adapted to differentially detect the difference between said tank region (32) and the source region (34) of the second transistor (30). A method for setting threshold voltage of an electrically-erasable, electrically-programmable read only memory cell (10) including a first transistor (12) having a source (14) and a drain (16) separated by an n-channel (20), a floating gate (24) insulatively overlying the channel (20), a tunneling window (22) disposed in the channel (20) adjacent the drain (16), and a control gate (26) insulatively overlying the floating gate (24), and a second transistor (30) having a source (34) and drain (36) separated by a p-channel (38), the n-channel (20) being controlled by the floating gate (24) of the first transistor (12), comprising the steps of: applying a drain write voltage to the drain (16) of the first transistor (12); applying a control gate write voltage to the control gate (26) of the first transistor (12); responsive to said steps applying write voltages, causing electrons to flow from the drain (16) of the first transistor (12) to the floating gate (24) via Fowler-Nordheim tunneling; grounding the drain (36) of the second transistor (30); allowing the source (34) of the second transistor (30) to float; biasing the channel (38) of the second transistor (30) to preselect the threshold voltage; monitoring the potential of the source (34) of the second transistor (30); and in response to said step of monitoring, halting the application of the write voltage to the control gate (26) of the first transistor (12) when the voltage on the source (34) of the second transistor (12) decreases. The method of claim 16, wherein said step of biasing the channel (38) of the second transistor (30) comprises the application of a positive voltage to increase the threshold voltage of the cell. The method of claim 17, wherein the positive voltage is applied to a tank (32) formed in a substrate and in which the second transistor (30) is formed. The method of claim 18, wherein the voltage applied to the tank (32) is equal to the gate write voltage less the desired change in threshold voltage of the cell (10).

Inventors: KAYA CETIN, KAYA, CETIN
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1991
Main classification: G11C16
IPC codes: H01L29, G11C16, G11C17, G11C27, H01L27, H01L21