Process for fabricating a thin film transistor

Abstract: A TFTs fabricating process practicable at a low temperature, the steps of forming a multi-layer body on a substrate (1), the multi-layer body including a semiconductor layer (2) a gate insulating layer (3) and a lower thin layer (2a), patterning the multilayer body into islands, thereby removing the other portions of the multi-layer body, forming an insulating layer (5) on the sides of the island-patterned multi-layered portion by etching at a selective ratio between the constituents of the insulating layer and the lower thin layer, forming an upper thin layer (4b), and etching the upper and lower thin layers into upper and lower gate electrodes by use of one resist pattern.

Description: The present invention relates to a process for fabricating thin film transistors, and is applicable particularly to a process for fabricating thin film transistors (hereinafter called "TFT") at a low temperature, the TFTs being adapted for use in display devices and image sensors. TFTs used for driving liquid crystal display devices and image sensors are fabricated in the same manner as the IC fabricating process. The ICs must be processed at about 1,000°C so as to effect crystallization, formation of insulating layers and activation of impurities, which requires that the substrate on which IDs are formed must be selected from materials which can withstand high temperatures. The commonest material is quartz. Such a requirement makes it difficult to use a large substrate on which ICs are formed. In order to solve the problems arising at high temperatures, amorphous or polycrystalline substance is used as a starting material which is crystallized by the solid phase growth or by laser annealing. A TFT is a MOS type transistor. The performances of transistors depend upon the interface condition of the gate insulating layer and the semiconductor layer. When transistors are processed at low temperatures, the gate insulating layers are also processed at equally low temperatures. Thin semiconductor layers are formed in a desired shape on a substrate, and subjected to surface treatment with the use of hydrofluoric acid, etc. Then, gate insulating layers are formed by sputtering or by a CVD method. These methods are not appropriate for reducing the interfacial level density for an unknown reason. The reason has been investigated. The investigation teaches that thin semiconductor layers should be followed by the formation of gate insulating layers without pause before the thin semiconductor layers are exposed to atmosphere. In order to improve the performance of TFTs formed at low temperatures, it is necessary to reduce the interfacial level density between the semiconductor and gate insulating layers. In order to achieve this, the formation of thin semiconductor layers must be followed by the overlaying of gate insulating layers. To make the overlying layers as a TFT, the layer to be overlaid is formed in a desired island-shaped pattern in which the sides of the semiconductor layer are exposed outside. If the gate electrode is formed under this condition, the exposed sides of the semiconductor layer and the gate electrode are likely to come into contact with each other, thereby increasing the current leak. In order to prevent this current leak, it is required to cover the exposed sides of the semiconductor layer with an insulating layer 8 as shown in Figure 9, prior to the formation of the gate electrode. In Figure 9, an insulating substrate 1 on which a semiconductor layer 2, a gate insulating layer 3, and a gate electrode 4 overlap one above another. If the insulating layer 8 is made of SiO₂, which is a material in common use for making gate insulating layers, the SiO₂ of the gate insulating layer 3 is simultaneously etched. This simultaneous etching leaves the insulating layer 8 from shaping, and even if SiO₂ and SiO₂ have a large etching selective ratio, the simultaneous fabrication by etching is difficult. A PSG is known in the art which is fabricated by doping the SiO₂ of an insulating layer with phosphorus. The larger the amount of the added phosphorus is, the larger the selective ratio becomes, but the phosphorus diffuses from the sides of the semiconductor layer 2, thereby changing the characteristics of the thin film transistor (TFT). There is known already from EP-A- 0 165 863 a process for fabricating a thin film field effect transistor, wherein a multi-layer body is formed on a substrate, the multi-layer including a semi-conductor layer, a gate insulating layer and a lower thin layer, the multi-layer body being patterned into islands to thereby remove the other portions of the multi-layer body. In accordance with the present invention, there is provided a process for fabricating a thin film transistor, according to claim 1. In a preferred embodiment, the substrate is prepared so as to have an insulating film on a surface and the multi-layer body is formed on the insulating film of the substrate. The formation of the multi-layer body is preferably conducted in a vacuum or inert-gas filled space, thereby preventing the multi-layer body from being exposed to the atmosphere. Advantageously the insulating film and the insulating layer of the substrate are made of different materials. In one embodiment, the insulating layer on both sides of the island is formed by overlaying it on the whole surface of the substrate, and removing other than a portion on both sides of the island by anisotropic etching. Preferably, the anisotropic etching is a plasma etching, and wherein the spectroscopic characteristics of the plasma applied to the insulating layer is detected throughout the etching process so as to detect a change in the spectroscopic characteristics occurring when the first insulating layer is exposed, thereby controlling the period of time over which the plasma etching is applied to the insulting layer. Advantageously the insulating layer on the sides of the island is made of Si₃N₄. Preferably, the multi-layered portion is etched with a reactive ion-etchant so as to make the sides of the island perpendicular to the substrate. The gate electrode is preferably made of metal or polycrystalline silicon. Thus, the invention described herein makes possible the objective of providing a TFT fabricating process which can form TFTs over a relatively wide range of a substrate easily with a high yield of manufacture. This invention is further described, by way of example, with reference to the accompanying drawings, in which: Figure 1 is a plan view showing a thin film transistor to be fabricated by the present invention; Figures 2 to 8 are diagrammatic sectional views, taken on lines A-A′ and B-B′ of Fig.1, showing the steps of fabricating a thin film transistor; Figure 9 is a sectional view showing a known thin film transistor; Figure 10 is a plan view showing a thin film transistor according to a second example of the present invention; Figures 11 to 17 are diagrammatic sectional views, taken on lines A-A′ and B-B′ of Fig.10, showing the steps of performing the second example; and Figure 18 is a graph showing the intensities of an emitting light varying with time. Referring to Figures 1 to 8, a first example of the present invention will be described: As shown in Figures 2 (a) and 2 (b), a glass substrate 1, after it is cleansed, is placed on a plasma CVD apparatus. The substrate 1 is heated to a temperature ranging from 400°C to 600°C, and a SiH₄ gas is decomposed by heat and plasma, so as to form an amorphous Si layer to a thickness of about 1000 angstroms (10Å=1nm) on the substrate 1. The deposited amorphous Si layer is annealed in a vacuum or in an inert gas atmosphere at 600°C for about 50 hours so as to form a polycrystalline silicon layer 2. Then, a SiO₂ layer is formed to a thickness of about 1000 angstroms by sputtering so as to make it into a gate insulating layer 3. In the course of conducting the steps described above, the glass substrate 1 is transported from the plasma CVD apparatus to the sputtering furnace by way of the annealing furnace in a confined chamber kept in a vacuum or filled with an inert gas, thereby ensuring that the substrate is kept free from exposure to the atmosphere. Then, a polycrystalline silicon layer is formed to a thickness of about 1000 angstroms by a vacuum CVD apparatus, so as to make a lower gate electrode 4a. The resulting three-layered structure is shown in Figures 2 (a) and 2 (b). The next step is shown in Figures 3 (a) and 3 (b), by which the three-layered layer is etched into an island-shaped pattern by use of a resist pattern produced in the transistor portion. The etching is a reactive ion-etching, which is called an anisotropic etching in which the sides of the island-patterned multi-layer portion are vertical to the surface of the substrate surface. The etchant can be a gaseous mixture of SF₆ and CCl₄ for a polycrystalline silicon layer, and a CHF₃ gas for a SiO₂ layer. The steps advance to that shown in Figures 4 (a) and 4 (b), in which the whole surface of the substrate 1 is covered with a SiO₂ layer 5 formed to a thickness of about 5000 angstroms by sputtering or a normal-pressure CVD method. Then, an anisotropic etching is carried out with a reactive ion etchant so that the SiO₂ remains only on the sides of the island-patterned multi-layer portion as shown in Figures 5 (a) and 5 (b). Then, as shown in Figure 6 (a), a polycrystalline silicon layer is deposited by a vacuum CVD method to a thickness of about 2000 angstroms as an upper gate electrode 4b, and then the upper gate electrode 4b and the lower gate electrode 4a are etched by a reactive ion etching step through a resist pattern formed as a gate electrode. The finished gate electrode 4 is shown in Figure 1. Then, any suitable impurities are ion implanted, and an activating annealling is carried out. In this way the upper gate electrode 4a, the lower gate electrode 4b and the polycrystalline silicon layer, which is later made into a source and a drain at opposite sides of the gate electrode, are made so as to have a low electrical resistance. The next step is the stage shown in Figures 7 (a) and 7 (b) in which an insulating layer 6 is formed. More specifically, a SiO₂ or a PSG layer having a phosphorus doping is formed on the whole surface of the substrate 1 by a normal pressure CVD method, and contact holes (not numbered) are formed in the layer 6 at the junction of electrodes. Other contact holes are formed in the layer 6 on a gate electrode 4 connected to an Al wiring, which is described in the next paragraph. An Al layer 7 having a thickness of about 5000 angstroms is first formed by sputtering, and then it is made into Al layer wirings 7a and 7b of a predetermined shape by photo-etching as shown in Figures 8 (a) and 8 (b). In this way, the final TFT having a desired wiring as shown in Figure 1 is obtained. As is evident from the foregoing description, the insulating layer on the sides of the island, that is, the island-patterned multi-layer portion, and the gate electrodes are made of different materials, thereby avoiding the difficulty resulting from the use of the same kind of material which is adopted under the known fabricating process. The insulating layer on the sides of the island-patterned multi-layer portion can be made of Si₃N₄ or other material if they do not unfavorably affect the semiconductor. The gate electrode can be made of metal such as Ti or W, instead of polycrystalline silicon, or made of a combination of them with silicide. Referring to Figures 10 to 18, a second example will be described: A SiN film 22 is formed on the substrate 1 to a thickness of about 3000 angstroms by a plasma CVD apparatus after the substrate 1 is cleansed. Then an amorphous Si layer is formed on the first SiN layer at a temperature of 400°C to 600°C by using a SiH₄ diluted with H₂ and decomposed by heat and plasma. This layer is about 1000 angstroms thick. The Si layer is annealed at 600°C at a vacuum or in an inert gas atmosphere for about 50 hours so as to make it into polycrystalline Si layer 23. A SiO₂ is then formed by sputtering to a thickness of about 1000 angstroms from which a gate insulating layer is formed at a later stage. These processes are conducted without being exposed to atmosphere as described above. Figure 11 shows the formation of a polycrystalline silicon layer having a thickness of about 1000 angstroms from which a first gate electrode 25a is formed. In this way three layers 23, 24 and 25a are obtained, all of which are patterned by use of the same resist pattern into an island-shaped portion, hereinafter referred to the island as shown in Figure 12. A reactive ion etchant is used and an anisotropic etching is adopted so that after etching each vertical section is perpendicular to the substrate 1. As an etching gas, a gaseous mixture of SF₆ and CCl₄ is used for the polycrystalline silicon layer and a CHF₃ gas is used for the SiO₂. Then, as shown in Figure 13, the whole surface of the substrate 1 is covered with a SiO₂ 26 having a thickness of about 5000 angstroms by a sputtering device or a normal pressure CVD device. Afterward, a reactive ion etchant is used to perform an anisotropic etching so as to remove the SiO₂ 26 until the only sides of the island remain as shown in Figure 14. Figure 18 shows the variations with time in the emitting light intensity from the initiation of the etching, of the spectrums of 388 nm of CN resulting from the etching gas CHF₃ and the SiN layer 22 selected from the plasma emitting spectrums. When a critical level is ascertained where the emitting light intensity does not increase any longer, the etching process is stopped. This ensures that a constant size of the SiO₂ layer is formed on the sides of the island. The next step is to form a polycrystalline silicon layer having a thickness of about 2000 angstroms by a reduced pressure CVD device from which a second gate electrode 25b is made. As shown in Figure 15, a resist pattern is formed so as to shape the gate electrode as desired. With the use of the pattern, the first gate electrode 25a and the second gate electrode 25b are etched with a reactive ion etchant at the same time. Then, ion is injected into the gate electrodes 25a and 25b so as to effect an activated annealing, so that the polycrystalline silicon layer of the two gate electrodes and the polycrystalline silicon layer from which a drain is later formed are treated so as to have low resistance. Then, a PSG layer is formed by doping the substrate 1 with SiO₂ or phosphorus, and contact holes are made at desired spots so as to form an inter-layer insulating layer 7. The gate insulating layer is also provided with holes so that the source and drain and an Al electrode referred to below may be electrically connected. The contact hole is made in a layer 27 on the gate electrode 25 connected to an Al wiring referred to below (not shown). The next step is to form an Al layer to a thickness of about 5000 angstroms by sputtering to a desired shape for a source electrode 28a and a drain electrode 28b, which, as a thin film transistor and a circumferential wirings, is shown in Figure 17. The final TFT is shown in Figure 10. The material for the first insulating layer on the substrate 1 and the material for the second insulating layer on the sides of the island are replaceable, and any other materials can be used for the insulating layers on condition that they have different spectroscopic characteristics. As described with respect to the first example, the gate electrode can be made of metals such as Ti or W instead of the polycrystalline silicon.

Claims: A process for fabricating a thin film transistor, wherein a multi-layer body is formed on a substrate (1), the multi-layer body including a semiconductor layer (2,23), a gate insulating layer (3,24) and a first thin layer (4a,25a), and the multi-layer body is patterned into islands, thereby removing the other portions of the multi-layer body, characterised in that an insulating layer (5,26) is formed on the obtained structure, and all but a portion of said insulating layer (5,26) on both sides of the island-patterned multi-layered portion is removed by selectively etching the insulating layer (5,26) and the first thin layer (4a,25a), and in that a second thin layer (4b,25b) is formed on the resulting structure, the second and first thin layers (4a,4b,25a,25b) are subsequently etched into a gate electrode including upper and lower gate electrodes formed from said second and said first thin layers, respectively by use of the same resist pattern, and a source region and a drain region are formed at respective sides across the gate electrode in the semiconductor layer (2,23). A process as claimed in claim 1, wherein the substrate (1) is prepared so as to have an insulating film (22) on a surface, and the multi-layer body is formed on the insulating film (22) of the substrate (1). A process as claimed in claim 1 or 2, wherein the formation of the multi-layer body is conducted in a vacuum or inert-gas filled space, thereby preventing the multi-layer body from being exposed to the atmosphere. A process as claimed in claim 2 or 3, wherein the insulating film (22) and the insulating layer (5,26,26′) of the substrate (1), are made of different materials. A process as claimed in any of claims 1 to 4, wherein the insulating layer (5,26′) on both sides of the island is formed by overlaying it on the whole surface of the substrate (1), and removing other than a portion on both sides of the island by anisotropic etching. A process as claimed in claim 5, wherein the anisotropic etching is a plasma etching, and wherein the spectroscopic characteristics of the plasma applied to the insulating layer is detected throughout the etching process so as to detect a change in the spectroscopic characteristics occurring when the first insulating layer is exposed, thereby controlling the period of time over which the plasma etching is applied to the second insulating layer. A process as claimed in any preceding claim, wherein the insulating layer on the sides of the island is made of Si₃N₄. A process as claimed in any preceding claim, wherein the multi-layered portion is etched with a reactive ion-etchant so as to make the sides of the island perpendicular to the substrate. A process as claimed in any preceding claim, wherein the gate electrode layer (4a,4b,25a,25b) is made of metal. A process as claimed in any of claims 1 to 9, wherein the gate electrode layer (4a,4b,25a,25b) is made of poly-crystalline silicon.

Inventors: MORITA TATSUO, TARUI KEIJI, TSUCHIMOTO SHUHEI, MORITA, TATSUO, TARUI, KEIJI, TSUCHIMOTO, SHUHEI
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1991
Main classification: H01L21
IPC codes: H01L21