Drive circuit for a display apparatus

Abstract: A drive circuit for a display apparatus having parallel signal electrodes has at least one voltage selecting circuit, a plurality of signal voltage circuits, and one selection signal circuit. The voltage selecting circuit selects one of voltages having different levels in accordance with an input digital video signal. The signal voltage circuits are respectively provided for the signal electrodes, and include one signal line which is disposed between the voltage circuit and the respective signal electrode. The signal line is provided with an input switch, a capacitor and an output switch. The selection signal circuit generates a signal for controlling the input switches of the signal voltage circuits to be sequentially closed.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention: This invention relates to a drive circuit for a display apparatus, and more particularly to a drive circuit for a display apparatus which is capable of gray-scale display by means of amplitude modulation. In this specification, a matrix type liquid crystal display apparatus will be described as a typical example of a display apparatus, but this invention can also be applied to drive circuits for other types of display apparatus such as electroluminescent (EL) display apparatus and plasma display apparatus. 2. Description of the Prior Art: When driving a liquid crystal display (LCD) apparatus, since the speed of response of a liquid crystal is very slow as compared with a luminescent material used in a cathode ray tube (CRT) display apparatus, a special drive circuit is used. That is, in the drive circuit for the LCD apparatus, video signals which are sequentially sent are not immediately supplied to respective pixels, but the video signals are sampled for each of the respective pixels in one horizontal period and held for the horizontal period. The held video signals are output at the same time at the beginning of the next horizontal period, or at an appropriate point of time in the next horizontal period. After the output of video signal voltages to the respective pixels are begun, the signal voltages are held for a period of time sufficiently over the speed of response of the liquid crystal. In order to hold the signal voltages, a prior art drive circuit utilizes capacitors, see US-A-4,799,057. Figure 11 shows a signal voltage output circuit (a source driver) for supplying drive voltages to N pixels on one scanning line selected by a scanning signal. A portion for the nth pixel of the signal voltage output circuit is shown in Figure 12. The portion includes an analog switch SW₁, a sampling capacitor C SMP , an analog switch SW₂, a holding capacitor C H , and an output buffer amplifier A. The operation of the signal voltage output in the prior art will be described with reference to the circuit diagrams of Figures 11 and 12, and also to the signal timing chart of Figure 13. Analog video signals v s to be input to the analog switches SW₁ are sequentially sampled in accordance with sampling clock signals T SMP1 - T SMPN which correspond to the respective N pixels on one scanning line selected by each horizontal synchronizing signal H syn . By this sampling, the sequential instantaneous voltages V SMP1 - V SMPN of the video signals v s are applied to the corresponding sampling capacitors C SMP . The nth sampling capacitor C SMP is charged up to the value of the video signal voltage V SMPn corresponding to the nth pixel, and holds this value. The signal voltages V SMP1 - V SMPN which are sequentially sampled and held in one horizontal period are transferred from the sampling capacitors C SMP to the holding capacitors C H , in response to an output pulse OE which is supplied to all of the analog switches SW₂ at the same time. Then the signal voltages V SMP1 - V SMPN are output to source lines O₁ - O N connected to the respective pixels through the buffer amplifiers A. To the drive circuit described above, analog video signals are supplied. Such a drive circuit presents the following problems (A1) to (A4) when attempts are made to increase the size or improve the resolution of a liquid crystal panel. (A1) When the charges in the sampling capacitors C SMP are transferred to the holding capacitors C H , the relationship betweeen the voltage V H of the holding capacitor C H and the sampled voltage V SMP is represented by the following expression: V H = 1 1 + C H C SMP · V SMP Accordingly, in order that the voltage V H held by the holding capacitor C H may substantially equal the sampled voltage V SMP , a condition of C SMP >> C H is required to be satisfied. That is, it is necessary to use the sampling capacitor C SMP of a relatively large capacitance. However, if the capacitance of the sampling capacitor C SMP is too large, it is necessary to make the time for charging (i.e. a sampling period) longer. On the contrary, as the size of the LCD apparatus is made larger or the resolution is improved, the number of pixels corresponding to one horizontal period increases, thereby necessitating a sampling period to be shortened in reverse proportion. It can be seen that there is a limit to the increase in size or the improvement in resolution of the LCD apparatus. (A2) Analog video signals are supplied to the source driver via bus lines. As the size and resolution of a display apparatus are increased, the frequency band of the video signal becomes wider and the distribution capacity of the bus lines increases . This results in the necessity of a wideband amplifier in the circuit supplying video signals, thereby increasing the cost of production. (A3) In a color display apparatus in which RGB video signals are used, bus lines for supplying multiple analog video signals are arranged. As the size and resolution of a display panel of such an apparatus are increased, the above-mentioned wideband amplifier is required to have an extremely high signal quality so that there is no phase differences between the multiple video signals and no dispersion in the amplitude characteristics and frequency characteristics. (A4) In the drive circuit for a matrix type display apparatus, unlike the display in a CRT, analog video signals are sampled in accordance with a clock signal and displayed in pixels arranged in a matrix. At this time, since delays of signals in the drive circuit including delays in the bus lines is unavoidable, it is extremely difficult to accurately establish the sampling position for the analog video signals. Particularly, when displaying a computer graphic image in which the relationship between video signals and pixel addresses should be precisely defined, shift in the image display position, bleeding of the image, etc., due to signal delays in the drive system and deterioration of the frequency characteristics cause significant problems. These problems which occur when using analog video signals are solved by using digital data as video signals. When the video signals are supplied in the form of digital data, a drive circuit shown in Figures 14 and 15 is used. For the sake of simplicity, the video signal data is composed of 2 bits (D₀, D₁). That is, video signal data have four values 0 - 3, and a signal voltage applied to each pixel is any one of four levels V₀ - V₃. Figure 14 is a circuit diagram showing a digital source driver circuit corresponding to the analog source driver circuit shown in Figure 11. The circuit diagram of Figure 14 shows the entire source driver for supplying driving voltages to N pixels. Figure 15 shows a portion for the nth pixel in the circuit. The portion of the circuit compriese a D-type flip-flop (sampling flip-flop) M SMP at a first stage and a flip-flop (holding flip-flop) M H at a second stage which are provided for the respective bits (D₀, D₁) of the video signal data, a decoder DEC, and analog switches ASW₀ to ASW₃ each of which is provided between corresponding one of four external voltage sources V₀ - V₃ and a source line O n . For the sampling of digital video signal data, various circuits may be used other than the D-type flip-flop. The digital source driver operates as follows. The video signal data (D₀, D₁) are sampled at the rising of a sampling pulse T SMPn corresponding to the nth pixel, by the sampling flip-flop M SMP . At the time when the sampling for one horizontal period is completed, an output pulse OE is fed to the holding flip-flops M H . All the video signal data (D₀, D₁) held in the holding flip-flops M H are simultaneously output to the respective decoders DEC. Each of the decoders DEC decodes the 2-bit video signal data (D₀, D₁). In accordance with the values (0 to 3), one of the analog switches ASW₀ - ASW₃ is conductive, and the corresponding one of the four external voltages V₀ - V₃ is output to the source line O n . The source driver in which digital video signals are used for sampling can solve the problems (A1) to (A4) which arise when analog video signals are used for sampling. However, this source driver still has the following problems (D1) and (D2) to be solved. (D1) With the increase in number of bits of digital video signal data, the size of each of memory cells, decoders, etc., constituting a drive circuit is drastically enlarged. Therefore, the size of a chip and the production coat are greatly increased. (D2) When voltage sources supplied externally (V₀ - V₃ in Figures 14 and 15) are selected by using analog switches, the selected voltage source is directly connected to a source line of the liquid crystal panel and drives the source line. Accordingly, the circuit is required to have a performance capable of sufficiently driving the heavy load, i.e. the liquid crystal panel. This causes the production cost to increase. SUMMARY OF THE INVENTION This invention, as defined by claim 1, provides a drive circuit for driving a display apparatus having a set of signal electrodes according to an input digital video signal, the circuit including voltage selecting means which is operable to repetitively sample the digital video signal and to output for each digital sample a signal voltage derived from a set of supply voltages in accordance with that digital sample, and a plurality of signal voltage supply means, each provided for supplying a said signal voltage to a respective one of said signal electrodes, and each connected to receive the same said output of said voltage selecting means, said signal voltage supply means each including a switching element controlled so as to pass the signal voltage for the corresponding signal electrode. Claims 2 to 5 are directed to embodiments of the invention. The objective of the invention is to provide a drive circuit for a display apparatus for digital video signal data in order to solve the disadvantages (A1) to (A4) in analogue sampling, and moreover, to eliminate the problems (D1) and (D2). BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a circuit diagram showing a signal voltage supplying circuit for an LCD apparatus in one embodiment of the invention. Figure 2 is a timing chart illustrating the operation of the signal voltage supplying circuit of the embodiment. Figure 3 is a block diagram showing the circuit of Figure 1 in a simplified manner. Figure 4 is a circuit diagram showing a signal voltage supplying circuit with two D/A conversion circuits in a second embodiment of the invention. Figure 5 is a timing chart illustrating the operation of the signal voltage supplying circuit of the second embodiment. Figure 6 is a block diagram showing the circuit of the second embodiment in a simplified manner. Figure 7 is a circuit diagram showing a portion of a D/A conversion circuit for 4-bit digital video signal data in a third embodiment of the invention. Figure 8 is a block diagram showing the circuit of the third embodiment in a simplified manner. Figure 9 is a block diagram of a signal voltage supplying circuit with four D/A conversion circuits for 4-bit data in a fourth embodiment of the invention. Figure 10 is a timing chart illustrating the operation of the signal voltage supplying circuit in the fourth embodiment. Figure 11 is a circuit diagram showing a drive circuit for analog video signals. Figure 12 is a circuit diagram showing a portion for one source line in the circuit of Figure 11. Figure 13 is a timing chart illustrating the operation of the drive circuit of Figure 11. Figure 14 is a circuit diagram showing a drive circuit in which digital sampling circuits are provided for every source line. Figure 15 is a circuit diagram showing a portion for one source line in the circuit of Figure 14. Figure 16 shows in (a) an equivalent circuit diagram when the signal voltage is supplied in the first embodiment of the invention and in (b) an equivalent circuit diagram when the signal voltage is supplied in the circuit of Figure 14. DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 1 shows a signal voltage output circuit (a source driver) for supplying signal voltages to N signal lines (source lines) in a drive circuit for a matrix type LCD apparatus in one embodiment of the invention. In this embodiment, for the sake of simplicity, 2-bit video signal data are used. The signal voltage output circuit of Figure 1 comprises a digital-analog (D/A) conversion circuit DA for selecting one of plural external voltages in accordance with digital video signal data, and signal voltage hold circuits MO i (i is 1 to N) provided for the respective N pixels on one scanning line. In the D/A conversion circuit DA, the 2-bit video signal data of D₀ and D₁ is sampled by a sampling flip-flop M SMP and input into a decoder DEC. The sampling flip-flop M SMP includes two D-type flip-flops corresponding to the respective bits of the input data. In accordance with the video signal data (D₀, D₁) input into the decoder DEC through input terminals A and B thereof, the decoder DEC outputs an ON-control signal to one of analog switches ASW₀ - ASW₃ through a corresponding one of four output terminals Y₀ - Y₃. External voltage sources V₀ - V₃ are connected to terminals of the analog switches ASW₀ - ASW₃, respectively. The other terminals of the analog switches are connected to a first analog switch ASWM in the input portion of each of the signal voltage hold circuits MO i (i is 1 to N). The configuration of the signal voltage hold circuit MO₁ for the first source line be described. The other terminal of the first analog switch ASWM is connected to one terminal of a second analog switch ASWH. A capacitor C M is connected between the other terminal of the first analog switch ASWM and the ground. The other terminal of the second analog switch ASWH is connected to an input terminal of a buffer amplifier A. A capacitor C H is connected between the other terminal of the second analog switch ASWH and the ground. A selection pulse Tm₁ is fed into the control terminal of the first analog switch ASWM. An output pulse OE is fed into the control terminal of the second analog switch ASWH. Each of the signal voltage hold circuits MO i corresponding to the other source lines has the same configuration as that of the signal voltage hold circuit MO₁. The selection pulses TM i are sequentially supplied to the respective signal voltage hold circuits MO i , and the output pulse OE is supplied in common to all the signal voltage hold circuits MO i at the same time. The operation of the signal voltage output circuit shown in Figure 1 will be described with reference to the timing chart of Figure 2. The 2-bit digital video signal data (D₀, D₁) is fed in synchronization with the falling edge of a clock pulse CK. The sampling flip-flop M SMP of the D/A convertion circuit DA shown in Figure 1 latches digital video signal data Data₁, Data₂, Data₃, ... corresponding to the respective pixels at the rising of the clock pulse CK, and outputs them to the decoder DEC as data DAM. The decoder DEC which receives the data Data i makes one of the outputs of the output terminals Y₀ - Y₃ effective, and thereby the corresponding one of analog switches ASW₀ - ASW₃ conductive. For example, if the contents of the data Data₁ is (D₀, D₁) = (1, 1), the analog switch ASW₃ is conductive, and the external voltage V₃ is selected to be output as the output DA out of the D/A conversion circuit DA. The outputs DA out of the D/A conversion circuit DA are supplied to all of the signal voltage hold circuits MO i . However, at the time when the data Data₁ is sampled, only the analog switch ASWM in the signal voltage hold circuit MO₁ for the 1st source line O₁ is conductive in accordance with the selection pulse Tm₁. As a result, the external voltage V₃ is applied only to the capacitor C M in the signal voltage hold circuit MO₁. At the next rising of the clock pulse CK, the next digital data Data₂ is sampled, and the value thereof is decoded by the decoder DEC. An external voltage corresponding to the decoded data is supplied to all of the signal voltage hold circuits MO i as the output DA out of the D/A conversion circuit DA. At this time, only the analog switch ASWM in the signal voltage hold circuit MO₂ for the 2nd source line O₂ is conductive in accordance with the selection pulse Tm₂, so that the output DA out is applied to the capacitor C M in the signal voltage hold circuit MO₂. That is, every time when the digital video signal data Data i in sampled, the external voltage V x is applied only to the capacitor C M in the ith signal voltage hold circuit MO i in accordance with the selection pulse Tm i . After N digital video signal data Data₁ - Data N in one horizontal period are sampled and the capacitor C M in the Nth signal voltage hold circuit MO N is charged, the output pulse OE is fed to the second analog switches ASWH in all of the signal voltage hold circuits MO₁ - MO N . Therefore, the data held in the capacitors C M are transferred to the capacitors C H at the same time, and output to the respective source lines O₁ - O N via the buffer amplifiers A. Thus, the pixels in the LCD apparatus are charged by the respective signal voltages. As described above, in the signal voltage output circuit of the embodiment shown in Figure 1, the external voltage source V x is connected only to the capacitor C M in one signal voltage hold circuit MO i selected by the selection pulse Tm i . The equivalent circuit at this time is shown in (a) of Figure 16, and the loads of the external voltage V x are the on-resistance R ON of the selected one analog switch ASWM and the capacitance of the capacitor C M . However, the on-resistance R ON of the analog switch ASWM is small and the capacitance of the capacitor C M can be made as small as about 7 pF, so that the load of the external voltage source is small. By contrast, for example, in the drive circuit shown in Figure 14, the external voltage V x directly drives the pixels of the liquid crystal panel. Therefore, as shown in (b) of Figure 16, the resistance R CL and the capacitance C CL of the line to the pixel and the pixel itself also are connected to the on-resistance R ON of the analog switch ASWM. Specifically, the values of the resistance R CL and the capacitance C CL have a large value such as approximately 50 kΩ and 200 pF, respectively. Moreover, in the circuit of Figure 14, the selected external voltage source V x is connected to a large number of pixels among the N pixels on one scanning line (the maximum number is N). As described above, since the loads of the external voltage sources V₀ - V₃ are very large in the drive circuit of Figure 14, it is necessary to prepare voltage sources having a large capacity. By contrast, in the embodiment of Figure 1, since the external voltage sources V₀ - V₃ are respectively used only for applying a voltage to one capacitor C M , the power source device is a very simple one, irrespective of the number of source lines. Figure 3 is a block diagram showing in a simplified manner the signal voltage output circuit in the embodiment of Figure 1. The signal voltage output circuit in this embodiment is provided with one D/A conversion circuit DA. The output DA out is connected to all of the N signal voltage hold circuits MO₁ - MO N . Actually, the signal voltage is sent out only to one signal voltage hold circuit MO i selected by a selection pulse Tm i . A second embodiment of the invention is shown in Figure 4. The second embodiment comprises a signal voltage output circuit which is provided with two D/A conversion circuits DA1 and DA2. In the embodiment, one half of the N source lines O₁ - O N (i.e., (N/2) source lines) is assigned to each of the D/A conversion circuits DA1 and DA2. The two D/A conversion circuits DA1 and DA2 receive digital video signal data, and output one of external voltages V₀ - V₃ as outputs DA 1out and DA 2out in accordance with the values of the received data, respectively. The first D/A conversion circuit DA1 is connected to the signal voltage hold circuits MO 2k-1 for odd source lines O 2k-1 such as the 1st and 3rd source lines. The second D/A conversion circuit DA2 is connected to the signal voltage hold circuits MO 2k for even source lines O 2k such as the 2nd and 4th source lines. In this embodiment, the clock pulse CK is not used as it is, but a pulse CKH the frequency of which is divided in half as compared with the clock pulse CK is used as a sampling pulse in a sampling flip-flop M SMP in the first D/A conversion circuit DA1. In a sampling flip-flop M SMP in the second D/A conversion circuit DA2, the inverted pulse of the pulse CKH through an inverter INV is used as a sampling pulse. The operation of the circuit is described with reference to the signal timing chart of Figure 5. The digital video signal data (D₀, D₁) is sampled by the sampling flip-flop M SMP of the first D/A conversion circuit DA1 at every rising of the clock pulse CKH, and sampled by the sampling flip-flop M SMP of the second D/A conversion circuit DA2 at every falling of the clock pulse CKH. Thus, the first sampling flip-flop M SMP1 samples data of odd numbers such as the first data Data₁ and the third data Data₃. The second sampling flip-flop M SMP2 samples data of even numbers such as the second data Data₂ and the fourth data Data₄. The sampling flip-flops sample at every period of the clock pulse CKH, so that the data are held in the sampling flip-flops M SMP1 and M SMP2 for two periods of the clock pulse CK. The outputs DAM₁ and DAM₂ of the sampling flip-flops M SMP1 and M SMP2 are supplied to decoders DEC₁ and DEC₂, respectively. Each of the decoders DEC₁ and DEC₂ selects one of the external voltages V₀ - V₃ in accordance with the same logic as in the decoder DEC shown in Figure 1. The external voltages selected by the decoders DEC₁ and DEC₂ are output to the odd and even signal voltage hold circuits MO i as outputs DA 1out and DA 2out , respectively. In the signal voltage hold circuits MO₁ - MO N , these signals are blocked by the first analog switches ASWM , but in the signal voltage hold circuit MO i which is sequentially selected by the pulse Tm i , the signal voltage DA 1out or DA 2out is applied to the capacitor C M . At this time, the duration of the selection pulse Tm i is equal to two periods of the clock pulse, so that the signal voltage DA 1out or DA 2out is applied to the capacitor C M for a time period twice as long as in the embodiment of Figure 1. Thus, when all of the capacitors C M of the N signal voltage hold circuits MO₁ - MO N hold the signal voltages, the output pulse OE is supplied to all of the signal voltage hold circuits MO₁ - MO N , so that the signal voltages are output to the source lines O₁ - O N to be applied to the pixels. As described above, in the embodiment of Figure 4, the signal voltage DA 1out or DA 2out generated by the selected external voltage can be applied to the capacitor C M for the period of time twice as long as the duration of the digital video signal data (i.e., the period of the clock pulse). In other words, even if the duration of the digital video signal data is shortened, it is possible to take sufficient time for charging the capacitor C M in the circuit of this embodiment. Figure 6 is a block diagram showing in a simplified manner the signal voltage output circuit in the embodiment of Figure 4. In the circuits shown in Figures 1 and 4, the digital video signal is a 2-bit data. Next, the configuration of a D/A conversion circuit to which the digital video data of 4 bits is supplied is shown in Figure 7. In this case, according to the number of bits of the data, a sampling flip-flop M SMP comprises four flip-flops, and the required number of levels of external voltage is 2⁴ = 16 (V₀ - V₁₅). This may cause the decoder DEC to become large (4 inputs, and 16 outputs). However, after one of the external voltages V x selected by analog switches ASW₀ - ASW₁₅ is output as an output DA out , the circuit operates in the same manner as in the circuit of Figure 1. Furthermore, the block configuration of a signal voltage output circuit with two D/A conversion circuits DA1 and DA2 to which digital video signal data of 4 bits is supplied is shown in Figure 8. The configuration is the same as that of the circuit shown in Figure 6, except that the number of external voltage levels is 16 (V₀ - V₁₅). Accordingly, the circuit is suitable as a drive circuit for a liquid crystal panel which has numerous pixels and numerous gray-scale levels. The block configuration of a signal voltage output circuit having four D/A conversion circuits DA1 - DA4 is shown in Figure 9, and the signal timing chart is shown in Figure 10. In this case, pulses CK1 - CK4 the frequency of each of which is divided into four with respect to the clock pulse CK are used. The pulses CK1 - CK4 are shifted by one clock period. Each of the four D/A conversion circuits DA1 - DA4 samples digital video signal data every four data. In other words, the first D/A conversion circuit DA1 samples the (4k-3)th data such as the 1st data Data₁ and the 5th data Data₅. The second D/A conversion circuit DA2 samples the (4k-2)th data such as the 2nd data Data₂ and the 6th data Data₆ . The third D/A conversion circuit DA3 samples the (4k-1)th data such as the 3rd data Data₃ and the 7th data Data₇. The fourth D/A conversion circuit DA4 samples the 4kth data such as the 4th data Data₄ and the 8th data Data₈. The sampled data are held in the sampling flip-flops for the four periods of clock pulse. Since the duration of the selection pulse Tm i equals four periods of the clock pulse, the outputs DA 1out - DA 4out of the D/A conversion circuits DA1 - DA4 are respectively applied to the capacitors C M for a time period four times as long as the duration of the digital data. Therefore, the drive circuit is extremely advantageous, when the number of pixels is increased and the duration of the input signal is shortened. According to the invention, digital video signal data are first converted into analog voltage signals, and then the signal voltages are sequentially output to respective capacitors for holding signal electrodes in accordance with selection pulses, in the same manner as in the prior art analog drive circuit. Therefore, since the external voltage source is connected only to the selected pixels, the loads for the external voltage source can be made very small. Accordingly, even when the number of pixels is increased with the increase in size and the improvement in resolution of the display apparatus, the capacity of the external voltage sources can still be extremely small. Furthermore, in the drive circuit of the invention, since a digital sampling circuit is not provided for each source line, the numbers of flip-flops, decoders and the like are still small, even if the number of pixels is increased. Moreover, even if the number of bits of the digital video signal data is increased, the number of flip-flops, decoders and the like which become larger in size is small. Therefore, if the size is increased and the resolution is improved in the display apparatus, the chip size can be prevented from being drastically enlarged. Furthermore, by providing a plurality of circuits for converting digital video signal data into analog voltages, the external voltage can be supplied to the capacitor of each signal voltage hold circuit for a longer time period than the duration of the digital video signal data. Therefore, the drive circuit of the invention can be sufficiently used in a display apparatus with high resolution in which the duration of the video signal is short.

Claims: A drive circuit for driving a display apparatus having a set of signal electrodes (O) according to an input digital video signal, the circuit including voltage selecting means (DA;DA1-2;DA1-4) which is operable to repetitively sample the digital video signal and to output for each digital sample a signal voltage derived from a set of supply voltages (V₀-V₃;V₀-V₁₅) in accordance with that digital sample, and a plurality of signal voltage supply means (MO), each provided for supplying a said signal voltage to a respective one of said signal electrodes, and each connected to receive the same said output of said voltage selecting means, said signal voltage supply means each including a switching element (ASWM) controlled so as to pass the signal voltage for the corresponding signal electrode. A drive circuit according to claim 1, comprising a predetermined number of said voltage selecting means (DA1-2;DA1-4), said signal voltage supply means (MO) being divided into the same predetermined number of groups, every signal voltage supply means of each group connected to receive the same output of a respective one of the voltage selecting means. A drive circuit according to claim 1 or claim 2, comprising selection signal generating means for generating selection signals (Tm) by which said switching elements are made sequentially conductive, said selection signal generating means being connected to the control terminals of said switching elements of all said signal voltage supply means. A drive circuit according to claim 3, as appendant to claim 2, wherein each group of signal voltage supply means (MO) supplies said signal voltage to a respective group of signal electrodes arranged at every said predetermined number, and said selection signal generating means generates selection signals by which said switching elements are made conductive for a period which continues said predetermined number of times as long as the duration of said digital video signal sample. A drive circuit according to any of claims 1 to 4, wherein each signal voltage supply means (MO) includes a signal holding capacitor (CH).

Inventors: OKADA HISAO, OKADA, HISAO
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1991
Main classification: H04N3
IPC codes: H04N3, G09G3, G11C27, G02F1