Improved architecture and process for integrating DMD with control circuit substrates

Abstract: DMD projection light values for HDTV have various manufacturing requirements, including the high yield integration of the DMD superstructue 213 on top of an underlying CMOS address circuit 126. The CMOS chip surface contains several processing artifacts 110, and 124, that can lead to reduced yield for the DMD superstructure. A modified DMD architecture and process are disclosed that minimizes the yield losses caused by these CMOS artifiacts while also reducing parasitic coupling of the high voltage reset pulses to the underlying CMOS address circuitry.

Description: TECHNICAL FIELD OF THE INVENTION This invention relates to deformable mirror devices and more particularly to deformable mirror devices as defined in the precharacterizing part of claim 4 and to a method of forming such devices in conjunction with control circuit substrates as defined in the precharacterizing part of claim 1. A device of this type is disclosed in US-A-4 615 595. RELATED APPLICATIONS AND PATENTS All of the following patent applications are cross-referenced to one another, and all have been assigned to Texas Instruments Incorporated. These applications have been concurrently filed and are hereby incorporated in this patent application by reference. Attorney Docket # TI-14568 Multi-Level Deformable Mirror Device TI-14643 Improved Bistable DMD Addressing Circuit and Method TI-14649 Improved Architecture and Process for Integrating DMD With Control Circuit Substrates TI-14715 Field Updated Deformable Mirror Device Also referenced herein and incorporated by reference is: TI-13173A Spatial Light Modulator and Method, Serial #355,049, filed May 15, 1989; TI-14481 Spatial Light Modulator and Method, Serial #408,355, filed September 14, 1989; U.S. Patent 4,662,746 Spatial Light Modulator and Method Dated May 5, 1987; U.S. Patent 4,566,935 Spatial Light Modulator and Method Dated January 28, 1986; and U.S. Patent 4,615,595 Frame Addressed Spatial Light Modulator Dated October 7, 1986 BACKGROUND OF THE INVENTION Bistable deformable mirror devices (DMDs) are the subject of the above-listed copending U.S. patent application entitled "Spatial Light Modulator" (TI-13173A). There are many uses for such devices, such as, for example, as a projection light valve for high-definition television (HDTV). For such a system, DMD pixel arrays as large as 1.8 megapixels are required, addressed by an underlying CMOS address circuit. In order to minimize development costs and maximize chip yields, it is important to choose a well established, production tested CMOS technology. High volume CMOS wafer fabricators are reluctant to customize their CMOS process for a particular user's application. For this reason, it is necessary that the DMD superstructure place no special requirements on the CMOS process. Unfortunately, there are several process artifacts in the CMOS multi-level metalization process that can cause yield losses in the DMD superstructure. These artifacts include aluminum hillocks, pinholes in the protective oxide, a nonplanar chip surface and protective oxide contacts with a steep sidewall angle. An example of a DMD device is shown in above-listed patent application, TI-13173A entitled "Spatial Light Modulator" filed May 15, 1989. As shown in the aforementioned application, the DMD device has a beam reflective surface which is deformed, or pivoted, into contact with a landing pad or electrode under control of voltages selectively applied either by the beam or to a control electrode or to both. Aluminum hillocks can cause weak spots in the overlying protective oxide, leading to dielectric breakdown when high voltage reset pulses, which are necessary with DMD system arrays, are applied to the overlying landing electrodes. An additional problem is that the hillocks are replicated by the electrode metal and when hillocks are under the DMD address control electrodes, the DMD torsion beam can land on these hillocks, causing the address electrodes to be shorted to the beam. When hillocks are under the landing electrode, the beam is prevented from rotating to the full deflection angle, thereby reducing the light-to-dark effect of the deforming beam. In addition, pinholes in the protective oxide cause shorts between the electrode metal and the final CMOS metallization layer, thereby further reducing the yield of good devices and also reducing their life expectancy. The final CMOS metallization layer containing the electrical circuits is not planarized and it produces steps in the protective oxide which can lead to residual filaments when the electrode metal is etched with an anisotropic plasma etch. Thus, filaments cause shorts between neighboring electrodes. Finally, the protective oxide contacts in a standard CMOS process are not etched with sloped sidewalls, but rather tend to be nearly vertical. This can lead to poor step coverage of the electrode metal down into the contacts. A need therefore exists in the art for a DMD device which is constructed integral with a CMOS substrate without being effected by the typical CMOS artifacts. SUMMARY OF THE INVENTION A modified DMD superstructure architecture that has the features of the characterizing part of claims 1 and 4 and eliminates the effects of CMOS artifacts has been devised said architecture consisting of a planarizing organic first spacer layer (typically 0.5µm thick) spun over the CMOS address circuit prior to the electrode metal deposition. Contact openings and electrode support post holes are patterned in this first spacer layer which is then deep UV hardened to a temperature 10° to 20°C hotter than the hardening temperature for the next level spacer which is typically 180°C. The first spacer layer is hardened to give slightly tapered sidewalls to the contacts and support posts for good metal step coverage. Further, the conventional DMD process which consists of the following steps is carried out :First the electrode metal is deposited and patterned followed by the deposition of a second spacer layer and patterning of support post holes. Then the hinge and beam metal patterns are formed by deposition and patterning of metal layers on the surface of the second spacer layer. Finally, the air gaps under the deflectable beam elements are formed by a plasma undercut. During the plasma undercut of the beams, the first spacer layer and the second beam or support spacer layer are removed. The plasma undercut forms an air gap between the electrode and the underlying CMOS address circuit. The electrode is supported by the contacts and electrode support posts. The effect of the first spacer layer on the CMOS process artifacts is that the gaps between leads of the final CMOS metalization layers are planarized. Hillocks are planarized and air gap isolation is provided over the weakened overlying protective oxide. Air gap isolation is also provided over pinholes in the protective oxide. Finally, the steep oxide sidewalls of the protective oxide contacts are replaced by the sloped contacts of the spacer layer. There are additional benefits to the modified DMD superstructure architecture. Because the landing electrodes are air isolated from the address circuit, there is reduced parasitic coupling of the fast rise-time, high-voltage reset pulse train to the underlying address circuit. This coupling, if uncontrolled, can produce voltage spikes on the gates of the address transistors, causing the transistors to momentarily turn on at the wrong time. Finally, because the address electrodes are air isolated, they have reduced capacitance. It is therefore possible with this modified DMD superstructure architecture to build a frame-addressed DMD where the address electrode rather than the beam is charge-addressed. One technical advantage of adding a spacer layer in the manner described is that the new architecture minimizes the yield loss caused by CMOS process artifacts, reduces parasitic coupling between the DMD and CMOS and provides an alternate architecture for the charge-addressed DMD. BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: FIGURE 1 is a substrate showing CMOS artifacts; FIGURE 2 is a substrate with an electrode spacer layer added to remove the effect of the CMOS artifacts and showing overlying electrodes; FIGURE 3 is the completed structure before the spacers layers are removed; and FIGURE 4 is the completed structure with the spacers layers removed. DETAILED DESCRIPTION OF THE INVENTION FIGURE 1 illustrates how typical CMOS process artifacts can lead to reduced DMD superstructure yields. These artifacts include aluminum hillocks 110, pinholes 122 in the protective oxide, nonplanar chip surface and protective oxide contacts with steep sidewalls 112. A modified DMD superstructure architecture that eliminates these artifacts is shown in FIGURE 2. It consists of a planarizing organic electrode spacer layer 20 (typically 0.5 µm thick) spun over the CMOS address structure 100, 11 and 12 prior to the electrode metal deposition. This electrode spacer layer is distinguished from the conventional DMD support spacer layer formed between the electrode and beam. Contact openings 211 and electrode support post holes 215 are patterned in said electrode spacer layer 20 and said spacer layer is deep UV hardened to a temperature 10° to 20°C hotter than the hardening temperature for the DMD spacer layer which is typically 180°C. The hardening program is chosen to give slightly tapered sidewalls 210, 214 to the contacts 211 and support posts 215 for good metal step coverage. Gaps 112 between leads of the final CMOS metallization layers (217) are planarized. Hillocks 110 are planarized and air gap isolation is provided over the weakened overlying protective oxide. Air gap isolation is also provided over pinholes 122 in the protective oxide. Finally, the steep oxide sidewalls 126 of the protective oxide contacts 211 are replaced by the sloped contacts 210 of spacer layer 20. The electrode metal 21 is deposited and patterned after the deposition of the electrode spacer layer 20. There are additional benefits to the modified DMD superstructure architecture. Because the landing electrodes are air isolated from the address circuit, there is reduced parasitic coupling of the fast rise-time, high-voltage reset pulse train to the underlying address circuit. This coupling, if uncontrolled, can produce voltage spikes on the gates of the address transistors, causing the transistors to momentarily turn on at the wrong time. Finally, because the address electrodes are air isolated, they have reduced capacitance. It is therefore possible with this modified DMD superstructure architecture to build a frame-addressed DMD (U.S. Patent Number 4,615,595) where the address electrode rather than the beam is charge-addressed. In summary, this new architecture minimizes the yield loss caused by CMOS process artifacts, reduces parasitic coupling between the DMD and CMOS and provides an alternate architecture for the charge-addressed DMD. Then as shown in FIGURE 3, a support spacer layer 30 is spin-deposited over the electrodes and patterned with holes that will form beam support posts 309. Support spacer 30 determines the torsion beam angular deflection and is typically 2.3 microns thick and is a positive photoresistant. It is deep UV hardened to a temperature of 180°C to prevent flow and bubbling during subsequent processing steps. Note that no degradation of the electrode spacer layer 20 occurs during this bake because said spacer layer 20 was hardened to a higher temperature (200° C). Finally, thin hinges 310 and thick beams 311 are formed on spacer 30 by a deposition and patterning process shown in the aforementioned U.S. Patent 4,662,746. This completes the process at the wafer level. The wafers are then coated with PMMA, sawed into individual chips and pulse spin-cleaned with chlorobenzene. Finally, the chips are placed in a plasma etching chamber where both spacer layers 20 and 30 are completely removed to form the air gaps under the hinges and beams as shown in FIGURE 4. Although this description describes the invention with reference to the above specified embodiments, the claims and not this description limits the scope of the invention. Various modifications of the disclosed embodiment, as well as alternative embodiments of the invention, will become apparent to persons skilled in the art upon reference to the dependent claims.

Claims: A method of planarizing an integrated semiconductor substrate for the purpose of constructing thereon an electromechanical device, said method comprising the steps of forming electrodes, spinning a planarizing liquid organic material over said electrodes to form a support spacer layer (30), patterning and curing said support spacer layer (30) to form support posts (309) for the mechanical portion of said electromechanical device, depositing and patterning a metal layer to form said mechanical portion (310, 311), and removing said spacer layer (30), said step of forming said electrodes being further characterized by: spinning a planarizing liquid organic material on said substrate to form an electrode spacer layer (20) prior to forming said electrodes; curing and patterning said electrode spacer layer (20) to form support posts (215) for said electrodes; and removing said electrode spacer layer (20) when said support spacer layer (30) is removed. The method set forth in claim 1 wherein said removing step allows mechanical gaps to exist between certain portions of said integrated semiconductor substrate and said formed electrodes and between certain portions of said formed electrodes and said established mechanical portion. The method set forth in claim 2 wherein said substrate is a CMOS substrate having a traditional oxide or nitride protective top coating over which said planarizing liquid is spun-on. An electromechanical device having a selectively movable mechanical portion constructed on an integrated semiconductor substrate, comprising electrodes, a mechanical portion being suspended over said electrodes by support posts (309), said electrodes characterized in that they are suspended over said substrate by electrode support posts (215). The device set forth in claim 4 wherein said substrate is a CMOS substrate having a traditional oxide or nitride protective top coating.

Inventors: HORNBECK LARRY J, HORNBECK, LARRY J.
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1991
Main classification: H01L21
IPC codes: H01L27, G02B26, H01L21