Security circuit for protecting data stored in an internal memory of a microcomputer

Abstract: The security circuit for protecting data stored in an internal memory of a microcomputer, comprises a first memory (2) for storing a security code supplied from external; a latch circuit (4) for latching a key code in order to read the data stored in the internal memory; a comparator (6) for comparing whether or not the security code in the first memory (2) and the key code in the latch circuit (4) are in agreement and for outputting comparison results; a second memory (12) for storing the comparison results of the comparator ( 6); and a read control circuit (20) for using the comparison results stored in the second memory (12) as the basis to prohibit read of data in the internal memory when the security code and the key code are not in agreement, and for using an output control signal which is inputted from external when there is agreement as the basis to control read of data stored in the internal memory.

Description: The present invention relates to a security circuit for protecting data which are stored in an internal memory of a microcomputer, said security circuit comprising: said internal memory, first non-volatile memory means for storing an externally inputted security code, latch means for latching a key code which is inputted in order to read said data that are stored in said internal memory, and comparator means for comparing whether or not said security code that is stored in said first memory means and said key code that is latched by said latch means are in agreement, and for outputting the comparison result. Such a security circuit is known from US-A-4 864 542. The invention finds particular application to use in single-chip microcomputers. The problem of security of data written to ROM that are internal to single-chip microcomputers has been being investigated for a long time and methods such as prohibiting the read of data in ROM have been thought of. In the conventional technology, the writing by the user of "0" or "1" in an electrically programmable ROM (EPROM) that stores the (1 bit) security code performs security operation to operate a security circuit and prohibit the read of data (programs) inside a ROM. In this conventional technology, once the security circuit has operated, it is not possible for the data that are stored in the ROM to be read by the user for the purpose of maintenance and management. In the light of this problem, the present invention has as an object the provision of a security circuit that enables the user who applied the security, to read data such as programs and the like that are stored in the memory, and that disables read by other users. The present invention is a security circuit as hereinbefore, defined and is characterised in further comprising: second non-volatile memory means for storing said comparison result dependent on an external write signal, said external write signal enabling, in its active state, said second memory means to store a value indicating said comparison result, and causing, in its inactive state, said second memory means to store, irrespective of said comparison result, the same value stored when the comparison result indicates non-agreement, and read control means arranged to use the value stored in said second memory means as a basis to prohibit read of data stored in said internal memory when the value stored indicates non-agreement, and also arranged to use an output control signal that is inputted from external when the comparison result indicates agreement as the basis to control read of data stored in said internal memory, and said security circuit being further characterised in that said internal memory is non-volatile. According to embodiments of the security circuit of the present invention and having the configuration described above, the input of a security code causes that security code to be stored in a non-volatile first memory, for example. Then, the key code to read that data that is stored in the internal memory is input and this key code is latched by the latch circuit. Also, this latched key code is compared in a comparator circuit with a security code which is stored in a non-volatile first memory and the results of comparison are stored in a non-volatile second memory. Then, the results of comparison which are stored in the second memory are used as the basis to prohibit the read of data stored in the internal memory when the security code and the key code are not in agreement, and an output control signal that is input from external when there is agreement is used as the basis to control the read of data that are stored in the internal memory. By this, for as long as the correct key code is not inputted, it is not possible to read that data from the internal memory, and it is possible for the user who has applied the key code to read that data of the program and the like that are stored in the internal memory, but it is not possible for this to be read by other users. The invention will be better understood by referring, by way of example, to the appended drawings, in which:- FIG. 1 is a block diagram showing one configuration of a security circuit according to an embodiment of the present invention; and FIG. 2 is a flow chart for describing the operation of the security circuit shown in FIG. 1. FIG. 1 is a block diagram showing the configuration of one form of security circuit according to an embodiment of the present invention. The security circuit of this embodiment is provided with a first memory 2, a latch circuit 4, a comparator circuit 6, an AND circuit 7, a flip-flop 8, a NOT circuit 9, a NAND circuit 10, a second memory 12 and a read control circuit 20, and the data that are stored in the internal memory such as an EPROM (not indicated in the figure) that is internal to the microcomputer or the like, is protected. The memory 2 is for example, a non-volatile memory comprising an EPROM and stores the security code that is inputted from external. The latch circuit 4 latches the key code that is input, in order to read the data that are stored in the memory internal to the microcomputer or the like. The comparator circuit 6 compares the key code that is latched to the latch circuit 4, with the security code that is stored in the first memory 2. The second memory 12 is a non-volatile memory comparing a 1-bit EPROM for example, and stores the comparison results that were compared by the comparator circuit 6. The read control circuit 20 has an AND circuit 21, an OR circuit 22, a NOT circuit 23 and an AND circuit 24, and controls the read of data that is stored in the memory (EPROM) internal to the microcomputer not indicated in the figure. Numeral 15 shows a NOT circuit that supplies to a reset terminal R of the flip-flop 8 a reset signal RESET having a negative level, and numeral 30 indicates an address decoder for decoding coded address data. The following is a description of the configuration and operation of the present embodiment, with reference to FIG. 1 and FIG. 2. First, when security has not been applied, that is, when the security code has been inputted, the step ST1 in FIG. 2 becomes NO, and the signal S 3 that is sent from the first memory 2 to the OR circuit 22 of the read control circuit 20 becomes the "1" status (refer to step ST2). At this time, the signal S 13 that controls the read of the data stored in the internal memory (EPROM) not indicated in the figure, is outputted from external and is inputted via the NOT circuit 23 in accordance with the output control signal OE (step ST3 and step ST4). More specifically, when the signal OE is "1", the output of the NOT circuit 23 becomes "0" and accordingly, the signal S 13 that is the output of the AND circuit 24 becomes "0" and read of the data from the internal memory (EPROM) not indicated in the figure is not performed (step ST5). Also, when the signal OE is "0", the output of the NOT circuit 23 becomes "1" and so the read enable signal which is the output of the AND circuit 24 becomes "1" (step ST6) and it is possible to read the data from the memory not indicated in the figure (step ST7). The following is a description of the case when security is applied. When the- security code and the address of the memory 2 are input (YES for step ST1), the signal S 1 sent from the address decoder 30 to the memory 2 becomes "0" and the memory 2 enters the status where data write is possible, and the security code is sent to the memory 2 via the data bus and stored. When this occurs, the signal S 3 sent from the memory 2 to the OR circuit 22 of the read control circuit 20 becomes "0" (step ST8). After the security code has been inputted in this manner, and the data that are stored in the memory (not indicated in the figure) internal to the microcomputer or the like is to be read, it is necessary to input the security code and the address of the latch circuit 4. Accordingly, this is judged in step ST9. When the key code and the address of the latch circuit 4 are input, the signal S 2 is sent from the address decoder 30 to the memory 2, the latch circuit 4, and the flip-flop 8. The first memory 2 enters the read mode, the flip-flop 8 enters the set status and the key code is latched to the latch circuit 4 (step ST10). Then, the security code that is stored in the memory 2 and the key code that is latched to the latch circuit 4 are compared in the comparator circuit 6 (step ST11) and if they are in agreement, the signal S 4 that is sent from the comparator circuit 6 to the AND circuit 7 becomes "1" (step ST12). The signal S 5 that is sent from external to the AND circuit 7 becomes "1" when the write voltage V pp is impressed (step ST14) and becomes "0" when the write voltage V pp is not impressed (step ST19). Accordingly, in step ST13, the write voltage V pp is determined as to whether or not it is impressed. The following will consider the case when the signal S 5 is "1" and the security code and the key code are in agreement, that is, the case for when the signal S 4 is "1". When this occurs, the output signal S 6 of the AND circuit 7 becomes "1" (step ST15) and the output signal S 7 of the NOT circuit 9 becomes "0". By this, the output signal S 9 of the NAND circuit 10 becomes "1" and write to the second memory 12 is performed. Moreover, the output signal S 8 of the flip-flop 8 is in the set status and is therefore "1". When there is not write, the signal S 10 sent from the memory 12 to the AND circuit 21 of the read control circuit 20 is "1" and so the signal S 11 sent from the AND circuit 21 to the OR circuit 22 becomes "1". Accordingly, the read enable signal S 13 which is the output of the read control circuit 20 is in accordance with the output control signal OE that is inputted from external. Judging step ST16 is the same as step ST13, so that the external input signal OE is judged whether it is in the read mode or not. Namely, when the signal OE is not "1", the signal S 13 becomes "1" (step ST6), and it is possible to read the data that stored in the memory (EPROM) not indicated in the figure (step ST7). Moreover, when step ST16 is determined to be YES the signal S 13 becomes "0" (step ST7), and it is impossible to read the data after this. On the other hand, when there is not agreement between the key code and the security code when the two are compared by the comparator circuit 6 (NO for step STll), the signal S 4 becomes "0", (step ST19), an output signal S 6 of the AND circuit 7 becomes "0" (step ST21). Then, an output signal S 7 of the NOT circuit 9 becomes "1". Also, since the signal S 8 becomes "1", an output signal S 9 of the NAND circuit 10 becomes "0" and is written to the second memory 12. When there is write to the memory 12, the signal S 10 becomes "0" and so the output signal S 11 of the AND circuit 21 becomes "0". Also, the security code is stored in the memory 2 and so the signal S 3 also becomes "0" and so the output signal S 12 of the OR circuit 22 also becomes "0". Accordingly, the read enable signal S 13 that is the output of the read control circuit 20 is always "0" and the read of the data that is stored in the memory (EPROM) internal to the microcomputer or the like is not possible for as long as the data in the memory 12 is not erased (step ST18). Moreover, if the data in the memory 12 is erased, then the memory for which read was prohibited, that is, the data in the memory internal to the microcomputer or the like is also erased at the same time and security is ensured. As has been described above, according to the present embodiment, it is possible for the user who has applied security to read the data that is stored in the memory but it is not possible for this data to be read by other users. Normal read is also not possible when an erroneous security code has been input. Accordingly, with the present embodiment, it is possible for the user who has applied security to read the data that is stored in the memory but it is not possible for this data to be read by other users. Also, normal read is not possible after an erroneous security code has been input. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A security circuit for protecting data which are stored in an internal memory of a microcomputer, said security circuit comprising: said internal memory; first non-volatile memory means (2) for storing an externally inputted security code; latch means (4) for latching a key code which is inputted in order to read said data that are stored in said internal memory; and comparator means (6) for comparing whether or not said security code that is stored in said first memory means (2) and said key code that is latched by said latch means (4) are in agreement, and for outputting the comparison result; said security circuit being characterized in further comprising: second non-volatile memory means (12) for storing said comparison result dependent on an external write signal (S5), said external write signal (S5) enabling, in its active state, said second memory means (12) to store a value indicating said comparison result, and causing, in its inactive state, said second memory means (12) to store, irrespective of said comparison result, the same value stored when the comparison result indicates non-agreement; and read control means (20) arranged to use the value stored in said second memory means (12) as a basis to prohibit read of data stored in said internal memory when the value stored indicates non-agreement, and also arranged to use an output control signal (OE) that is inputted from external when the comparison result indicates agreement as the basis to control read of data stored in said internal memory; and said security circuit being further characterised in that said internal memory is non-volatile. The security circuit according to claim 1, wherein: said first and second memory means (2, 12) are each comprised of an electrically programmable read only memory (EPROM) of a non-volatile memory. The security circuit according to claim 1 or 2, wherein: said security circuit is connected with a data bus for transferring said security code to said first memory means (2) and said key code to said latch means (4), respectively. The security circuit according to any preceding claim, further comprising an address decoder (30) which is connected with an address bus and is arranged to supply to said first memory means (2) a signal (S1) for directing write of said security code, and to said latch means (4) a signal (S2) for directing latch of said key code, respectively. The security circuit according to claim 4, further comprising a set-reset flip-flop (8) having a set terminal (S) for receiving said signal for directing latch of said key code to said latch means (4) as an input setting signal, and a reset terminal (R) thereof for receiving an external reset signal. The security circuit according to claim 4 or 5, further comprising a data bus for transferring said security code and said key code inputted from an input device to said first memory means (2) and said latch means (4), respectively, and an address bus for transferring address data inputted from said input device to said address decoder (30). The security circuit according to any preceding claim, wherein the security circuit is formed as a single chip.

Inventors: YAEZAWA KATSUMI, YAEZAWA, KATSUMI, YAEZAWA, KATSUMI, 414, TOSHIBA MICRO ELECTRONICS
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1991
Main classification: G11C7
IPC codes: G06F15, G11C7, G06F21, G06F12