Transversal equalizer

Abstract: A transversal equalizer having a specified number of rear taps. The transversal equalizer is characterized by further including a first transversal equalizer unit (TF1) which receives input signals through a first input terminal, equalizes their waveforms, and outputs the equalized signals as cascaded signals and a second transversal equalizer unit (TF2) which receives the cascade output signals and also receives input signals and outputs an equalized signal derived from the input signals.

Description: The present invention relates generally to a transversal equalizer, and more particularly, to a transversal equalizer for a real-time filter processing on input signals. In recent years, a GCR (ghost cancel reference) signal has been adopted in a TV broadcasting signal. The GCR signal is placed in the vertical retrace line period of the TV signal to be referenced for deghosting operation in TV receivers. Such a TV receiver uses a transversal equalizer for performing the deghosting operation in reference to the received GCR signal. Shown in FIGURE 1 is a typical construction of such a transversal equalizer. Such a transversal equalizer shown in FIGURE 1 is discussed in, for example, Shri Goyal et al., "Performance Evaluations of Selected Automatic Deghosting Systems for Television", "IEEE Transactions on Consumer Electronics", Vol. CE-26, pp. 100-120 (February 1980) and is called a 6-taps transversal equalizer. In FIGURE 1, an input signal is sampled at every T second and this input sample value Xi is applied to the input terminal 1. This input sample value Xi is applied to the multipliers M1 through M6, respectively and multiplied by coefficients (hereinafter called tap coefficients)C1 through C6. Outputs of the multipliers M1 through M6 are applied to the adders A1 through A6, respectively. Outputs from the adders A1 through A6 are delayed by the delay units D1 through D6, respectively and applied to the output terminal 2 and the adders A1 through A5 in the next filter stage. Further, the delay units D1 through D6 are driven by the clock CK having a period of T second supplied through the input terminal 3, and outputs the input signals delayed by T seconds. At the output terminal 2, an output based on a tap coefficient appears and it is possible to equalize the transmission lines by setting the tap coefficient. Further, signals from a preceding stage may be input to the cascade input terminal 4. This signal is added to the output from the multiplier M6 in the adder A6. Now, assuming that an input sample value Xi is δ function {δi}, its impulse response {αi} is α1 = C1, α2 = C2, ..., α6 = C6. As the length of a train of impulse responses is the same as the number of taps, a longer train of impulse responses is obtained by increasing the number of taps. That is, filtering time can be extended by increasing the number of taps. The range of delay times in which ghost can be cancelled by GCR signal is 44.7 µs of GCR signal width. See, for example, Susumu Takayama et al., "System of Ghost Cancel Reference Signal", "1989 National Convention Record of the Institute of Television Engineers of Japan", pp. 239-240. As described above, the length of the filtering time is determined by the number of taps and the number of taps required to obtain the range of 44.7 µs delay time is expressed by 44.7 µs/T (clock period). Normally, the clock frequency in the TV signal digital processing is set at 4 times the color subcarrier frequency (14.31818 MHz) and the clock period T is 69.84 ns. Thus, in de-ghosting using a GCR signal, as many as 640 taps are needed. Transversal equalizers have normally been made in integrated circuits (IC) and with the advanced degree of integration, 64 taps have been integrated in a single chip such as TF-IC adopted in Toshiba's ghost clean TV tuner (TT-GC9). Shown in FIGURE 2 is a block diagram showing a conventional transversal equalizer which has adopted such transversal equalizers. See, for example, "Ghost Image Reducing Tuner and its Operation", Japanese magazine "Chroma", pp. 48-51, (December 1989). A video signal subjected to disturbance by a ghost image is applied to the input terminal 5. In this input video signal the GCR signal has been inserted. The incoming video signal is applied to the input terminal 6 of the transversal equalizer 11. The cascade input terminal 7 of the transversal filter 11 is connected to the reference voltage point. Further, the input terminals 6 and 7 correspond to the input terminals 1 and 4 shown in FIGURE 1. To respective taps of 64 multipliers of the transversal filter 11, not shown, tap coefficients C-29 and C34 are applied. Further, subscripts of the tap coefficients indicate which delay time of clock period T they correspond to. The coefficient of the main tap corresponding to the rising edge of the GCR signal is C0 and 1 is set for C0 and 0 for other tap coefficients at the time of initialization. Therefore, in the state of initialization, the transversal filter 11 directly outputs the video signal input from the input terminal 6 to the output terminal 8. This transversal filter 11 is of the non-recursive type and cancels ghosts existing between -2 µs (pre-ghost) and 2.4 µs (delayed-ghost) by the tap coefficients C-29 through C34. That is, cancellation of waveform distortion (waveform equalization) and cancellation of ghost in short delay times (nearby-ghost) are performed by the transversal filter 11. The output from the transversal filter 11 is applied to the output terminal 10 through the subtractor 9 and,at the same time, to the delay unit 21 from the output terminal 10. Output of the delay unit 21 is applied to the input terminal 6 of each of the transversal filters 12 through 20 in the same construction as the transversal filter 11. The number of taps of the transversal filters 12 through 20 is 64 and tap coefficients C35 through C610 are applied to the transversal filters 12 through 20. That is, the transversal falters 12 through 20 correspond to delayed ghosts existing between 2.4 µs and 42.6 µs. Output from respective output terminals 8 to the transversal equalizers 20 through 12 are applied to each cascade input terminal 7 of the transversal filters 19 through 12 in the next stage and to the substractor 9, thus forming the recursive filter. The coefficients C35 through C610 are set at 0 in the initial state and when tap coefficients are corrected thereafter, a ghost cancelling signal is output from the transversal equalizer 12. The subtractor 9 outputs a deghosted video signal to the output terminal 10 after subtracting the ghost cancelling signal from the output of the transversal filter 11. Tap coefficients C-29 through C610 are obtained through operation of the GCR signal extracted from input/output video signals and reference signal and are successively corrected at specified time intervals. That is, the GCR signal contained in video signal from the input terminal 5 and GCR signal contained in the video signal from the output terminal 10 are extracted, the GCR signal contained in the output video signal is compared with a reference signal to get an error signal and further, correlated operation of this error signal with GCR signal contained in the input video signal is carried out and tap coefficients are corrected to minimize the error signal. Further, as described above, the same ICs are used for the transversal filters 11 through 20 to reduce the cost of the equalizer. As described above, waveform equalization and nearby-ghost image removal are performed by the non-recursive transversal filter 11 and long delayed ghost and secondary ghost (see the above-mentioned magazine, "Chroma") produced by this transversal filter 11 are removed by the recursive transversal filters 12 through 20. Series connection of the non-recursive and recursive transversal filters is the construction best suited for the removal of ghost image as shown in the above-mentioned "Chroma". Generally, if pre-gost images of delay time less than 2 µs are removed, there will be no problem in practical use. Hovewer, the delay time of delayed ghost image may sometimes be more than 40 µs. Since the range of delay times for ghost images which can be removed is 44.7 µs as described above, the corresponding range of pre-ghost images was set at -2 µs in the example shown in FIGURE 2. That is, tap coefficients of the transversal filter 11 are from C-29, through C0 to C34. The circuit is of such a construction that output of the transversal filter 11 and the transversal filter 12 are subtracted in the subtractor 9 to remove ghost image components. The delay unit 21 operates for a delay time 34T. So that output of the transversal filters 11 and 12 are delayed by T on time base. It is, however, considered that with the advancement of integration of digital IC, the number of taps that can be integrated in a single chip will further increase in the future. If so, the number of taps of the transversal filter 11 will be increased. In this case, therefore, it becomes also necessary to extend the delay time (the number of delay taps) of the delay unit 21 corresponding to the increase in the number of taps in order to delay the outputs of the transversal filters 11 and 12 by T. This will increase the size of the circuit and its cost. Thus, in the conventional transversal equaliser described above there is the problem that it becomes necessary to increase the delay time of the delay unit and the circuit size becomes large, with a corresponding increase in the number of taps in a single chip. A channel equaliser and ghost cancelling technique are disclosed in US-A-4359778. The equaliser comprises a chain of cascaded filters, and the filter conditions are altered until the ghosts resulting from a training signal are eliminated. Patent Abstracts of Japan vol 13 no. 2 (E700) and JP-A-63214024 discloses an echo suppressor which suppresses ghost echos by means of a cyclic filter connected in cascade with non cyclic filters. Patent Abstracts of Japan vol 5 no. 23 (E45) and JP-A-55149524 discloses an automatic equalisation system in which a first non cyclic filter is connected to a second equaliser. The present invention therefore seeks to provide a transversal equaliser which is able to reduce the circuit size without requiring a delay unit even when the series connection of recursive and non-recursive transversal equalizers is adopted. According to a first aspect of the present invention, there is provided a transversal equaliser comprising: (i) a first transversal filter (TF1) comprising: a first input means (31) for receiving a first equaliser input signal; a plurality of multiplier means (M-k -Mm-1), coupled in parallel to the first input means (31), for respectively multiplying the first equaliser input signal by predetermined coefficients (C-k -Cm-1); a plurality of adder means (A-k -Am-1) respectively coupled to outputs of the multiplier means (M-k -Mm-1) for adding the outputs of the multiplier means (M-k -Mm-1); a plurality of delay means (D-k -Dm-1) coupled to outputs of respective adder means (A-k -Am-1) for delaying outputs thereof; a first cascade input means (33) coupled to a first adder means (A-k) of the first transversal filter (TF1) for receiving a cascade equaliser input signal; and a first output means coupled to a last of the delay means of the first transversal filter (Dm-1) for outputting a first output signal; (ii) a second transversal filter (TF2) comprising: a second input means (32) for receiving a second equaliser input signal or the first equaliser input signal; a plurality of multiplier means (Mm -Mn-1), coupled in parallel to the second input means (32), for respectively multiplying the input signal by predetermined coefficients (Cm -Cn-1); a plurality of adder means (Am - An-1) respectively coupled to outputs of the multiplier means (Mm -Mn-1) for adding the outputs of said multiplier means (Mm -Mn-1); a plurality of delay means (Dm -Dn-1) coupled to outputs of respective adder means (Am -An-1) for delaying outputs thereof; and a second cascade input means coupled to a first adder means (Am) of the second transversal filter, the second cascade input means being coupled to the first output means of the first transversal filter; (iii) a second output means coupled to a last delay means (Dn-1) of the second transversal filter for outputting a second output signal; (iv) an equaliser output means for outputting an equalised output signal; (v) a delay means (41) coupled to the second output means, for delaying the signal output from the second output means by a specified time; (vi) a selecting means (42) connected to said delay means (41) and to said second output means, which couples the signal from one of said delay means or said second output means to the equaliser output means. According to a second aspect of the present invention, there is provided a transversal equaliser device comprising a first transversal equaliser (40a), as set out above in which the selecting means (42) couples the signal from the second output means to the equaliser output means of the first equaliser, and a second transversal equaliser (40c) as set out above in which the selecting means couples the signal from the delay means (41) to the equaliser output means of the second equaliser, wherein: the signal to be equalised is applied to the first input means (31a) of the first equaliser and the equalised signal is supplied from the equaliser output means of the second equaliser (34c); the equaliser output means of the second equaliser (34c) is coupled to the second input means (32a) of the first equaliser (40a) and to the first (31c) and second (32c) input means of the second equaliser (40c); and the equaliser output means of the first equaliser (34a) is coupled to the first cascade input means (33c) of the second equaliser (40c). According to a third aspect of the present invention, there is provided a transversal equaliser device comprising a first and second transversal equaliser (30a, 30c) each transversal equaliser comprising: first and second transversal filters (TF1, TF2) each filter comprising: an input means (31, 32) for receiving an equaliser input signal; a plurality of multiplier means coupled in parallel with the input means (31, 32) for multiplying the input signal by predetermined coefficients; a plurality of adder means respectively coupled to outputs of the multiplier means for adding the outputs of the multiplier means; a plurality of delay means coupled to the outputs of respective adder means for delaying the outputs thereof; a cascade input means coupled to the respective first adder means; and an output means coupled to the respective last of the delay means; wherein the transversal equaliser device also comprises: a delay means (36), coupled to the output means (34c) of the second filter (TF2c) of said second transversal equaliser (30c); an equaliser input means (37), to which the signal to be equalised is applied; and an equaliser output means (38), coupled to said delay means (36), from which the equalised signal is supplied; wherein the equaliser input means (37) is connected to the input means (31a) of the first filter (TF1a) of the first transversal equaliser (30a); the equaliser output means (38) is connected to the input means (32a) of the second filter (TF2a) of the first transversal equaliser (30a) and to the input means of the first and second filters of the second transversal equaliser (30c); the output means of the first filter (TF1a, TF1c) of each transversal equaliser (30a, 30c) is connected to the cascade input of the second filter (TF2a, TF2c) of the respective equaliser (30a, 30c); and the output means (34a) of the second filter (TF2a) of the first equaliser (30a) is coupled to the cascade input means (33c) of the first filter (TF1c) of the second equaliser (30c). For a better understanding of the present invention and many of the attendant advantages thereof reference will now be made by way of example to the accompanying drawings, wherein: FIGURE 1 is a circuit diagram showing a conventional transversal filter; FIGURE 2 is a circuit diagram showing a conventional deghosting apparatus using the transversal filter of FIGURE 1; FIGURE 3 is a circuit diagram showing a transversal equalizer; FIGURE 4 is a circuit diagram showing a transversal equaliser device incorporating the transversal equalizer of FIGURE 3; FIGURE 5 is a circuit diagram showing a transversal equalizer according to the present invention; FIGURE 6 is a circuit diagram showing a transversal equalizer device according to the invention incorporating the transversal equalizer of FIGURE 5; and FIGURE 7 is a circuit diagram showing another transversal equalizer device incorporating the transversal equalizer of FIGURE 5, according to the present invention. The present invention will be described in detail. Throughout the drawings, reference numerals or letters used in FIGURES 1 and 2 will be used to designate like or equivalent elements for simplicity of explanation. Referring now to FIGURE 3, a first arrangement of a transversal equlizer will be described in detail. A transversal equalizer 30, enclosed in a broken line, is composed of the transversal filters TF1 and TF2 which are connected in series. The transversal filters TF1 and TF2 are the same construction as the transversal equalizer shown in FIGURE 1. The transversal filter TF1 has k+m coefficient multipliers, i.e., k+m taps (not shown). The coefficients C-k through Cm-1 respectively are applied to these taps. The transversal filter TF2 has n-m coefficient multipliers, i.e., n-m taps (not shown). The coefficients Cm through Cn-1 respectively are applied to these taps. On the transversal filters TF1 and TF2, the cascade output of the preceding stage is output to the cascade input terminal 4. An incoming signal is applied to the input terminal 1. A waveform equalization is performed through multiplication based on tap coefficients by the coefficient multiplier and delay processing based on clock CK which is input to the terminal 3. Then signals are output from the output terminal 2 after waveforms are equalized. The input terminals 31 and 32 of the transversal equalizer 30 are connected to the input terminal 1 of the transversal filters TF1 and TF2, respectively. The cascade input terminal 33 is connected to the cascade input terminal 4 of the transversal filter TF1 and provides the cascade output of the transversal equalizer at a preceding stage (not shown) to the transversal filter TF1. The cascade output from the output terminal 2 of the transversal filter TF1 is applied to the cascade input terminal 4 of the transversal filter TF2. The output terminal 34 is connected to the output terminal 2 of the transversal filter TF2 and leads out the cascade output. Clock CK supplied to the clock input terminal 35 of the transversal equalizer 30 is applied to the delay unit (not shown) through the input terminal 3 of the transversal filters TF1 and TF2. Further, when 214 is set as the total number of taps (k+n) of the transversal equalizer 30, values of 29, 35 and 185 are considered for k, m and n, respectively, when conventional equalizing performance is considered. That is, the number of fore taps of the transversal filter TF1 is 29 and the number of rear taps is 34. These figures are equivalent of those of the transversal filter TF1. In this case, equalization times of the transversal filter TF1 ranges from -kT to (m-1)T (T is the clock period) and if T is 69.84 ns, they range from -2 to 2.4 µs. Further, the transversal filter TF2 has a range of equalization times from mT to (n-1)T (35T through 184T). In the transversal equalizer constructed as described above, when non-cyclic and cyclic type filters are connected in series, it is necessary to connect a delay unit (not shown) which generates some delay time (m-1)T of the transversal filter TF1 between the output terminal 34 and the input terminal 32. The cascade output from the transversal filter TF2 is input to the input terminal 1 of the transversal filter TF2 through the input terminal 32 after being delayed by (m-1)T. On the other hand, the cascade output from the output terminal 2 of the transversal filter TF1 is input to the cascade input terminal 4 of the transversal filter TF2. That is, the operation corresponding to the last tap of the transversal filter TF1 and that corresponding to the first tap of the transversal filter TF2 are continuously carried out on the time base. Furthermore, it does not depend on the number of taps of the transversal filter TF2. For instance, if the maximum delay time is set at the same delay time as before by the transversal filter TF1, it is possible to use a delay unit which operates for the same delay amount as before irrespective of the number of taps of the transversal filter TF2. Thus, it has been made possible to perform waveform equalization and removal of ghost images through series connection of non-cyclic and cyclic type filters without increasing the number of stages of the delay units. Shown in FIGURE 4 is a circuit diagram showing an embodiment of the transversal equalizer device according to the present invention applied to a deghosting apparatus. In this embodiment, transversal equalizer ICs 30a, 30b and 30c are the same construction as the transversal equalizer 30 shown in FIGURE 3, and are used by connecting them in series. A video signal containing ghost components is input to the input terminal 37. This video signal is input to the input terminal 31a of the transversal equalizer IC 30a. The cascade input terminal 33a of the transversal equalizer IC 30a in the initial stage is connected to the reference voltage point and the cascade output from the output terminal 34a is applied to the cascade input terminal 33b of the transversal equalizer IC 30b in the next stage. The cascade output from the transversal equalizer IC 30b is applied to the cascade input terminal 33c of the transversal equalizer IC 30c in the last stage through the output terminal 34b. The cascade output from the output terminal 34c of the transversal equalizer IC 30c is applied to the delay unit 36, which operates at (m-1)T delay time and outputs a delayed output signal to the output terminal 38 and at the same time, to the input terminals 31b, 31c, 32a, 32b and 32c of the transversal equalizers 30a, 30b and 30c. Thus, the transversal filter TF1a is a non-cyclic type construction and the transversal filters TF2c, TF1c, TF2b, TF1b and TF2a are cyclic construction. A video signal received through the input terminal 31a is applied to the coefficient multipliers of the transversal filter TF1a. To all the taps of the transversal filter TF1a, tap coefficients C-k through Cm-1 are applied, respectively and the transversal filter TF1a performs waveform equalization based on the tap coefficients and gives the cascade output to the transversal filter TF2a. Waveform equalization in the time range of -kT through (m-1)T is possible by the transversal filter TF1a and therefore, as described above, the delay unit 36 which operates at (m-1)T delay time is adopted. Further, clock CK is applied at the clock input terminal 39. This clock CK is applied to the delay units(not shown) through the clock input terminals 35a, 35b and 35c. In order to continuously carry out the operation corresponding to the last taps of the transversal filter TF1a and that corresponding to the first taps of other transversal filters TF2a, TF1b, TF2b, TF1c and TF2c on the time base, the signal is delayed for a delay amount by the delay units, which give the signal to the delay unit 36. The more taps located closer to the front stage side from this tap, the more the delay amount in the cyclic loop increases, and the tap coefficient C3n+2k-1 (C612) to remove ghost image of the longest delay time is applied to the tap of the transversal filter TF2a to which the cascade output of the transversal filter TF1a is applied. That is, tap coefficients C3n+2k-1 through Cm+2n+2k are applied to the taps of the transversal filter TF2a, tap coefficients Cm+2n+2k-1 through C2n+k to the taps of the transversal filter TF1b, tap coefficients C2n+k-1 through Cn+m+k to the taps of the transversal filter TF2b, coefficients Cn+m+k-1 through Cn to the taps of the transversal filter TF1c, and tap coefficients Cn-1 through Cm to the taps of the transversal filter TF2c. The transversal filters TF1a, TF2a, TF1b, TF2b, TF1c and TF2c perform waveform equalization based on these tap coefficients. In the embodiment of the transversal equalizer as described above, if k, m and n are assumed to be, for instance, 29, 35 and 185, respectively, the number of front taps of the transversal filter TF1 will be 29, the number of rear taps will be 34 and the total number of taps of the transversal equalizer ICs 30a, 30b and 30c will become 642. That is, if the T is 69.84 ns, the non-cyclic type transversal filter TF1a will remove -2 through 2.4 µs pre-ghost and nearby-ghost images and the cyclic type transversal filters TF2c, TF1c, TF2b, TF1b and TF2a will remove 2.4 through 42.7 µs long delayed ghost images. As described above, in this embodiment the transversal filter TF1a is non-cyclic type construction and the transversal filters TF2a, TF1b, TF2b, TF1c and TF2c are cyclic type construction by giving the cascade outputs of the transversal equalizers to the transversal equalizers in the next stage and also, by giving the output from the transversal filter TF2c in the last stage to the transversal filters TF2a, TF1b, TF2b, TF1c and TF2c in the second stage and thereafter by delaying it by an amount based on the transversal filter TF1a. Thus, it is possible to compose a transversal equalizer with delay units of the specific number of stages and prevent an increase of circuit scale irrespective of the number of taps of the transversal equalizers after the second stage. Further, the case where the number of taps of an equalizing IC is limited as described above. It is however apparent that if an equalizing IC having 320 taps is used, it is sufficient to use the transversal equalizer ICs 30a and 30c only and omit the transversal equalizer IC 30b. Shown in FIGURE 5 is a circuit diagram showing another embodiment of the present invention. In FIGURE 5 the same components as those shown in FIGURE 3 are assigned the same symbols and the explanations are omitted. The transversal equalizer 40 in this embodiment differs from that shown in FIGURE 3 in that a delay unit 41 and a switch 42 have been added. That is, the cascade output of the transversal filter TF2 is applied to:the delay unit 41 and the terminal q of the switch 42. The delay unit 41 operates at a delay of (m-1)T and outputs the delay output to the terminal r of the switch 42. The terminal p of the switch 42 is connected to the output terminal 34 of the transversal equalizer 40. The switch 42 selects the terminal r according to a high level control signal (thereafter referred to as "H") which is input from a control terminal 43 of the transversal equalizer 40,and selects the terminal q according to a low level control signal (thereafter referred to as "L"). In the embodiment of the transversal equalizer composed in such construction as described above, the switch 42 is changed over by a control signal which is input to the control terminal 43. Now, if "H" control signal is applied to the control terminal 43, the switch 42 selects the terminal r. Then, the cascade output of the transversal filter TF2 is delayed by (m-1)T by the delay unit 41 and is output through the output terminal 34 to the input terminal 32. When the output terminal 34 is connected with the input terminal 32, it becomes possible to compose the transversal filter TF2 in cyclic type construction without connecting a delay unit externally. On the other hand, if "L" control signal is applied to the control terminal 43, the switch 42 selects the terminal q. Then, the cascade output of the transversal filter TF2 is directly output through the output terminal 34 to the input terminal 32. In this case, it is possible to give the cascade output to a transversal equalizer in the next stage. Shown in FIGURE 6 is a circuit diagram showing an embodiment of a deghosting apparatus which is composed by connecting this transversal equalizer 40 in series. In FIGURE 6 the same components as those shown in FIGURE 4 are assigned the same symbols and the explanations are omitted. The transversal equalizer ICs 40a, 40b and 40c in the same construction as the transversal equalizer shown in FIGURE 5. In this embodiment the delay unit 36 shown in FIGURE 4 has been omitted and the cascade output from the output terminal 34c of the transversal equalizer IC 40c is output to the output terminal 38 and also, to the input terminals 32a, 31b, 32b, 31c and 32c of the transversal equalizer ICs 40a, 40b and 40c. The control terminals 43a and 43b of the transversal equalizer ICs 40a and 40b are connected to the reference voltage point i.e. to a "L" control signal and "H" control signal is applied to the control terminal 43c of the transversal equalizer IC 40c. In the embodiment of the transversal equalizer as described above, the switch 42 of the transversal equalizer ICs 40a and 40b selects the terminal q and the cascade output of the transversal equalizer ICs 40a and 40b is directly applied to the transversal equalizer ICs 40b and 40c in the next stage. Further, since the switch 42 of the transversal equalizer IC 40c selects the terminal r, the cascade output of the transversal equalizer IC 40c is delayed by (m-1)T and applied to each input terminal. That is, the circuit shown in FIGURE 6 will become the same circuit construction as shown in FIGURE 4. Other operations are the same as those of the embodiment shown in FIGURE 4. Since the transversal equalizer 40 having the delay unit 41 internally is used in this embodiment, it is not necessary to provide a delay unit externally having the advantage that it becomes easy to mount the transversal equalizer on a circuit board. Shown in FIGURE 7 is a circuit diagram showing another embodiment of the present invention. In FIGURE 7 the same components as those shown in FIGURE 6 are assigned with the same symbols and the explanations are omitted. This embodiment differs from the embodiment shown in FIGURE 6 in that signal input to the input terminal 37 is applied to the input terminals 31a and 32a of the transversal equalizer IC 40a, the input terminals 31b and 32b of the transversal equalizer IC 40b and the input terminals 31c and 32c of the transversal equalizer IC 40c. In addition, the cascade output of the transversal equalizer IC 40c is output only to the output terminal 38 without feeding it back, and the control terminals 43a through 43c are connected to the reference potential point in order that the switch 42 selects the terminal q. In the embodiment as described above, the cascade outputs of the transversal equalizer ICs 40a, 40b and 40c are applied to the transversal equalizer ICs inputs 33b, 33c and the output terminal 38 respectively and the transversal equalizer ICs 40a, 40b and 40c are connected in non-cyclic type construction. It is thus possible to avoid an unstable phenomenon that oscillation may be generated on a transversal equalizer in cyclic type construction. Further, the present invention is not limited to the embodiments described above but it is apparent that the cyclic type construction is possible by connecting the transversal equalizer 30 shown in FIGURE 3 in series with the same wiring as the external wiring shown in FIGURE 7 and omitting the delay unit 36. Further, delay amount of the delay units 36 and 41 may be permitted at (m-1)T or less. That is, in this case the operations are carried out repeatedly on the time axis at part of the taps of the cyclic and non-cyclic type transversal equalizers but it is possible to remove ghost images certainly by stopping use of other taps. As described above, the present invention can provide an extremely preferable transversal equalizer.

Claims: A transversal equaliser comprising: (i) a first transversal filter (TF1) comprising: a first input means (31) for receiving a first equaliser input signal; a plurality of multiplier means (M-k -Mm-1), coupled in parallel to the first input means (31), for respectively multiplying the first equaliser input signal by predetermined coefficients (C-k -Cm-1); a plurality of adder means (A-k -Am-1) respectively coupled to outputs of the multiplier means (M-k -Mm-1) for adding the outputs of the multiplier means (M-k -Mm-1); a plurality of delay means (D-k -Dm-1) coupled to outputs of respective adder means (A-k -Am-1) for delaying outputs thereof; a first cascade input means (33) coupled to a first adder means (A-k) of the first transversal filter (TF1) for receiving a cascade equaliser input signal; and a first output means coupled to a last of the delay means of the first transversal filter (Dm-1) for outputting a first output signal; (ii) a second transversal filter (TF2) comprising: a second input means (32) for receiving a second equaliser input signal or the first equaliser input signal; a plurality of multiplier means (Mm -Mn-1), coupled in parallel to the second input means (32), for respectively multiplying the input signal by predetermined coefficients (Cm -Cn-1); a plurality of adder means (Am - An-1) respectively coupled to outputs of the multiplier means (Mm -Mn-1) for adding the outputs of said multiplier means (Mm -Mn-1); a plurality of delay means (Dm -Dn-1) coupled to outputs of respective adder means (Am -An-1) for delaying outputs thereof; and a second cascade input means coupled to a first adder means (Am) of the second transversal filter, the second cascade input means being coupled to the first output means of the first transversal filter; (iii) a second output means coupled to a last delay means (Dn-1) of the second transversal filter for outputting a second output signal; (iv) an equaliser output means for outputting an equalised output signal; (v) a delay means (41) coupled to the second output means, for delaying the signal output from the second output means by a specified time; (vi) a selecting means (42) connected to said delay means (41) and to said second output means, which couples the signal from one of said delay means or said second output means to the equaliser output means. A transversal equaliser as claimed in claim 1 wherein the first transversal filter (TF1) comprises a smaller number of multiplier means than the second transversal filter (TF2). A transversal equaliser as claimed in claim 1 or 2, wherein the selecting means (42) is externally controllable. A transversal equaliser device comprising a first transversal equaliser (40a), as claimed in claim 1, in which the selecting means (42) couples the signal from the second output means to the equaliser output means of the first equaliser, and a second transversal equaliser (40c) as claimed in claim 1 in which the selecting means couples the signal from the delay means (41) to the equaliser output means of the second equaliser, wherein: the signal to be equalised is applied to the first input means (31a) of the first equaliser and the equalised signal is supplied from the equaliser output means of the second equaliser (34c) ; the equaliser output means of the second equaliser (34c) is coupled to the second input means (32a) of the first equaliser (40a) and to the first (31c) and second (32c) input means of the second equaliser (40c); and the equaliser output means of the first equaliser (34a) is coupled to the first cascade input means (33c) of the second equaliser (40c). A transversal equaliser device as claimed in claim 4 comprising at least one further transversal equaliser as claimed in claim 1 in which the selecting means is arranged so as to couple the signal from the second output means to the respective equaliser output means wherein the or each further transversal equaliser is connected in series between the first and second transversal filters, the first cascade input means of the or each further transversal equaliser being connected to the equaliser output means of the preceding equaliser of said first and further equalisers, and the equaliser output means of each of said further transversal filters being connected to the first cascade input means of the succeeding equaliser of said second and further equalisers, wherein the equaliser output means of the second equaliser is coupled to the first and second input means of the or each further transversal equaliser. A transversal equaliser device comprising a first and second transversal equaliser (30a, 30c) each transversal equaliser comprising: first and second transversal filters (TF1, TF2) each filter comprising: an input means (31, 32) for receiving an equaliser input signal; a plurality of multiplier means coupled in parallel with the input means (31, 32) for multiplying the input signal by predetermined coefficients; a plurality of adder means respectively coupled to outputs of the multiplier means for adding the outputs of the multiplier means; a plurality of delay means coupled to the outputs of respective adder means for delaying the outputs thereof; a cascade input means coupled to the respective first adder means; and an output means coupled to the respective last of the delay means; wherein the transversal equaliser device also comprises: a delay means (36), coupled to the output means (34c) of the second filter (TF2c) of said second transversal equaliser (30c); an equaliser input means (37), to which the signal to be equalised is applied; and an equaliser output means (38), coupled to said delay means (36), from which the equalised signal is supplied; wherein the equaliser input means (37) is connected to the input means (31a) of the first filter (TF1a) of the first transversal equaliser (30a); the equaliser output means (38) is connected to the input means (32a) of the second filter (TF2a) of the first transversal equaliser (30a) and to the input means of the first and second filters of the second transversal equaliser (30c); the output means of the first filter (TF1a, TF1c) of each transversal equaliser (30a, 30c) is connected to the cascade input of the second filter (TF2a, TF2c) of the respective equaliser (30a, 30c); and the output means (34a) of the second filter (TF2a) of the first equaliser (30a) is coupled to the cascade input means (33c) of the first filter (TF1c) of the second equaliser (30c). A transversal equaliser device as claimed in claim 6 comprising at least one further transversal equaliser, the or each further equaliser comprising: first and second transversal filters (TF1, TF2), each filter comprising: an input means for receiving an equaliser input signal; a plurality of multiplier means coupled in parallel with the input means for multiplying the input signal by predetermined coefficients; a plurality of adder means respectively coupled to the outputs of the multiplier means for adding the outputs of the multiplier means; a plurality of delay means coupled to the outputs of respective adder means for delaying the outputs thereof; a cascade input means coupled to the respective first adder means; and an output means coupled to the respective last of the delay means; wherein the cascade input of the second filter of the or each further equalisers is connected to the output of the respective first filter, and the or each further transversal equaliser is connected in series between the first and second transversal equaliser, the cascade input of the first filter of the second and further equalisers being connected to the output of the second filter of the preceding one of the first and further equalisers; the output of the second filter of the first and further equalisers is connected to the cascade input of the first filter of the succeeding one of the second and further equalisers; and the equaliser output means is connected to the input means of the first and second filters of the or each further transversal equaliser. A transversal equalizer device comprising at least a first and at least one subsequent transversal equalizer as claimed in claim 1 wherein the selecting means of each of said transversal equalizers couples the signal from the second output means to the equalizer output means of each equalizer, wherein: the signal to be equalized is applied to the first and second input means of the first and subsequent transversal equalizers, the equalizer output means of each transversal filter is applied to the first cascade input means of the preceding one of said first and succeeding transversal filters; and the equalizer signal is supplied from the equalizer output means of the first transversal equalizer.

Inventors: IGA HIROYUKI C O INTELL PROP D, IGA, HIROYUKI, C/O INTELL.PROP.DIV.TOSHIBA CORP.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: H04N5
IPC codes: H03H17, H04L25, H04B3, H04N5, H03H15, H03H21