Apparatus for detecting digital data

Abstract: In an apparatus for detecting input digital data, for example as derived by analog-to-digital conversion (6) of a reproduced binary signal in analog form, the input digital data is distributed into at least two channels, a processing circuit (21,22) in each channel processes the respective digital data in accordance with a predetermined formula (1 + D), a Viterbi decoder (23,24) in each channel decodes an output of the respective processing circuit (21,22) in accordance with the Viterbi algorithm, and the outputs of the decoders (23,24) are combined (25) to provide a single sequence of digital data.

Description: This invention relates to apparatus for detecting digital data, and more particularly but not exclusively, is directed to apparatus for detecting digital data for use in a video tape recorder which uses class IV or other partial response signalling in high density digital tape recording and reproducing. Digital video tape recorders (VTRs) have been developed to record a video signal in the form of a digital signal on a magnetic tape such that deterioration of image quality in the dubbing mode can be minimised. When a signal is recorded on and/or reproduced from a magnetic tape, the electromagnetic transducing system used therefor (such as a magnetic head or the like) has a differentiation characteristic so that the carrier-to-noise (C/N) ratio is degraded at lower frequencies. The C/N ratio will be similarly degraded due to a magnetisation characteristic of the magnetic tape itself, as shown in Figure 1 of the accompanying drawings, if the frequency is increased. Accordingly, when using a magnetic recording and/or reproducing system for a digitised video signal (hereinafter referred to as a digital video signal), the frequency band in which a satisfactory C/N ratio can be obtained is relatively narrow. For this reason, when a digital video signal is to be detected, a detection system is employed having a signal spectrum concentrated near a region in which the C/N ratio is maximised, so as to effectively avoid deterioration of the C/N ratio of the reproduced signal, and thereby ensure that the digital video signal will be recorded and/or reproduced efficiently. In connection with the foregoing, it has been proposed to utilise a class IV partial response scheme in the reproduction and detection of a digital video signal, for example, as disclosed in US Patent Nos. US-A-4 504 872 and US-A-4 984 099 both assigned to the present applicants. More specifically, since the C/N ratio in a magnetic recording and/or reproducing system is degraded at the lower and higher frequencies, its frequency characteristic can be approximated by a frequency characteristic H(ω) of a class IV partial response (1 - D 2 ) scheme expressed by using a delay operator D, as shown in Figure 2 of the accompanying drawings. The Nyquist frequency ω 0 at which the response is minimised has a relation to the delay time T imposed by the delay operator D as expressed in the following equation: ω 0 = π T Accordingly, if the amount of delay imposed by the delay operator D is selected so that the signal spectrum is concentrated near the region in which the C/N ratio is maximised, then the digital video signal can be recorded and/or reproduced efficiently by effectively utilising the frequency characteristic of the magnetic recording and/or reproducing system. In other words, in the recording mode, a calculation process corresponding to the following expression (2) is sequentially performed on the digital video signal: where MOD2 represents the remainder of 2. Further, since the electromagnetic transducing system (for example, a magnetic head) has a differentiation characteristic, a reproduced signal from the magnetic head has a characteristic expressed as (1 - D) with reference to the delay operator D and which is shown by the correspondingly labelled dashed line in Figure 2. Accordingly, in the playback or reproducing mode, a calculation process of (1 + D) is performed on the reproduced signal, whereby the correction expressed by the following equation can be executed: (1 - D) · (1 + D) = 1 - D 2 In view of expression (2) and equation (3), the digital video signal can be reproduced with the transfer function of the recording and reproducing system being substantially maintained at "1". When the digital video signal is recorded and/or reproduced by making effective use of class IV partial response signalling, a digital video signal having a low bit error rate can be reproduced by the application of the Viterbi decoding technique, which indicates that, as shown in Figure 2, the digital video signal can be efficiently detected by effectively utilising a frequency characteristic nearly equal to the characteristic of Figure 1 which represents the frequency characteristic of the magnetic recording and/or reproducing system. As disclosed in detail, for example, in "Analog Viterbi Decoding for High Speed Digital Satellite Channels", A.S. Acampora et al., IEEE Transactions on Communications, Vol. Com. - 26, No. 10, October 1978, pages 1463-1470, and in "The Viterbi Algorithm", G.D. Forney, Jr., Proceedings of the IEEE, Vol. 61, No. 3, March 1973, pages 268-278, a Viterbi decoding circuit utilises the likelihood of correlation between data input successively thereto for detecting transit of the data, and decodes the data on the basis of the detected result. Accordingly, if the relationship (1 - D 2 ) of the reproduced signal relative to the signal used for recording (hereinafter referred to as the recording signal) is utilised to decode the recording signal from the reproduced signal and then the digital video signal is decoded on the basis of the decoded data, the bit error rate of the decoded data can be reduced as compared with a standard decoding circuit which decodes data with reference to the signal level. A previously-proposed reproducing circuit of a digital VTR which incorporates class IV partial response and Viterbi decoding schemes will now be described with reference to Figure 3 of the accompanying drawings in which digital video data recorded as a binary signal in analog form on a video tape 1 is reproduced by a magnetic head 2. The reproduced signal is supplied through an amplifier 3 to an equaliser circuit 4, and the equalised reproduced signal from the equaliser circuit 4 is supplied to a processing circuit 5. The processing circuit 5 performs on this reproduced signal the calculation (1 + D) in accordance with the above-mentioned partial response scheme. The resulting output of the processing circuit 5 is supplied to an analog-to-digital (A/D) converter 6. A reproduced clock is generated from the reproduced signal by a phase-locked loop (PLL) circuit 7 also connected to the output of the amplifier 3. This reproduced clock is supplied to the A/D converter 6 which detects digital data from the reproduced signal level on the basis of the reproduced clock. Detected digital data is supplied to a Viterbi decoder circuit 8, in which the data is decoded in accordance with the Viterbi decoding scheme to provide a detected digital video signal. The detected digital video signal is supplied through an output terminal 9 to a reproduced signal processor circuit (not shown) in a succeeding stage. When the digital video signal is reproduced by the previously-proposed circuit arrangement of Figure 3, the transmission rate of the digital video data is very high so that the clock frequency necessary for processing reproduced data in each of the circuits must be selected to be higher than about 30 MHz. The circuits which are operated at such a high clock frequency require a calculation circuit of a special configuration, which cannot be readily provided in practice. Further, it is preferable that the equaliser circuit 4 and the processing circuit 5 be fabricated as digital circuits because such digital equaliser circuits and digital processing circuits can provide excellent characteristics. However, it is very difficult to operate the equaliser circuit 4 and the processing circuit 5 at any clock frequency higher than about 30 MHz if these circuits 4 and 5 are in digital form. Therefore, in the circuit shown in Figure 3, the equalizer and processing circuits 4 and 5 precede the A/D converter 6 and are not fabricated as digital circuits. Similarly, in the above US Patent No. US-A-4 504 872, the analog-to-digital conversion follows passage of the reproduced signal through a 1 - D 2 class IV response filter so that the latter is not fabricated as a digital circuit and, hence, does not provide the advantageous characteristics inherent in digital fabrication. In IEEE TRANSACTIONS ON COMMUNICATIONS, vol 34, no. 5, May 1986, New York USA, pages 454-461 (R.W. Wood and D. A. Petersen) "Viterbi Detection of Class IV Partial Response on a Magnetic Recording Channel", a technique is disclosed in which data is initially equalised and subjected to a partial response detection scheme. and then subjected to analog to digital conversion; the resulting digital data is split so as to be processed by two Viterbi decoders arranged in parallel. According to the present invention there is provided apparatus for detecting input digital data, the apparatus comprising: processing means for processing the digital data in accordance with a predetermined formula; decoder means for decoding an output of the processing means in accordance with the Viterbi algorithm, the decoder means comprising first and second decoders for odd and even numbered data samples of the digital data; and means for composing outputs of said decoder means to obtain digital data in one sequence; characterised in that: distributing means is provided for distributing said input digital data among first and second channels, respectively for odd and even numbered data samples; and the processing means comprises first and second processors respectively in said first and second channels for processing the respective data samples in accordance with the predetermined formula using both odd and even numbered data samples, the opposite sense data samples for each channel being derived from the other channel via crosswise connections between the channels for combination with the sample being processed in the respective channel. A preferred embodiment of the invention provides an improved apparatus for detecting digital data in which the above-mentioned problems and disadvantages encountered with the previously-proposed systems can be substantially overcome. In the preferred embodiment, when digital data is detected in a digital video tape recorder or the like, the signal processing speed of each of the circuits can be substantially reduced. Also, the circuit arrangement can be simplified so as to be operable by a clock signal of a relatively low frequency. The invention will now be described by way of example with reference to the accompanying drawings, throughout which like parts are referred to by like references, and in which: Figures 1 and 2 are frequency characteristic graphs to which reference is made in explaining a previously-proposed partial response scheme; Figure 3 is a schematic block diagram showing an example of a reproducing circuit of a previously-proposed digital video tape recorder which incorporates a class IV partial response scheme and a Viterbi decoding scheme; Figure 4 is a schematic block diagram showing an apparatus for detecting digital data according to an embodiment of the present invention; Figure 5 (formed of Figures 5A and 5B) is a schematic block diagram showing a specific example of a main portion of the apparatus shown in Figure 4; and Figures 6A to 6C and Figures 7A to 7E are timing charts to which reference is made in explaining the operation of the apparatus shown in Figures 4 and 5. An apparatus for detecting digital data according to an embodiment of the present invention will now be described with reference to Figures 4 and 5, in which parts corresponding to those previously described with reference to Figure 3 are identified by the same reference numerals and therefore will not be again described in detail. In the preferred embodiment, the invention is applied to a reproducing system of a digital video tape recorder (VTR) in which digital data representing a video signal are recorded as a binary signal in analog form on a magnetic tape. This reproducing system is generally arranged as shown in Figure 4, in which the signal reproduced from the magnetic tape 1 by the magnetic head 2 is supplied through the playback amplifier 3 to the A/D converter 6, and digital data is derived from the reproduced signal by the A/D converter 6 on the basis of the reproduced clock signal supplied thereto from the PLL circuit 7. Digital data output from the A/D converter 6 are divided into an odd sequence and an even sequence which are then supplied to respective channels containing equaliser circuits 11 and 12. In this embodiment, each of the equaliser circuits 11 and 12 is formed by a transversal filter. Outputs of the equaliser circuits 11 and 12 are supplied to processing circuits 21 and 22 in the respective channels, which perform the (1 + D) calculation on the outputs of the equaliser circuits 11 and 12, respectively, where D is a delay operator. In the embodiment being described, the processing circuit 21 derives the resulting processed data for the odd sequence and the processing circuit 22 derives the resulting processed data for the even sequence. Outputs of the processing circuits 21 and 22 are supplied to Viterbi decoders 23 and 24, in the respective channels. The Viterbi decoder 23 is operable to Viterbi-decode data of the odd sequence and the Viterbi decoder 24 is operable to Viterbi-decode data of the even sequence. Outputs of the two Viterbi decoders 23 and 24 are supplied to a change-over or composing switch 25. The change-over switch 25 alternately switches the outputs for the odd sequence and the even sequence from the Viterbi decoders 23 and 24 to compose them into data of one sequence, and supplies this data of one sequence to an output terminal 26. Data developed at the output terminal 26 are supplied to a reproduced signal processing circuit (not shown) forming a succeeding stage. A specific circuit arrangement extending from the A/D converter 6 through to the processing circuits 21 and 22 will now be described with reference to Figures 5A and 5B which together constitute Figure 5. In the arrangement of Figure 5, the A/D converter 6 detects digital data from the level of a reproduced signal developed at a terminal 6a on the basis of a reproduced clock signal supplied thereto through a terminal 6b from the PLL circuit 7 (Figure 4). The frequency of the reproduced clock signal supplied to the terminal 6b is selected to be 40 MHz. The output digital data from the A/D converter 6 are supplied to a distributor which includes latch circuits 41 and 42. The latch circuits 41 and 42 latch the digital data on the basis of a clock signal having a frequency of 20 MHz and which is supplied thereto through a terminal 40. The clock signal supplied to the latch circuit 41 and the clock signal supplied to the latch circuit 42 are inverted in phase relative to each other by 180 degrees, so that the latch timings of the latch circuits 41 and 42 are mutually displaced, whereby data of an even sequence is latched by the latch circuit 41 and data of an odd sequence is latched by the latch circuit 42. Data latched by the latch circuit 41 is supplied through a latch circuit 43 functioning as a delay circuit to the equaliser circuits 11 and 12, and data latched by the latch circuit 42 is supplied through latch circuits 44 and 45 arranged in series and also functioning as delay circuits to the equaliser circuits 11 and 12. The 20 MHz clock signal applied to the terminal 40 is also supplied to the latch circuits 43, 44 and 45, so that data are delayed by one clock in each of the latch circuits 43, 44 and 45. In the equaliser circuit 11, output data from the latch circuit 43 is supplied to a series circuit of delay circuits 11a and 11b and output data from the latch circuit 45 is supplied to a delay circuit 11c. Outputs of the delay circuits 11a, 11b and 11c are supplied through respective coefficient multipliers 11d, 11e and 11f to an adder 11g. In the equaliser circuit 12, output data from the latch circuit 43 is supplied to a series circuit of delay circuits 12a and 12b, and output data from the latch circuit 45 is supplied to a series circuit of delay circuits 12c and 12d. Outputs of the delay circuits 12b, 12c and 12d are supplied through respective coefficient multipliers 12e, 12f and 12g to an adder 12h. The coefficient multipliers 11d, 11e and 11f and the coefficient multipliers 12e, 12f and 12g are operative to multiply the respective delayed data supplied thereto by coefficients K 1 , K 2 and K 3 , respectively. Thus, the two equaliser circuits 11 and 12 constitute respective transversal filters and the adders 11g and 12h provide respective equalised signals. By adjusting the coefficients K 1 , K 2 and K 3 employed in the coefficient multipliers 11d, 11e and 11f, and in the coefficient multipliers 12e, 12f and 12g of the equaliser circuits 11 and 12, the equalising level is changed. Each of the delay circuits 11a, 11b, 11c, 12a, 12b, 12c and 12d is formed by a latch circuit which delays an input signal by a delay time of one clock having the frequency of 20 MHz. Outputs of the equaliser circuits 11 and 12 are supplied to the processing circuit 21 which performs the (1 + D) calculation so as to obtain the processed data of the odd sequence. More specifically, the output data of the equaliser circuit 11 is supplied through a series circuit of delay circuits 21a and 21b to one input terminal of an adder 21c, and the output of the equaliser circuit 12 is supplied through a delay circuit 22a to the other input terminal of the adder 21c. An added or sum output of the adder 21c is supplied through a delay circuit 21d to an input terminal 23a of the Viterbi decoder circuit 23 (Figure 4) in the respective channel. In other words, the output of the delay circuit 21d is supplied to the Viterbi decoder circuit 23 which Viterbi-decodes the odd sequence data constituting the output of the processing circuit 21. The outputs of the equaliser circuits 11 and 12 are also supplied to the processing circuit 22 which performs the (1 + D) calculation so as to obtain the processed data of the even sequence. More specifically, the output of the delay circuit 21a in the odd sequence data processing circuit 21 is supplied to one input terminal of an adder 22b, and an output of the delay circuit 22a is supplied to the other input terminal of the adder 22b. An added or sum output of the adder 22b is supplied through a delay circuit 22c to an input terminal 24a of the Viterbi decoder circuit 24 (Figure 4). In other words, the output of the delay circuit 22c is supplied to the Viterbi decoder circuit 24 which Viterbi-decodes the even sequence data constituting the output of the processing circuit 22. Each of the delay circuits 21a, 21b and 21d, and each of the delay circuits 22a and 22c in the processing circuits 21 and 22 respectively, is formed of a latch circuit which delays the input signal supplied thereto by a delay time of one clock period of the clock signal having a frequency of 20 MHz. Operation of the above embodiment of the invention will now be described with reference to Figures 6A to 6C and Figures 7A to 7E. If it is assumed that digital data a 1 , a 2 , a 3 , ..... are output with a sampling frequency of 40 MHz from the A/D converter 6, as shown in Figure 6A, then such digital data will be divided into data a 0 , a 2 , a 4 ....., of even sequence (Figure 6B) and data a -1 , a 1 , a 3 , ..... of odd sequence (Figure 6C). The data shown in Figure 6B represents the output of the latch circuit 43 and the data shown in Figure 6C represents the output of the latch circuit 44. Since the digital data are divided into the even sequence data and the odd sequence data, as described above, the sampling frequency of each of the even or odd sequence data becomes 20 MHz (namely one-half of the sampling frequency of 40 MHz of the original data). Further, by delaying the odd sequence data by means of the latch circuit 44, the even sequence data and the odd sequence data are synchronised with each other. The separated even sequence data and odd sequence data are then supplied to the respective transversal filter or equaliser circuits 11 and 12, thereby generating equalised data EQ which are separately equalised for the odd and even sequences. More specifically, assuming that data EQ 1 , EQ 3 , EQ 5 , ..... obtained at a junction or point e 1 corresponding to the output of the delay circuit 21a, are considered to be the output of the equaliser circuit 11, as shown in Figure 7A, then data EQ 0 , EQ 2 , EQ 4 , ..... are obtained at a point e 2 , corresponding to the output of the delay circuit 22a at the same timing, and may be considered to be the output of the equaliser circuit 12, as shown in Figure 7B. Further, at the same timing, as shown in Figure 7C, data EQ -1 , EQ 1 , EQ 3 , ..... will be obtained at a point e 3 corresponding to the output of the delay circuit 21b. The added or sum output of the adder 21c in the processing circuit 21 is simply the sum of the signals at the points e 2 and e 3 , and hence becomes the data EQ -1 + EQ 0 , EQ 1 + EQ 2 , EQ 3 + EQ 4 , ..... as shown in Figure 7D. This added output is supplied to the Viterbi decoder circuit 23 which decodes the odd sequence data as data processed by (1 + D). Similarly, the added or sum output of the adder 22b in the processing circuit 22 is simply the sum of the signals at the points e 1 and e 2 , and hence becomes the data EQ 1 + EQ 0 , EQ 3 + EQ 2 , EQ 5 + EQ 4 , ..... as shown in Figure 7E. This added output is supplied to the Viterbi decoder circuit 24 which decodes the even sequence data as data processed by (1 + D). The odd sequence and even sequence data are separately decoded by the two Viterbi decoder circuits 23 and 24, and are then composed into data of one sequence by operation of the switch 25. It will be seen that, in the data detecting circuit according to this embodiment of the invention, the reproduced signal is converted into digital data by the A/D converter 6 before being equalised so that the transversal filter or equaliser circuits 11 and 12 and the processing circuits 21 and 22, each of which performs the calculation of (1 + D), can be fabricated as digital circuits. Accordingly, the digital equaliser circuits 11 and 12 and the digital processing circuits 21 and 22 can be provided with stable characteristics which can be adjusted with ease. Further, since the equaliser circuits 11 and 12 and the processing circuits 21 and 22 are arranged in respective channels to divide the data into odd sequence data and even sequence data, the digital signal having a sampling frequency of 40 MHz is equalised using a clock frequency which is one-half the sampling frequency, that is, a clock frequency of 20 MHz, and the (1 + D) calculation or processing is also performed at such reduced frequency. Therefore, a simplified digital data detecting circuit which is operable by a clock signal of relatively low frequency can be employed, that is, there is no need to provide a special circuit which is operated by a clock signal of high frequency. While the reproduced data is divided into data of two channels, that is, odd sequence data and even sequence data in the above described embodiment, it will be appreciated that the reproduced data may be divided into data of three or more channels thereby to further lower the clock frequency. Although the present invention has been described as being applied to the reproducing circuit of a digital VTR, it is not limited thereto and may be applied to other digital devices. Since the above described digital data detecting apparatus employing the partial response scheme and the Viterbi decoding system can be incorporated in a simple circuit operated by a clock signal of relatively low frequency, it will be apparent that the digital data detecting apparatus embodying the present invention can be applied to a consumer digital VTR which, of necessity, is limited in cost.

Claims: Apparatus for detecting input digital data, the apparatus comprising: processing means (21, 22) for processing the digital data in accordance with a predetermined formula (1 + D); decoder means (23, 24) for decoding an output of the processing means (21, 22) in accordance with the Viterbi algorithm, the decoder means (23, 24) comprising first and second decoders (23, 24) for odd and even numbered data samples of the digital data; and means (25) for composing outputs of said decoder means (23, 24) to obtain digital data in one sequence; characterised in that: distributing means (41, 42) is provided for distributing said input digital data among first and second channels, respectively for odd and even numbered data samples; and the processing means comprises first and second processors (21, 22) respectively in said first and second channels for processing the respective data samples in accordance with the predetermined formula (1 + D) using both odd and even numbered data samples, the opposite sense data samples for each channel being derived from the other channel via crosswise connections between the channels for combination with the sample being processed in the respective channel. Apparatus according to claim 1, wherein said predetermined formula (1 + D) is derived from a partial response detection scheme. Apparatus according to claim 2, wherein said partial response detection scheme is a class IV partial response. Apparatus according to claim 1, claim 2 or claim 3, comprising means (6,7) deriving said input digital data from a binary signal of analog form reproduced from a magnetic medium (1) by a magnetic head (2), and wherein said predetermined formula is [1 + D] in which D is a delay operator. Apparatus according to claim 4, wherein said means deriving said input digital data from said reproduced binary signal of analog form includes analog-to-digital converting means (6) having a predetermined sampling frequency, and wherein said distributing means includes first and second latch means (41,42) receiving said input digital data from said converting means (6), means (40) providing a latching signal to said first latch means (41) with a frequency which is one-half said sampling frequency, means inverting said latching signal and applying the inverted latching signal to said second latch means (42) so that said first and second latch means (41,42) are operable to latch odd and even numbered sequences, respectively, of said input digital data, and third latch means (44) in series with said second latch means (42) and also receiving said latching signal for synchronising sequences of digital data applied through said first and third latch means (41,44) to one channel and to the other channel. Apparatus according to any one of claims 1 to 4, comprising means (2,3) for reproducing a binary signal recorded in analog form on a magnetic medium (1), and analog-to-digital converting means (6) for deriving said input digital data from the reproduced binary signal in analog form in advance of said distributing means (41,42). Apparatus according to any one of the preceding claims, comprising equaliser means constituting a transversal filter (11, 12) in each of said channels between said distributing means (41,42) and the processing means (21,22) in the respective channel, each transversal filter (11, 12) using both odd and even numbered data samples, the opposite sense data samples for each channel being derived from the other channel via crosswise connections between the channels. Apparatus according to claim 7 as dependent on claim 5 or claim 6, wherein said analog-to-digital converting means (6) has a predetermined sampling frequency, and wherein said equaliser means (11,12) and said processing means (21,22) in each of said channels is operable by a clock having a frequency which is a fraction of said sampling frequency. Apparatus according to claim 1, claim 2 or claim 3, comprising playback means (2,3) including a magnetic head (2) for reproducing said signal recorded on said magnetic medium (1), and analog-to-digital converter means (6) for converting an output of said playback means (2,3) into digital data in the form of odd and even numbered data samples. Apparatus according to claim 9, comprising equaliser means functioning as a transversal filter (11, 12) in each of said channels between said distributing means (41,42) and the processing means (21,22) in the respective channel, each transversal filter (11, 12) using both odd and even numbered data samples, the opposite sense data samples for each channel being derived from the other channel via crosswise connections between the channels. Apparatus according to claim 10, wherein said analog-to-digital converter means (6) has a predetermined sampling frequency, and wherein said equaliser means (11,12) and said processing means (21,22) in each of said channels is operable by a clock having a frequency which is one-half of said sampling frequency.

Inventors: INOUE HAJIME, KANOTA KEIJI, SEKI TAKAHITO, INOUE, HAJIME, KANOTA, KEIJI, SEKI, TAKAHITO
Applicants: SONY CORP, SONY CORPORATION
Application year: 1991
Main classification: G11B20
IPC codes: H04N5, H03M13, G11B20, H03M5