Cache coherence in logical caches

Abstract: A cache uses A bits of an offset portion which are not subjected to the address translation of the logical address and B bits of the portion other than the offset portion, which are subjected to an address translation. (Fig. 2B) It has an address monitor portion (13) having a tag portion (14) corresponding to the tag portion (12) of the CPU using only A bits of the offset portion of the set address which are used as the set address in the cache and having a 2 B x N-way set associative structure and means for making said tag portion (12) of the cache to correspond to said tag portion (14) of the address monitor portion (13), thereby performing management of N address stored in the tag portion (14) of the address monitor portion and transmitting the result of the management of the address to the cache and for invalidating corresponding recording portion of the tag in the cache.

Description: The present invention relates to a computer system having a logical cache memory and more particularly to means for maintaining consistency, or coherence, between main memory and such a logical cache. To meet recent demand for a high-speed data-processing apparatus, the data access to the main memory must be speeded up. Therefore, a cache memory for copying data from the main memory is provided in the data processing apparatus and the cache is made larger. To raise the performance of the apparatus, increased use has been made of a multi-processor structure with a plurality of micro-processors (MPUs) instead of a single micro-processor, and of a system in which a DMA controller is used to speed up transmission speed between memories. In such systems it is necessary to maintain consistency between the contents of the cache memory or memories and the main memory. To maintain consistency between a logical, or internally-installed, cache memory and the main memory, an address bus monitor, or simply address monitor, is conventionally used. This address monitor observes the system bus to which the main memory is connected. When the other bus master produces a write signal for the main memory, the address monitor reads the address on the system bus and compares it with the contents in a tag memory which forms a part of the logical cache. when the address accords with the content in the tag portion, the corresponding data in the internally-installed cache memory is invalidated. Thus, consistency is maintained between the main memory and the logical cache. As an ordinary program is written using logical addresses, it is necessary to translate the logical addresses into physical addresses so that the program can be operated on actual hardware. This operation is called address translation. The offset portion of the logical address subjected to this address translation is not changed in the physical address and the portion other than the offset portion, referred to as the page number portion, is not the same as that of the physical address when the logical address is translated to the physical address according to the address translation table. When the logical cache is small, as in some conventional data processing apparatus, only the offset portion of the logical address is used as the set address for the logical cache. Since by definition, the offset portions of corresponding logical and physical addresses are the same, the physical addresses on the system bus can be used directly to determine the set addresses of the logical cache. However, when, to satisfy demand for a larger cache, the cache is made larger, the offset portion will become insufficient for the set address, so that a bit or bits from the translated, page number portion of the address must also be used for the set address of the logical cache. When the physical address of the system bus is used as the set address of the cache, there is no problem when the logical address is the same as the physical address. However, the logical address is different from the physical address, there is the problem that the conventional control invalidates a different content of the cache memory and the portion of the cache memory which should be invalidated remains valid. There is in addition the problem of address synonyms or aliasing when the logical cache is an N-way set associative cache. This problem is now described in more detail with the aid of Figures 1A, 1B and 1C of the accompanying drawings. In the following, LA represents a logical address and PA represents a physical address. LA(a:b) represents a bit series from the a-th bit to the b-th bit of the logical address. PA(a:b) represents a bit series from the a-th bit to the b-th bit of the physical address. In this example, both the logical address and the physical address comprise 32 bits. The highest bit is the 31st bit and the lowest bit is 0th bit. The address translation table shown in Figure 1A is provided and correspondence between the logical and physical addresses and the data is as shown in Figure 1B. The data is registered in the cache as shown in Figure 1C in which the tag memory and the cache memory are shown. When PA(31:0) = H'00003000 is provided on a system bus as an address to be address-monitored, and PA(14:4) = H'300 is a set address, PA(31:12) = H'0003 on the system bus is compared with H'0002 stored n the set address H'300 in the tag memory and as they do not coincide, the data stored in the set address H'300 is not subjected to any operation. PA(31:0) = H'00003000, which should be originally invalidated, remains. When the page number portion of the logical address is used as the set address of the cache, the physical address cannot determine the set address to be subjected to the address comparison. Therefore, where the page number portion of the logical address is used as the set address in a cache having a set associative structure, the conventional method cannot maintain consistency between the main memory and the logical cache. A cache multi-processor computer system is known from EP-A-313857 in which the cache set addresses comprise bits from the page number protion of the system address. In this system, in order to counteract synonym problems, synonym control circuits are provided, either in each processor block or centrally in a system controller, which detect the existence of any synonyms in the system subsequent to a buffer miss occurring in a processor block translation lookaside buffer. Any synonyms detected in this way are then invalidated. An object of the present invention is to maintain consistency between a main memory and a logical, internally-installed, cache even when a page number portion of the logical address (i.e. a portion other than the offset portion) is used as the set address of the cache. According to the invention, there is provided a computer system as defined in claim 1. With this design, the logical cache can be made large, contributing greatly to the improved performance of the data processing apparatus. For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, by way of example, to the accompanying drawings, in which:- Figures 1A to 1C are tables of logical and physical addresses together with associated data used to explain the problem to be solved by the present invention, Figures 2A and 2B show a preferred embodiment of the present invention, Figures 3A and 3B are tables showing the correspondence between the address monitor tag way on the one hand and CPU way and page number bit portion of the CPU cache set address (LA 14:12) on the other hand; Figure 4 shows an example of data registration in a cache according to the preferred embodiment; Figure 5 shows an example of address monitoring in a cache according to the preferred embodiment; Figures 6A to 6D show circuit diagrams of the blocks shown in Figures 4 and 5; Figure 7 shows a block diagram for explaining the relation between a TLB and cache according to the preferred embodiment of the present invention; and Figure 8 designates a timing chart of a read operation in the block diagram in Figure 7. In Figure 2A, CPU 10 performs an arithmetic operation and a memory management, for example. The CPU 10 contains a cache memory 11 and an associated tag memory 12. An address monitor 13 is provided for the logical cache and has its own tag memory 14. A main memory apparatus 15 stores a program or data processed by the CPU 10. An external, physical, cache 16 is provided to decrease the load of the system bus. It has a larger capacity than the cache installed in the CPU 10. A data bus 17 and an address bus 18 are connected to the CPU 10. A monitor bus 19 is connected between the CPU 10 and the address monitor 13. The data bus 17 and the address bus 18 are connected to an external data bus 21 and an external address bus 20, respectively, through the external cache 16. The present system comprises a plurality of data processing apparatuses, a main memory apparatus 15, and a system bus comprising an external address bus 20 and an external data bus 21 which interconnect the plurality of data processing apparatuses and the main memory apparatus 15. At least one of the data processing apparatuses comprises a CPU 10, address monitor 13 and external cache 16. The data bus 17 connects the CPU 10 and the external cache 16, and the address bus 18 connects the CPU 10 to the external cache 16 and the address monitor 13. The external address bus 20 connects the main memory apparatus 15 to the address monitor 13 and the external cache 16. The external data bus 21 connects the main memory apparatus 15 to the external cache 16. In this embodiment, the CPU 10 and the address monitor 13 are formed of different chips. The CPU 10 performs an address translation from logical address LA to physical address PA by using the portion other than the offset portion, i.e. the page number portion, as an object of the address translation, as shown in Figure 1B. The cache memory 11 and the tag memory 12 in the CPU 10 use A bits from the offset portion of the logical address and B bits from the page number portion, as shown in Figure 2B, to provide a set address of (A+B)bits. Moreover, the CPU cache 11 and 12 has an N-way set associative structure. The tag memory 12 has an address information recording portion for updating the address of the data stored in the cache memory 11 in the main memory apparatus 15 and a recording portion designating that the data of the cache memory portion 11 is effective, i.e. valid. The address monitor 13 is used for maintaining the consistency of the contents of the cache memory 11 in the CPU 10 and the main memory apparatus 15. The address monitor 13 contains the address monitor tag memory 14, which uses as its set address only the A bits of the offset portion. The address monitor tag memory 14 has a 2 B x N-way set associative structure. That is, 2 B x N regions or "ways" (WAY0 to WAY15) exist in the address monitor tag memory 14. When an A-bit set address is applied to the address monitor tag memory 14, a physical address is read out from a particular one (for example, WAY2) of its 16 ways. This particular way is designated by B+log N when the physical address is written in the address monitor 13. In this embodiment, as the number N of the way is 2, and B comprises 3 bits, for example, B+log N=4 bits and one of 16 ways is selected as described in detail later by referring to Figures 4 and 5. In this data processing apparatus, the tag memory 12 of the CPU 10 is made to correspond to the address monitor tag memory 14 of the address monitor 13. The chip of the address monitor portion 13 performs an address monitor function, thereby sending the result of the monitoring function to the CPU 10, and then invalidating the corresponding recorded data in the tag memory 12 of the CPU 10. In the present embodiment, when the address monitoring is performed as shown in Figure 2A, the physical address of the external address bus 20 is compared with the content of 2 B x N ways of the address monitor tag portion 14 for a set address of A bits. The result of the comparison of the respective ways (2 B x N ways) is converted to B bits of the set address of tag memory 12 in the CPU 10, a way signal and an invalidation enable signal designating whether the invalidation is performed and then is transmitted to the CPU 10. The CPU 10 combines the B bits with the A bits of the offset portion of the physical address on the external address bus 20 which is transmitted through the monitor bus 19 and determines the corresponding address set of the tag portion 12 in the CPU 10 and invalidates a valid bit of the corresponding portion based on the way signal output from the address monitor portion 13, thereby maintaining consistency between the main memory apparatus 15 and the logical cache in the CPU 10. The preferred embodiment is now explained in more detail with reference to Figures 3 to 7 and with the following exemplary structure. (1) The logical address LA has 32 bits, LA(31:0), and the offset portion the 12 least-significant bits thereof, LA (11:0). (2) The block of the logical cache memory in the CPU has 16 bytes. (3) The structure of the logical cache in the CPU is a 2-way set associative structure (N=2). (4) The logical cache memory in the CPU has 32 Kbytes. (5) The tag memory of the address monitor has a 16-way set associative structure and a set address of LA(11:4). According to the above condition 4, LA(14:4) is used as the set address of the cache installed in the CPU. Firstly, the case in which data is registered in the cache is explained by referring to Figures 2A, 2B and 4. The logical address designated by the program is subjected to an address translation and is translated to the physical address, which is output to address bus 18. The CPU 10 receives 16 bytes of data to be registered from the physical cache 16 through the data bus 17. Then, the CPU 10 registers a physical address PA(31:12) (for example, 00003) corresponding to the data registered in the set address (for example, 200) corresponding to the logical address LA(14:4) and in the way (for example, WAY0) designated by the CPU-way selecting circuit 30 with regard to the tag memory 12 in the CPU 10, thereby invalidating the validity bit. In this example, 16 bytes of data are registered in the set portion in the cache memory 11 in the same way as in the tag memory 12. However, this is not directly related to the present invention so its detailed explanation is omitted. At the same time, the above-recited physical address PA(31:12) is registered in the way given by CPU way number + logical address LA(14:12) and in the set address given by the logical address LA(11;4) for the address monitor tag memory 14 of the address monitor 13. Figure 3A is a correspondence table between a signal transmitted from the CPU 10 to the address monitor 13 and the way of the address monitor tag memory 14. The address monitor way selecting circuit 31 controls the way selection in accordance with this table. For example, as shown in Figure 4, suppose that, as a result of the address translation, the logical address is H'00002000 and the physical address is H'00003000. The set address A+B applied to the CPU cache 10 comprises LA(14:4) and can be expressed as 200 in hexadecimal numbers. In this instance, where 200 is used as the set address of the CPU cache 10, and the CPU way selecting circuit 30 designates WAY0, 00003 of PA(31:12), namely, H'000003000 of the physical address is stored at the address 200 of the tag memory 12 and the validity indicating bit is made valid. Simultaneously, the way selection signal (WAY=0) provided by the CPU way selecting circuit 30 and the logical address LA(14:12) = B'010 (which corresponds to B of A+B in Figure 2A) are input to the address monitor way selecting circuit 31 and WAY2 is selected as a way of address monitor tag memory 14 based on the third line of the correspondence table shown in Figure 3A. 00003 is registered at the place designated by logical address LA(11:4), i.e. 00 of LA 200 in Figure 4, i.e., 0 address and WAY 2, and the validity bit is simultaneously made valid. One of 16 ways is selected the number of ways being determined by LA(14:12), i.e., three bits. The number of ways can be generally expressed as 2B. In this manner, the same physical address is registered in the tag memory 12 of the CPU 10 and in the tag memory 14 in the address monitor 13. Next, an operation of the address monitor for performing an invalidation operation of the cache memory is explained by referring to Figure 5. The invalidation of the cache is performed by detecting that PA(31:12) of a physical address produced on the address bus when another one of the CPUs rewrites to the main memory apparatus is stored in the address monitor; by decoding the way number of the address monitor when the physical address (31:12) exists in the address monitor, thereby providing B bits and combining them with the A bits to provide A+B bits; and by invalidating the contents of the cache memory address defined by the A+B bits. First, an external address EA (31:0) H'000030000, i.e., the physical address PA to be monitored, is latched in the external address buffer 40 of the address monitor 13 and the set to be monitored is determined by using (11:4) of EA, i.e., 00 of 3000 of the external address EA, which is the offset portion and is thus equal to the logical address (11:4). Thus, the logical address (11:4) is used to access the address monitor tag memory 14, and the 0 address of the address monitor tag memory 14 is accessed. Then, as shown in Figure 4, the 0 address of the address monitor tag memory 14 outputs 0003 in WAY2, which is written in the address portion 00 in the address monitor tag memory 14. 0003 is physical address (31:12) and is equal to external address EA(31:12). The physical address of respective ways WAY0 - WAY15 registered in address monitor tag memory 14 are respectively compared with (31:12) of the external address EA by the address comparator 41. As a result, if the physical address accords with (31:12) of the external address EA, the circuit 42 for signal translation and invalidation control converts the HIT signal of the WAY2 to the CPU WAY0 and the address monitor logical address LA(14:12), namely B bits, which should be used for the invalidation, in accordance with the third line of the correspondence relation table shown in Figure 3B, and transmits the CPU way and the address monitor logical address to the CPU 10. Only HIT2 of CMP2 selected from among CMP0 to CMP15 becomes 1 and the other HIT signals become 0. When the signal of HIT2 is decoded to provide the B bits (B'110). As the A bits of LA(14:11) already exist, the B bits are connected to the upper side of LA(14:11), thereby providing LA(14:4) to tag memory 12 through selector 9. The circuit 42 also outputs to the CPU 10 the invalidation enable signal 53 (obtained by the logical OR of HIT signals) designating whether the cache should be invalidated or not. The CPU 10 combines the above output (B bits) from the circuit 42 with the external address EA(11:4), namely, address monitor logical access LA(11:4), to provide the set address and access the tag memory 12 by using the set address. The address monitor tag memory 14 has a validity bit, so the address which is hit in the address monitor 13 should always be hit in the CPU 10. Therefore, the validity bit to be accessed by the tag memory 12 of the CPU 10 is invalidated. Comparison with the corresponding portion of the address monitor 13, namely, external address EA, is performed simultaneously. Then, the validity bit of the portion which accords with the external address EA is invalidated. The physical cache 16 shown in Figure 2A performs an address monitor function for itself using physical addresses. If the address 3000 is in the external address bus 20 and the address monitoring operation is required in Figure 5, the external address EA(31:4) is first input and latched in the external address buffer 40. Then, the set address of the address monitor tag memory 14 becomes 00 based on (11:4) of the external address EA. WAY0 - WAY15 designated by the set number is compared with the external address EA(31:12) = 00003 and then HIT2 is asserted. As other HIT lines are not asserted, the invalidation way 54 designating the way of the tag portion 12 in the CPU 10 is determined as WAY0, and the address monitor logical address LA(14:12) = B'010 for the set address in accordance with the correspondence cable shown in Figure 3B. Thus, the invalidation enable signal 53 is also asserted. The external address EA(11:4) is simultaneously transmitted to the CPU 10, and the validity bit of the set address=00 and way=2, which are hit in address monitor tag memory 14, are invalidated. The CPU 10 uses the address transmitted from the address monitor 13 as the set address of the tag memory 12 and receives the invalidation way 54 as the input. The CPU way selecting circuit 30 selects WAY0 to be invalidated and the validity bit control circuit 43 invalidates the validity bit selected by the above set address and the way. Where the external address EA does not accord with the address of the address monitor tag memory 14, the invalidation enable signal 53 is put in a negate state so that the CPU 10 does not perform the invalidation process, but instead performs the ordinary process. The above embodiment uses, as the monitor bus 19, logical address LA(14:4) for the bus from the CPU 10 to the address monitor 13, the CPU way signal 51, the address monitor logic address LA(14:12) for the bus from the address monitor 13 to the CPU 10, the invalidation enable signal 53, the invalidation way 54 and the external address EA(11:4) 55. The comparison signal of the chip of the address monitor 13 may be directly output to the CPU 10 and translated to the logical address on the CPU 10 side. When an address is registered in the address monitor 13, the above embodiment uses address bus 18. However, instead, by increasing the number of lines of the monitor bus 19, the monitor bus 19 can be used for registering the address in the address monitor 13. Figure 6A shows the detailed structure of the address monitor way selecting circuit 31, which comprises a decoder. The selecting circuit 31 comprises inverters and 16 AND circuits 31-0 to 31-15. The logical address 12, 13 and 14 and CPU way are input to each of AND circuit 31-0 to 31-15, which produce address monitor TAG WAY0 to 15, respectively. When addresses 12, 13 and 14, and CPU WAY are at "L" level, "H" is output as TAG WAY0 of the address monitor from AND circuit 31-0. Figure 6B shows a detailed circuit of the CPU way selecting circuit 30. The way selecting signal 54 is input to inverter 30-1 and then 30-2 and the output of the LRU is also provided to inverter 30-3 and then 30-4. The output of inverter 30-2 is put in the enable state by the address monitor signal during the period of the address monitor operation. Thus, the way selecting signal 54 is transmitted to the cache through the CPU way selecting circuit 30 when the address monitor is not being performed, i.e., in ordinary time, and the buffer 34-4 is put in the enable state to transmit the output of the LRU to the cache. Figure 6C shows the detailed structure of the HIT signal to way + LA(14:12) conversion circuit and the invalidation control circuit 42. The conversion and the invalidation control circuit 42 comprises a decoder comprising 16 sets of four buffers. The address monitor hit way 0 signal (HIT0) is input to the gates of buffers 42-11, -12, -13 and -14 and the inputs of these buffers are grounded. Thus, when the HIT 0 signal is made at "L" level, buffers 41-11, -12, -13 and -14 produce "L" level signals of the CPU way signal 54 and logical addresses 14, 13 and 12, respectively, and LA14, 13 and 12 form the signal 52 in Figure 5. In the same manner, the HIT way 1 signal is provided to buffers 42-21, -22, -23 and -24 and the inputs of these buffers are grounded and the input of buffer 42-24 is pulled up. Therefore, when the HIT 1 signal is made at "L" level, the CPU way 54 and logical addresses 14 and 13 are made at "L" level but logical address 12 is made at "H" level. Therefore, by detecting the output of the circuit 42, the HIT signal which is made active can be obtained. HIT 0 to 15 signals are input to OR circuit 42-0 to produce a validity bit signal. When all of the HIT 0 to 15 signals are at "L" level, the invalidation enable signal 53 is inactive. Thus, the validity bit of the cache is not invalidated because the address designated by such physical address is not stored in the cache. Figure 6D shows the detailed structure of the validity bit control circuit 43, in which the ground signal is provided to the validity bit of the cache memory. The invalidation enable signal 53 is transmitted to the selector 9 and tag memory 12 through buffer 43-1. The selector 9 selects the address monitor logical address (14:4) when the output of the validity bit control circuit 43 is active. The AND circuit 12-1 is provided at the output of the decoder 12-2 corresponding to the respective logical addresses (14:4). When one set address of the cache is selected by the logical address (14:4) through the decoder 12-2 and the invalidation enable signal 53 is also made active, the AND circuit 12-1 provides an active output so that the signal (ground signal in the validity bit control circuit 43 is written into the validity bit of the cache register, making the particular address data invalid. Next, the relation between TLB (Translation Lookaside Buffer) and the cache is explained by referring to Figures 7 and 8. Both the TLB and the cache use a 2-way set associative method in this example. When the data is registered in the cache, it is first necessary to cause a cache miss. In this embodiment, as the structure shown in Figure 7 is utilized, the TLB and the tag memory 12 are accessed within one machine cycle. When the logical address 60 and the physical address 61 are accessed by the TLB by using logical address LA (16:12), logical address LA(31:17), which can be translated to a physical address, is registered in logical address portion 60 in TLB. Physical address portion 61 registers physical address PA(31:12) to be obtained by the address translation. Comparison circuit CMP1 compares an actual logical address LA(31:17) with the portion read from WAY0 and WAY1 of the logical address portion 60 of TLB, thereby detecting whether the physical address is registered in TLB. when both hit0 and hit1 are "0", TLB miss is caused, thus moving the process to the dynamic address translation (DAT). Comparison circuit CMP2 compares the WAY0 and WAY1 of the physical address PA(31:12) read from the physical address portion 61 of the TLB with the WAY0 and WAY1 of the physical address PA(31;12) read from the tag memory 12. The output of comparison circuits CMP1 and CMP2 produces hit signal HIT00 - HIT11 designating a hit. In case of HIT00 or HIT10, data of WAY0 read from the cache memory 11 is output and in case of HIT01 or HIT11, the data of WAY1 read from the cache memory 11 is output. There is a case where a plurality of logical addresses LA designate one physical address PA depending on the manner of operation of a program performed by an operating system. In this case, when the logical address LA(14:12) is not the same, the data cannot be mapped in the same physical address. To solve this problem, the following solution is considered. (1) A certain limitation is provided upon forming an address translation table. (2) Upon a TLB miss, the data is not registered in the cache. i) The data is also not registered in the TLB. In this case, the number of DAT increases and the merit achieved by extending the size of the cache becomes suppressed. ii) If the data does not exist in the main memory apparatus, it is registered in the TLB after it is fetched from the bit. Upon a TLB miss, the whole entry of the physical address portion 61 of the TLB shown in Figure 7 is compared with the physical address corresponding to the logical address which causes the TLB miss. When there is no hitting data, the data is registered in the TLB and the process is moved to the next stage and data can be also registered in the cache. If hitting data exists, it is not registered in the cache by validating the NC (non-cacheable) flag of the TLB corresponding to the entry causing the TLB miss when the data is registered in the TLB. In the above method recited in (2), the performance of the apparatus may decrease, thus suppressing the merit achieved by enlarging the size of the cache. Therefore, considering the performance of the apparatus, it is practical to provide a limitation to the address translation table so that, when the logical address LA(14:12) of (1) is not the same, the data cannot be mapped in the same physical address. A solution may be considered, but this is not directly related to the subject of the present invention so its detailed explanation is omitted.

Claims: A computer system comprising a plurality of processors (10, 13, 16, 17, 18) and a main memory (15) interconnected via a system address bus (20) and ; a system data bus (21), each processor having a CPU (10) comprising an N-way set associative logical cache memory (11) with an associated first tag memory (12), the computer system being constructed to operate with logical addresses having an offset portion, which is not subjected to logical-to-physical address translation, and a page number portion, which is subjected to logical-to-physical address translation, the set addresses of the CPU (10) being defined by a first group of one or more bits A taken from the offset portion of the logical address and a second group of one or more bits B taken from the page number portion of the logical address, said set addresses of A+B bits being used to address the logical cache memory (11) and the first tag memory (12) wherein a portion of a physical address to which a corresponding logical address has been translated is stored in said first tag memory, characterised in that each processor comprises an address bus monitor (13) having a second tag memory (14), the address bus monitor (13) being connected to the CPU (10) for communicating with the first tag memory (12) and to the system address bus (20) for monitoring physical addresses on the system address bus, wherein the second tag memory (14) has a set-associative structure with 2 B x N ways, said first group of bits A defining the set addresses in the second tag memory (14) and said second group of bits B in combination with the CPU way number defining the way number in the second tag memory (14), the address bus monitor (13) further comprising: first means (31) operable, when a portion of a first physical address to which a corresponding first logical address has been translated is registered into the first tag memory (12), to make a corresponding registration of said portion of the first physical address into the second tag memory (14) in a way thereof defined by the CPU way number N and said second group of bits B of the first logical address at a set address of A bits of the first logical address; and second means (41, 42) operable, when the address bus monitor (13) detects on the system address bus (20) a write to a second physical address stored in the second tag memory (14), to decode said second group of bits B and the CPU way number N from the hit way of the second tag memory (14), to combine said second group of bits B with said first group of bits A which are available from the offset portion of the second physical address, thus to obtain a second set address A+B, and to invalidate in the CPU (10) the contents of the logical cache memory address defined by the thus obtained second set address A+B and the CPU way number N. A computer system according to claim 1, wherein said second groups of bits B lies next to the offset portion of the logical address. A computer system according to claim 2, wherein said second and first group of bits B and A form a continuous bit sequence in the logical address. A computer system according to claim 1, 2 or 3, wherein there are a plurality of CPU ways N. A computer system according to claim 1, 2 or 3, wherein the number of CPU ways N is 2. A computer system according to any one of the preceding claims, wherein the second group of bits B is formed of 3 bits. A computer system according to any one of the preceding claims, wherein the first group of bits A is formed of 8 bits. A computer system according to any one of the preceding claims, wherein the logical address comprises 32 bits and the offset portion thereof 12 bits. A computer system according to any one of the preceding claims, each processor having a physical cache (16) connected on one side to the CPU (10) and on the other side to the system address and data buses (20, 21) in a manner that bypasses the address bus monitor (13).

Inventors: OHTA HIDENOBU, SATO TAIZO, OHTA, HIDENOBU, SATO, TAIZO, OHTA, HIDENOBU, 301, YOU-CREST, SATO, TAIZO, 205 MAISON-TAKATSU
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1991
Main classification: G06F12
IPC codes: G06F12