Logarithmic amplifier with gain control

Abstract: A logarithmic amplifier includes a first diode (11) wherein the anode receives an input signal current (i IN ) and a standing current (I ST ). The cathode of the first diode (11) is coupled to the emitter of a PNP transistor (14). The collector of the PNP transistor is coupled to the anode of a second diode (15). A bias current (I BIAS ) is added to the emitter and subtracted from the collector of the PNP transistor (14) to provide a lower emitter impedance. The cathode of the second diode (15) is coupled to a negative supply voltage through a load resistor (R C ). A feedback network including an emitter coupled pair of NPN transistors (50, 52) samples the voltage at the anode of the second diode (15) and sinks a current from the base of the PNP transistor (14). The voltage at the anode of the first diode (11) is amplified to provide a logarithmic output voltage (e OUT ). The output voltage may be attenuated (R₂, R₁) and applied to the base of the PNP transistor.

Description: Background of the Invention This invention relates to logarithmic amplifiers, and more particularly, to logarithmic amplifiers wherein the gain is easily changed to accomodate a range of input signal currents. Logarithmic amplifiers are used in applications where there is a need to compress an input having a large dynamic range into an output having a small dynamic range. However, in prior art logarithmic amplifiers, the linear gain factor imposed on the logarithmic output voltage was either a fixed function or not easily changed. From US-A-3,928,774, especially figure 5, it is known to convert an input current into a logarithmic output voltage (V = logI), thereby using four bipolar transistors, two series connected diodes and three operational amplifiers. What is desired is a logarithmic amplifier having an easily changeable gain in order that a range of input signal currents may be accomodated and in order that the dynamic range requirements of linear amplifiers following the logarithmic amplifier may be relaxed. Summary of the invention Therefore, according to the present invention, a logarithmic amplifier comprises a first non-linear element having an input terminal for receiving an input signal current and an output terminal; a first transistor having a first controlled terminal coupled to the output terminal of the first non-linear element, a second controlled terminal and a control terminal; a second non-linear element having an input terminal coupled to the second controlled terminal of the first transistor and an output terminal; a load element having a first terminal coupled to the output terminal of the second non-linear element and a second terminal coupled to a first source of supply voltage; a feedback network having an input terminal coupled to the input terminal of the second non-linear element and an output terminal coupled to the control terminal of the first transistor; and means for amplifying having an input terminal coupled to the input terminal of the first non-linear element and an output terminal for providing a logarithmic output voltage. A feature of the present invention is to provide a logarithmic amplifier wherein the gain is easily adjustable. Another feature of the present invention is to provide a logarithmic amplifier wherein the gain may be optimized to provide a maximum dynamic range of output voltage for a given input current. Yet another feature of the present invention is to provide a logarithmic amplifier that is capable of operating at high frequencies greater than 100Mhz. These and other features of the present invention will be more readily understood by those skilled in the art from a reading of the following detailed specification and drawing figures. Brief Description of the Drawings FIG. 1 is a schematic diagram of a logarithmic amplifier according to the present invention; and FIG. 2 is a plot of the output voltage that is a logarithmic function of the input signal current. Description of the Preferred Embodiment A logarithmic amplifier 10 according to the present invention is shown in the schematic diagram of FIG. 1. The anode of a first diode 11 receives a portion of an input signal current 26, i IN , and a standing or biasing current 24, I ST , at node 62. The portion of the input signal current that flows into the first diode 11 is designated I ₁. Diode 11 is shown as consisting of an ideal diode 12 designated d1 and a parasitic resistance 30 designated R d ₁. A PNP transistor 14 has an emitter coupled to the cathode of the first diode 11. PNP transistor 14 is shown as consisting of an ideal transistor Q ₁ and a parasitic resistance 32 designated R T . A bias current 28 designated I BIAS is added to the standing current 24 at the emitter of PNP transistor 14. The same bias current 28 is subtracted from the collector of PNP transistor 14. The bias current 28 flows only through PNP transistor 14 and is used to decrease the emitter impedance of the transistor. The anode of a second diode 15, shown as ideal diode 16 designated d2 and a parasistic resistance 34 designated R d ₂, is coupled to the collector of PNP transistor 14. A load element, resistor 36 designated R c couples the cathode of the second diode 15 to a -5 volt power supply. A feedback network 22 samples the voltage at the anode of the second diode 15 and compares this voltage to a reference voltage. The output of the feedback network 22 is an error current that is coupled to the base of PNP transistor 14. The means for generating the error current includes NPN transistors 50 and 52 designated Q ₂ and Q₃ . The emitters of NPN transistors 50 and 52 are coupled together and to an emitter current source 58 designated I E through emitter resistors 46 and 48, designated R ₃ and R ₄ to form a differential amplifier. Thus an output error current is formed at the collector of NPN transistor 50 if the voltage at the base of NPN transistor 50 is unequal to the voltage at the base of NPN transistor 52. The voltage at the base of NPN transistor 52 is provided by a reference voltage generator including a bias element, resistor 54 designated R ₅, and a third diode 56 designated d3. The voltage provided by the reference voltage generator tracks the thermal variations in the voltage at the anode of the second diode 15. Therefore the error current at the collector of NPN transistor 50 is only a function of the voltage at the anode of the second diode 15 attributable to the input signal current, i IN . A second current path is established through an input resistor 40 designated R I and a feedback resister 38 designated R f . The current flowing through the input resistor 40 and feedback resistor 38 is designated I ₂. Operational amplifier 18 that is configured to provide a negative gain equal to R f /R I amplifies the voltage at node 62 to provide the output voltage at node 60 designated e OUT . The logarithmic output voltage e OUT is attenuated by an attenuation network 20 and applied to the base of PNP transistor 14. The attenuation network 20 includes a series resistance 44 designated R ₂ and a shunt resistance 42 designated R ₁. For a more thorough understanding of the operation of logarithmic amplifier 10, the following additional voltages are defined: e ₁ is the voltage at node 62, e ₂ is the voltage at the cathode of ideal diode d1, e ₃ is the voltage at the anode of the second diode 15, and e ₄ is the voltage at the base of PNP transistor 14. These voltages, together with previously defined voltages and currents may be used to derive the logarithmic output voltage with respect to a linear input current. Starting with first principles, the diode equation is given by: e=K ln ( I I S +1), where K = nkt / q and I s = saturation current. However, if a standing current is used to bias the diode, the diode equation is modified: e=K ln ( I I S + I ST +1), where I ST = standing current. If I ST » I S , then the diode equation is simply given by: e=K ln ( I I ST +1), Equations [1] and [2] are obtained by inspection of the schematic diagram of FIG. 1: [1] I IN = I 1 + I 2 [2] e 2 = e 4 + I 1 (R d 1 + R T ) Equations [3A] and [3B] are obtained by superposition of the attenuation of the output voltage e out and the voltage produced by the error current from the collector of transistor 50 through the parallel combination of resistors 42 and 44. Thus: [3A] e 4 ≈ e OUT R 1 R 1 + R 2 - e 3 R 1 R 3 + R 4 and [3B] e 4 = e OUT A x - e 3 b , where A x = R 1 R 1 + R 2 and b= R 1 R 3 + R 4 . The voltage at the anode of diode 15, e ₃, and the output voltage, e OUT in terms of e₁ is given by equations [4] and [5]: [4] e 3 = K ln (α I 1 I S2 +1)+α I 1 ( R d2 + R C ) and [5] e OUT = - e 1 R f R I . Substituting equations [4] and [5] into equation [3] gives: [6] e 4 = - e 1 R f A x R I - bK ln(α I 1 I S2 +1)- b α I 1 ( R d2 + R C ) [7] e 2 = - e 1 R f A x R I - bK ln(α I 1 I S2 +1)- b α I 1 ( R d2 + R C )+ I 1 ( R d1 + R T ). Combining terms gives: [8] e 4 = - e 1 R f A x R I - bK ln(α I 1 I S2 +1)+ I 1 ( R d1 + R T - α b ( R d2 + R C )). Adjusting R c such that α b (R d2 + R c ) = R d1 + R T gives: [9] e 2 =- e 1 R f A x R I - bK ln (α I 1 I S2 +1) and [10] e 1 = K ln ( I 1 I S1 +1)- e 1 R f A x R I - bK ln (α I 1 I S2 +1). Note that the correct selection of the value of R c eliminates the parasitic resistance elements R d ₁ , R d2 , and R T . By using a high beta transistor for Q₁, α approaches one. Thus there is minimal error if α is set to one. Assuming I S1 = I S ₂ and combining terms gives: [11] e 1 = (1-b)K ln ( I 1 I S1 +1)- e 1 R f A x R 1 . Solving for e₁ gives: [12] e 1 (1+ R f A x R 1 )=(1- b ) K ln( I 1 I S1 +1), [12A] e 1 = (1- b ) K (1+ R f A x R 1 ) ln( I 1 I S1 +1), or, alternatively: [13] exp e 1 ( R 1 + R f A x (1- b ) KR 1 ) = I 1 I S 1 +1 or [14] I 1 =I S1 (exp e 1 ( R 1 + R f A x (1- b ) KR 1 ) -1). Since e 1 =- e OUT R 1 R f , [15] I 1 =I S1 ( ex p e OUT R f ( R 1 + R f A x (1- b ) KR 1 ) -1). and since I 2 = - e OUT R f , and substituting into [1] then: [16] I IN =I S1 ( ex p e OUT R f ( R 1 + R f A x (1- b ) KR 1 ) -1)- e OUT R f . Equation [16] is the final equation that demonstrates the logarithmic output voltage with respect to a linear input current. It is important to note that the undesirable effect of the parasitic resistance in the diodes and PNP transistor on the logarithmic gain characteristic has been removed. However, this equation is transcendental and the output voltage, e OUT , cannot be written as a direct function of the input current, I IN . Therefore the graphical representation of equation [16] is shown in FIG. 2. Figure 2 is a graph that shows the output voltage as a function of the logarithm of the input signal current. For currents higher than approximately 1 µA, the logarithmic amplifier according to the present invention provides a logarithmic output that is represented by a straight line on the graph. For currents less than 1 µA, the output voltage is a linear function of the input current and is represented by the curved line on the graph. This linear portion of the gain characteristics of the logarithmic amplifier is useful for averaging low level input signal currents to ascertain the signal level as the noise level becomes significant. The gain of the amplifier may be easily changed as can be seen from the form of equation [16]. For example, if high dynamic range is required with low input signal currents, the following component values may be desirable: R ₁ = 150Ω R ₂ = 10 K Ω R f = 300 K Ω R I = 1 K Ω I ST = 1µA As another example, if maximum bandwidth up to 30 Mhz is required for high signal current levels, the following component values may be desirable: R₁ = 150Ω R₂ = ∞ R f = 30KΩ R I = 1KΩ I ST = 50µA Other remaining component values that may be desirable for either example are: I BIAS = 3 mA I E = 6 mA R₃ = R ₄ = 120Ω R₅ = 47 K Ω For optimum frequency performance it is further desirable that Schottky diodes be used for diodes 11 and 15. Under appropriate operating conditions, an alternative embodiment may be used wherein the attenuation factor, A x , is set to zero. This is accomplished by removing resistors R I , R f , R₂, and the operational amplifier 18. In this embodiment, equation [12A] simplifies to: [12B] e 1 = (1-b)K ln ( I 1 I S1 +1), Thus, there has been described and illustrated herein a logarithmic amplifier having a logarithmic characteristic that is not a function of the parasitic resistance of the diodes and transistors used and provides an easily adjustable gain that may be optimized to the level of input current. It will be obvious to those having skill in the art that many changes may be made in the above-described details of the preferred embodiment without departing from the scope of the invention as claimed. For example, the polarity of the transistors may be changed with an appropriate change in polarity of the biasing voltages and currents.

Claims: A logarithmic amplifier comprising: (a) a first non-linear element (11) having an input terminal for receiving an input signal current (26) and an output terminal; (b) a first transistor (14) having a first controlled terminal coupled to the output terminal of the first non-linear element (11), a second controlled terminal and a control terminal; (c) a second non-linear element (15) having an input terminal coupled to the second controlled terminal of the first transistor (14) and an output terminal; (d) a load element (36) having a first terminal coupled to the output terminal of the second non-linear element (15) and a second terminal coupled to a first source of supply voltage; (e) a feedback network (22) having an input terminal coupled to the input terminal of the second non-linear element (15) and an output terminal coupled to the control terminal of the first transistor (14); and (f) means for amplifying having an input terminal coupled to the input terminal of the first non-linear element (11) and an output terminal (60) for providing a logarithmic output voltage. A logarithmic amplifier as in claim 1, wherein the first non-linear element (11) has a parasitic resistance equal to R d1 ; the first transistor (14) has a parasitic resistance equal to R T ; the second non-linear element (15) has a parasitic resistance equal to R d2 ; the load element (36) has a value equal to R C ; the feedback network (22) has a gain from the input terminal to the output terminal with a value equal to b; and wherein the logarithmic output voltage is substantially independent of the R d1 , R d2 , and R T when R C is selected such that (R d2 + R C ) = (R d1 + R T ). A logarithmic amplifier as in claim 1 or 2 further comprising an attenuation network (20) for attenuating the logarithmic output voltage and applying the attenuated voltage to the control terminal of the first transistor (14). A logarithmic amplifier as in claim 3 wherein the attenuation network (20) has an attenuation factor of A X and the logarithmic amplifier has a logarithmic output voltage that is scaled by the factor (1-b) and is inversely scaled by the factor A x . A logarithmic amplifier according to one of the preceding claims further comprising a source of standing current (24) coupled to the input terminal (62) of the first non-linear element (11). A logarithmic amplifier according to one of the preceding claims further comprising a first source of bias current (28) coupled to the first controlled terminal of the first transistor (14) and a second source of bias current (28) having a magnitude equal to the magnitude of the first source of bias current but an opposite direction, the second source of bias current (28) being coupled to the second controlled terminal of the first transistor (14). A logarithmic amplifier according to one of the preceding claims wherein the first and second non-linear elements (11, 15) each comprise a Schottky diode having an anode coupled to the input terminal and a cathode coupled to the output terminal. A logarithmic amplifier according to one of the preceding claims wherein the first transistor (14) comprises a bipolar PNP transistor having an emitter coupled to the first controlled terminal, a base coupled to the control terminal, and an collector coupled to the second controlled terminal. A logarithmic amplifier according to one of the preceding claims wherein the feedback network (22) comprises: (a) a second transistor (50) having a base coupled to the input terminal of the second non-linear element (15), a collector coupled to the control terminal of the first transistor (14), and an emitter; and (b) a third transistor (52) having a base coupled to a reference voltage generator, a collector coupled to a second source of supply voltage, and an emitter coupled to the emitter of the second transistor (50) and to a source of emitter current (58). A logarithmic amplifier as in claim 9 wherein the reference voltage generator comprises: (a) a bias element (54) coupled between the second source of supply voltage and the base of the third transistor (52); and (b) a diode (56) having an anode coupled to the base of the third transistor (52) and a cathode coupled to the first source of supply voltage. A logarithmic amplifier as in claim 9 wherein the feedback network (22) further comprises a first emitter resistor (46) coupled between the emitter of the second transistor (50) and the source of emitter current (58) and a second emitter resistor (48) coupled between the emitter of the third transistor (52) and the source of emitter current (58). A logarithmic amplifier according to one of the preceding claims wherein the means for amplifying comprises: (a) an operational amplifier (18) having a positive input coupled to the second source of supply voltage, a negative input, and an output; (b) an input resistor (40) coupled between the input terminal (62) of the amplifying means and the negative input of the operational amplifier (18); and (c) a feedback resistor (38) coupled between the output terminal (60) of the amplifying means and the negative input of the operational amplifier (18).

Inventors: BATEMAN GLENN, BATEMAN, GLENN
Applicants: TEKTRONIX INC, TEKTRONIX, INC.
Application year: 1991
Main classification: H03G7
IPC codes: G06G7, H03G11