Parabolic voltage generating circuit

Abstract: A parabolic voltage generating circuit includes an arrangement (IC1) for generating a sawtooth vertical deflection current (i V ) that flows in a vertical deflection winding (L V ), in a DC blocking capacitor (C V ) and in a deflection current sampling resistor (R S ). An emitter electrode of a transistor (Q3) is coupled between the deflection winding and the capacitor. A base electrode of the transistor is coupled between the capacitor and the resistance. A collector current (i c ) of the transistor varies in a vertical rate parabolic manner and has a DC average value that is determined by a DC average value of a voltage that is developed in the capacitor. The collector current is applied to an East-West raster distortion correction circuit for modulating an amplitude of a horizontal deflection current.

Description: The invention relates to a circuit for generating a voltage having a parabolic voltage component at a vertical rate. In some prior art vertical deflection circuits of, for example, television receivers, a DC blocking capacitor is coupled between a vertical deflection winding and a deflection current sampling resistor. A vertical rate sawtooth deflection current that flows in the capacitor produces a vertical rate parabolic voltage in the capacitor and a sawtooth voltage in the resistor. The resistor is coupled between the capacitor and a common conductor or ground. The sawtooth voltage is used for providing negative feedback in a vertical deflection circuit amplifier. The DC blocking capacitor prevents a DC voltage that is applied to the vertical deflection winding by the vertical deflection circuit amplifier from producing a large DC current in the vertical deflection winding. In some prior art vertical deflection circuits the parabolic voltage in the capacitor is used for producing a modulating voltage that is referenced to the common conductor. The modulating voltage is used, for example, to modulate an amplitude of a horizontal deflection current in a horizontal deflection winding at a vertical rate parabolic manner for providing East-West raster distortion correction. GB-A-2 150 796 discloses such a vertical deflection circuit. The invention is as set out in Claim 1. The dependent Claims 2-15 relate to embodiments of the invention. In a circuit embodying an aspect of the invention, a transistor is utilized for deriving the modulating voltage from the capacitor voltage such that at least a portion of the sawtooth voltage in the resistor is prevented from affecting the modulating voltage. A DC voltage is developed in the capacitor. In accordance with an inventive feature, the DC voltage in the capacitor is utilized for supplying DC operating voltages between electrodes of the transistor. By utilizing the DC voltage in the capacitor for producing, for example, corresponding DC voltages at an emitter electrode, at a base electrode and at a collector electrode in the transistor, the circuitry associated with the transistor is, advantageously, simplified. Advantageously, a DC collector current in the transistor may be utilized for providing vertical centering. A video apparatus, embodying an aspect of the invention, for controlling a landing of an electron beam on a display screen of a cathode ray tube, includes a source of an input signal at a vertical rate and a vertical deflection winding disposed on the cathode ray tube. An impedance is provided for generating a deflection current indicative voltage. A capacitor is coupled to the deflection winding and the impedance to form a series arrangement. A vertical deflection amplifier is responsive to the input signal and to the deflection current indicative voltage for generating a vertical deflection current that flows in the series arrangement. First and second voltages are developed at the first and second terminals, respectively, of the capacitor that vary at the vertical rate such that a voltage difference between the first and second terminals varies in a parabolic manner at the vertical rate. A transistor has first, second and third terminals. The first and second terminals of the transistor are coupled across the capacitor. An output signal is generated at the third terminal that varies in the parabolic manner in accordance with the voltage difference. A DC voltage is developed between the terminals of the transistor. The DC voltage is coupled to the transistor via at least one of the deflection winding, the first terminal of the capacitor and the second terminal of the capacitor. The output signal is applied to the cathode ray tube to control the landing of the electron beam in a manner that varies upon vertical deflection. The sole FIGURE illustrates a parabolic voltage generating circuit, embodying an aspect of the invention. The sole FIGURE illustrates a modulation voltage generating circuit 102, embodying an aspect of the invention, for generating a voltage V IN containing a vertical rate parabolic voltage component. Voltage V IN is applied to an input terminal 111a of a control stage 111 for generating a voltage V m that contains a vertical rate parabolic component. Voltage V m is applied via a modulation inductor L m1 to a conventional horizontal deflection circuit 100 that includes a diode modulator for correcting East-West raster distortion correction. A baseband television signal 150 obtained from a video detector, not shown in the FIGURE, is coupled to a stage 13 that includes a sync separator. The sync separator generates a signal H S containing a horizontal synchronizing information. Signal H S is applied to a horizontal oscillator and driver stage 14 that produces a horizontal rate control signal 15 for controlling switching operation in circuit 100 that is synchronized to signal H S . Control stage 111 includes a resistor 166 coupled between terminal 111a and a reference voltage V REF . A wiper of resistor 166 is coupled via a resistor 167 to a noninverting input terminal of a comparator 110. The position of the wiper of resistor 166 is adjusted for controlling an amplitude of parabolic voltage V m . An adjustable resistor 67 is used for generating an adjustable DC voltage that is coupled to the noninverting input terminal of comparator 110 to control vertical raster width. A horizontal flyback pulse voltage H FB is coupled from flyback transformer T of circuit 100 via a pulse shaper circuit 120 to a resistor 71. Resistor 71 is coupled to the noninverting input terminal of comparator 110. A capacitor 72 that is coupled to the noninverting input terminal of amplifier 110 develops from voltage H FB a horizontal sawtooth voltage at the noninverting input terminal of amplifier 110. Comparator 110 produces a voltage V₁₁₀ at an output terminal of comparator 110 at the horizontal rate having a pulse width that varies at a vertical rate parabolic manner. Voltage V₁₁₀ is coupled to the base of a switching transistor Q5 that is switched at the horizontal rate. The interval within each horizontal cycle in which transistor Q5 is conductive varies in the vertical rate parabolic manner. The collector of transistor Q5 is coupled via an inductor L m2 to a capacitor 73 where East-West modulating voltage V m is developed. The collector of transistor Q5 is coupled via a diode D4 to a voltage at a magnitude of +26 volts for preventing the collector voltage of transistor Q5 from significantly exceeding +26 volts. Modulation of the conduction interval of transistor Q5 produces a sink current i m in inductor L m2 that causes voltage V m to vary at the vertical rate parabolic manner. Voltage V m provides East-West raster distortion correction in a well known manner. A vertical deflection circuit 101 produces a vertical rate parabolic voltage V P and a sawtooth voltage 22 that are used for generating voltage V IN . In circuit 101 that operates as a Miller feedback arrangement, a supply voltage V is applied to a supply voltage receiving terminal 18a of an integrated circuit (IC) ICI, such as the IC LA7831, manufactured by Sanyo Corporation. Integrated Circuit ICI includes a vertical amplifier 18 having a push-pull driver stage. Amplifier 18 is responsive to an input signal 19 produced in a negative feedback loop at an inverting input terminal 16. An output terminal 17 of amplifier 18 is coupled to one end terminal of a vertical deflection winding L V that conducts a deflection current i v . A second end terminal, a terminal 20, of winding L V is coupled through a DC blocking capacitor C V to a deflection current sampling resistor R S that is coupled to a common potential, referred to herein as ground. During each vertical trace interval trace, sawtooth voltage 22 developed at a terminal 21 across resistor R S is a downramping voltage that changes in a sawtooth manner and that is indicative of the waveform current i v . Resistors R10 and R11 that provide a DC feedback in deflection circuit 101 are coupled in series between terminal 20 and between a terminal 23 of a Miller integrating capacitor C10. A capacitor C11 that provides S-correction is coupled between ground and a junction terminal of resistors R10 and R11. A resistor R12 and a capacitor C12 are coupled in series between a second terminal 24 of capacitor C10 and terminal 21 of resistor R S to provide linearity correction. A resistor R13 is coupled between ground and a junction terminal of resistor R12 and capacitor C12. A diode D3 that provides a fast discharge path for discharging capacitor C10 during vertical retrace is coupled between terminal 24 and a wiper terminal of a resistor R15 to provide vertical size control. Resistor R15 forms with a resistor R16 a series arrangement that is coupled across resistor R S . A pulse generator that is included in stage 13 generates vertical rate signal V RES , in accordance with the corresponding vertical synchronization pulses of signal 150. A transistor switch Q2 operates at a vertical rate in accordance with vertical rate signal V RES . A collector electrode of transistor Q2 is coupled via a resistor R17 to terminal 23 of capacitor C10. The emitter electrode of transistor Q2 if grounded. Resistor R17 controls a discharge rate of capacitor C10 during vertical retrace that is partially discharged when transistor switch Q2 is conductive. A terminal of resistor R17 that is remote from terminal 23 of capacitor C10 is coupled to a noninverting input terminal of a pre-amplifier 26. Preamplifier 26 has an output terminal that is coupled to input terminal 16 of amplifier 18 to complete the negative feedback loop. The feedback arrangement causes vertical amplifier 18 to generate a downramping portion 28 of a vertical sawtooth voltage V v having a DC voltage component or average value of, illustratively, +12.5 volts. Voltage V v produces deflection current i v that flows in winding L v . Vertical current i v develops corresponding sawtooth voltage 22 across resistor R S that is a downramping voltage. Vertical current i v also develops vertical rate parabolic voltage V P across capacitor C V , in a well known manner. Parabolic voltage V P is referenced to terminal 21 where sawtooth voltage 22 is developed. The DC average value of voltage V P that may be, for example, 12.5 volts is produced from the DC voltage component of voltage V v . Terminal 20, that is coupled between capacitor C V and winding L V , is coupled via an emitter resistor 60 to an emitter electrode of a PNP transistor Q3 operating in a common emitter amplifier configuration. In accordance with an aspect of the invention, a voltage V₂₀ that is developed at terminal 20 containing a DC voltage component is DC-coupled to the emitter of transistor Q3. Voltage V₂₀ is also coupled via a DC voltage divider that includes a resistor 61 and a resistor 62 to the base electrode of transistor Q3. Resistor 61 is coupled between the base of transistor Q3 and terminal 20. Terminal 21 is coupled between capacitor C V and resistor R S . Resistor 62 is coupled between the base of transistor Q3 and terminal 21. The collector electrode of transistor Q3 is coupled to ground via a load resistor 64. In accordance with another aspect of the invention, resistors 61 and 62 determine a magnitude of a DC voltage that is developed at the base of transistor Q3 that is derived from voltage V₂₀. The base electrode voltage is selected such that a collector voltage V C is maintained less positive than the base voltage, as required for a linear operation of a PNP transistor. A capacitor 63 having an impedance that is small relative to resistor 61 at the vertical rate is coupled in parallel with the resistor 62. Advantageously, the entire AC parabolic component of voltage V P is substantially developed across emitter resistor 60, between the emitter of transistor Q3 and terminal 20. An AC vertical rate parabolic component of voltage V P produces a vertical rate parabolic component of a collector current i c in transistor Q3 that develops an amplified parabolic voltage component of voltage V C across collector load resistor 64. Voltage V P is developed between terminals 20 and 21. Sawtooth voltage 22 is developed between terminal 21 and ground. A voltage change between terminals 20 and 21 that occurs at a vertical rate parabolic manner produces a current change in collector current i c at a vertical rate parabolic manner. On the other hand, a voltage change at terminal 21 that occurs at a vertical rate sawtooth manner does not produce any change in current i c . Therefore, current i c is unaffected by sawtooth voltage 22. It follows that a first portion of collector voltage V C that is produced from current i c does not contain any sawtooth waveform component. Thus, transistor Q3 generates the first portion of voltage V C having a parabolic waveform that is derived from voltage V P . Voltage V P is referenced to terminal 21 where sawtooth voltage 22 is developed. In contrast, the first portion of voltage V C is, advantageously, referenced to ground and does not contain any sawtooth voltage component. A resistor 66 that is coupled from terminal 21 to the collector of transistor Q3 provides trapezoidal distortion correction by combining sawtooth voltage 22 with the first portion of voltage V C that is parabolic current component of collector current i c of transistor Q3. In this way, a second portion of voltage V C that varies in a sawtooth manner is produced. Because resistors 61 and 62 are coupled to the base of transistor Q3 that forms a high input impedance, values of resistors 61 and 62 can be relatively large. Therefore, advantageously, capacitor 63 that bypasses resistor 62 can have a relatively low capacitance. Using capacitor 63 with low capacitance reduces the cost of capacitor 63. Transistor Q3 derives its emitter, base and collector DC voltages from the DC average voltage of voltage V₂₀ at terminal 20. Advantageously, such arrangement simplifies the circuitry that is required for producing voltage V C from voltage V P . Collector voltage V C of transistor Q3 is coupled via a transistor Q4, operating as an emitter follower, and via a DC blocking capacitor 65 to terminal 111a where vertical rate voltage V IN is generated. As a result, voltage V IN contains a significant vertical rate parabolic component portion that is required for East-West pincushion distortion correction. The collector of transistor Q4 is coupled to terminal 20. A DC current flows through winding L V and through the collectors of transistors Q3 and Q4. In accordance with another inventive feature, the DC collector current through transistors Q3 and Q4 is used for providing vertical centering. Vertical centering may be required when, for example, the vertical retrace time is maintained short.

Claims: A video apparatus for controlling a landing of an electron beam on a display screen of a cathode ray tube, comprising: a source (13) of an input signal (VRES) at a vertical rate; a vertical deflection winding (LV ) disposed on said cathode ray tube; an impedance (RS) for generating thereacross a deflection current indicative voltage (22); a capacitor (CV) coupled in series with said deflection winding and with said impedance to form a series arrangement; a vertical deflection amplifier (26,18) responsive to said input signal and to said deflection current indicative voltage and coupled to said series arrangement for generating a vertical deflection current (iV ) that flows in said series arrangement and that develops first (22) and second (V20) voltages at first (21 ) and second (20) terminals, respectively, of said capacitor that vary at said vertical rate such that a voltage difference (VP) between said first and second terminals varies in a parabolic manner at said vertical rate; characterized by a transistor (Q3) having first and second terminals that are AC coupled across said capacitor for generating at a third terminal (collector) of said transistor an output signal (VC) that is determined in accordance with said voltage difference; means (IC1) ) for developing an energizing DC voltage from the output of said vertical deflection amplifier and applied between a pair of said terminals of said transistor (Q3) and that is coupled to said transistor via at least one (LV) of said deflection winding (LV), said first terminal (21) of said capacitor and said second terminal (20) of said capacitor; and means (111) ) responsive to said output signal (VC) for applying said output signal to said cathode ray tube to control said landing of said electron beam in a manner that varies upon vertical deflection. An apparatus according to Claim 1 characterized in that said impedance comprises a deflection current sampling resistance (R S ). An apparatus according to Claim 2 characterized in that said deflection current flows in said resistance and produces a sawtooth voltage (22) between one (21) of said first and second terminals of said capacitor and a common conductor (ground). An apparatus according to Claim 3 characterized in that a current (i c ) that flows in said transistor does not contain any current component having a sawtooth waveform. An apparatus according to Claim 3 characterized by, means (66) responsive to said sawtooth voltage (22) for combining said sawtooth voltage with said output signal (V C ) to provide a trapezoidal correction. An apparatus according to Claim 1 characterized by, a DC voltage divider (61,62) having an input terminal (top 61) that is coupled to said DC voltage developing means (IC1) and an output terminal (junction 61,62) that is coupled to said one (base) of said terminals of said transistor (Q3). An apparatus according to Claim 6 characterized by, a second capacitor (63) coupled between one (21) of said first and second terminals of the other capacitor and one (base) of said first and second terminals of said transistor (Q3) for AC-coupling said voltage difference (V P ) to said transistor to prevent said voltage divider (61,62) from significantly attenuating an AC component of said voltage difference. An apparatus according to Claim 1 characterized in that a substantial portion of said deflection current flows in each of said capacitor (C V ) and in said impedance (R S ). An apparatus according to Claim 1 characterized in that said transistor (Q3) conducts a DC current (DC component i c ) that flows in said deflection winding to provide vertical centering. An apparatus according to Claim 1 characterized in that said first terminal (emitter) of said transistor (Q3) is coupled between said capacitor (C V ) and said deflection winding (L V ) and said second terminal (base) of said transistor is coupled between said capacitor (C V ) and said impedance (R S ). An apparatus according to Claim 1 characterized in that said electron beam landing control means comprises an East-West raster distortion correction circuit (111) for providing East-West raster distortion correction in accordance with said output signal (V C ). An apparatus according to Claim 1 characterized in that a given amplitude of said voltage difference (V P ) produces a larger amplitude of said output signal (V C ) than produced in said output signal by the same given magnitude of said second voltage (V₂₀). An apparatus according to Claim 1 characterized in that said transistor (Q3) operates in a common emitter amplifier configuration. An apparatus according to Claim 1 characterized in that an amplitude of said output signal (V C ) is affected more by said voltage difference (V P ) than by each of said first (22) and second (V₂₀) voltages, alone. An apparatus according to Claim 14 characterized in that said first voltage (22) is a sawtooth voltage.

Inventors: SMITH LAWRENCE EDWARD, WILBER JAMES ALBERT, SMITH, LAWRENCE EDWARD, WILBER, JAMES ALBERT
Applicants: THOMSON CONSUMER ELECTRONICS, THOMSON CONSUMER ELECTRONICS, INC.
Application year: 1991
Main classification: H04N3
IPC codes: H04N3