Channel selecting circuit

Abstract: The circuit comprises a tuner (12) for converting a high frequency signal with a local oscillating signal controlled by a synchronous voltage, a detector (18) for detecting a difference between the frequency of the intermediate frequency signal and predetermined frequency, a first divider (262, 265) for dividing the local oscillating signal of the tuner (12), a reference oscillator (263) for outputing a reference signal, a second divider (264, 266) for dividing the reference signal from the reference oscillator (263), a phase comparator (268) for comparing the output from the first divider (262, 265) with the output from the second divider (264, 266), a supply circuit (28) for supplying the output from the phase comparator (268) to the tuner (12) as the synchronous voltage, a channel input circuit (24) for inputting a selected channel, and a controller (20) for changing the ratio of the frequency division in the first divider (262, 265) according to the selected channel, wherein the first divider (262, 265) includes two dividers (262, 265) connected serially and a first switch (267) for selecting the output from the divider of the first step or the second step (262, 265); the second divider (264, 266) includes two dividers (264, 266) connected serially and a second switch (269) for selecting the output from the divider of the first step or the second step (264, 266); and the controller (20) connects the first and the second switches (267, 269) to the first step dividers (262, 264) of the first and the second dividers (262, 265, 264, 266), respectively, until the synchronous voltage from the supply circuit (28) becomes stable, and connects the first and the second switches (267, 269) to the second step dividers (265, 266) of the first and the second dividers (262, 265, 264, 266), respectively, during the tuning after the synchronous voltage becomes stable.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of channel selecting circuits for television signal receivers and, in particular, to a frequency synthesis circuit for use in channel selecting circuits which synthesizes a selected channel frequency quickly and efficiently. 2. Description of the Related Art In general, a particular television signal received by an antenna is selected by use of a tuner. The received signal is amplified and detected by a video intermediate frequency (IF) circuit. The output video signal is taken from the video IF circuit and a synchronous voltage is developed to control the selection of a particular broadcast signal. A known circuit for outputting the synchronous control voltage is described below. A PLL (phase locked loop) frequency synthesizer system is adapted for use in a channel selecting circuit of a known color television receiver. The channel selecting circuit using the PLL frequency synthesizer system has a tuner and a PLL circuit which supplies synchronous voltage for controlling a local oscillator of the tuner. The PLL circuit has a prescaler which divides the local oscillating signal supplied from the tuner, a reference oscillator which oscillates a highly accurate signal, a first divider which divides the signal supplied from the prescaler by N, a second divider which divides the signal supplied from the reference oscillator by X, and a phase comparator which compares the phases between the outputs of the first and second dividers. The output from the phase comparator is supplied to the local oscillator of the tuner as a synchronous voltage through a filter circuit for smoothing the phase comparator output. To be precise, the dividing ratios of the prescaler and the second divider are 1/8 and 1/512, respectively. The frequency of the known reference oscillator is 4 MHz. The output frequency fr of the second divider is then 7.8125 kHz (= 4 MHz/512). The dividing ratio of the first divider is varied by control of a microcomputer. A user orders the microcomputer to receive the desired channel through an input unit, typically a remote control. In many instances, the users may select a very high frequency channel after having viewed a very low frequency channel. Known tuning systems are slow to respond to such orders. The microcomputer changes the dividing ratio of the first divider and also changes the locked frequency of the PLL circuit. A local oscillating frequency fosc in the tuner is as follows: fosc = fr.8.N The minimum interval of frequency change is 62.5 kHz (= 7.8125 kHz ·8). Additionally, a television broadcast signal may really be offset to the broadcast standard. This offset is discussed later. The operation of the channel selecting circuit is described below on the condition that the intermediate frequency fo' of the broadcast signal of the received channel is offset from the standard intermediate frequency fo of the channel. Now, if the user selects another desired channel at the time t0, that is, if the dividing ratio N of the first divider is changed by control of the microcomputer, a phase difference occurs as a result of a comparison in the phase comparator. The correction of the synchronous voltage for cancelling the phase difference is carried out every time interval tx by the phase comparator. The time interval tx for the correction is 0.128 msec (= 1/7.8125 kHz), because the output frequency fr of the second divider equals 7.8125 kHz. The synchronous voltage becomes stable after the corrections of the synchronous voltage are done. After the synchronous voltage becomes stable, next, the microcomputer operates a signal retrieval so that the intermediate frequency tunes in the selected one of the broadcast signals. In this case, the minimum interval of frequency change is 62.5 kHz and the intermediate frequency may not converge to the broadcast signal quickly which is at a frequency interval of 62.5 kHz. If the minimum interval of frequency change is inadequate, dividing steps of the first and second dividers have to be increased, e.g. the dividing ratio of the second divider should equal 1/1024 (then, the output frequency fr of the second divider will be 3.90625 kHz). In this case, the minimum interval of frequency change becomes 31.25 kHz. However, as the minimum interval of frequency change is decreased, the time interval for correction of the synchronous voltage increases to 0.256 msec (=1/3.90625 kHz) and the response time becomes longer. That is, when the channel selected is changed, the time t1 until the synchronous voltage becomes stable is longer. When the microcomputer retrieves a real broadcasting signal so that the intermediate frequency f0 tunes in the real intermediate frequency f0' of the broadcasting signal, the response time until the tuning is completed increases too. One previously known channel selection apparatus is disclosed in Patent Abstracts of Japan Vol 3, No. 98 (E-131), 18 August 1979, page 153, and the corresponding JP-A-54-77004. This apparatus enables a channel selection to be stabilised by allowing fine adjustments to be made to the local oscillator frequency. A channel changeover system of a frequency synthesizer is known from Patent Abstracts of Japan Vol 6, No. 81 (E107)(959) May 19 1982 and JP-57-20037 in which the natural frequency of the PLL circuit is increased at the start of channel changeover, whereupon the frequency is made stationary once a rough adjustment is made. "Motorola Technical Developments" page 68 Volume 7, October 1987 discloses a channel selecting circuit comprising a channel input circuit for inputting a selected channel, a tuning circuit, a frequency synthesizer circuit for use in controlling the frequency of a local oscillator of the tuning circuit, and means for detecting the difference between the local oscillator frequency and the actually received intermediate frequency, the frequency synthesizer circuit comprising: a processor and a phase locked loop, which phase locked loop includes a first divider means connected to the local oscillator of the tuning circuit, a reference oscillator, and a second divider means connected to the reference oscillator, the division ratio of each of the first and second divider means being variable under the control of the processor, a phase comparator for comparing the outputs of the first and second divider means, and a supply circuit for supplying the output from the phase comparator to the tuning circuit as a control signal for the local oscillator. Such a circuit is operable by a method comprising the steps of dividing an output of the local oscillator in the tuner by frequency to form a first control signal; dividing an output of a reference oscillator by frequency to form a second control signal; comparing the phases of the first and second control signals; and controlling the frequency of the local oscillator on the basis of the phase comparison. Accordingly, the present invention seeks to provide an improved channel selecting circuit which desirably shortens the response time and minimizes the minimum frequency change interval. According to a first aspect of the present invention, there is provided a channel input circuit for inputting a selected channel, a tuning circuit, a frequency synthesizer circuit for use in controlling the frequency of a local oscillator of the tuning circuit, and means for detecting the difference between the local oscillator frequency and the actually received intermediate frequency, the frequency synthesizer circuit comprising: a processor and a phase locked loop, which phase locked loop includes a first divider means connected to the local oscillator of the tuning circuit, a reference oscillator, and a second divider means connected to the reference oscillator, the division ratio of each of the first and second divider means being variable under the control of the processor, a phase comparator for comparing the outputs of the first and second divider means, and a supply circuit for supplying the output from the phase comparator to the tuning circuit as a control signal for the local oscillator, characterised in that the processor controls the division ratio of the first divider means to select a target channel frequency, in response to a selected channel input by the channel input circuit, until the synchronous control signal from the supply circuit becomes stable wherein the processor subsequently alters the division ratio of the first divider means so as to tune the local oscillator frequency to the actual frequency of the received signal of the selected channel and alters the division ratios of the first and second divider means simultaneously by the same factor when the detecting means detects that the local oscillator frequency will approach the actual signal frequency. According to a second aspect of the present invention, there is provided a method of changing the frequency of a local oscillator of a tuning circuit to match the actual frequency of the incoming signal, comprising the steps of: dividing the frequency of an output of the local oscillator in the tuner to form a first control signal; dividing the frequency of an output of a reference oscillator to form a second control signal; comparing the phases of the first and second control signals; and controlling the frequency of the local oscillator on the basis on the phase comparison; characterised by the steps of, during a frequency jump of the incoming signal to a new frequency, changing the frequency division ratio of the local oscillator output to define a target frequency of the local oscillator, close to the real frequency of the incoming signal; detecting whether the local oscillator frequency has attained the target frequency; and changing the frequency division ratio of the local oscillator output so as to match the frequency of the local oscillator more closely the actual frequency of the incoming signal; determining whether the frequency of the local oscillator will approach the actual signal frequency; and simultaneously changing the frequency division ratios of both the local oscillator output and the reference oscillator output by the same factor when it is determined that the local oscillator frequency will approach the actual signal frequency. A more complete appreciation of the present invention and many of its attendant advantages will be readily obtained by reference to the following detailed description considered in connection with the accompanying drawings, in which: Figure 1 provides a block diagram of a channel selecting circuit according to the present invention. Figure 2 illustrates a characteristic of the AFT signal from the AFT detector of the channel selecting circuit shown in Figure 1. Figure 3 illustrates a change of frequency in a process of channel selecting in the channel selecting circuit shown in Figure 1. Figure 4 is a flow chart illustrating the operation of the data processor shown in Figure 1. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT The preferred embodiment of the present invention will now be described in more detail with reference to the accompanying drawings. Figure 1 is a block diagram of a channel selecting circuit of one embodiment of the invention. An antenna 10 receives a broad band television signal. A tuner 12 is connected to the antenna 10 and has an amplifier 12a, a local oscillator 12b and a mixer 12c. The tuner 12 selects a channel from the broad band television signal. A video intermediate frequency (IF) circuit 14 is connected to the tuner 12. The circuit 14 connected to the output terminal 16 outputs the video signal. The circuit 14 has an AFT (automatic fine tuning) detector 18 which detects the difference between the real video intermediate frequency and the standard frequency. That is, there may exist a case when there is a difference between the real video intermediate frequency and the broadcasting standard (frequency). The AFT detector 18 is used for detecting the difference. The AFT detector 18 is known and the circuit 14 including the AFT detector 18 is supplied by, for example, Toshiba Corporation as an IC whose model number is TA7607. Figure 2 illustrates a characteristic of the AFT signal from the AFT detector of the channel selecting circuit shown in Figure 1. In Figure 2, fO, f0' means a broadcasting standard (intermediate frequency) and the real intermediate frequency of the broadcasting signal, respectively. The AFT voltage is higher than the center voltage Vf0' in response to a center frequency f0' when the intermediate frequency approaches the center frequency f0', from a lower frequency than the frequency fo', by sweeping the local oscillating frequency of the local oscillator 12b. The AFT voltage becomes lower than the center voltage Vf0' when the intermediate frequency passes and becomes higher than the center frequency f0'. The change from higher to lower than Vfo' of the AFT voltage shows the position of the frequency f0', namely the position of offset of the broadcasting signal. A data processor 20 which most conveniently comprises a microcomputer is connected to the circuit 14 through a level detector 22. This level detector 22 converts the analogue AFT signal from the AFT detector 18 of the video IF circuit 14 to a digital signal. The output of the level detector 22 is shown in Figure 2(B), where the threshold level of the level detector 22 is VTH shown in Figure 2(A). An input circuit 24 is connected to the data processor 20 and the input circuit 24 is operated by a user to select the channel. There are a PLL circuit block 26 and a filter circuit 28 between the data processor 20 and the tuner 12. A prescaler 261 of the PLL circuit is connected to the local oscillator 12b of the tuner 12. The dividing ratio of the prescaler 261 is 1/8. A first divider 262 is connected to the prescaler 261. A reference oscillator 263 genarates a 4 MHz signal, which is connected to a second divider 264. A third and a fourth divider 265, 266 are connected to the first and the second dividers 262, 264, respectively. The dividing ratios of the second, third and fourth dividers 264, 265, 266 are set at 1/512, 1/2, and 1/2, respectively. The dividing ratio of the first divider 262 is variable by the data processor 20. Each of the first, second, third and fourth dividers may comprise, for example, a counter. A first switch 267 has two input terminals 267a, 267b which are connected to the first and the third dividers 262, 265, respectively. Its output is connected to one input of a phase comparator 268. A second switch 269 also has two input terminals 269a, 269b which are connected to the second and the fourth dividers 264, 266, respectively. Its output is connected to a second input of the phase comparator 268. These switches 267, 269 are controlled by the data processor 20. The phase comparator 268 is connected to the first and second switches 267, 269. This comparator 268 compares the outputs of the switches 267, 269. A filter circuit 28, which most conveniently comprises a low pass filter, is connected between the phase comparator 268 and a control terminal of the local oscillator 12b of the tuner 12. This filter circuit smooths the output of the phase comparator 268 and obtains a direct current voltage. The operation of the channel selecting circuit is described below by using Figures 3 and 4 on the supposition that another television channel is selected by a user of the input circuit 24 at the time t0, after the circuit has been steadily tuned to another channel with in-phase signals to the comparator 268. The data processor 20 changes the dividing ratio N of the first divider 262 at the time t0. As a result, a phase difference occurs between the phases at the input terminals of the phase comparator 269. On the difference between the two phases, a synchronous voltage response to the designated channel is output from the phase comparator 268. In this time (after time t0), the data processor 20 controls the switches 267, 269 first to select the input terminals 267a, 269a, respectively. The comparator 268 compares the output of the first divider 262 with the output of the second divider 264. The change of the synchronous voltage during the correction process is shown in Figure 3(A). The correction of the synchronous voltage is done every predetermined time interval tx (tx = 0.128 msec = 512/4MHz = 1/7.8125KHz) by the phase comparator 268. This time interval for correction is comparatively short according to the divided outputs from the first and second dividers 262, 264. Namely, the correction is carried out at a high speed for a large interval of frequency change with small dividing steps and the synchronous voltage becomes stable before a time t1 with the local oscillator tuned to the channel broadcasting standard, Fo. The time t1 is, for example, 100 msec, from the time t0. As shown in Figure 3(B), at a time after the synchronous voltage becomes stable (at the time t1' where t1' to t1' is, for example, 200 msec, and is determined with adequate time in relation to the time t1), the data processor 20 changes the dividing ratio N again, this time in response to the AFT signal from the video intermediate frequency circuit 14, and retrieves the broadcasting signal so that the local oscillator 12b tunes in the real broadcast signal. This signal retrieval is shown as a process from time t1' to t5 through t2, t3, t4 in Figure 3(B). From time t1' to t3, switches 267, 269 are connected to the terminals 267a and 269a, respectively, as well as before time t1' (from time t0 to t1'). When the data processor 20 detects, from the change of the AFT signal, that the intermediate frequency will approach the real signal frequency fo' (namely, when the time is at t3), the micro-computer 20 controls the switches 267 and 269 to be connected to the terminals 267b and 269b, respectively. Thus, the correction of the synchronous voltage is carried out at low or a lower speed by a smaller interval of frequency change under the large dividing steps. Namely, from time t3 to t5, the correction of the synchronous voltage is slow; however, the interval of frequency change is small and the intermediate frequency converges closer to the frequency f0'. The locking in to the broadcasting signal is further discussed in greater detail below using the flow chart of Figure 4. The flow chart of Figure 4 begins once there has been a first pass through the PLL circuit 26 and the tuning frequency of the local oscillator 12b is within a range, for example, fo - fo' (Figure 2) or time t1 of Figure 3 is reached. Referring now to Figure 4, after the synchronous voltage becomes stable (time t1' in Figure 3(B)), a mode is set to "P" in step S1. The mode hereinafter means the direction, and the speed in retrieval of the broadcasting signal refers to frequency. Next, the time interval of correction of the synchronous voltage for the retrieval is set. First, a short time interval of correction is set. That is, the switches 267 and 269 are connected to the terminals 267a, 269a, respectively (step S2). The data processor 20 changes the dividing ratio N, when it processes the change selecting step (step S3). The data processor 20 recognizes whether the mode is set to "P" (step S4). If the mode is "P", the data processor 20 recognises whether there are any horizontal synchronous signals retrievable from the incoming television signal (step S5). Horizontal synchronous signals are obtained from the receiving signal when the intermediate frequency f is positioned between fs and fs' (see Figure 2). If some horizontal synchronous signals are detected (that is, a broadcasting signal is captured or received and the horizontal signal is obtained), the data processor 20 recognises whether AFT output is 'H' (high level) (step S6). If AFT output becomes 'L' (low level) by the above process (that is, if the answer is no), the step moves to step S7. That is, the mode is set to "Q". This means that a change of a retrieval direction is accomplished. Thus, in step S8, the new data is calculated for a step up in frequency. In this case, data processor 20 changes the dividing ratio of the divider 262 so as to increase the frequency of local oscillator 12b. In step S5, if there is no synchronous signals detected, the data processor 20 calculates the new data for the step up in frequency which is stepped up by 62.5 kHz (step 8). In step S6, if the AFT output is maintained as 'H' (that is, if the answer is yes), the data processor 20 calculates the new data for the step down in frequency (step S9). In this case, the direction of the frequency change is towards frequency decrease. The data calculated in step S8 or S9 outputs (in step S10) from the data processor 20 to control the divider 262. If the mode was set to "Q" in step S7, in step S4 of the next passage through the flow chart, the output of step S4 moves to step S11 and to step S12 from step S11, because the mode is now "Q". In step S12, the microcomputer judges whether the AFT output is 'H'. If the AFT output is not 'H' (this means that the intermediate frequency is not close to that of broadcasting signal fo'), the flow moves to step S8 mentioned above. If the AFT output is 'H' (this means that the intermediate frequency becomes closer to that of broadcasting signal, fo' from the lower frequency than fo'), the mode is set to mode "R" (step S13). That is, after this point (time t3), the time interval of correction of the synchronous voltage becomes longer (step S14). Then, flow moves to step S15, S16. The data processor 20 calculates a new intermediate frequency which is stepped up by 31.25 kHz (step S15) and outputs data (step S16). That is, the interval of frequency change becomes small. If the mode was set to "R" in step S13, flow moves to step S18 from S4, S11, and S17 in sequence. Then at step S18, the data processor 20 Judges whether the AFT output is 'H'. If the intermediate frequency does not become greater than the intermediate frequency fo' of the real broadcasting signal, the AFT output is maintained as 'H'. Thus, if the answer to step S18 is yes, flow moves to step S15 to increase the intermediate frequency more. If the intermediate frequency becomes greater than the intermediate frequency fo' of the real broadcasting signal, the AFT output decreases (becomes 'L') (see Figure 2). Thus, if the answer to step S18 is no, the mode is set to "S" (to reverse the direction from the mode "R") (step S19). Then, the data processor 20 calculates new data for the next frequency to retrieve (step S20) and outputs data (step S16). If the mode was set to "S" in step S19, the flow moves to step S21 from S4, S11, and S17 in sequence on the next pass through the loop. The data processor 20 Judges whether the AFT output is 'H' (step S21). The AFT output changes to a high voltage when the intermediate frequency reaches the intermediate frequency fo' of the broadcasting signal. If the AFT output becomes 'H', then, frequency retrieval is stopped (step END). If the AFT output does not increase, the data processor 20 calculates a new intermediate frequency which is stepped down by 31.25 kHz (step S20) and outputs data (step S16). Of course, the pass through the loop continues until the "end" step is reached in this case. Thus, there has been shown and described a first phase locking process using a first divide ratio to obtain a first level of locking to a real broadcast signal followed by a second phase locking process using a second divide ratio to obtain a greater degree of locking. While the process is organized into two overall steps, the overall process operates more quickly and efficiently than obtaining lock using only a single divide ratio.

Claims: A channel selecting circuit comprising a channel input circuit (24) for inputting a selected channel, a tuning circuit (12), a frequency synthesizer circuit for use in controlling the frequency of a local oscillator (12b) of the tuning circuit (12), and means (18) for detecting the difference between the local oscillator frequency and the actually received intermediate frequency, the frequency synthesizer circuit comprising: a processor (20) and a phase locked loop (26), which phase locked loop (26) includes a first divider means (262, 265) connected to the local oscillator of the tuning circuit, a reference oscillator (263), and a second divider means (264, 266) connected to the reference oscillator, the division ratio of each of the first and second divider means being variable under the control of the processor (20), a phase comparator (268) for comparing the outputs of the first and second divider means, and a supply circuit (28) for supplying the output from the phase comparator (268) to the tuning circuit (12) as a control signal for the local oscillator, characterised in that the processor controls the division ratio of the first divider means (262, 265) to select a target channel frequency, in response to a selected channel input by the channel input circuit, until the synchronous control signal from the supply circuit (28) becomes stable wherein the processor subsequently alters the division ratio of the first divider means so as to tune the local oscillator frequency to the actual frequency of the received signal of the selected channel and alters the division ratios of the first and second divider means simultaneously by the same factor when the detecting means (18) detects that the local oscillator frequency will approach the actual signal frequency. A channel selecting circuit claimed in claim 1, wherein the supply circuit (28) includes a filter circuit (28) for smoothing the output from the phase comparator (268). A channel selecting circuit as claimed in one of claims 1 or 2, wherein the first divider means (262, 265) includes first and third dividers (262, 265) connected serially and a first switch (267) for selecting the output from the first or third divider (262, 265), the second divider means (264, 266) includes second and fourth dividers (264, 266) connected serially and a second switch (269) for selecting the output from the second or fourth divider (264, 266), the third and fourth dividers having the same division ratio, and wherein the processor (20) connects the first and the second switches (267, 269) either to the first and second dividers, respectively, or to the third and fourth dividers, respectively. A channel selecting circuit as claimed in claim 3, wherein each of the dividers (262, 264, 265, 266) comprises a counter. A channel selecting circuit claimed in any preceding claim, wherein the processor (20) is a microcomputer operated by software. A method of changing the frequency of a local oscillator of a tuning circuit to match the actual frequency of the incoming signal, comprising the steps of: dividing the frequency of an output of the local oscillator (12b) in the tuner to form a first control signal; dividing the frequency of an output of a reference oscillator (263) to form a second control signal; comparing the phases of the first and second control signals; and controlling the frequency of the local oscillator on the basis on the phase comparison; characterised by the steps of, during a frequency jump of the incoming signal to a new frequency, changing the frequency division ratio of the local oscillator output to define a target frequency of the local oscillator, close to the real frequency of the incoming signal; detecting whether the local oscillator frequency has attained the target frequency; and changing the frequency division ratio of the local oscillator output so as to match the frequency of the local oscillator more closely the actual frequency of the incoming signal; determining whether the frequency of the local oscillator will approach the actual signal frequency; and simultaneously changing the frequency division ratios of both the local oscillator output and the reference oscillator output by the same factor when it is determined that the local oscillator frequency will approach the actual signal frequency.

Inventors: SUIZU KATSUTO, SUIZU, KATSUTO,, SUIZU, KATSUTO, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA AVE KK, TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA, TOSHIBA AVE CO., LTD
Application year: 1991
Main classification: H03J5
IPC codes: H04B1, H03J5, H03L7