Process and circuit arrangement for converting analogue read signals into digital signals

Abstract: In the process of a circuit arrangement for converting analogue read signals, which are read by a read head of a storage device on sensing a storage medium, the signals read by the read head are converted into digital signals by amplification and filtering compensation for linear distortion, amplitude control, etc. Thereafter the profile of the processed analogue read signal is sensed and compared with a stored read signal comparison pattern which corresponds to a normal read signal. In the case of agreement, which is given on the presence of a certain correlation, this part of the read signal is evaluated as a read pulse and on non-agreement as a non-pulse.

Description: The invention relates to a process and a circuit arrangement for converting analogue read signals, which are read by a read-head of a storage device sensing a storage medium, into digital signals, wherein the analogue read signals are previously treated. For storing large quantities of data, in mass stores the information is written on to moving magnetic or optical media. In this connection, the data are coded into a series of bits and the series of bits is then "written" by means of a write head in the form of magnetic flux changes on to the medium. For retrieving the information, the data are read by a read-head and decoded by means of a read channel into the original sequence of bits. In this connection, various coding processes are used, such as say the MFM (Modified Frequency Modulation) process, the RLL (Run Length Limited) 1.7 process, the RLL 2.7 process or the like, which have differing storage capacities and transfer rates as a result and which have the common factor that the data are converted into magnetic flux changes. The object of the reading channel consists in so treating the weak reading signals received by the read-head that a subsequent conversion into digital signals/information is possible. In this connection, the signals read by the read-head are customarily first prepared by amplification and filtering, compensation for linear distortion, amplitude control or the like. Thereafter, to determine the signal maximum, the analogue read signal is differentiated and compared in a threshold value detector with a threshold value in order thus to achieve digital information. This still coded digital information is then decoded in a decoder into the original bit sequence. In the known techniques, exceeding a threshold value is used as a criterion as to whether a change in flux has taken place or not. The disadvantages of the known techniques, which show themselves in falsely detected flux changes, then become obvious if the interference level (signal to noise ratio or ratio of the amount of signal to the amount of interference) becomes worse. Since the error rate of data decoding is dependent on the signal to noise ratio, with increasing storage density the criterion of the flux change for high power stores becomes ever more critical. Current stores show on going below around 20 to 26 dB signal to noise ratio an increase in the error rate. These errors can, indeed - within limits - be corrected with error correction procedures. However this requires a substantial expenditure of time in the entire storage system and accordingly reduces the maximum achievable data throughput in comparison to the theoretically possible data throughput. US-4,227,175 discloses a data recognition apparatus which includes a temporary storage to hold three data bits, a readable storage to store eight different sequences which are expected to occur, and a comparison means to find the closest match of the contents of the temporary storage with the readable storage at each bit time. Error detection and error correction are realized as each bit is recognized three times sequentially. The apparatus may use surface acoustic wave and charge coupled device filter banks, and analog to digital conversion plus data processor comparison. In contrast to this, the invention has the object of so improving the process and the circuit arrangement of the above described type that the error rate of data decoding can be maintained small even with a small signal to noise ratio, that is with a poor ratio of the amount of signal to the amount of interference. This object is solved in that the shape of the treated analogue read signal is sensed, compared with a stored read signal comparison pattern, which corresponds to a normal read signal, and on agreement the presence of a certain correlation is given, this part of the read signal is evaluated as a read pulse and on non-agreement this part of the read signal as a non-pulse. The present invention is defined in claims 1 and 6. The dependent claims disclose particular embodiments of the invention. An advantage of the invention consists in that with it a much improved immunity against noise and other interference signals can be achieved. Thereby an improved data security and integrity can be guaranteed. With the invention it is possible to keep the error rate of data decoding small even with a small signal to noise ratio or generally to diminish the error rate so that the actually achieved and theoretically possible data throughput strongly approximate one another. In the invention in contrast to the state of the art in which the exceeding of a threshold value was used as a recognition criteria for the flux change, the signal shape of the read signal is made use of as a criterion for recognising the flux change. If in the known techniques reading signals could be safely determined only down to signal to noise ratios of at minimum 20 dB, then with the invention up to a signal to noise ratio of only 3 dB is possible. Further advantageous embodiments of the invention are described in Claims 2 to 16. Brief Description of The Drawing A more detailed understanding of the invention may be had from the following description of a preferred embodiment, given by way of example and to be understood in conjunction with the accompanying drawing wherein: Fig. 1 the block circuit diagram of a reading channel; Fig. 2 the block circuit diagram of the data correlator in acccordance with the invention; Fig. 3 the circuit diagram of an emodiment of an analog pipeline of the data correlator in acccordance with the invention according to Fig. 2 and Fig. 4 the block circuit diagram of the data correlator according to Fig. 2 in accordance with the invention with nine taps. In the block circuit diagram illustrated in Fig. 1 of a normal read channel, an analogue read signal RD sensed by a reading head is fed to a pre-amplifier 1. Therein the reading signal RD is normally amplified to voltage values in the lower voltage region. The output signal of the pre-amplifier 1 is fed to a low pass filter (TP) 2 which filters out undesired high frequency interference signals. In a compensator 3, linear distortion of the read signal RD, which is phase distorted on account of magnetic phenomena and electric characteristics such as packet running time distortion, are compensated. The output signal of the compensator 3 is fed to a control circuit for amplitude control of the analogue read signal, wherein the control circuit for amplitude control has one after the other a variable amplifier 4, a full wave rectifier 5 and a compensator integrator 6. In this connection, the output signal of the compensator/ integrator 6 is fed back to the variable amplifier 4. Because of errors in the recording medium, the read signal amplitude can vary, which, by means of the control circuit, is so controlled that the automatic amplification control provides at an output signal a constant amplitude analogue signal A, which is fed to a differentiator 7. In differentiator 7, the analogue read signal is differentiated to determine the signal maximum, whereon at the output of the differentiator 7, the processed analogue read signal RD* and the differentiated read signal RD' are present. In a data detector 8, the differentiated analogue read signal RD' and optionally also the treated analogue read signal RD* are compared with a threshold value and converted into a digital signal/information. In this connection, the presence of a signal is interpreted as a logical "1" and the remainder or "no signal" as a logical "0". This digital signal is then decoded in a decoder 9, in the example illustrated into NRZ (non-return-to-zero) data, which correspond to the original sequence of bits. In the process according to the invention or in the circuit arrangement in accordance with the invention, in place of the differentiator 7 and the data detector 8, a data correlator 10 is used, the block circuit diagram of which is illustrated in Fig. 2. The data correlator 10 has an analogue pipeline 11, a correlator 12 and a curve shape store 13, which is connected to a microprocessor 14. In the case of the analogue pipeline 11, this is an analogue short period store to which the output signal A (compare Fig. 1) of the control circuit for amplitude control is fed. The object of analogue pipeline 11 consists in the short period storage of an analogue read signal and for collimating this signal. The function is thus similar to a shift register with serial input and parallel output with the exception that the process is continuous and requires no clock. The actual read signal continuously flows through the analogue short period store. The analogue pipeline 11 has at equal time delay distances n taps, which in the following are simply called taps. At these taps, the signal condition can be simultaneously taken off at various points in time. The number of taps determines the accuracy and quality of the correlation or of the entire system. The total length of the analogue pipeline should preferably have the width of one read impulse, which normally lies in the region of 10s of nanoseconds. As analogue pipeline, there can be used, for example, a transmission line on which the signal is delayed. Thus, for example, there amounts with a 50 Ohm coax cable a delay of around 5 nsec/m. As analogue pipeline, however, there can also be used a delay line which consists essentially of an inductance with distributed capacity, as is illustrated in Fig. 3. This delay line has end taps and a capacitative layer on which forms a plurality of capacitors, of which one electrode in each case is earthed and the other electrode of which is connected in each case with the delay line. Thereby the delay line has a distributed capacity C' and a distributed inductance L'. The delay line is continuously fed with the input signal RD and it can be simultaneously taken off at various points in time at the end taps. With such delay lines currently delays of ≤ 100 picoseconds to 1 microsecond are achieved. As analogue pipeline, also other analogous short period signal stores can be used, such as, for example, amplifier stages, which, determined by capacitances and cutout behaviour of transistors likewise have a delay time, so that by a corresponding number of amplifier stages, a similar short period signal store can be achieved. The data correlator in accordance with the invention is now described in more detail with reference to the block circuit diagram illustrated in Fig. 4. In this embodiment, the analogue pipeline 11 has n = 9 taps, on which the signals R1 to R9 are taken off. The correlator 12 has, in the embodiment illustrated in Fig. 4, seven adders 21 to 27 as well as dividers 31 to 33, a comparator 34, and dividers 35 to 37. In this connection, it is, in each case, a question of analogue calculation functions which can be implemented by corresponding switches. The curve shape store 13 has seven stores 41 to 47. As already explained above, the analogue pipeline 11 has nine tappings or taps at which, in each case, the signals R1 to R9 are taken off. The signal R1 is fed to the first input of the adder 21 and the signal R2 to the first input of the adder 22. The signal R3 is fed to the second input of adder 21 and the first input of adder 23. The signal R4 is fed to the second input of adder 22 and the first input of adder 24. The signal R5 is fed to the second input of adder 23, the second input of adder 24 and the first input of adder 25. The signal R6 is fed to the third input of adder 24 and the first input of adder 26. The signal R7 is fed to the second input of adder 25 and the first input of adder 27. The signal R8 is fed to the second input of adder 26 and the signal R9 to the second input of adder 27. The output signal S1 present at adder 21 is fed to the divider 31, the signal S2 at the output of adder 22 to the divider 32 and the signal S3 present at the output of adder 23 to the divider 33. The signal S4 present at the output of adder 24 is fed to the comparator 34. The signal S5 present at the output of adder 25 is fed to the divider 35, the signal S6 present at the output of adder 26 is fed to the divider 36 and the signal S7 present at the output of adder 27 is fed to the divider 37. As already explained above, the curve shape store 13 has stores 41 to 47. The curve shape store 13 stores the time collimated image of a typical read signal in the form of analogue voltage values, which are fed to the stores 41 to 47 from a microprocessor 14. The signal M1 present at the output of the store 41 is fed to the divider 31, the signal M2 present at the output of store 42 is fed to the divider 32, the signal M3 present at the output of store 43 is fed to the divider 33, the signal M4 present at the output of store 44 is fed to the comparator 34, the signal M5 present at the output of store 45 is fed to divider 35, the signal M6 present at the output of store 46 is fed to the divider 36 and the signal M7 present at the output of store 7 is fed to the divider 37, as is evident from Fig. 4. The correlator 10 has the object of comparing the actual read signal A fed continuously into the analogue pipeline 11 with a stored pattern. In order to minimise the amplitude dependence of the actual read signal, the comparison is divided up into three regions "rising", "maximum" and "falling". For this purpose, stores 41 to 43 contain the rise comparison values M1, M2 and M3 of the "rise" region, the store 44, the average maximum of amplitude M4 of the comparison pattern read signal, and the stores 45 to 47 the slope comparison values M5 to M7 of the "falling" region. For calculating the correlation in the "rising" region, the signals R1 to R5 taken off from the analogue pipeline 11 and the signals M1 to M3 present at the output of stores 41 to 43 are used. In the functional blocks, adder 21, adder 22 and adder 23 for calculating the rise of the read signal the differences are formed by the following equation S i = R i+2 - R i wherein i runs from 1 to 3 and the intermediate result Si (S1, S2, S3) lies, in each case, at the adders 21, 22 or 23 respectively. This means that at the output of adder 21, the intermediate result S1 = R3 - R1, at the output of adder 22 the intermediate result S2 = R4 - R2 and at the output of the adder 23 intermediate result S3 = R5 - R3. Then in the divider 31, divider 32 and divider 33, the individual correlations are formed according to the following formula wherein i runs from 1 to 3 and Q i represents the output signals Q 1 , Q 2 or Q 3 present at the dividers 31 to 33 and the signals M1, M2 and M3 provided by the source 41 to 43 rise comparison values of a typical read signal. The calculation of the correlation in the "maximum" region takes place by a comparison of the signals R4, R5 and R6 with the signal M4 provided from store 44. In the functional block adder 24, the arithmetic mean of the expected peak amplitude of the actual reading signal as an intermediate result S4 is determined according to the following formula: Then in comparator 34, the intermediate result S4 is compared with the signal M4 provided from store 44 according to the following equation to determine the individual correlation: wherein the individual correlation Q 4 represents the starting signal for the comparator 34. The parameter c lies with 9 taps according to experience in the region 0.4 ≤ c ≤ 0.6 The parameter c must be changed with a higher number of taps correspondingly. With the exception of the sign, the calculation of the correlation in the "falling" region takes place in the same sense as in the "rising" region by comparison of the signals R5 to R9 with the signals M5, M6, M7. Thus in the function blocks adder 25, adder 26 and adder 27 the differences for calculating the gradients of the read signal according to equation (1), wherein i runs from 5 to 7 are formed. As an intermediate result at the output of the adder 25, the signal S5 = R7 - R5, at the output of the adder 26, the signal S6 = R8 - R6 and at the output of the adder 27, the signal S7 = R9 - R7 is formed. Then, as in the "rising" region, in divider 35 the output signal Q5, in divider 36 the output signal Q6 and in divider 37 the output signal Q7 is formed in accordance with equation (2), wherein i runs from 5 to 7. The output signals Q1 to Q7 are fed to an adder 28 which at its output D determines the overall correlation factor CORR as the arithmetic mean of the individual correlations Qi according to the following formula: with n=9 in the example illustrated in Fig. 4. The entire correlation factor CORR is fed for digitisation to the threshold value detector 15. The entire correlation factor in which at the output of the threshold value detector 15 a logical "1" is present, depends on the system requirements, in each case depending upon what interference distance the system should allow. Should, e.g. also a smaller interference distance be omitted, then the overall correlation factor CORR, which determines whether at the output of the threshold value detector 15 there is present a logical "1" is chosen correspondingly high, e.g. at 0.8. Because to the curve shape store 13 the time collimated image of typical read impulses are fed in the form of analogue voltage comparison values or gradient comparison values from the microprocessor 14, it is also possible to use adaptive techniques in order to achieve optimum efficiency. Thus it is, e.g. possible by iterative algorithms to determine the optimum comparison pattern for the curve shape store 13 in an individual system of test traces on a storage medium automatically. Thus, in particular, also the values illustrating the ideal curve shape stored in the curve shape store 13 can be matched to the individual characterising data of the respective read head or storage medium. For storing the quasi static signal Mi (M1 to M7) suited for stores 41 to 47 are, in particular, digital/analogue (D/A) converters. In this connection, the voltage values or gradient comparison values are written by the microprocessor 14 into the D/A converter and can, if appropriate, also be modified by this for the purpose of optimisation. Advantageous embodiments of the invention are possible without more ado for the man skilled in the art. Thus, e.g. an acceleration of the data throughput can be achieved in that the read signals are worked on in parallel and for this multiple curve shape stores are used.

Claims: Process for converting analog signals corresponding to individual bits into digital signals, said analog signals having been read by a read-head of a storage device on sensing a storage medium, wherein the analog read signals have discernable shapes and have been previously processed before conversion, said conversion process comprising the steps of sensing the shape of the processed analog read signal, correlating it with a stored analog signal reference pattern which corresponds to a reference signal, and on agreement, which is given on the presence of a particular correlation result, evaluating the correlation result of the analog signal as a read pulse, and on non-agreement evaluating the correlation result of the read signal as a non-pulse, wherein the read pulse is evaluated as logical "1" and the non-pulse as logical "0", further comprising the steps off dividing the signal reference pattern into a plurality of sections, and storing a value per section characterizing the signal reference pattern, causing the read signals to run continuously through a short period signal store divided into a plurality of sections, thereby causing the read signal pattern to distributedly show up along those sections, deriving the voltage value of the read signal at each section from the short period signal store and correlating it section by section with the coresponding read signal reference pattern, wherein the correlation is divided into three regions,namely into a "rising" region, in which the signal reference pattern rises, into a "maximum" region in which the signal reference pattern has a maximum and into a "falling" region in which the signal reference pattern is falling, that in the "rising" region and in the "falling" region an intermediate value (S i ) is calculated by the voltage value (R i ) taken off at each respective section of the short period signal store being subtracted from that of the next but one section, and the correlation factor (Q i ) of the respective section is calculated by means of correlation with the corresponding value (M i ) of the signal reference pattern according to the following equation: that in the "maximum" region for calculating an intermediate value (S j ) is calculated by the arithmetic mean being formed of the voltage values (R j ) taken off in the centre sections of the short period signal store, and the correlation factor (Q j ) is calculated by correlation with the value (M j ) weighted by the number of sections of the signal reference pattern according to the following equation: wherein c is chosen corresponding to the number (n) of the sections of the short period signal store; that the total correlation factor (CORR) is determined as the arithmetic mean of the individual correlations (Q i , Q j ), and that for a given total correlation factor (CORR) a read impulse or a logical "1" is emitted from a threshold value detector. Process according of Claim 1, characterized in that the correlation condition is adjusted correspondingly to the permitted signal to noise ratio (ratio of signal amount to amount of interference). Process according to one of Claims 1 to 2, characterized in that the values (M i , M j ) are characterizing the signal reference pattern and are stored in sections in the storage provided by a microprocessor. Process according to Claim 3, characterized in that the values characterising the signal reference pattern are matched by means of the microprocessor to the individual system consisting of read head and storage medium. Process according to one of Claims 1 to 4, characterized in that on parallel working of a plurality of read signals, a corresponding plurality of signal reference pattern stores are used. Circuit arrangement for converting analogue signals corresponding to individual bits which are read by a read head of a storage device on sensing a storage medium into digital signals, with a device for processing the analogue read signals and a decoder for decoding the signals/data into a sequence of bits corresponding to the stored sequence of bits, characterized in that the circuit arrangement comprises: a data correlator (10) which includes a short period signal store (11) in which the treated analogue read signal is stored, and a curve shape storage (13) in which a analog signal reference pattern corresponding to a reference signal is stored, and a correlator (12) which generates a correlation between the processed analogue read signal and the analog signal reference pattern, as well as a threshold value detector (15) which emits a read pulse on the presence of a particular correlation, wherein the read pulse is evaluated as logical "1" and the non-pulse as logical "0", further comprising means for dividing the signal reference pattern into a plurality of sections, and storing a value per section characterizing the signal reference pattern, causing the read signals to run continuously through a short period signal store divided into a plurality of sections, thereby causing the read signal pattern to distributedly show up along those sections, deriving the voltage value of the read signal at each section from the short period signal store and correlating it section by section with the coresponding read signal reference pattern, wherein the correlation is divided into three regions, namely into a "rising" region, in which the signal reference pattern rises, into a "maximum" region in which the signal reference pattern has a maximum and into a "falling" region in which the signal reference pattern is falling, that in the "rising" region and in the "falling" region an intermediate value (S i ) is calculated by the voltage value (R i ) taken off at each respective section of the short period signal store being subtracted from that of the next but one section, and the correlation factor (Q i ) of the respective section is calculated by means of correlation with the corresponding value (M i ) of the signal reference pattern according to the following equation: that in the "maximum" region for calculating an intermediate value (S j ) is calculated by the arithmetic mean being formed of the voltage values (R j ) taken off in the centre sections of the short period signal store, and the correlation factor (Q j ) is calculated by correlation with the value (M j ) weighted by the number of sections of the signal reference pattern according to the following equation: wherein c is chosen corresponding to the number (n) of the sections of the short period signal store; that the total correlation factor (CORR) is determined as the arithmetic mean of the individual correlations (Q i , Q j ), and that for a given total correlation factor (CORR) a read impulse or a logical "1" is emitted from a threshold value detector. Circuit arrangement according to claim 6, characterized in that the short period signal store is an analogue pipeline (11). Circuit arrangement according to Claim ,7 characterized in that the analogue pipeline is a transmission line. Circuit arrangement according to Claim 7, characterized in that the analogue pipeline is a delay line. Circuit arrangement according to Claim 7, characterized in that the analogue pipeline is constructed from a series of amplifier stages. Circuit arrangement according to one of Claims 6 to 10, characterized in that the short period signal store (11) has at even distances a plurality of tappings (taps) at which the analogue read signal can be continuously extracted in sections, that the curve shape storage is divided up into a plurality of individual storages, in which, in each of them, a value characterizing one section of the signal reference pattern is stored and that the correlator (12) is divided into a plurality of correlators which can carry out a sectionwise correlation between the analogue read signal and the signal reference pattern. Circuit arrangement according to one of Claims 6 to 11, characterized in that the curve shape storage (13) is connected to a microprocessor (14) which feeds the signal reference pattern to the curve shape storage (13). Circuit arrangement according to Claim 12, characterized in that the signal reference pattern fed by the microprocessor (14) to the curve shape storage (13) is matched to the individual characteristics of the respective read head or storage medium respectively.

Inventors: SADOWSKI SIEGBERT, SADOWSKI, SIEGBERT
Applicants: DIGITAL EQUIPMENT INT, DIGITAL EQUIPMENT INTERNATIONAL GMBH
Application year: 1991
Main classification: G11B20
IPC codes: H03M1, G11B20, H03H17, H03H15