Vertical type semiconductor device

Abstract: A vertical type semiconductor device capable of greatly decreasing the on-resistance without impairing the breakdown voltage of the element. In the fundamental DMOS cells 2 that control the current to constitute the vertical semiconductor device, through hole cells 3 are arranged along the sides of the cell that form a channel 21. The through hole cell 3 has a through hole 23 extending from the surface of an n⁻-type drift region toward an n⁺-type drain region 12, and has an n⁺-type through hole region 25 that is formed by diffusing impurities from the inner wall of the through hole 23 and that is continuous to the n⁺-type drain region 12. A breakdown voltage of the element is maintained by the n⁻-type drift region 11 between a p-type well region 13 and the n⁺-type through hole region 25 or the n⁺-type drain region 12. Owing to the disposition of the through hole cells 3, the JFET resistance component becomes negligibly small between the DMOS cells 2 neighboring along the sides of the cells despite the fact that the cells are finely formed, and a small on-resistance is exhibited.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical type semiconductor device, such as a vertical type power MOSFET, particularly for decreasing on-resistance. 2. Description of the Related Art The conventional vertical type power MOSFETs have in many cases been constructed as shown in Fig. 3 (e.g., see Japanese Unexamined Patent Publication (Kokai) No. 63-254769 or US patent no. 4,366,495). When the channel conduction type is of the n type in this structure, a p-type well 13 is formed on the surface of a semiconductor substrate 11 in which the elements will be formed, and n-type source regions 14 of a high concentration are formed in the well 13. An n⁺-type drain region 12 of high concentration is formed maintaining a predetermined depth depending upon the breakdown voltage of the elements. The portion 11 sandwiched between the well 13 and the n⁺-type drain region 12 is called n-type drift region having a relatively low concentration. The breakdown voltage between the drain and source of this element is determined by the thickness of the drift region 11, the impurity concentration, and a thickness and a concentration are selected to satisfy the desired breakdown voltage. When a voltage is applied to a gate 17 disposed over the well 13, an n-type inverted layer is formed on the surface of the semiconductor substrate in the well 13, and an electric current flows between the source and the drain. In a practical vertical type MOSFET, a portion (cell) denoted by A in Fig. 3 is repetitively arranged to constitute the vertical type MOSFETs. The size a of the portion A is selected to be as small as possible allowed under the manufacturing process or under the element characteristics. This makes it possible to maximize the number of current paths included per unit area. One of the important characteristics of the vertical power MOSFET is a product (referred to as R ONS ) of element area and on-resistance. If compared on the basis of a predetermined element area, the voltage drop across the source and drain when a current is permitted to flow decrease with a decrease in the value of a product, and a reduced amount of electric power is consumed by the element. The product R ONS can be decreased by either decreasing the resistance of the element itself or decreasing the element area. Hatched portion in Fig. 4 represent current paths in the drift region. If viewed in the direction of depth from the surface of the substrate, it will be recognized that a region sandwiched by the wells 13 forms a bottleneck that broadens toward the drain 12. The bottleneck is formed by the effect of a junction-type field-effect transistor (referred to as JFET) parasitically formed in the semiconductor substrate in the vertical direction. That is, a potential difference develops along the current path due to a resistance component in the drift region, the junction between the well and the drift region is inversely biased by a potential difference between the drift region 11 and the source 14 and well 13 secured to a ground potential, and a depletion layer expands toward the drift region having a relatively low impurity concentration to narrow the current path. The effect of JFET is conspicuous with an increase in the voltage applied to the drain or with an increase in the drain current. The resistance of a region upon which will act the effect of JFET is denoted by R JFET . The on-resistance R CELL between the source terminal S and the drain terminal D of a vertical type MOSFET cell can be represented by a resistance R S of the source region, by a channel resistance R CH , by a resistance R DRI of the drift region and by a resistance R DRA of the drain region, in addition to by R JFET , i.e., R CELL = R S + R CH + R JFET + R DRI + R DRA Furthermore, a relation between R CELL and R ONS can obviously be given as follows: R ONS = R CELL /N where N denotes a number of cells per unit area. Referring to Fig. 4, a distance s between the neighboring gates provides a space for making contact with the wiring and for a p⁺-type region 15 that gives potential to the source 14 and well 13. The distance s varies depending upon the precision of processing for forming elements, and can be determined if the manufacturing apparatus and process are specified, and cannot be smaller than a predetermined value. Fig. 5 shows a relationship between the well distance ℓ and the product R ONS of element area and on-resistance. As the distance ℓ decreases, the bottleneck of the current path shown in Fig. 3 becomes narrow and R JFET increases, whereby R CELL increases more than N, and R ONS increases. If the distance ℓ is increased, on the other hand, the effect of JFET is weakened but the area increases unnecessarily and R ONS also increases. As a result, therefore, if the breakdown voltage and the precision of the machining process are determined, there is an optimum distance ℓ at which point the product R ONS is the smallest as shown in Fig. 5. In order to further decrease the minimum value of R ONS shown in Fig. 5, Japanese Unexamined Patent Publication (Kokai) No. 63-254769 proposes a structure that is shown in Fig. 6. According to this structure, a groove 20 is formed in a region sandwiched by the wells 13, and a layer 21 of a high impurity concentration is formed around the groove in order to decrease the resistance of this portion. Therefore, even if the depletion layer expands from the boundary of the well and drift region toward the drift region, the high-impurity-concentration layer 21 around the groove is not depleted. Accordingly, a low resistance is maintained and the low resistance R JFET is maintained. R CELL = R S + R CH + R DRI + R DRA As described above, the structure of Fig. 6 makes it possible to suppress the on-resistance from increasing by the JFET effect. This eventually makes it possible to shorten the distance ℓ between the wells; i.e., R CELL is decreased without changing the number N of cells and R ONS is also decreased, compared with that of the structure of Fig. 3. The prior art shown in Fig. 6 can be expected to decrease R ONS more than the prior art shown in Fig. 3. Owing to the progress in machining technology in recent years, however, the distance ℓ between the wells shown in Fig. 4 has now been shortened to several microns for the vertical type low-voltage-breakdown MOSFETs, which have a breakdown voltage of several tens of volts, and the size a of the portion A of Fig. 3 has been reduced to smaller than 20 µm (e.g., Nikkei Electronics, Nikkei BP Co., June 4, 1990, p. 142). Even if the groove 20 is simply formed in the region sandwiched by the wells 13 as shown in Fig. 6, the distance ℓ between the wells must be increased to provide a gap so that the wells 13 will not come in contact with the groove 20. Therefore, the area increases undesirably, and N decreases more than R CELL decreases as is obvious from the relation (2), and R ONS increases. According to the conventional technology shown in Fig. 6, which is effective for decreasing the resistance R JFET of the bottleneck portion only, the value R ONS decreases little since the resistance R DRI of the drift region and like resistance of like regions are not decreased. That is, even if high grade machining technology is adapted to the structures of the prior art of Figs. 3 and 6, it is not possible to decrease the product R ONS without impairing the breakdown voltage of the element. Moreover, when the element of the structure shown in Fig. 6 is in a turned-off position, a high voltage applied to the drain electrode is induced in the channel portion via the drift region 11 and there is an impurity layer 21 of high concentration around the groove, giving rise to the occurrence of breakdown that makes it difficult to obtain a necessary breakdown voltage and, further, causes the gate oxide film 16 to be destroyed. SUMMARY OF THE INVENTION The object of the present invention is to provide a vertical low-breakdown-voltage type semiconductor device having a breakdown voltage of several tens of volts and having a structure capable of greatly decreasing the R ONS without impairing the breakdown voltage of the element. In order to a accomplish the above object, the vertical type semiconductor device according to the present invention basically has the technical constitution as described in claim 1. The preamble of claim 1 corresponds to subject matter disclosed in US-4,366,495. According to the present invention, R JFET and R DRI , which are on-resistance components of the vertical semiconductor device, decrease drastically due to a low-resistance region near the hole formed between the well regions, and the resistance decreases in these regions. Moreover, since the region between the channel and the hole is formed in the recessed structure, the concentration of electric field under the off condition is reduced enabling the breakdown voltage to increase and, at the same time, resistance of the portion of the recessed structure decreases under the on condition. Owing to the pattern in which the well regions and the holes are alternatingly arranged, furthermore, the distance is maintained between the channel and the hole while the pattern is finely formed, and a necessary breakdown voltage is maintained because of this distance. It is therefore possible to realize a vertical low-breakdown-voltage type semiconductor device having a breakdown voltage of several tens of volts that greatly decreases the R ONS . DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram which schematically illustrates the three-dimensional structure of a vertical type MOSFET according to an embodiment of the present invention; Fig. 2(a) is a section view along the line A-A′ in Fig. 1, and Fig. 2(b) is a section view along the line B-B′ in Fig. 1; Fig. 3 is a section view illustrating the basic structure of the vertical type MOSFET; Fig. 4 is a diagram showing a current path and a resistance component of the vertical type MOSFET; Fig. 5 is a diagram showing a relationship between the wall distance ℓ and the R ONS ; Fig. 6 is a section view of a conventional vertical type MOSFET; Fig. 7 is a diagram of a schematic plane pattern illustrating the arrangement of DMOS cells and through hole cells of when present invention is adapted to another cell form; and Fig. 8 is a diagram of a schematic plane pattern illustrating the arrangement of DMOS cells and through hole cells when the present invention is adapted to a further cell form. DESCRIPTION OF THE PREFERRED EMBODIMENTS In the vertical semiconductor device according to the present invention, there is imposed no particular limitation on the structure of the transistor; i.e., it may be a field-effect transistor and in particular, the field-effect transistor may have a MOS structure. The invention will now be described in detail with reference to embodiments shown in the drawings. Figs. 1 and 2 are diagrams of an embodiment in which the present invention is adapted to an n-channel vertical type MOSFET, and wherein Fig. 1 is a diagram that schematically illustrates the three-dimensional structure, Fig. 2(a) is a section view along the line A-A′ in Fig. 1, and Fig. 2(b) is a section view along the line B-B′ in Fig. 1. If mentioned briefly, the vertical type MOSFET 1 of the present invention shown in Fig. 1 consists of DMOS (double diffused MOS) cells 2 and through hole cells 3 alternatingly arranged in the vertical and lateral directions. In the DMOS cell 2 shown in Figs. 1 and 2, the constituent portions common to those of Fig. 3 are denoted by the same reference numerals. Next, described below is the constitution of the vertical type MOSFET 1 of the present invention and the rough method of fabricating the same. A semiconductor substrate consists of a layer of a high impurity concentration that serves as an n⁺-type drain region 12 (i.e., a first semiconductor layer 12 having a first type of conduction) and a layer 11 of a low impurity concentration, i.e., a second semiconductor layer 11 having the first type of conduction part of which forms an n⁻-type drift region. The surface of the n⁻-type layer having the low impurity concentration serves as a main surface F. On this main surface is formed a step by the LOCOS (local oxidation of silicon) method that effects the selective oxidation using a patterned silicon nitride film that is not shown as a mask or by the anisotropic etching method using a patterned resist film. A recessed structure is formed on the main surface wherein the surface of the through hole is higher by 1 to 1.5 µm than the surface of the DMOS cell, and an n⁻-type recessed region 22 is formed. Next, a gate oxide film 16 is formed maintaining a thickness of about 50 nm, and a polysilicon film is formed thereon maintaining a thickness of about 400 nm by the CVD method. The polysilicon film is patterned into a predetermined shape to form a gate electrode 17. Using the gate electrode 17 as a mask, a p-type well region 13 (i.e., a well region consisting of a semiconductor of a second type of condition) is formed by the diffusion from the main surface. An n⁻-type drift region 11 sandwiched by the p-type well region 13 and an n⁺-type drain region 12 must have a thickness d₁ and an impurity concentration n₁ that satisfy a desired breakdown voltage. Then, an n⁺-type source region (i.e., a source region consisting of a semiconductor of a first type of conduction) 14 is formed by the diffusion from the main surface using the gate electrode 17 and a resist that is not shown as masks. A channel 21 is formed in a portion where the p-type well region 13 comes into contact with the main surface F by double diffusion of the p-type well region 13 and the n⁺-type source region 14. When a voltage in excess of a threshold voltage is applied to the gate electrode 17, an inverted layer is formed in the channel 21 due to the effect of an electric field, and the n⁺-type source region 14 and the n⁻-type recessed region 22 become electrically conductive to each other via the channel 21. Further, a p⁺-type well contact region 15 is formed by diffusion at the center in the main surface of the p-type well region 13. The above gate electrode serves as part of the elements that constitute the current control cell region of the present invention. Next, a thin and elongated hole 23 is formed vertically from the center in the main surface of the through hole cell 3 up to the n⁺-type drain region 12 penetrating through the n⁻-type drift region 11 by the anisotropic dry etching using a resist that is not shown as a mask. An n⁺-type through hole region 25 is formed by the vapor phase diffusion from inside the hole 23. Then, the inside of the hole 23 is filled with an insulating material 24 to form an interlayer insulating film 18. The n⁺-type through hole resin 25 makes the n⁻-type recessed region 22 and the n⁺-type drain region 12 electrically conductive to each other maintaining a small resistance. Here, the n⁻-type recessed region 22 must have a length d₂ and an impurity concentration n₂ that help obtain a desired breakdown voltage. Owing to the pattern in which the DMOS cells 2 and the through hole cells 3 are alternatingly arranged in the vertical and lateral directions, the n⁻-type recessed region 22 maintaining a sufficient length d₂ is formed. That is, the above-mentioned hole portion forms a low-resistance region of the vertical type that exhibits actions and effects of the present invention. The interlayer insulating film 18 is patterned using a resist mask not shown to form a contact hole and, then, a source electrode 19 is formed that comes in ohmic contact with the n⁺-type source region 14 and the p⁺-type well contact region 15. On the other hand, the drain electrode 10 is formed even on the back surface of the semiconductor substrate to come in ohmic contact with the drain region 12. The source electrode 19 is connected to a source terminal S, the drain electrode 10 is connected to a drain terminal D, and the gate electrode 17 is connected to a gate terminal G. Next, described below is the operation of the vertical type MOSFET 1 constituted as described above. First, the flow path of carriers under the on condition will be described with reference to Fig. 2(a). When a voltage in excess of a threshold voltage is applied to the gate electrode 17, an inverted layer is formed in the channel 21 due to the effect of an electric field, and the n⁺-type source region 14 and the n⁻-type recessed region 22 are rendered electrically conductive via the channel 21. Therefore, the electrons flow from the source electrode 19 into the n⁺-type drain region 12 along the electron flow path 31. That is, the electrons flow along the below-mentioned path, i.e., source terminal S -> source electrode 19 -> n⁺-type source region 14 -> channel 21 -> n⁻-type recessed region 22 -> n⁺-type through hole region 25 -> n⁺-type drain region 12 -> drain electrode 10. Here, the electrons that flow from the channel 21 into the n⁻-type recessed region 22 readily disperse throughout the n⁻-type recessed region 22 and flow toward the n⁺-type through hole region 25. Next, described below with reference to Fig. 2(a) is the voltage distribution under the off condition and the breakdown voltage across the drain and the source. Under the condition where a voltage lower than the threshold voltage is applied to the gate electrode 17, the inverted layer is not formed in the channel 21, and the n⁺-type source region 14 and the n⁻-type recessed region 22 positioned on both sides of the channel 21 are electrically insulated. The n⁺-type through hole region 25 and the n⁺-type drain region 12 are rendered electrically conductive. As a result, the voltage applied across the drain and the source is further mostly applied not only to the n⁻-type drift region 11 sandwiched between the p-type well region 13 and the n⁺-type drain region 12 but also to the n⁻-type recessed region 22 sandwiched between the p-type well region 13 and the n⁺-type through hole region 25, and depletion layers are formed in these regions. Therefore, the breakdown voltage of the vertical type MOSFET 1 is determined by either the pn junction consisting of the n⁻-type drift region 11 and the p-type well region 13 or the pn junction consisting of the n⁻-type recessed region 22 and the p-type well region 13. That is, the breakdown voltage BV₁ of the pn junction consisting of the n⁻-type drift region 11 and the p-type well region 13 is basically determined by the impurity concentration n₁ and the thickness d₁ of this region, and the breakdown voltage BV₂ of the pn junction consisting of the n⁻-type recessed region 22 and the p-type well region 13 is determined by the impurity concentration n₂ and the thickness d₂ of this region. Here, however, the impurity concentration n₁ and n₂ are equal to each other, i.e., n₁ = n₂ (= n) since these regions consist of the n⁻-type low-impurity-concentration layer of the semiconductor substrate. In designing the breakdown voltage of the vertical type MOSFET 1, the below-mentioned relationship should be maintained between the above BV₁ and BV₂ so that the avalanche breakdown will take place only at the pn junction portion consisting of the n⁻-type drift region 11 and the p-type well region 13 but that the avalanche breakdown will not take place at the pn junction portion consisting of the n⁻-type recessed region 22 and the p-type well region 13. BV₁ < BV₂ The reason is because if the avalanche breakdown takes place at the pn junction portion consisting of the n⁻-type recessed region 22 and the p-type well region 13, the generated hot carriers deteriorate the interface of silicon and oxide film in the channel region 21 creating such adverse effects as a change in the threshold voltage, decrease in the breakdown voltage of the gate oxide film, breakage of insulation and the like. Described below is the element structure in the case when the breakdown voltage across the drain and the source is designed to be several tens of volts. For instance, when the breakdown voltages BV₁ and BV₂ are set to be 60 volts, the impurity concentration n and the thickness d₁ or d₂ of the n⁻-type drift region 11 and the n⁻-type recessed region 22 are selected to be as follows from the literature, S.M. Sze, "Physics of Semiconductor Devices", John Wiley and Sons Inc., 1969, pp. 115 and 117. n = 1 x 10¹⁶ [cm⁻³] d₁ = d₂ = 2.5 [µm] From the equation 5, the outer size of the through hole cell 2 in the element plane shown in Fig. 1 is given, if one side thereof is denoted by L TH , by the following equation, L TH = d₂ x 2 + d₃ x 2 + d₄ where d₃ denotes the thickness of the n⁺-type through hole region 25, and d₄ denotes the width of the hole 24. For instance, if d₃ = 0.5 [µm] and d₄ = 1 [µm], then L TH = 7 [µm] from the above equations (5), (6) and (7). From the viewpoint of dimensional precision in modern machining technology, it is possible to set L TH to be smaller than 10 µm. Therefore, if the DMOS cells 2 and the through hole cells 3 are alternatingly arranged in the vertical and lateral directions as shown in Fig. 1, the outer size of the DMOS cells can be set to be smaller than 10 µm too, since the outer sizes of these cells are set to be equal in the element plane. Next, described below is the on-resistance. The on-resistance R DCELL of a DMOS cell 2 in the vertical MOSFET 1, the on-resistance R TCELL of a through hole cell 3, and the product R ONS of element area and on-resistance of the vertical MOSFET 1 are given by the following equations from the consideration of flow path of the carriers, R DCELL = R S + R CH R TCELL = R REC + R DRA + R TH where R S denotes the resistance of the n⁺-type source region 14, R CH denotes the resistance of the channel 21, R REC denotes the resistance of the n⁻-type recessed region 22, R TH denotes the resistance of the n⁺-type through hole region 25, and R DRA denotes the resistance of the n⁺-type drain region 12. R ONS = (R DCELL + R TCELL )/N where N is the number of DMOS cells 2 and the through hole cells 3 per unit area. Since R S , R TH and R DRA are set to be smaller than R CH and R REC , the equations (8), (9) and (10) can be simplified as follows. R DCELL ≒ R CH R TCELL ≒ R REC R ONS ≒ (R CH + R REC )/N The equations (1) to (3) that give the on-resistances of the conventional vertical type MOSFET shown in Figs. 3 and 6 can similarly be simplified as follows: R CELL ≒ R CH + R JFET + R DRI R CELL ≒ R CH + R DRI The resistances R REC and R DRI in the equations (11) to (15) are equal considering the breakdown voltage designing conditions represented by the equations (5) to (7) and their structure, i.e., R REC ≒ R DRI Therefore, there is no difference between the vertical type MOSFET 1 of this embodiment and the vertical type MOSFET that is shown in Fig. 6 based on the on-resistance of one cell only. Next, described below is the product R ONS which is one of the important characteristics of the vertical type MOSFET when comparing the vertical MOSFET 1 of this embodiment with the conventional vertical type MOSFET shown in Figs. 3 and 6. What is very important here is that even if the size of the cell of the conventional structure shown in Fig. 3 is reduced by utilizing modern machining technology as exemplified in Fig. 5, R JFET increases and R ONS becomes the smallest when the size of the cell is ten and several µm. Therefore, a further reduction in the size of the cell has no effect. In the conventional structure shown in Fig. 6, on the other hand, when the element is in an off condition, a high tension applied to the drain electrode is induced near the channel via the drift region 11 and the high-impurity-concentration layer 21 around the groove to easily develop the breakdown. In order to obtain a necessary breakdown voltage, the distance between the groove 20 and the well 13 must be sufficiently great. Accordingly, the size of the cell inclusive of the groove is not reduced and R ONS also does not decrease. The products R ONS will now be compared between the vertical type MOSFET 1 according to the embodiment shown in Figs. 1 and 2 and the conventional vertical type MOSFET shown in Fig. 3. It is now presumed that the DMOS cells and the through hole cells have a side that measures 10 µm in the vertical type MOSFET 1 shown in Figs. 1 and 2, and the cells have a side that measures 15 µm in the vertical type MOSFET (hereinafter referred to as vertical type MOSFET O) of Fig. 3. If the number of cells is N O per unit area of the vertical type MOSFET O, the number N₁ of cells per unit area of the DMOS cells and through hole cells of the vertical type MOSFET 1 can be easily calculated as follows: N₁ = (9/8).N O Next, considered below is the channel resistance. In general, the channel resistance R CH maintains the following relationship concerning the channel length L and the channel width W. R CH ∝ L/W If the boundary line between the channel 16 and the drift region 11 is formed 2 µm inside the outer peripheral line, then the channel width W O of the cell of vertical type MOSFET O is (15 - 2 x 2) x 4 = 44 [µm]. On the other hand, the channel width W₁ of the DMOS cell of the vertical type MOSFET 1 is 10 x 4 = 40 [µm] since the boundary line between the channel 21 and the recessed region 22 is in agreement with the outer peripheral line of the cell, i.e., If the cells of the vertical type MOSFET 0 and the DMOS cells of the vertical type MOSFET 1 have channel resistances that are R CH0 and R CH1 , and if they have an equal channel length L, then there exists the following relationship from the equations (18) and (19), R CH1 = 1.1 x R CH0 Next, R ONS of the vertical type MOSFET 0 is denoted by R ONS0 and R ONS of the vertical type MOSFET 1 is denoted by R ONS1 , and are compared with each other. R ONS0 is given as follows from the equations (2) and (14), and R ONS1 is given as follows from the equations (11) to (13), R ONS0 ≒ (R CH0 + R JFET + R DRI )/N₀ R ONS1 ≒ (R CH1 + R REC )/N₁ The equations (16), (17) and (20) are substituted for the equations (21) and (22) to eliminate R CH1 , R REC and N₁ , and to find R ONS0 /R ONS1 . R ONS0 R ONS1 ≒ 9 8 .[1 + R JFET - 0.1 x R CH0 1.1 x R CH0 + R DRI ] As will be obvious from the equation (23), R ONS0 /R ONS1 > 1 from which it is proved that the product R ONS of the element area and the on-resistance of the vertical type MOSFET 1 of this embodiment is smaller than that of the conventional vertical type MOSFET 0 that is shown in Fig. 3. At a corner portion of the DMOS cell having a square shape as shown in Fig. 1, furthermore, the p-type well region 13 and the n⁺-type source region 14 are formed by double diffusion, which is positioned in a self-aligned manner by the gate electrode 17, and whereby the channel length becomes shorter than the sides of the cells, the impurity concentration decreases and the threshold voltage decreases. Therefore, even if the cell is designed to be turned on at a gate voltage V G of 1.5 volts, the cell may be turned on at the corner portion at, for example, 1.2 volts or may be broken down at the corner portion by the surge voltage when the device is turned off. These problems, however, can be overcome by employing the structure of this embodiment. That is, by alternatingly arranging the DMOS cells in the vertical and lateral directions as shown in the B-B′ section view f Fig. 2(b), the distance can be decreased between the neighboring DMOS cells 2 at the corner portion, and the DMOS cell 2 is prevented from being turned on at the corner portion since the JFET resistance increases in the n⁻-type drift region 11 that is sandwiched by the p-type well regions 13 of the neighboring cells 2. Under the turned-off condition, the depletion layers 50 extending from the two DMOS cells 2 become continuous and the electric field becomes mild at the JFET portion. This helps eliminate the breakage that results from the surge voltage applied to the drain that is concentrated at the corner portion. At the other sides of the cells, there exists the through hole cell 3 because of the pattern in which they are alternatingly arranged in the vertical and lateral directions, and the effect of the depletion layer 50 becomes negligibly small. According to the above-mentioned embodiment shown in Figs. 1 and 2, the n⁺-type through hole region 25 is formed as the structure for decreasing the electric resistance in the lengthwise direction near the hole 23. It is, however, allowable to employ another structure. For instance, the effect of the present invention can be obtained and R ONS can be decreased even when the insulating material 24 filled inside the hole 23 is changed into a conductor having a small resistance such as a metal, and the side surface of the hole 23 is brought into ohmic contact with the conductor. Moreover, though this embodiment has dealt only with a structure that includes the recessed structure, the product R ONS can be decreased smaller than that of the conventional vertical type MOSFET even with a planar structure that does not have the recessed structure owing to the effect of the through hole cell 3. In the above embodiment, furthermore, the invention was adapted to the lattice-like cells having a plane of a square shape. It should, however, be noted that the present invention can be suitably adapted to any other polygonal cells or striped cells. In these cases, the DMOS cells 2 and the through hole cells 3 are arranged as follows; i.e., the through hole cells 3 are neighboring each other at the sides that serve as channels of the DMOS cells 2. Moreover, the through hole cells 3 need not be arranged for all sides of the DMOS cells 2, but may be determined depending upon the preset number per unit area of the DMOS cells 2 and the required decrease in the on-resistance. Figs. 7 and 8 illustrate examples of application. Fig. 7 is a schematic diagram of a plane pattern that illustrates the arrangement of DMOS cells 2 and through hole cells 3 when the present invention is adapted to hexagonal cells having nearly a triangular shape. In Fig. 7, a p-type layer 51 (in the case of the n-channel type) is formed under the gate electrode 17 between the corners of the DMOS cells 2 in a triangular shape to make the depletion layers communicate with each other under the off condition in view of a drop in the threshold voltage at the corners. Here, the p-type layer 51 may be continuous to the p-type well region 13, or may be eliminated by bringing the DMOS cells 2 closer to each other. Fig. 8 illustrates an example in which the DMOS cells 2 of orthohexagonal shape and the through hole cells 3 of equilateral triangular shape are arranged. In this case, all sides of the DMOS cells 2 can face the through hole cells 3 and an increased number of DMOS cells can be laid per unit area eventually making it possible to increase the peripheral length of the effective channels and to decrease the on-resistance. According to the vertical type semiconductor device of the present invention, there is imposed no particular limitation on the shape of the current control cell regions that include a gate electrode, and the current control cell regions are arranged around, for example, the cell region and the region where the hole is formed, i.e., arranged around the low-resistance cell region and are hence formed depending upon the shapes of these regions. Therefore, if the cell region has a polygonal shape, such as a hexagonal shape, the current control cell region is formed in a shape that meets the outer peripheral shape thereof. At the same time, the current control cell region is formed in a shape that varies depending upon the peripheral shape of the region where the hole is formed. That is, it is desired that the current control cell region has a polygonal cellular shape that enables the channel region to be formed along the sides thereof and the low-resistance cell regions are arranged to face all sides of the current control cell region. It is further desired that both the current control cell regions and the low-resistance cell regions have a square cellular shape and are alternatingly arranged in the vertical and lateral directions on the semiconductor layer. As another example, it is desired that the current control cell regions have an orthohexagonal cellular shape and the low-resistance cell regions have an equilateral triangular shape. It is further desired that the current control cell regions that are neighboring each other at the corners of the polygonal cellular shape thereof maintain a distance among themselves such that the depletion layers thereof overlap each other under the turn-off condition of the device. In the semiconductor device of the present invention, it is desired that the surfaces of the low-resistance cell regions are higher than the surfaces of the current control cell regions. Though the aforementioned embodiments have dealt with those of the n-channel type, the invention can be adapted to those of the p-channel type as a matter of course. Furthermore, the insulated gate structure is not necessarily limited to the MOS type, but, for instance, a nitride film may be formed as the gate insulating film as a matter of course. According to the present invention, the on-resistance of the vertical type semiconductor device can be strikingly decreased without impairing the breakdown voltage of the element.

Claims: A vertical type semiconductor device, comprising: a semiconductor substrate of a first type of conductivity consisting of a layer (12) of a high impurity concentration and, formed thereon, a layer (11) of a low impurity concentration, said layer (12) of said high impurity concentration serving as a drain region, the surface of said layer (11) of said low impurity concentration forming a main surface (F); current control cell regions (2), each comprising a well region (13) of a second type of conductivity formed in a portion of said main surface (F), a source region (14) of said first type of conductivity being formed in a portion of the surface of said well region (13), a gate electrode (17) formed on a periphery of said well region of said second type of conductivity via an insulating film (16) in order to form a channel region on the periphery of said well region (13), said layer (11) of said low impurity concentration forming a drift region between said well region (13) of said second type of conductivity and said drain region (12), and a current between said drain region (12) and said source region (14) being controlled by applying a voltage to said gate electrode (17); characterized by: a low-resistance cell region (3) comprising an annular through hole region (25) of said first type of conductivity extending from said main surface (F) between neighboring well regions (13) to said drain region (12) passing through said layer (11) of said low impurity concentration, the electric resistance of said annular through hole region (25) being smaller than the electric resistance of said layer (11) of said low impurity concentration and the position of said main surface (F) between said neighboring well regions (13) being higher than the position of said channel region in order to constitute a recessed structure. Semiconductor device according to claim 1, characterized in that said annular through hole region (25) of said low resistance cell region (3) is located at the center of a portion between said neighboring well regions (13). Semiconductor device according to claim 2, characterized in that said low-resistance cell region (3) is surrounded by a plurality of said current control cell regions (2). Semiconductor device according to one of claims 1 through 3, characterized in that the interior of said annular through hole region (25) is filled with a conductor material having a small resistance, such as metal, while ensuring an ohmic contact. Semiconductor device according to one of claims 1 through 4, characterized in that said current control cell regions (2) have a polygonal cellular shape such that said channel regions are formed along the sides thereof. Semiconductor device according to claim 5, characterized in that there are provided a plurality of said low-resistance cell regions (3) which are arranged to be opposed to all sides of said current control cell regions (2). Semiconductor device according to claim 6, characterized in that said current control cell regions (2) and said low-resistance cell regions (3) both have a square cellular shape. Semiconductor device according to claim 6, characterized in that said current control cell regions (2) have an orthohexagonal cellular shape and in that said low-resistance cell regions (3) have an equilateral triangular cellular shape. Semiconductor device according to one of claims 5 through 8, characterized in that said current control cell regions (2) neighboring one another at the corners of the polygonal cellular shape thereof maintain such a distance among themselves that the depletion layers overlap each other when the semiconductor device is turned off.

Inventors: HARA KUNIHIKO, TOKURA NORIHITO, HARA, KUNIHIKO, TOKURA, NORIHITO
Applicants: NIPPON DENSO CO, NIPPONDENSO CO., LTD.
Application year: 1991
Main classification: H01L29
IPC codes: H01L29