Logic element and article comprising the element

Abstract: Disclosed are a novel logic element (designated NORAND), and articles that comprise the element. Exemplarily, the NORAND element comprises three input terminals (A,B,C) and an output terminal (42). If one of the input terminals is at logic 0 then the element functions as a logic NOR unit, and if the terminal is at logic 1 the element functions as a logic AND unit. The novel element thus makes possible reprogrammable and/or self-organizing logic circuits. The NORAND element can be realized with a single active semiconductor device, exemplarily a real space transfer (RST) device.

Description: Field of the Invention This invention pertains to devices (typically semiconductor devices) that can be used to perform logic operations, and to articles comprising such a device. In a particular embodiment the devices are real space transfer semiconductor devices. Background of the Invention Real space transfer (RST) devices are known to the art. See, for instance, "Heterojunction Band Discontinuities: Physics and Device Applications", F. Capasso et al., editors, Elsevier 1987, especially pages 513-537. Known RST devices are a transistor variously called charge-injection transistor (CHINT) or negative resistance field effect transistor (NERFET), and the hot-electron erasable programmable random access memory (HE 2 PRAM). See, for instance, U.S. Patent 4,903,092. Briefly, the transistor is a three-terminal device based on real-space transfer of hot electrons from a first to a second conducting region. The two conducting regions are separated by a barrier region and are contacted independently, with one of the conducting regions (referred to as the "channel") having two surface contacts (frequently referred to as "source" and "drain"). Application of a source-to-drain bias V sd leads to a heating of channel electrons and consequent charge injection into the second conducting layer. The channel thus acts as a hot electron emitter and the second conducting layer as a collector. This terminology will be used herein. The above discussed transistor shows a strong negative differential resistance in the source-drain characteristic (the NERFET action) and an efficient control of the injection current (I c ) by the source-drain voltage (CHINT action). HE 2 PRAM comprises, in addition to the above described elements, a "deep" drain that contacts both the emitter and the collector. A logic circuit that comprises prior art RST devices is also known. For instance, on page 520 of the above referenced monograph is disclosed a logic circuit comprising two NERFETs. Those skilled in the art are well aware of the desirability of having available devices that have novel operating characteristics, since such devices may make possible attainment of previously unachievable results, or may result in more economical attainment of some desired results. For instance, prior art implementation of basic logic functions (e.g., AND, NOR) generally requires a multiplicity of active elements (typically transistors). It would clearly be desirable, both from an economic and from a performance point of view, to be able to implement such logic functions with logic elements that comprise only a single active device, and thus reducing the device count and the number of gate delays. As a second example, it would be highly desirable to have available a device that can carry out a logic function which in the prior art required two or more separate logic elements. As a third example, it would be very desirable to have available a device that can carry out either a first or a second logic function. This application discloses a novel device that has these and other advantageous attributes. It also discloses articles that utilize the novel device. Circuitry according to the preamble portion of present claim 1 is disclosed in S.L. HURST : "The Logical Processing of Digital Signals", Crane, Russak & Company, Inc., New York 1979, page 483. Patent Abstracts of Japan, vol. 14, no. 28, (E-875) 19th January 1990 (abstract of JP-A-01265561) discloses a logic element consisting of two resonant-tunneling hot-electron transistors (RHET) integrated back-to-back with a common emitter layer. The logic element can perform as a two output flip-flop or an exclusive OR/NOR element. A paper by N. Yokohama et al. in Japanese Journal of Applied Physics, vol. 24, no. 11, November 1985, pages L853-L854 entitled 'A new functional, resonant-tunneling hot electron transistor (RHET)' discloses a two-input exclusive NOR element comprising a single RHET with two inputs connected to the base via respective resistors. Definitions A "logic element" herein is a circuit element that has at least two input terminals and an output terminal. The element accepts binary input signals, performs a predetermined transformation on the input signals, and presents the resulting binary output signal at the output terminal. Examples of logic elements are AND, OR, NAND, NOR, and EXCLUSIVE-NOR (XNOR) elements. A "logic function" herein is the transformation provided by a logic element. For instance, a AND logic element provides and AND logic function, i.e., its output depends on the inputs in the manner described by the AND truth table. By the "electrical state" of a logic element we mean herein the totality of electrical signals applied to the input terminals. For a logic element with two input terminals (A,B) a particular electrical state thus is A=1, B=0, and a further particular state is A=0, B=1, where 1 and 0 are used in conventional fashion. By the "general" electrical state of a logic element we mean herein the combination of electrical signals applied to the input terminals. By this we mean that, for instance, A=1, B=0 is the same general electrical state as A=0, B=1, since the combination in both cases is a logic 0 and a logic 1. Summary of the Invention A device according to the invention is set out in claim I. Prefered forms are set out in the dependent claims. An exemplary device is a semiconductor RST which comprises three semiconductor regions which are spatially sequential in a first direction. The regions are designated, in sequence, as channel or emitter region, barrier region, and collector region. The barrier region has a composition that is adapted to forming a potential barrier between the emitter and the collector. The device also comprises first, second, and third spaced apart electrical contacts to the emitter, with neither of said first, second and third contacts making electrical contact to the collector. The device furthermore comprises an electrical contact to the collector that does not make electrical contact to the emitter region. The charge carriers injected into the collector from the emitter can be hot electrons or hot holes, with the former typically being preferred. In the novel RST device the geometry is such that, for a given voltage V sd , the current into (or out of, as the case may be) the collector contact (the current to be termed I c ) is substantially the same for all electrical states of a given general electrical state of the device. In other words, in these preferred embodiments the contacts are arranged such that I c is substantially the same, regardless of which pair of input contacts a given voltage V sd is applied to, and regardless of which member of the pair of contacts to remaining input contact is connected to. I c in a particular electrical state is "substantially the same" as I c in another electrical state (both states belonging to the same general electrical state) if the currents differ by at most 25%. In a further particular embodiment the invention is an article that comprises a multiplicity of logic elements, including at least one element according to the invention. A given logic element comprises a multiplicity of terminals including at least two input terminals and an output terminal. The output terminal of at least one of the logic elements is connected to an input terminal of at least one of the other logic elements. Associated with each logic element is a logic function (e.g., logic AND, logic OR, etc.). Connected to one of the input terminals (to be referred to as the "control" terminal) of the at least one element according to the invention (this logic element will be referred to as a "re-programmable" element) are electrical means adapted for applying an electrical signal corresponding to logic 0 or to logic 1 to the "control" terminal. In other words, said electrical means are adapted for changing the electrical state of the re-programmable element, by causing the "control" terminal to be either at logic 0 or at logic 1. Exemplarily, the electrical means are the output terminal of another logic element, or they are an external signal source. Significantly, the re-programmable element performs a first logic function if the "control" terminal is at logic 0, and a second logic function if it is at logic 1. A logic circuit containing a re-programmable logic unit that can be switched by external electrical means will be referred to as a "re-programmable" logic circuit. A logic circuit that contains a re-programmable logic element that can be switched by internal electrical means, e.g., by application to the "control" terminal of a voltage that is derived from, or controlled by, the output of another of the logic elements, will be referred to as a "self-organizing" logic circuit. Brief Description of the Drawings FIG. 1 schematically depicts a prior art RST device; FIG. 2 shows an exemplary electrical characteristic of a prior art RST device; FIG. 3 schematically depicts, in plane view, the arrangement of contact means associated with an exemplary device according to the invention; and FIG. 4 shows schematically a further exemplary device according to the invention; FIG. 5 shows the proposed circuit symbol for the inventive logic element (NORAND); FIGS. 6 and 7 schematically depict relevant portions of, respectively, a re-programmable logic circuit and a self-organizing logic circuit. FIG. 8 symbolically represents the action of a general NORAND logic element; FIG. 9 exemplifies the logic function carried out by a general NORAND element; and FIG. 10 depicts an exemplary combination of a device according to the invention with resistive means and a source of voltage. Detailed Description of Some Exemplary Embodiments of the Invention FIG. 1 schematically depicts relevant features of a prior art RST device and the associated energy band diagram. Reference numeral 10 refers to the semi-insulating substrate (e.g., InP), 11 to the collector region (e.g., about 500 nm n + InGaAs), 12 to the barrier region (e.g., 200 nm undoped InAlAs), and 13 to the emitter region, (e.g., 50 nm InGaAs, 10 16 cm -3 Si). Numbers 14 and 14' refer to the two "channel" contacts, and 15 to the collector contact. In the energy band diagram of FIG. 1, numeral 16 refers to the conduction band edge for V c = 0 (V c is the voltage applied to contact 15), and 17 to the conduction band edge for V c > V T , where V T is a threshold voltage associated with the device, defined by the condition that, if 13 is essentially undoped, essentially no free electrons are in the channel if V c <V T , but free electrons are induced into the channel by a positive V c > V T . Numeral 18 refers to these electrons, and E F indicates the Fermi energy. In principle V T need not be a positive voltage. For instance, the barrier layer may have one or more modulation doped donor layers, so as to induce a "normally-on" channel. FIG. 2 shows an exemplary plot of I c versus V sd for a transistor according to FIG. 1, wherein I c is the current into contact 15 and V sd is the voltage applied between channel contacts 14 and 14'. Further details of the above referred to device will be discussed in Example 1. Next we will describe an exemplary RST device according to the invention. The novel device comprises at least three contacts to the emitter, and thus clearly differs structurally from prior art RST devices. For the sake of definiteness the discussion herein will be primarily in terms of a device with three emitter contacts. Inventive devices exemplarily have a layer structure substantially as shown in FIG. 1, but differ, inter alia, with regard to number and arrangement of emitter contacts. FIG. 3 schematically shows in plane view an exemplary emitter contact arrangement, wherein regions 30, 31, and 32 indicate the emitter contacts (the channel is not shown). Identifying contacts 30, 31, and 32 with terminals A, B, and C, respectively, and the collector contact of the inventive RST device with "output" (the latter contact corresponds to 15 of FIG. 1 but is not shown in FIG. 3), the device characteristics correspond to the truth table shown in Table 1. The collector voltage is applied not directly to the collector layer but through an appropriate resistive load, which may comprise a resistor or, preferably, a depletion-mode transistor, as is well known to those skilled in the art. The value of this resistive load typically will be low compared to the resistance of the barrier in the absence of an appropriate applied voltage V sd , and high compared to the resistance of the source-to-collector path over the barrier when an appropriate V sd is applied, resulting in "heating" of the channel electrons and induction of the RST. Consequently, the electric potential of the collector layer will be high (logic level 1) in the absence of RST and low (logic level 0) in the presence of RST. FIG. 10 depicts schematically in combination an exemplary RST device according to the invention, together with resistive means and a source of electrical power. The combination 100 is an embodiment of the inventive logic element, with numerals 101, 102, and 103 referring, respectively to emitter, barrier, and collector of the RST device, numerals 1040, 1041 and 1042 referring to the input terminals, and numerals 105, 106 and 107 referring to the output terminals, load resistor, and voltage source, respectively. A B C out 1 1 1 1 0 1 1 0 1 0 1 0 0 0 1 0 1 1 0 0 0 1 0 0 1 0 0 0 0 0 0 1 It will be noted that for terminal C fixed at logic 1 the device functions as a logic AND unit, and for C fixed at logic 0 it functions as a logic NOR unit. As is well known, any binary logic can be implemented with either of these two logic functions, combined with a NOT element. The NOT element or inverter is trivially obtained by setting both B and C to 0, then out = NOT (A). Of course, implementation of an inverter does not require three electrodes and the NOT function can, for instance, be obtained directly from the basic CHINT device in FIG. 1. As those skilled in the art will recognize, the above truth table is unlike that of any previously known logic element, and could previously only be obtained by a combination of two or more prior art logic elements. A device according to the invention thus can form a novel logic element. We are proposing to refer to the novel element as "NORAND", and are also proposing the circuit symbol shown in FIG. 5 for a NORAND element. The above described three input NORAND element is a particular example of the novel, more general NORAND logic element, schematically shown in FIG. 8, which has n input terminals (n is an integer ≥2) and one output terminal, with X 1 , X 2 , ....... X n signifying the n boolean inputs (having values of either 0 or 1), and f(X 1 , X 2 ......... X n ) being the boolean output (having value of 0 or 1 ) depending on the inputs X 1 , X 2 .......... X n . The logic function provided by the general NORAND logic element can be defined as follows: wherein the first term on the right hand side represents the logical AND of all the inputs, the second term represents the logical AND of the inverses of all of the inputs, and "+" signifies logic OR. As those skilled in the art will recognize, the above definition can be implemented as is symbolically depicted in FIG. 9, wherein logic element 91 is a n-input AND element, logic element 92 is an n-input NOR element, and logic element 93 is a 2-input OR element. As is evident from FIG. 9, the "prior art" implementation of the NORAND function involves three logic elements with the signals experiencing 2 gate delays. On the other hand, a NORAND element according to the invention is a single logic element. Furthermore, prior art logic elements (including AND, NOR, and OR) typically require more than one active device, whereas the inventive NORAND element can be implemented with a single active device. Thus, logic circuits that include logic elements according to the invention can involve fewer gate delays and requires less area than equivalent prior art circuits. Exemplarily, a two-terminal NORAND element [or, equivalently, a n-terminal (n>2) NORAND in which all input terminals except one are tied together electrically] is an XNOR logic element and may be advantageously used, for instance, in a binary adder. Applying the above definition of the general NORAND element to the case n=2 results in the following: f(X 1, X 2 ) = X 1 ·X 2 + X 1 · X 2 = X 1 ⊕ X 2 , where ⊕ signifies EXCLUSIVE-OR. Implementing the XNOR logic function with conventional devices typically involves 3 gates, resulting in 2 gate delays. Thus, conventional implementation of XNOR is relatively inefficient, whereas it can be implemented very simply and efficiently with a device according to the invention. It should be noted that, even though the two-terminal NORAND element is a two-terminal NXOR element, the n-terminal (n>2) NORAND element is not equivalent to a n-terminal XNOR element. All logic elements according to the invention have the property that their output is logic 1 only if all inputs are at the same logic state (1 or 0), and is zero whenever all inputs are not at the same logic state. Although the at least three input terminals of a NORAND element are logically identical, we believe that frequently one of the terminals will be used as a control terminal, whereas the remaining terminals will be used as logic input terminals. A single three-terminal device according to the invention can implement either logic AND or logic NOR, depending on the bias applied to one of the three channel contacts (in the above described case termed the "control" terminal). This not only has the advantage that it can greatly simplify the design of complex logic and greatly reduce the number of gate delays associated with any given logic process, but it also permits simple re-configuration of a logic circuit, either through deliberate re-biasing of the control terminal of one or more logic units of the circuit, or through internal action of the circuit itself. FIG. 6 schematically depicts a portion of an exemplary article 60 according to the invention, wherein 66 refers to appropriate supporting means, 610, 611, and 612 to logic elements (or combination of elements, possibly consisting completely or in part of devices according to the invention), 62 to a NORAND element, 630, 631, 632, 633 to logic input terminals, 64 to the control terminal of the NORAND element, and 65 to an output terminal. It will be appreciated that FIG. 6 is meant to be representative of all possible re-programmable logic circuits. FIG. 7 schematically depicts a portion of a further exemplary article 70 according to the invention. Numeral 73 refers to appropriate supporting means (e.g., circuit board), numerals 710, 711, 712, and 713 to logic elements (or combination of elements, possibly consisting completely or in part of devices according to the invention), numerals 740, 741,..... to logic input terminals, numeral 72 to a NORAND element, and numeral 75 to an output terminal. Again, FIG. 7 is intended to be representative of all possible self-organizing logic circuits. As those skilled in the art will appreciate, it is of course possible to design logic circuits that are both re-programmable and self-organizing, and such circuits are also contemplated. Devices according to the invention need not comprise an electrode arrangement of the type shown in FIG. 3, and MG. 4 schematically depicts a further, and currently preferred, exemplary contact arrangement. On substrate 10 is collector 11, thereon is barrier layer 22, which is followed by channel region (emitter) 13. Numeral 40 refers to a conducting semiconductor cap layer, and 41 to appropriate contacts. Terminal 42 is the output terminal, terminals A and B are, exemplarily, the input terminals, and terminal C is the control terminal. It should be noted that the control terminal does not have to be the split outside terminal. Devices according to the invention can be embodied in a variety of materials system, including the GaAs/AlGaAs and InGaAs/InAlAs systems. RST devices, based not on hot electrons but on hot holes, have been embodied in the Ge 1-x Si x /Si system, and this system can also be used for devices according to the invention. Currently we consider the InGaAs/InAlAs system, lattice matched to InP, to be particularly advantageous because, due to certain features of its electronic structure, devices embodied in this material system can have high peak-to-valley ratio (of the I d versus V sd characteristic), low leakage current, and high speed. Among the features are a relatively large conduction band discontinuity (ΔE c ), relatively low electron mass in InGaAs, and ΔE ΓL in InGaAs that is substantially greater than ΔE c (ΔE ΓL is the energy separation between the Γ valley and the L valleys) in the conduction band of InGaAs. Example 1: On a semi-insulating Fe-doped InP(100) substrate was grown by conventional MBE at 500°C the following sequence of epitaxial semiconductor layers: a 500 nm In 0.53 Ga 0.47 As collector layer, doped with a donor (Si) concentration of 10 19 cm -3 ; a 200 nm undoped In 0.52 Al 0.48 As barrier layer; a 50 nm In 0.53 Ga 0.47 As channel layer, lightly doped with Si(1x10 16 cm -3 ); and a 30 nm In 0.53 Ga 0.47 As cap layer, Si dopant concentration 1x10 20 cm -3 . Three terminal (CHINT/NERFET) devices were then defined by conventional semiconductor manufacturing techniques that included photolithography, and etching in H 3 PO 4 :H 2 O 2 :H 2 O. These processing steps involved formation of a "trench" through the cap layer to define the source and drain areas, and of a deep trench to the collector, analogous to what is shown in FIG. 4. The former trench width was chosen to vary from 0.6 to 1.2 µm for different devices, and the emitter width to vary from 25 to 75 µm. After etching of the trench, the exposed portion of the channel region is depleted of mobile charge carriers by the surface potential. Therefore, the conductivity of this layer relies on a positive voltage applied to the collector, which induces an inversion layer. Subsequent to etching of the trenches metal contacts (Au-Ge) were formed on the cap layer and on the exposed collector region, resulting in non-alloyed ohmic contacts to the channel and the collector at room temperature and at temperatures as low as liquid He temperature. The electrical characteristics of many of the thus produced devices were determined by conventional procedures. A particular one of these devices had the I c versus I sd curve shown in FIG. 2. Example 2: A multilayer semiconductor structure identical to the structure of Example 1 was produced by a method essentially as described in Example 1. By conventional techniques the structure is patterned so as to define a multiplicity of devices of the type shown in FIG. 4. In a given device the trenches between cap layer regions are about 1 µm wide and about 50 µm long. Means are provided for electrically contacting the two terminals A and B, the two members of the terminal C and the output terminal. After connecting an appropriate voltage source to the output terminal through a depletion mode transistor, the device is tested and is found to perform in accordance with Table 1. The switching time is found to be less than 1 microsecond.

Claims: An article comprising a first electronic logic element (62) comprising input terminals and an output terminal, associated with each input terminal and the output terminal being a first and a second electrical condition to be termed logic 0 and logic 1, respectively, wherein the first logic element comprises at least three input terminals (A, B, C) and is a logic element other than a NOT element, wherein the first logic element contains a single active electronic device, the device having two different general electrical states corresponding to the output terminal being either at logic 1 or at logic 0, and wherein the output terminal is at logic 1 if all input terminals are at logic 1, or if all input terminals are at logic 0, and the output terminal is at logic 0 for all other combinations of logic 1 and logic 0 of the input terminals, CHARACTERIZED IN THAT said single active electronic device comprises a) three semicondoctor regions which are spatially sequential in a first direction and which are designated, in sequence, emitter region (13), barrier region (22), and collector region (11), the emitter region having at least three emitter contacts constituting the at least three input terminals of the first logic element, the barrier region being undoped and forming a potential barrier between the emitter region and the collector region; b) an electrical contact (42) to the collector region, wherein a collector current is substantially the same for all those combinations of logic 1 and logic 0 of the input terminals that belong to a given general electrical state of the device. The article of claim 1, further comprising means responsive to the electrical condition of the output terminal of said logic element. The article of claim 1, wherein the first electronic logic element (62) has at least first and second logic functions and is switchable between states associated, respectively, with the first and second logic functions by electrical means connected to an input terminal (64) of the first electronic logic element; and wherein the article further comprises at least a second electronic logic element (612) having an output terminal (65), at least two input terminals and a logic function, and the output terminal of the first electronic logic element is connected to an input terminal of the second electronic logic element.

Inventors: LURYI SERGEY, PINTO MARK RICHARD, LURYI, SERGEY, PINTO, MARK RICHARD
Applicants: AT & T CORP, AT&T CORP.
Application year: 1991
Main classification: H03K19
IPC codes: H01L29, H01L27