System for information exchange, comprising an information carrier and a read/write unit

Abstract: System for information exchange between a read/write unit (2) and an information carrier (4) which stores the information signals in a memory (38). The exchange of information is controlled by a microprocessor (6), while the data to be stored in the memory (38) are to be monitored. This monitoring is effected by means of a tuned circuit (34, 36) connected to an input/output (39) of the memory through a switching transistor (32). With a logic "high" value on the basis of the transistor (32), tuned circuit (34, 36) is short-circuited and no longer resonates. The resonating or not of the tuned circuit is detected by a detector (14) and passed on to the processor (6). Systems of this type may be used in hotels for access control, recording costs of hotel facilities for which fees are to be paid and for mail and/or message reporting.

Description: The invention relates to a system for information exchange, comprising an electronic information carrier and a read/write unit for reading and writing in the information carrier, the read/write unit including: a. detection means for detecting the presence of the information carrier at a read/write location on the read/write unit; the system for information exchange further comprising b. first transmitting means for transmitting data from the read/write unit to the information carrier, comprising a send section in the read/write unit and a receiving section in the information carrier; and c. second transmission means for transmitting data from the information carrier to the read/write unit, comprising a send section in the information carrier and a receiving section in the read/write unit; the information carrier including a memory. System of this type may be used, for example, for access control in hotels, the information carrier serving as a key to a room and having a further possibility of containing additional information (for example, validity) which is to be read out by the read/write unit and the unit also being capable of writing information on the carrier. This type of information may refer to, for example, the use of hotel facilities for which a fee is to be paid, so that this information may be used for computing the amount to be settled on departure. An information exchange system according to the preamble of Claim 1 is known for EP 0 289 830 A2. In this system a test sequence is transmitted from the read/write unit to the information carrier, which without delay echoes back the test sequence to the read/write unit. When the echoed back test sequence equals the original test sequence, it is assumed that the read/write unit and the information carrier are positioned well with respect to each other. When this is the case information can be exchanged between the read/write unit and the information carrier. A disadvantage of this information exchange system is, that it is not checked if the exchange of information between the read/write unit and the information carrier proceeds without faults. The information exchange could very well comprise faults due to a change of the position of the information carrier with respect to the read/write unit. Since the position of the information carrier is only tested with respect to the read/write unit before the exchange of information starts, such faults are not detected. Alternatively the monitoring of the data integrity could be carried out by performing a read cycle of the information carrier, and in case a bit error occurs by repeating the write and read cycles. However, this manner of checking is time-consuming and may therefore lead to an undesirable interruption of the information exchange if the information carrier is removed from the read/write unit in a great hurry. It is an object of the invention to provide a system for information exchange in which the data integrity can be monitored without an appreciable delay during the data transmission to the information carrier. For this purpose, the information exchange system according to the invention is characterized in that a data input and a data output of the memory are constituted by the same conductor, in that the output of the receiving section in the information carrier, the input/output of the memory and the input of the send section in the information carrier are interconnected, such that information written in the memory during a writing cycle is returned to the read/write unit without delay, to monitor the data integrity during the data transmission to the information carrier. Since the transmitting means for data transmission from the read/write unit to the information carrier are installed separate from the reverse transmitting means, it is possible during the writing cycle on the information carrier to produce a return message to the arrangement that provides the data production such as, for example, a microprocessor. Once a bit has appeared on the input/output of the memory during a writing cycle, the input of the send section is likewise provided with this same bit so that virtually immediately this bit is again detected in the receiving section of the read/write unit. If this detected bit deviates from the bit previously sent, the writing cycle can be stopped forthwith and started anew. An embodiment for the system according to the invention is characterized in that the induction coil for the send section of the second transmitting means forms part of an absorption circuit that can be short-circuited. If the absorption circuit is not short-circuited, it is adjusted to the frequency of a receiving oscillator connected to the receiving coil of the read/write unit. Consequently, this oscillator loses energy, which is detected in the read/write unit. If the absorption circuit is not short-circuited, this loss of energy will not occur, which is also detected. Thus, by short-circuiting the absorption circuit binary signals are transmitted. Another embodiment for the system according to the invention is characterized in that the read/write unit is formed by a central unit with a microprocessor and a plurality of gates and formed by further peripheral units having each a read/write location and connected each to one of the gates. When the system is used as an access system for a hotel or a holiday park it is now possible to place a peripheral unit outside the room and another peripheral unit inside the room. The outside unit may then be used for access to the room, whereas the inside unit may be used for recording the costs of the use of facilities for which a fee is to be paid such as a minibar, pay television or telephone. By means of the outside unit the hotel staff are now able at any moment without disturbing the hotel guest to check the condition of, for example, the minibar in the room and re-stock same on the basis of the findings. Another embodiment for the system according to the invention is characterized in that the system comprises comparing means for comparing, once the information carrier has been placed at the read/write location, a codeword stored in the read/write unit with a similar codeword stored in the information carrier, generating a match signal when the two codewords match, and generating a new codeword based on the read out codeword which is thereafter stored in the information carrier and the read/write unit in lieu of the existing codewords. These measures provide a safeguard against illegal copying of the information carrier. If the information carrier is used as a key to a hotel room, it is conceivable that this key is copied illegally, without the rightful owner of the key noticing this. Because the matching codewords are changed each time the room is accessed, the illegal copy will be rendered useless after the rightful owner has accessed the room only once. If the illegal key were inserted into the read/write unit prior to the rightful key, the rightful key holder will notice this immediately because he will then be barred from access to the room. In that case an alarm may be given forthwith. A further embodiment for the system according to the invention is characterized, in that the memory in the information carrier has a unique identification code and in that the read/write unit comprises: a. a first memory field; b. an additional data input coupled to the first memory field, for receiving identification codes as well as an indication code belonging to each identification code; c. a second memory field for storing the identification code read out from the information carrier; d. comparing means for comparing identification codes in the first and second memory fields and decoding the indication code when the two codes match and activating an indicator in response thereto. When using the system in, for example, a hotel or a holiday park, the above measures may assist in presenting an indication function for received mail and/or messages. In a hotel the unique identification code is formed, for example, by the room number. If there is mail for the hotel guest on that room number, through the additional data input the hotel staff can feed the room number together with an indication code indicating what kind of message (letter, telefax, telephone, or report to the reception desk) is waiting for the hotel guest. When the hotel guest arrives back at the hotel, he inserts his information carrier into the read/write unit, after which the room number in the information carrier is compared with that in the first memory field of the read/write unit. If, for example, there is a message for this guest, an indicator (e.g. a small light) conveying the contents of the message (e.g. "a fax message has arrived") will be activated. The hotel guest need not wait at a busy reception desk then, but notices on the read/write unit thus structured whether mail has arrived for him or not. Yet another embodiment for the system according to the invention is characterized in that the read/write unit comprises means for automatically generating different groups of speech signals, and means for activating one of the groups of speech signals in response to a type of information detected in the information carrier. The different groups of speech signals may be formed each by a text in a certain language. In the information carrier it may be indicated which language is used by the hotel guest. Once a hotel guest has inserted the information carrier into the read/write unit, he can get instructions for the use of the facilities in the hotel room in his native language when the code for that language is detected by the read/write unit. The invention will now be described with reference to the following drawing Figures, in which: Fig. 1 shows a circuit diagram of the information carrier and the read/write unit; Fig. 2 shows a number of time diagrams of the different types of bits used for reading and writing in the memory of the information carrier; Fig. 3 shows the structure of a command word preceding the reading or writing of data bits in the information carrier; Fig. 4 shows a circuit diagram of the memory circuit in the information carrier; Fig. 5 shows a flow chart representing the course of the process in the read/write unit when the information carrier is used as a hotel key; and Fig. 6 shows a flow chart of the course of the process in a read/write unit when used as a mail or message indicator. Fig. 1 shows a combination of an information carrier 4 and a read/write unit 2. This combination comprises first transmitting means 9 for transmitting data from the read/write unit 2 to the information carrier 4, and second transmitting means 13 for transmitting data from the information carrier 4 to the read/write unit 2. Inside the read/write unit 2 the transmitting means 9 comprise a send oscillator 8 whose output is connected to the input of a send amplifier 10. A send coil 12 is connected to the output of the send amplifier 10. The send amplifier 10 can be switched on and off controlled by a microprocessor 6 through a data output of the microprocessor. The second transmitting means 13 inside the read/write unit 2 comprise a receive oscillator 16 whose input is connected to a receive coil 18. An output of the receive oscillator 16 is connected to the detector 14 for detecting amplitude variation of the receive oscillator 16. The output of detector 14 is connected to a data input of microprocessor 6. This microprocessor also has an additional data input 7. Microprocessor 6 is of a customary type, for example, Philips 80 C 51; it may comprise an equally prior art program memory, for example, EPROM Signetics 27 C 256 and a prior art RAM memory, for example, a 256 kbit SRAM Toshiba TC 55257 APL-12. The section of the first transmitting means 9 located inside the information carrier 4 comprises a receive coil 20, a diode 22, a capacitor 24, a zener diode 26 and a resistor 28. One side of the receive coil is connected to the anode of diode 22 whose cathode is connected to one side of capacitor 24, to the cathode of zener diode 26 and to one side of resistor 28. The other side of resistor 28 forms the output of the receiving section of the transmitting means inside the information carrier. This output is connected on one side to the input/output 39 of memory circuit 38 fed by a small battery 37 and on the other side to the input of the receiving section of the second transmitting means 13 inside the information carrier. The sides of coil 20, capacitor 24 and zener diode 26 that have not been mentioned are connected to a common reference voltage. The send section of the second transmitting means 13 comprises a parallel circuit formed by a send coil 34 and a capacitor 36. One side of this parallel circuit is connected to the common reference voltage, the other side of this parallel circuit is also connected to the common reference voltage through the main current path of a transistor 32. One side of a resistor 30 is connected to the base of transistor 32, the other side forming the input of the send section of the second transmitting means 13. The exchange of information between information carrier 4 and read/write unit 2 takes place as follows. As long as the read/write unit 2 does not detect the presence of an information carrier, send coil 12 of the read/write unit 2 does not radiate energy. Consequently the electronic circuit of information carrier 4 is not supplied with energy and all the points in this circuit are at quiescent potential. This means that the base of transistor 32 has the same potential as the emitter of transistor 32. So this transistor is in a non-conductive state. If the information carrier 4 is placed at the read/write location of the read/write unit 2, an inductive coupling will be effected between the receive coil 18 and send coil 34. The parallel circuit of send coil 34 and capacitor 36 forms an absorption circuit for the frequency of the receive oscillator 16 ( for example, 7 MHz). As a result of the inductive coupling between the coils 18 and 34, energy is tapped from receive oscillator 16 causing the amplitude of the signal from this oscillator to drop. This drop is detected by detector 14 which applies a detection signal to the data input of microprocessor 6. In this manner the presence of information carrier 4 at the read/write location is detected. The data transfer can now be effected controlled by the microprocessor 6. For this purpose, controlled by the microprocessor, the send oscillator 8 (having a send frequency of e.g. 3 MHz) is connected to send coil 12 through send amplifier 10. This causes a voltage to be induced in receive coil 20, so that capacitor 24 is charged across diode 22. The voltage across capacitor 24 is stabilized by zener diode 26. The voltage at the junction between the cathode of zener diode 26 and resistor 28 now has the logic value "high". Resistor 28 has been installed to enable the junction between resistor 28 and zener diode 26 to assume the logic value "high", while the input/output 39 of memory 38 may have the logic value "low". It is assumed that input/output 39 does not affect the voltage on the junction between the resistors 28 and 30. This causes the voltage on the base of transistor 32 to rise likewise, rendering the transistor 32 conductive and thus short-circuiting the parallel circuit of send coil 34 and capacitor 36. As a result, this parallel circuit no longer forms a resonance circuit for the frequency of the receive oscillator 16, so that the amplitude of the oscillator signal is increased. This situation is detected by detector 14 which sends a corresponding signal to microprocessor 6. In this manner the microprocessor has a monitoring option to verify whether the transmitted logic value has actually arrived at the input/output 39 of memory 38. Figure 2 shows three time diagrams illustrating the voltage variations on input/output 39 of memory 38. Each of the diagrams a, b and c shows the voltage variation in a time slot with which a bit can be written in the memory 38 or read out from it respectively. The time slot is formed by the sum of the time intervals T1 and T3. Diagram a shows the voltage variation necessary for writing a 1 bit value in the memory, diagram b shows the voltage variation necessary for writing a 0 bit value in the memory and diagram c shows the voltage variation necessary for reading a bit from the memory. These voltage variations are necessary due to the specific structure of memory circuit 38, as will be further explained with reference to Fig. 4. For the memory to be writable, it is first to be brought into the writing state and for the memory to be readable it is first to be brought into the reading state. This is effected by means of a command word which will be further described with reference to Fig. 3. It is assumed that the memory has already been brought into the writing state. A writing cycle is initiated by presenting a high-to-low transition on the input to the memory. The memory is now arranged so that it writes the logic value present at input/output 39 at an instant 35 µs after the high-to-low transition. Because a certain spread may occur in the above-mentioned value of 35 µs, the desired logic value is to be present on the input/output no later than after 15 µs and be maintained there till 60 µs have passed. In diagram a T2 corresponds to 15 µs and T3 to 60 µs. From diagram a it appears that at the writing instant of 35 µs the logic value on the input/output is high so that diagram a represents the writing of a 1 bit value. From diagram b it appears that at the writing instant the logic value is low so that diagram b represents the writing of a 0 bit value. In order to be in a position to read a bit from the memory, the memory is first to be brought into the reading state. It is assumed that this is the case. The reading of a bit from the memory is introduced by a high-to-low transition of input/output 39. Because the memory is in the reading state, input/output 39 shows the bit value of the memory location concerned during an interval ranging from 2 µs after the high-to-low transition to 15 µs after the high-to-low transition (interval T4). After the interval T4, the presence of this bit value has become uncertain. Memory 38 is used in the following manner. In order to bring the memory into a known state, first 264 zeroes are written in the memory. (The voltage variation shown in diagram b is thus repeated 264 times on input/output 39 of memory 38). Any additional zeroes to be written in the memory are discarded by the memory. The memory can now be brought into the writing or reading state by applying a defined command word to the memory. Fig. 3 shows the structure of this command word. Each command word contains 8 bits, the three first bits being formed by a 1, a 0 and a 0 in this order. To bring the memory into the writing state, the subsequent five bits are all to be 1's. In order to bring the memory into the reading state, one or more of these five bits are to be 0. Once the memory has been brought into the reading state, it is possible to read the 256 data bits from the memory by supplying 256 time slots. Once the memory has been brought into the writing state it is possible to write 256 data bits in the memory by supplying 256 time slots each being capable of representing a 1 or 0 bit value. Fig. 4 gives a more detailed representation of memory circuit 38. The memory circuit comprises a 256-bit shift register 42 having a serial input, a serial output and a clock input which is activated by a descending edge. To the serial input of shift register 42 is connected the output of OR gate 44. One input of OR gate 44 is connected to the output of an AND gate 46, the other input of OR gate 44 being connected to the output of an AND gate 48. The serial output of shift register 42 is connected, on one side, to either of the two inputs of AND gate 46 and, on the other side, to the input of inverter 76. The clock input of shift register 42 is connected to the output of an OR gate 50. One input of OR gate 50 is connected to the output of AND gate 52, the other input of OR gate 50 being connected to the output of an AND gate 54. The memory circuit 38 further includes an 8-bit shift register 62 having a serial input, a parallel output and a clock input which is activated by a descending edge. The parallel input of decoding logic 64 is connected to the parallel output of shift register 62. This decoding logic 64 furthermore has a 1-bit reset input, a 1-bit initialization input, a 1-bit read output and a 1-bit write output. Through data input 39 and input buffer 60 signals can be fed to the buffer circuit. Input buffer 60 is merely used for bringing the input pulses into the proper form. The output of buffer 60 is connected to the serial input of shift register 62, an input of AND gate 48 and the clock input of a one-shot multivibrator 68. This clock input is activated by a descending edge of the signal supplied thereto. This multivibrator 68 produces a pulse having a duration of about 35 µs on its output in response to a descending edge on its clock input. The output of the multivibrator 68 is connected to the clock input of shift register 62, the input of an inverter 56, the first of three inputs of AND gate 54, the clock input of counter 70 and to the second of three inputs of an AND gate 78. The 8-bit counter 70 has an overflow output connected to the set input of a flip-flop 72 and to the reset input of decoding logic 64. The output of flip-flop 72 is connected to the reset input of counter 70 and the input of an inverter 58, whose output is connected to the second of three inputs of AND gate 54. The reset input of flip-flop 72 is connected to an output of an OR gate 74. The write output of decoding logic 64 is connected to an input of AND gate 48, a third input of AND gate 54 and to a first of three inputs of OR gate 74. The read output of decoding logic 64 is connected to an input of AND gate 46, an input of AND gate 52 and to the first of three inputs of AND gate 78. The initialization output of decoding logic 64 is connected to the third input of OR gate 74. The output of inverter 76 is connected to the third input of AND gate 78. The output of this AND gate is connected to the gate of field effect transistor 80, whose first main electrode is connected to data input 39 through a resistor 84 of, for example, 100 Ω and whose second main electrode is connected to the common reference voltage. Likewise connected to data input 39 is a resistor 82 which has a value of, for example, 500 Ω. The other side of this resistor is connected to the common reference voltage. For explaining the operation of the memory circuit it is assumed that initially all three outputs of decoding logic 64 are logic (logic "low" corresponds to the 0 bit value). At the same time, flip-flop 72 is of the asymmetric type, which is to say that the output is high when the supply voltage is switched on. Consequently, the 8-bit counter 70 is initially kept in the reset state. A complete memory cycle consists of an initialization part during which the memory is brought to a prior-art state, a command word as described with reference to Fig. 3, and a read or write sequence of 256 bits. The initialization part consists of supplying 264 time slots for writing 0-bit values (write-zero-time slot) to the data input 39. With the first descending edge (thus at the end of time interval T1 in Fig. 2b) one-shot multivibrator 68 generates a 35 µs pulse. Due to the descending edge of this pulse the clock input of shift register 62 is activated so that a 0-bit value is written in the shift register (Counter 70 does not change its count because the reset input is high). When eight zeroes have thus been written in shift register 62, this situation is detected by the decoding logic 64 in response to which the initialization output becomes high (this situation is retained until the reset input is rendered high again). The high value of the initialization output is supplied to the reset input of flip-flop 72 through OR gate 74, in response to which the output of this flip-flop becomes low. Consequently, the 8-bit counter 70 is driven out of the reset state. With the descending edge of the ninth 0-bit multivibrator 68 again produces a pulse having a duration of 35 µs. The descending edge at the end of this pulse activates the clock input of counter 70 so that this counter is incremented by unity. This process takes place 256 times after which, at the last 0-bit, the overflow output of counter 70 becomes high. As a result, the set input of flip-flop 72 becomes high and the reset input of decoding logic 64 also becomes high. The result is that the output of flip-flop 72 becomes high so that the reset input of counter 70 becomes high and the counter 70 is retained at the count of zero. Since the reset input of decoding logic 64 becomes high, the initialization output, the read output and the write output all become low. In this state the decoding logic 64 no longer reacts to any further presented zeroes. Neither does the count of counter 70 change by the presentation of 0-bits. The state of decoding logic 64 can now be changed only by the presentation of a write command or a read command. It is now assumed that a read command is presented, thus an 8-bit bit sequence in which the first bit has the 1 value and all further bits have the zero value. This command word is decoded by decoding logic 64 so that the read output becomes high and remains in this state until the reset input becomes high again. As a result of the first descending edge in the first time slot after the command word, one-shot multivibrator 68 generates a pulse having a duration of 35 µs. The descending edge of this pulse makes the counter 70 increment by unity. The ascending edge of this pulse is inverted to a descending edge by the inverter 56. Consequently, the output of AND gate also presents a descending edge which is applied to the clock input of shift register 42 through OR gate 50. Thus, the data in the shift register 42 are shifted by one location. It is assumed that a 0-bit value, i.e. logic value "low", appears on the serial output of this shift register. This low value is inverted to a high value by the inverter 76. All three inputs of AND gate 78 are high now: the first input is connected to the read output of decoding logic 64, to the second input is applied the 35 µs pulse multivibrator 68 and the third input is connected to the output of inverter 76. Consequently, the output of AND gate 78 will be high, so that field effect transistor 80 is rendered conductive. The result is that the data input 39 is connected to the common reference voltage through the low resistor 14. As a result, the base of transistor 32 ( cf . Fig. 1) is kept low, so that the resonance circuit (34, 36) is no longer short-circuited. This situation is detected by detector 14 which delivers the thus detected 0-bit to microprocessor 6. The 0-bit clocked to the serial output of shift register 42 is also applied to AND gate 46. Consequently, the output of this AND gate becomes low, which low value is fed to the serial input of shift register 42 through OR gate 44. Thus, the data in the shift register are not lost as a result of a reading cycle. If the bit clocked to the serial output of shift register 42 had had the 1 value, an input of AND gate 78 would be kept low by means of inverter 76. The gate of transistor 80 would then also be low so that this transistor would not be conductive. This results in the fact that data input 39 is not maintained at a low value, so that the base of transistor 32 is raised and this transistor thus becomes conductive during the reading interval (during which the voltage on the junction between the cathode of zener diode 26 and resistor 28 is rendered high, cf. Fig. 1). Also with the 0-bit this situation is detected by detector 14 and passed on to microprocessor 6. When 256 time slots have passed in this manner, the overflow output of counter 70 becomes high, so that decoding logic 64 is reset. The logic read output is rendered low again and the decoding logic now again waits for an initialization cycle or a command word. It is now assumed that a write command word is applied to shift register 62, i.e. a sequence of 8 bits of which the first bit is a 1, the next two 0's and all further bits are 1's. After the write command word the write output of decoding logic 64 becomes high. (The two other inputs remain low.) This high value is passed on through OR gate 74 to the reset input of flip-flop 72, so that its output becomes low and counter 70 is moved to the counting state. This low output value is likewise made high by the inverter 58 and supplied to an input of AND gate 54. The high write signal of decoding logic 64 is then applied to an input of AND gate 48 and to an input of AND gate 54. As a result of the first descending edge in the first time slot after the command word multivibrator 68 generates a 35 µs pulse. Due to the descending edge of this pulse counter 70 is incremented by unity. This 35 µs pulse is also applied to a third input of AND gate 54 whose two other inputs are also high. Consequently, the output of AND gate 54 becomes high and this high value is transferred to the clock input of shift register 42 through OR gate 50. The descending edge of this pulse likewise forms the descending edge of the signal on this clock input so that the shift register at that moment writes the bit value present on its input. This bit value is determined by the value of the output of AND gate 48. One of the inputs of AND gate 48 is high since it is connected to the write output of decoding logic 64. The other input of AND gate 48 is connected to data input 39. If a 1-bit value is available on data input 39 at the write instant, the output of AND gate 48 will also present the value of 1 and this value will be applied to the input of shift register 42 through OR gate 44; if at that moment a 0-bit value is present on data input 39, one of the inputs of AND gate 48 will be low so that the output of this gate will also be low. This low value will then be applied to shift register 42. When 256 write time slots have thus passed, the overflow output of counter 70 becomes high so that decoding logic 64 is reset. The write output now becomes low again and the decoding logic again waits for an initialization cycle or an instruction word. The flow chart shown in Fig. 5 illustrates the course of the process in the read/write unit when an information carrier is used as a hotel key. The blocks in this flow chart have the following connotations: When the information carrier is used as a key for a hotel room or bungalow in a holiday park, the information carrier ( i.e. the key) is inserted into a read/write unit outside the door or the bungalow. After the access cycle has been started (90) it is verified whether there is a key present at the read/write location (92). If there is, the reading of the key is initialized by the transmission of 264 write-0 time slots (94) to the key. After the memory in the key is brought to a known state in this manner, the read command word is transmitted to the key (96). Then the read/write unit transmits 256 read time slots to the key and reads the relevant bits from the time slots in the key memory (98). In the 256 bit sequence there are a number of bits forming the access codeword. The first time a key is inserted into a read/write unit of a room, the read/write unit is to adopt this codeword so as to calculate therefrom new codewords at a later stage, for example, by adding unity thereto. In order to indicate that the key has not yet been inserted into the relevant read/write unit before, there is a bit F, a flag, representing this situation with the 1-bit value. The processor is thus to verify whether the flag has the 0 value (100). If not, the key has been inserted into the read/write unit for the first time. From the bit sequence of 256 bits the access codeword is taken over by the memory of the read/write unit (110) after which the flag is set to 0 (112). Then the thus modified (F from 1 to 0) bit sequence is again written back to the key memory and access is given to the room. If, during the testing of the flag, the flag has the 0 value, the access codeword read out from the key is compared with the access codeword present in the memory of the read/write unit (102). If these words do not match, an alarm signal can be given (104). If they do match, a new access codeword is calculated on the basis of the access codeword present (106). For this purpose, a simple algorithm may be used, for example, adding unity to the number represented by the bit combination of the codeword. Alternatively, more intricate algorithms are possible. The newly calculated access codeword is now stored both in the bit sequence intended for the key and in the memory of the read/write unit (108). Finally, the bit sequence containing the new access codeword is written in the key memory (114) and access is given to the room (116). If the key were copied illegally, the illegal copy would not give access to the room any more after the original key had been used once or twice to open the room. In that case the access codeword in the read/write unit is different from that in the illegal copy. The flow chart represented in Fig. 6 illustrates the course of the process in a read/write unit used as mail/message indicator. The blocks in this flow chart have the following connotations: If the read/write unit has an additional data input, this unit may be used as a mail/message indicator, for example, in a hotel or holiday park. Through the additional data input there may be stored in the memory of the read/write unit for each room whether there is any mail or message. The memory in the information carrier thereto has a unique identification code, for example, the room number. If there is any mail for that specific room, this will be notified to the first memory field of the read/write unit (122 or 124) at a memory address matching the identification code. If a hotel guest returns to the hotel, he places his information carrier at the read/write location where it is read out by the read/write unit (126). The reading of the key is initialized by sending 264 write-0 time slots to the key (128). Once the memory in the key has been moved to a known state in this manner, the command word for reading is sent to the key (130). Then the read/write unit sends 256 read time slots to the key and reads from each time slot the relevant bit from the key memory (132). After the 256-bit bit sequence from the information carrier has been read out, the read/write unit selects the identification code (134). This identification code forms the address of the location in the first memory field from which the indication code is to be read out. This code is decoded. The result may be that there is no message at all. In that case a light is activated representing this situation. For example, if a telefax message has arrived, a different light is activated representing that situation. Thus, after the hotel guest has been informed of this message, the indication code is erased and the process returns to the starting point.

Claims: System for information exchange, comprising an electronic information carrier (4) and a read/write unit (2) for reading and writing in the information carrier (4), the read/write unit (2) including: a. detection means for detecting the presence of the information carrier (4) at a read/write location on the read/write unit (2); the system for information exchange further comprising b. first transmitting means (9) for transmitting data from the read/write unit (2) to the information carrier (4), comprising a send section (8, 10 12) in the read/write unit (2) and a receiving section (20-28) in the information carrier; and c. second transmission means (13) for transmitting data from the information carrier (4) to the read/write unit (2), comprising a send section (30-36) in the information carrier (4) and a receiving section (14, 16, 18) in the read/write unit (2); the information carrier (4) including a memory (38), characterized in that a data input and a data output of the memory (38) are constituted by the same conductor (the input/output (39)), in that the output of the receiving section (20-28) in the information carrier (4), the input/output (39) of the memory (38) and the input of the send section (30-36) in the information carrier (4) are interconnected, such that information written in the memory during a writing cycle is returned to the read/write unit (2) to monitor the data integrity during the data transmission to the information carrier (4). System as claimed in Claim 1, wherein the send section (8, 10, 12) and the receiving section (20-28) in the first transmitting means (9) comprise each an induction coil (12, 20) which two induction coils (12, 20) are inductively intercoupled when the information carrier (4) is in the inserted state. System as claimed in Claim 1, wherein the send section (30-36) and the receiving section (14, 16, 18) in the second transmitting means (13) comprise each an induction coil (18, 34) which two induction coils (18, 34) are inductively intercoupled when the information carrier (4) is in the inserted state. System as claimed in Claim 3, wherein the induction coil (34) for the send section (30-36) of the second transmitting means (13) forms part of an absorption circuit that can be short-circuited (34,36). System as claimed in Claim 4, wherein the detection means comprise the absorption circuit (34,36). System as claimed in Claim 1, wherein the read/write unit is formed by a central unit with a microprocessor (6) and a plurality of gates and formed by further peripheral units having each a read/write location and connected each to one of the gates. System as claimed in Claim 1, comprising comparing means for comparing, once the information carrier has been placed at the read/write location, a codeword stored in the read/write unit with a similar codeword stored in the information carrier, generating a match signal when the two codewords match, and generating a new codeword based on the read out codeword which is thereafter stored in the information carrier and the read/write unit in lieu of the existing codewords. System as claimed in Claim 1, wherein the memory (38) in the information carrier (4) has a unique identification code and wherein the read/write unit (2) comprises: a. a first memory field; b. an additional data input (7) coupled to the first memory field, for receiving identification codes as well as an indication code belonging to each identification code; c. a second memory field for storing the identification code read out from the information carrier; d. comparing means for comparing identification codes in the first and second memory fields and decoding the indication code when the two codes match and activating an indicator in response thereto. System as claimed in Claim 1, characterized in that the read/write unit comprises means for automatically generating different groups of speech signals, and means for activating one of the groups of speech signals in response to a type of information detected in the information carrier. Information carrier (4) to be used in a system as claimed in one of the preceding Claims. Read/write unit (2) to be used in a system as claimed in one of the Claims 1 to 9.

Inventors: VAN SANTBRINK RONALD BAREND, VAN SANTBRINK, RONALD BAREND
Applicants: PHILIPS ELECTRONICS NV, PHILIPS ELECTRONICS N.V.
Application year: 1991
Main classification: G06K7
IPC codes: G06K19, G06K17, G06K7