Electronic device package with battery

Abstract: An integrated circuit package (10) encapsulates a volatile memory chip (12) and a backup battery (32) for preserving data in the event of loss of main power supply. The package (10) includes a finger lead assembly (20) encapsulated within a body of non-conductive material (30), with a coplanar base support finger lead traversing an interconnect region. One terminal of the battery (32P) is welded to the base support finger lead (62), and the integrated circuit chip (12) is bonded directly onto the other battery terminal (32N) by a layer of conductive epoxy. The stacked assembly of the integrated circuit chip (12), the battery (32) and the base support finger lead (62) is disposed within a central region whereby the stacked assembly, including gold interconnect wires (34P), are completely encapsulated within the molded package body (30).

Description: This invention relates generally to packaging for semiconductor devices, and in particular to an integrated circuit package for encapsulating a semiconductor integrated circuit such as a memory chip and a backup battery for preserving memory data in the event of loss of main power supply. Conventional electronic circuit packages for semiconductor integrated circuit chips are adapted to enclose and seal the chip devices, while also providing heat dissipation, structural support, electrical attachment of device leads to external pin connectors, and electrical interconnection with other devices in the package. Such packages may be formed of one or more layers of a non-conductive material, with the semiconductor chip embedded within one of the layers. Flexible metal leads are extended from an interconnect region surrounding the chip to edge mounted connector pins for connecting the device input/output terminals to a printed circuit board socket in a host electronic circuit. An important integrated circuit product which is implemented on an IC chip encapsulated within an integrated circuit package includes a volatile semiconductor memory such as the static random access memory (SRAM) which is characterized by low power consumption and high memory cell density. The generation of valid logic signals and the retention of data in such integrated memory circuits having volatile memory cells depend in part on maintenance of power supply voltages within specified limits. In conventional integrated circuit memory devices, internal circuits sense the external source voltage being applied to determine if it is sufficient for reliable operation. In response to a low voltage condition, control signals are generated which cause active chips to be de-selected and maintained in standby condition. This is usually carried out by means of true and complement chip select signals, CS and CS , respectively, which inhibit read/write operations until the low voltage condition has been corrected. During the period that a memory chip is in the unselected condition it is necessary to maintain the charge levels of the storage capacitors in the volatile memory cells so that stored data will be retained. Otherwise, the information stored in the memory cells, including programs and data, will be lost when main power is removed. Although the loss of power does not result in memory circuit damage, the loss of stored information requires that the memory be reloaded with programs and data before processing can be reestablished. It has been proposed to solve the data loss problem by using an additional pin terminal on memory semiconductor circuits and that the additional terminal will be supplied with backup power from a remote source to maintain the data in the memory cells. However, there are now established standardized pin patterns for most integrated circuit memories; consequently, the addition of another pin dedicated to a remote backup power supply would not be compatible with standard pin patterns, and would require a substantial redesign of existing circuits. Patent Abstracts of Japan 13(396), (E-815) and JP-A-1143249 discloses a device package where an auxiliary battery on an island of a lead frame is provided with pin connections external to the device which requires the addition of two pins. Accordingly, there exists a need for a semicondcutor memory packge for encapsulating a memory chip and a backup battery wherein the socket area and standard pin configuration are not affected, and stored data are retained despite a loss of the main power supply. A substantial portion of the cost and size of a packaged chip is attributable to package fabrication, and two important design criteria in addition to providing a reliable electrical connection are cost effectiveness and space efficiency. A need thus exists for an improved device package for safely supporting an integrated circuit chip and a backup battery wherein the package is provided with pin connectors formed therein for plug-in compatibility with standard printed circuit board sockets, and the packaging space required for supporting the backup battery is minimized. Patent Abstracts of Japan 10(367),(E-462) and JP-A-61164257 discloses an arrangement within a device wherein a semiconductor element and a battery are mounted on opposite sides of an insulating plate thereby minimising the packaging space required by the battery. European patent application publication No. EP-A-0180219 discloses an arrangement wherein an integrated circuit chip is mounted on a capacitor which in turn is mounted on a conductive lead but in which the conductive lead is offset from the other conductive leads, thereby to minimise the packaging space required by the battery. Some packages for integrated circuit memory devices include a battery molded within one half section of a two-part package. In that construction, a chip is loaded onto the base plate of a lead frame and wires are bonded between I/O pads and respective internal leads. The mold is heated, and molding resin is then injected into the heated mold cavity. Consequently, the lead frame and IC chip are encapsulated by the resin within one molded half section. A small battery and other discrete components, for example a crystal, are mounted within a second half section. The second selected half section includes connector pins accurately positioned for engaging finger leads in the lead frame of the first molded half section. The dual section arrangement has served well for many product applications. However, the additional height imposed by the second half section produces a package which exceeds the maximum height limit established for critical space product applications. Accordingly, a need thus exists for am improved device package in which a semiconductor circuit device, a lead frame assembly and a backup battery are encapsulated within a single molded body of non-conductive material, wherein the packaging height dimension is less than the height of conventional two-part device packages which include a backup battery. According to one aspect of the present invention there is provided a device package for providing electrical power to an electronics circuit device comprising: a body of non-conductive material; a finger lead assembly encapsulated within said body and including a plurality of conductive finger leads for connection external to said body; and a battery encapsulated within said body having a positive polarity power terminal and a negative polarity power terminal, wherein the electronic circuit device is encapsulated within said body and is electrically coupled to the plurality of conductive finger leads, characterised in that said finger lead assembly further includes a power lead wholly contained within said body, wherein one of the battery power terminals is mounted onto and electrically coupled to the power lead, the electronic circuit device is mounted onto and electrically coupled to the other of the battery power terminals, and the electronic circuit device is electrically coupled to the power lead. The conductive finger leads and the power lead may be substantially coplanar with each other. The power lead may have a segment offset in a non-coplanar relation to said finger lead assembly, wherein the one of the battery power terminals may be mounted into the offset segment of the power lead. According to another aspect of the invention there is provided a method for packaging an electronic circuit device and a battery for providing electrical power to said electronic circuit device, comprising the steps of: connecting the electronic circuit device to a plurality of conductive finger leads of a finger lead assembly; encapsulating the finger lead assembly, the electronic circuit device, and the battery within a body of non-conductive material; and providing for the connection of the plurality of conductive finger leads external to the body of non-conductive material, characterised in that said method further comprises the steps of: mounting a power terminal of the battery onto a power lead of the finger lead assembly; mounting the electronic circuit device onto another power terminal of the battery; and connecting the electronic circuit device to the power lead and the other power terminal of the battery, wherein the power lead is wholly contained within said body. The method may further comprise the step of: supporting the power lead in a substantially coplanar relation to said finger lead assembly. The method may further comprise the step of: supporting a segment of the power lead within said interconnect region in non-coplanar, offset relation to said finger lead assembly. The present invention provides an improved package for encapsulating an integrated circuit device, including a backup battery, and it overcomes the foregoing backup battery limitations by mounting the integrated circuit device onto one of the terminals of the backup battery, and by mounting the other battery terminal on a base plate finger lead of a lead frame assembly. In this arrangement, the battery is stacked on top of a base support segment of the power lead, and the integrated circuit is stacked on top of the battery. In the preferred embodiment, the base plate finger lead is coplanar with the other finger leads, and includes a base support segment which traverses the finger lead interconnect region. The integrated circuit substrate is bonded to the battery terminal by a layer of conductive adhesive. The backup battery and integrated circuit are totally enclosed within the molded body of the package, without altering the socket area or the pin configuration. In this coplanar arrangement, the package thickness is increased slightly, but wire bonding problems are avoided. In an alternative embodiment, one terminal of the backup battery is mounted onto the base plate finger lead with a ceramic substrate being mounted onto the other battery terminal. The integrated circuit substrate is bonded onto the ceramic substrate by a layer of non-conductive epoxy, with electrical contact being made to the underlying backup battery terminal by a via conductor. The surface of the ceramic substrate is highly polished to a smooth finish, thereby supporting integrated circuit chips of different sizes for electrical contact to either the positive or negative terminal of a backup battery which may have rough, uneven terminal surfaces. In a surface mount embodiment, the backup battery is hermetically sealed, and it is protected from heat damage during reflow soldering by a thermally reflective metal layer. Operational features and advantages of the present invention will be appreciated by those skilled in the art upon reading the detailed description which follows in connection with the attached drawings, wherein: FIGURE 1 is a plan view of a lead frame assembly having an integrated circuit chip mounted onto the negative terminal of a backup battery according to a first embodiment of the invention; FIGURE 2 is a side elevational view, partly in section, of the semiconductor integrated circuit battery and lead frame in a unitary molded package; FIGURE 3 is a top plan view, partially broken away, of the integrated circuit, backup battery and finger lead assembly of FIGURE 2; FIGURE 4 is a plan view of a lead frame assembly having an integrated circuit chip mounted onto the positive terminal of a backup battery; FIGURE 5 is a side elevational view, partly in section, of a lead frame assembly, backup battery and integrated circuit chip of FIGURE 4 encapsulated within a unitary molded package; FIGURE 6 is a top plan view, partially broken away, of the integrated circuit package of FIGURE 5; FIGURE 7 is a top plan view of a semiconductor chip and backup battery mounted onto a lead frame assembly according to an alternative embodiment of the invention; FIGURE 8 is a side elevational view, partly in section, of an integrated circuit package having a backup battery, ceramic substrate and integrated circuit chip mounted onto the finger lead assembly of FIGURE 7 and encapsulated within a unitary molded package; FIGURE 9 is an enlarged top plan view, partially broken away, of the integrated circuit chip, ceramic substrate, backup battery and modified finger lead assembly of FIGURE 8; FIGURE 10 is an enlarged sectional view of a portion of the unitary molded circuit package of FIGURE 8; FIGURE 11 is a side elevational view, partly in section, of a semiconductor integrated circuit with a battery and integrated circuit being mounted on a coplanar base plate finger lead in a straight lead frame assembly and encapsulated in a unitary molded package; FIGURE 12 is a top plan view, partially broken away, of the integrated circuit, backup battery and finger lead assembly of FIGURE 11; FIGURE 13 is a view similar to FIGURE 11, in which the negative terminal of a battery is mounted on the coplanar base plate finger lead, with the integrated circuit chip being mounted on the positive terminal of the battery; FIGURE 14 is a top plan view of the integrated circuit, backup battery and finger lead assembly of FIGURE 13; FIGURE 15 is a side elevational view of a surface mount, dual-in-line integrated circuit chip package having J-leads soldered onto a landed substrate; FIGURE 16 is a right side elevational view of the surface mount, dual-in-line chip package shown in FIGURE 15; FIGURE 17 is a sectional view of the surface mount, dual-in-line chip package taken along the line 17-17 in FIGURE 15; and FIGURE 18 is a sectional view of the surface mount, dual-in-line chip package taken along the line 18-18 in FIGURE 15. In the description which follows, like parts are indicated throughout the specification and drawings with the same reference numerals, respectively. By way of example, the invention is described in combination with a static random access memory (SRAM) which is implemented by monolithic CMOS/LSI techniques on an N-type silicon semiconductor chip. It will be appreciated, however, that the packaging assembly of the invention may be used to encapsulate and provide replaceable backup battery power for discrete as well as integrated devices, but has particular utility for volatile memory integrated circuits having multiple input/output nodes. Accordingly, it should be understood that the invention in its broadest aspects may be incorporated in any moldable package which houses one or more circuit devices requiring backup power, including but not limited to discrete, micro-discrete and integrated circuit components, and hybrid combinations of discrete and integrated devices. Referring now to FIGURE 1 and FIGURE 2, there is shown an exemplary semiconductor chip package 10 incorporating the present invention. The package 10 supports and encapsulates an integrated circuit chip 12 having input/output nodes 14. The IC chip 12 may be, for example a 2K x 8 static random access memory (SRAM) circuit which is characterized by low power consumption, high memory cell density and which is implemented by complementary metal oxide semiconductor (CMOS) technology. The exemplary package 10 has a conventional dual-in-line pin configuration including twenty-four external connector pins arranged in two parallel rows with 600 mil spacing along the longitudinal edges of the package. The input/output nodes 14 of the integrated circuit chip 12 are electrically connected to selected connector pins 16 by conductive finger leads 18 of a lead frame assembly 20 as shown in FIGURE 1. Referring to FIGURE 1 and FIGURE 2, the inner lead fingers 18 are radially spaced with respect to a central interconnect region 22 and are integrally formed with the connector pins 16. Linking segments 20L of the lead frame assembly 20 are ultimately trimmed away during manufacture, whereby each inner lead 18 is electrically connected to a single connector pin 16. Transport side rail strips 24, 26 on the outer perimeter of the lead frame 20 are also cut away during trim and form operations in the last stages of manufacture, after molding has taken place. The inner tips of the conductive fingers 18 are symmetrically spaced about the interconnect region 22. The inner tips of the conductive fingers 18 are relatively narrow, and the fingers expand substantially as they radiate outwardly from the interconnect region 22. The lead frame assembly 20 includes a central base support finger lead 28 which extends in alignment with the longitudinal axis Z of the integrated circuit package 10. According to one aspect of the preferred embodiment, the base plate support lead 28 is severed about its midpoint and is then formed in offset relation to the plane of the lead frame assembly 20 as indicated in FIGURE 2, thereby producing separated finger lead tie bar segments 28A, 28B. The separated tie bar segments 28A, 28B are offset by a vertical spacing dimension A with respect to the finger leads 18. The external connector pins 16 and inner finger leads 18 are initially coplanar during molding. After molding, the connector pin portions 16 are bent through a 90 degree angle along the longitudinal side surfaces of the package during the trim and form operation. The semiconductor chip package 10 provides a standard external pin pattern for electrically connecting the input/output nodes 14 of the semiconductor chip 12 to a socket on a printed circuit board of a host electronic system or on some other semiconductor package. The chip package 10 includes a molded body 30 of non-conductive material, for example a polymer such as polyetherimide or epoxy resin. In this arrangement, the finger lead assembly 20, the semiconductor chip 12 and a backup battery 32 are embedded and encapsulated within the molded body 30. Preferably, the backup battery 32 is hermetically sealed so that its electrolyte will not evaporate when it is exposed to the elevated temperature conditions of the transfer molding procedure. Additionally, it is preferred that the battery 32 have a non-linear internal resistance which increases rapidly to a high current limiting value in response to short circuit current flow. This is desirable because the backup battery 32 will be shorted by the lead frame during assembly, during transfer molding, until the lead frame has been trimmed. For some applications, it is desirable that the backup battery 32, in addition to being hermetically sealed and having short circuit protection, is also rechargeable so that its charge level can be restored to its rated value after assembly has been completed. In one exemplary embodiment, the battery 32 is a 3.2 volt DC cell having a 12.5 mm diameter. It is essential that the battery 32 be rated for high temperature duty, since it will be exposed to high temperatures during wire bonding and transfer molding. Otherwise, the electrolyte within the battery will evaporate and the battery charge will be destroyed. An example of a suitable battery 32 is a lithium-carbon monofluroide cell which can be obtained from Rayovac Corporation, Part No. BR 1225 UHT. That Rayovac cell is rated at 3.2 volt DC and 35 mAh, has a 70 degree C shelf life of 10 years, and can survive elevated temperature conditions of 225 degrees C for three to five minutes without failure, which is more than adequate for the transfer molding procedure contemplated herein. The battery 32 has a positive terminal 32P and a negative terminal 32N which are insulated with respect to each other by an annular layer of dielectric insulation 32Q. The semiconductor chip 12 is bonded and electrically connected to the negative battery terminal 32N by a conductive deposit of silver-filled epoxy adhesive such as Amicon CT-5047-2. The input/output nodes 14 are electrically connected to selected ones of the conductive fingers 18 by fine gold wires 34 having a diameter of 1.3 mil. Bonding of the gold wires 34 to the conductive fingers 18 and I/O nodes 14 is preferably by the conventional thermosonic ball bonding technique. The positive terminal 32P of the backup battery 32 is electrically attached to the tie bar segments 28A, 28B prior to encapsulation, preferably by resistance welding or by soldering. As can be seen in FIGURE 2, the tie bar segments 28A, 28B are separated by a longitudinal gap, with the positive terminal 32P engaging both tie bar segments, and being centered about the gap. In one fabrication process, the longitudinal gap between the ends of the tie bars 28A, 28B is produced by severing the base support finger lead 28 at its midpoint and thereafter forming the vertically offset tie bar segments 28A, 28B. The vertical offset A of the tie bar segments 28A, 28B permits the backup battery 32 and integrated circuit chip 12 to be centered vertically and longitudinally within the interconnect region 22. Moreover, this arrangement also permits encapsulation of the finger lead assembly, the backup battery, chip and the gold wires 34 completely within the molded body 30. It should be understood, however, that the lead frame material 20 can be selected to have a sufficient ductility so that the tie bar segments 28A, 28B can be integrally formed in a continuous base support segment which is vertically offset with respect to the finger leads 18 and base support finger lead 28. After the battery 32 has been electrically attached to the tie bar segments 28A, 28B, the integrated circuit chip 12 is bonded to the negative battery terminal 32N. The ends of the fine gold wires 34 are then connected between the chip I/O nodes 14 and the respective finger leads 18. A gold wire 34P is bonded between the positive base plate finger lead 28 and the positive backup voltage node 14P of chip 12. The negative backup voltage node 14N is electrically connected to the negative battery terminal 32N by a gold wire 34N. The lead frame assembly 20 is then placed in a multi-cavity split mold. The mold cavity is closed in a transfer molding machine and a non-conductive encapsulant material such as polyphenolene sulfide is injected in fine pellet form from a nozzle. The pressure at which this injection takes place is closely controlled to prevent damage to the gold wire bonds. Under the appropriate pressure and temperature, the pellets melt and flow into channels within the mold and fill the cavities around the lead frame assembly 20, thereby completely encapsulating the lead frame 20, backup battery 32, IC chip 12 and gold wires 34. The resin is cured while still in the mold by the applied heat and pressure. Further curing takes place in an oven. As a result of the foregoing transfer mold procedure, the package 10 is produced in the form of an elongate, generally rectangular molded body 30 of non-conductive material. After removal from the mold, the linking segments 20L between adjacent pins 16 in the lead frame assembly 20 are cut to separate and electrically isolate the pins and conductive finger leads from one another. Additionally, the transport side rails 24, 26 are also cut and separated from the molded assembly. The lead frame 20 material preferably comprises a conventional metal alloy, such as a tin-plated nickel or iron alloy or, alternatively, a tin-plated copper alloy such as CDA 194. It will be appreciated that during assembly, the connector pins and inner conductive leads are structurally interconnected by the linking segments 20L and by the side transport side rails 24, 26, preferably stamped from a continuous metal strip. The connecting sections remain attached to the connector pins for handling purposes only and are severed prior to ultimate use. It will be understood that a selected one of the external pins 16 is adapted for connection to a primary power supply node which provides a voltage V cc which is typically at +5.0 volts DC. Similarly, another external connector pin is adapted for connection to a ground node of a host electronic system for providing a ground-reference GND. Other pins are dedicated for true and complement chip select signals, CS and CS , a signal CLK for synchronously clocking data to and from the monolithic integrated circuit 12, as well as various other I/O signals which are produced by the host electronic circuit. A comparator and switching circuit (not illustrated) compares the voltage V cc from the primary power supply of the host electronic circuit with the voltage of the backup battery 32 and automatically connects the highest detected voltage to power the integrated circuit 12. Referring now to FIGURE 4, FIGURE 5 and FIGURE 6, according to an alternative embodiment of the invention, a semiconductor chip package 40 supports and encapsulates the integrated circuit chip 12 and the backup battery 32, with the IC chip 12 being mounted onto the positive terminal surface 32P of the backup battery 32. A gold wire 34N is electrically connected between the base support finger lead 28 and the appropriate negative battery voltage node 14N, and a gold wire 34P is bonded between the positive backup voltage node 14P of chip 12 and the positive battery terminal surface 32P as shown in FIGURE 6. The negative terminal 32N of the backup battery is electrically connected to the offset tie bar segments 28A, 28B by resistance welds. Except for inversion of the battery 32, the chip package 40 is essentially the same as the package 10 illustrated in FIGURES 1-3. The integrated circuit chip 12 is electrically bonded to the positive battery terminal 32P by a conductive adhesive, for example a deposit of silver-filled epoxy adhesive such as Amicon CT-5047-2. Because of the vertical offset A, the stacked combination of the backup battery 32 and integrated circuit chip 12 is centered vertically and longitudinally within the interconnect region 22. According to this arrangement, the finger lead assembly, the backup battery, chip and gold wires are completely encapsulated within the body of the molded body 30. It will be apparent, therefore, that the chip package 40 differs from the chip package 10 only in that the battery 32 is inverted with respect to the battery orientation of FIGURE 2, and that the package standoff height is the same. Referring now to FIGURE 7, FIGURE 8, FIGURE 9 and FIGURE 10, yet another alternative embodiment of the invention is provided by a semiconductor chip package 50 in which the backup battery 32 is electrically bonded to the tie bar segments 28A, 28B by resistance welds, and the integrated circuit chip 12 is mechanically mounted onto the negative battery terminal 32N by a ceramic coupling substrate 52. In this arrangement, the integrated circuit chip 12 is attached to the ceramic coupling substrate 52 by deposit of conductive epoxy adhesive. The ceramic coupling substrate 52 is bonded to the negative battery terminal 32N by a layer of non-conductive epoxy adhesive. The negative power node 14N on the chip 12 is electrically connected to the negative battery terminal 32N by a via conductor 34V, as illustrated in the enlarged view of FIGURE 10. The via conductor 34V is extended through an aperture 52A which intersects the coupling substrate 52. The purpose of the ceramic coupling substrate 52 is to provide a stable, uniform support surface for the integrated circuit chip 12. Typically, the battery terminal surfaces 32P, 32N are rough and uneven, with the result that uniform seating against the battery surface is difficult to achieve. A smooth, large area contact between the integrated circuit chip and the support surface is needed to avoid the effects of mechanical stress induced into the integrated circuit chip which might damage the LSI circuitry. Additionally, the ceramic substrate 52 should present a bonding surface area which is large enough to provide mechanical coupling for different IC chip sizes. For example, it may be desirable to couple an integrated circuit chip having a coupling surface area larger than the surface area of the negative battery terminal 32N. It will be apparent, therefore, that the chip package 50 differs from the chip package 10 in that the ceramic substrate 52 is interposed between the IC chip 12 and the negative battery terminal 32. The total stacked height of the battery, ceramic substrate and chip 12 remains small enough to be completely encapsulated within the molded body 30. Referring now to FIGURE 11 and FIGURE 12, according to the preferred embodiment of the invention, a semiconductor chip package 60 supports and encapsulates the integrated circuit chip 12 with the positive terminal 32P of the backup battery 32 being mounted onto a base plate support segment 62A of a power lead 62 which is coplanar with the finger leads 18. The advantage of this coplanar configuration is that thermosonic wire bonding can be accomplished with less difficulty as compared with the offset lead frame assembly shown in FIGURE 2 and FIGURE 5. A limitation on the use of the straight, coplanar base plate finger lead 62 is that it produces a slightly thicker encapsulation package 30. Otherwise, the semiconductor chip package 60 is constructed identically to the chip package shown in FIGURE 2. FIGURE 13 and FIGURE 14 illustrate another mounting arrangement in which the negative terminal 32N of the battery 32 is mounted onto the base plate support segment 62A of the straight, coplanar base plate finger lead 62. The construction of the chip package 70 is identical to the construction of the chip package 60 shown in FIGURE 11, except that in FIGURE 13, the battery 32 is inverted with respect to the battery 32 shown in FIGURE 11. Yet another embodiment of the invention is shown in FIGURE 15, FIGURE 16, FIGURE 17 and FIGURE 18 in which a surface mount, dual-in-line molded package 80 is illustrated. In this arrangement, the battery 32 is mounted onto the offset base plate finger lead segments 28A, 28B. Although only finger lead segment 28B is shown in the sectional view of FIGURE 18, it should be understood that the battery 32 is mounted on both finger lead segments in the same manner as shown in FIGURE 2. The gold wires 34 are bonded by thermo-sonic weld bonds onto the corresponding finger leads 18, in the same manner as illustrated in FIGURE 3. In the surface mount assembly 80, the conductive fingers 18 are integrally formed with external J-leads 82 which are preferably of the freestanding, compliant type which have an end portion 82A which is curled under the molded body 30 and is received within a pocket 84. The J-lead 82 also includes a rounded portion 82B which engages a solder land 86. The solder lands 86 are bonded to the surface of an insulating substrate 88. The substrate 88 preferably has a high glass transition temperature (T G ), for example G-30 polyimide, and which has good laminate compliancy, for example as provided by Kevlar R epoxy or Kevlar R polyamide fiber. The solder lands 86 are carefully aligned in a parallel, spaced pattern on the substrate 88 for surface contact by the rounded portions 82B of the J-leads 82. The J-leads 82 are each precoated with solder. A solder joint is then formed at each J-lead/land interface in a batch soldering process, for example by dual-wave reflow soldering. During the reflow soldering process, the surface mount package 80 will be exposed to heat radiation from the solder bath, which may be at or near 363 degrees F, for example the melting point of eutectic SN 63-Pb 36 solder. Heat is transferred to the molded polymer package body 30 by conduction through the J-leads and finger leads, and also by thermal radiation from the solder bath. Consequently, the molded body 30 and the battery 32 are subjected to high temperature levels during the reflow soldering process. According to an important feature of the surface mount embodiment, radiant heat transfer from the solder bath is reflected by a thermally reflective metal layer 90, for example aluminum, copper or nickel. The reflective layer 90 is preferably a thin leaf or foil of polished aluminum which is bonded by an adhesive to the surface mount underside surface 30A of the molded package body 30. Alternatively, the reflective layer 90 is a thin coating of reflective metal particles mixed with an organic bonding material, for example, the 90-8™ reflector coating produced by Bausch & Lomb Incorporated. Although the invention has been described with reference to certain specific embodiments, and with reference to a package which encapsulates and provides backup battery power for an integrated circuit device, the foregoing description is not intended to be construed in a limiting sense. Various modifications of the disclosed premolded battery package as well as alternative applications thereof will be suggested to persons skilled in the art by the foregoing specification and illustrations. It is therefore contemplated that the appended claims will cover any such modifications or embodiments that fall within the true scope of the invention.

Claims: A device package for providing electrical power to an electronic circuit device (12) comprising: a body (30) of non-conductive material; a finger lead assembly (20) encapsulated within said body (30) and including a plurality of conductive finger leads (18) for connection external to said body (30); and a battery (32) encapsulated within said body (30) having a positive polarity power terminal (32P) and a negative polarity power terminal (32N), wherein the electronic circuit device (12) is encapsulated within said body (30) and is electrically coupled to the plurality of conductive finger leads (18), characterised in that said finger lead assembly (20) further includes a power lead (62) wholly contained within said body (30), wherein one of the battery power terminals (32P,32N) is mounted onto and electrically coupled to the power lead (62), the electronic circuit device (12) is mounted onto and electrically coupled to the other of the battery power terminals (32P,32N), and the electronic circuit device (12) is electrically coupled to the power lead (62). The device package of claim 1 wherein the conductive finger leads (18) and the power lead (62) are substantially coplanar with each other. The device package of claim 1 or claim 2 wherein the power lead (62) includes a base support segment (62A) disposed within a finger lead interconnect region and the one of the battery power terminals (32P,32N) is mounted on and electrically connected to said base support segment (62A). The device package of any preceding claim wherein the electronic circuit device (12) has a plurality of input/output nodes and a plurality of wire conductors connecting the input/output nodes to the conductive finger leads (18). The device package of claim 4 wherein the electronic circuit device (12) has a positive power node (14P) and a negative power node (14N), the wire conductors additionally connecting the positive (14P) and negative (14N) power nodes to a respective one of the power lead (62) and the other of the battery power terminals (32N,32P). The device package of any preceding claim further comprising a non-conductive substrate (52) interposed between the electronic circuit device (12) and the one battery power terminal (32N,32P). The device package of claim 6 when dependent on claim 5 wherein the non-conductive substrate (52) has a via aperture (52A), one of the wire conductors extending from the electronic circuit device (12) through said via aperture (52A) to the other of the power terminals (32N,32P). The device package of any preceding claim wherein the negative polarity power terminal (14N) is mounted on and electrically coupled to the power lead (62). The device package of any of claims 1 to 7 wherein the positive polarity power terminal (14P) is mounted on and electrically coupled to the power lead (62). The device package of claim 1 wherein the power lead (28) has a segment offset in a non-coplanar relation to said finger lead assembly (20), wherein the one of the battery power terminals (32P,32N) is mounted onto the offset segment of the power lead (28). The device package according to claim 10 wherein the offset segment of the power lead (28) comprises first (28A) and second (28B) tie bar segments which are separated by a longitudinal gap, said battery (32) being mounted on at least one of said tie bar segments. The device package according to claim 10 wherein said conductive finger leads (18) are spaced about an interconnect region and the offset segment of the power lead (28) includes an offset base support segment which traverses said interconnect region, and one of said battery terminals (32P,32N) is mounted on and electrically connected to said base support segment. The device package according to any one of claims 10 to 12 wherein said electronic circuit device (12) is an integrated circuit implemented on a semiconductor chip, said chip being mechanically mounted upon and electrically connected to said other battery terminal (32N,32P) in stacked relation therewith, said integrated circuit having a plurality of input/output nodes and a plurality of wire conductors connecting said input/output nodes to said conductive finger leads, and having positive (14P) and negative (14N) power nodes electrically connected by said wire conductors to said offset segment of the power lead (28) and to the battery terminal (32N,32P) on which said chip is mounted, respectively. The device package of any one of claims 10 to 13 wherein the negative polarity power terminal (32N) is mounted on and electrically connected to the offset segment of the power lead. The device package of any one of claims 10 to 13 wherein the positive polarity power terminal (32P) is mounted on and electrically connected to the offset segment of the power lead. The device package according to any one of claims 10 to 12 including a non-conductive coupling substrate (52) interposed between said chip and said other battery power terminal (32N,32P). The device package according to claim 16 when dependent on claim 13 wherein said coupling substrate (52) is intersected by a via aperture (52A) with one of said wire conductors being extended from said integrated circuit device through said via aperture (52A) to the battery terminal on which said coupling substrate is mounted. The device package of any preceding claim wherein the electronic circuit device (12) is mechanically mounted upon and electrically connected to the other battery power terminal (32N,32P) in stacked relation thereto. The device package of any preceding claim wherein the electronic circuit device (12) is an integrated circuit implemented as a silicon chip. The device package of any preceding claim wherein said battery (32) is hermetically sealed. The device package of any preceding claim wherein said battery (32) is characterized by an internal resistance which increases non-linearly in response to short circuit current flow. The device package of any preceding claim wherein said battery (32) is rechargeable. The device package of any preceding claim wherein the device package is adapted for surface mount, including a layer (90) of thermally reflective metal attached to the external surface on the surface mount side of said body (30) of non-conductive material. The device package of any preceding claim further comprising a plurality of connector leads (16) projecting externally of the body (30 of non-conductive material and connected electrically to said plurality of conductive finger leads (18). A method for packaging an electronic circuit device (12) and a battery (32) for providing electrical power to said electronic circuit device (12), comprising the steps of: connecting the electronic circuit device (12) to a plurality of conductive finger leads (18) of a finger lead assembly (20); encapsulating the finger lead assembly (20), the electronic circuit device (12), and the battery (32) within a body (30) of non-conductive material; and providing for the connection of the plurality of conductive finger leads (18) external to the body (30) of non-conductive material, characterised in that said method further comprises the steps of: mounting a power terminal (32N,32P) of the battery (32) onto a power lead (62) of the finger lead assembly (20) ; mounting the electronic circuit device (12) onto another power terminal (32P,32N) of the battery (32); and connecting the electronic circuit device (12) to the power lead (62) and the other power terminal (32P,32N) of the battery (32), wherein the power lead (62) is wholly contained within said body (30). The method of claim 25 further comprising the step of: supporting the power lead in a substantially coplanar relation to said finger lead assembly (20). The method of claim 25 further comprising the step of: supporting a segment (28) of the power lead (62) within said interconnect region in a non-coplanar, offset relation to said finger lead assembly (20). The method of claim 27 wherein the step of mounting a power terminal (32N,32P) of the battery (32) onto a power lead (62) comprises mounting said power terminal (32N,32P) onto the offset segment of said power lead (62).

Inventors: QUEYSSAC DANIEL, QUEYSSAC, DANIEL
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS, INC.
Application year: 1991
Main classification: H01L23
IPC codes: H01L25, H05K3, H01L27, H01L23, G11C5