ERROR DETECTING SYSTEM

Abstract: This invention relates to an error detecting system used in digital communications and the like which is intended to reduce the probability that data including errors still is subjected to a speech decoding process to be outputted. Speech data subjected to error detection encoding and error correction encoding is transmitted. Data detected that it has errors upon either of decoding the error correcting code and CRC code inspection is subjected to interpolating process. Thereby, it is eliminated that the data including errors actually is subjected to the speech decoding process as it is.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to an error detection method which is applied to e.g. digital communication. Description of the Related Art Fig. 2 is a flowchart for explaining the prior art error detection. As seen from Fig. 2, on a transmission side, speech is inputted (Step 14) and the speech is encoded (Step 15). The information (a bits) thus obtained is supplemented with an error detection code CRC (cyclic redundancy check code) (b bits) (Step 16). The information of (a + b) bits is encoded with an error correction code (Step 17) to be transmitted as one frame data (Step 18). On a receiving side, the above error correction code is decoded (Step 20) and subjected to a CRC checking (Step 21) to detect an error (Step 22). The data having no error detected during the checking is subjected to a speech decoding processing on the decoded data (Step 23). The data having some error bits detected is subjected to sound processing such as interpolation using a previous frame or muting in place of the above speech decoding (Step 24). Both outputs are synthesized to be outputted as speech (Step 25). However, in the above prior art error detection method, the CRC cannot detect the error in the case where one or more error bits are included in (a + b) bits. Thus, the prior art error detection method cannot provide error detection with high accuracy. For example, when assuming a generator polynomial G (x) represented by G(x) = 1 + x + x 2 + x 4 + x 5 + x 7 and assuming an error pattern represented by a polynomial e(x) = 1 + x 2 + x 8 + x 9 then the above e(x) can be transformed into e(x) = (1 + x + x 2 + x 4 + x 5 + x 7 )(1 + x + x 2 ). In this case, e(x) can be divided by G(x) so that the CRC checking will detect e(x) as a correct pattern. Therefore, although the error as many as 4 (four) bits is included in (a + b) bits, the error detection cannot be made. Another prior art error detection method is described in IEEE Journal on Selected Areas in Communications (1988), Volume 6 February, No. 2, pages 332-345. This describes a method which carries out an initial error detection on an information block and provides for a final error check using protected side information and the CRC. The present invention intends to solve the above conventional problem, and an object of the present invention is to provide an excellent error detection method which can reliably detect the error for the data including the error pattern as mentioned above. According to the present invention there is provided an error detection method comprising: (a) receiving data comprising speech data and a cyclic redundancy checking code encoded in a error correction code, (b) decoding said data, (c) determining whether an error is included in the data encoded in step (b), (d) when no error is detected carrying out an error check on the decoded data, and (e) either decoding the data into speech data or interpolating the data into speech data according to whether or not errors are detected, characterised in that steps (d) and (e) comprise (f) when step (c) determines that no error is included in the data decoded in step (b), performing a CRC check on the data, (g) determining whether an error is included in the data which was CRC checked in step (f), (h) when step (g) determines that no error is included in the data which was CRC checked in step (f), decoding said data which was CRC checked in step (f) into speech data, (i) when step (c) determines that an error is included in the data decoded in step (b), interpolating the data decoded in step (b) into first interpolated data and decoding the first interpolated data into first interpolated speech data, and (j) when step (g) determines that an error is included in the data which was CRC checked in step (f), interpolating the data which was CRC checked in step (f) into second interpolated data and decoding the second interpolated data into second interpolated second speech data. In a form of the method a CRC and an error correction code are selected so as to satisfy the following condition Kmin ≤ Mmax where Kmin represents the minimum value of the number of bits which may be overlooked by the error detection code (CRC) although some error bits is included in (a + b) bits, and Mmax represents the error detection capability (the number of error bits which can be surely detected) of the error correction code. In the above case of G(x) = 1 + x + x 2 + x 4 + x 5 + x 7 , Kmin = 4 so that CRC is combined with the error correction code satisfying Mmax ≥ 4. Further, the error detection in decoding the error correction code as well as the above CRC checking is given to the error detection method. If an error has been detected in decoding the error correction code or in the CRC checking, it is decided that an error is included in the above a bits. Thus the corresponding frame including the a bits is interpolated or sound reproduced from the frame is muted. Thus, the probability of outputting the speech obtained by decoding data which includes the error can be greatly reduced. The present invention has the following advantage in the construction described above. If an error is detected in decoding the error correction code, it is decided that the error is included in the a bits. Therefore, the error which cannot be detected by the CRC checking can be surely detected. Thus, in accordance with the present invention, the probability of outputting the speech obtained by decoding the data as it includes the error can be greatly reduced. The invention will be described now by way of example only, with particular reference to the accompanying drawings. In the drawings: Fig. 1 is a flowchart for explaining the error detection method according to one embodiment of the present invention; Fig. 2 is a flowchart for explaining the prior art error detection method; and Figs. 3A and 3B are views showing exemplary combinations of an error detection code (CRC) and an error correction code in the error detection method. DESCRIPTION OF THE PREFERRED EMBODIMENT Fig. 1 is a flowchart in the case where the error detection method according to one embodiment of the present invention is applied to decoding of encoded speech data. As seen from Fig. 1, on a transmission side, speech is inputted (Step 1) and the speech is encoded (Step 2). The information ( a bits) thus obtained is supplemented with an error detection code CRC (cyclic redundancy check code) (b bits) (Step 3). The information of (a + b) bits is encoded with an error correction code (Step 4) to be transmitted as one frame data (Step 5). On a receiving side, in Step 7, error correction is made on the basis of decoding of the error correction code. In addition, in Step 8, error detection is made. If an error is detected in Step 8, it is decided that the data in the pertinent frame includes an error, and the data is subjected to interpolation processing using a previous frame and speech decoding. Then, the pertinent frame may be muted as the interpolation processing. The data with no error detected in Step 8 is subjected to the CRC checking (Step 9) to detect an error (Step 10). The data with no error detected in Step 10 is subjected to a speech decoding processing on the basis of the above decoded data (Step 11). The data with an error detected in the CRC checking in Step 10 is subjected to the interpolation processing and speech decoding (Step 12). Then, the pertinent frame may be muted as the interpolation processing. Figs. 3A and 3B show exemplary combinations of CRC and an error correction code according to the error detection method of the present invention. In both examples of Figs. 3A and 3B, CRC is adopted as an error detection code in the above generator polynomial: G(x) = 1 + x + x 2 + x 4 + x 5 + x 7 Kmin in this CRC is Kmin = 4. In the example of Fig. 3A, the CRC is combined with a BCH (32, 21) code is used error correction code. If the BCH (32, 21) code is used to correct one error bit and detect 4 (four) error bits, Mmax = 4 which satisfies the condition Kmin ≦ Mmax. In this case, the data of a = 14 bits is supplemented with CRC of 7 (seven) bits. The information bits of 21 bits thus formed are supplemented with 11 (eleven) bits in the BCH (32, 21) code. Now if 4 error bits are included in the information bits of 21 bits, the BCH (32, 21) code can detect an error provided that the checking bits are correct. Therefore, the probability of overlooking error detection in the CRC checking can be reduced. In the example of Fig. 3B, CRC is combined with two Golay (23, 12) codes. If the Golay (23, 12) codes are used to correct 2 (two) or less error bits and detect 4 (four) or less error bits, Mmax = 4 which satisfies the above condition Kmin = Mmax. In the example of Fig. 3B, data composed of 17 bits (a = 17) has a high possibility of generating code errors. As information bits, 12 bits of 17 bits of the data are given to the one Golay code (referred to as Golay #1) whereas the remaining 5 (five) bits and CRC 7 (seven) bits are given to another Golay code (referred to as Golay #2). Further, 11 bits as checking bits are given to each of the Golay codes. In the example of Fig. 3B, it is assumed that an error has been detected in Step 8 in decoding the Golay #1 or the Golay #2, and also 4 error bits are included in (a + b) = 24 bits. In this case, if the error is included in only one of the Golay codes #1 or #2, it can be detected by the Golay code providing that the checking bits are correct. On the other hand, if the error is included on both Golay codes, Mmax = 4 so that even if one or two error bits are included in the checking bits of each of the Golay codes, 4 or less error bits in 23 bits in each of the Golay codes can be surely corrected or detected. In this way, in accordance with the above embodiment, if an error is detected in Step 8 of Fig. 1, the pertinent data is subjected to the interpolation processing using a previous frame without experiencing the CRC checking. The error which cannot be detected by the CRC checking can be surely removed with a strong probability. The probability of outputting the speech obtained by decoding the data that includes an error can be greatly reduced. INDUSTRIAL APPLICABILITY As apparent from the above embodiment, the present invention, which intends to execute error detection based on the error correction code as well as that based on the CRC, has an advantage that the errors which cannot be detected by the CRC, can be surely detected. Thus, the probability of overlooking error detection can be sufficiently reduced so that the probability of outputting the speech obtained by decoding the data that includes an error can be greatly reduced.

Claims: An error detection method comprising: (a) receiving data comprising speech data and a cyclic redundancy checking code (CRC) encoded in a error correction code, (b) decoding said data, (c) determining whether an error is included in the data encoded in step (b), (d) when no error is detected carrying out an error check on the decoded data, and (e) either decoding the data into speech data or interpolating the data into speech data according to whether or not errors are detected, characterised in that steps (d) and (e) comprise (f) when step (c) determines that no error is included in the data decoded in step (b), performing a CRC check on the data, (g) determining whether an error is included in the data which was CRC checked in step (f), (h) when step (g) determines that no error is included in the data which was CRC checked in step (f), decoding said data which was CRC checked in step (f) into speech data, (i) when step (c) determines that an error is included in the data decoded in step (b), interpolating the data decoded in step (b) into first interpolated data and decoding the first interpolated data into first interpolated speech data, and (j) when step (g) determines that an error is included in the data which was CRC checked in step (f), interpolating the data which was CRC checked in step (f) into second interpolated data and decoding the second interpolated data into second interpolated second speech data. An error detection method according to claim 1 in which the received data has been obtained by supplementing encoded speech data with a cyclic redundancy checking code (CRC), encoding the data including said CRC into an error correction code to be transmitted, and transmitting said encoded data. An error detection method according to claim 1 or claim 2, wherein interpolation steps (i) and (j) are performed by muting. An error detecting method according to any preceding claim, wherein step (c) is performed in accordance with said CRC code included in said error correction code to yield a relationship Kmin ≤ Mmax between Kmin (minimum number of error bits which may be overlooked by CRC) and Mmax (maximum error detection capability of the error correction code).

Inventors: HONMA KOUICHI, KATO OSAMU, MIYA KAZUYUKI, HONMA, KOUICHI, KATO, OSAMU, MIYA, KAZUYUKI
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1991
Main classification: H03M13
IPC codes: G11B20, G06F11, H03M13