Liquid crystal display

Abstract: A half-tone pixel (40) having subpixels (41,42,43,44,45) and control capacitors constituting a 100 percent optically active pixel. The subpixel design results in no reductions in the maximum pixel aperture ratio, brightness or contrast, as a pixel with no subpixels would have. Various subpixel layouts including differing numbers of subpixels and subpixel-turn-on sequences may be implemented that result in the entire pixel being optically active.

Description: Field of the Invention The present invention pertains to displays, and particularly, to liquid crystal displays (LCD's). More particularly, the invention pertains to active matrix LCD's having half tone gray scales and high pixel aperture ratios. Background of the Invention LCD technology is being developed as a possible successor to cathode ray (CRT) technology for many applications. LCD technology offers important advantages, such as higher reliability and reduced power, size and weight. However, in the current state of development, LCD image rendering capability falls short of that achievable from the use of CRT's. The present invention addresses one of the major technical obstacles which involves viewing angle and brightness limitations associated with LCD's when they are operated in a gray scale mode. An example of a liquid crystal display unit with grey scale capability is disclosed for example in EP-A-316 708. It is the object of the present invention to devise a liquid crystal display having improved pixel luminance. This object is achieved according to the features of the independent claims. Further advantageous embodiments may be taken from the dependent claims. The invention provides a half-tone greyscale liquid crystal display as claimed in claim 1. The invention implements a half-tone gray scale in the active matrix liquid crystal display (AMLCD). As an example of the related art, gray scale display technology incorporates four subpixels. There is space between the subpixels which is inactive and thus reduces the pixel aperture ratio. In the gray scale or half tone pixel of the present invention, the entire pixel is optically active due to the control capacitor array design of the invention. The invention may incorporate a half tone pixel with subpixels having uniform cell spacing or a half tone pixel having concentric subpixels of different sizes. Brief Description of the Drawings Figure 1 shows a layout of a half-tone pixel according to the related art. Figure 2a and 2b show a layout and the electrical equivalence of the related art half-tone pixel. Figure 3 shows a half-tone pixel according to the invention. Figures 4a and 4b reveal a layout and the electrical equivalent of the half-tone pixel of the invention. Figures 5a, 5b and 5c show a layout of the half tone pixel for uniform cell spacing. Figures 6a, 6b and 6c reveal a layout of a half tone pixel having three concentric subpixels. Figure 7a, 7b and 7c show a layout of a concentric-type half tone pixel having a coupling capacitor. Figure 8 illustrates a cross-section of a display incorporating the half tone pixel configuration of Figure 5. Description of the Preferred Embodiments The present invention incorporates a half-tone approach to the active matrix liquid crystal displays, which is based on the fact that the liquid crystal electro-optic response is essentially independent of the viewing angle when it is operated in a bi-level mode, i.e., either fully on or fully off. A control capacitor approach has been developed to achieve the half-tone gray scale. Such approach involve subdividing the pixel into a number of subpixels, and incorporating a control capacitor in series with each subpixel. Figure 1 shows a layout of a half-tone pixel 12 having four subpixels 14, 16, 18 and 20. Space 22, which is the shaded area between subpixels 14, 16, 18 and 20, is inactive and thus reduces the pixel aperture ratio. Figure 2a reveals greater detail of the construction of the half-tone pixel of Figure 1. Figure 2b is a schematic of the electrical equivalent of the pixel illustrated in Figure 2a. Control capacitors 27, 29 and 31 act as voltage dividers and serve to control the voltage across the liquid crystal subpixels 14, 16, 18 and 20 thereby controlling the number of subpixels that turn on as the source voltage (Vs) of thin film transistor (TFT) 32 is changed to vary the overall gray level of pixel 12. One or more subpixels are either totally on or off. The control capacitor values are determined so that at the most only one subpixel is at a voltage between the threshold and saturation voltages of the liquid crystal to minimize the gray scale errors at off-normal viewing angles. This approach improves the viewing angle behavior of the AMLCD's. Control capacitors 27, 29 and 31 are fabricated either on the active matrix substrate or on the common electrode substrate. The capacitance for each of the control capacitors 27, 29 and 31 is determined according to the area for each of the electrodes of these capacitors. A first layer of indium tin oxide (ITO) 33 which is a transparent and conducting oxide, defines the area of control capacitors 27, 29 and 31. A dielectric film having a controlled thickness, such as silicon nitride or silicon dioxide, serves as the control capacitor dielectric. There is a via 34 in the dielectric so as to eliminate a control capacitor for subpixel 14. A second layer of ITO 35 provides the electrodes of subpixels 14, 16, 18 and 20. Capacitors 24, 26, 28 and 30 represent the incidental liquid crystal display capacitances of subpixels 14, 16, 18 and 20, respectively. Control capacitors 27, 29 and 31 are in series with display capacitances 26, 28 and 30, respectively. A significant problem of the above-mentioned approach is the reduction of pixel aperture ratio (pixel luminance) which reduces the maximum brightness and contrast achievable in the liquid crystal display. Pixel aperture ratio is the sum of the active subpixel areas divided by the total pixel area incorporating the subpixels. The reduction of pixel aperture ratio is due to space 36 between or among subpixels 14, 16, 18 and 20, not being optically active. To increase the aperture ratio, space 36 among the subpixels 14, 16, 18 and 20, is reduced. However, product yield considerations prevent the minimizing of intra-subpixel spacing 36 and thus reducing the aperture ratio loss to satisfactory levels. Further, optically inactive space 36 mandates the use of either a dark matrix between or among subpixels 14, 16, 18 and 20 or a normally dark mode of the AMLCD operation having parallel polarizers. The use of the dark matrix between subpixels 14, 16, 18 and 20, increases the complexity of fabrication of a color filter ray circuit due to the reduction in feature sizes. Alternatively, a lack of normally white mode of the AMLCD panel operation reduces design flexibility and makes optimization for improved image quality impractical. The present invention incorporating a new half-tone pixel design eliminates these deficiencies and obstacles. Figure 3 shows a drawing of a half-tone pixel array according to the invention, having subpixels 41, 42, 43, 44 and 45. Figure 4a shows more detail of half-tone pixel 40 of Figure 3. Figure 4b is a schematic of the electrical equivalent of half-tone pixel 40 of Figure 4a. First ITO layer 46 defines areas for control capacitors 62, 63, 64 and 65. Layer 48 represents the capacitor dielectric. Second ITO layer 50 defines the regions of subpixels 42, 43, 44 and 45. In addition to defining the control capacitor areas, the first ITO layer 46 defines the area of subpixel 41 which is the space between subpixels 42, 43, 44 and 45. Cross-hatched area 48 represents a via and serves to remove the series control capacitor for subpixel 41. Because ITO layers 46 and 50 are separated by dielectric layer 48, layers 46 and 50 can have a slight overlap as shown in Figure 4a. Thus, in this design, there are no restrictions with respect to minimum subpixel spacing due to photolithographic processes, as in related art designs. The fabrication sequence of the control capacitor array of Figure 4 is: 1) deposit, pattern and etch first ITO layer 46, 2) deposit control capacitor dielectric 48, 3) deposit, pattern and etch second ITO layer 50, and 4) pattern and etch a via in dielectric 48 to define subpixel 41. The design of half-tone pixel 40 results in 100 percent of the pixel being optically active. As a result, such design allows implementation of half-tone gray scale using a control capacitor approach with no reductions in the maximum pixel aperture ratio, brightness, and contrast. A feature of the half-tone pixel 40 design of Figures 4a and 4b is that the layout of layers 46, 48 and 50 are such that subpixel 41, having no series control capacitor, is positioned at the intra-subpixel region. Even though Figures 3, 4a and 4b show five subpixels, any number of subpixels may be utilized with the present invention. Since entire pixel 40 is optically active, there is additional flexibility for various subpixel layouts and subpixel turn-on sequences for desired image quality. Figures 5a, 5b and 5c reveal another layout of a half-tone pixel 70. Figure 5a shows a six subpixel design having subpixels 71, 72, 73, 74, 75 and 76. Layer 78 is continuous throughout the pixel except for a small contact via 80 at the subpixel 71 region as illustrated in Figures 5a and 5b. The continuity of layer 78 permits the entire liquid crystal cell or pixel 70 except for the small contact via region 80, to be maintained at the Gooch-Tarry minimum cell spacing, for maximum contrast. Gooch and Tarry derived an optimum value for liquid crystal cell spacing that would result in the best off-state and thus at a maximum contrast. Layers 81 and 82 of ITO are revealed in Figure 5a. The layout of layers 81, 78 and 82 are such that subpixel 71, whose area is defined by ITO layer 81, is positioned at the intra-subpixel region. Figures 6a, 6b and 6c show the layout of a half-tone pixel 90 having three concentric subpixels 91, 92 and 93. Figure 6c shows the electrical equivalent of pixel 90. Layer 96 is continuous in pixel 90 except for small contact via region 100. ITO layers 94 and 98 delineate the control capacitor and subpixel areas, respectively. Figures 7a, 7b and 7c reveal another half-tone subpixel arrangement. Figure 7a shows a halftone pixel 104 having three concentric subpixels 101, 102, and 103. Figure 7b is a cross sectional view of the halftone pixel 104. Figure 7c is a schematic of the electrical equivalent of pixel 104. It includes a coupling capacitor, C c , 106. The role of coupling capacitor 106 is to provide additional flexibility in the choice of the dielectric materials used, and the thickness employed, in the fabrication of control capacitors C₂ and C₃. Figure 8 shows the cross-section for a display employing the control capacitor design shown in Figures 5a-c. Control capacitor array 84 is fabricated along with the TFT array 86 on the same substrate 88. The drain electrode of the TFT 86 is connected to first ITO electrode 81 defining the control capacitor areas of array 84. After active matrix substrate 88 with control capacitor array 84 is fabricated, display assembly 110 is fabricated by sandwiching liquid crystal 112 between active matrix substrate 88 and common electrode substrate 114, using conventional liquid crystal display assembly technologies.

Claims: Halftone grayscale liquid crystal display comprising a plurality of pixels (40, 70, 90, 104), wherein each pixel comprises N-1 subpixels (42-45; 73-75; 91-93; 101-103) defining an intra-subpixel region (48) with at least one of the N-1 subpixels having a double electrode structure consisting of a control capacitor (62-65) and a subpixel display capacitor (52-55) , characterized in that a Nth subpixel (41; 72) is positioned at said intra-subpixel region (48) in order to achieve a 100 percent pixel aperture ratio. Display according to claim 1, wherein each pixel comprises: a first substrate (88); a number N of subpixels (71, 72, 73, 74, 75, 76) wherein each of N-1 subpixels comprises: a first electrode (81) on said first substrate; a layer of dielectric (78) on said first electrode; a second electrode (82) on said layer of dielectric; a layer of liquid crystal (112) on said second electrode; and a third electrode (114) on said layer of liquid crystal; and wherein the Nth subpixel (72) comprises: a first electrode (81) on said first substrate (88); a layer of dielectric (78) on said first electrode (81); a layer of liquid crystal (112) on said layer of dielectric (78); and a second substrate electrode (114) on said layer of liquid crystal (112); and wherein said first electrodes (81) of the N-1 subpixels are interconnected. Display according to claim 2, characterized in that said each of N-1 subpixels (71, 73, 74, 75, 76) are proximate to one another; said Nth subpixel (729 is interspersed between said N-1 subpixels; and said first electrodes (81) of at least one of said N-1 subpixels and of said Nth subpixel are interconnected. Display according to claim 2, characterized in that said each of N-1 subpixels (91, 93) are concentric to one another and to said Nth subpixel (92). Display according to claim 2, further characterized in that said coupling capacitor (106) comprises: a first electrode connected to said first electrode of at least one of said each of N-1 subpixels (102, 103); and a second electrode capacitively connected to said first electrode of said Nth subpixel (101). Display according to claim 1, wherein each pixel comprises: first (42), second (43), third (44), fourth (45) and fifth (41) subpixels; a first glass substrate (88); a first electrode (62) on said glass substrate; a second electrode (63) on said glass substrate; a third electrode (64) on said glass substrate; a fourth electrode (65) on said glass substrate; a fifth electrode (51) situated between said first, second, third and fourth electrodes, respectively, on said glass substrate (88) and proximate to said fifth subpixel; a dielectric layer on said at least first (42), second (43), third (44) and fourth (45) electrodes; a sixth electrode (52) situated on said dielectric layer proximate to said first electrode (62) and said first subpixel (42); a seventh electrode (53) situated on said dielectric layer proximate to said second electrode (63) and said second subpixel (43); an eighth electrode (54) situated on said dielectric layer proximate to said third electrode (64) and said third subpixel (44); a ninth electrode (55) situated on said dielectric layer proximate to said fourth electrode (65) and said fourth subpixel (45); a liquid crystal layer (112) situated on said fifth (51), sixth (52), seventh (53), eighth (54) and ninth (55) electrodes; a tenth electrode on said liquid crystal (114); and a second glass substrate (114) on said tenth electrode. Display according to claim 6, characterized in that said first, second, 8 third, fourth and fifth electrodes (62 - 65, 51) are connected to one another. Display according to claim 7, further characterized by a transistor (TFT, 60) connected to at least one of said first, second, third, fourth and fifth electrodes. Display according to claim 8, characterized in that said first and sixth electrodes (62, 52) form a first control capacitance (C2); said second and seventh electrodes (63, 53) form a second control capacitance (C3); said third and eighth electrodes (64, 54) form a third control capacitance (C4); said fourth and ninth electrodes (65, 55) form a fourth control capacitance (C5); said tenth electrode and sixth electrode form a first liquid crystal capacitance (LC2) of said first subpixel (42); said tenth electrode and seventh electrode form a second liquid crystal capacitance (LC3) of said second subpixel (43); said tenth electrode and eighth electrode form a third liquid crystal capacitance (LC4) of said third subpixel (44); said tenth electrode and ninth electrode form a fourth liquid crystal capacitance (LC5) of said fourth subpixel (45); and said tenth electrode and fifth electrode form a fifth liquid crystal capacitance (LC1).

Inventors: SARMA KALLURI R, SARMA, KALLURI R.
Applicants: HONEYWELL INC, HONEYWELL INC.
Application year: 1991
Main classification: G02F1
IPC codes: G02F1, G09F9