A semiconductor memory having improved latched repeaters for memory row line selection

Abstract: An integrated circuit memory is disclosed which has its memory array divided into blocks, or sub-arrays. Between each sub-array is placed a row line repeater which communicates the row line from the row decoder, or from a prior sub-array, into the next sub-array. The row line repeaters are controlled according to a portion of the column address so that, after the entire selected row has been energized, those row line repeaters which are not associated with the selected sub-array will de-energize the row line at their output. The row line repeaters each include a latch, so that the row line repeater which is associated with the selected sub-array will maintain the selected row line energized. Various embodiments of the row line repeater circuit are disclosed. Further control of the row line repeaters from a power-on reset circuit is also disclosed. A dummy row line is also disclosed, which emulates an actual row line so that the time at which the selected row has been fully energized is more closely known. The dummy row line thus can control the time at which the unselected row line repeaters de-energize their outputs.

Description: This invention is in the field of integrated memory circuits, and is more specifically directed to the selection of memory storage cells therein. This application is related to European Patent Applications Nos EP-A-0 478 251, EP-A-0 478 253 and EP-A-0 478 254 (Attorney's references 69103, 69105, 69106 based on US Serial Nos 588601, 588609, 588600) all contemporaneously filed with this application. Conventional integrated memory circuits, such as random access memories (RAMs), both of the static type (sRAMs) and dynamic type (dRAMs), read-only memories (ROMs), both of the mask-programmed type and of the electrically programmable type (including PROMs, EPROMs, EEPROMs and EAROMs), and other memories such as dual-port RAMs and FIFOs, are generally organized into rows and columns. This row-by-column organization applies both to the physical arrangement of the memory cells in an array, and also to the electrical operation of the memory itself. Certain ones of the address terminals are used in selection of a row of memory cells in the array, and certain others are used in the selection of a column, providing access to one or more memory cells in the selected row. It should be noted that in dRAMs, the row and column addresses are generally time-multiplexed at the device address terminals. Where the number of memory cells is quite large, such as on the order of 2 20 storage locations (i.e., 1 Mbits), the physical size of the memory array accordingly becomes quite large, even when fabricated with state-of-the-art technology which allows feature sizes of less than one micron. Besides the larger physical memory size necessary for such memories, the selection of a row of the memory array results in the activation of a larger number of memory cells. Such activation is generally performed by a row decoder presenting an active logic level on a long conductor commonly referred to as a row line, or word line. The active level on this conductor connects the memory cells in its associated row to their respective bit lines, in effect placing the storage cells in communication with sense amplifiers. The number of memory cells activated for each row, of course, depends upon the storage capacity of the memory and the organization of the memory array. For example, in a "square" 1 Mbit memory array having 1024 columns by 1024 rows, the selection of an entire row activates 1024 memory cells, and connects this number of memory cells to bit lines for the communication of their stored data to a sense amplifier. Accordingly, the power consumption required for the selection and energizing of an entire row of memory cells becomes larger with such higher density memories. In sRAM devices where a single row address may be presented for a relatively long period of time (e.g., for sequential operations to multiple numbers of memory cells in the same row), the active power consumed by the device is quite high. It is therefore desirable to limit the duration for which an entire row is activated. The problem of high active power dissipation is especially acute in memories such as dual-port RAMs and FIFOs. In each of these memory types, selection and simultaneous enabling of two rows of memory cells is often performed in accomplishing simultaneous read and write operations. Accordingly, the active power for such memories, for such simultaneous operations, is double that of a similarly-sized single port RAM. One prior technique for limiting the duration of row line selection is to "time-out" the energizing of the row line, so that after a row is initially accessed, the row line signal is returned to an inactive logic level. Storage of the contents of the memory cells in the row is provided by sense amplifiers in such an arrangement, so that repeated read operations may be performed without requiring that the row line be energized. This technique monitors transitions at the data input terminals, indicative of a write operation, in which case the row line signal is again energized to allow for the writing of data into the memory cells of the selected row. It has been observed that this technique is subject to error in the case where transitions at the data inputs are relatively slow, as such slow transitions may possibly be undetected by the transition detection circuit. In addition, the presence of tri-state conditions on the data bus to which the input terminals are connected may present an erroneous transition to the detection circuit. Another prior technique for limiting power dissipation is the reduction of the active bit line loads served by a particular row line. For example, multiple row decoders may be provided for each "row", so that a combination of the row address and the most significant column address bits selects a row decoder, with the number of memory cells in each selected row reduced. While such a technique reduces the active power, the size of the integrated circuit chip must increase in order to implement additional row decoders. This not only increases the cost of manufacture of the circuit, but also may present problems in fitting the circuit into the desired package size. Another prior technique for selecting a portion of a row line is described in Sakurai, et al., "A Low Power 46 ns 256 kbit CMOS Static RAM with Dynamic Double Word Line", IEEE J. Solid State Circuits, Vol. SC-19, No. 5 (IEEE, October 1984), pp. 578-585. The technique described in this article uses two word lines in accessing each bit, one being a main word line MWL and the other being smaller section word lines SWLs. As shown in Figure 2 of the Sakurai et al. article, the main word line is presented by the row decoder, with NOR gates controlled by the column decoder for driving the section word lines; the NOR gates for each section are connected in parallel relative to each other, all off of the main word line. In this way, only the portion of the row in the selected section is accessed. However, this scheme requires an additional level of conductor, namely a second aluminum layer (see page 579, right hand column, and Table II). Such additional process complexity is, of course, quite costly. In addition, the main word line from the row decoder must remain energized for the full duration of the time that the selected section word line is to remain active. US-A-4583202 discloses a semiconductor memory comprising a plurality of memory cells arranged in rows and columns, and grouped into first and second sub-arrays, a row decoder, a plurality of first row line repeaters and a plurality of second row line repeaters. US-A-4695981 discloses an integrated circuit memory array having a segmented line arrangement using cumulative selection, such that when one enable line is selected, all previous enable lines are selected. Thus no additional word line to the second word line is required. Nogami et al., "A 9ns HIT-Delay 32-Kbyte Cache Macro for Highspeed RISC", IEEE J. Solid State Circuits, Vol. 25, No. 1, Feb. 1990 discloses an on-chip pipelined cache memory including a row decoder, word line select circuitry, and a slave latch with a clocked CMOS inverter acting as pipeline latches between each memory stage. The CMOS inverter includes two series transistors between a positive supply and an output node, and two further series transistors between the output node and a ground supply. The clock and its complement are applied to the transistors adjacent the output node and the outer transistors are supplied with the input signal. It is therefore an object of this invention to provide a memory architecture which provides for reduced power dissipation by limiting the number of memory cells selected after a row line has been energized. It is a further object of this invention to provide such an architecture which does not require additional row decoder circuitry. It is a further object of this invention to provide such an architecture which can be implemented without the audition of another metal, or other conductor, layer. It is a further object of this invention to provide such an architecture which includes latched repeaters which require reduced layout area. It is a further object of this invention to provide such an architecture which includes latched repeaters which have simpler and more stable operation. Other objects and advantages of the invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings. According to a first aspect of the present invention there is provided a semiconductor memory circuit comprising a row line repeater circuit for controlling the selection of a row of memory cells in said memory, comprising a latch, having an input connected to a latch node and having an output driving an output row line of said memory, responsive to said input; a select transistor, having a conduction path coupled in series between said latch node and a reference voltage node, said reference voltage node for receiving a reference voltage at a level such that, when said reference voltage is applied to the input of said latch, said latch places said output row line at a logic level enabling selection of memory cells associated therewith, said select transistor also having a control terminal coupled to an input row line; and a deselect transistor, having a conductive path connected between a bias voltage node and said latch node, and having a control terminal for receiving a reset signal, said deselect transistor being conductive responsive to said reset signal at a first logic level, said bias voltage node for receiving a bias voltage at a level such that, when said bias voltage is applied to the input of said latch, said latch places said output row line at a logic level disabling selection of memory cells associated therewith, wherein said repeater circuit further comprising a discharge transistor, having a conduction path connected in series with the conduction path of said select transistor between said latch node and said reference voltage, and having a control terminal coupled to said reset signal, said discharge transistor being conductive responsive to said reset signal being at a second logic level. According to a second aspect of the present invention there is provided a semiconductor memory circuit comprising a row line repeater circuit for controlling the selection of a row of memory cells in said memory, comprising a latch, having an input connected to a latch node and having an output driving an output row line of said memory, responsive to said input; a select transistor, having a conduction path coupled in series between said latch node and a reference voltage node, said reference voltage node for receiving a reference voltage at a level such that, when said reference voltage is applied to the input of said latch, said latch places said output row line at a logic level enabling selection of memory cells associated therewith, said select transistor also having a control terminal coupled to an input row line; and a deselect transistor, having a conductive path connected between a bias voltage node and said latch node, and having a control terminal for receiving a reset signal, said deselect transistor being conductive responsive to said reset signal at a first logic level, said bias voltage node for receiving a bias voltage at a level such that, when said bias voltage is applied to the input of said latch, said latch places said output row line at a logic level disabling selection of memory cells associated therewith, wherein said reference voltage node is connected to a signal line driven to the logical complement of said reset signal, and wherein the logical complement of a second logic level of said reset signal is the level of said reference voltage. According to a third aspect of the present invention there is provided a semiconductor memory, comprising a plurality of memory cells arranged in rows and columns, and grouped into first and second sub-arrays; means for selecting a row of memory cells in said first sub-array by energizing a first local row line according to a row address value; a plurality of first row line repeaters, each receiving a first local row line at an input, and each presenting at an output a second local row line for selecting a row of memory cells in said second sub-array; characterised by a column decoder, for selecting a sub-array according to a portion of a column address value, said column decoder having a first reset line connected to said selecting means, and having a second reset line connected to said plurality of first row line repeaters, said first and second reset lines indicating, with a first logic level, that the first or second sub-array, respectively is not selected; and by each of said first row line repeaters comprising a latch, having an input and an output, the output of said latch presenting said second local row line; a select transistor having a conduction path, and having a control terminal receiving the associated first local row line so that when the associated first local row line is energized, said select transistor is conductive; coupling and isolating means, receiving said second reset line at an input, for coupling the conduction path of said select transistor in series between the input of said latch and a potential enabling energizing of the second local row line, responsive to the second reset line at its second logic level, and for isolating the input of said latch from said enabling potential, responsive to the second reset line at its first logic level; and de-energizing means for coupling the input of said latch to a potential that de-energizes the second local row line at its output, responsive to said second reset line at its first logic level. The invention may be incorporated into an integrated memory circuit having one or more arrays of memory cells arranged in rows and columns. After selection of a row of memory cells according to a row address, certain ones of the column address bits select the portion of the row to be interrogated, and the row line for the unselected portions of the row is de-energized. A latching repeater is used to maintain the portion of the row line energized, so that the row line on either side of the selected portion can be disabled. The latched repeater is constructed in such a manner that only a single signal (or a signal and its complement) is required to isolate the repeaters after selection of the row lines, and to discharge repeaters associated with unselected sub-arrays. Some embodiments of the invention will now be described by way of example and with reference to the accompanying drawings in which: Figure 1 is an electrical diagram, in block form, of a memory. Figure 2 is an electrical diagram, in schematic form, of a row line in the memory of Figure 1 together with latched repeaters. Figure 3 is an electrical diagram, in schematic form, of a first latched repeater useful in understandinq the invention Figure 4 is a timing diagram illustrating the operation of the latched repeater of Figure 3 in the memory of Figures 1 and 2. Figures 5a and 5b are electrical diagrams, in schematic form, of second and third latched repeaters useful in understanding the invention. Figure 6 is an electrical diagram, in schematic form, of a fourth latched repeaters useful in understanding the invention. Figure 7 is an electrical diagram, in schematic form, of a latched repeater which in a semiconductor memory forms a first embodiment of the invention. Figure 8 is an electrical diagram, in schematic form, of a second latched repeater which in a semiconductor memory forms a second embodiment of the invention. Figure 9 is an electrical diagram, in schematic form, of control circuitry for controlling the latched repeaters. Referring now to Figure 1, a block diagram of an integrated circuit memory 1 incorporating the preferred embodiment of the invention described herein will be discussed. Memory 1 is an integrated circuit memory, for example a static random access memory (SRAM), having 2 20 , or 1,048,576, storage locations or bits. Memory 1 in this example is a wide-word memory, organized as 2 17 , or 128k, addressable locations of eight bits each. Accordingly, for example in a read operation, upon the access of one of the memory locations, eight data bits will appear at the eight input/output terminals DQ. The electrical organization of memory 1, in this example, is 1024 rows of 1024 columns, with eight columns accessed in each normal memory operation. In this example of memory 1, the memory array is divided into eight sub-arrays 12 0 through 12 7 , each of which have 1024 rows and 128 columns. Memory 1 includes seventeen address terminals A0 through A16, for receiving the seventeen address bits required to specify a unique memory address. In the conventional manner, the signals from these seventeen address terminals are buffered by address buffers (not shown). After such buffering, signals corresponding to ten of the address terminals (A7 through A16) are received by row decoder 14, for selecting the one of the 1024 rows to be energized by row decoder 14. Figure 1 illustrates schematically the relative physical location of sub-arrays 12 relative to one another, and relative to row decoder 14. As will be described in further detail hereinbelow, the selection of a row of memory cells in sub-arrays 12 is accomplished by row lines, one of which is driven from row decoder 14 according to the value of the row address at terminals A7 through A16. In an arrangement such as shown in Figure 1 where row decoder 14 is located centrally, with sub-arrays 12 on either side thereof, it is preferred that the most significant column address bit (address terminal A6 in this embodiment) also be decoded by row decoder 14, so that the row line may be energized only on one side of the centrally located row decoder 14, according to this most significant column address bit. The energizing of a row line connects the contents of memory cells to their corresponding bit lines in the conventional manner. Sense amplifiers 13 are provided for sensing and storing the data state on the bit lines in sub-arrays 12. It should be noted that many conventional arrangements and organization of sense amplifiers 13 may be utilized in memory 1 according to the invention, such arrangements including the assignment of one sense amplifier for each bit line pair, or the assignment of one sense amplifier for multiple bit line pairs, with the selection of which bit line pair is to be sensed made by column decoder 18 according to the column address. For purposes of reducing the power consumed during active operation, in this memory only one of the sub-arrays 12 remains energized during each active cycle, with the selection of the sub-array 12 which remains energized determined by the desired memory address (i.e., three bits of the column address). This is done by repeaters 16, which are provided between sub-arrays 12, and also between row decoder 14 and sub-arrays 12 3 and 12 4 . Repeaters 16 pass along the energized state of the selected row line and, as will be described in further detail hereinbelow, latch the energized state of the selected row line for the selected sub-array 12, and de-energize the row line for sub-arrays 12 which are not selected. This arrangement requires that all eight bits of the accessed memory location are to be located in the same sub-array 12. Signals corresponding to the remaining seven address terminals (A0 through A6) are received by column decoder 18 to control repeaters 16 to maintain selection of one of sub-arrays 12 by way of lines RST0 through RST7. Column decoder 18 also selects the desired columns in the selected sub-array 12 responsive to the remainder of the column address value, in the conventional manner. While single lines are indicated for the communication of the address value to row decoder 14 and column decoder 18, it should be noted that, as in many conventional memories, both true and complement values of each address bit may alternatively be communicated from the address buffers to the decoders, for ease of decoding. Further included in memory 1 is input/output circuitry 20, which is in communication with column decoder 18 via an n-bit bus 21, with input/output terminals DQ, with write enable terminal W_, and with output enable terminal OE. Input/output circuitry 20 includes conventional circuitry for providing and controlling communication between input/output terminals DQ and the memory cells selected according to the address value presented to memory 1, and accordingly will not be described in further detail herein. It should be noted that many other alternative organizations of memory 1, relative to the input/output width, and including dedicated rather than common input/output terminals, may also utilize the present invention. Memory 1 further includes timing control circuitry 22, which controls the operation of various portions of memory 1 during a memory cycle in the conventional manner. It should be noted that timing control circuitry 22 is generally not a particular block of circuitry, as suggested by Figure 1, but generally is distributed within memory 1 to control the operation of various portions therein. Timing control circuitry 22 receives, for example, signals from terminal CE which enables and disables the operation of memory 1. It should also be noted that, for some static memories, timing control circuitry 22 may also respond according to a conventional address transition detection circuit (not shown), to control the operation of memory 1 dynamically. It should be noted that such control according to address transition detection is preferred in this embodiment of the invention, as control of repeaters 16 is preferably performed dynamically within a cycle, as will be described further hereinbelow. As shown in Figure 1, line SEL from timing control circuitry 22 is connected to repeaters 16, for control thereof as will be described hereinbelow. Memory 1 further includes a power-on reset circuit 24. Power-on reset circuit 24 receives bias voltage from power supply terminal V cc (as of course do other portions of memory 1 by connections not shown), and generates a signal on line POR indicating that the V cc power supply has reached a sufficient level upon memory I initially powering up, to prevent portions of memory 1 from powering-up in an indeterminate, or undesired, state. As will be described hereinbelow, and as described in copending application S.N. 569,000 (US-A-5115140), filed August 17, 1990, said application assigned to SGS-Thomson Microelectronics, Inc., power-on reset circuit 24 may similarly also control other portions of memory 1, as suggested by the connection of line POR to timing control circuitry 22 in Figure 1. Said copending application S.N. 569,000 (US-A-5115146) also describes preferred configurations of power-on reset circuit 24, although for purposes of this invention conventional power-on reset circuits may also be used. As noted above, for purposes of reducing power consumption, memory 1 according to this embodiment energizes only one of the eight sub-arrays 12, selected according to the three most significant column address bits. In this embodiment, repeaters 16 are present between sub-arrays 12, and also between row decoder 14 and each of sub-arrays 12 3 and 12 4 , for maintaining the application of the energized row line within the selected sub-array 12 and, after a period of time, de-energizing the row line in the other sub-arrays 12. In this way, the column address (particularly the three most significant bits) controls the application of the word line so that only that portion of the word line in the selected sub-array 12 is energized for the entire memory operation cycle. Column decoder 18 also selects eight of the 128 columns in the selected sub-array 12, according to the value of the remaining bits of the column address. In this embodiment, also for purposes of reducing active power consumption, only those sense amplifiers 13 in the selected sub-array 12 which are associated with the desired memory bits are energized. Sense amplifiers 13 so selected by column decoder 18 are then placed in communication with input/output circuitry 20 via bus 21, through which the reading of data from or writing of data to the selected memory cells may be done in the conventional manner. Of course, many alternative organizations of memory 1 may be used in conjunction with the invention described herein. Examples of such organizations would include by-one memories, where a single bit is input to or output from in normal operation. In addition, wide-word memories where each sub-array is associated with one of the input/output terminals, and memories where the entire array is energized during normal operation, may alternatively be used. As mentioned hereinabove, of course, other memory types such as dynamic RAMs, EPROMs, embedded memories, dual-port RAMs, FIFOs, and the like, each with organization of their own, may also benefit from this invention. It should also be noted that other physical and electrical arrangements of the sub-arrays 12 may be alternatively be used with the present invention. For example, two row decoders 14 may be incorporated into memory 1, each of which controls the application of a row line signal into half of the memory. Row decoder or decoders 14 may also be located along one edge of its associated sub-arrays 12, rather than in the middle thereof as shown in Figure 1. It is contemplated that the particular layout of memory 1 will be determined by one of ordinary skill in the art according to the particular parameters of interest for the specific memory design and manufacturing processes. Referring now to Figure 2, the implementation of repeaters 16 in memory 1 will be described in further detail, relative to two rows of memory cells 26 in sub-arrays 12 4 and 12 5 . In this embodiment, memory cells 26 are static RAM cells, consisting of cross-coupled inverters having polysilicon resistor pull-ups, with each memory cell 26 associated with a row line RL and a pair of bit lines BL and BL_ by way of a pair of pass transistors 28. It should be noted that, memory cells 26 may alternatively be dynamic RAM cells of the one-transistor one-capacitor type, FAMOS EPROM cells, or such other storage cells used in the art. Figure 2 shows row lines RL4 1 and RL4 2 , each of which is connected to the gates of n-channel pass transistors 28 so that, with a high level on the selected row line RL4, the pass transistors 28 having their gates connected to the selected row line RL4 will connect their memory cells 26 to bit line pairs BL4 and BL4_ . In sub-array 12 4 , in this example, there are 128 columns, and accordingly pairs of bit lines BL4 0 , BL4 0_ through BL4 127 , BL4 127_ . Sub-array 12 5 is similarly arranged. As noted hereinabove, repeaters 16 each receive a signal on line SEL from timing control circuitry 22 in Figure 1. In addition, each of repeaters 16 41 and 16 42 (as well as all repeaters 16 4 ), receive line RST4 from column decoder 18, and each of repeaters 16 51 and 16 52 receive line RST5 from column decoder 18. Similar lines RST from column decoder 18 similarly control others of repeaters 16 in memory 1. Each of lines RST from column decoder 18 in this embodiment, are generated according to the three most significant bits A6, A5, A4 of the column address, these three bits having the function of selecting the desired sub-array 12. As shown in Figure 2, column decoder 18 either includes or receives true and complement values of each address bit. For selecting sub-arrays 12 4 and 12 5 , the values of column address bits A6, A5, A4 are 100 and 101, respectively. Accordingly, NAND gate 30 4 receives lines A6, A5_ and A4_ at its three inputs, and drives line RST4 accordingly. Similarly, NAND gate 30 5 receives lines A6, A5_, and A4 at its three inputs, for generating line RST5. Of course, only that portion of column decoder 18 useful for controlling repeaters 16 is shown in Figure 2; the remainder of column decoder 18 for selecting the desired bits in the selected rows of sub-arrays 12 is constructed conventionally, according to the desired memory architecture. Referring now to Figure 3, the construction and operation of a first repeater 16 will now be described, relative to the example of repeaters 16 41 through 16 4n . Each of repeaters 16 4 receive a row line RL associated with its row of sub-array 12 4 . In the case of repeaters 16 4 , which are adjacent to row decoder 14, row lines RL are driven directly from row decoder 14. For those repeaters which are not directly adjacent to row decoder 14, the input to each is the row line from the prior repeater 16. For example, the input to each of repeaters 16 5 is the output of a corresponding repeater 16 4 , on row lines RL4. The input row line RL is communicated, for each repeater 16, via n-channel pass gate 32 which has its gate connected to line SEL from timing control circuitry 22. Pass gate 32 is connected to the input of inverter 36, the output of which is connected, via buffering inverter 38, to the output row line RL4, in the example of Figure 3. Inverter 37 has its input connected to the output of inverter 36 and has its output connected to the input of inverter 36, so that a latch is formed by inverters 36 and 37. Inverters 36, 37, and 38 are conventional inverters, such as CMOS inverters. Each repeater 16 also includes n-channel transistor 34, which has its source-to-drain path connected between the input of inverter 36 and ground, and which has its gate controlled by line RST4, in the case of repeaters 16 4 . Inverter 37 preferably has weak drive capability relative to transistor 34, in order that transistor 34 can reset the state of the latch of inverters 36 and 37. In addition, inverter 37 is also preferably weak relative to pass transistor 32, so that the state of the latch may also be rewritten upon the energizing of a row line by row decoder 14. This weak drive may be implemented by using transistors in inverter 37 which have small width-to-length ratios (W/L) relative to that of transistor 34. Similarly, repeaters 16 associated with other sub-arrays 12 will have the gates of their transistors 36 controlled by the appropriate line RST from column decoder 18, as shown in Figure 1. In addition, all of repeaters 16 in this embodiment include pass gates 32 controlled by line SEL from timing control circuitry 22. Referring to the timing diagram of Figure 4, together with Figures 1, 2 and 3, the operation of memory 1 including repeaters 16 will now be described, for the example where row 1 in sub-array 12 5 is selected. At time t 0 , the address terminals A0 through A16 make a transition to the desired memory address, which in this case is row 1 in sub-array 12 5 ; the least significant bits of the column address, i.e., from terminals A0 through A3, are not shown in Figure 4 as they are don't cares for purposes of the operation of repeaters 16. Responsive to the address transition, timing control circuitry 22 issues a high logic level on line SEL at time t 1 , so that pass gates 32 in all of repeaters 16 are conductive at this point in the cycle, allowing for row decoder 14 to drive the selected row line (in this case, row line RL1) therethrough. Also responsive to the beginning of the cycle, all of lines RST preferably go to a high logic level, turning on each of transistors 34 in repeaters 16, which resets all row lines RL to low logic levels prior to the decoding of the row address by row decoder 14. This ensures that only one row line RL is enabled in the new cycle, by ensuring that the row line RL which was enabled in the prior cycle is discharged low. Also at or about time t 1 , preferably prior to or coincident with line SEL going to a high logic level, column decoder 18 presents low logic levels on all lines RST, so that transistors 34 are turned off for all of repeaters 16. This is preferred in order to reduce the row line load for row decoder 14 and inverters 38, so that power dissipation is reduced in the selection of a row and so that the speed of energizing the selected row line RL is not compromised. This may be done by timing control circuitry 22 precharging high all of the address lines A6, A6_, A5, A5_, A4, and A4_ as presented to NAND gates 30. Alternatively, NAND gates 30 in column decoder 18 may also be controlled by timing signals from timing control circuitry 22, so that no transistors 34 are turned on prior to line SEL going to a low logic level. For example, each of lines RST may be generated by gating the output of its associated NAND gate 30 by the signal on line SEL. Responsive to the value of the row address at terminals A7 through A16 selecting row 1, row decoder 14 issues a high logic level on line RL1 at time t 2 , which appears on line RL4 1 at time t 3 , and which appears on line RL5 1 at time t 4 . This similarly ripples through each of repeaters 16, so that all memory cells 26 associated with row 1 are connected to their respective bit line pairs BL and BL_. After a delay time sufficient to guarantee that all memory cells 26 in the selected row have been connected to their respective bit lines by the energizing of row line RL, turning on pass gates 28, line SEL is driven to a low logic level by timing control circuitry 22, occurring at time t 5 of Figure 4. This isolates each of repeaters 16 from its input; for example, repeaters 16 4 of Figure 3 now are isolated from row lines RL from row decoder 14. For selected row 1, in this example, since the entire row line RL 1 has been energized through repeaters 16, a high logic level will be latched and maintained by the operation of inverters 36 and 37 for each of the repeaters 16 associated with row 1. Responsive to the value of column address bits A6, A5, A4 selecting sub-array 12 5 and at a point in time after line SEL has returned to a low level, NAND gate 30 4 issues a high logic level on line RST4 at time t 6 , with NAND gate 30 5 maintaining a low logic level on line RST5. Of course, all other lines RST besides line RST5 will, similarly as line RST4, be at a high logic level responsive to this value of the column address. This state on lines RST (other than line RST5) causes transistors 34 to connect the inputs of inverters 36 in each of repeaters 16 to ground. In the example of sub-array 12 4 , line RST4 is at a high logic level, and transistors 34 in Figure 3 will be on, pulling the input of inverter 36 toward ground. Since transistor 34 is relatively large as compared to the pull-up device in latching inverter 37, the on condition of transistor 34 for row 1 in repeater 16, will cause the latch of inverters 36 and 37 to change state, presenting a low logic level on row line RL4 1 at time t 6 . This causes pass gates 28 for memory cells 26 associated with row 1 in sub-array 12 4 to turn off, reducing the power consumption of memory 1 resulting from the driving of bit lines BL and BL_ in this non-selected sub-array 12 4 . Of course, similar operation occurs for the other non-selected sub-arrays 12. For selected sub-array 12 5 in this example, however, the transistors 34 in repeaters 16 5 are not turned on, since the output of NAND gate 30 5 on line RST5 is at a low logic level. Row line RL5 1 is thus maintained at a high logic level by the operation of inverters 38 therein, with this state latched by the latch of inverters 36 and 37. The memory cells 26 associated with row 1 in sub-array 12 5 thus remain selected, allowing multiple read and write operations to be performed thereto. As described above, prior techniques for the reduction of active power included the timing-out of the selected row line signal RL, after a period of time in which no write activity occurred. While the above-described memory reduces power without such a time-out feature, and without the attendant problems therewith, it should be noted that the time-out feature may be used in combination with the present invention. After the row lines RL in the non-selected sub-arrays 12 are discharged, such a time-out feature may still be used in order to discharge the row line RL for the selected sub-array 12. This could be implemented by way of timing control circuitry 22 presenting a signal to NAND gate 30, for example, which causes line RST to go to a high level. Upon the detection of a transition at terminals DQ, terminal W_, or at the addresses, timing control circuit 22 could then effect the beginning of a new cycle. Alternatively to the operation described above, transistors 34 in the decoding of NAND gates 30 may also be constructed to have a W/L which is small relative to the drive capability of row decoder 14 and pass transistor 32 in series therewith, and of buffering inverters 38. In this arrangement, NAND gates 30 may statically decode the address lines, and present their output on lines RST prior to line SEL returning low. Since transistors 34 are relatively small, as compared to the drive of row decoder 14 in series with pass transistor 32, and to the drive of buffering inverters 38, so long as line SEL is at a high logic level, transistors 34 are incapable of discharging the input of inverters 36 to ground. Therefore, the decoding of the column address value can be done at this time, prior to line SEL isolating repeaters 16, and even prior to the energizing of the selected row line RL. Referring now to Figure 5a, an alternative repeater 16a will now be described. Repeater 16a, as in the case of repeater 16 described hereinabove, includes a pass gate 32 which receives the input row line signal (designated in Figure 5a as row line RL in ) and communicates the same to the input of inverter 36; pass gate 32 has its gate controlled by line SEL from timing control circuitry 22. Also similarly as repeater 16 described hereinabove, repeater 16a of Figure 5a includes a pull-down transistor 34 which is connected between the input of inverter 36 and ground, and which has its gate controlled by the appropriate line RST. Buffering inverter 38 has its input connected to the output of inverter 36 and presents the row line signal at its output, shown here as row line RL out . Repeater 16a according to this embodiment includes a simpler latching arrangement, in this case a p-channel transistor 35 which has its source-to-drain path connected between the input of inverter 36 and V cc , and which has its gate connected to the output of inverter 36. Accordingly, the inverter 37 is reduced to a single p-channel transistor 35, which is preferably smaller than transistor 34 as described hereinabove, so that transistor 34 can pull down the input of inverter 36 when line RST is high. This is due to the recognition that the state of inverter 36 need only be latched in the event when a high logic level is to be presented on line RL out , i.e., when the sub-array 12 associated therewith is selected. No latching is required in repeaters 16 when the associated sub-array 12 is not selected, as transistors 34 discharge the input to inverters 36 in those cases. Referring to Figure 5b, repeater 16a' according to an alternative arrangement will now be described. In repeater 16a', an n-channel latching transistor 35' is provided, having its source-to-drain path connected between the input of inverter 36 and V cc , and having its gate connected to the output of inverter 38. Repeater 16a' may be more efficient to layout than repeater 16a of Figure 5a, since transistors 34 and 35' are both n-channel, and may be included within the same active region. It should be noted that this layout efficiency of repeater 16a' is achieved at a cost of having less than a full V cc level presented to the input of inverter 36, since a threshold voltage drop from V cc is presented by transistor 35' to the input of inverter 36 in repeater 16a'. It is contemplated that the selection between these and other alternatives may be made by one of ordinary skill in the art, depending upon the particular design, layout and processing constraints of the circuit application. It should be noted that the alternatives of Figures 5a and 5b are most appropriately used in clocked memories, especially those with relatively high clocking frequencies. In repeaters 16a and 16a', the input of inverter 36 will be floating for the unselected rows in the selected sub-array 12, since transistors 32 and 34 are off, and since the latching transistors 35 and 35' are off, for unselected rows in selected sub-arrays. Accordingly, so long as the length of time that the input of inverters 36 is floating is limited, such as is the case where the cycle time is relatively short, the alternative arrangements of repeaters 16a and 16a' of Figures 5a and 5b, respectively, allow implementation of the latched repeater with one fewer transistor than that of repeater 16 of Figure 3. Referring to Figure 6, repeater 16b is illustrated. Repeater 16b further includes, in addition to pass transistor 32, discharge transistor 34, and inverters 36 and 38 in the same configuration as in repeaters 16 and 16a. Also provided in repeater 16b is p-channel latching transistor 39 having its source-to-drain path connected between the output of inverter 38 and the input of inverter 36. Transistor 39 is preferably much smaller than transistor 34, so that transistor 34 can pull down the input of inverter 36 when line RST is high. With pass transistor 32 off, and with line RST low, transistor 39 will connect the high level at the output of inverter 38 to the input of inverter 36, latching the selected state onto line RL out . Referring now to Figure 7, a repeater 16c which in a semiconductor memory forms an embodiment of the invention will now be described. Repeater 16c includes a latch comprised of inverter 36 and weak inverter 37, cross-coupled with one another, similarly as repeater 16 of Figure 3. For repeater 16c of Figure 7, no buffering inverter 38 is necessary, due to the inverting operation of the remainder of the circuit as will be apparent from this description. Accordingly, the output of inverter 36 directly drives row line RL out . Repeater 16c further includes p-channel transistor 42, and n-channel transistors 40 and 44, all having their source-to-drain path connected in series between V cc and ground, with n-channel transistor 40 connected in series between transistors 42 and 44. The input of inverter 36 is connected to the drains of transistors 42 and 40; the node at the source of transistor 40 and the drain of transistor 44 is designated in Figure 7 as node N. It should be noted that node N for multiple repeaters 16c associated with the same sub-array 12 may be connected together, so that a single transistor 44 may serve multiple repeaters 16c. The gate of transistor 40 receives row line RL in , and the gates of transistors 42 and 44 receive line RST from column decoder 18. The logic for driving line RST from the column address bits may be the same as that shown in Figure 2 (i.e., NAND gates 30), together with such additional timing logic as required to perform the operation described herein, a preferred example of which will now be described relative to Figure 9. It should be noted that the location of transistors 40 and 44 in series between the input of inverter 36 and ground may be exchanged if desired, i.e., with the drain of transistor 44 being connected to the input of inverter 36 and with the source of transistor 40 being connected to ground. In such an alternative arrangement, the functionality of repeater 16c is equivalent to that of repeater 16c shown in Figure 7. However, transistor 44 may not be shared among multiple repeaters if the locations of transistors 40 and 44 are exchanged from that shown in Figure 7, as such sharing would cause one row line signal RL in to energize all row lines RL out for the sub-array 12 with which the repeaters 16c are associated. The timing of the return of line RST to a low logic level for the repeaters 16c associated with the unselected sub-arrays 12 must be such that the selected row line RL is enabled along its full length prior thereto. As memory devices become larger in density, and especially as the feature sizes such as the physical width of row lines RL become smaller, the RC delay along the row lines RL from row decoder 14 to the far end can be significant. Assurance and control of line RST from timing and control circuitry 22 may be done by modeling and characterization of the row line RC delay, with sufficient delay provided so that line RST does not return to a low logic level too early. In order to reduce the active power consumption as much as possible, however, it is preferable to cause line RST to return to a low logic level as soon as possible. Accordingly, a penalty in active power dissipation results from designing the timing of line RST too conservatively. Referring now to Figure 9, a preferred embodiment of circuitry for actively determining the time at which line RST is to return low, for unselected sub-arrays 12, will be described. In this embodiment, row decoder 14 not only drives the row lines RL, but also drives a dummy row line DRL. Dummy row line DRL is connected to one plate of a number of capacitors 50, each capacitor emulating the gate capacitance of a pass transistor 28 in the memory sub-arrays 12. Preferably, capacitors 50 are implemented with the same geometry and construction as pass transistors 28, with the number of capacitors 50 equalling the number of pass transistors 28 connected to each row line RL in sub-arrays 12. With such equivalent construction, changes in the fabrication process, such as actual feature sizes, will be equally reflected for capacitors 50 as for pass transistors 28. In this construction, the number of capacitors 50 will be equal to the number of pass transistors 28 along the full length of a row (e.g., 1024 capacitors 50 for a half-row of 512 memory cells on one side of row decoder 14 in memory 1 of Figure 1). In addition, the physical characteristics, such as line width, line length, and material, of dummy row line DRL is the same as an actual row line RL, so that the resistance of dummy row line RL is the same as an actual row line RL. Alternatively, a single capacitor having the same capacitance as the pass transistors 28, connected to a resistive line having the same resistance as a row line RL, may be used to conserve layout area. The accuracy of the timing result will depend, for such an alternative, on the accuracy of the single-capacitor single-resistor network to match the RC delay of an actual row line. The end of dummy row line DRL, at the node DRL', is connected to a reset input of a D-type flip-flop 52. The D input of flip-flop 52 is connected to V cc . The clock and complement clock inputs of flip-flop 52 are driven by line SEL, and line SEL inverted by inverter 53, respectively. Line SEL is driven by timing and control circuitry 22, in this embodiment, with similar timing as described hereinabove in Figure 4. The output of inverter 53, with the complementary state of line SEL, is also connected to an input of AND gate 56. The output of each of NAND gates 30 (only one of which is shown in Figure 9) is connected, via inverter 55, to one input of OR gate 54 which has its other input connected to the Q output of flip-flop 52. The output of OR gate 54 is connected to a second input of AND gate 56. In this embodiment, line POR from power-on reset circuitry is connected to one input of AND gate 58, which has its other input connected to the output of AND gate 56. The output of AND gate 58 is line RST for the particular group of repeaters 16c, in this embodiment. The use of power-on reset circuitry 24, indicating on line POR with a high logic level, for example, that power-up has been achieved, with repeaters 16c precludes the selection of multiple row lines RL during power-up. With line POR low during power-up, line RST will be low for all repeaters 16. Referring to Figure 7, this causes all row lines RL out to be at low logic levels, since transistor 42 is turned on for all repeaters 16b, presenting a high logic level at the input of inverter 36 (overcoming weak feedback inverter 37) and causing a low logic level at the output of inverter 36 on all lines RL out . This embodiment of the invention thus actively disables all row lines RL in memory 1 during power-up, preventing the selection of multiple row lines RL and the resulting massive and destructive power dissipation that can result, for example when memory cells 26 having opposite data states are connected to the same bit line pair. It should of course be noted that use of line POR to disable all row lines RL may similarly be incorporated into the embodiment of Figures 3, for example by logically combining the RST lines with line POR so that all transistors 34 in repeaters 16 are turned on during power-up, forcing a low logic level on all row lines. The operation of repeater 16c, controlled according to the preferred embodiment of the control logic in Figure 9, will now be described. At the beginning of a memory cycle in this example, row decoder 14 drives all row lines RL to a low logic level, as is conventional. Also at this time, line SEL goes to a high logic level. This causes line RST (assuming line POR is high) to go to a low logic level for all repeaters 16c, via AND gate 56. This causes transistors 42 in all repeaters 16c to conduct, placing the inputs of all inverters 36 at a high logic level. All row lines RL out driven by repeaters 16c are thus placed into the low, non-enabled, logic state. In addition, a high logic level is clocked into flip-flop 52 by line SEL going to a high logic level. Line SEL then returns to a low logic level which allows the output of AND gate 56 to be determined by the logical OR of the output of flip-flop 52 and NAND gate 30 (inverted). Since a high logic level has been clocked into flip-flop 52, lines RST are driven to a high logic level, turning off transistors 42 and turning on transistors 44. Since all row lines are at a low logic level (either from row decoder 14 or from repeaters 16c), the inputs of all inverters 36 are maintained at a high logic level by the operation of weak inverter 37. After decoding of the row address by row decoder 14, the selected row line RL in is driven to a high logic level. With transistor 44 on and transistor 42 off, transistor 40 will connect the input of inverter 36 for the repeaters 16c associated with the selected row to be discharged to ground through transistors 40 and 44. This will change the state of inverter 36, due to latching inverter 37 being weak relative to transistors 40 and 44, so that a high, enabling, logic level is driven on row line RL out by repeaters 16c associated with the selected row. In the embodiment of Figures 7 and 9, line RST will remain high for all repeaters 16c until such time as dummy row line DRL' remains low, i.e., during the time required for the high logic level to propagate along the length of a full row line. Upon dummy row line DRL' reaching a high logic level, flip-flop 52 will be reset, so that its Q output returns to a low logic level. Accordingly, the output of NAND gate 30 (via inverter 55) will determine the state of line RST. Accordingly, for the non-selected sub-arrays 12, the output of NAND gate 30 is high, which causes line RST to be taken to a low logic level. The repeaters 16c associated with the selected row in non-selected sub-arrays 12 will have the input of their inverters 36 driven to a high logic level, due to transistors 42 in such repeaters 36 being conductive. This causes row lines RL out for non-selected sub-arrays 12 to be de-energized. Conversely, for the selected sub-array 12, line RST remains at a high logic level due to the output of NAND gate 30 being low, so that a high logic level is presented to OR gate 54 (line SEL being low at this time). Transistors 42 in repeaters 16c associated with the selected sub-array 12 thus remain off. If the selected sub-array 12 is adjacent to row decoder 14, row line RL in will continue to be driven high by row decoder 14, so that transistor 40 will remain on to pull down the input to inverter 36 via transistor 44, also remaining on. For the repeater 16c which is associated with the selected row and with a selected sub-array 12 which is not adjacent to row decoder 14, row line RL in will be driven to a low logic level from the prior repeater 16c. This will turn transistor 40 in repeater 16c off, and with transistor 42 also off, weak inverter 37 will maintain the low logic level at the input to inverter 36 so that row line RL out remains at a high, energized, state. As noted hereinabove, it is also desirable to time out the row line RL in the selected sub-array 12, in order to further reduce the power dissipation. Such timing out of the row line may be done according to conventional techniques, such as de-energizing the row line after the sense amplifiers 13 have been clocked, i.e., have sensed and latched the state of the bit lines connected thereto. It is believed that repeater 16c will provide certain advantages relative to repeaters 16, 16a and 16b described hereinabove. First, only one signal line RST is necessary, rather than the two signal lines SEL and RST required for the prior described embodiments. This results in a reduced number of drivers required for memory 1, and accordingly in less layout area (due not only to fewer drivers, but to the reduced number of lines). Secondly, the sequencing of the operation of repeaters 16c is simpler, since isolation of the input node in all repeaters 16 is not required. Third, the circuit is implemented with fewer transistors, especially considering the sharing of transistors 44 among multiple repeaters 16c. Finally, it is believed that repeater 16c provides additional stability of operation, since the potential for source follower action (which is especially sensitive to process variation such as threshold voltage, body effect, and size ratios of p-channel to n-channel transistors) is minimized. Accordingly, the demands on the weak feedback inverter 37 are reduced due to pull-up transistor 42 for the non-selected rows, and heavy crowbar current in repeater 16c is substantially avoided. Referring now to Figure 8, repeater 16d which in a semiconductor memory forms a second embodiment of the invention will be described. Repeater 16d differs from repeater 16c by eliminating n-channel pull-down transistor 44; line RST_ is connected to the source of transistor 40, while line RST is connected to the gate of p-channel transistor 42. Line RST is at a high logic level (and line RST_ is low) responsive to the selection of the sub-array 12 with which the particular repeater 16d is associated. Operation of repeater 16d is similar to that of repeater 16c, with all lines RST going low (and lines RST_ going high) at the beginning of the memory cycle so that all row lines RL out are reset to a low logic level. For the selected row, row line RL in is driven high, turning on transistor 40 and discharging the input of inverter 36 to the low logic level driven on line RST_. After the period of time required for full selection of the memory cells in the selected row, line RST will go to a low logic level for those repeaters 16d associated with non-selected sub-arrays 12. Transistors 42 will turn on for those repeaters 16d, pulling the input of inverters 36 high (overcoming weak inverters 37), and thus placing a low logic level on row lines RL out . For the repeater 16d associated with the selected row and selected sub-array 12, line RST will remain high so that transistor 42 is not turned on. Even if row line RL in goes low, as is the case where repeater 16d is not adjacent row decoder 14, this will allow inverter 37 to maintain a low logic level at the input of inverter 36, so that row line RL out remains high for the selected row in the selected sub-array 12. Of course, if repeater 16d is adjacent row decoder 14, row line RL in may be maintained at a high logic level, with the same output on row line RL out . The alternative embodiment of Figure 8 provides the benefits of repeaters 16c described hereinabove, and may be implemented with one fewer transistor than the alternative of repeaters 16c, although at the cost of an additional line required for line RST. Accordingly, choice between the implementations of repeaters 16c and 16d will depend upon the particular layout constraints of memory 1. For each of the embodiments described hereinabove, the implementation in an integrated circuit having a memory provides for reduced active power dissipation, as the portions of the row line associated with the selected row, but not associated with the selected sub-array, or block, may be turned off. Furthermore, such reduction in power dissipation is achieved while still allowing access to the selected memory cell (and those nearby in the same row), so that a later write operation may be performed without the use of transition detection and the like. Furthermore, the layout impact of additional row decoders is avoided in the embodiments described hereinabove, without double level metallization, or another conductive layer, as required in the case of a main word line connected in parallel with multiple section word lines and decoding, as described in the Sakurai et al. article cited hereinabove. While the invention has been described herein relative to its preferred embodiments, it is of course contemplated that modifications of, and alternatives to, these embodiments, such modifications and alternatives obtaining the advantages and benefits of this invention, will be apparent to those of ordinary skill in the art having reference to this specification and its drawings. It is contemplated that such modifications and alternatives are within the scope of this invention as subsequently claimed herein.

Claims: A semiconductor memory circuit comprising a row line repeater circuit for controlling the selection of a row of memory cells in said memory, comprising: a latch (36,37), having an input connected to a latch node and having an output driving an output row line (RL OUT) of said memory, responsive to said input; a select transistor (40), having a conduction path coupled in series between said latch node and a reference voltage node, said reference voltage node for receiving a reference voltage at a level such that, when said reference voltage is applied to the input of said latch (36,37), said latch (36,37) places said output row line at a logic level enabling selection of memory cells associated therewith, said select transistor (40) also having a control terminal coupled to an input row line (RL IN); and a deselect transistor (42), having a conductive path connected between a bias voltage node and said latch node, and having a control terminal for receiving a reset signal (RST), said deselect transistor (42) being conductive responsive to said reset signal (RST) at a first logic level, said bias voltage node for receiving a bias voltage at a level such that, when said bias voltage is applied to the input of said latch (36,37), said latch (36,37) places said output row line (RL OUT) at a logic level disabling selection of memory cells associated therewith, wherein said repeater circuit further comprises: a discharge transistor (44), having a conduction path connected in series with the conduction path of said select transistor (40) between said latch node and said reference voltage, and having a control terminal coupled to said reset signal (RST), said discharge transistor (44) being conductive responsive to said reset signal (RST) being at a second logic level. A memory circuit according to claim 1, wherein said deselect (42) and discharge (44) transistors are of opposite conductivity type. A semiconductor memory circuit comprising a row line repeater circuit for controlling the selection of a row of memory cells in said memory, comprising: a latch (36,37), having an input connected to a latch node and having an output driving an output row line (RL OUT) of said memory, responsive to said input; a select transistor (40), having a conduction path coupled in series between said latch node and a reference voltage node, said reference voltage node for receiving a reference voltage at a level such that, when said reference voltage is applied to the input of said latch (36,37), said latch (36,37) places said output row line at a logic level enabling selection of memory cells associated therewith, said select transistor (40) also having a control terminal coupled to an input row line (RL IN); and a deselect transistor (42), having a conductive path connected between a bias voltage node and said latch node, and having a control terminal for receiving a reset signal (RST), said deselect transistor (42) being conductive responsive to said reset signal (RST) at a first logic level, said bias voltage node for receiving a bias voltage at a level such that when said bias voltage is applied to the input of said latch (36,37), said latch (36,37) places said output row line (RL OUT) at a logic level disabling selection of memory cells associated therewith, wherein said reference voltage node is connected to a signal line (RST_) driven to the logical complement of said reset signal (RST), and wherein the logical complement of a second logic level of said reset signal (RST) is the level of said reference voltage. A memory circuit according to claim 3, wherein said reset signal (RST) is generated by a column decoder (18). A memory circuit according to any preceding claim, wherein said select and deselect transistors (42,40) are MOS transistors. A memory circuit according to any preceding claim, wherein said latch comprises: first and second cross-coupled inverters (36,37), said second inverter (37) having its output coupled to the input of the latch; and wherein said second inverter (37) has weak drive relative to said deselect transistor (42). A semiconductor memory comprising row line repeater circuitry for controlling the selection of first and second rows of memory cells in said memory, having: a circuit as claimed in claims 1 to 3 wherein said input row line (RL IN) coupled to said select transistor (40) is a first input row line, and a second transistor (40), having a conduction path connected between a second node and said discharge node, and having a control terminal coupled to a second input row line; a second latch (36,37), having an input connected to said second node and having an output driving a second output row line; and a second deselect transistor (42), having a conductive path connected between a bias voltage and said second node, and having a control terminal for receiving said reset signal, said second deselect transistor being conductive responsive to said reset signal at said first logic level, said bias voltage being at a level such that, when applied to the input of said second latch, said second output row line is at a logic level disabling selection of memory cells associated therewith; and means for connecting said discharge node to a reference voltage, said reference voltage being at a level such that, when applied to the input of said first latch, said first output row line is at a logic level enabling selection of memory cells associated therewith. A semiconductor memory, comprising: a plurality of memory cells (26) arranged in rows and columns, and grouped into first and second sub-arrays; means (14,16) for selecting a row of memory cells in said first sub-array by energizing a first local row line according to a row address value; a plurality of first row line repeaters (16), each receiving a first local row line (RL IN) at an input, and each presenting at an output a second local row line (RL OUT) for selecting a row of memory cells in said second sub-array; characterised by:- a column decoder (18), for selecting a sub-array according to a portion of a column address value, said column decoder having a first reset line (RST) connected to said selecting means (16), and having a second reset line (RST) connected to said plurality of first row line repeaters, said first and second reset lines indicating, with a first logic level, that the first or second sub-array, respectively is not selected; and by each of said first row line repeaters comprising: a latch (36,37), having an input and an output, the output of said latch presenting said second local row line (RL OUT); a select transistor (40) having a conduction path, and having a control terminal receiving the associated first local row line (RL in ) so that when the associated first local row line is energized, said select transistor is conductive; coupling and isolating means (44), receiving said second reset line at an input, for coupling the conduction path of said select transistor in series between the input of said latch and a potential enabling energizing of the second local row line, responsive to the second reset line at its second logic level, and for isolating the input of said latch from said enabling potential, responsive to the second reset line at its first logic level; and de-energizing means (42) for coupling the input of said latch to a potential that de-energizes the second local row line at its output, responsive to said second reset line at its first logic level. The memory of claim 8, wherein said column decoder drives said first reset line to the first logic level after the second local row line has been energized for the selected row. The memory of claim 9, wherein said de-energizing means in each of said first row line repeaters comprises: a deselect transistor (42), having a conductive path connected between a first bias voltage and the input to said latch (36,37), and having a control terminal coupled to said second reset line (RST), said deselect transistor being conductive responsive to said second reset line at said first logic level, said first bias voltage at a level such that, when applied to the input of said latch, said latch (36,37) places said second local row line at a logic level disabling selection of memory cells associated therewith. The memory of claim 10, wherein said coupling and isolating means comprises: a connection between the conduction path of said select transistor (40) and the logical complement of said second reset signal (RST_); wherein the voltage of said first logic level, when applied to the input of said latch, causes said latch to place said second local row line at its output in a state enabling selection of memory cells associated therewith. The memory of claim 10 or 11, wherein said coupling and isolating means in each of said plurality of first row line repeaters comprise: a discharge transistor (44) having a conduction path connected in series with the conduction path of its associated select transistor between a second bias voltage and the input of said latch, said second bias voltage being at a level that, when applied to the input of said latch, said latch places said second local row line at its output in a state enabling selection of memory cells associated therewith, and having a control terminal coupled to said second reset line, said discharge transistor being conductive responsive to said second reset line being at a second logic level. The memory of any of claims 8-12, wherein said selecting means comprises: a row decoder (14) for selecting a row of memory cells by energizing a row line according to a row address value; and a plurality of second row line repeaters (16), each comprising: a latch (36,37), having an input and an output, the output of said latch presenting said first local row line; a select transistor (40) having a conduction path, and having a control terminal receiving the associated row line so that when the associated first local row line is energized, said select transistor is conductive; coupling and isolating means, receiving said first reset line at an input, for coupling the conduction path of said select transistor in series between the input of said latch and a potential enabling energizing of the first local row line, responsive to the first reset line at its second logic level, and for isolating the input of said latch from said enabling potential, responsive to the first reset line at its first logic level; and de-energizing means (42) for coupling the input of said latch to a potential that de-energizes the first local row line at its output, responsive to said first reset line at its first logic level. The memory of claim 13, wherein said memory cells are grouped into first, second, third and fourth sub-arrays; and further comprising: a plurality of third row line repeaters (16), each receiving a second local row line at an input, and each presenting at an output a third local row line for selecting a row of memory cells in said third sub-array; and a plurality of fourth row line repeaters (16), each receiving a third local row line at an input, and each presenting at an output a fourth local row line for selecting a row of memory cells in said fourth sub-array; wherein said column decoder also has a third reset line connected to said plurality of third row line repeaters, and a fourth reset line connected to said plurality of fourth row line repeaters, said third and fourth reset lines also indicating, with a first logic level, that the third or fourth sub-array, respectively, is not selected. The memory of any of claims 8-14, wherein the memory cells are random access memory cells. The memory of any of claims 8-15, wherein the memory cells in the selected row are each connected to a bit line responsive to its local row line being energized; and further comprising: a sense amplifier (13) for sensing and latching the data state on the bit lines; and wherein the reset line associated with the selected sub-array is driven to its first logic level responsive to the sense amplifier latching the data state on the bit lines.

Inventors: MCCLURE DAVID CHARLES, MCCLURE, DAVID CHARLES
Applicants: SGS THOMSON MICROELECTRONICS, STMICROELECTRONICS, INC.
Application year: 1991
Main classification: G11C8
IPC codes: G11C11, G11C8, G11C17, G11C16