Method of manufacturing a semiconductor device using bonding wires of different material

Abstract: Disclosed is a semiconductor device comprising a semiconductor integrated chip (11) having at least a power processing circuit (12b) in which larger current flows and a signal processing circuit (12a) in which smaller current flows each having bonding pads (15 and 16), a package having leadframes (14 and 17) on which the semiconductor integrated chip (11) is mounted, and a plurality of bonding wires (15 and 16) with different materials through which the bonding pads (13a and 13b) are joined to the leadframes (14 and 17).

Description: 1. Field of the Invention This invention relates to a method of manufacturing a semiconductor device according to the preamble of claim 1, including semiconductor integrated chips mounted on a package such as a ceramic package or a plastic package, more particularly to a semiconductor devices in which electrodes of the semiconductor integrated chips such as a power processing circuit (a power MOS FET), a signal processing circuit and others are joined to leadframes of the package through a plurality of bonding wires of different materials, for example Au (Gold) wires and Aluminum (Al) wires. A semiconductor device of this kind is known from Patent Abstracts of Japan vol. 7 no. 186 (E-193)(1331). 2.Description of the Prior Art Recently LSI (Large Scale Integration) or VLSI (Very-Large Scale Integration) devices mounted on one chip, as semiconductor devices has been fabricated. Each device comprises a semiconductor integrated circuit with a power element as a power processing circuit which is capable of handling large electrical power and a signal processing circuit for processing signals (digital/analog) dissipating relatively small current. These devices are used for applying to an automobile switch (as called by "IPD" in our Corp.). In such semiconductor devices, an electrical power portion of the chip (as the power processing circuit) for handling approximately several ampere current or more consists of the power MOS FETs or power bipolar transistors, and others. Accordingly, in the prior art, Multi-point wire bonding method is used for wiring multi-point bonding wires at the electrical power portion so as to supply the electrical power to outside of the chip, by which a leadframe of the chip is connected to a bonding pad as an electrode of the electrical power portion. As an example of the multi-point bonding wires formed by the multi-point bonding method in the prior art, for example, there is a following case. Fig. 1 is a schematic diagram showing a bonding pad as a multi-point bonding portion and bonding pads in a signal processing portion (as the signal processing circuit) in the semiconductor device. In the same diagram, the power processing portion 2b and the signal processing portion 2a are formed on a chip 2 mounted on a die pad 1 in a package (not shown). The bonding pads 3a in the signal processing portion 2a in which small current flows are joined to inner lead portions 4 (as leadframes of the package) through bonding wires 5 of Au (Gold) or Cu (Copper) wires of approximately 25 to 50 µm in diameter which are commonly used. While, in the power processing portion 2b or a power portion in the chip 2, the bonding pad 3b is joined to the inner lead portion 8 using the three bonding wires 6 whose diameter are as large as the bonding wires 5 used in the signal processing portion 2a. Thus, in the prior art, the plural bonding wires must be required per pad to be able to flow the larger current in the power processing portion 2b because when one bonding wire is used per bonding pad in the power processing portion 2b, the bonding wire can not flow the amount of the large current, for example several ampere. On the other hand, there are several demerits in Multi-point wire bonding method. For example, the number of the bonding wires to be able to bond the inner lead portion 8 are limited by the size of a capillary which leads the bonding wired 6 to a target portion (in such a case, it is the bonding pad 3b) for bonding, area of innerlead, and others. When the bonding wire of 50 µm in diameter is used for bonding is the bonding pad of 1 x 3 mm 2 in area, the maximum number of the bonding wires is three or four. Accordingly, the current intensity taken out from the power portion 3b is limited by the number of the bonding wires provided at the bonding pad 3b. Thus, the ability of the power portion 2b is limited and reduced by the number of the bonding wires. Moreover, in the multi-point bonding method, the bonding wires are integrated in a small area such as the bonding pad 3b and the leadframe 8 for bonding so that these are short-circuited to each other, then the large short current flows so as to weld these bonding wires. Furthermore, the current intensity taken out from the power processing portion 2b or the balance of the power consumption in the power processing portion 2b are changed by the difference of the portion joined with the bonding wires 6 in the power processing portion 2b or of the interval between the bonding wires 6 so that the power processing portion 2b can not exhibit adequately its ability. In the prior art, the multi-point bonding method is commonly used for bonding of the semiconductor device including the integrated circuit capable of handling large electrical power and the integrated circuit for processing signals having small current. Consequently, the power processing circuit can not exhibit its ability so that the reliability of the semiconductor device is reduced. From Patent Abstracts of Japan vol. 11 no. 31 (E-475) a ball forming method for wire bonding is known, the wire consisting of aluminum, copper or palladium or the alloy of these materials. From EP-0 288 776 a gold alloy wire connection to a bonding pad formed of copper doped aluminum is known. The wire is formed of copper doped gold. From EP-0 418 749 belonging to the prior art according to Article 54(3) EPC an integrated device including signal components as well as power components is provided with connecting wires consisting of different materials. Wires for the power connections are based on aluminum while the wires for the signal connections are gold based. SUMMARY OF THE INVENTION An object of the present invention is to solve the problem in the prior art, as described above, and to provide a semiconductor device having a high reliability including a power processing circuit and a signal processing circuit with the plurality of bonding wires of different materials. According to the invention, this problem is solved by a method of manufacturing a semiconductor device comprising the steps of: mounting a semiconductor integrated chip having at least a power MOSFET or a bipolar transistor and a signal processing circuit processing a signal of a small current, each circuit having bonding pads, on a package having lead frames; and joining said bonding pads to the lead frame through a plurality of bonding wires with different materials wherein the bonding wires used for the signal processing circuit are formed by using a Ball Bonding method or Nail head bonding method and the bonding wires used for the power MOS FET are formed by an Ultrasonic bonding method; characterized in that the bonding wires used for the power MOS FET each consist of an aluminum wire or an aluminum alloy wire; and the bonding wires used for the signal processing circuit each consist of a silver wire or a palladium wire. In the semiconductor device having the above construction, the bonding wires having larger diameters whose material are an Aluminum (Al) or an Al alloy are used in the power processing circuit for bonding the bonding pads to the leadframes. Thereby, the semiconductor device can exhibit its true performance. Moreover, productivity of the semiconductor device can be increased because the failure rate of it is reduced. These and other objects, features and advantages of the present invention will be more apparent from the following description of a preferred embodiment, taken in conjunction with the accompanying drawing. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram showing a bonding pad as a multi-point bonding portion formed by the multi-point bonding method and bonding pads in a signal processing portion in a semiconductor device according to a prior art. Fig. 2 shows a schematic diagram of a semiconductor device useful for understanding present invention in which a bonding pad as an electrodes of a power processing portion is joined to a leadframe of a package by one bonding wire whose material is an Al or an Al alloy. DETAILED DESCRIPTION OF THE EMBODIMENTS Hereinafter, an embodiment of the present invention will be described with reference to the attached drawings. Fig. 2 shows a schematic diagram of a semiconductor device according to the embodiment in which a semiconductor chip 12 is formed on a die pad 11 mounted on a package (not shown) such as a ceramic package or a plastic package having leadframes. The semiconductor chip 12 comprises a signal processing portion 12a made up of bipolar transistors and a power processing portion 12b consists of a power MOS FET. In the signal processing portion 12a, each bonding pad 13a is joined to an inner lead 14 of the leadframe of the package through a bonding wire 15 of approximately 38 µm in diameter whose material is an Au wire. The Au wire has low electrical resistance. While, the power processing portion 12b comprises the power MOS FET whose voltage limit between the source and the drain is more than sixty (60) voltages, whose current is approximately four (4) ampere, and whose ON-resistance is approximately 0.22 Ω. The bonding pad 13b as an output electrode of the power MOS FET is joined to the inner lead 17 as the leadframe of the package through the bonding wire 16 whose material is an aluminum (Al) wire or an Al alloy wire. The Al wire has low electrical resistance and approximately 100-400 µm in diameter. The bonding wires in the signal processing portion 12a are formed using Ball bonding method (Nail head bonding method), which is commonly used. While, the power processing portion 12b is formed by Ultrasonic bonding method so as to form the bonding wire 16 having a relatively larger diameter. These bonding method are widely used so that they are used in order so as to join the bonding pads and the inner leads as the leadframes through the bonding wires 15 and 16. Moreover, in the present invention, because apparatus for fabricating the wire bondings of the signal processing portion 12a and the power processing portion 12b (in which Ball bonding method and Ultrasonic bonding method are used together), are integrated into one apparatus, these wire bonding processes can be carried out without decreasing the productivity. The bonding wire 16 having the construction described above can continuously flow relatively larger current in the power MOS FET. When the maximum output current of the power MOS FET as the power processing portion 12b is approximately eight (8) ampere being twice as large as its continuous output current, one bonding wire 16 of approximately 250 µm in diameter can be used per bonding pad in the power processing portion 12b for the maximum output current. On the other hand, in the prior art, the bonding wire of approximately 50 µm in diameter conventionally used can continuously flow only two or three ampere and is welded by the maximum output current of approximately six (6) ampere. In this case, at least more than three bonding wires are required for the bonding pad in the power MOS FET, as described in the description of the prior art. Comparing the present invention and the prior art about the area of the bonding pad for connecting the bonding wire in the power processing portion, the area for connecting the bonding wire of the present invention is smaller than that of the prior art. Therefore the size of the semiconductor device can be reduced. Moreover, since one pad is joined to one bonding wire in the present invention, poor bonding wires are not yielded so that the reliability of the semiconductor device can be increased. Furthermore, in the prior art, unbalance of the output electrical current caused by the difference of the length of the bonding wires joined to the bonding pad or of the connecting portions of the bonding wires in the power processing portion as the power MOS FET is generated, and unbalance of electric power consumption caused by the difference between the areas of the power processing portion and the signal processing portion is occurred, but they are not generated in the present invention because one bonding wire having larger diameter is joined to one bonding pad in the power processing portion. Accordingly, the reliability of the semiconductor device can be increased. In addition, in the semiconductor device of the present invention, the Al wire as the bonding wire is used for the bonding pad in the power processing portion so that the Al bonding wire having a larger diameter can be joined to the bonding pad without damage of the power MOS FET chip 12b as compared to the Au bonding wires used for the bonding pad 3b in the power processing portion 2b in the prior art. Moreover, as the Al bonding wire is cheaper than the Au bonding wire, the productivity cost of the semiconductor device according to the present invention can be reduced. This invention is not limited to the foregoing embodiment. In particular, it is possible to apply the construction of the embodiment to a chip of an integrated circuit in which bonding pads for a small amount of current and a bonding pads for a large amount of current are incorporated. Furthermore, for example, Silver (Ag), and Palladium (Pd) other than Au can be used for the bonding wire in the signal processing portion 12a. An aluminium alloy can also be used for the bonding wire in the power processing portion as the power MOS FET. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A method of manufacturing a semiconductor device comprising the steps of: mounting a semiconductor integrated chip (11) having at least a power MOSFET (12b) or a power bipolar transistor (12b) and a signal processing circuit (12a) processing a signal of a small current, each circuit having bonding pads, on a package having lead frames (14, 17); and joining said bonding pads (13a, 13b) to the lead frame (14, 17) through a plurality of bonding wires (15, 16) with different materials wherein the bonding wires (15) used for the signal processing circuit (12a) are formed by using a Ball Bonding method or Nail head bonding method and the bonding wires (15) used for the power MOS FET (12b) or the bipolar transistor (12b) are formed by an Ultrasonic bonding method; characterized in that the bonding wires used for the power MOS FET or the power bipolar transistor (12b) each consist of an aluminum wire or an aluminum alloy wire; and the bonding wires used for the signal processing circuit (12a) each consist of a silver wire or a palladium wire.

Inventors: OTA MASAKI, OTA, MASAKI
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: H01L21
IPC codes: H01L21, H01L23