D/A converter

Abstract: This invention is a D/A converter including a preset current source (11), first and second differential switches (12, 13) for selectively deriving an output current of the preset current source in response to complementary signals supplied to control electrodes thereof, and an imaginary short circuit (41) for connecting output portions of current paths of the switches to each other. Variation in the voltage at the time of switching operation of the differential switch can be suppressed by use of the imaginary short circuit with the above construction, thus making it possible to enhance the operation speed.

Description: This invention relates to a digital/analog (D/A) converter of differential current source type having a preset current source (which is the same as a constant current source) and selectively deriving the output of the current source by means of a differential switch. One unit circuit of an ordinary D/A converter (which is hereinafter referred to as a DAC) constituted by MOS transistors is shown in Fig. 1 as an example of a conventional D/A converter of differential current source type. A multi-bit input DAC comprises a plurality of circuits of the type shown in Fig. 1, whose outputs Q are connected together. In Fig. 1, 11 denotes a preset current source (constant current source), and 12 3 and 13 3 denote N-channel MOS transistors constituting differential switches, and the differential switches 12 3 and 13 3 are respectively provided on the dummy side and DAC side (DAC output deriving side). The drain of the transistor 12 3 is connected to a power source V DD , and current outputs Q and Q indicate that a current may flow in one of the DAC output deriving path and the dummy path and no current is permitted to flow in the other current path. Control inputs  and  which are in the inverted relationship (complementary relationship) are digital inputs. The multi-bit input DAC comprises, for example, 16 circuits of the type shown in Fig. 1. This is a 4-bit input DAC. Unlike a ladder resistor voltage dividing system, in this circuit system, a preset current is created according to a reference voltage and current outputs Q and Q are derived by turning on one of the differential switches 12 3 and 13 3 on the DAC side and dummy side in accordance with a decoded input code, thereby obtaining an output. The above differential current system has an advantage that one of the current outputs Q and Q always flows along one of the current paths. Hence, the constant current will not vary and the high speed operation can be attained, provided the outputs Q and Q have the same output impedance. However, with the actual device, since the output impedances of portions for the current outputs Q and Q are different from each other, a voltage (at a node B) of the preset current source 11 and a current (a Q output on the DAC side) transiently vary as shown in Fig. 2 when one of the current paths for Q and Q is changed over to the other current path, and a certain period of time will pass before the voltage at the node B becomes stable, thereby lowering the D/A conversion speed (settling time) and preventing the high speed operation. In order to solve the above problem, the output terminals are provided on the Q and Q sides to make the impedances equal to each other in the prior art, but in this case, the number of terminals is increased, the number of parts used is increased and the cost thereof increases. Further, a means having a previously set impedance in a chip is provided on the Q side, but it is almost impossible to actually detect the correct values of an inductance (L), resistor (R) and capacitor (C) given by an externally attached impedance on the Q side and stably mount the impedance. As described above, in the system in which the constant current is selected and output by means of the differential switch, it is ideal that the current values of Q (DAC side) and Q (dummy side) are equal to each other, but the current at the node B will vary when the current path is changed from the Q side current path to the Q side current path since the output impedances on the current paths are different from each other. An object of this invention is to provide a highspeed D/A converter which comprises a Q switch output section, a Q switch output section, and an impedance-adjusting circuit incorporated in the the Q switch output section, for adjusting the impedance of this section to the value equal to the impedance of the Q switch output section. According to the invention, there is provided a D/A converter comprising a differential current source circuit having a preset current source; and first and second differential switches for selectively deriving output currents of the preset current source in response to complementary signals supplied to control electrodes thereof; characterised by an output impedance adjusting circuit in the form of an imaginary short circuit for connecting output portions of current paths of the switches to each other. That is, according to this invention, the output portions of the first and second differential switches are set into the imaginary short state by use of a differential amplifier so as to make the impedances of the first and second output sides equal to each other. As a result, since the voltage and current of the node between the preset current source and the differential switch will not transiently vary at the time of switching operation, a high speed D/A conversion can be attained. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram showing a conventional D/A converter of differential current source type; Fig. 2 is a diagram for illustrating the operation of the circuit of Fig. 1; Fig. 3 is a circuit diagram showing a circuit according to one embodiment of this invention; Figs. 4 to 6 are circuit diagrams showing circuits according to the embodiments of this invention; and Fig. 7 is a diagram for illustrating the operation of the circuit of Fig. 3. There will now be described an embodiment of this invention with reference to the accompanying drawings. Fig. 3 is a circuit diagram of the embodiment, and this embodiment is an example corresponding to the circuit shown in Fig. 1 and portions which correspond to those of the circuit of Fig. 1 are denoted by the same reference numerals. As shown in Fig. 3, one end of a preset current source (constant current source) 11 is grounded and the other end or node B is commonly connected to the sources of N-channel MOS transistors 12 and 13 serving as differential switches. The gates of the transistors 12 and 13 are connected to receive signals  and  as digital inputs set in the complementary relationship. An output impedance adjusting N-channel MOS transistor 21 is connected between the drain of the transistor 12 on the dummy side path and the Q output terminal (for example, power source V DD ) and an output of a differential amplifier 22 is supplied to the control electrode of the transistor 21. A node between the transistors 12 and 21 is connected to a negative input terminal of the differential amplifier 22 and a node between the transistor 13 on the DAC side path and the Q output terminal (DAC output terminal) is connected to a positive terminal of the amplifier 22. In the circuit of Fig. 3, the drain voltages of the transistors 12 and 13 serving as the differential switches are set equal to each other in the imaginary short state of the differential amplifier 22 so as to adjust the bias voltage of the transistor 21. Therefore, the voltage and current of the node B of the preset current source 11 will not vary at the time of switching operation of the transistors 12 and 13, making it possible to enhance the operation speed. Fig. 3 shows the current drawing type circuit constituted by the N-channel MOS transistors as described above, and Fig. 4 shows a current deriving-out type circuit constituted by P-channel MOS transistors 12 1 , 13 1 , and 21 1 corresponding to the N-channel MOS transistors of Fig. 3, and Fig. 5 shows a current drawing type circuit formed by use of the bipolar-CMOS technique using bipolar transistors 12 2 and 13 2 serving as differential switches and an N-channel transistor 21 2 serving as an output impedance adjusting element to realize this invention. The effects and operations of the circuits shown in Figs. 4 and 5 are the same as that of the circuit shown in Fig. 3, and the output sides of both of the differential switches are set into the imaginary short state by use of the differential amplifier so as to make the impedances of the output sides of the differential switches equal to each other. Fig. 6 shows a circuit having a plurality of units 31 which have no imaginary short circuit and are equivalent to the DAC of Fig. 1, for example, and in which Q outputs are commonly connected and Q outputs are commonly connected. In this example, the total sum output of all of the units is derived at a final output stage by means of the single differential amplifier 22 so as to control a bias voltage applied to the impedance adjusting transistor 21 3 . In this case, 32 denotes a pad from which an analog output is derived and 1 and 1 to 8 and 8 denote digital inputs corresponding to  and  . This invention has the following advantages. The operation of the conventional circuit shown in Fig. 1 is illustrated in Fig. 2. Assuming now that the Q (DAC) terminal has an impedance providing VDD/2 potential thereon, for example, the node B varies as shown in Fig. 2 when the state of the gate input of the differential switch is changed from the state in which  = "H" (high level) and  = "L" (low level, thus conductive in the dummy path) to the state in which  = "L" and  = "H" (thus, conductive in the DAC path). Therefore, time required for the node B to become stable is used as the settling time of the DAC as it is. On the other hand, for example, the operation of the circuit shown in Fig. 3 is illustrated in Fig. 7 corresponding to Fig. 2. That is, since the impedances of the output sides of the differential switches equal each other in the circuit of Fig. 3, the voltage of the node B is substantially the same as that obtained when a current flows in the DAC path, even if a current flows in the dummy path. Due to there being no changes in the voltage at the node B, no time needs to be spent performing the voltage variation shown in Fig. 2. As a result, the operation speed of the D/A conversion can be further enhanced. The circuit shown in Fig. 3 has another advantage over the circuit of Fig. 1. Even if the same impedance as that of the DAC side is provided on the dummy side in the chip, it is extremely difficult to add parasitic L, R and C of the lead frame, socket and the like included in the impedance on the DAC side. In this invention, the impedances on both sides can accord easily and accurately to each other by use of the imaginary short circuit 41 of this invention shown in Fig. 3, thereby making it possible to increase the operation speed of the D/A conversion, reduce the occupied area and enlarge the application range thereof.

Claims: A D/A converter comprising a differential current source circuit having a preset current source (11) ; and first and second differential switches (12, 13) for selectively deriving an output current of said preset current source (11) in response to complementary signals (,  ) supplied to control electrodes thereof; characterized by an output impedance adjusting circuit in the form of an imaginary short circuit (41) for connecting output portions of current paths of said switches (12,13) to each other. A D/A converter according to claim 1 wherein said imaginary short circuit (41) has an impedance adjusting element (21) provided on the output side of a current path of said first differential switch, a control electrode of said impedance adjusting element (21) is connected to an output of a differential amplifier (22), a node between said impedance adjusting element (21) and said first differential switch is connected to a first input of said differential amplifier, and an output terminal of said second differential switch is connected to a second input of said differential amplifier. A D/A converter according to claim 1 or 2, characterized in that said complementary signals are digital inputs and an analog output is derived from the output side of said second differential switch. A D/A converter according to claim 1 or 2, characterized in that said first and second differential switches are formed of MOS transistors to constitute a current drawing type circuit. A D/A converter according to claim 1 or 2, characterized in that said first and second differential switches are formed of MOS transistors to constitute a current deriving-out type circuit. A D/A converter according to claim 1 or 2, characterized in that said first and second differential switches are formed of bipolar transistors to constitute a current drawing type circuit. A D/A converter according to claim 1 further comprising at least one further differential current source circuit (31) having a preset current source and first and second differential switches for selectively deriving an output current of said preset current source in response to complementary signals supplied to control electrodes thereof; said imaginary short circuit connecting output sides of current paths of said first differential switches of said differential current source circuits together and connecting output sides of current paths of said second differential switches together, and having an impedance adjusting element (21 3 ) provided on the output side of the current paths of said differential switches, a control electrode of said impedance adjusting element (21 3 ) connected to an output of a differential amplifier, a node between said impedance adjusting element and the output side common connection node of the current paths of said first differential switches connected to a first input of said differential amplifier, and an output side common connection node of said second differential switches used as an analog output connected to a second input of said differential amplifier.

Inventors: KASAI KAZUHIKO, MATSUO KENJI, NOINE YASUKAZU, KASAI, KAZUHIKO,, MATSUO, KENJI,, NOINE, YASUKAZU,, Kasai, Kazuhiko, c/o Intellectual Prop. Division, Matsuo, Kenji, c/o Intellectual Prop. Division, Noine, Yasukazu, c/o Intellectual Prop. Division
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1991
Main classification: H03M1
IPC codes: H03M1, H03K17