High voltage MOS transistor and production method thereof, and semiconductor device having high voltage MOS transistor and production method thereof

Abstract: A high voltage MOS transistor includes a semiconductor substrate (1) of a first semiconductor type, a gate electrode (14) formed on the semiconductor substrate via a gate oxide layer (13), first and second diffusion regions (15, 16) formed in the semiconductor substrate on both sides of the gate electrode and being of a second semiconductor type opposite to the first semiconductor type, and an electrode (38) which is directly connected to the first diffusion region (15) and is made up of a conductor layer (49) including polysilicon. An impurity concentration of the conductor layer (49) including the polysilicon is higher than an impurity concentration of the first diffusion region (15).

Description: BACKGROUND OF THE INVENTION The present invention generally relates to metal oxide semiconductor (MOS) transistors and methods of producing such MOS transistors, and semiconductor devices having a high voltage MOS transistor and methods of producing such semiconductor devices. More particularly, the present invention relates to a high voltage MOS transistor which is suited for use in a boost part of a dynamic random access memory (DRAM), for example, a method of producing such a high voltage MOS transistor, a semiconductor device having such a high voltage MOS transistor, and a method of producing such a semiconductor device. Document INTERNATIONAL ELECTRON DEVICES MEETING 1987, IEEE, New York, pages 32 - 35, discloses a Si-MOSFET bounded by a field oxide layer and comprising a semiconductor substrate, a gate electrode formed on the substrate, two diffusion regions formed in the substrate and an electrode being directly connected to the diffusion regions and being made of a conductor layer including polysilicon. The impurity concentration of the conductor layer is higher than the impurity concentration of the diffusion regions and the impurity concentration of both diffusion regions is equal since both impurity reagions are formed by the same diffusion step. The edge of the field oxide layer makes complete contact with the solid phase diffusion region of the polysilicon. Furthermore, from document EP-A-0 248 292 a Si-MOSFET is known, wherein the drain region is formed by a low impurity concentration layer and a high concentration layer at the region contacted by an Al - electrode. A channel stopper layer is inserted between the substrate of the MOSFET and a field oxide layer. The channel stopper layer and the diffusion region are separated in order to prevent the withstand voltage from decreasing at the edge of the field oxide layer. However, due to this arrangement it is necessary to provide an alignment margin with respect to the active region when carrying out a patterning process at the time of forming the channel stopper layer. The contact region where the electrode contacts the diffusion region is separated from the field oxide layer in longitudinal direction of the channel of the MOSFET. In DRAMs, the voltage applied to a word line is generally boosted to a voltage greater than or equal to the power source voltage in order to apply a sufficiently high voltage to a capacitor of a memory cell and positively write data. FIG.1 shows an example of a boot strap word line driver circuit for applying the boosted voltage to the word line. As shown, first and second n-type MOS transistors 551 and 552 are connected in series, and a drain d3 of a third n-type MOS transistor 553 is connected to a gate g1 of the transistor 551 at a node A. A boost voltage Vo from a voltage boost circuit (not shown) is applied to a drain dl of the transistor 551 via a terminal 555. A power source voltage Vcc from a power source (not shown) is applied to a gate g3 of the transistor 553 via a terminal 556. An output signal of a decoder (not shown) is applied to a source s3 of the transistor 553 via a terminal 557. The source s3 and the terminal 557 are connected at a node B. A gate g2 of the transistor 552 is coupled to a reset signal line RL via a terminal 558. A source s1 of the transistor 551 and a drain d2 of the transistor 552 are connected at a node D, and the node D is coupled to a word line WL via a terminal 559. A source s2 of the transistor 552 is grounded. When the transistor 553 is selected by the output signal of the decoder and is turned ON, the potential at the source s3 (node B) becomes Vcc. The potential at the drain d3 (node A) becomes Vcc-Vth, where Vth denotes a threshold voltage of the transistor 553. Accordingly, the transistor 551 turns ON, the transistor 553 turns OFF and the drain d3 assumes a floating state. Since the potential at the node A is Vr which is raised greater than or equal to the boost voltage Vo due to the gate capacitance coupling of the transistor 551, the boost voltage Vo at the node D is applied to the word line WL without a voltage drop. For example, Vcc=5 V, Vo=7.5 V, and Vr=14 V. Because the power source voltage Vcc is boosted to Vr and applied to the drain d3 of the transistor 553, a diffusion layer which forms the drain d3 must have a sufficiently high withstand voltage. If the diffusion layer forming the drain d3 does not have a sufficiently high withstand voltage, the potential at the node A gradually falls and it becomes impossible to maintain the voltage applied to the word line WL to Vo. As a method of preventing the voltage drop at the node A, it is conceivable to make a gate oxide layer of the transistor 553 thick. However, this method would go against the recent trend which is to make the gate oxide layer thin in order to reduce the size of the semiconductor device. FIG.2 shows an example of a conventional high voltage MOS transistor having lightly doped drain (LDD) structure. The drain d3 of the transistor 553 is formed by a wide n-type layer 553d which has a relatively low impurity concentration, and the high withstand voltage is realized by increasing a depletion layer which is formed at a junction interface between the n-type layer 553d and a p-type semiconductor substrate 600. In addition, because a drain electrode 601 is normally made of aluminum (Al), the drain d3 is made of an n⁺-type layer 553e having a relatively high concentration at a portion where the drain d3 connects to the drain electrode 601 so as to prevent the contact resistance from becoming high. In FIG.2, the MOS transistor also includes a field oxide layer 602, a gate oxide layer 603 and a boron phospho silicate glass (BPSG) interlayer insulator layer 604. There roughly are two methods of producing the conventional high voltage MOS transistor. According to a first method, a contact hole for the drain electrode 601 is formed with respect to the n⁺-type layer 553e which is formed in advance. On the other hand, according to a second method, an ion implantation is made via a contact hole for the drain electrode 601 so as to form the n⁺-type layer 553e in a self-align manner. The first method described above will now be described with reference to FIG.3. In FIG.3, L₁ denotes a distance between the gate g3 and the n⁺-type layer 553e, L₂ denotes a distance for which the BPSG interlayer insulator layer 604 and the n⁺-type layer 553e overlap, and L₃ denotes a distance corresponding to a width of the contact hole for the drain electrode 601. The withstand voltage of the drain d3 is determined by the distance L₁. However, the contact resistance becomes too large if the n-type layer 553d makes direct contact with the A1 drain electrode 601, and the n⁺-type layer 553e must be provided to make contact with the drain electrode 601. For this reason, there is a limit to reducing the distance L₃ for making the contact. In addition, the drain electrode 601 may make direct contact with the n-type layer 553d if the contact hole is not formed with the margin corresponding to the distance L₂, and there is a limit to reducing the distance L₂. Accordingly, the element spreads laterally by the distance L₁+L₂+L₃ in order to ensure the withstand voltage of the drain d3 which is determined by the distance L₁. In other words, there is a limit to reducing the area occupied by the high voltage MOS transistor. Next, a description will be given of the second method described above, by referring to FIGS.4A through 4C. FIG.4A shows a state where the contact hole is formed in the BPSG interlayer insulator layer 604 and the gate oxide layer 603. FIG.4B shows a process of forming a resist layer 605 and thereafter carrying out an ion implantation to form the n⁺-type layer 553e and an n⁺-type layer 553s which forms the source s3. When carrying out the ion implantation, the impurity ions are also injected at portions indicated by "x" marks due to the positioning margin of the resist layer 605. For this reason, when a process using an HF system etchant is carried out before a process of forming an A1 layer which forms the drain electrode 601, stepped portions 610 are formed as shown in FIG.4C because the portions injected with the impurity ions have a faster etching rate compared to other portions. When the stepped portions 610 are formed, an interconnection layer and the like which are formed thereafter may easily be damaged, and an open circuit may occur in the case of the interconnection layer. This second method forms the n⁺-type layer 553e in the self-align manner, and thus, the distance L₂ can be reduced when compared to the first method. However, there is a limit to reducing the area occupied by the high voltage MOS transistor because the distance L₁+L₂+L₃ is still required. Further, the number of processes required in the second method is larger when compared to that required in the first method. SUMMARY OF THE INVENTION Accordingly, it is a general object of the present invention to provide a novel and useful high voltage MOS transistor, a method of producing the high voltage MOS transistor, a semiconductor device having the high voltage MOS transistor and a method of producing the semiconductor device, in which the problems described above are eliminated. Another and more specific object of the present invention is to provide a high voltage MOS transistor comprising a semiconductor substrate of a first conductivity type, a gate electrode formed on the semiconductor substrate via a gate oxide layer, first and second diffusion regions formed in the semiconductor substrate on both sides of the gate electrode and being of a conductivity type opposite to the first conductivity type, and an electrode which is directly connected to the first diffusion region and is made of a conductor layer including polysilicon with an impurity concentration of the conductor layer including the polysilicon being higher than the impurity concentration of the first diffusion region, the MOS transistor being bounded by a surrounding field oxide layer formed on the substrate, wherein the impurity concentration of the first diffusion region is smaller than that of the second diffusion region and the contact region where the electrode is contacting the first diffusion region is formed spatially separated from the field oxide layer. According to the high voltage MOS transistor of the present invention, the drain/source region of the relatively low impurity concentration makes direct contact with the drain/source electrode, and, thus, it is possible to reduce the size of the high voltage MOS transistor. Furthermore, the first diffusion region is formed solely by a diffusion region with a relatively low impurity concentration and, thus, an additional process step is saved. In addition, since the doped polysilicon is used for the drain/source electrode, it is possible to prevent the contact resistance between the drain/source region and the drain/source electrode from increasing and also realize a high withstand voltage. Still another object of the present invention is to provide a method of producing a high voltage MOS transistor comprising the steps of selectively forming a field oxide layer on a semiconductor substrate of a first conductivity type, successively forming a gate oxide layer and a gate electrode on a region of the semiconductor substrate defined by the field oxide layer, forming first and second impurity regions of a second conductivity type opposite to the first conductivity type in the semiconductor substrate on both sides of the gate electrode by a first ion implantation, and forming a conductor layer directly on at least the first impurity region so as to form an electrode with the conductor layer including polysilicon with an impurity concentration higher than that of the first impurity region, comprising the additional steps of covering the first impurity region by a mask layer, and increasing the impurity concentration of the second impurity region higher than the impurity concentration of the first impurity region by a second ion implantation using the field oxide layer, the gate electrode and the mask layer as masks, wherein a contact region where the electrode makes direct contact with the first diffusion region is arranged so as to make no contact with the field oxide layer. A further object of the present invention is to provide a semiconductor device having a high voltage MOS transistor as described above, wherein a plurality of elements are formed on the semiconductor substrate and the conductor layer including the polysilicon also forms an interconnection layer which connects to at least one of the elements. Another object of the present invention is to provide a method of producing a semiconductor device having at least a high voltage MOS transistor as described above and a second MOS transistor which forms a memory cell formed on a semiconductor substrate which is of a first conductivity type, the method comprising the steps of selectively forming a field oxide layer on the semiconductor substrate, successively forming gate oxide layers and gate electrodes on the semiconductor substrate in regions defined by the field oxide layer, and forming impurity regions of a second conductivity type opposite to the first conductivity type in the semiconductor substrate on both sides of the gate electrodes by a first ion implantation, further comprising the steps of covering the impurity regions of the second MOS transistor forming a memory cell and the first impurity regionof the high voltage MOS transistor by a mask layer, increasing an impurity concentration of a second impurity region of the high voltage MOS transistor higher than the impurity concentration of the first impurity region by a second ion implantation using the field oxide layer, the gate electrode of the high voltage MOS transistor and the mask layer as masks, and forming a conductor layer directly on at least a portion of the first impurity region so as to form an electrode, wherein the conductor layer includes polysilicon with an impurity concentration higher than that of the first impurity region. Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG.1 is a circuit diagram showing an example of a boot strap word line driver circuit; FIG.2 is a cross sectional view showing an example of a conventional high voltage MOS transistor having a LDD structure; FIG.3 is a cross sectional view for explaining a first conventional method of producing the high voltage MOS transistor; FIGS.4A through 4C are cross sectional views for explaining a second conventional method of producing the high voltage MOS transistor; FIG.5 is a cross sectional view for explaining an operating principle of a high voltage MOS transistor according to the present invention; FIG.6 is a diagram comparing a characteristic of the high voltage MOS transistor according to the present invention with characteristics of the conventional high voltage MOS transistors produced by first and second conventional methods; FIGS.7A and 7B respectively are a cross sectional view and a circuit diagram showing a first embodiment of a semiconductor device according to the present invention; FIG.8 is a diagram showing a relationship of an impurity dosage of polysilicon and a contact resistance between an electrode and an n⁻-type diffusion layer; FIG.9 is a cross sectional view showing a first embodiment of the high voltage MOS transistor according to the present invention; FIG.10 is a cross sectional view showing an essential part of the first embodiment of the high voltage MOS transistor on an enlarged scale; FIGS.11A through 11G are cross sectional views for explaining a first embodiment of a method of producing the semiconductor device according to the present invention; FIGS.12A through 12D are cross sectional views for explaining a second embodiment of the method of producing the semiconductor device according to the present invention; FIG.13 is a cross sectional view showing an essential part of a second embodiment of the high voltage MOS transistor on an enlarged scale; FIG.14 is a cross sectional view showing a third embodiment of the high voltage MOS transistor according to the present invention; FIG.15 is a diagram showing a relationship of a distance d2 and a withstand voltage on the side of the n⁻-type diffusion layer; FIGS.16A and 16B respectively are a cross sectional view and a plan view showing an essential part of a fourth embodiment of the high voltage MOS transistor according to the present invention; FIG.16C is a plan view showing an essential part of a fifth embodiment of the high voltage MOS transistor according to the present invention; FIG.17 is a cross sectional view showing an essential part of a second embodiment of the semiconductor device according to the present invention; FIGS.18A and 18B are cross sectional views for explaining a first embodiment of a method of producing the high voltage MOS transistor according to the present invention; FIG.19 is a cross sectional view for explaining a second embodiment of the method of producing the high voltage MOS transistor according to the present invention; FIG.20 is a cross sectional view for explaining a third embodiment of the method of producing the high voltage MOS transistor according to the present invention; FIG.21 is a cross sectional view for explaining a fourth embodiment of the method of producing the high voltage MOS transistor according to the present invention; FIGS.22A and 22B are cross sectional views for explaining a third embodiment of the method of producing the semiconductor device according to the present invention; and FIGS.23A and 23B are cross sectional views for explaining a fourth embodiment of the method of producing the semiconductor device according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a description will be given of an operating principle of a high voltage MOS transistor according to the present invention, by referring to FIG.5. The high voltage MOS transistor shown in FIG.5 includes a semiconductor substrate 1 of a first semiconductor type, a gate oxide layer 13, a gate electrode 14, a drain/source region 15 which is made of a second semiconductor type with a relatively low impurity concentration, a source/drain region 16 of a second semiconductor type with a relatively high impurity concentration, a contact hole 29 for a source/drain electrode, a contact hole 29 for a drain/source electrode, a source/drain electrode 35, a drain/source electrode 38, and an interlayer insulator layer 27. The source/drain electrode 35 and the drain/source electrode 38 made up of a second semiconductor type conductor layer 49 which includes polysilicon and has an impurity concentration which is higher than that of the source/drain region 15. The first and second semiconductor types are mutually opposite semiconductor types, and for example, the first semiconductor type is the p-type and the second semiconductor type is the n-type. The drain/source of the MOS transistor is formed solely of the drain/source region 15 which is made of the second semiconductor type with the relatively low impurity concentration. The drain/source electrode 38 makes direct contact with the drain/source region 15, and not indirectly via a region of the second conductor type with a relatively high impurity concentration. For this reason, the distance L₂ which is required according to the conventional methods described above may be eliminated in the present invention, thereby making it possible to further reduce the size of the MOS transistor. The drain/source electrode 38 connects directly to the drain/source region 15 which is made of the second semiconductor type with the relatively low impurity concentration. However, the drain/source electrode 38 is not made of Al, but is made of the second semiconductor type conductor layer 49 which includes polysilicon. Hence, the contact resistance does not become large at the part where the drain/source electrode 38 makes contact with the drain/source region 15. In addition, because the drain/source region 15 is thin, the spike of Al would become a problem if an Al electrode were formed directly on the drain/source region 15, but the problem of the Al spike will not occur in the present invention because the drain/source electrode 38 does not use Al. Furthermore, compared to the contact between Al and silicon (Si), the contact between polysilicon and Si can be made at a lower impurity concentration. Since the withstand voltage of the transistor is larger for smaller impurity concentrations, the present invention can more easily increase the withstand voltage of the transistor compared to the conventional transistors. When the drain/source region 38 is made of the second semiconductor type conductor layer 49 including polysilicon, the impurities within the conductor layer 49 diffuses into the drain/source region 15 to a shallow depth due to solid phase diffusion because it is sufficient for the drain/source region 38 to have the relatively low impurity concentration in the view point of contact resistance In addition, it is possible to realize a withstand voltage which is higher than that obtainable in the conventional transistors, because a boundary between the drain/source region 15 having the relatively low impurity concentration and the shallow portion having the slightly higher impurity concentration caused by the solid phase diffusion is gradual. FIG.6 shows the characteristic of the high voltage MOS transistor according to the present invention in comparison with the characteristics of the conventional high voltage MOS transistors which are produced by the first and second methods. In FIG.6, the ordinate indicates the impurity concentration in a log scale, and the abscissa indicates a direction x in FIGS.2, 4C and 5. Dotted lines I and II respectively indicate the characteristics of the high voltage MOS transistors produced by the first and second methods, and a one-dot chain line III indicates the characteristic of the high voltage MOS transistor according to the present invention. Next, a description will be given of a first embodiment of the high voltage MOS transistor according to the present invention, by referring to FIGS.7A and 7B. FIGS.7A and 7B respectively show the cross section and the circuit diagram of the first embodiment of the high voltage MOS transistor. A p-type semiconductor substrate 1 made of Si or the like has a plurality of elements including n-type MOS (nMOS) transistors formed thereon. A boot strap word line driver circuit 2 for applying a voltage to a word line WL includes three nMOS transistors 3, 4 and 5. The first and second MOS transistors 3 and 4 are connected in series, and the drain layer 15 of the third MOS transistor 5 is connected to a gate electrode 7 of the first MOS transistor 3. The first MOS transistor 3 includes the gate electrode 7 which is formed on the semiconductor substrate 1 via a gate oxide layer 6, and source and drain layers 8 and 9 which have an LDD structure including n⁺ and n⁻ regions and are formed on respective sides of the gate electrode 7. The second MOS transistor 4 includes a gate electrode 11 which is formed on the semiconductor substrate 1 via a gate oxide layer 10, and source and drain layers 12 and 113 which have an LDD structure including n⁺ and n⁻ regions and are formed on respective sides of the gate electrode 11. The drain layer 113 is provided integrally to the source layer 9 of the first MOS transistor 3, and thus, the first and second MOS transistors 3 and 4 are connected in series. The third MOS transistor 5 includes a gate electrode 14 formed on the semiconductor substrate 1 via a gate oxide layer 13, an n⁻-type diffusion layer 15 formed on one side of the gate electrode 14, and a diffusion layer 16 having an LDD structure formed on the other side of the gate electrode 14. The n⁻-type diffusion layer 15 is connected to the gate electrode 7 of the first MOS transistor 3 via an interconnection electrode (not shown). A fourth MOS transistor 18 forms a stacked capacitor type DRAM cell 17. Similarly to the three MOS transistors 3 through 5, the fourth MOS transistor 18 includes a gate electrode 21 formed on the semiconductor substrate 1 via an insulator layer 20, and n or n⁻ type diffusion layers 22 and 23 formed on respective sides of the gate electrode 21. The diffusion layer 22 is connected to a bit line BL, and the gate electrode 21 is connected to the word line WL. A capacitor 19 of the DRAM cell 17 is formed on the diffusion layer 23 via a contact hole 34 which will be described later. The capacitor 19 has a stacked structure in which a storage electrode 24 which is made of polysilicon doped with n-type impurity ions such as phosphor (P) ions, a dielectric layer 25 made of silicon dioxide (SiO₂), and a confronting electrode 26 which is made of polysilicon including n-type impurity ions are successively stacked. A voltage Vcc/2 is applied to the confronting electrode 26. An interlayer insulator layer 27 made of PSG or the like is formed on the first through fourth MOS transistors 3 through 5 and 18. Contact holes 28 through 33 are formed in the interlayer insulator layer 27 so as to expose the diffusion layers 8, 9, 15, 16 and the like. Electrodes 35 through 40 are formed to fill the contact holes 28 through 33. These electrodes 35 through 40 are made of polysilicon doped with impurities of the same impurity type as the source layers 9 and 12 and the drain layers 8 and 13. In addition, an electrode 41 is similarly formed on the diffusion layer 22 of the fourth MOS transistor 18. A field oxide layer 42 is formed around the periphery of the first through third MOS transistors 3 through 5 and in the periphery of the DRAM cell 17 by a selective oxidation such as local oxidation of silicon (LOCOS). In this embodiment, the power source voltage Vcc is first applied to the gate electrode 14 of the third MOS transistor 5 when writing data into the DRAM cell 17. When an output signal of a decoder (not shown) is input to the n⁺-type diffusion layer 16 of the third MOS transistor 5, the potential of this n⁺-type diffusion layer 16 becomes Vcc. Accordingly, the potential of the n⁻-type diffusion layer 15 becomes Vcc-Vth, where Vth denotes the gate threshold voltage. As a result, the first MOS transistor 3 turns ON, the third MOS transistor 5 turns OFF, and the n⁻-type diffusion layer 15 is raised to a voltage higher than the boost voltage Vo due to the capacitance coupling of the first MOS transistor 3. Therefore, the boost voltage Vo is applied to the drain layer 9 of the first MOS transistor 3 and to the word line WL without a voltage drop. Hence, the boost voltage Vo is applied to the gate electrode 21 of the fourth MOS transistor 18 via the word line WL. The fourth MOS transistor 18 which is selected by a bit selection signal from the bit line BL turns ON, and a charge is stored in the capacitor 19 which is connected to the fourth MOS transistor 18. In this case, the data is written in the DRAM cell 17. When the boost voltage Vo which is higher than the power source voltage Vcc is applied to the drain layer 8 of the first MOS transistor 3, the potential at the gate electrode 7 of the first MOS transistor 3 is raised by the capacitance coupling to a voltage which is approximately two times the boost voltage Vo. For this reason, the double-boosted voltage is also applied to the n⁻-type diffusion layer 15 of the third MOS transistor 5. However, since the n⁻-type diffusion layer 15 of the third MOS transistor 5 has the relatively low impurity concentration, the withstand voltage is high with respect to the semiconductor substrate 1. In addition, the n⁻-type diffusion layer 15 is made up solely of the layer having the relatively low impurity concentration, and does not have a layer having the relatively high impurity concentration. Hence, the area occupied by the element (third MOS transistor 5) does not become large. Furthermore, the electrode 38 formed on the n⁻-type diffusion layer 15 is made of the polysilicon which includes the impurities of the same impurity type as the n⁻-type diffusion layer 15. For this reason, it is possible to carry out an annealing to diffuse the impurities within the electrode 38 into the shallow portion of the n⁻-type diffusion layer 15 and reduce the contact resistance. FIG.8 shows the relationship of the impurity dosage of the polysilicon and the contact resistance between the electrode 38 and the n⁻-type diffusion layer 15. In FIG.8, the ordinate indicates the resistance in log scale, and the abscissa indicates the impurity dosage in log scale. The relationship shown in FIG.8 is obtained for a case where the polysilicon electrode 38 has a thickness of 200nm (2000 Å) and the impurity dosage of the n⁻-type diffusion layer 15 is 1 x 10¹³/cm². It may be seen from FIG.8 that the contact resistance is extremely small when the impurity dosage of the polysilicon is 1 x 10¹⁵ /cm² or greater. FIGS.9 and 10 respectively show essential parts of the first embodiment of the high voltage MOS transistor. In this embodiment, the n⁺-type diffusion layer 16 has the LDD structure as shown in FIG.9 and includes an n⁺-type portion 16₁ and an n⁻-type portion 16₂. The impurity concentration of the n⁺-type portion 16₁ is greater than that of the n⁻-type portion 16₂, and the impurity concentration of the n⁻-type portion 16₂ is approximately the same as that of the n⁻-type diffusion layer 15. In addition, as shown in FIG.10, the n⁻-type portion 16₂ partially overlaps the gate electrode 14. Under the condition that the dosage of P ions for the n⁻-type diffusion layer 15 is 1 x 10³/cm², the polysilicon electrode 38 has a thickness of 200nm (2000 Å), the dosage of P ions for the polysilicon is 1 x 10¹⁵ /cm² and a distance D between the gate electrode 14 and the contact hole 29 shown in FIG.9 is 1 µm, it was confirmed that a withstand voltage of 20 V is obtainable at the drain. Next, a description will be given of embodiments of a method of producing a semiconductor device which has the drain layer 15 with the relatively low impurity concentration and the source layer 16 with the relatively high impurity concentration, by taking the method of forming the first and third MOS transistors 3 and 5 as an example. First, a description will be given of a first embodiment of a method of producing a semiconductor device according to the present invention. As shown in FIG.11A, the field oxide layer 42 is formed by a LOCOS around the peripheries of transistor forming regions T₁ and T₂ where the first and third transistors 3 and 5 are to be formed on the semiconductor substrate 1, and the gate oxide layers 6 and 13 are thereafter formed by thermal oxidation. Then, a polysilicon layer including impurities is formed and patterned by a photolithography technique, so as to form the polysilicon gate electrodes 7 and 14 via the respective gate oxide layers 6 and 13 at respective centers of the transistor forming regions T₁ and T₂. Next, n-type impurity ions such as P ions are injected and diffused in the semiconductor substrate 1 to form n -type diffusion layers 43 of relatively low impurity concentration in the self-align manner on both sides of the gate electrodes 7 and 14. For example, the impurity ions are injected into the semiconductor substrate 1 with a dosage of 10¹³ to 10¹⁴ /cm². Thereafter, as shown in FIG.11B, a SiO₂ layer 44 is formed on the entire surface to a thickness of approximately 100nm (1000 Å) by a chemical vapor deposition (CVD). In addition, one of the diffusion layers 43 in the transistor forming region T₂ and the periphery of this one diffusion layer 43 are covered by a resist 45, and the SiO₂ is selectively removed by a reactive ion etching (RIE). Only the portions of the SiO₂ layer 44 covered by the resist 45 remains after the RIE, and sidewalls 46 of the remaining SiO₂ layer 44 are formed on the sides of the gate electrodes 7 and 14 as shown in FIG.11C. Next, the SiO₂ layer 44 and the sidewalls 46 are used as masks and arsenic (As) ions are injected and diffused in the semiconductor substrate 1. As a result, a diffusion layer of a relatively high impurity concentration of approximately 10²⁰/cm³ is formed in a region of the diffusion layer 43 not covered by the SiO₂ layer 44, thereby forming this diffusion layer 43 into the LDD structure as shown in FIG.11D. On the other hand, the diffusion layer 43 covered by the SiO₂ layer 44 is maintained to the relatively low impurity concentration as shown in FIG.11D. Thereafter, a SiO₂ layer 47 is formed on the entire surface as shown in FIG.11E. A photolithography technique is used to pattern the SiO₂ layer 47 and the SiO₂ layer 44, thereby forming the contact holes 28 through 31 on the diffusion layers 43 as shown in FIG.11F. Then, a polysilicon layer 49 having a thickness of approximately 200nm (2000 Å) is formed on the entire surface, and P ions are injected with a dosage of 1 x 10¹⁵ /cm². In addition, a photolithography technique is used to selectively etch the polysilicon layer 49, and the polysilicon layer 49 is left within the contact holes 28 through 31 as shown in FIG.11G. In this state, the diffusion layers 43 formed in the transistor forming region T₁ have the LDD structure, and one diffusion layer 43 forms the drain layer 8 shown in FIG.7A while the other diffusion layer 43 forms the source layer 9 shown in FIG.7A. On the other hand, between the diffusion layers 43 formed in the transistor forming region T₂, the diffusion layer 43 which is covered by the SiO₂ layer 44 and has the relatively low impurity concentration is used as the n⁻-type diffusion layer 15 while the other diffusion layer 43 is used as the diffusion layer 16 having the LDD structure. Furthermore, the polysilicon layer 49 remaining within the contact holes 28 through 31 functions as the electrodes 35 through 38. The electrodes 35 through 38 are heated in a later thermal process such as thermal oxidation and annealing, and the impurities included in the electrodes 35 through 38 diffuse shallowly into the source layer 9, the drain layer 8 and the diffusion layers 15 and 16. As a result, the contact resistance between these layers 16, 8, 8 and 15 and the corresponding electrodes 35 through 38 is reduced. Accordingly, even when the voltage higher than the boost voltage Vo is applied the diffusion layer 15 of the third MOS transistor 5 which is an n⁻-type layer, the contact resistance between the electrode 38 and the diffusion layer 15 is reduced and a satisfactory contact is obtained. When covering the n⁻-type diffusion layer 15 of the third MOS transistor 5 by the SiO₂ layer 44, a stepped portion with a vertical edge is formed by the SiO₂ layer 44 remaining on the semiconductor substrate 1 after the resist 45 is used as the mask to pattern the SiO₂ layer 44. For this reason, when the SiO₂ layer 44 is thick, there are problems in that the stepped portion may cause damage to an interconnection layer which is formed at a latter stage and etching residue may be generated during a process. Next, a description will be given of a second embodiment of the method of producing the semiconductor device according to the present invention, by referring to FIGS.12A through 12D. According to this embodiment, the above described problems of the first embodiment of the method of producing the semiconductor device are eliminated. FIG.12A shows a state where the resist 45 is removed from the state shown in FIG.11C. Then, as shown in FIG.12B, a second SiO₂ layer 44b is formed on the entire surface to a thickness of approximately 100nm (1000 Å) and etched by a RIE. As a result, the side edge portion of the SiO₂ layer 44 remaining on the n⁻-type diffusion (source) layer 15 becomes smooth as shown in FIG.12C and the step coverage is improved. In this case, the sidewalls 46 on both sides of the gate electrodes 7 and 14 have the two-layer structure. However, the thickness of the sidewall 46 can easily be controlled by appropriately adjusting the thicknesses of the first and second SiO₂ layers 44 and 44b. Thereafter, impurity ions are injected and diffused in the semiconductor substrate 1 using the sidewalls 46 and the two SiO₂ layers 44 and 44b as masks. Hence, the diffusion layers 43 having the LDD structure and the diffusion layer 43 having the relatively low impurity concentration are formed as shown in FIG.12D, similarly to FIG.11D. According to the second embodiment of the method of producing the semiconductor device, a second embodiment of the high voltage MOS transistor according to the present invention is produced. FIG.13 shows an essential part of the second embodiment of the high voltage MOS transistor. In this embodiment of the high voltage MOS transistor, the n⁻-type portion 16₂ of the n⁺-type diffusion layer 16 is formed under the sidewall 46. Next, a description will be given of a third embodiment of the high voltage MOS transistor according to the present invention, by referring to FIG.14. In FIG.14, those parts which are the same as those corresponding parts in FIG.7A are designated by the same reference numerals, and a description thereof will be omitted. In this embodiment of the high voltage MOS transistor, a distance d₁ between the contact hole 28 and the gate electrode 14 is set smaller than a distance d₂ between the contact hole 29 and the gate electrode 14. FIG.15 shows the relationship of the distance d₂ and the withstand voltage on the side of of the n⁻-type diffusion layer 15. As may be seen from FIG.15, the withstand voltage is 20 V when the distance d₂ is approximately 0.8 µm or greater. Next, a description will be given of fourth and fifth embodiments of the high voltage MOS transistor according to the present invention, by referring to FIGS.16A through 16C. In FIGS.16A through 16C, those parts which are the same as those corresponding parts in FIG.7A are designated by the same reference numerals, and a description thereof will be omitted. FIG.16A shows a cross section of the fourth and fifth embodiments, and FIGS.16B and 16C respectively show plan views of the fourth and fifth embodiments. As shown in FIG.16B, the contact hole 29 is made up of a plurality of holes in the fourth embodiment. On the other hand, as shown in FIG.16C, the contact hole 29 is made of a single hole which is large compared to those of the fourth embodiment. Hence, the contact area of the fifth embodiment is improved compared to that of the fourth embodiment. When forming the electrode 38 and the like by a polysilicon layer, it is possible to simplify the production process as a whole if the polysilicon layer can be formed by a process which is common to the process of forming a conductor layer of the semiconductor device. Hence, in a second embodiment of the semiconductor device according to the present invention, the polysilicon layer which forms the electrode 38 is also used as a conductor layer within the DRAM. FIG.17 shows an essential part of the second embodiment of the semiconductor device. In FIG.17, those parts which are the same as those corresponding parts in FIG.7A are designated by the same reference numerals, and a description thereof will be omitted. For example, the storage electrode 24 of the DRAM may be formed by the same polysilicon layer which forms the electrode 38. As another example, the bit line BL of the DRAM may be formed by the same polysilicon layer which forms the electrode 38. Next, a description will be given of a first embodiment of a method of producing a high voltage MOS transistor according to the present invention, by referring to FIGS.18A and 18B. In FIGS.18A and 18B, those parts which are the same as those corresponding parts in FIGS.11A through 11G are designated by the same reference numerals, and a description thereof will be omitted. In this embodiment, the field oxide layer 42 is formed by a LOCOS as shown in FIG.18A, similarly as described before in conjunction with FIG.11A. In addition, the gate oxide layer 13 is formed by a thermal oxidation, and a polysilicon layer is formed and patterned to form the gate electrode 14. Further, an ion implantation is carried out to form the diffusion layers 43 having the relatively low impurity concentration. Thereafter, as shown in FIG.18B, the resist 45 is formed on the diffusion layer 43 to which the high voltage is applied, similarly as described before in conjunction with FIG.11C. An ion implantation is carried out using the field oxide layer 42, the gate electrode 14 and the resist 45 as masks, so as to form the diffusion layer 43 (source layer 16) having the LDD structure. The formation of the interlayer insulator layer, the contact holes and the electrodes may be carried out similarly as described before in conjunction with FIGS.11D through 11G, and a description thereof will be omitted. Next, a description will be given of a second embodiment of the method of producing the high voltage MOS transistor according to the present invention, by referring to FIG.19. In FIG.19, those parts which are the same as those corresponding parts in FIGS.11A through 11G are designated by the same reference numerals, and a description thereof will be omitted. In this embodiment, the SiO₂ oxide layer 44 is formed on the entire surface of the structure shown in FIG.18A and the SiO₂ oxide layer 44 is etched by a RIE to form the sidewalls on the side surfaces of the gate electrode 14 as shown in FIG.19. Furthermore, the resist 45 is formed on the diffusion layer 43 to which the high voltage is applied. An ion implantation is carried out using the field oxide layer 42, the sidewalls 46, the gate electrode 14 and the resist 45 as masks, so as to form the diffusion layer 43 (source layer 16) having the LDD structure. Next, a description will be given of a third embodiment of the method of producing the high voltage MOS transistor according to the present invention, by referring to FIG.20. In FIG.20, those parts which are the same as those corresponding parts in FIGS.11A through 11G are designated by the same reference numerals, and a description thereof will be omitted. In this embodiment, the SiO₂ oxide layer 44 is used as a part of the mask in place of the resist 45 shown in FIG.18B when forming the diffusion layer 43 (drain layer 16) having the LDD structure. Next, a description will be given of a fourth embodiment of the method of producing the high voltage MOS transistor according to the present invention, by referring to FIG.21. In FIG.21, those parts which are the same as those corresponding parts in FIGS.11A through 11G are designated by the same reference numerals, and a description thereof will be omitted. In this embodiment, the sidewalls 46 are formed on the side surface of the gate electrode 14 when etching the SiO₂ layer 44 shown in FIG.20 by the RIE. Accordingly, when forming the diffusion layer 43 (source layer 16) having the LDD structure, the sidewall 46 is also used as a part of the mask. Next, a description will be given of a third embodiment of the method of producing the semiconductor device according to the present invention, by referring to FIGS.22A and 22B. In FIGS.22A and 22B, those parts which are the same as those corresponding parts in FIGS.7A and 11A through 11G are designated by the same reference numerals, and a description thereof will be omitted. In this embodiment, the SiO₂ oxide layer 44 is formed on the entire surface after the gate electrode 14 of the high voltage MOS transistor 5 and the gate electrode 21 of the MOS transistor 18 of the DRAM cell 17 are formed as shown in FIG.22A. A photolithography technique is used to leave the SiO₂ oxide layer 44 on the MOS transistor 18 which forms the memory cell and on the diffusion layer 43 (drain layer 15) of the high voltage MOS transistor 15 as shown in FIG.22B. As shown in FIG.22B, the remaining SiO₂ oxide layer 44 is used as a mask when carrying out an ion implantation to form the diffusion layer 43 (source layer 16) which has the LDD structure. The sidewall 46 which remains on the side surface of the gate electrode 14 when the SiO₂ oxide layer 44 is etched by a RIE is also used as a part of the mask, similarly as in the case described before in conjunction with FIG.21. Next, a description will be given of a fourth embodiment of the method of producing the semiconductor device according to the present invention, by referring to FIGS.23A and 23B. In FIGS.23A and 23B, those parts which are the same as those corresponding parts in FIGS.7A and 12A through 12D are designated by the same reference numerals, and a description thereof will be omitted. In this embodiment, the SiO₂ layer 44b is formed after the SiO₂ oxide layer 44 is etched by a RIE, and the SiO₂ layer 44b is etched by a RIE as shown in FIG.23A. As a result, the side edge portions of the SiO₂ oxide layer 44 remaining on the diffusion layer 43 (source layer 16) and the gate electrode 14 become smooth and both sides of the gate electrode 21 become smooth as shown in FIG.23B. For this reason, it is possible to prevent damage to an interconnection layer which is formed at a latter stage and also prevent etching residue from being generated during a process. The etching of the oxide layer increases the junction leak due to contamination and surface damage, because the substrate surface is directly etched. Hence, in the memory cell part of the DRAM where even the extremely small leak current causes characteristic deterioration, it is desirable not to etch the oxide layer. In the third and fourth embodiments of the method of producing the semiconductor device, a process is required to cover the memory cell part by the resist when etching the SiO₂ oxide layer 44. However, at the same time, the diffusion layer 43 (drain layer 15) of the high voltage MOS transistor 5 is also covered by the resist. Hence, there is no need to increase the number of processes exclusively for the protection of the memory cell part. The diffusion layers 22 and 23 of the memory cell part have a relatively low impurity concentration which is approximately the same as that of the diffusion layer 43 (drain layer 15). But since ion implantation with a high impurity dosage induces crystal defect and junction leak, no problems are caused by the relatively low impurity concentration of the diffusion layers 22 and 23. In each of the embodiments described heretofore, the electrode which is formed on the diffusion layer having the relatively low impurity concentration is made of polysilicon. However, it is possible to use amorphous silicon or refractory metal silicide in place of polysilicon. For example, the refractory metal included in the refractory metal silicide may be tungsten (W), molybdenum (Mo), tantalum (Ta), titanium (Ti) and the like. In addition, it is possible to use a polycide layer on the diffusion layer as the electrode. In this case, the polycide layer includes a refractory metal silicide such as tungsten silicide on a polysilicon layer. Moreover, it is possible to form an Al interconnection layer on the electrode which is made of polysilicon or polycide, and "AL" in FIG.5 shows such an Al interconnection layer. For example, the polycide layer is formed by forming a refractory metal layer of approximately 0.1 µm on a polysilicon layer of approximately 0.1 µm, and P ions are injected into the refractory metal layer with a dosage of approximately 10¹⁵ /cm². Further, the present invention is not limited to these embodiments, but various variations and modifications may be made without departing from the scope of the present invention.

Claims: A high voltage MOS transistor comprising a semiconductor substrate (1) of a first conductivity type, a gate electrode (14) formed on said semiconductor substrate via a gate oxide layer (13), first and second diffusion regions (15, 16) formed in said semiconductor substrate on both sides of said gate electrode and being of a conductivity type opposite to said first conductivity type, and an electrode (38) which is directly connected to said first diffusion region (15) and is made of a conductor layer (49) including polysilicon with an impurity concentration of said conductor layer (49) including the polysilicon being higher than the impurity concentration of said first diffusion region (15), said MOS transistor being bounded by a surrounding field oxide layer (42) formed on said substrate (1), characterized in that the impurity concentration of said first diffusion region (15) is smaller than that of said second diffusion region (16), and the contact region where said electrode (38) contacts said first diffusion region (15) is formed spatially separated from said field oxide layer (42). A MOS transistor according to claim 1, characterized in that said second diffusion region (16) has a lightly doped drain structure including a first region (16₂) which is formed at a surface portion of said semiconductor substrate (1) and has an impurity concentration approximately equal to that of said first diffusion region (15) and a second region (16₁) which connects to said first region and has an impurity concentration higher than that of said first diffusion region (15). A MOS transistor according to claim 2, characterized by a sidewall (46) on at least said first region (16₂) on a side surface of said gate electrode (14). A MOS transistor according to claim 2 or 3, characterized in that said first region (16₂) overlaps a part of said gate electrode (14) via said gate oxide layer (13). A MOS transistor according to anyone of the claims 1 to 4, characterized in that a depth of solid phase diffusion of impurities from said conductor layer (49) into said first diffusion region (15) is less than a depth of said first diffusion region. A MOS transistor according to anyone of the claims 1 to 5, characterized in that said conductor layer (49) includes refractory metal silicide. A MOS transistor according to claim 6, characterized in that the refractory metal silicide includes a refractory metal selected from a group consisting of tungsten (W), molybdenum (Mo), tantalum (Ta) and titanium (Ti). A MOS transistor according to anyone of the claims 1 to 7, characterized by an insulator layer (47) which covers said first and second diffusion regions (15, 16) and said gate electrode (14), a first contact hole (29) formed in said insulator layer (47) and exposing said first diffusion region (15), and a second contact hole (28) formed in said insulator layer (47) and exposing said second diffusion region (16), a first distance (d₂) between said gate electrode (14) and said first contact hole (29) being greater than a second distance (d₁) between said gate electrode (14) and said second contact hole (28). A MOS transistor according to anyone of the claims 1 to 8, characterized in that said first conductivity type is a p-type and said second conductivity type is a n-type. A method of producing a high voltage MOS transistor comprising the steps of selectively forming a field oxide layer (42) on a semiconductor substrate (1) of a first conductivity type, successively forming a gate oxide layer (13) and a gate electrode (14) on a region of said semiconductor substrate defined by said field oxide layer, forming first and second impurity regions (43, 15, 16) of a second conductivity type opposite to said first conductivity type in said semiconductor substrate on both sides of said gate electrode by a first ion implantation, and forming a conductor layer (49) directly on at least said first impurity region (43, 15) so as to form an electrode (38) with said conductor layer (49) including polysilicon with an impurity concentration higher than that of said first impurity region (43, 15), characterized by the steps of covering said first impurity region (43, 15) by a mask layer (45, 44); and increasing the impurity concentration of said second impurity region (43, 16) higher than the impurity concentration of said first impurity region (43, 15) by a second ion implantation using said field oxide layer (42), said gate electrode (14) and said mask layer (45, 44) as masks; wherein a contact region where said electrode (38) makes direct contact with said first diffusion region (15) is arranged so as to make no contact with said field oxide layer (42). A method according to claim 10, characterized in that the step of forming said mask layer (45, 44) on said first impurity region (43, 15) forms said mask layer (45, 44) on an entire surface of said semiconductor substrate (1) and selectively etches said mask layer so that a sidewall (46) of said mask layer remains on a side surface of said gate electrode (14) on at least said second impurity region (43, 16). A method according to claim 11, characterized in that said step of forming said mask layer (45, 44) further forms a second mask layer (44b) on said mask layer (45, 44) and selectively etches said second mask layer so that side edge portions of said mask layer (45, 44) and said sidewall (46) are smoothed. A method according to anyone of the claims 10 to 12, characterized in that said conductor layer (49) includes refractory metal silicide. A method according to claim 13, characterized in that said refractory metal silicide includes a refractory metal selected from a group of tungsten (W), molybdenum (Mo), tantalum (Ta) and titanium (Ti). A method according to anyone of the claims 10 to 14, characterized in that said step of forming said conductor layer (49) includes forming an insulator layer (47) which covers said first and second impurity regions (15, 16) and said gate electrode (14), forming first and second contact holes (29, 28) in said insulator layer (47) to respectively expose said first and second impurity regions (15, 16), so that a first distance (d₂) between said gate electrode (14) and said first contact hole (29) is greater than a second distance (d₁) between said gate electrode (14) and said second contact hole (28), and forming said conductor layer (49) on said insulator layer (47) to fill at least said first contact hole (29). A method according to anyone of the claims 10 to 15, characterized in that said first conductivity type is a p-type and said second conductivity type is a n-type. A semiconductor device having a MOS transistor according to claim 1, characterized in that a plurality of elements are formed on said semiconductor substrate (1), and said conductor layer (49) including said polysilicon also forms a conductor layer of at least one of said elements. A semiconductor device having a MOS transistor according to claim 1, characterized in that a plurality of elements are formed on said semiconductor substrate (1), and said conductor layer (49) including said polysilicon also forms an interconnection layer which connects to at least one of said elements. A semiconductor device according to claim 17 or 18, characterized in that said elements include a MOS transistor (3) which receives at one of source and drain electrodes thereof a voltage (Vo) being higher than a power source voltage (Vcc) and which has a gate electrode (7) being connected to said first electrode (38) of said high voltage MOS transistor (5). A semiconductor device according to claim 19, characterized in that a voltage applied to a node which connects said first electrode (38) of said high voltage MOS transistor (5) and said gate electrode (7) of said MOS transistor (3) is higher than said voltage (Vo) which is applied to said one of said source and drain electrodes of said MOS transistor (3). A semiconductor device according to claim 19 or 20, characterized in that said elements include a memory cell (18, 19) which is connected to a word line (WL), and the other of said source and drain electrodes of said MOS transistor (3) is connected to said word line (WL). A semiconductor device according to claim 21, characterized in that said memory cell (18, 19) includes one MOS transistor (18) and one capacitor (19) connected thereto. A semiconductor device according to claim 22, characterized in that said conductor layer (49) contacting said low impurity concentration layer (43) forms a bit line of a DRAM cell. A semiconductor device according to anyone of the claims 17 to 23, characterized in that said first conductivity type is a p-type and said second conductivity type is an n-type. A method of producing a semiconductor device having at least a high voltage MOS transistor (5) according to claim 1 and a second MOS transistor (18) which forms a memory cell formed on a semiconductor substrate (1) which is of a first conductivity type, said method comprising the steps of selectively forming a field oxide layer (42) on said semiconductor substrate (1), successively forming gate oxide layers (13, 20) and gate electrodes (14, 21) on said semiconductor substrate in regions defined by said field oxide layer (42), and forming impurity regions (43, 15, 16, 22, 23) of a second conductivity type opposite to said first conductivity type in said semiconductor substrate on both sides of said gate electrodes by a first ion implantation, characterized by the steps of covering said impurity regions (43, 33, 34) of said second MOS transistor (18) forming a memory cell and said first impurity region (43, 15) of said high voltage MOS transistor (5) by a mask layer (45, 44); increasing an impurity concentration of a second impurity region (43, 16) of said high voltage MOS transistor higher than the impurity concentration of said first impurity region (43, 15) by a second ion implantation using said field oxide layer (42), said gate electrode (14) of said high voltage MOS transistor (5) and said mask layer (45, 44) as masks; and forming a conductor layer (49) directly on at least a portion of said first impurity region (43, 15) so as to form an electrode (38), wherein said conductor layer (49) includes polysilicon with an impurity concentration higher than that of said first impurity region (43, 15).

Inventors: IKEMASU SHINICHIROU, IKEMASU, SHINICHIROU
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1991
Main classification: H01L29
IPC codes: H01L29, H01L21