Image reading device transferring the reset charge for a charge accumulating element through the associated photosensitive element

Abstract: An image reading device is provided with plural photoelectric converting elements, accumulating elements provided respectively corresponding to said photoelectric converting elements and adapted to accumulate output signals thereof, and switch means for taking out the signals accumulated in said accumulating means in succession as optical information. On the device, the photoelectric converting elements have switching function; and further comprising means for driving said photoelectric converting elements in such a manner as to release the accumulated charges from the accumulating elements through the photoelectric converting elements.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to an image reading device, and more particularly to an image reading device provided with means for accumulating incident light information, adapted for use in a reader unit of an image information processing apparatus such as facsimile. Related Background Art There are already known various image reading methods for use in the image reading devices. Examples of such methods are frame transfer method and interline transfer method employed in CCD (charge coupled devices). Also image reading circuit structures for use in the amplifying devices with improved S/N ratio are disclosed for example in the U.S. Patent Publications US-A4,791,469, -4,831,454, -4,835,404 and -4,876,601. Furthermore, circuit structures adapted for use in thin film devices suitable for forming large area devices are disclosed, for example, in the U.S. Patents Publications US-A-4,390,791, -4,461,956, -4,829,485 and -4,886,977. Furthermore, the U.S. Patent Publication US-A-4,963,955 discloses a circuit structure in which transistors constituting pixels are serially connected for every vertical line for enabling collective resetting. However these structures have a limit in reducing the resetting time, because of large parasite resistance and capacitance in the serially connected line of pixels. In addition to the conventional structures mentioned above, there is also proposed a resetting method utilizing block drive. Fig. 8 is a circuit diagram of a conventional image reading device, showing, as an example, a photosensor array with nine photosensors. In the circuit shown in Fig. 8, among photosensors E1 - E9, three constitute a block, and three blocks constitute the photosensor array. Capacitors C1 - C9 and switching transistors T1 - T9, respectively corresponding to the photosensors E1 - E9, are similarly grouped. Electrodes at a side (common electrodes) of the photosensors E1 - E9 are connected to a power source 101, while the other electrodes (individual electrodes) are grounded through respective capacitors C1 - C9. Also the individual electrodes of a same cardinal number in different blocks of the photosensors E1 - E9 are connected, through respective switching transistors T1 - T9, to one of common lines 102 - 104. More detailedly, first switching transistors T1, T4, T7 of different blocks are connected to the common line 102; second switching transistors T2, T5, T8 of different blocks are connected to the common line 103; and third switching transistors T3, T6, T9 of respective blocks are connected to the third common line 104. Said common lines 102 - 104 are connected, respectively through switching transistors T10 - T12, to an amplifier 105. The gate electrodes of the switching transistors T1 - T9 are commonly connected for each block, and are respectively connected to parallel output terminals of a shift register 106. Said output terminals release high-level signals in succession at predetermining timings, whereby the switching transistors T1 - T9 are turned on in succession in the unit of each block. Also the gate electrodes of the switching transistors T10 - T12 are respectively connected to parallel output terminals of a shift register 107. Said output terminals release high-level signals in succession at predetermined timings, whereby the switching transistors T10 - T12 are turned on in succession. The common lines 102 - 104 are also grounded respectively through capacitors C10 - C12 and switching transistors CT1 - CT3. The capacitance of the capacitors C10 - C12 is selected sufficiently larger than that of the capacitors C1 - C9. The gate electrodes of the switching transistors CT1 - CT3 are commonly connected to a terminal 108. Thus the application of a high-level signal to said terminal 108 turns on the switching transistors CT1 - CT3 simultaneously, thereby grounding the common lines 102 - 104. Such an image reading device is disclosed in the U.S. Patent No. Publication US-A-4,827,345. In the following there will be explained the function of such a conventional image reading device, with reference to a timing chart of the switching transistors T1 - T12 and CT1 - CT3, shown in Fig. 9. In Fig. 9 there is shown the timing when each switching transistor is turned on, and it is also the timing of release of high-level signal from the shift register 106 or 107. When the light enters the photosensors E1 - E9, charges are accumulated in the capacitors C1 - C9 from the power source 101 through the photosensors E1 - E9, according to the intensity of said incident light. Then the switching transistors T1 - T3 are turned on when a high-level signal is released from the first output terminal of the shift register 106 (Fig. 9(a)). With said switching transistors T1 - T3 being turned on, charges accumulated in the capacitors C1 - C3 are respectively transferred to the capacitors C10 - C12. Subsequently the shift register 107 effects shifting operations to turn on the switching transistors T10 - T12 in succession [Fig. 9(d) - (f)], whereby the optical information of the first block transferred to and accumulated in the capacitors C10 - C12 are read in succession and released through the amplifier 105. After the reading of the information of the first block, an unrepresented circuit detects said reading and applies a high-level signal to the terminal 108, whereby the switching transistors CT1 - CT3 are simultaneously turned on [Fig. 9(g)]. Thus the remaining charges in the capacitors C10 - C12 are dissipated, and said capacitors become ready for another transfer of optical information. Then the shift register 106 effects a shift to release a high-level signal from the second output terminal, thereby turning on the switching transistors T4 - T6 [Fig. 9(b)]. Thus the information reading of the second block is conducted in a similar manner as in the first block. Operations for the third block are also conducted in a similar manner. As explained above, information are accumulated in the capacitors C1 - C9, according to the shift timing of the shift registers 106, 107 and the timing of high-level signal application to the terminal 108 as shown in Fig. 9. The information accumulated in said capacitors C1 - C9 are transferred to the capacitors C10 - C12 by the unit of each block at a time, and the information thus transferred are time-sequentially read by the switching transistors T10 - T12. However the conventional structure has been associated with the following drawbacks, because of the on-resistance (resistance in "on" state) in the switching transistors: (1) The timing constants, determined by the capacitances of the capacitors C1 - C9 and the resistances of the corresponding switching transistors T1 - T9 become large, and the discharging time of the capacitors C1 - C9 becomes longer because of the parasite capacitances of the common lines 102 - 104 and the switching transistors T10 - T13, the capacitances of the capacitors C10 - C12 and the wiring resistances. Consequently, such image reading device requires a long time for the information reading operation; (2) As the discharge of the capacitors C1 - C9 requires a long time, it is limited to a certain time in practice, but the image reading operation becomes unreliable because the amount of remaining charge in the capacitors C1 - C9 varies depending on the light intensity. SUMMARY OF THE INVENTION An object of the present invention is to provide an image reading device being improved with respect to the afore-mentioned drawbacks of the conventional devices. Another object of the present invention is to provide an image information processing apparatus comprising the above-mentioned image reading device, original support means for supporting an original, bearing image information thereon, in a reading position for said image reading device, and recording means for recording the image information read by said image reading device. The invention is as set out in appended claim 1. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram of an image reading device constituting a first embodiment of the present invention; Fig. 2 is a timing chart of the signals in the circuit shown in Fig. 1; Fig. 3 is a characteristic chart of transistors employed as components in the device shown in Fig. 1; Fig. 4A is a schematic plan view of a part, corresponding to a bit, of the device shown in Fig. 1; Fig. 4B is a cross-sectional view along a line X-X' in Fig. 4A; Fig. 4C is a cross-sectional view along a line Y'Y' in Fig. 4A; Fig. 5 is a circuit diagram of an image reading device constituting a second embodiment of the present invention; Fig. 6 is a timing chart of the signals in the circuit shown in Fig. 5; Fig. 7 is a schematic view of an image information processing apparatus of the present invention; Fig. 8 is a circuit diagram of a conventional image reading device; and Fig. 9 is a timing chart of the signals in the circuit shown in Fig. 8. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The circuit structure of the present invention employs a unit cell composed of a photoelectric converting element connected to a charge accumulating element, wherein said photoelectric converting element comprises a switching element showing different resistances between two terminals in on- and off-states. Such unit cells are connected in parallel at least in each block, and the signal charges accumulated in the charge accumulating elements are dissipated, utilizing the switching characteristic of the photoelectric converting elements. The structure of the present invention can reduce the resetting time, thereby contributing significantly to the improvement of image reading speed. The photoelectric converting element to be employed in the present invention can be any element with a switching function, such as an ordinary bipolar transistor or a gate-insulated field effect transistor. The effect of the present invention is particularly evident in thin film elements, such as thin film transistors (TFT), employed for providing a large-area inexpensive sensor, because such elements have a high on-resistance. However the present invention is not limited to such thin film elements. In the following the present invention will be explained in detail by embodiments thereof shown in the attached drawings. Fig. 1 is a circuit diagram of an image reading device constituting a first embodiment of the present invention. In the present embodiment, capacitors C1 - C12 constituting the first accumulating means, capacitors CT10 - CT12 constituting the second accumulating means, switching transistors T1 - T12, and shift transistors 106, 107 are same as those in the conventional structure shown in Fig. 8, and will not be explained, therefore, in further detail. In the present embodiment, elements D1 - D9, corresponding to phototransistors, have according to an equivalent circuit the functions as sensors E1 - E9 having a photoconductive layer and as switching transistors ST1 - ST9. The control electrodes of the switching transistors are connected to the respective common lines (202, 203, 204) of the blocks of the sensors E1 - E9, and are connected in blocks to the output terminals of a shift register 201 which also serves as a reference voltage source. Consequently, according to the timing of shift operation of the shift register 201, the switching transistors of the elements D1 - D9 are in succession turned on blockwise, whereby the capacitors C1 - C9 are charged to the high-level voltage V1 supplied from the shift register 201. In the following, the function of the present embodiment of the above-explained structure will be explained with reference to a timing chart of the switching transistors T1 - T12, CT1 - CT3 and elements D1 - D9 shown in Fig. 2. In Fig. 2 there is shown the timing when each switching transistor is turned on, and it is also the timing of release of high-level signals from the shift registers 106, 107 or 201. When light enters the photosensors E1 - E9, the capacitors C1 - C9 emit charges through the common electrodes 202, 203 and 204, according to the intensity of said light. In this state, the switching transistors remain turned off, since a low-level signal V2 is supplied to the common electrodes 202, 203 and 204 from the shift register 106. Fig. 3 shows typical transistor characteristic of the elements D1 - D9 employed in the present embodiment. In Fig. 3, the abscissa indicates the gate-source potential V of the switching transistors ST1 - ST9 of the elements D1 - D9, while the ordinate indicates the drain-source current I ds in logarithmic scale. When the gate electrode is maintained at a high-level state, for example V1 = 12 V, I ds is indicated by (a) in Fig. 3. It does not vary much in the light and dark states, and is in a range of 1.0 - 1.5 x 10 -5 A in the illustrated example. On the other hand, when the gate electrode is maintained at the low-level state, for example V2 = 0 V, I ds is indicated by (b) in Fig. 3, and shows a ratio of 1,000 - 10,000 between the light and dark states. The transistors ST1 - ST9 of the elements D1 - D9 preferably have a same characteristic, and the off-resistance in the dark state is structurally same as the dark resistance of the sensors E1 - E9 of the elements D1 - D9. Also the on-resistance is preferably 1/1000 to 1/10000 of the resistance of the sensors E1 - E9 of the elements D1 - D9 when receiving light. In the example shown in Fig. 3, this ratio is about 1/10000. The function of the circuit continues in the following manner. At first the shift register 106 releases a high-level signal from its first output terminal, thereby turning on the switching transistors T1 - T3 [Fig. 2(a)]. Thus the charges remaining in the capacitors C1 - C3, after discharge according to the light intensity, are respectively transferred to the capacitors C10 - C12. Subsequently the shift register 107 serving as reading means shifts a high-level output signal, thereby turning on the switching transistors T10 - T12, also serving as reading means, in succession [Fig. 2(d) - (f)]. In this manner the optical information of the first block, transferred to and accumulated in the capacitors C10 - C12, are read through the amplifier 105. Eventually, the optical information is defined by the decrease of the read information from the black level. After the information reading of the first block, a high-level signal is applied to the terminal 108, thereby turning on the switching transistors CT1 - CT3 simultaneously [Fig. 2(g)]. Thus the charges remaining in the capacitors C10 - C12 are dissipated completely. When said remaining charges of the capacitors C10 - C12 are dissipated, the shift register 106 effects a shift to release a high-level signal from its second output terminal, thereby turning on the switching transistors T4 - T6 [Fig. 2(b)]. Thus the charges remaining, after the aforementioned discharge, in the capacitors C4 - C6 of the second block, are respectively transferred to the capacitors C10 - C12. At the same time the shift register 201, serving as the resetting means, releases a high-level signal V1 from its first output terminal, now serving as the reference voltage source, whereby the switching transistors ST1 - ST3 of the elements D1 - D3 are turned on [Fig. 2(h)] and the capacitors C1 - C3 are completely charged to the high-level voltage V1 supplied from the shift register 201. As explained above, the charting operation for the capacitors C1 - C3 of the first block is conducted, in parallel manner, with the transfer of the charges, remaining in the capacitors C4 - C6 of the second block after discharge according to the light intensity, to the capacitors C10 - C12. Then, as in the case of the first block, the switching transistors T10 - T12 are turned on in succession by the shifting operation of the shift register 107, whereby the optical information of the second block accumulated in the capacitors C10 - C12 are read in succession [Fig. 2(d) - (f)]. The charge transfer operation for the third block is similarly conducted in parallel manner with the charging operation of the capacitors C4 - C6 of the second block [Fig. 2(i)]. Thereafter, the above-explained operations are repeated by the unit of each block. Fig. 4A is a schematic plan view of a part, corresponding to a bit, of the image reading device, Fig. 4B is a cross-sectional view along a line X-X' in Fig. 4A, and Fig. 4C is a cross-sectional view along a line Y-Y' in Fig. 4A. For the purpose of simplicity, Fig. 4A only shows the upper and lower wirings and the contact holes. The image reading device is formed by integrating photoelectric converting elements, accumulating capacitors, thin film transistors, matrix signal wirings etc. on an insulating substrate, utilizing hydrogenated amorphous silicon (hereinafter written as a-Si:H) as a non-monocrystalline material. In the above-mentioned drawings there are shown a matrix wiring part 13; a photoelectric converting part 14; a gate-source connecting contact hole 15; an accumulating capacitor 16; a transfer TFT 17; and a gate driving wiring part 19. This embodiment is constructed as so-called lensless image reading device which reads the image of the original by direct contact of the sensor part (photoelectric converting part) with the original without an imaging lens therebetween. For this reason, there is provided a window 20 for illumination from the original, and a lower gate electrode, serving as the control electrode of the photoelectric converting part 14, is formed with an opaque material, thus serving also as a light shield film for excluding the light other than that reflected from the original. There are also shown a substrate 1 composed for example of glass, and a lower electrode 21 serving as the gate electrode of the photoelectric converting part in Fig. 4B. An insulating layer 3 is composed for example of SiN X H or SiO 2 . A photoelectric semiconductor layer 4 is composed for example of hydrogenated amorphous silicon (a-Si:H). An n + layer 5 is provided for forming ohmic contact with an upper electrode 22 constituting source and drain electrodes, namely two main electrodes, of the photoelectric converting part. As explained in the foregoing, as the accmulating capacitors of each block which has been subjected to information reading can be completely charged, the present embodiment can reduce the time required for transferring the information of each block to the capacitors C10 - C12, and can improve the reliability of image reading. The present embodiment has been described by a case of nine elements, serving as photosensors and phototransistors, divided into three blocks, but such a structure is not limitative. Division of an arbitrary number of such elements into an arbitrary number of blocks is easily achievable from the present embodiment. Fig. 5 is a circuit diagram of a second embodiment of the image reading device of the present invention. In Fig. 5, components are same as those in Fig. 1, and the basic function is therefore substantially same as that in Fig. 1, except that the gate electrodes of the switching transistors ST1 - ST9 are not connected to the common electrodes of the photosensors E1 - E9 but to parallel output terminals of another shift register 205 constituting resetting means. In the following there will be explained the function of the second embodiment of the above-explained structure, with reference to a timing chart of the switching transistors T1 - T12, CT1 - CT3 and ST1 - ST9 shown in Fig. 6. It is to be noted that, in Fig. 6, (a) to (j) indicate the timings when the switching transistors are turned on, while (k) to (m) indicate the timings of bias signals supplied to the photosensors E1 - E9, namely a high-level signal V1 and a low-level signal V2 released from the shift register 205. At first the gates of switching transistors ST1 - ST9 are driven by a low-level signal while the common electrodes of the photosensors E1 - E9 are supplied with a high-level signal V1, whereby, when the light enters the photosensors E1 - E9, charges corresponding to the incident light intensity are accumulated in the capacitors C1 - C9 through the common electrodes 201 - 204. Then, at first a high-level signal is released from the first output terminal of the shift register 106 to turn on the switching transistors T1 - T3 [Fig. 6(a)], whereby the charges accumulated in the capacitors C1 - C3 are respectively transferred to the capacitors C10 - C12. Then a high-level signal released from the shift register 107 is shifted to turn on the switching transistors T10 - T12 in succession [Fig. 6(d) - (f)], whereby the optical information of the first block, transferred to and accumulated in the capacitors C10 - C12 is read in succession through the amplifier 105. After the reading of the information of the first block, a high-level signal is applied to the terminal 108 from an external circuit, whereby the switching transistors CT1 - CT3 are simultaneously turned on [Fig. 6(g)]. Thus the remaining charges in the capacitors C10 - C12 are completely dissipated. When the charges remaining in the capacitors C10 - C12 are completely dissipated, the shift register 106 effects a shift to release the high-level signal from the second output terminal, whereby the switching transistors T4 - T6 are turned on [Fig. 6(b)] and the charges accumulated in the capacitors C4 - C6 of the second block are transferred to the capacitors C10 - C12. At the same time, a high-level signal is released from the first output terminal of the shift register 205 to turn on the switching transistors ST1 - ST3 [Fig. 6(h)], and a low-level signal V2 is released from the first output terminal of the shift register 201, serving as the reference voltage source, thereby completely dissipating the charges remaining in the capacitors C1 - C3. In this manner there are conducted, in parallel manner, the discharge operation of the capacitors C1 - C3 of the first block and the transfer operation of the charges from the capacitors C4 - C6 of the second block to the capacitors C10 - C12. Thereafter the above-explained operations are repeated for each block. In the second embodiment explained above, the bias levels V1, V2, supplied to the photosensors E1 - E9 as shown in (k), (l) and (m) in Fig. 6, need not satisfy a relation V1 > V2 but can be arbitrarily selected. This fact is different from the first embodiment and is one of the effects provided by the second embodiment. For example, when a condition V1 < V2 is employed, discharge is caused according to the optical information and the difference in the amount of charge is read as in the first embodiment. Also in the foregoing first embodiment, it has been explained that the accumulating capacitors C1 - C9 are charged by the bias voltage V1 applied to the photosensors E1 - E9, but this is based on an assumption that the threshold value (V th ) of the transistors ST1 - ST9 is 0 V. Consequently, for example if V th is +1.0 V, the capacitors C1 - C9 are charged only to a potential V1 - V th (1.0). On the other hand, in the second embodiment, since the gate electrodes are independent, there can be obtained a specific advantage that the accumulating capacitors can be completely charged or discharged to the bias level of the photosensors E1 - E9 by selecting a sufficiently high bias voltage (15 - 20 V). In the second embodiment, therefore, since the accumulating capacitors of a block already subjected to information reading can be completely charged to an arbitrary voltage regardless of V th of the transistors, the time required for the transfer of information of each block to the capacitors C10 - C12 can be reduced . It is also rendered possible to improve the reliability of image reading. The present embodiment has been explained by nine elements, serving as photosensors and switching transistors, divided into three blocks, but such structure is not limitative. It will be understandable from this embodiment that an arbitrary number of such elements can be divided into an arbitrary number of blocks. Fig. 7 illustrates a facsimile apparatus with communicating function, as an example of the image information processing apparatus employing the image reading device of the present invention. There are shown a feed roller 102 constituting feed means for feeding the original 6 to a reading position; a separating member 104 for securely separating the originals 6 one by one; and a platen roller 106 provided at the reading position opposite to a sensor unit thereby defining the surface of the original 6 to be read, and also serving for transporting the original 6. Recording medium P is composed, in the illustrated example, of rolled sheet, on which reproduced is the image information read by the sensor unit or transmitted from the outside. A recording head 110, serving as recording means for effecting formation of said image, may be of various types such as a thermal head or an ink jet recording head. Said recording head can be serial type or line type. A platen roller 112 serves to transport the recording medium P to the recording position by the recording head 110 and to define the recording surface of said recording medium. An operation panel 120, serving as input/output means, is provided with switches for entering instructions, and a display unit for displaying the state of the apparatus by messages, etc. A system control board 130, serving as control means, is provided with a controller for controlling various units, a driver for the photoelectric converting elements, a processor for the image information, a transmit/receiving unit etc. There is also provided a power source 140. The recording means to be employed in the image information processing apparatus of the present invention is preferably based on a method of which basic constitution and principle are disclosed for example in the U.S. Patents Publications US-A-4,723,129 and -4,740,796. Said method is based on applying at least one driving signal which gives rapid temperature elevation exceeding nucleus boiling corresponding to the recording information, on an electrothermal converting element arranged corresponding to an ink-holding sheet or a liquid channel, whereby heat energy is generated at the electrothermal converting element to induce film boiling on a heat acting surface of the recording head and bubbles can be formed in the liquid ink corresponding one-by-one to said driving signal. The liquid ink is discharged from a discharge opening by the growth and shrinkage of said bubbles, thereby forming at least a liquid droplet. A full-line multiple type recording head, having a length corresponding to the maximum width of the recording medium recordable on the apparatus, may be composed, as described in the above-mentioned patents, of a combination of plural recording heads or an integral recording head. The present invention is effective also in case of using an interchangeable chip type recording head which can make electrical connections with or can receive ink supply from the main body of the apparatus by mounting thereon, or a cartridge type recording head provided integrally with an ink tank. As detailedly explained in the foregoing, the image reading device of the present embodiment employs photoelectric converting elements with the function of switching elements and dissipates charges, representing the optical information, from the accumulating capacitors through said elements, whereby said accumulating capacitors can be sufficiently discharged within a short time after the transfer of charges, representing the optical signals, from said accumulating capacitors to readout capacitors. Consequently the charges accumulating as signals of a line are not affected by the charges in a preceding line in the sub scanning direction, and the precision and reliability of image reading are significantly improved. Also since the accumulating capacitors can be sufficiently discharged, the time required for the transfer of the signal charges to the readout capacitors need not be prolonged in consideration of the discharging time, so that the functioning speed of the entire apparatus can be increased.

Claims: An image reading device comprising a plurality of photoelectric converting elements (D1-D9) , a plurality of accumulating elements (C1-C9) provided respectively corresponding to said photoelectric converting elements and adapted to accumulate output signals thereof, and first switch means (T1-T9, 106) for transferring the signals accumulated in said accumulating elements, characterized in that each of said photoelectric converting elements has a switching function and includes a first main electrode coupled to a respective accumulating element and a second main electrode alternatively coupled to a high or a low potential, and that said device comprises means (201, 205) for causing precharging or discharging for reset said accumulating elements to said potential through said photoelectric converting elements, using the switching function thereof. A device according to claim 1, characterized in that said means ( 201, 205 ) for precharging or discharging for reset includes a first shift register ( 201, 205 ) and each of said photoelectric converting elements includes a field-effect transistor ( ST1-ST9 ) for implementing said switching function the gate electrode of which is connected to said shift register. A device according to claim 2, characterized in that said gate electrode is connected to either of the source and drain electrodes of said field effect transistor. A device according to claim 1, characterized in that said first switch means includes a plurality of transistors ( T1-T9 ) having gate, source and drain lines and provided respectively corresponding to said accumulating elements, wherein the gate lines and either one of the source and drain lines of said plural transistors are connected to a matrix structure of lines ( 13 ). A device according to claim 4, characterized in that said gate lines are connected to a second shift register ( 106) and said source or drain lines are connected through second switch means ( T10-T12 ) to an amplifier ( 105 ). A device according to claim 1, further comprising additional accumulating elements ( C10-C12 ) connected through said first switch means to said accumulating elements ( C1-C9 ). A device according to claim 6, further comprising an additional switch means ( CT1-CT3 ) for resetting said additional accumulating elements. An image information processing apparatus comprising: an image reading device according to claim 1, original support means (106) for supporting an original (6) , bearing information thereon, in a reading position for image reading by said image reading device, and recording means (110) for recording image information read by said image reading device. An apparatus according to claim 8, characterized in that said recording means is a recording head (110) for forming a record by ink discharge utilizing thermal energy.

Inventors: ENDO TADAO, KAIFU NORIYUKI, KOBAYASHI ISAO, SAIKA TOSHIHIRO, ENDO, TADAO, KAIFU, NORIYUKI, KOBAYASHI, ISAO, SAIKA, TOSHIHIRO, ENDO, TADAO, C/O CANON KABUSHIKI KAISHA, KAIFU, NORIYUKI, C/O CANON KABUSHIKI KAISHA, KOBAYASHI, ISAO, C/O CANON KABUSHIKI KAISHA, SAIKA, TOSHIHIRO, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1991
Main classification: H04N3
IPC codes: H01L27, H04N3, H04N1