MESFET and manufacturing method therefor

Abstract: A field effect transistor comprises a semi-insulating first compound semiconductor substrate having a surface, a first compound semiconductor active layer disposed at the surface of the substrate and having a first dopant concentration, a gate electrode disposed on the active layer, an epitaxial first compound semiconductor source region disposed on part of the active layer spaced from the gate electrode wherein the source region has a second dopant concentration higher than the first dopant concentration, a source electrode disposed on the source region, an electrically insulating layer disposed on the active layer between and contacting the source region and the gate electrode, a drain region disposed in the substrate adjacent to and in contact with the active layer on an opposite side of the gate electrode from the source region having a dopant concentration intermediate the dopant concentrations of the source region and the active layer, and a drain electrode disposed on the drain region. A method of manufacturing a field effect transistor comprises sequentially epitaxially growing on a semi-insulating compound semiconductor substrate an active layer of the first compound semiconductor having a first dopant concentration and a source layer of the first compound semiconductor having a second dopant concentration higher than the first dopant concentration, removing part of the source layer to leave a source region on the substrate, forming a gate electrode on the active layer spaced from the source region, forming a drain region in the substrate spaced from the gate electrode, on the opposite side of the gate electrode from the source region, adjacent to and in contact with the active layer and having a dopant concentration intermediate the dopant concentrations of the active layer and the source region, and forming source and drain electrodes on the source and drain regions, respectively.

Description: The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. In a conventional enhancement type FET, an active layer is formed by ion implantation on the surface of a semi-insulating compound semiconductor substrate. At opposite ends of the active layer, source and drain regions are formed in the substrate by ion implantation. A gate electrode is disposed-on the active layer and forms a Schottky barrier with the active layer. For high quaiity performance, the dopant concentrations of the source and drain regions are as high as possible, and the active layer has a lower dopant concentration. When the source and drain regions are formed by ion implantation in GaAs, there is a limit to the dopant concentration of about 2 x 10 18 cm -3 . When there are crystalline defects in the substrate occurring naturally or as a result of the ion implantation process, a leakage current can flow between the source and drain regions, unaffected by the gate signal. This invention relates more particularly to an FET, as disclosed in JP-A-1-303762, comprising: a semi-insulating first compound semiconductor substrate having a surface; a compound semiconductor active layer disposed at the surface of the substrate and having a first dopant concentration; a gate electrode disposed on the active layer; an epitaxial first compound semiconductor source region disposed on part of the active layer spaced from the gate electrode wherein the source region has a second dopant concentration higher than the first dopant concentration; a source electrode disposed on the source region; a drain region disposed in the substrate on an opposite side of the gate electrode from the source region; and a drain electrode disposed on said first drain region. By employing such an arrangement, the dopant concentration of the source region can be increased so as to reduce the source resistance, and the leakage current can be reduced. The FET of JP-A-1-303762 is of the enhancement type. The present invention is firstly concerned with providing these advantages in the depletion type of FET and is secondly concerned with enabling an FET to have improved high frequency characteristics. The FET according to the present invention is characterised by: the drain region having a dopant concentration intermediate the dopant concentrations of the source region and the active layer; an electrically insulating side wall film disposed on the active layer between and contacting the source region and the gate electrode; and a first doped region disposed in the substrate between and in contact with the active layer and the drain region, and having a dopant concentration intermediate the dopant concentrations of the active layer and the drain region. Thus, a depletion type FET is provided, and the electrically insulating side wall film between the source region and the gate electrode enables a small spacing to be provided between the source region and gate electrode. Other features of the present invention, including a method of manufacturing such an FET are defined in the claims. Specific embodiments of the present invention will now be described by way of example with reference to the accompanying drawings, in which:- Figure 1 is a schematic cross-sectional view of an FET which will be described to illustrate the background to the invention. Figures 2(a)-2(f) are cross-sectional views illustrating a method of manufacturing the FET of Figure 1. Figure 3 is a schematic cross-sectional view of another FET which will be described to illustrate the background to the invention. Figures 4(a)-4(i) are cross-sectional views illustrating a method of manufacturing the FET of Figure 3. Figures 5(a) and 5(b) are a schematic cross-sectional view of a semiconductor device structure for an inverter circuit in accordance with an embodiment of the invention and a schematic view of an inverter circuit using the structure of Figure 5(a), respectively. Figures 6(a)-6(d) are schematic cross-sectional views illustrating a method of manufacturing the structure of Figure 5(a). Figures 7(a) and 7(b) are schematic cross-sectional views of dual gate FET structures in accordance with embodiments of the invention. In the structure shown in Figure 1, a semi-insulating GaAs substrate 1 has a surface on which a relatively low dopant concentration, n-type GaAs active layer 2, preferably prepared by epitaxial growth, is disposed. For convenience, the relative dopant concentration of layer 2 is designated n. A gate electrode 5, which may be a refractory metal silicide such as WSi x , is disposed on the active layer 2. A relatively highly doped, i.e., n ++ , n-type GaAs source region 4 is disposed on a highly doped n-type compound semiconductor etch-stopping layer 3 which, in turn, is disposed on the active layer 2. The etch-stopping layer 3 may be aluminum gallium arsenide (AlGaAs) or indium gallium arsenide (InGaAs) when, as preferred, the n-type source region 4 is GaAs. At the opposite end of the active layer 2 on the opposite side of the gate electrode 5 from the source region 4, an n-type GaAs drain region 6 of intermediate dopant concentration, i.e., n + , is disposed in the substrate 1, adjacent to and in contact with the active layer 2. The metal drain electrode 7 is disposed on the drain region 6 and the metal source electrode 8 disposed on the source region 4. In a typical structure, the dopant concentration of the source region 4 is approximately 1 x 10 19 cm -3 , of the drain region 6 is approximately 2 x 10 18 cm -3 , and of the active layer 2 is approximately 2 x 10 17 cm -3 . A method of making the FET structure of Figure 1 is illustrated in the schematic cross-sectional views of Figures 2(a)-2(f). Initially, as shown in Figure 2(a), the GaAs active layer 2, the etch-stopping layer 3 of AlGaAs or InGaAs, and the most heavily doped layer, GaAs layer 4', are successively epitaxially grown on the semi-insulating GaAs substrate 1. Typically, the active layer 2 is about 0.1 µm thick, the etch-stopping layer 3 is about 0.05 µm thick, and the heavily doped layer 4' is about 0.2 µm thick. A photoresist layer 11' (not shown) is deposited on layer 4' and formed into a resist pattern 11a on a portion of the heavily doped layer 4' by conventional photolithographic techniques. As illustrated in Figure 2(b), the mask 11a is employed for RIE of the heavily doped layer 4' and the etch-stopping layer 3. When the etch-stopping layer 3 is AlGaAs, the RIE may be typically carried out using chlorine as an etchant species at a gas pressure of 0.25 Torr with a gas flow rate of 10 standard cubic centimeters per minute (sccm). When, during etching, the etch-stopping layer 3 is exposed, aluminum species enter the RIE plasma and are spectroscopically detected from characteristic light wavelength emission of the aluminum species. Upon detection of aluminum in the plasma, the etching is terminated. Because the etch-stopping layer 3 is so thin, essentially all of the etch-stopping layer beyond the mask 11a is removed in the termination of the RIE process. Thereafter, the mask 11a is removed to produce the structure shown in Figure 2(b). The gate electrode 5 is formed by depositing the gate material, which may be a refractory metal silicide, a refractory metal, or tungsten nitride, for example, on the surface of the active layer 2 as well as on source region 4 by sputtering or another process. The excess gate material is removed by masking and etching so that the gate electrode 5, which may have a sub-micron gate length, is formed. Because of the use of the photolithographic process, the spacing between the source region 4 and the gate electrode 5 should be 0.5 to 1 µm depending upon the alignment precision of the photolithographic apparatus employed. A drain region 6 is produced by ion implantation. In order to protect the active layer 2 and the other elements of the FET structure outside the drain region during ion implantation, a photoresist film 11" (not shown) is deposited on the entire structure. An aperture is opened in the film 11" to expose an area of the active layer 2 spaced approximately 0.5 to 1 µm from the gate electrode 5 where the drain region is to be formed in the substrate 1. This patterning leaves photoresist mask 11b in place. Ions producing n-type doping, such as silicon ions when the substrate 1 is GaAs, are then implanted in the active layer 2 and substrate 1 using the resist pattern 11b as a mask to produce a dopant concentration of about 2 x 10 18 cm -3 . After removal of mask 11b, the surface of the structure is lightly etched with hydrofluoric acid (HF) to remove any damage that may have been produced during the ion implantation step. While this description of a method for making the structure of Figure 1 is directed to a single FET structure, in practice, many such FETs are usually made simultaneously on a single semiconductor wafer. In order to electrically isolate the FETs on the wafer from each other, still another photoresist film 11''' (not shown) is deposited on the surface and patterned to form a mask 11c, as shown in Figure 2(e). In that figure, the mask 11c extends exactly to the outer surfaces of the source region 4 and drain region 6 but absolute alignment precision of the mask with those surfaces is not required. Nevertheless, after etching to remove the portions of the active layer 2 that lie outside the mask 11c, the side surfaces of the mask and of the source region 4 and drain region 6 will be effectively aligned with the mask 11c. After removal of the mask 11c, the structure is annealed for approximately thirty minutes at 800° Centigrade consistent with the ion implantation step in which the drain region was formed. Finally, the device structure is completed by the formation of the drain and source electrodes 7 and 8 on the respective drain and source regions, as shown in Figure 2(f). The FET thus formed has significant advantages over the prior art structures. Since the source region 4 and the drain region 6 are independently formed, they can have different dopant concentrations. Since the source region is formed by epitaxial growth, it can have a relatively high dopant concentration, i.e., higher than can be achieved by ion implantation, and, therefore, a desirably low resistance. The relatively low dopant concentration active region intervenes in any current path through the substrate 1 between the source and drain regions so that the flow of leakage current due to defects in the substrate is prevented. In addition, because layers 2, 3, and 4 are successively epitaxially grown without interruption, interface defects between them are significantly reduced, contributing to a reduction in the source resistance. The employment of the etch-stopping layer 3 permits accurate control of the etching process in which the source region 4 is formed so that the active layer 2 is not significantly damaged by excessive etching. Moreover, since no layers are grown on the active layer 2 after removal of part of the source layer 4' by etching, no crystalline defects due to etching damage affect the crystallinity of other layers. Finally, since the gate electrode is formed on a planar surface, rather than a non-planar surface as in the process illustrated in Figure 11(b), the gate electrode 5 can be repeatedly produced with a high degree of uniformity in position and width. As an alternative to the ion implantation step of Figure 2(d), an n-type dopant impurity, including silicon, can be diffused through the opening in mask llb to form the drain region 6. While Figures 2(a)-2(f) and other figures are described as employing GaAs in the substrate 1, the active layer 2, and the source region 4, indium phosphide (InP) and other compound semiconductors can also be used to form FET structures according to the invention. The structure of Figure 3 is similar to that of Figure 1 except that the gate electrode 5b is much closer to the source region 4 and is separated from the source region 4 by an insulating side wall film 9b disposed on the active layer 2 and contacting side walls of the source region 4 and of the gate electrode 5b. A method of manufacturing the FET structure of Figure 3 is illustrated in schematic cross-sectional views in Figures 4(a)-4(i). The process steps illustrated in Figures 4(a) and 4(b) are the same as those illustrated in Figures 2(a) and 2(b) and, therefore, do not require additional explanation. In Figure 4(c), an electrically insulating film 9' has been deposited on the surface of the active layer 2 and on and covering the source region 4. The electrically insulating film 9' may be, for example, SiO x , where x ranges from 1 to 2, or SiN. As illustrated in Figure 4(d), the insulating film 9' is etched, for example, by RIE, leaving residual side wall films 9a and 9b, disposed on the active layer 2 and contacting each of two opposed side walls of the source region 4. As is known in the art, the widths of the residual side wall films 9a and 9b are approximately equal to the thickness of the insulating film 9' as deposited remotely from the source region 4. That thickness can easily be controlled to be as thin as 0.05 µm. The film deposition and RIE steps are repeated to form the side wall gate electrodes 5a and 5b shown in Figure 4(e). Those side wall gate electrodes of a refractory metal or a refractory metal silicide are formed by RIE of a film of the gate material deposited on the active layer 2 and covering the source region 4 and the side wall films 9a and 9b. A typical width, i.e., gate length, of the side wall gate electrodes 5a and 5b is roughly equal to the thickness of the gate material layer and may be 0.5 µm or less. In forming the gate electrodes, the RIE remote from the sectioning plane of the cross-section shown in Figure 4(e) leaves contact pads on the surface of the active layer 2. The side wall film 9a and the side wall gate electrode 5a are removed to form a single gate FET structure with the side wall gate electrode 5b as the gate electrode. A photoresist film 11' (not shown) is deposited and an aperture opened in the photoresist film using photolithographic techniques to form the mask 11d shown in Figure 4(f) and to expose the side wall gate electrode 5a and side wall film 9a. The side wall gate electrode 5a and the side wall film 9a are removed by RIE or another etching technique. The aperture formed in the photoresist film need not be precisely aligned with the junction between the source region 4 and the side wall film 9a, but any error in mask alignment should be controlled so that all of the side wall gate electrode 5a is removed even if a portion of the side wall 9a remains or a portion of the source region 4 and the etch-stopping layer 3 are removed in the etching. After removal of the photoresist pattern 11d, another photoresist film 11'' (not shown) is deposited and patterned by the opening of an aperture for the formation of the drain region 6 to form the mask 11e, as shown in Figure 4(g). The mask 11e exposes a portion of the area of the active layer 2. Generally, the opening in the mask 11e is spaced 0.5 to 1 micron from the gate electrode 5b. Ions producing n-type conductivity, such as silicon ions in a GaAs active layer 2 and substrate 1, are implanted, using the resist pattern 11e as a mask, to form the drain region 6. As described for Figure 2(f), in the step illustrated in Figure 4(h), still another photoresist film 11''' is deposited, a mask 11f is formed from the film, and etching is carried out to isolate the FET from other FETs or other electronic devices formed on the same wafer. The isolation is achieved by removing portions of the active layer 2 from the substrate that lie beyond the area between the source region 4 and the drain region 6. Finally, metallic drain and source electrodes 7 and 8 are formed on the drain region 6 and the source region 4, respectively, to complete the structure, as shown in Figure 4(i). While the source electrode 8 is shown as extending across the entire width of the source region 4, that electrode may be narrower to ensure that there is no short-circuit between the source electrode 8 and the gate electrode 5b. Since the insulating film 9b and the gate electrode 5b are formed using side walls, the source region 4 is completely insulated from the gate electrode while the spacing between the source region 4 and the gate electrode 5b is as short as possible and is not limited by the precision of mask alignment. Moreover, the spacing between the source region and the gate is not dependent upon the alignment precision of photolithographic processes. Since, as in the structure of Figure 1, the source region may be relatively highly doped because it is epitaxially grown, the source resistance is reduced over prior art FETs. Finally, because the gate length of the gate 5b is so short, the FET occupies a relatively small area and a high integration density can be achieved, the upper limit operating frequency is increased, and the power efficiency is improved. Figure 5(a) is a schematic cross-sectional view of a dual gate FET structure that, with appropriate interconnections, functions as an inverter. A schematic diagram of such an inverter circuit is shown in Figure 5(b). In Figure 5(b), FET 20, which corresponds to the left half of the structure of Figure 5(a), is a depletion-type FET and FET 30, which corresponds to the right half of the structure of Figure 5(a), is an enhancement-type FET. In Figure 5(b), the elements of the structure shown in Figure 5(a) are given the same reference numbers for convenience in comparing the two figures. The connection between the gate electrode 5a of FET 20 and the common source electrode 8 shown in Figure 5(b) is not shown in Figure 5(a). That connection can be made at connection pads that are remote from the section shown in Figure 5(a) or can be made by extending the source electrode 8 to overlap with and contact the gate electrode 5a. The structure of Figure 5(a) includes a doped region 10 of intermediate doping concentration disposed between the active layer 2 of relatively low dopant concentration and the intermediate dopant concentration drain region 6a to form the depletion-type FET 20. Otherwise, all of the elements of the structure of Figure 5(a) have previously been identified except that the two drain electrodes, identified as 7a and 7b, and the two drain regions, identified as 6a and 6b, are present. As in the structure of Figure 3, the spacing between the source region 4 and the two gate electrodes 5a and 5b is minimized and is not dependent upon the precision of photolithographic mask alignments. Leakage current flow between the common source region 4 and the drain regions 7a and 7b is prevented by the interposition of the active layer 2 and the intermediate dopant concentration doped region 10 between the source region and drain regions. Figures 6(a)-6(d) show important steps in a method for producing the structure of Figure 5(a). Initially, the processes illustrated by Figures 4(a)-4(e) are carried out. Since those processes have already been described, it is not necessary to describe them again. After the formation of the structure shown in Figure 4(e), yet another photoresist layer 11' (not shown) is deposited and formed into a mask 11g by opening two apertures lying on opposite sides of the source region 4 and spaced from the respective gate electrodes 5a and 5b, as shown in Figure 6(a). The drain regions 6a and 6b are formed by ion implantation, just as described for the other structures, using mask 11g to control the implanted areas. After removal of the mask 11g, a further photoresist layer 11' (not shown) is deposited over the entire surface of the structure and an aperture is opened in the layer, thereby forming ion implantation mask 11h of Figure 6(b). The opening in the mask 11h is generally aligned with the outside edge of the gate electrode 5a. If the aperture in the mask 11h should extend into the region of the gate electrode 5a, that gate electrode acts as an ion implantation mask so that the second ion implantation step is self-aligning with respect to that gate electrode. The doped region 10 is then formed by ion implantation using the mask 11h as an ion implantation mask. The doped region 10 has a dopant concentration intermediate that of the active layer 2 and the drain region 6a. In Figure 6(c), insulation is accomplished by masking and removing the active layer 2 beyond the two drain regions 6a and 6b. The isolation step is analogous to the steps illustrated in Figures 2(e) and 4(h). Finally, after removal of mask 11i used in the isolating step and any annealing necessary in conjunction with the ion implantation steps, source electrode 8 and drain electrodes 7a and 7b are deposited, completing the structure. The structure of Figures 5(a) and 6(d), which may be employed as an inverter, incorporates one depletion-type FET and one enhancement-type FET. Related dual gate structures incorporating two enhancement-type or two depletion-type FETs can be easily made. Examples of such structures are shown in Figures 7(a) and 7(b), respectively. Two enhancement-type FET structures with a common source region, i.e., a dual gate enhancement-type FET, are shown in a schematic cross-sectional view in Figure 7(a). In Figure 7(b), each of two depletion-type FETs includes intermediate dopant concentration doped regions 10a and 10b disposed between the active layer 2 and the respective drain regions 6a and 6b. The FETs have a common source region but separate gate and drain electrodes. As with the structure of Figure 5(a), the structures of Figures 7(a) and 7(b) can be prepared with a high integration density, producing high speed performance that is especially suitable for use in linear GaAs integrated circuits. Although, in the structures of Figures 4(i), 6(d), 7(a), and 7(b), the source electrode 8 is exactly aligned with and extends between the side walls of the source region 4, such precise alignment is not required. Rather, the electrode 8 may be narrower than the source region 4 or may be offset to one side or the other of the source region 4 so long as no unintended short-circuiting to any of the gate electrodes occurs. The FETs described have n-type source and drain regions, n-type active layers, and n-type doped regions in the depletion-type FETs. As is understood in the art, n-type doping in FETs is preferred because the mobility of electrons is larger than that of holes. However, the invention can be applied to FETs with p-type regions, provided all of the doped elements of an FET are of the same conductivity type.

Claims: A field effect transistor comprising: a semi-insulating first compound semiconductor substrate (1) having a surface; a compound semiconductor active layer (2) disposed at the surface of the substrate and having a first dopant concentration; a gate electrode (5a) disposed on the active layer; an epitaxial first compound semiconductor source region (4) disposed on part of the active layer (2) spaced from the gate electrode (5a) wherein the source region (4) has a second dopant concentration higher than the first dopant concentration; a source electrode (8) disposed on the source region (4); a drain region (6a) disposed in the substrate (1) on an opposite side of the gate electrode (5a) from the source region (4); and a drain electrode (7a) disposed on said first drain region (6a); which field effect transistor is characterised by: the drain region having a dopant concentration intermediate the dopant concentrations of the source region (4) and the active layer (2); an electrically insulating side wall film (9a) disposed on the active layer (2) between and contacting the source region (4) and the gate electrode (5a); and a first doped region (10; 10a) disposed in the substrate (1) between and in contact with the active layer (2) and the drain region (6a), and having a dopant concentration intermediate the dopant concentrations of the active layer (2) and the drain region (6a). A field effect transistor as claimed in claim 1, and further comprising: a second gate electrode (5b) disposed on the active layer (2) on the opposite side of the source region (4) to the first-mentioned gate electrode (5a); a second electrically insulating side wall film (9b) disposed on the active layer (2) between and contacting the source region (4) and the second gate electrode (5b); a second drain region (6b) disposed in the substrate (1) on the same side of the source region (2) as the second gate electrode (5b) with the second gate electrode (5b) disposed between the source region (4) and the second drain region (6b), and having a dopant concentration intermediate the dopant concentrations of the source region (4) and the active layer (2); and a second drain electrode (17b) disposed on the second drain region (6b). A field effect transistor as claimed in claim 2, further comprising: a second doped region (10b) disposed in the substrate (1) between and in contact with the active layer (2) and the second drain region (6b). The field effect transistor as claimed in any one of the preceding claims wherein the compound semiconductor is selected from the group consisting of GaAs and InP. The field effect transistor as claimed in any one of the preceding claims wherein the substrate (1) is GaAs, the dopant concentration of the active layer (2) is approximately 2 x 10 17 cm -3 , the dopant concentration of the source region (4) is approximately 1 x 10 19 cm -3 , and the dopant concentration of the first-mentioned drain region (6a), or said first and second drain regions (6b,6a), is approximately 2 x 10 18 cm -3 . A method of manufacturing a field effect transistor according to any of the preceding claims comprising the following steps: (a) sequentially epitaxially growing on a semi-insulating compound semiconductor substrate (1), an active layer (2) of a compound semiconductor having a dopant concentration and a source layer (4') of the first compound semiconductor having a second dopant concentration higher than the first dopant concentration; (b) removing part of the source layer (4') to leave a source region (4) on the substrate (1); (c) depositing an electrically insulating film (9') on the active layer (2) and on and covering the source region (4); (d) etching the electrically insulating film (9') to remove it from the source region (4) and from part of a the active layer (2), leaving a side wall film (9b) of the electrically insulating film (9') disposed on the active layer (2) and contacting a side wall of the source region (4); (e) depositing a gate electrode material layer on the active layer (2) and on and covering the source region (4) and the side wall film (9b); (f) etching the gate electrode material layer to remove it from the source region (4) and from part of the active layer (2), leaving a side wall gate electrode (5b) disposed on the active layer (2) and contacting the side wall film (9b); (g) forming a drain region (6b) in the substrate (1) spaced from the gate electrode (5b), on the opposite side of the gate electrode (5b) from the source region (4), and having a dopant concentration intermediate the dopant concentrations of the source region (4) and the active layer (2); (i) forming source and drain electrodes (8,7b) on the source and drain regions (4,6b), respectively; and (j) forming a doped region (10b) in the substrate (1) between and contacting the drain region (6b) and the active layer (2), and having a dopant concentration intermediate the dopant concentrations of the active layer (2) and the first drain region (6b). A method as claimed in claim 6, wherein: as a result of the step of etching the electrically insulating film, a second side wall film (9a) of the electrically insulating film (9') is left, disposed on the active layer (2) and contacting a side wall of the source region (4) opposite the first-mentioned side wall film (9b); and as a result of the step of etching the gate electrode material layer, a second side wall gate electrode (5a) is left, disposed on the active layer (2) and contacting the second side wall film (9a); the method further comprising the steps of: forming a second drain region (6a), in the substrate (1) spaced from the second gate electrode (5a), on the opposite side of the second gate electrode (5a) from the source region (4), and having a dopant concentration intermediate those of the source region (4) and the active layer (2); and forming a second drain electrode (7a) on the second drain region (6a). A method as claimed in claim 7, further including the steps of forming a second doped region (10a) in the substrate (1) between and contacting the second drain region (6a) and the active layer (2), and having a dopant concentration intermediate the dopant concentrations of the active layer (2) and the second drain region (6a). A method as claimed in any of claims 6 to 8, wherein the or at least one of the doped regions (10a,10b) is formed by ion implantation.

Inventors: NAKATANI MITSUNORI, NAKATANI, MITSUNORI, NAKATANI, MITSUNORI, C/O MITSUBISHI DENKI K. K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1991
Main classification: H01L29
IPC codes: H01L29, H01L21, H01L27