Short circuit detector circuit for memory array

Abstract: A method for detecting voltage supply short circuits in integrated circuits and a circuit for implementing that method is disclosed. Entire rows of memory cells in an SRAM are coupled to a single sense line. The sense line to each row is activated individually. The sense lines are in turn coupled to a current sensing circuit. If a short exists on any memory cell in a given row, the current sensing circuit generates a low output, indicating a short circuit.

Description: This invention relates to Static Random Access Memories ("SRAMs"). In particular, it relates to a circuit which can be incorporated into a SRAM to simplify the detection of power supply short circuits within arrays of SRAM memory cells. A generic SRAM memory cell is shown in Figure 1a. The construction and operation of such cells is known. In the illustrated cell, transistor T₁ is the driver and transistor T₃ the load for an inverter that is cross-coupled to a second inverter formed from transistors T₂ and T₄, the two inverters forming a storage flip-flop. When transistor T₂ is on and transistor T₁ is off, output Q is a logic 1 (herein, +5V). With the row-select line low (0V), transistors T₅ and T₆ are off, and the cell is isolated from both bit lines. When the memory cell is read, as soon as the row-select line goes high (+5V), transistors T₅ and T₆ couple the bit lines to the cell and output Q appears on bit line D. As shown in Figure 1b, a sense amplifier is connected to the bit line to provide output buffering, and the proper logic level appears on the sense output line. In a write operation, the selected row of cells is connected to the bit lines, and Q or Q is set or reset by a logic 1 (+5V) placed on bit line D or D by the write amplifiers while a logic 0 (0V) is placed on the complement bit line. In this SRAM with nondestructive readout, the state of the flip-flop persists as long as power is supplied to the chip, and it is not altered by the read operation. It should be understood that an SRAM chip will comprise many thousands of such memory cells. In normal operations, transistors T₁and T₂ have a certain amount of capacitance, shown in Figure 1a as capacitors C₁ and C₂. If V dd were shorted to V ss , due to a manufacturing error, a certain amount of time would be required before the charge present on either C₁ and C₂ (the nature of the flip-flop requires that either Q or Q be high (+5V), but not both) is drained through transistors T₃ and T₄ to V ss . This discharge time is often large in comparison to the amount of time required to access the memory cell and the frequency of such access. It is therefore quite possible to read data several times from a cell with such a short circuit before the charge is dissipated sufficiently to detect the presence of the short. This long dissipation time makes testing for this type of short circuit a long, tedious and costly process. A method and/or an apparatus which can speed the process of testing for and detecting such power supply short circuits is needed. The document EP-A-0 146 975 discloses a short detection circuit incorporated in a programmable read only memory so that a selected positive voltage can be applied across each memory cell to allow the detection, prior to programming, of shorts between bit lines and word lines and shorts or leaks in a memory cell. By measuring the current flowing into the bit lines shorts or leaky junctions within memory cells can be detected in unprogrammed devices prior to actual delivery to a customer. The short detection circuit is isolated from the memory during normal operation thereof so that it does not have an adverse effect on the operation of the PROM. The present invention as defined in the independent claims provides a method to test an array of SRAM memory cells for power supply short circuits. It also provides a circuit for detecting such short circuits in conjunction with the testing method. According to one embodiment, each row of memory cells is individually activated and scanned. Each row select line is coupled to a common current sense line, which in turn is coupled to a current sense circuit. In operation, each successive row of memory cells is activated. If the voltage supply (V dd ) for that row of cells is shorted to ground (V ss ) or any lower voltage for any reason a current will flow through the current sense line and will be detected by the current sense circuit. The circuit which selects individual rows of memory cells for testing also provides a means for uniquely identifying the memory chip. Certain fuses within the select circuit can be selectively blown, the pattern of open fuses providing the identification information. The present invention will now be described in detail with reference to the following figures. Figure 1a shows a typical SRAM memory cell; Figure 1b shows the write and sense amplifiers coupled to the SRAM memory cell; Figure 2 shows the current sense row selector circuit; Figure 3 is a detailed schematic of the row selector circuit; and Figure 4 is a detailed schematic of the current sensing circuit. Figure 1a shows how each prior art SRAM memory cell is individually coupled to a row select line and to V dd , herein, by example only, +5V. In the present invention, as shown in Figure 2, the SRAM cell receives V dd ′, V dd being first coupled to R₁ which resistor limits the amount of current which can flow through the voltage supply lines to the memory cell. Each cell is coupled to a row line, shown in Figure 2 as row lines N and N + 1. As the particular workings of the memory cells is not relevant to an understanding of the present invention, the cells are not illustrated in Figure 2. For the purposes of this description, it suffices to state that each cell is coupled to the current sense row selector circuit shown in Figure 2 by means of the memory cell's row select line and its V dd ′ voltage supply line. There can be any arbitrary number of rows of memory cells. Row line N and memory cell supply V dd ′N are coupled respectively to the gates of PMOS transistors T₈ and T₉. Similarly, the gates of transistors T₁₀ and T₁₁ are coupled respectively to memory cell supply V dd ′N+1 and row line N + 1. In this type of SRAM array, voltage supply V dd ′ to the cell can be inadvertently shorted to either V ss or, possibly, to a row line which is active low (0V) as a result of a manufacturing defect. Such short circuits can be detected by using this invention in a test mode. When the present invention is used in its test mode, each consecutive row of memory cells is scanned. When a row becomes active (row N, for example), PMOS transistor T₈ turns on. If V dd ′ is shorted low for any reason, transistor T₉ will also turn on. Current will then flow through current sense line 20 (Figure 2) to current sense circuit 30. The current sense circuit, as will be explained, detects even small current flows through the current sense line when the SRAM is being tested. It outputs a logic signal to indicate if such a flow is detected. A detailed schematic of the row select circuit is shown in Figure 3. As discussed transistors T₈ and T₉, whose gates are respectively coupled to the row select signal and V dd ′, the isolated memory matrix supply voltage, act to detect shorts in the matrix between V dd ′ and either V ss or the row select signal, which is active low. This is done by selecting a particular row, whereby that row's select signal goes low and transistor T₈ turns on. If V dd ′ is low, the result of a short circuit, transistor T₉ will turn on and current will flow along the SSTENS line (current sense line 20, Figure 2) to current sensing circuit 30 (Figure 2) during the supply short circuits test mode. Transistor T₁₂ is a pull-up transistor for the row select signal which maintains a high voltage level of V dd for nonselected row select lines. Another feature of the row select circuit is that it provides a circuit ID encoding scheme. This is done in a similar fashion to the voltage supply short circuit test. The row select signal selects the appropriate row. If fuse F₁ is not open, current will flow through the IDSENS signal line. There is one fuse per row of memory cells and it can be blown or not blown to encode the chip lot and wafer number or other desired information. Resistors R₂, R₃ and R₄ are used to isolate the memory cell top supply V dd ′ from the external supply V dd . Doing so limits the current that can flow if a short circuit occurs to approximately 1 ma. If fuse F₂ opens, the flow of current stops completely. A detailed schematic drawing of current sensing circuit 30 is shown in Figure 4. The MODE signal is used to turn the sensing circuit on during test mode. In the test mode, node A is set at V dd - 2V be (transistor T₂₂ and T₂₄ providing the requisite 2V be drops) as a reference voltage level for the gate of PMOS transistor T₂₆. T₂₆ serves as a cascode device coupled to the bottom rail of circuit 30. When not in the matrix voltage supply short circuit test mode, the MODE signal is low. Transistor T₂₃ is off and transistor T₂₁ is on, holding node A at the supply voltage V dd . In turn, transistor T₂₆ turns off, allowing resistor R₁ to hold node B low. Transistor pairs T₂₉/T₃₁, T₃₂/T₃₄ and T₃₅/T₃₇ act as inverters so when node B is low, the output ('OUT') of the circuit is high. In the test mode, the MODE signal is high. This turns off transistors T₂₁ and T₂₅ and turns transistor T₂₃ on. With transistor T₂₃ on, node A is biased to V dd - 2V be , the voltage drop through T₂₂ and T₂₄. Node B will change voltage as current modulation occurs along the SENSLINE signal in test mode. When current is sensed, node B will rise, tripping the three inverters that drive the OUT output signal. The beta ratio for the first inverter (T₂₉/T₃₁) is low to allow node B, which has a small voltage swing, to trip the three inverters. Bipolar transistors T₂₇ and T₂₈ are used to clamp the low level voltage to a certain minimum on the SENSLINE signal line to prevent SENSLINE voltage from coupling around. Transistor T₂₆ will clamp the high level of the SENSLINE signal to V dd - 2V be + V tp . Although the present invention has been described in the specific environment of a BiCMOS SRAM, its utility is not limited thereto. Its use in any type of SRAM or even in a dynamic random access memory is easily envisioned. Therefore, this application should not be read in a limited sense.

Claims: A method for testing an array of memory cells for short circuits, the cells being arranged in rows, the method comprising: coupling the cells of the array to a plurality of row select lines and a current sense line (20), each row of memory cells being coupled to a different row select line; coupling said current sense line to a current detector circuit (30); characterized by the steps of: sequentially activating each row select line; and detecting whether any current flows through the current sense line when the row select line is activated. The method of claim 1 wherein the coupling of each row select line to the current detector circuit occurs upon command of a computer coupled to the array of memory cells. The method of claim 1 wherein the step of activating each row select line sequentially occurs upon commands received from a computer to which the array of memory cells is coupled. A circuit for detecting voltage supply short circuits in an array of static random access memory cells, the cells being arranged in rows and each row being coupled to a row select line, the cells having a power supply, the circuit characterized by: a first (T8) and second (T9) PMOS transistor coupled in series, their gates being coupled respectively to the voltage supply (V′ DD ) for the cells and the row select line, the source of the first transistor coupled to the power supply, the drain of the first transistor and the source of the second transistor being coupled together; a current sense line (20) coupled to the drain from the second PMOS transistor; and a current detector circuit (30) coupled to the current sense line which provides a logic output signal when current flows in the current sense line. The circuit of claim 4 wherein said second transistor has its gate coupled to an external power supply (V DD ). The circuit of claim 5 wherein there is one pair of first and second transistors for each row of memory cells. The circuit of claim 4 wherein the current sensing circuit comprises: first switching network (T21, T23) coupled to a first circuit node (A), the first switching network being coupled to receive a testing mode input signal, the first switching network biasing the first circuit node to the power supply voltage when the testing mode input signal is low and biasing the first circuit node to a lower voltage when the testing mode signal is high: current sensing transistor means (T25, T26) coupled to the current sense line, the first circuit node and a second circuit node (B), the current sensing transistor means conducting current from the current sense line when the testing mode input signal is high, the voltage at the second circuit node increasing as increasing current flows through the current sensing transistor means; and inverter output circuit (T29-T37), for outputting a high voltage signal when the voltage at the second circuit node rises above a predefined value, coupled to the second circuit node. The circuit of claim 7 wherein the inverter output circuit further comprises three inverter logic gates coupled together in series so that a low input value becomes a high output value.

Inventors: KERTIS ROBERT A, KERTIS, ROBERT A.
Applicants: NAT SEMICONDUCTOR CORP, NATIONAL SEMICONDUCTOR CORPORATION
Application year: 1991
Main classification: G11C29
IPC codes: G11C29, G11C11, H01L27