RADIO TEST LOOP FOR A RADIO TRANSCEIVER

Abstract: The invention relates to a device (11) for looping a radio-frequency quadrature-modulated test signal transmitted by a transmitter section in a duplex type transceiver to a receiver section for testing the transceiver. The device (11) of the invention comprises a quadrature-demodulator (23) for demodulating the transmitting-frequency signal into two base-frequency quadrature-phase signals (I, Q); and a quadrature-modulator (28) for modulating said base-frequency signals into a receiving-frequency quadrature-modulated test signal. Electronic delay lines (26A, 26B) are connected between the demodulator (23) and the modulator (28) for delaying both base-frequency signals (I, Q) separately with a period of time corresponding to the time difference required between the transmission and reception of the transceiver.

Description: Radio test loop for a radio transceiver The invention relates to a device for looping a radio-frequency quadrature-modulated test signal transmitted by a transmitter section in a transceiver to a receiver section for testing the transceiver. The specifications of the European mobile telephone system GSM (Groupe Special Mobile) define a test function in which a base station tests the oper- ation of the radio sections of its transceiver by generating a test signal which is transmitted by the transmitter section and which is looped back to the receiver section. The object of the invention is to provide a device forming a test loop of this type. This is achieved by means of a device of the invention which is characterized in that the device comprises a quadrature-demodulator means for de¬ modulating the transmitting-frequency quadrature- modulated test signal into two base-frequency quadrature-phase signals; a quadrature-modulator means for modulating said base-frequency signals into a receiving-frequency quadrature-modulated test signal; and a delay means connected between the de- modulator and modulator means for delaying both base- frequency signals separately by a period of time cor¬ responding to the time difference required between the transmission and reception of the transceiver. To loop a test signal generated by the trans- mitter in an appropriate way to the receiver, the test signal should be converted over a duplex inter¬ val from the transmitting frequency to the receiving frequency and delayed by a period of time correspond¬ ing to the time difference defined between the trans- mission and reception of one channel in the trans- ceiver, in the GSM specifications three channel intervals. In addition, the transceiver may operate in the frequency hopping mode, whereby the used frequencies change from one test interval to another. It is difficult to combine these properties especially in view of the required delay. The realization of the delay at the used frequencies (800 to 1000 MHz) on a coaxial delay line or the like would result in physical delay line lengths im- possible to realize in practice. In the invention, the test signal is de¬ modulated to the base frequency and the delay is realized by delaying both base-frequency signals I and Q before they are quadrature-modulated to the receiving frequency. The delay of the base-frequency signal can be realized by means of an electronic delay line. In the preferred embodiment of the invention, the delay of the base-frequency signal is realized by means of a delay line based on analog charge transfer. This is the simplest and most advantageous way of realizing the required delay. In another embodiment of the invention, the delay line is realized digitally. However, this embodiment has at least the following shortcomings as compared with the analog solution: - the A/D and D/A conversions of the test signal impair the signal-to-noise ratio unless a high resolution is used; - rapid high-resolution A/D and D/A converters increase costs; -digital circuits require more circuit board space; - analog and digital circuits coupled to the signal path require different sources of operating voltage, whereby the combining of the different operating voltages would interfere with the analog test signal. In the following the invention will be described in greater detail by means of exemplifying embodiments with reference to the attached drawings, in which Figure 1 is a block diagram of a transceiver comprising a device of the invention; and Figure 2 illustrates the principal features of the device of the invention by means of a schematic block diagram. The purpose of the radio test unit of the invention is to enable a radio-frequency test signal generated by the transmitter section of a full duplex-type transceiver to be controlled in such a way that it is passed appropriately back to the receiver section of the same transceiver for reception and analyzing. In this way, a test loop is formed which contains at least the radio sections of the transceiver, possibly also the multiplexing means, etc. The condition and operation of the transceiver can be automatically observed by measuring the test performance and suitable properties of the received test signal passed through the test loop. In the following, the invention will be described in connection with a transceiver to be used at the base station of a cellular mobile radio telephone system, but the invention is not in any way restricted to this application. In Figure 1, the transceiver comprises at least two, preferably four, transmitter-receiver pairs 1A, 10A and IB, 10B, respectively, whereby each pair forms one full duplex link. The outputs of the trans- mitter units 1A and IB are coupled by means of a summing means 2 to a common antenna line 3 and to a common transmitting antenna 4. A receiving antenna 6 is coupled through an antenna line 7 to a branching device 9 which divides the received signal to the receiver units 10A and 10B. As used in this con¬ nection, the transmitter and receiver units refer primarily to the radio sections of the transceiver. Each transmitter and receiver unit has its own trans¬ mitting or receiving frequency, whereby the trans- mitting and receiving frequencies of units forming a full duplex pair, e.g., 1A and 10A, are positioned at a distance of one duplex interval from each other, e.g. 45 MHz. In addition, each frequency channel is TDMA time-division multiplexed so as to comprise several digital traffic and/or control channels. The GSM specification defines eight base frequencies for the base station, each divided into eight channel intervals. In the preferred embodiment of the invention, a radio test unit 11 is coupled between the antenna lines 5 and 7. For this purpose, the antenna line 5 comprises a branching device 3 which branches a portion of the transmitted signal to an input 12 in the radio test unit 11. An output 13 in the radio test unit 11 is coupled to the antenna line 7 by means of a directional coupler 8 which applies an output signal from the radio test unit to the antenna line 7 in a direction towards the receiver units. Alternatively, the radio test unit can be e.g. coupled directly to the individual transmitter and receiver units. Figure 2 is a block diagram of the preferred embodiment of the radio test unit 11. From the input 12, a radio-frequency test signal, e.g. 800-1000 MHz, is applied through a fixed attenuator 21 to a branch- ing device 22 which divides the signal to inputs A and B in a quadrature demodulator 23, whereby the signals at the inputs are mixed in mixers 23A and 23B by means of quadrature-phase local oscillator signals (a phase shift of 90 degrees) to a base frequency so as to form two quadrature-phase signals I and Q, the frequency range of which is between 0 and 100 kHz. The output signal I of the mixer 23A is applied through a lowpass filter 24A, an amplifier 25A, a delay line 26A, and a lowpass filter 27A to a mixer 28A in a quadrature modulator 28. Correspondingly, the output signal from the mixer 23B is applied through a lowpass filter 24B, an amplifier 25B, a delay line 26B and a lowpass filter 27B to a mixer 28B in the quadrature modulator 28. In the quadrature modulator 28, the signals I and Q are modulated by quadrature-phase local oscillator signals to the re¬ ceiving frequency. The output signals of the mixers 28A and 28B are combined by a summing means 29 to form the final test signal, which is applied through an amplifier 30 to a switching unit 31, which under the guidance of a control unit 38 switches the test signal through it only during predetermined test intervals. From the switching unit 31, the test signal is applied to a branching device 32, which divides the signal to a signal level control branch and through a bandpass filter 33 to the output 13 of the radio test unit. The purpose of the delay lines 26A and 26B is to delay the test signal before it is applied to the receiver for a period of time which corresponds to the time required between the transmission and reception of one line in the transceiver in question. In the GSM specifications, this time period is three channel intervals. The delay lines 26A and 26B are mutually identical. In the preferred embodiment of the invention, they are realized by a circuit based on analog sampling and charge offset, in which charges are transferred in synchronization with a clock signal generated by an oscillator 39. One suit¬ able circuit is RD5108A, which is manufactured by Reticon Inc and in which there are 2048 charge storing means coupled in sequence. The signals I and Q are sampled during every other clock period and the samples pass from one charge storing means to another during every clock period. The magnitude of the delay is determined by the frequency of the oscillator 39, 1.216 MHz in this specific case, thus obtaining the above-mentioned delay of three channel intervals in conformity with the GSM system. The delayed signals I and Q at the outputs of the delay lines 26A and 26B are sampled analog signals, the spectra of which in¬ clude the sampling frequency. This sampling frequency is removed by means of the lowpass filters 27A and 27B connected after the delay lines. Alternatively, the delay lines 26A and 26B may be realized digitally, whereby they comprise an analog-to-digital converter, a digital shift register and a digital-to- analog converter for both base-frequency signals. In the preferred embodiment of the invention, the switching unit 31 has " two primary functions: 1) to separate the test signal at the output of the modulator 28 sufficiently efficiently from the receiver between the test intervals, and 2) to set the initial level of the test signal to a desired value. Therefore, the input of the switching unit comprises a branching means 311 which divides the output signal of the amplifier 30 into two branches. The first branch comprises three switching means 312, 313 and 314 connected in series and an amplifier with constant gain, so that the gain of the branch is 15 dB. The other branch comprises two switching means 316 and 317 connected in series and a fixed attenuator 318, the attenuation of the branch being 15 dB. In the preferred embodiment of the invention, the difference in the power levels of signals passed through the different branches is thus 30 dB. The output signals of the attenuator 318 and the amplifier 315 are fed to a summing means 319, the output of which forms the output of the switching unit 31 coupled to the branching device 32. During the test interval, the control unit 38 causes the switching means 312 to 314 to be closed by a control signal RF HIGH or alternatively causes the switching means 316 to 317 to be closed by a control signal RF LOW so as to apply a receiving-frequency test signal to the receiver. Between the test intervals, the switching means of both branches are open, so that they separate the test signal from the input of the receiver. The choice of the power level of the branch and the test signal depends on whether it is the upper or lower end of the dynamic range of the re¬ ceiver that is to be tested. The attenuation of open switching means within the radio frequency range has to be such that the level of a signal leaking through an open branch is at least 25 dB smaller than the signal level at the output of the selected branch. In the preferred embodiment of the invention, the switching means are realized by PIN diodes. The alternative power levels of the test signal may be formed by combinations of switches, amplifiers and attenuators different from that described above, provided that at least two alternative signal paths having different fixed attenuations or gains are achieved. The level of the test signal leaking to the output of the radio test unit 11 is monitored by passing a portion of the output signal of the switching unit 31 by the branching device 32 to the power level control branch, in which the power level of the signal is measured. If the power level of the output signal between the test intervals exceeds a predetermined threshold level, the control unit 38 assumes that the switches are damaged or operate faultily and prevents the generation of the test signal by interrupting the supply of operating power to the oscillator 45, for instance. The power level control branch also monitors the level of the outpulled test signal during the test interval. If the power level of the test signal during the test does not exceed the predetermined threshold level, the control unit 38 assumes that the switching unit 31 has operated faultily and disregards the loop test performed during this interval. In the preferred embodiment of the invention, the control branch com¬ prises a series connection of the following com¬ ponents in the following order: a bandpass filter 34; a switching means 35 operating in its closed state as a 10 dB attenuator for protecting subsequent com- ponents; a rectifier formed by a diode Dl; and a level measuring circuit, such as a comparator, posi¬ tioned in the control unit 38. The control unit 38 causes the switching means 35 to open during the test intervals and to close between the test intervals by a signal SDETC. The local oscillator signals of the demodulator 23 are generated from the output signal of a frequency synthesizer 44 by feeding it to the mixer 23A with a phase shift of 0° and to the mixer 23B with a phase shift of 90°. Correspondingly, the local oscillator signals of the modulator 28 are formed by feeding the output signal of a frequency synthesizer 45 to the mixer 28A of the modulator 28 with a phase shift of 0° and to the mixer 28B with a phase shift of 90°. During testing, the radio test unit receives a test signal from the transmitter unit 1 and transmits it further to the receiver section 2 either during every test interval within the same fixed frequency channel or, when the transceiver operates in the fre¬ quency hopping mode, by changing the physical fre¬ quency channel during each test interval. The operation of the frequency synthesizers is controlled and monitored by means of the control unit 38. During testing, the control unit 38 receives from some other component in the transceiver, e.g. from the frequency hopping unit, an absolute channel number for each test interval prior to the beginning of the test interval. Thereafter the control unit 38 generates command data from this absolute channel number for the synthesizers 44 and 45, on the basis of which data the output signals of the synthesizers are locked to a frequency corresponding to each par¬ ticular channel. In the preferred embodiment of the invention, in which each frequency channel has eight channel intervals, the command data is applied to the synthesizers approximately 4ms, i.e. 7 intervals, before the test interval. In this way, it is ensured that the synthesizers 44 and 45 have a setting time of at least 3 ms before the test interval. About 0.5 ms before the beginning of the test interval, the control unit 38 monitors the states of alarm signals RXALM and TXALM of the synthesizers, which signals indicate whether the synthesizers 44 and 45 have locked or not. If both synthesizers have locked before the beginning of the test interval, the control unit 38 controls the switching unit 31 so that it connects the test signal to the output 13 for the test interval. If only one or neither one of the synthesizers 44 and 45 has locked before the beginning of the test interval, the control unit 38 does not close the switches of the switching unit 31 and the test signal will not be applied to the output 13, so that the interference of the receiver is prevented. The control unit 38 contains several error counters for monitoring the operation of the radio test unit. Error counters to be updated include a frequency hopping command counter, synthesizer counters, switching unit counters and a counter for test intervals lost due to an error in the test unit during testing. The correctness of the received channel number commands is controlled by means of the frequency hopping command counter. The control unit 38 receives the channel numbers from the transceiver in duplex form and checks that both channel numbers are identical and that they have the right parity. If this is not the case, the control unit updates the frequency hopping counter and does not generate command data to the synthesizers 44 and 45. In this way, the test interval in question is disregarded in the radio test unit and the counter for lost inter¬ vals is incremented. A separate synthesizer counter is provided for each synthesizer, which counter is incremented if the synthesizer is not locked before the test interval and the test interval is disregarded. If the reading of the synthesizer counters exceeds a predetermined threshold value, the operation of the radio test unit stops wholly. The switching unit counter is incremented if it is found out that the switches of the switching unit 31 have not closed or opened at the proper time during testing. The figures and the description related to them are only intended to illustrate the present inven¬ tion. In its details, the device of the invention may vary within the attached claims.

Claims: Claims : 1. Device for looping a radio-frequency quadrature-modulated test signal transmitted by a transmitter section (1A, IB) in a transceiver to a receiver section (2A, 2B) for testing the transceiver, c h a r a c t e r i z e d in that the device (11) comprises a quadrature-demodulator means (23) for demodulating the transmitting-frequency quadrature-modulated test signal into two base-fre¬ quency quadrature-phase signals (I, Q); a quadrature- modulator means (28) for modulating said base- frequency signals into a receiving-frequency quadrature-modulated test signal; and a delay means (26A, 26B) connected between the demodulator and modulator means (23, 28) for delaying both base- frequency signals (I, Q) separately by a period of time corresponding to the time difference required between the transmission and reception of the trans- ceiver. 2. Device according to claim 1, c h a r a c ¬ t e r i z e d in that the delay means (26A, 26B) comprises a delay line based on analog charge trans¬ fer for both base-frequency signals (I, Q), and that both delay lines are controlled by the same clock signal, the frequency of which determines the magnitude of the delay. 3. Device according to claim 2, c h a r a c ¬ t e r i z e d in that the output signal of both delay lines (26A, 26B) is filtered (27) for removing the frequency of the clock signal controlling the delay lines from the delayed signal prior to modula¬ tion. 4. Device according to claim 1, c h a r a c - t e r i z e d in that the delay means (26A, 26B) comprises a digital delay line for both base- frequency signals, said delay line comprising an analog-to-digital converter, a digital transfer register and a digital-to-analog converter. 5. Device according to claim 1, c h a r a c ¬ t e r i z e d in that the local oscillator signal frequencies of the demodulator means (23) and the modulator means (28) are adjustable independently of each other. 6. Device according to any of the preceding claims, c h a r a c t e r i z e d in that the device (11) is connected between the a transmitting antenna line (5) and a receiving antenna line (7) in the transceiver. 7. Device according to claim 6, c h a r a c ¬ t e r i z e d in that switching means (31) are provided between the output of the modulator means (28) and the receiving antenna line (7) for connect¬ ing the modulator means (28) to the receiving antenna line only during predetermined test intervals. 8. Device according to any of the preceding claims, for use in a TDMA system, c h a r a c t e r ¬ i z e d in that said delay is 3 channel intervals.

Inventors: KATISKO KEIJO, KATISKO, KEIJO
Applicants: TELENOKIA OY
Application year: 1991
Main classification: H04B17
IPC codes: H04B17, H04W24