CAPACITIVE STRUCTURES FOR WEIGHTED SUMMATION, AS USED IN NEURAL NETS

Abstract: The capacitances of a pair of capacitors associated with a neural net are arranged to be complementary in value, even where their differential capacitance is subjected to variation, so the sum of the capacitances remains equal to a constant, Ck. Each of a set of component capacitors with capacitances related in accordance with powers of two is selected to be a component of one or the other of the pair of capacitors, the selecting being done by field effect transistors (FETs) operated as transmission gates. The gate signals for the FETs are respective ones of the bits in a binary number stored in a word storage element of a semiconductor memory.

Description: CAPACITIVE STRUCTURES FOR WEIGHTED SUMMATION, AS USED IN NEURAL NETS The invention relates to capacitive structures, as can be realized using complementary metal-oxide-semiconductor (CMOS) technology, that can implement weighted summation procedures and are useful in neural nets. BACKGROUND OF THE INVENTION 1 0 The networking ability of the neurons in the brain has served as a model for the formation of a highly interconnected set of processors, called a "neural network" or "neural net" that can provide computational and reasoning functions without the need of formal 1 5 programming. The neural nets can learn the correct procedure by experience rather than being preprogrammed for performing the correct procedure. The reader is referred to R.P. Lippmann's article "An Introduction to Computing With Neural Nets" appearing on pages 4-21 of the April 1987 IEEE ASSP MAGAZINE (0740-7467/87/0400- 20 0004/$10.00 " 1987 IEEE), incorporated herein by reference, for background about the state of the art in regard to neural nets. Neural nets are composed of a plurality of neuron models, processors each exhibiting "axon" output signal response to a plurality of "synapse" input signals. In a type of neural net called a 25 "perceptron", each of these processors calculates the weighted sum of its "synapse" input signals, which are respectively weighted by respective weighting values that may be positive- or negative- valued, and responds non-linearly to the weighted sum to generate the "axon" output response. This relationship may be described in ' 30 mathematical symbols as follows. Here, i indexes the input signals of the perceptron, of which there are an integral number M, and j indexes its output signals, of which there are an integral number N. Wj is the SUBSTITUTE SHEET weighting of the i th input signal as makes up the j tn output signal at such low input signal levels that the function f| _£ w i ;j Xi is approximately linear. At higher absolute values of its argument, the function fj w i# j Xi no longer exhibits linearity, but rather exhibits -i-l a reduced response to J i-l A more complex artificial neural network arranges a plurality of perceptrons in hierarchic layers, the output signals of each earlier layer providing input signals for the next succeeding layer. Those layers preceding the output layer providing the ultimate output signal(s) are called "hidden" layers. The processing just described normally involves sampled- data analog signals, and prior-art neural nets have employed operational amplifiers with resistive interconnecting elements for the weighting and summing procedures. The resistive elements implement weighted summation being done in accordance with Ohm's Law. The speed of such a processor is limited by capacitances in various portions of the processor, and computations have been slow if the power consumption of a reasonably large neural net is to be held within reasonable bounds. That is, speed is increased by reducing resistance values to reduce RC time constants in the processors, but the reduced resistance values increase the V2/R power consumption (R, C and V being resistance, capacitance and voltage, respectively.) Using capacitors to perform weighted summation in accordance with Coulomb's Law provide neural nets of given size operating at given speed that consume less power than those the processors which use resistors to implement weighted summation in accordance with Ohm's Law. A problem that is encountered when one attempts to use capacitors to perform weighted summation in a neural net layer is associated with stray capacitances, which problem tends to be a formidable one in neural net layers constructed using a metal-oxide- semiconductor (MOS) integrated circuit technology. The problem of stray capacitances between operating lines is compounded by the fact that the capacitive elements used to provide weights in a capacitive voltage summation network have stray capacitances to the substrate of the monolithic integrated circuit in which they are incorporated; a perfect two-terminal capacitance is not actually available in the monolithic integrated circuit. Where capacitive elements having programmable capacitances are used, capacitance is usually not programmable to zero value, either. In neural nets it is often desirable to be able to have inhibitory, or negative, weights as well as excitory, or positive weights. To avoid or solve the foregoing problems, the inventor has resorted to using the difference in capacitance between two capacitive elements to determine the weights in a capacitive voltage summation network. Neural nets employing capacitors in accordance with those described herein lend themselves to being used in performing parts of the computations needed to implement a back-propagation training algorithm. The back-propagation training algorithm is an iterative gradient algorithm designed to minimize the mean square error between the actual output of a multi-layer feed-forward neural net and the desired output. It requires continuous differentiable non- linearities. A recursive algorithm starting at the output nodes and working back to the first hidden layer is used iteratively to adjust weights in accordance with the following formula. Wi, j (t+l) = Wy(t) - ηδj x ± (2) In this equation Wj (t) is the weight from hidden node i (or, in the case of the first hidden layer, from an input node) to node j at time t; XJ is either the output of node i (or, in the case of the first hidden layer, is an input signal); η is a gain term introduced to maintain stability in the feedback procedure used to minimize the mean square errors between the actual output(s) of the perceptron and its desired output(s); and δj is a derivative of error. The general definition of δj is the change in error energy from output node j of a neural net layer with a change in the weighted summation of the input signals used to supply that output node j. Lippman presumes that a particular sigmoid logistic non- linearity is used. Presuming the non-linearity of processor response is to be defined not as restrictively as Lippmann does, then δ j can be more particularly defined as in equation (2), following, if node j is an output node, or as in equation (3), following, if node j is an internal hidden node. δj - yj « (d - yj > (3) β j - Yj ' ∑ δ k Wj , k ^ In equation (3) dj and yj are the desired and actual values of output response from the output layer and yj' is differential response of yj to the non-linearity in the output layer - i.e., the slope of the transfer function of that non-linearity. In equation (4) k is over all nodes in the neural net layer succeeding the hidden node j under consideration and Wj,k is the weight between node j and each such node k. The term yj' is defined in the same way as in equation (3). The general definition of the yj' term appearing in equations (3) and (4), rather than that general term being replaced by the specific value of yj' associated with a sigmoid logistic non- linearity, is the primary difference between the training algorithm as described here and as described by Lippmann. Also, Lippmann defines δj in opposite polarity from equations (1), (3) and (4) above. During training of the neural net, prescribed patterns of input signals are sequentially repetitively applied, for which patterns of input signals there are corresponding prescribed patterns of output signals known. The pattern of output signals generated by the neural net, responsive to each prescribed pattern of input signals, is compared to the prescribed pattern of output signals to develop error signals, which are used to adjust the weights per equation (2) as the pattern of input signals is repeated several times, or until the error signals are detected as being negligibly valued. Then training is done with the next set of patterns in the sequence. During extensive training the sequence of patterns may be recycled. SUMMARY OF THE INVENTION The invention is useful in weighted summation networks which use capacitors to perform weighted summation in accordance with Coulomb's Law, as employed in neural nets, for example. The invention concerns how a plurality, P greater than three in number, of capacitive elements identified by respective consecutive ordinal numbers zeroeth through (P-1)th can be separated into two groups of parallelly connected capacitive elements to provide two capacitances, the sum of which two capacitances is constant, and the difference of which two capacitances is a multiple of the value of the capacitance of the first capacitive element, which multiple may be either positive or negative in sense. The zeroeth and first capacitive elements each have the same capacitance and are smaller than each of the other capacitive elements. The second through (P- 1)th of the other capacitive elements have respective capacitances scaled in binary integer ratio with the first capacitive element. The invention is particularly useful in weighted summation networks which use capacitors where the weights afforded by the capacitors are to be changed in accordance with digital programming code words, in order to implement training or learning procedures. BRIEF DESCRIPTION OF THE DRAWING FIGURE 1 is a schematic diagram of a neural net layer as described by W. E. Engeler in U. S. patent application serial No. 366,838 entitled "NEURAL NET USING CAPACITIVE STRUCTURES CONNECTING INPUT LINES AND DIFFERENTIALLY SENSED OUTPUT LINE PAIRS", which neural net layer uses capacitors to perform weighted summations of synapse signals to be subsequently sensed and non- linearly amplified to generate axon response signals. FIGURES 2A and 2B together form a FIGURE 2 that is a schematic diagram of a modification of the FIGURE 1 neural net that can be made manifold times to provide in accordance with a further aspect of the invention, for the programmable weighting of the capacitances used in performing weighted summation of synapse signals. FIGURE 3 is a schematic diagram of a neural net layer as described by W. E. Engeler in U. S. patent application serial No. 366,839 entitled "NEURAL NET USING CAPACITIVE STRUCTURES CONNECTING OUTPUT LINES AND DIFFERENTIALLY DRIVEN INPUT LINE PAIRS", which neural net layer uses capacitors to perform weighted summations of synapse signals to be subsequently sensed and non- linearly amplified to generate axon response signals. FIGURES 4A and 4B together form a FIGURE 4 that is a schematic diagram of a modification of the FIGURE 3 neural net that can be made manifold times to provide in accordance with a further aspect of the invention, for the programmable weighting of the capacitances used in performing weighted summation of synapse signals. FIGURE 5 is a schematic diagram illustrating one way of pulsing the non-linear output driver amplifiers, as may be used in a FIGURE 1 neural net layer modified manifoldly per FIGURE 2, or as may be used in a FIGURE 3 neural net layer modified manifoldly per FIGURE 4. FIGURES 6A, 6B and 6C together form a FIGURE 6 that is a schematic diagram of another neural net described by W. E. Engeler in U. S. patent application serial No. 366,838, which other neural net uses pairs of input lines driven by balanced input signals for connection to the pairs of differentially sensed output lines by weighting capacitors connected in quad configurations and operated as full bridges. FIGURE 7 is a schematic diagram of training apparatus described by W. E. Engeler in U. S. patent applications serial Nos. 366,838 and 366,839, which training apparatus can be used with the FIGURE 1 neural net layer manifoldly modified per FIGURE 2, with the FIGURE 3 neural net layer manifoldly modified per FIGURE 5, or with the FIGURE 1 neural net layer manifoldly modified per FIGURE 6. TUTE SHEET FIGURE 8 is a schematic diagram of a system described by W. E. Engeler in U. S. patent applications serial Nos. 366,838 and 366, 839, which system has a plurality of neural net layers each constructed in accordance with FIGURE 1 modified manifold times per FIGURE 2, with FIGURE 3 modified manifold times per FIGURE 5, or with FIGURE 1 modified manifold times per FIGURE 6. FIGURE 9 is a conceptual schematic diagram of a pair of capacitors having capacitances that sum to a constant value and that are programmable responsive to digital words encoding weighting factor in two's complement arithmetic, which pair of capacitors embodies the invention. FIGURE 10 is a table indicating the disposition of capacitive elements as components of the FIGURE 9 pair of capacitors as determined by the digital words encoding weighting factor in two's complement arithmetic. FIGURE 11 is a conceptual schematic diagram of a pair of capacitors having capacitances that sum to a constant value and that are programmable responsive to digital words encoding weighting factor in one's complement arithmetic, which pair of capacitors embodies the invention. FIGURE 12 is a table indicating the disposition of capacitive elements as components of the FIGURE 11 pair of capacitors as determined by the digital words encoding weighting factor in one's complement arithmetic. FIGURE 13 is a schematic diagram showing in greater detail the electrical connections of one of the switched capacitive elements used in the FIGURE 9 or FIGURE 11 pair of capacitors. FIGURE 14 is a view of a portion of the top surface of a monolithic integrated circuit in which reposes two of the switched capacitive elements and the single-bit storage elements for storing their respective control bits, which FIGURE 14 has been labelled to indicate the location of circuit elements. This view can be analyzed in accordance with a normal procedure of designers of monolithic integrated circuits using stacked transparencies of different colors reproducing the masks of FIGURES 15, 16, 17, 18, 19, 20, 21 , 22 and 23, respectively, all aligned by superposing their corresponding corner alignment keys. The masks of FIGURES 15, 16, 17, 18, 19, 20, 21 , 22 and 23 are those used for constructing, in accordance with conventional complementary metal oxide semiconductor (CMOS) processing, each pair of capacitors, that are adjustable in complementary way to a weighting word and for the word storage element to store that weighting word. FIGURE 15 is the mask defining the extent of the n-well region in a p-type silicon die, which n-well region underlies portions of a FIGURE 14 double switched capacitor structure. FIGURE 16 is the mask defining the active area regions of both the n- and p-channel devices in a FIGURE 14 double switched capacitor structure. These active area regions, covered by relatively thin gate oxide, are within rectangular boxes and include source, drain and channel regions. The region that surrounds each of these active area regions is a relatively thick field oxide area. FIGURE 17 is the mask defining the shape of the polycrystalline silicon conductors used in a FIGURE 14 switched capacitor structure as gate electrodes in both the n- and p-channel field-effect transistors and for short-run conductors. FIGURE 18 is the mask defining the extent of the p+ implant used for establishing the source and drain regions of the p- channel field-effect transistors and for contacting to the p-type silicon substrate in a FIGURE 14 double switched capacitor structure. FIGURE 19 is the mask defining the extent of the n+ contacts to n-well and of the n+ source and drain regions of the n- channel field-effect transistors in a FIGURE 14 double switched capacitor structure. FIGURE 20 is the mask locating, in a FIGURE 14 double switched capacitor structure, the position of contact openings between the first metallization layer and all of the following: the polycrystalline silicon conductors defined by the FIGURE 17 mask, the p+ source and drain regions of the p-channel field-effect transistors, and the n+ source and drain regions of the n-chanπel field-effect transistors. E SHEET FIGURE 21 is the mask defining the pattern of the first metallization layer in a FIGURE 14 double switched capacitor structure. FIGURE 22 is the mask locating the position of contact openings between the first and second metallization layers in a FIGURE 14 double switched capacitor structure. FIGURE 23 is the mask defining the pattern of the second metallization layer in a FIGURE 14 double switched capacitor structure. FIGURE 24 is a conceptual schematic diagram of a quad connection of four capacitors, the capacitances of which are programmable responsive to digital words encoding weighting factor in two's complement arithmetic, as constructed in accordance with the invention. FIGURE 25 is a conceptual schematic diagram of a quad connection of four capacitors, the capacitances of which are programmable responsive to digital words encoding weighting factor in one's complement arithmetic, as constructed in accordance with the invention. Each of FIGURES 26, 27 and 28 is a schematic diagram of a neural net layer wherein in accordance with the invention weighting with higher bit resolution is provided without having to have as wide a range of weighting capacitor sizes. Each of FIGURES 29 and 30 is a conceptual schematic diagram of capacitor quads constructed in accordance with the invention to implement weighting with higher bit resolution in a neural net layer per FIGURE 26, 27 or 28. DETAILED DESCRIPTION FIGURE 1 shows a neural net comprising a plurality, N in number, of non-linear amplifiers ODi , OD2, ...OD(N-1), ODN. Each of a plurality, M in number, of input voltage signals xι , X2, ...X(M-1) > X M supplied as "synapse" signals is weighted to provide respective input voltages for the non-linear voltage amplifiers OD , OD2, ...OD(N-1 ), ODN, which generate respective "axon" responses yi , y2, ...y(N-i)» yN- STITUTE SHEET This weighting is, as will be described in detail further on in this specification, done using capacitive structures in accordance with the invention. M is a positive plural integer indicating the number of input synapse signals to the FIGURE 1 neural net, and N is a positive plural integer indicating the number of output axon signals the FIGURE 1 net can generate. To reduce the written material required to describe operation of the FIGURE 1 neural net, operations using replicated elements will be described in general terms; using a subscript i ranging over all values one through M for describing operations and apparatuses as they relate to the (column) input signals xι , X2, •■•x(M-l ). *M." and using a subscript j ranging over all values one through N for describing operations and apparatus as they relate to the (row) output signals yi , y2, ...y(N-i), YN- That is, i and j are the column and row numbers used to describe particular portions of the neural net. Input voltage signal xj is applied to the input port of an input driver amplifier IDj that is a voltage amplifier which in turn applies its voltage response to an input line ILj. Respective output lines OLj and OL(J+N) connect to the non-inverting input port of output driver amplifier ODj and to its inverting input port. The non¬ linear output driver amplifier ODj is shown in FIGURE 1 as simply being a differential-input non-linear voltage amplifier with the quiescent direct potential applied to its (+) and (-) input signal terminals via output lines OLj and OL(J+N) being adjusted by clamping to a desired bias voltage at selected times using a respective direct-current restorer circuit DCRj. (The direct-current restorer circuit DCRj is shown at the left of FIGURE 1 for drafting reasons, but is normally associated with the input port of the output driver amplifier ODj.) Output driver amplifier ODj generates at its output port a non-linear voltage response to the cumulative difference in charge on that respective pair of output lines OLj and OL(j+N). A respective capacitor Cj,j connects each of the input lines ILj to each of the output lines OLj, and a respective capacitor Cj, ( j + N) connects each of the input lines ILj to each of the output lines OL(J+N)- Since at its output terminal the output driver amplifier ODj responds without inversion to XJ input signal voltage applied to its non-inverting (+) input terminal via capacitor C and responds with inversion to XJ input signal voltage applied to its inverting (-) input terminal via capacitor CJ.(J + N), respectively, the electrically equivalent circuit is XJ signal voltage being applied to a single output line OLj by a capacitor having a capacitance that equals the capacitance of Cj minus the capacitance of CJ,(J+N)- This technique of single-ended output signal drive to paired output lines that are differentially sensed avoids the need for switched- capacitance techniques in order to obtain inhibitory (or negative) weights as well as excitory (or positive) weights. Thus, this technique facilitates operating the neural net with analog signals that are continuous over sustained periods of time, if so desired. FIGURE 1 shows each of the input lines ILj as being provided with a respective load capacitor CLj to cause that capacitive loading upon the output port of the input driver amplifier IDj to be substantially the same as that upon each output port of the other input driver amplifiers. This is desirable for avoiding unwanted differential delay in responses to the input signals x.. Substantially equal capacitive loading can be achieved by making the capacitance of each of the input line loading capacitors, CLi through CL , very large compared to the total capacitance of the capacitors Cj. j connecting thereto. Preferably, however, this result is achieved by making the capacitance of each of the input line loading capacitors complement the combined value of the other capacitances connecting thereto. This procedure reduces the amount of line loading capacitance required. Where the voltages appearing on the output lines OLj and OL(J+N) are sensed directly by the non-linear output driver amplifiers ODi , ...ODN, as shown in FIGURE 1 , this procedure makes the voltage division ratio for each input voltage XJ , ... x m independent of the voltage division ratios for the other input voltages. FIGURE 1 also shows each of the output lines OLj being loaded with a respective load capacitor CL(M + j) and each of the output lines OL ( N + j) being loaded with a respective load capacitor CL(M + N + j)- This is done so that the total capacitance on each output line remains substantially the same as on each of the other output lines. This can be done by choosing CL( + j) to be much larger than other capacitances to output line OLj, and by choosing CL(M + N+J) to be much larger than other capacitances to output line OLN+J). Alternatively, this can be done by choosing CL(M + j) and CL( + N + J) to complement the combined value of the other capacitances connecting the same output line. The input voltage to output driver amplifier OD j will (to good approximation) have the following value, VJ, in accordance with Coulomb's Law. j - (C j ) £ (Ci, j - Ci, ( j+N) ) Xi i-i (5) The generation of voltage VJ can be viewed as the superposition of a plurality of capacitive divisions between, on the one hand, the effective capacitance (C(j.j) - CJ.(J+N)) each input voltage has to output line OL j and, on the other hand, the total capacitance C j of the output line to its surroundings. That is, Cj is the total capacitance on output line OLj or the total capacitance on output line OL(N + J), which capacitances should be equal to each other and fixed in value. Each non-linear output driver amplifier ODj in the FIGURE 1 neural net layer can be implemented using linear voltage amplifier circuitry followed by non-linear voltage amplifier circuitry. Each output driver amplifier can comprise a long-tailed pair connection of transistors having a current mirror amplifier load for converting their output signal voltage to single-ended form for application to an ensuing non-linear voltage amplifier . The long-tailed pair connection of transistors is a differential amplifier connection where their source electrodes have a differential-mode connection to each other and to a constant-current generator. An ensuing non¬ linear voltage amplifier can, as described in patent applications serial Nos, 366,838 and 366,839, comprise a cascade connection of two source-follower transistors, one an n-channel MOSFET and the other a p-channel MOSFET, each provided with a respective suitably- valued constant-current generator source load. Non-linearity of response in such a cascade connection comes about because (I) source-follower action of the n-channel MOSFET for positive-going excursions of its gate electrode potential becomes limited as its source potential approaches its drain potential VHI and (2) source- follower action of the p-channel MOSFET for negative-going excursions of its gate electrode potential becomes limited as its source potential approaches its drain potential V__o- At the source electrode of the output source-follower of the cascade connection, there is a sigmoidai response to a linear ramp potential applied to the gate electrode of the input source-follower of the cascade connection. Alternatively, the difference in charge appearing on the output lines OLj and OLQ+N) can be sensed by fully differential charge-sensing amplifiers preceding the non-linear voltage amplifiers in the output driver amplifiers. In such case the output signals from the charge-sensing amplifiers will be balanced with reference to a reference VBIAS potential. This alternative will be described presently in connection with FIGURE 2. Consider now how neuron model behavior is exhibited by input driver amplifier IDj , capacitors Cjj and CJ,(J+N) > and non¬ linear output driver amplifier ODj for particular respective values of i and j. If the capacitance of capacitor Cj,j is larger than the capacitance of capacitor CJ,(J+N) for these particular values of i and j, then the output voltage yj for that j will exhibit "excitory" response to the input voltage XJ. If the capacitances of Cjj and Cj,(j + N) are equal for these i and j values, then the output voltage yj for that j should exhibit no response to the input voltage yj. If the capacitance of capacitor Cj is smaller than the capacitance of capacitor Cj(j + N) f r those i and j values, then the output voltage yj for that j will exhibit "inhibitory" response to the input voltage XJ. In some neural nets using capacitors for weighting synapse signals, the capacitors Cj and CJ,(J+N) for all i and j may be fixed-value capacitors, so there is never any alteration in the weighting of input voltages XJ where i-1 ,...M. However, such neural nets lack the capacity to adapt to changing criteria for neural responses - which adaptation is necessary, for example, in a neural network that is to be connected for self-learning. It is desirable in certain applications, then, to provide for altering the capacitances of each pair of capacitors Cjj and CJ,(J+N) associated with a respective pair of values of i and j. This alteration is to be carried out in a complementary way, so the sum of the capacitances of Cjj and of CJ,(J + N) remains equal to Ck- In accordance with the invention, each of a set of component capacitors with capacitances related in accordance with powers of two is selected to be a component of one or the other of the pair of capacitors Cj j and Cj,(j + N). the selecting being done by field effect transistors operated as transmission gates. FIGURE 2, comprising component FIGURES 2A and 2B, shows a representative modification that can be made to the FIGURE 1 neural net near each set of intersections of output lines OLj and OL(J+N) with an input line ILj from which they receive with differential weighting a synapse input signal Xj. Such modifications together make the neural net capable of being trained. Each capacitor pair Cjj and CJ,(J+N) of the FIGURE 1 neural net is to be provided by a pair of digital capacitors DCjj and DC . ,(j + N)- The capacitances of DCjj and DCJ.(J + N) are controlled in complementary ways by a weighting factor and its one's complement as described by a digital word stored in a respective word-storage element WSEjj of an array of such elements located interstitial ly among the rows of digital capacitors and connected to form a memory. This memory may, for example, be a random access memory (RAM) with each word-storage element WSEjj being selectively addressable by row and column address lines controlled by address decoders. Or, by way of further example, this memory can be a plurality of static shift registers, one for each column j. Each static shift register will then have a respective stage WSEjj for storing the word that controls the capacitances of each pair of digital capacitors DCjj and DCJ,(J+N)- The word stored in word storage element WSEjj may also control the capacitances of a further pair of digital capacitors DC(j + )j and DC(j + M),(j+N). respectively. The capacitors DC(J+M),J and DC(J+M),(J + N) connect between "ac ground" and output lines OLj and OL(J+N), respectively, and form parts of the loading capacitors CL(M + j). The capacitances of DC(j+2Mj) and DCjj are similar to each other and changes in their respective values track each other. The capacitances of DC(J+ ),(J+N) and DCJ,(J+N) are similar to each other and changes in their respective values track each other. The four digital capacitors DCjj, DCJ. +N), DC(J + M),J and DC(jk + M),(j + N) are connected in a quad or bridge configuration having input terminals connecting from the input line ILj and from a-c ground respectively and having output terminals connecting to output lines OLj and OL(J+N) respectively. This configuration facilitates making computations associated with back-propagation programming by helping make the capacitance network bilateral insofar as voltage gain is concerned. Alternatively, where the computations for back- propagation programming are done by computers that do not involve the neural net in the computation procedures, the neural net need not include the digital capacitors DC(j + M),j and DC(j + M),(j + N)- When the FIGURE 2 neural net is being operated normally, following programming, the φp signal applied to a mode control line MCL is a logic ZERO. This ZERO on mode control line MCL conditions each output line multiplexer OLMj of an N-numbered plurality thereof to select the output line OLj to the inverting input terminal of a respective associated fully differential amplifier DA j . This ZERO on mode control line MCL also conditions each output line multiplexer OLM (J+N) to select the output line OL(J + N) to the non-inverting input terminal of the respective associated fully differential amplifier DAj differential amplifier DAj, which is included in a respective charge-sensing amplifier QSj that performs a charge-sensing operation for output line OL j . A fully differential amplifier constructed of MOS field-effect transistors, as may serve for any one of the fully differential amplifiers DAj for j - 1, 2, ...N, is described on pages 255-257 of the book Analog MOS Integrated Circuits for Signal Processing by R. Gregorian and G.C. Temes, copyright 1986, published by John Wiley & Sons, Inc., of New York, Chichester, Brisbane, Toronto and Singapore. In furtherance of this charge-sensing operation, a transmission gate TGj responds to the absence of a reset pulse QR to connect an integrating capacitor Clj between the (+) output and (-) 1 6 input terminals of amplifier DAJ; and a transmission gate TG +SN) responds to the absence of the reset pulse ΦR to connect an integrating capacitor CI(J+N) between the (-) output and (+) input terminals of amplifier DAj. With integrating capacitors Clj and Cl(j + N) so connected, amplifier DAj functions as a differential charge amplifier. When <j> p signal on mode control line MCL is a ZERO, the input signal Xj induces a total differential change in charge on the capacitors DCjj and DCJ,(J+N) proportional to the difference in their respective capacitances. The resulting displacement current flows needed to keep the input terminals of differential amplifier DAj substantially equal in potential requires that there be corresponding displacement current flow from the integrating capacitor Clj and CI(J + N) differentially charging those charging capacitors to place thereacross a differential voltage VJ defined as follows. _1 M j = (Clj + CI (j+N) ) ∑ (C ± j - C (i+M) ) xi i=l (6) The half Vj signal from the non-inverting (+) output terminal of amplifier DAj is supplied to a non-linear voltage amplifier circuit NLj which can be the non-linear voltage amplifier circuit using a cascade connection of p-channel and n-channel source-follower field effect transistors as previously described. The non-linear voltage amplifier circuit NLj responds to generate the axon output response y j . It is presumed that this non-linear voltage amplifier NLj supplies y j at a relatively low source impedance as compared to the input impedance offered by the circuit yj is to be suppled to - e.g. on input line in a succeeding neural net layer. If this is so there is no need in a succeeding neural net layer to interpose an input driver amplifier IDj as shown in FIGURE 1. This facilitates interconnections between successive neural net layers being bilateral. An output line multiplexer OLMj responds to the φp signal appearing on the mode control line MCL being ZERO to apply yj to an input line of a succeeding neural net layer if the elements shown in are in a hidden layer. If the elements shown in FIGURE 2 are in the output neural net layer, output line multiplexer OLM j responds to the φp signal on the mode control line being ZERO to apply yj to an output terminal for the neural net. From time to time, the normal operation of the neural net is interrupted; and, to implement dc-restoration a reset pulse ΦR is supplied to the charge sensing amplifier QSj. Responsive to Φ ,the logic complement of the reset pulse ΦR, going low when Φ goes high, transmission gates TGj and TG +SN) are no longer rendered conductive to connect the integrating capacitors Cl j and CIQ+N) from the output terminals of differential amplifier DAj. Instead, transmission gates TG(j + N) and TG(j + 4N) respond to ΦR going high to connect to VBIAS the plates of capacitor Clj and CI(J+N) normally connected from those output terminals, VBIAS being the 2.5 volt intermediate potential between the Vss β 0 volt and VQD - 5 volt operating voltages of differential amplifier DA j . Other transmission gates TG(j + 2N) and TG(j + 3N) respond to ΦR going high to apply direct-coupled degenerative feedback from the output terminal of differential amplifier DAj to its input terminals, to bring the voltage at the output terminals to that supplied to its inverting input terminal from output lines OLj and OL(J+N). During the dc- restoration all Xj are "zero-valued". So the charges on integrating capacitor Clj and CI(J+N) are adjusted to compensate for any differential direct voltage error occurring in the circuitry up to the output terminals of differential amplifier DAj. Dc-restoration is done concurrently for all differential amplifiers DAj (i.e., for values of j ranging from one to N). During training, the φp signal applied to mode control line MCL is a logic ONE, which causes the output line multiplexer OLMj to disconnect the output lines OLj and OL(J+N) from the (+) and (-) input terminals of differential amplifier DAj and to connect the output lines OLj and OL(J+N) to receive +δj and -δj error terms. These +δj and -δj error terms are generated as the balanced product output signal of a analog multiplier AMj, responsive to a signal Δj and to a signal y'j which is the change in output voltage yj of non- linear amplifier NLj for unit change in the voltage on output line OLj. The term Δ j for the output neural net layer is an error signal that is the difference between yj actual value and its desired value d j . The term Δj for a hidden neural net layer is also an error signal, which is of a nature that will be explained in detail further on in this specification. Differentiator DF j generates the signal y'j, which is a derivative indicative of the slope of yj change in voltage on output line OLj, superposed on VBIAS- TO determine the y'j derivative, a pulse doublet comprising a small positive-going pulse immediately followed by a similar-amplitude negative-going pulse is introduced at the inverting input terminal of differential amplifier DAj (or equivalently, the opposite-polarity doublet pulse is introduced at the non-inverting input terminal of differential amplifier DA j ) to first lower yj slightly below normal value and then raise it slightly above normal value. This transition of yj from slightly below normal value to slightly above normal value is applied via a differentiating capacitor CDj to differentiator DFj. Differentiator DFj includes a charge sensing amplifier including a differential amplifier DA(J+N) and an integrating capacitor CI(J+N)- During the time yj that is slightly below normal value, a reset pulse φs is applied to transmission gates TG(j + 4N) and TG(j + 5N) to render them conductive. This is done to drain charge from integrating capacitor Cl( + N). except for that charge needed to compensate for DA(J+N) input offset voltage error. The reset pulse φs ends, rendering transmission gates TGB(j + 4N) and TG(J + 5N) no longer conductive, and the complementary signal Φs goes high to render a transmission gate TG(j + 3N) conductive for connecting integrating capacitor CI(J+N) between the output and inverting-input terminals of differential amplifier DA(J+N). With the charge-sensing amplifier comprising elements DA(J+N) and CI(J+N) reset, the small downward pulsing of yj from normal value is discontinued and the small upward pulsing of yj from normal value occurs. The transition between the two abnormal conditions of yj is applied to the charge-sensing amplifier by electrostatic induction via differentiating capacitor CDj. Differential amplifier DA(J+N) output voltage changes by an amount y'j from the VBIAS value it assumed during reset. The use of the transition between the two pulses of the doublet, rather than the edge of a singlet pulse, to determine the derivative y'j makes the derivative-taking process treat more similarly those excitory and inhibiting responses of the same amplitude. The doublet pulse introduces no direct potential offset error into the neural net layer. Responsive to a pulse φj, the value y'j + VBIAS from differentiator DFj is sampled and held by row sample and hold circuit RSHj for application to an analog multiplier AMj as an input signal. This sample and hold procedure allows yj to return to its normal value, which is useful in the output layer to facilitate providing yj for calculating (yj - dj). The sample and hold circuit RSHj may simply comprise an L-section with a series-arm transmission-gat sample switch and a shunt-leg hold capacitor, for example. The . ilog multiplier AMj accepts a first push-pull input signal between nput terminals ΪNI and IN1 , accepts a second push- pull input signal between terminals ΪN2 and IN2, and supplies product output signal in balanced form at its output terminals POUT and POUT . The difference between y'j + VBIAS and VBIAS voltages is applied as a differential input signal to the analog multiplier AMj, which exhibits common-mode rejection for the VBIAS term. In U. S. patent applications serial numbers 366,838 and 366, 839 respectively entitled "NEURAL NET USING CAPACITIVE STRUCTURES CONNECTING INPUT LINES AND DIFFERENTIALLY SENSED OUTPUT LINE PAIRS" and "NEURAL NET USING CAPACITIVE STRUCTURES CONNECTING OUTPUT LINES AND DIFFERENTIALLY DRIVEN INPUT LINE PAIRS", the four-quadrant analog multiplier AMj is described as being a push-pull-output analog multiplier formed by modifying a single-ended-output analog multiplier described by K. Bultt and H. Wallinga in their paper "A CMOS Four-quadrant Analog Multiplier" appearing on pages 430-435 of the IEEE JOURNAL OF SOLID STATE CIRCUITS. Vol. SC-21, No. 3, June 1986, incorporated herein by reference. During training, the ^P signal applied to mode control line MCL is a logic ONE, as previously noted. When the FIGURE 2 elements SUBSTITUTE SHEET are in the output layer, the ONE on mode control line MCL conditions an output multiplexer OMj to discontinue the application of yj signal from non-linear amplifier NLj to an output terminal. Instead, the output multiplexer OMj connects the output terminal to a charge- sensing amplifier QSj. Charge sensing amplifier QSj includes a differential amplifier DA(j + 2N) and an integrating capacitor CI(j + 2N) and is periodically reset responsive to a reset pulse φu- Reset pulse φu can occur simultaneously with reset pulse φs, for example. Output signal Δj from charge-sensing amplifier QSj is not used in the output layer, however. Analog multiplier AMj does not use Δj + VBIAS and VBIAS as a differential input signal in the output layer, (y j - d j ) being used instead. When the FIGURE 2 elements are in a hidden neural net layer, φp signal on the mode control line MCL being a ONE conditions output multiplexer OMj to discontinue the application of yj signal from non-linear amplifier NL j to the input line IL j of the next neural net layer. Instead, output multiplexer OMj connects the input line IL j to a charge-sensing amplifier QS j . Charge-sensing amplifier QSj senses change in the charge on input line ILj during training to develop a Δj error signal superposed on VBIAS direct potential. The difference between Δj+ VBIAS and VBIAS voltages is used as a differential input signal to analog multiplier AMj, which multiplier exhibits common-mode rejection for the VBIAS term. Charge-sensing amplifier QSj employs a differential- input amplifier DA(j + 2N) and an integrating capacitor CI(j + 2N). Transmission gates TG(J+9N), TG +I ON) and TG(J + H N) cooperate to provide occasional resetting of charge conditions on the integrating capacitor CI J+ 2N responsive to the reset pulse Φu- FIGURE 3 shows a neural net in which the input driver amplifier IDj applies, in response to input voltage signal XJ , not only an non-inverted voltage response from its (+) output port to an input line ILj, but also an inverted voltage response from its (-) output port to an input line IL(i + )- A respective degenerative feedback connection from its (+) output terminal to its (-) input terminal conditions each of the input driver amplifiers ID; in the FIGURE 3 neural net to provide XJ voltage-follower response at its (+) output terminal to x; signal applied to its (+) input terminal and to provide inverted, -XJ response at its (-) output terminal. A respective single output line OLj connects to the input port of output driver amplifier ODj .which generates at its output port a non-linear voltage response to the cumulative charge on that respective output line OLj. The non-linear output driver amplifier ODj is shown in FIGURE 3 as being just a non-linear voltage amplifier with the quiescent direct potential applied to its input signal terminal via output line OLj being adjusted by clamping to a desired bias voltage at selected times using a respective direct-current restorer circuit DCRj. A respective capacitor Cjj connects each of the input lines ILj to each of the output lines OLj, and a respective capacitor C(j + M),j connects to each of the output lines OLj the one of the input lines IL(j + ) paired with that ILj. Since the paired ILj and IL(J+M) input lines are driven with XJ and -XJ signal voltages respectively, the electrically equivalent circuit is XJ signal voltage being applied to output line OLj by a capacitor having a capacitance that equals the capacitance of Cjj minus the capacitance of C(j + M),j- This balanced input signal drive to paired input lines technique avoids the need for switched-capacitance techniques in order to obtain inhibitory as well as excitory weights, and thus facilitates operating the neural net with analog signals that are continuous over sustained periods of time, if so desired. FIGURE 3 shows each of the input lines ILj or IL(J+M) as being provided with a respective load capacitor Clj or CL(J+M) to cause that capacitive loading upon each of the output terminals of the input driver amplifier IDj to be substantially the same as that upon each output port of the other input driver amplifiers. This is desirable for avoiding unwanted differential delay in responses to the input signals XJ. Substantially equal capacitive loading can be achieved by making the capacitance of each of the input line loading capacitors CLi - CL2 very large compared to the total capacitance of the capacitors Cjj or C(J+M),J connecting thereto. Preferably, however, this result is achieved by making the capacitance of each of the input line loading capacitors complement the combined value of the other capacitances connecting thereto. This procedure reduces the amount of line loading capacitance required. Where the voltage appearing on the output lines is sensed directly by the non¬ linear output driver amplifiers ODi , ...ODN, as shown in FIGURE 3, this preferable procedure makes the voltage division ratio for each input voltage XJ , ... XM independent of the voltage division ratios for the other input voltages. Where the charge appearing on the output lines is sensed by charge-sensing amplifiers preceding the non¬ linear output driver amplifiers, as will be described later on in this specification in connection with FIGURE 4, this latter consideration is not as important. FIGURE 3 also shows each of the output lines OLj being loaded with a respective load capacitor CL(2M + j) to cause the total capacitance on that line to remain substantially the same as on each of the other output lines. Again, this can be done either by choosing CL(2 + j) to be much larger than other capacitances to output line OLj, or by choosing CL(2M + j) to complement the combined value of the other capacitances connecting thereto. The input voltage to output driver amplifier ODj will (to good approximation) have the following value, VJ, in accordance with Coulomb's Law. -l M (C j ) ∑ (C^ j - C ( i+M) / j ) x i=l (7) Here Cj is the total capacitance on output line OLj. The generation of voltage VJ can be viewed as the superposition of a plurality of capacitive divisions between, on the one hand, the effective capacitance (C(jj) - C(j + M),j) each input voltage has to output line OLj and, on the other hand, the total capacitance Cj of the output line to its surroundings. Consider now how neuron model behavior is exhibited by input driver amplifier ID; , capacitors Cjj and C(J + M),J , and non¬ linear output driver amplifier ODj for particular respective values of i and j. The voltage responses input driver amplifier IDj applies to input lines ILj and IL(i+M) are the same in amplitude but are of opposing polarity as referred to a common-mode voltage that is designed to be nominally the same as a bias voltage VBIAS midway between the 0-volt Vss and +5-volt VDD supply voltages. If the capacitance of capacitor Cjj is larger than the capacitance of capacitor C(j + M),j for these particular values of i and j, ' then the output voltage yj for that j will exhibit "excitory" response to the input voltage xj. If the capacitances of Cjj and C(j + M)j are equal for these i and j values, then the output voltage yj for that j should exhibit no response to the input voltage yj. If the capacitance of capacitor Cjj is smaller than the capacitance of capacitor C(j + M),j for those i and j values, then the output voltage yj for that j will exhibit "inhibitory" response to the input voltage XJ. In some neural nets constructed in accordance with the invention the capacitors Cjj and C(j + M)j for all i and j may be fixed- value capacitors, so there is never any alteration in the weighting of input voltages XJ where i*1 ,...M. However, such neural nets lack the capacity to adapt to changing criteria for neural responses ~ which adaptation is necessary, for example, in a neural network that is to be connected for self-learning. It is desirable in certain applications, then, to provide for altering the capacitances of each pair of capacitors Cjj and C(J+ ),J associated with a respective pair of values of i and j. This alteration is to be carried out in a complementary way, so the sum of the capacitances of Cjj and of C(j + M),j remains equal to CR. In accordance with the invention, each of a set of component capacitors with capacitances related in accordance with powers of two is selected to be a component of one or the other of the pair of capacitors Cjj and C(j + M),j, the selecting being done by field effect transistors operated as transmission gates. FIGURE 4, comprising component FIGURES 4A and 4B, shows a representative modification that can be made to the FIGURE 3 neural net near each set of intersections of an output line OLj with input lines ILj and IL(J+M) driven by opposite senses of a synapse input signal XJ. Such modifications together make the neural net capable of being trained. Each capacitor pair Cjj and C(J+ )J of the FIGURE 3 neural net is to be provided by a pair of digital capacitors DCjj and DC(j + M),j- The capacitances of DCJ and DC(J+M) are controlled in complementary ways by a digital word, as drawn from a respective word-storage element WSEjj in an array of such elements located interstitially among the rows of digital capacitors and connected to form a memory. This memory may, for example, be a random access memory (RAM) with each word-storage element WSEjj being selectively addressable by row and column address lines controlled by address decoders. Or, by way of further example, this memory can be a plurality of static shift registers, one for each column j. Each static shift register will then have a respective stage WSEjj for storing the word that controls the capacitances of each pair of digital capacitors DCjj and DC(J+M) j. The word stored in word storage element WSEjj may also control the capacitances of a further pair of digital capacitors DCj . (j+N) and DC(J+M),(J+N)» respectively. The capacitors DCJ.Q+N) and DC(j + M),( j+ N) connect between "ac ground" and input lines ILj and IL(j + M), respectively, and form parts of the loading capacitors CLj and CL(j + M). respectively. The capacitances of DC(J+M,(J+N) and DCjj are similar to each other and changes in their respective values track each other. The four digital capacitors DCjj, DC(J+M) , DCj,(j + N) and DC(j + M),(j + N) are connected in a quad or bridge configuration having input terminals to which the input lines ILj and IL(j + M) respectively connect and having output terminals connecting to output line OLj and to ac ground respectively. The capacitances of DCj,(j + N) and DC(j + M)j are similar to each other and changes in their respective values track each other. This configuration facilitates making computations associated with back-propagation programming by helping make the capacitance network bilateral insofar as voltage gain is concerned. Alternatively, where the computations for back-propagation programming are done by computers that do not involve the neural net in the computation procedures, the neural net need not include the digital capacitors DCjj + N and DC(j + M),(j + N)- These digital capacitors DCJ,(J+N) and DC(i + ),(j + N) are not needed either where very large loading capacitors are placed on the output lines OLj, but this alternative undesirably reduces sensitivity of the output driver amplifier ODj. When the FIGURE 4 neural net is being operated normally, following programming, the φp signal applied to a mode control line MCL.is a logic ZERO. This ZERO conditions a respective input line multiplexer ILMj to connect the non-inverting output port at each input driver amplifier ID; to input line ILj. The φp signal on mode control line MCL being a ZERO also conditions a respective input line multiplexer ILM(J + ) to connect the inverting output port of each input driver amplifier ID; to input line IL(J+M)- A ZERO on mode control line MCL also conditions each output line multiplexer OLMj of an n-numbered plurality thereof to select the output line OLj to the inverting input terminal of a respective associated differential-input amplifier DA j , included in a respective charge-sensing amplifier QSj that performs a charge- sensing operation for output line OLj. In furtherance of this charge- sensing operation, a transmission gate TGj responds to the absence of a reset pulse QR to connect an integrating capacitor Clj between the output and inverting-input terminals of differential-input amplifier DAj. Amplifier DAj may be an operational amplifier of the conventional voltage amplifier type or may be an operational transconductance amplifier. With integrating capacitor Cl j so connected, amplifier DA j functions as a charge amplifier. When ^p signal on mode control line MCLis a ZERO, the input signal XJ induces a total change in charge on the capacitors DCjj and DC ( j + M),j proportional to the difference in their respective capacitances. The resulting displacement current flow from the inverting input terminal of differential-input amplifier DAj requires that there be a corresponding displacement current flow from the integrating capacitor Clj charging that capacitor to place thereon a voltage VJ defined as follows. Vj - (Clj) X (C lp j - C (i+M ) , j) i i-i (8) The voltage Vj is supplied to a non-linear voltage amplifier circuit NLj, which non-linear voltage amplifier circuit responds to generate the axon output response yj. From time to time, the normal operation of the neural net is interrupted, and to implement dc-restoration a reset pulse ΦR is supplied to each charge sensing amplifier QSj. Responsive to ΦR the logic complement of the reset pulse ΦR, going low when ΦR goes high, transmission gate TGj is no longer rendered conductive to connect the integrating capacitor Clj from the output terminal of differential amplifier DAj. Instead, a transmission gate TG(J+N) responds to ΦR going high to connect to VBIAS the plate of capacitor C j normally connected from that output terminal, VBIAS being the 2.5 volt intermediate potential between the Vss β 0 volt and VQD ■ 5 volt operating voltages of differential amplifier DA j . Another transmission gate TG(j + 2N) responds to ΦR going high to apply direct-coupled feedback from the output terminal of differential amplifier DAj to its inverting input terminal, to bring the voltage at the output terminal to that supplied to its inverting input terminal from output line OL j . During the dc-restoration all x; are "zero- valued". So the charge on integrating capacitor Clj is adjusted to compensate for any direct voltage error occurring in the circuitry up to the output terminal of differential amplifier DAj. DC-restoration is done concurrently for all differential amplifiers DA j (i.e., for values of j ranging from one to N). During training, the φp signal applied to mode control line MCL is a logic ONE, which causes the output line multiplexer OLMj to disconnect the output line OLj from the inverting input terminal of differential amplifier DA j and to connect the output line OLj to receive a δj error term. This δj error term is generated as the product output signal of a analog multiplier AMj, responsive to a signal Δj and to a signal y'j which is the change in output voltage yj of non-linear amplifier NLj for unit change in the voltage on output line OLj. The term Δj is for the output neural net layer the difference between yj actual value and its desired value d j . The term Δj is for a hidden neural net layer the Δj output of the succeeding neural net layer during the back-propagation procedure. Differentiator DFj generates the signal y'j, which is a derivative indicative of the slope of yj change in voltage on output line OLj, superposed on VBIAS- TO determine the y'j derivative, a pulse doublet comprising a small positive-going pulse immediately followed by a similar-amplitude negative-going pulse is introduced at the inverting input terminal of differential amplifier DA j (or equivalently, the opposite-polarity doublet pulse is introduced at the non-inverting input terminal of differential amplifier DAj) to first lower yj slightly below normal value and then raise it slightly above normal value. This transition of yj from slightly below normal value to slightly above normal value is applied via a differentiating capacitor CDj to differentiator DFj. Differentiator DFj includes a charge sensing amplifier including a differential amplifier DA(j + N) and an integrating capacitor CI(J+N). During the time that yj is slightly below normal value, a reset pulse φs is applied to transmission gates TG(J+4N) and TG(j + 5N) to render them conductive. This is done to drain charge from integrating capacitor CI(J+N), except for that charge needed to compensate for DA(J + N) input offset voltage error. The reset pulse Φs ends, rendering transmission gates TGB(j + 4N) and TG(J+SN) no longer conductive, and the complementary signal Φs goes high to render a transmission gate TG(J + 3 ) conductive for connecting integrating capacitor CI(J + N) between the output and inverting-input terminals of differential amplifier DA(J+N). With the charge sensing amplifier comprising elements DA(J + N) and CI(J+N) reset, the small downward pulsing of yj from normal value is discontinued and the small upward pulsing of yj from normal value occurs. The transition between the two abnormal conditions of yj is applied to the charge sensing amplifier by electrostatic induction via differentiating capacitor CDj. Differential amplifier DA(J+N) output voltage changes by an amount y'j from the VBIAS value it assumed during reset. The use of the transition between the two pulses of the doublet, rather than the edge of a singlet pulse, to determine the derivative y'j makes the derivative-taking process treat more similarly those excitory and inhibiting responses of the same amplitude. The doublet pulse introduces no direct potential offset error into the neural net layer. Responsive to a pulse ΦT, the value y'j + VBIAS from differentiator DF j is sampled and held by (row) sample and hold SUBSTITUTE SHEET circuit RSHj for application to the analog multiplier AMj as an input signal. This sample and hold procedure allows yj to return to its normal value, which is useful in the output layer to facilitate providing yj for calculating (yj - dj). The sample and hold circuit RSHj may simply comprise an L-section with a series-arm transmission-gate sample switch and a shunt-leg hold capacitor, for example. The difference between yj + VBIAS and VBIAS voltages is used as a differential input signal to the analog multiplier AM j , which exhibits common-mode rejection for the VBIAS term. During training, the φp signal applied to the mode control line MCL is a ONE, as previously noted, and this causes the input line multiplexers ILMj and ILM(J+M) to disconnect the input lines ILj and IL(j + M) from the input driver amplifier IDj output terminals and connect them instead to the non-inverting and inverting input terminals of a differential charge-sensing amplifier BDQSi. The voltage δj induces a differential change in charge between input lines ILj and IL(J+M) proportional to δj (Cjj - C(J + M),J), which differential change in charge is sensed using the differential charge sensing amplifier BDQSi. Differential charge-sensing amplifier BDQSi includes a fully differential amplifier provided with integrating capacitors ICj and IC(j + M) in respective degenerative feedback connections from each of its output terminals to each of its input terminals. Resetting of differential charge-sensing amplifier BDQSi is similar to the resetting of a single-ended amplifier such as QS j , except for involving two integrating capacitors ICj and IC(J+M), rather than just the one integrating capacitor Clj. Resetting of differential charge-sensing amplifier BDQSi is done responsive to a pulse Φu. which occurs during the time when mode control line MCL has a ONE thereon conditioning input line multiplexers ILMj and IM(J+ ) to connect input lines ILj and IL(J+M) to the differential charge-sensing amplifier BDQSi. Resetting is normally done shortly after a ZERO to ONE transition appears in the φp signal applied to mode control line MCL and may also be done at other times. This procedure corrects for capacitive unbalances on the input lines ILj and IL(J+ ) during back-propagation computations that follow the resetting procedure. In these computations voltages +Δj + VBIAS and -Δj V BIAS are developed at the (+) and (-) output terminals of the fully differential amplifier included in differential charge-sensing amplifier BDQSi. The voltage +Δj + VBIAS is used by the preceding neural net layer during the back-propagation training procedure, if such a preceding neural net layer exists. The use of single-ended +Δj and +Δj drive is shown in FIGURE 4A, presuming the neural net layers to be integrated within separate monolithic integrated circuits, and presuming the limitation on number of pin-outs is restrictive. Where a plurality of neural net layers are integrated within the same monolithic integrated circuitry, or where maximum pin-out count is not a restrictive design factor, balanced Δ signals may be applied from one neural net layer to the preceding one. So, too, if the non-linear voltage amplifier NLj is of a correct type (for example, a long-tailed pair connection of transistors) yj + VBIAS and -yj + VBIAS balanced output signals may be supplied to the next neural net layer. Indeed, the y'j signals applied to the analog multiplier AMj may be generated in balanced form, replacing differentiator DFj and sample-and-hold circuit SHj with balanced circuitry. FIGURE 5 shows how in either FIGURE 2 or 4 each output line OLj for j - 1 , ...N may be pulsed during calculation of y'j terms. Each output line OL j is connected by a respective capacitor CO j to the output terminal of a pulse generator PG, which generates the doublet pulse. FIGURE 5 shows the doublet pulse applied to the end of each output line OLj remote from the - terminal of the associated differential amplifier DA j in the charge-sensing amplifier QSj sensing the charge on that line. It is also possible to apply the doublet pulses more directly to those - terminals by connecting to these terminals respective ones of the plates of capacitors COj that are remote from the plates connecting to pulse generator PG. Each output line OLj has a respective capacitor COj connected between it and a point of reference potential, and each output line OL(J+N) has a respective capacitor CO(J+N) connected between it and the point of reference potential, which capacitors are not shown in the drawing. The respective capacitances of the capacitors COj and CO(J + N) are all of the same value, so that the back-propagation algorithm is not affected by the presence of these capacitors. Arrangements for adding the doublet pulse to VJ before its application to the non-linear amplifier NL j can be used, rather than using the FIGURE 5 arrangement. FIGURE 6 comprising component FIGURES 6A, 6B and 6C shows further modification that can be made to the FIGURE 4 modification for the FIGURE 3 neural net. This modification, as shown in FIGURE 6A provides for a pair of input lines ILj and IL(J+M) for driving each quad configuration of digital capacitors DCj j , DCj,(j + N), DC(j + M)j and DC(J+M),(J+N) push-pull rather than single- ended. Push-pull, rather than single-ended drive is provided to the differential charge sensing amplifier FDQSj, doubling its output response voltage. Push-pull drive also permits differential charge sensing amplifier FDQSj to be realized with differential-input amplifiers that do not provide for common-mode suppression of their output signals, if one so desires. FIGURE 6A differs from FIGURE 4A in that sign detector CSDj and CSH; do not appear, being relocated to appear in FIGURE 6C as shall be considered further later on. FIGURE 6B differs from FIGURE 4B in that the single- ended charge-sensing amplifier QSj does not appear, being inappropriate for sensing differences in charge appearing on a pair of input lines. Instead, Δj +BBIAS is developed in the following neural net layer and is fed back to analog multiplier AMj via the output multiplexer OMj when the Φ p signal on mode control line MCL is a tc FIGURE 6C shows circuitry that may be used in each neural net layer to provide balanced input signal drive to a pair of input lines ILj and IL(J+ ) during normal operation and to differentially sense the charge on those input lines during back- propagation calculations. A single fully differential amplifier IDj is multiplexed to implement both functions in duplex circuitry DPXj shown in FIGURE 6C. Alternatively, the functions could be implemented with separate apparatus. During normal operation the δp signal appearing on mode control line MCL is a ZERO, conditioning an input multiplexer IMj to apply xj signal to the non-inverting (+) input terminal of differential amplifier IDj and conditioning input line multiplexers ILMj and ILM(j + M) to connect the non-inverting (+) and inverting (-) output terminals of differentia^ amplifier IDj to input lines ILj and IL(J+M) respectively. A signal θp is a ONE during normal operation and appears in the Φu + θp control signal applied to a transmission gate between the non-inverting (+) output terminal of differential amplifier IDj and its inverting (-) input terminal, rendering that transmission gate conductive to provide direct-coupled feedback between those terminals. This d-c feedback conditions differential amplifier ID; to provide XJ and -XJ responses at its (+) and (-) output terminals to the XJ signal applied to its (-) input terminal. Other transmission gates within the duplex circuitry DPXj are conditioned to be non-conductive during normal operation. During back-propagation calculations, the φp signal appearing on mode control line MCL is a ONE, conditioning input multiplexer IMj to apply Δj signal from the non-inverting (+) output terminal of differential amplifier ID; to the preceding neural net layer, if any, and conditioning input line multiplexers ILMj and ILM(j + ) to connect the input lines ILj and IL(J+ ) to respective ones of the non-inverting (+) and inverting (-) input terminals of differential amplifier IDj. Integrating capacitors ICj and IC(J+M) connect from the (+) and (-) output terminals of differential amplifier IDj to its (-) and (+) input terminals when transmission gates in duplex circuitry DPXj that are controlled by Φu • Φp signal receive a ZERO during back-propagation calculations. The charge conditions on integrating capacitors ICj and IC(J+ ) are reset when φu occasionally pulses to ONE during back-propagation calculations. This happens in response to transmission gates in duplexer circuitry DPXj receptive of φu and φu + ^p control signals being rendered conductive responsive to φu being momentarily a ONE, while transmission gates in duplexer circuitry DPXj receptive of Φu control signal being rendered non-conductive. Column sign detector CSD; and column sample and hold circuit CSHj appear in FIGURE 6C. Column sign detector receives output signal from differential amplifier ID; directly as its input signal and can simply be a voltage comparator for the xj and -Xj output signals from the differential amplifier IDj. FIGURE 7 shows apparatuses for completing the back- propagation computations, as may be used with the FIGURE 1 neural net manifoldly modified per FIGURE 2, with the FIGURE 3 neural net manifoldly modified per FIGURE 4, or with the FIGURE 1 neural net manifoldly modified per FIGURE 6. The weights at each word storage element WSEjj in the interstitial memory array IMA are to be adjusted as the i column addresses and j row addresses are scanned row by row, one column at a time. An address scanning generator ASG generates this scan of i and j addresses shown applied to interstitial memory array IMA, assuming it to be a random access memory. The row address j is applied to a row multiplexer RM that selects δj to one input of a multiplier MULT, and the column address i is applied to a column multiplexer CM that selects XJ to another input of the multiplier MULT. Multiplier MULT is of a type providing a digital output responsive to the product of its analog input signals. Multiplier MULT may be a multiplying analog-to-digital converter, or it may comprise an analog multiplier followed by an analog-to-digital converter, or it may comprise an analog-to-digital converter for each of its input signals and a digital multiplier for multiplying together the converted signals. Multiplier MULT generates the product XJ δj as reduced by a scaling factor η, which is the increment or decrement to the weight stored in the currently addressed word storage element WSEjj in the memory array IMA. The former value of weight stored in word storage element WSEjj is read from memory array IMA to a temporary storage element, or latch, TS. This former weight value is supplied as minuend to a digital subtractor SUB, which receives as subtrahend η XJ δj from multiplier MULT. The resulting difference is the updated weight value which is written into word storage element WSEJJ in memory array IMA to replace the former weight value. SUBSTITUTE SHEET FIGURE 8 shows how trained neural net layers Lo, Li and L2 are connected together in a system that can be trained. Lo is the output neural net layer that generates yj output signals; is similar to that described in connection with FIGURES 1 and 2, in connection with FIGURES 3 and 4, or in connection with FIGURE 6 ; and is provided with a back-propagation processor BPPo with elements similar to those shown in FIGURE 2, 4 or 6 for updating the weights stored in the interstitial memory array of Lo. Li is the first hidden neural net layer which generates yj output signals supplied to the output neural net layer as its XJ input signals. These yj output signals are generated by layer Li as its non-linear response to the weighted sum of its xh input signals. This first hidden neural net layer Li is provided with a back-propagation processor BPPi similar to BPPo. L2 is the second hidden neural net layer, which generates yh output signals supplied to the first hidden neural net layer as its xh input signals. These yh output signals are generated by layer L2 as its non-linear response to a weighted summation of its x g input signals. This second hidden layer is provided with a back- propagation processor similar to BPPo and to BPP1. FIGURE 8 presumes that the respective interstitial memory array IMA of each neural net layer Lo, Li , L2 has a combined read/write bus instead of separate read input and write output busses as shown in FIGURE 2, 4 or 6. FIGURE 8 shows the Δ j , Δj and Δh signals being fed back over paths separate from the feed forward paths for yj, yj and yh signals, which separate paths are shown to simplify conceptualization of the neural net by the reader. In actuality, as shown in FIGURE 2, 4 or 6, a single path may be used to transmit yj in the forward direction and Δj in the reverse direction, etc. Back-propagation processor BPPo modifies the weights read from word storage elements in neural net layer Lo interstitial memory array by η Xj δj amounts and writes them back to the word storage elements in a sequence of read-mod if y-write cycles during the training procedure. Back-propagation processor BPP1 modifies the weights read from word storage elements in neural net layer Li interstitial memory array by η Xh δj amounts and writes them back to the word storage elements in a sequence of read-modify-write cycles, during the training procedure. Back-propagation processor BPP2 modifies the weights read and storage elements in neural net layer L2 interstitial memory array by η x g δh amounts and writes them back to the word storage element in a sequence of read- modify-write cycles during the training procedure. The neural nets thusfar described make extensive use of pairs of capacitors wherein the capacitances of each pair of capacitances are determined in response to a digital word, sum to a prescribed constant value, and differ so as to determine the weighting to be applied to a synapse input signal. The foregoing specification also describes the usefulness in a neural net of two pairs of capacitors, wherein the capacitances of each pair of capacitances are determined in response to the same digital word. While the capacitors Cjj and CJ,(J+N) for all i and j could in some instances be fixed-value capacitors, so there would never be any alteration in the weighting of input voltages XJ where i-1,...M, such neural nets lack the capacity to adapt to changing criteria for neural responses. Such adaptation is necessary, for example, in a neural network that is to be connected for self-learning. So it is desirable to provide for altering the capacitances of each pair of capacitors Cjj and C(j + ) j associated in FIGURE 1 or 2 neural net with a respective pair of values of i and j. This alteration is to be carried out in a complementary way, so the sum of the capacitances of Cjj and of C(j + ),j remains equal to Ck- in FIGURE 2 neural net it is also desirable to provide for altering the capacitances of each pair of capacitors CJ,(J+N) and C(J+M),(J+N) in a complementary way, so the sum of their capacitances remains equal to Ck- Similarly, it is desirable to provide for altering the capacitances of each pair of capacitors Cjj and CJ,(J + N) associated in FIGURE 3 or 4 neural net with a respective pair of values of i and j. This alteration is to be carried out in a complementary way, so the sum of the capacitances of Cjj and of CJ,(J+N) remains equal to Ck- In FIGURE 4 neural net it is also desirable to provide for altering the capacitances of each pair of capacitors C(j + M),j and C(J + M),(J+N) SUBSTITUTE SHEET in a complementary way, so the sum of their capacitances of remains equal to C . Altering the capacitances of each pair of capacitors can be implemented along the lines of W. E. Engeler's teachings in regard to "digital" capacitors having capacitances controlled in proportion to binary-numbers used as control signals, as particularly disclosed in connection with FIGURE 11 of his U.S. patent No. 3,890,635 issued 17 June 1975, entitled "VARIABLE CAPACITANCE SEMICONDUCTOR DEVICES" and assigned to General Electric Company. Each pair of capacitors is then two similar ones of these capacitors and their capacitances are controlled by respective control signals, one of which is the one's complement of the other. Another way of realizing the pair of capacitors is to control the inverted surface potentials of a pair of similar-size metal-oxide-semiconductor (MOS) capacitors with respective analog signals developed by digital-to-analog conversion. Such methods of constructing a pair of capacitors use separate capacitive element structures for each capacitor, portions of which capacitive element structures are unused when weighting values are chosen to be low. This undesirably tends to make the capacitive element structures take up nearly twice as much area on an integrated circuit die than is necessary, it is here pointed out. In the method of constructing a pair of capacitors in accordance with the invention, each of a set of component capacitors with capacitances related in accordance with powers of two is selected to be a component of one or the other of the pair of capacitors, the selecting being done by field effect transistors (FETs) operated as transmission gates. This method, which requires a minimum capacitor size providing capacitance half as large as the capacitance associated with the minimum weight, easily provides for a 2 4 : 1 range of capacitive weights without requiring much concern about unbalanced stray capacitances on the balanced input lines or balanced output lines affecting the accuracy of the scaling of the differential capacitance between those lines. With present day design rules a minimum-area capacitor of three square microns is feasible, which makes a capacitor eight times as large have an SUBSTITUTE SHEET area of twenty-four square microns. There is no unused portion of the capacitive element structures in this method. FIGURE 9 is a conceptual schematic diagram of a pair of capacitors with digitally programmed capacitances, designed in accordance with the invention to be operated as a half bridge. The two capacitors are provided by selective connection of component capacitive elements CO, C1, C2, C3 and C4, which have a shared first plate labelled COMMON LINE and have respective second plates POSITIVE LINE and NEGATIVE LINE. As related to FIGURE 1, to FIGURE 2A or to FIGURE 6A, COMMON LINE corresponds to the single-ended input line ILJ; and POSITIVE LINE and NEGATIVE LINE correspond to the balanced output lines OLj and OL(J + N). respectively. As related to FIGURE 3 or to FIGURE 4A, COMMON LINE corresponds to the single- ended output line OLJ; and POSITIVE LINE and NEGATIVE LINE correspond to the balanced input lines ILj and IL(J+M)» respectively. Component capacitive elements CO, C1 , C2, C3 and C4 of the FIGURE 9 capacitor pair have respective capacitances weighted in 2°:2°:2 1 :2 2 :23 ratio; have respective first plates each connected to COMMON LINE; and have respective second plates connected by respective ones of single-pole-double-throw electronic switches SW1, SW2. SW3 and SW4 each to POSITIVE LINE or to NEGATIVE LINE. Single-pole-double-throw electronic switches SW1 , SW2, SW3 and SW4 each provide for connection to POSITIVE LINE or to NEGATIVE LINE, as determined by a respective bit of a weighting word, which word is stored in a respective word storage element WSEjj. The least significant bit of the weighting word is stored in a bit store BS1 and successively more significant bits are stored in bit stores BS2, BS3 and BS4 FIGURE 9 shows bit stores BS1, BS2, BS3 and BS4 as respective square boxes within the rectangular box representing word storage element WSEjj. A tabulation of the various connections that can be made responsive to a four-bit weighting word, as shown in FIGURE 10, suffices to indicate that a continuous set of incremental weights extending over a range with both positive and negative values is made possible by the method of constructing a pair of capacitors in accordance with the invention. The most significant bit of the four- bit weighting word governs connection of capacitive element C4 to POSITIVE LINE or to NEGATIVE LINE by electronic switch SW4 in the reverse sense that the less significant bits of the weighting word govern connections of capacitive elements C1 , C2 and C3 to POSITIVE LINE or to NEGATIVE LINE by electronic switches, or multiplexers SW1 , SW2 and SW3. A feeling of why this is done (which is to accommodate the use of two's complement numbers) and a feeling of why the NEGATIVE LINE is provided with the bias capacitive element CO can be gotten from study of the FIGURE 10 table. The first, second, third and fourth component terms in the NEGATIVE LINE and POSITIVE LINE capacitances (which are to the COMMON LINE) are determined by which of the NEGATIVE LINE and POSITIVE LINE capacitive elements with weights of four, two, one, and one-half are switched to, responsive to the most significant bit, the secondmost significant bit, the thirdmost significant bit and the least significant bit of the four-bit weighting word, respectively, as read from left to right. The fifth component term in the NEGATIVE LINE capacitance is the capacitance of the bias capacitive element corresponding to the bias capacitive element CO of FIGURE 9. This fifth component term is constant in its application and is not switched responsive to the weighting word or any bit thereof. FIGURE 11 shows another pair of capacitors with digitally programmed capacitances, designed in accordance with the invention for half bridge operation, which pair is composed of component capacitive elements C20, C21 , C22, C23 and C24. Capacitive elements C20, C21 , C22, C23 and C24 have respective capacitances weighted in 2°:2°:2 1 :2 2 :2 3 ratio; have respective first plates each connected to COMMON LINE; and have respective second plates connected by respective ones of single-pole-double-throw electronic switches SW20, SW21 , SW22, SW23 and SW24 each to POSITIVE LINE or to NEGATIVE LINE. Single-pole-double-throw electronic switches SW20, SW21 , SW22, SW23 and SW24 each provide for connection to POSITIVE LINE or to NEGATIVE LINE, as determined by a respective bit of a weighting word, which word is stored in a respective word storage element WSEjj'. FIGURE 11 shows bit stores BS14, BS10, BS13, BS12 and BS11 as respective square boxes arranged from left to right within the rectangular box representing word storage element WSEjj'. This arrangement from left to right is in accordance with the bit order of a binary diminished radix number system known as a one's complement system because the sign of the number can be reversed simply by replacing each bit in the number with the bit complement. The one's complement system codes arithmetic zero in two ways. The arrangement of bits shown in FIGURE 11 allows conventional digital adders to be used for signed addition in one's complement arithmetic through the expedient of end-around carry, wherein the carry out from the single-bit adder generating the leftmost bit-place of the plural-bit sum is returned as carry in to the single-bit adder generating the rightmost bit-place of the plural-bit sum. It is this arrangement of bits that will be presumed to be used for one's complement arithmetic in the remainder of this specification. The bits in bit stores BS14, BS10, BS13, BS12 and BS11 control electronic switches SW24, SW20, SW23, SW22 and SW21 , respectively. The leftmost bit of the five-bit weighting word governs connection of capacitive element C24 to POSITIVE LINE or to NEGATIVE LINE by electronic switch SW24 in the reverse sense that the bits of the weighting word to the right govern connections of capacitive elements C20, C23, C22 and C21 to POSITIVE LINE or to NEGATIVE LINE by electronic switches, or multiplexers SW20, SW23, SW22 and SW21. Study of the FIGURE 12 table, which tabulates the capacitances between COMMON LINE and each of the POSITIVE LINE and NEGATIVE LINE connections for the various one's complement numbers used as weighting words in the FIGURE 11 pair of digitally programmable capacitors, helps provide a feeling of how this accommodates the use of one's complement numbers. The first, second, third, fourth and fifth component terms in the NEGATIVE LINE and POSITIVE LINE capacitances (which are to the COMMON LINE) are determined by which of the NEGATIVE LINE and POSITIVE LINE capacitive elements with weights of four, one-half two, one, and one-half are switched to, responsive to the respective bits of the five-bit weighting word as read from left to right. The arithmetic of the one's complement number system for the set of weighting words used in the FIGURE 11 capacitor pair has two zeroes, a "positive " zero of 00000 and a "negative" zero of 11111. When the interstitial memory array IMA has its contents modified by the increment ηxjδj supplied in two's complement form from multiplier MULT as shown in FIGURE 7, the effects on the neural net training of this double zero arithmetic can be suppressed by the subtractor SUB being of the type using end-around carry. Alternatively, the effects of the double zero arithmetic may be left unsuppressed by subtractor SUB to make change between excitory and inhibitory weights less inclined to happen. The FIGURE 11 capacitor pair has the advantage for half bridge operation that the range of excitory weights is as wide as the range of inhibitory weights, which may overweigh in design considerations the disadvantages of the extra bit storage and somewhat more complicated arithmetic used in training. Symmetry in the ranges of available excitory and inhibitory weights is an especially important design consideration where the range of available weights is very restricted — such as just -1 , 0 and +1 in a modification of the FIGURE 11 capacitor pair wherein elements C22, SW22, C23, SW23, C24, SW24, BS12, BS13 and BS14 are dispensed with. Also, though there is extra bit storage in the FIGURE 11 capacitor pair than in the FIGURE 9 capacitor pair, there is greater regularity in the weighting capacitor pair structure with all component MOS capacitors being switched. A MOS capacitor in a monolithic integrated circuit inherently has a substantial stray capacitance to substrate ground from the one of its two plates adjacent to the substrate. To prevent such stray capacitance appearing in unbalanced form, more on one of the POSITIVE LINE and NEGATIVE LINE than on the other, the component capacitive elements CO, C1 , C2, C3 and C4 of FIGURE 9 are poled so as to place their stray capacitances to substrate on the COMMON LINE. Similarly, in FIGURE 11 the component capacitive elements C20, C21 , C22, C23 and C24 are poled so as to place their stray capacitances to substrate on the COMMON LINE. This balancing out of stray capacitance is also done in the capacitor quads of FIGURES 24 and 25. The multiplexers employed in various portions of the circuits described in this specification are customarily constructed of single-pole switch elements, similar to the SW1 , SW2, SW3 and SW4 switch elements of FIGURE 9 and to the SW21 , SW22, SW23 and SW24 switch elements of FIGURE 11. Each of these single-pole switch elements is conventionally a pair of so-called "transmission gate" connections of one or more field effect transistors in CMOS design. A suitable transmission gate is provided by the paralleled channels of a p-channel FET and an n-channel FET having oppositely swinging control voltages applied to their respective gate electrodes to control the selective conduction of those paralleled channels. FIGURE 9 shows the SW4 switch element connected to POSITIVE LINE and NEGATIVE line oppositely from the SW1 , SW2 and SW3 switch elements; and FIGURE 11 shows the SW24 switch element connected to POSITIVE LINE and NEGATIVE line oppositely from the SW1 , SW2 and SW3 switch elements. In an actual integrated circuit layout of the FIGURE 9 capacitor pair, rather than this being done for the various word storage elements, the bit lines can write to the opposite halves of the flip-flops providing bit stores BS4 that the bit lines write to the flip-flops providing bit stores BS1 , BS2 and BS3. Similarly, in an actual integrated circuit layout of the FIGURE 11 capacitor pair, rather than this being done for the various word storage elements, the bit lines can write to the opposite halves of the flip-flops providing bit stores BS24 that the bit lines write to the flip-flops providing bit stores BS21 , BS22 and BS23. FIGURE 13 shows in detail the electrical connections to a corresponding memory element MEX of capacitive element CX that is one of the FIGURE 9 switched capacitive elements C1 , C2, C3 and C4. The memory element MEX is a flip-flop connection of enhancement- mode field effect transistors (FETs) Q1 , Q2, Q3 and 04 and is supplied a relatively positive operating supply voltage VDD and a relatively negative operating supply voltage Vss- One plate of capacitive element CX is shown with fixed connection to COMMON LINE. The switch element SWX, used to connect the other plate of capacitive element CX selectively either to POSITIVE LINE or to NEGATIVE LINE, comprises enhancement-mode FETs Q5, Q6, Q7 and Q8. Enhancement-mode n-channel FETs Q10 and Q11 are selectively rendered conductive by a WRITE command applied to their gate electrodes to impose the bit conditions D and DBAR on the complementary output connections Q and QBAR of memory element MEX to switch element SWX. If D is high (e. g„ VDD) and DBAR is low (e. g., Vss). when the WRITE command is no longer applied to the gate electrodes of Q10 and Q12, DBAR being low conditions Q1 to be conductive and Q2 to be nonconductive to maintain Q high at VDD potential; and D being high conditions Q3 to be nonconductive and Q4 to be conductive to maintain QBAR low at Vss potential. In switch element SWX, Q being high conditions p-channel FET Q5 for non-conduction and n-channel FET Q6 for conduction, and QBAR being low conditions p-channel FET Q7 for conduction and n-channel FET Q8 for non-conduction. The NEGATIVE LINE is connected to capacitive element CX by FETs Q6 and Q7 being conditioned for conduction; and the POSITIVE LINE is disconnected from capacitive element CX by FETs Q5 and Q8 being conditioned for nonconduction. If D is low (e. g., Vss) and DBAR is high (e. g., VDD). when the WRITE command is no longer applied to the gate electrodes of Q10 and Q12, DBAR being high conditions Q1 to be nonconductive and Q2 to be conductive to maintain Q low at Vss potential; and D being low conditions Q3 to be conductive and Q4 to be nonconductive to maintain QBAR high at VDD potential. In switch element SWX, Q being low conditions p-channel FET Q5 for conduction and n-channei FET Q6 for non-conduction, and QBAR being high conditions p-channel FET Q7 for non-conduction and n-channel FET Q8 for conduction. The POSITIVE LINE is connected to capacitive element CX by FETs Q5 and Q8 being conditioned for conduction; and the NEGATIVE LINE is disconnected from capacitive element CX by FETs Q6 and Q7 being conditioned for nonconduction. FIGURES 14-23 depict two basic monolithic structure cells, the one at the left of these figures and the one at the left of these figures being laid out as mirror duplicates of each other. The basic monolithic structure cell can be replicated a small number of times to form a pair of weighting capacitors composed of switched capacitive elements. A network of such pairs of weighting capacitors formed by row and column array of the basic monolithic structure cells, with adjacent column structures mirroring each other, can be used in constructing weighted summation circuitry in accordance with the invention. The smallest switched capacitive eiement(s) can each consist of one basic monolithic structure cell, and the larger switched capacitive elements can each be a combination of a plurality of the basic monolithic structure cells having electrical connections in parallel. The bit storage element need not be duplicated if a single bit storage element is used to control both sets of electronic switches in the combination, however, and modifications of the monolithic circuit layout that eliminate the redundant bit storage element are possible. A quad of weighting capacitors composed of switched capacitive elements can simply comprise two pairs of weighting capacitors, each pair composed of switched capacitive elements as just described, but again there are redundant bit storage elements. Layout modifications are possible that can remove these redundant bit storage elements, so there is the possibility of layout reconfiguration to save area on the monolithic die. Reconfigurations where the first and second switched capacitive elements controlled by the same bit storage element adjoin each other can give rise to T-shaped or L-shaped basic monolithic structure cells. A row of T- shaped or L-shaped basic monolithic structure cells exhibits teeth along one edge of the row. Where there are rows of T-shaped or L- shaped basic monolithic structure cells, a technique to save area on the monolithic die is to flip alternate rows of cells about their row axes so their teeth can be interleaved. Monolithic structure cells as shown in FIGURES 14-23 have been used in implementing a network of pairs of weighting capacitors where two-bit digital words encode weighting factors in one's complement arithmetic. Each weighting capacitor in the pair has an effective weight of 0.5. In neural net layers of the type using capacitive structures connecting input lines and differentially sensed output line pairs, the bits of the digital word stored in the two bit storage elements of a basic monolithic structure cell both being ZEROs or both being ONEs causes the pair of weighting capacitors to be connected to opposite ones of a pair of differentially sensed output lines, so an effective weight of zero is provided by the capacitor pair. The digital word stored in the two bit storage elements being 01 causes both weighting capacitors to be connected to the positive output line, so the capacitor pair provides an effective weight of +1. The digital word being 10 causes, both weighting capacitors to be connected to the negative output line, so the capacitor pair provides an effective weight of -1. In neural net layers of the type using capacitive structures connecting output lines and differentially driven input line pairs, the digital word stored in the two bit storage elements being either 00 and 11 causes the two weighting capacitors to be connected to opposite ones of a pair of differentially driven input lines, so an effective weight of zero is provided by the capacitor pair. The digital word stored in the two bit storage elements being 01 causes both weighting capacitors to be connected to the positive input line, so the capacitor pair provides an effective weight of +1. The digital word stored in the two bit storage elements being 10 causes both weighting capacitors to be connected to the negative input line, so the capacitor pair provides an effective weight of -1. FIGURE 24 is a conceptual schematic diagram of how a quad connection of four capacitors having their capacitances digitally controlled by two's complement weighting factor words can be constructed in accordance with the invention. Lines LINE1 , LINE2, LINE3 and LINE4 of FIGURE 24 may be considered to correspond to POSITIVE LINE, to NEGATIVE LINE, to COMMON LINE and to ac ground, respectively, of FIGURE 9. One pair of the four capacitors in the quad is provided by selective connection of component capacitive elements CO, C1, C2, C3 and C4 to lines LINE1 44 and LINE2. Capacitive elements CO, C1 , C2, C3 and C4 have respective capacitances weighted in 2°:2°:2 1 :2 2 :2 3 ratio; have respective first plates each connected to LINE3; and have respective second plates connected by respective ones of single-poie-doubie- throw electronic switches SW1 , SW2, SW3 and SW4 each to LINE1 or to LINE2. Single-pole-double-throw electronic switches SW1, SW2, SW3 and SW4 each provide for connection to LINE1 or to LINE2, as determined by a respective bit of a weighting word, which word is stored in a respective word storage element WSEjj. The other pair of the four capacitors in the quad is provided by selective connection of component capacitive elements C10, C11, C12, C13 and C14. Capacitive elements C10, C11, C12, C13 and C14 have respective capacitances weighted in 2°:2°:2 1 :2 2 :2 3 ratio; have respective first plates each connected to LINE4; and have respective second plates connected by respective ones of single-pole-double- throw electronic switches SW11, SW12, SW13 and SW14 each to LINE1 or to LINE2. Component capacitive elements C10, C11 , C12, C13 and C14 have respective capacitances which correspond to the respective capacitances of component capacitive elements CO, C1 , C2, C3 and C4, respectively. Single-pole-double-throw electronic switches SW11, SW12, SW13 and SW14 each provide for connection to L1NE1 or to LINE2 in a way complementary to the way the electronic switches SW1, SW2, SW3 and SW4 do, as determined by a respective bit of the weighting word stored in a respective word storage element WSEjj. Lines LINE1 , LINE2, LINE3 and LINE4 of FIGURE 24 have thusfar been considered to correspond to POSITIVE LINE, to NEGATIVE LINE, to COMMON LINE and to ac ground, respectively. In such case, to prevent stray capacitance to substrate ground appearing in unbalanced form on the POSITIVE LINE and the NEGATIVE LINE - i.e., more on one of the lines LINE1 and LINE2 than on the other - the component capacitive elements CO, C1, C2, C3 and C4 are poled so as to place their stray capacitances to substrate on LINE3, the COMMON LINE. The component capacitive elements C10, C11, C12, C13 and C14 are poled so as to connect to LINE4, and thence to substrate ground, their stray capacitances to substrate, which avoids their having to be charged and discharged at all. Alternatively, lines LINE1 , LINE2, LINE3 and LINE4 of FIGURE 24 can be considered to correspond to COMMON LINE, to ac ground, to POSITIVE LINE and to NEGATIVE LINE, respectively. In such case, to prevent stray capacitance to substrate ground appearing in unbalanced form, more on one of the lines POSITIVE LINE and NEGATIVE LINE than on the other, the component capacitive elements CO, C 1 , C2, C3 and C4 are poled so as to place their stray capacitances to substrate on the POSITIVE LINE, LINE3; and the component capacitive elements C10, C11 , C12, C13 and C14 are poled so as to place their stray capacitances to substrate on the NEGATIVE LINE, LINE4. However, this method of avoiding unbalanced stray capacitance to substrate appearing on the POSITIVE LINE and NEGATIVE LINE relies on matching between the stray capacitances of component capacitive elements CO, C1 , C2, C3 and C4 and the stray capacitances of component capacitive elements C10, C11 , C12, C13 and C14, unless the stray capacitances to substrate of the POSITIVE LINE and of the NEGATIVE LINE is shunted by relatively low source impedance balanced drive from differential amplifier IDj. So, the former method of avoiding unbalanced stray capacitance to substrate appearing on the POSITIVE LINE and NEGATIVE LINE is preferred over the latter method, at least where these lines are to differentially sensed by an output driver amplifier ODj. The FIGURE 6 type of neural net uses pairs of input lines driven by balanced input signals for connection to the pairs of differentially sensed output lines by weighting capacitors connected in quad configurations and operated as full bridges. In the FIGURE 6 type of neural net, lines LINE3 and LINE4 of FIGURE 24 can be chosen to correspond to one of the pairs of input lines driven by balanced input signals, and LINE1 and LINE2 can be considered to correspond to one of the the * pairs of differentially sensed output lines. This choice arranges for the unbalanced stray capacitance to substrate appearing on LINE3 and LINE4 to be shunted by relatively low source impedance balanced drive from differential amplifier IDj. FIGURE 25 is a conceptual schematic diagram of how a quad connection of four capacitors having their capacitances digitally controlled by one's complement weighting factor words can be constructed in accordance with the invention. One pair of the four capacitors is provided by selective connection of component capacitive elements C20, C21 , C22, C23 and C24 . Capacitive elements C20, C21 , C22, C23 and C24 have respective capacitances weighted in 2°:2°:2 1 :2 2 :2 3 ratio; have respective first plates each connected to LINE3; and have respective second plates connected by respective ones of single-pole-double-throw electronic switches SW20, SW21 , SW22, SW23 and SW24 each to LINE1 or to 2LINE. Single-pole-double-throw electronic switches SW24, SW20, SW23, SW22 and SW21 each provide for connection to LINE1 or to LINE2, as determined by successive bits of a weighting word stored in bit stores BS14, BS10, BS13, BS12 and BS11 of a respective word storage element WSEjj'. The other pair of the four capacitors is provided by selective connection of component capacitive elements C30, C31 , C32, C33 and C34. Capacitive elements C30, C31 , C32, C33 and C34 have respective capacitances weighted in 2°:2°:2 1 :2 2 :2 3 ratio; have respective first plates each connected to LINE 4; and have respective second plates connected by respective ones of single-pole-double-throw electronic switches SW30, SW31 , SW32, SW33 and SW34 each to LINE1 or to LINE2. Component capacitive elements C30, C31, C32, C33 and C34 have respective capacitances which correspond to the respective capacitances of component capacitive elements C20, C21, C22, C23 and C24, respectively. Single-pole-double-throw electronic switches SW34, SW30, SW33, SW32 and SW31 each provide for connection to LINE1 or to LINE2 in a way complementary to the way the electronic switches SW24, SW20, SW23, SW22 and SW21 do,, as determined by successive bits of a weighting word stored in bit stores BS14, BS10, BS13, BS12 and BS11 of a respective word storage element WSEjj'. In the FIGURE 25 quad connection of capacitors, as in the FIGURE 24 quad connection of capacitors, lines LINE1 , LINE2, LINE3 and LINE4 can be considered to correspond to POSITIVE LINE, to NEGATIVE LINE, to COMMON LINE and to ac ground, respectively, or alternatively, can be considered to correspond to COMMON LINE, to ac ground, to POSITIVE LINE and to NEGATIVE LINE, respectively. In the FIGURE 6 type of neural net lines LINE1 and LINE2 of FIGURE 25 can be considered to correspond to one of the pairs of input lines driven by balanced input signals, and LINE3 and LINE4 can be considered to correspond to one of the the pairs of differentially sensed output lines. In any case, the component capacitive elements C20, C21 , C22, C23 and C24 are poled so as to place their stray capacitances to substrate on LINE3; and the component capacitive elements C30, C31 , C32, C33 and C34 are poled so as to place their stray capacitances to substrate on LINE4. The reasons for this are the same as offered in regard to the FIGURE 24 quad connection of capacitors. FIGURE 26 illustrates how, in order to provide greater resolution in weighting, at every i,j crosspoint in the neural net layer a plurality of similar weighting capacitor quads are employed rather than just a single weighting capacitor quad comprising digital capacitors DCjj, DC(j +m) ,j, DCj,(j +π ) and DC(j +m ),(j +n ). In FIGURE 26, one weighting capacitor quad MSWCi.j is used to provide weighting responsive to the leftmost (generally more significant) bits of the eight-bit weighting word stored in the word storage element WSEjj of the interstitial memory array, and another weighting capacitor quad LSWCjj is used to provide weighting responsive to the rightmost (generally less significant) bits of the weighting word stored in the word storage element WSEjj of the interstitial memory array. The relative significances of the weighting provided by the weighting capacitor quad MSWCi.j and by the other weighting capacitor quad LSWCjj are in a prescribed ratio. Much as previously, weighting capacitor quad MSWCjj supplies to a charge-sensing amplifier FDQS j weighted response to XJ input signal. Another charge-sensing amplifier FDQS( j+n ) besides charge sensing amplifier FDQSj is used for the forward propagation of signals at the i,j crosspoint of the neural net layer and is supplied via weighting capacitor quad LSWCjj with another weighted response to XJ input signal. The output port of analog multiplier AMj supplies analog signal to the input port of an analog scaling amplifier ASAj, and the analog scaling amplifier ASAj responds with an analog signal at its output port that is scaled down from the analog signal at its input port by a factor equal to the ratio of the relative significances of the weighting provided by the weighting capacitor quad MSWCi.j and by the other weighting capacitor quad LSWCjj. The input port of charge-sensing amplifier FDQS(J + N) and the output port of the analog scaling amplifier ASAj are multiplexed to the weighting capacitor quad LSWCjj via output lines OL(j + 2N) and OL(j+3N) by multiplexers OLM(j + 2N) and OLM(J+3N). Differential-input charge-sensing amplifiers FDQSj and FDQS(J+N) are both linear charge-sensing amplifiers; and in a weight and sum circuit FW&S j their output responses are added after being scaled in accordance with the ratio of the relative significances of the weighting provided by the weighting capacitor quad MSWCi.j and by the other weighting capacitor quad LSWCj j . Weight and sum circuit FW&Sj thereby generates the input signal for non-linear amplifier NLjj. For example, suppose the word storage element WSEjj stores an eight-bit word describing a weight in two's complement arithmetic, four bits of which control the weighting afforded by the weighting capacitor quad MSWCj j and four bits of which control the weighting afforded by the weighting capacitor quad LSWCj j . Then, the output signal from charge-sensing amplifiers FDQSj and FDQS(J+N) are weighted in 16:1 ratio before being summed in the weight and sum circuit FW&Sj to generate the input signal for the non-linear amplifier NLj. FIGURE 27 shows a modification of the FIGURE 26 portion of a neural net layer to provide for driving pairs of balanced output lines from single-ended input lines per FIGURES 2A and 2B. FIGURE 28 shows a modification of the FIGURE 26 portion of a neural net layer to provide for driving single-ended output lines from pairs of balanced input lines per FIGURES 4A and 4B. FIGURE 26 shows a portion of a neural net layer in which neither the input lines to or the output lines from the weighting capacitance network are single-ended. Modifications per FIGURES 27 and 28 do not affect the way in which different magnitudes of weighting are achieved with groups of switched capacitor elements which groups are alike. While FIGURES 26, 27 and 28 each show two ranks of switched capacitor elements, one for responding to the more significant bits of the weighting words stored in the interstitial memory array and the other for responding to the less significant bits of the weighting words stored in the interstitial memory array, there may instead be three or more such ranks of switched capacitor elements in accordance with the invention. Indeed, bit-slicing the weighting factors may be a preferred structure for neural net layers, owing to the facts that each portion of a neural net layer associated with a single bit slice of the weighting factors is like the other portions of the neural net layer respectively associated with the other bit slices of the weighting factors; and that that single design can use the minimum-size digitally controlled capacitors throughout. FIGURE 29 shows more particularly the nature of two corresponding pairs of capacitors in the weighting capacitor quads MSWCjj and LSWCjj when the word storage element WSEjj stores an eight-bit weight in two's complement arithmetic. One pair of capacitors in the quad is formed from the capacitive elements CO, C1 , C2, C3, and C4, which determine the differential capacitance to COMMON LINE from lines POSITIVE LS LINE and NEGATIVE LS LINE in the weighting capacitor quad LSWCj j , and from the capacitive elements C5, C6, C7, and C8, which determine the differential capacitance to COMMON LINE from lines POSITIVE MS LINE and NEGATIVE MS LINE in the weighting capacitor quad MSWCjj. The capacitive elements C5, C6, C7 and C8 in the weighting capacitor quad MSWCjj have capacitances respectively similar to those of capacitive elements C1 , C2, C3, and C4 in the weighting capacitor quad LSWCjj. The other pair of capacitors in the quad is formed from the capacitive elements C10, C11, C12, C13, and C14, which determine the differential capacitance to signal ground from lines POSITIVE LS LINE and NEGATIVE LS LINE in the weighting capacitor quad LSWCjj, and from the capacitive elements C15, C16, C17, and C18, which determine the differential capacitance to signal ground from lines POSITIVE MS LINE and NEGATIVE MS LINE in the weighting capacitor quad MSWCjj. The capacitive elements C15, C16, C17 and C18 in the weighting capacitor quad MSWCjj have capacitances respectively similar to those of capacitive elements C11 , C12, C13, and C14 in the weighting capacitor quad LSWCjj. Capacitive elements in the capacitor quad that have the same last digit in their call-out have capacitances that are similar to each other. FIGURE 29 shows bit stores BS8, BS7, BS6, BS5, BS4, BS3, BS2 and BS1 , which respectively store progressively less significant bits of a weighting word, as respective square boxes arranged from left to right within the rectangular box representing the word storage element WSEjj. The most significant bit of the eight-bit weighting word governs connection of capacitive element C8 to POSITIVE MS LINE or to NEGATIVE MS LINE by electronic switch SW8 in the reverse sense that the three next most significant bits of the eight-bit weighting word govern connection of capacitive elements C7, C6 and C5 to POSITIVE MS LINE or to NEGATIVE MS LINE by electronic switches SW7, SW6, and SW5 and in the reverse sense that the four least significant bits of the weighting word govern connections of capacitive elements C1 , C2, C3 and C4 to POSITIVE LS LINE or to NEGATIVE LS LINE by electronic switches SW1 , SW2, SW3 and SW4. The four most significant bits of the eight-bit weighting word govern connection of capacitive elements C18, C17, C16 and C15 to POSITIVE MS LINE or to NEGATIVE MS LINE by electronic switches SW18, SW17, SW16, and SW15 in the reverse sense that it governs connection of capacitive elements C8, C7, C6 and C5 to POSITIVE MS LINE or to NEGATIVE MS LINE by electronic switches SW8, SW7, SW6 and SW5. The four least significant bits of the eight-bit weighting word govern connection of capacitive elements C14, C13, C12 and C11 to POSITIVE LS LINE or to NEGATIVE LS LINE by electronic switches SW14, SW13, SW12, and SW11 in the reverse sense that it governs connection of capacitive elements C4, C3, C2 and C1 to POSITIVE LS LINE or to NEGATIVE LS LINE by electronic switches SW4, SW3, SW2 and SW1. In the FIGURE 26 neural net layer using capacitor quads per FIGURE 29, then, when respective capacitive elements C8 and C18 are included in each quad of capacitors in the weighting capacitor quad MSWCj ; these respective capacitive elements C8 and C18 are switched in reverse sense from all other capacitive elements in that quad of capacitors to implement two's complement arithmetic in regard to weighting value. Respective non-switched CO and C10 minimum-weight capacitive elements are included in each quad of capacitors in the weighting capacitor quad LSWCjj, to bias the zero-capacitance condition to correspond to the all-ZERO condition of the two's complement numbers that can be stored in the word storage element WSEjj of the interstitial memory array. However, the weighting capacitor quad MSWCj j includes no non- switched minimum-weight capacitive elements. FIGURE 30 shows more particularly the nature of a quad of capacitors in the weighting capacitance networks MSWCjj and LSWCjj when the word storage element WSEjj stores nine-bit weights in one's complement form in bit stores BS10, BS11 , BS12, BS13, BS14, BS15, BS16, BS17 and BS18. One pair of capacitors in the quad is formed from the capacitive elements C20, C21 , C22, C23, and C24, which determine the differential capacitance to COMMON LINE from lines POSITIVE LS LINE and NEGATIVE LS LINE in the weighting capacitor quad LSWCjj, and from the capacitive elements C25, C26, C27, and C28, which determine the differential capacitance to COMMON LINE from lines POSITIVE MS LINE and NEGATIVE MS LINE in the weighting capacitor quad MSWCjj. The capacitive elements C25, C26, C27 and C28 in the weighting capacitor quad MSWCjj have capacitances respectively similar to those of capacitive elements C21 , C22, C23, and C24 in the weighting capacitor quad LSWCjj. The other pair of capacitors in the quad is formed from the capacitive elements C30, C31 , C32, C33, and C34, which determine the differential capacitance to signal ground from lines POSITIVE LS LINE and NEGATIVE LS LINE in the weighting capacitor quad LSWCj j , and from the capacitive elements C35, C36, C37, and C38, which determine the differential capacitance to signal ground from lines POSITIVE MS LINE and NEGATIVE MS LINE in the weighting capacitor quad MSWCjj. The capacitive elements C35, C36, C37 and C38 in the weighting capacitor quad MSWCjj have capacitances respectively similar to those of capacitive elements C31 , C32, C33, and C34 in the 52 weighting capacitor quad LSWCjj. Capacitive elements in the capacitor quad that have the same last digit in their call-out have capacitances that are similar to each other. The weighting capacitor quad MSWCj j has no capacitive element corresponding to capacitive element C20 or C30 in the weighting capacitor quad LSWCjj. FIGURE 30 shows bit stores BS18, BS10, BS17, BS16, BS15, BS14, BS13, BS12 and BS11 which respectively store successive bits of a nine-bit weight in one's complement arithmetic, as respective square boxes arranged from left to right within the rectangular box representing the word storage element WSEjj'. The leftmost bit of the nine-bit weighting word stored in bit store BS18 governs connection of capacitive element C28 to POSITIVE MS LINE or to NEGATIVE MS LINE by electronic switch SW28, depending whether that bit is a ONE or a ZERO; and that leftmost bit also governs connection of capacitive element C38 to POSITIVE MS LINE or to NEGATIVE MS LINE by electronic switch SW38, depending whether that bit is a ZERO or a ONE. The next to leftmost bit of the nine-bit weighting word stored in bit store BS10 governs connection of capacitive element C20 to POSITIVE LS LINE or to NEGATIVE LS LINE by electronic switch SW20, depending whether that bit is a ONE or a ZERO; and that next to leftmost bit also governs connection of capacitive element C30 to POSITIVE LS LINE or to NEGATIVE LS LINE by electronic switch SW30, depending whether that bit is a ZERO or a ONE. The three next most left bits of the nine-bit weighting word stored in bit stores BS17, BS16 and BS15 govern connection of capacitive elements C27, C26 and C25 to POSITIVE MS LINE or to NEGATIVE MS LINE by electronic switches SW27, SW26 and SW25, respectively, depending whether those bits are respectively each a ONE or a ZERO. The bits stored in bit stores BS17, BS16 and BS15 also govern connection of capacitive elements C37, C36 and C35 to POSITIVE MS LINE or to NEGATIVE MS LINE by electronic switches SW37, SW36 and SW35, respectively, depending whether those bits are respectively each a ZERO or a ONE. The four rightmost bits of the weighting word stored in bit stores BS11, BS12, BS13 and BS14 govern connections of capacitive elements C21 , C22, C23 and C24 to POSITIVE LS LINE or to NEGATIVE LS LINE by electronic switches SW21 , SW22, SW23 and SW24, respectively, depending whether those bits are respectively each a ONE or a ZERO. The four bits stored in bit stores BS11 , BS12, BS13 and BS14 also govern connections of capacitive elements C31 , C32, C33 and C34 to POSITIVE LS LINE or to NEGATIVE LS LINE by electronic switches SW31 , SW32, SW33 and SW34, respectively, depending whether those bits are respectively each a ZERO or a ONE.

Claims: WHAT IS CLAIMED IS: 1. Apparatus for generating a number of weighted summation signals responsive to a plurality of input signals, wherein each weight is determined by the difference in the respective capacitances of a respective pair of first and second weighting capacitors CHARACTERIZED BY each pair of first and second weighting capacitors comprising: a respective plurality, P in number, of capacitive elements (C1, C2, C3, C4; C21 , C22, C23, C24) respectively identified by consecutive ordinal numbers first through P tπ , each said capacitive element having between respective first and second plates thereof a respective capacitance, the capacitance of each capacitive element being scaled in 2 (k~1) ratio with the capacitance of said first capacitive element, where k corresponds to the ordinal number of that said capacitive element; a respective storage location (WSEjj) in an electronic memory, for storing a selection signal in digital form; and respective electronic selection switch circuitry, composed of transmission gates (SW1 , SW2, SW3, SW4; SW21 , SW22, SW23, SW24) responding to said selection signal stored in digital form in respective storage location in said electronic memory, for selecting each of said first through P tπ capacitive elements as a component of either the first or second of said respective pair of weighting capacitors, to be parallelly connected with any other of said first through P tn capacitive elements selected as a component of the same weighting capacitor. 2. Apparatus for generating a number of weighted summation signals, as set forth in Claim 1 CHARACTERIZED BY each said pair of first and second weighting capacitors being in bridge connection with a respective other pair of third and fourth weighting capacitors of similar construction that shares a respective storage location (WSEjj) in said electronic memory; that includes a respective plurality, P in number, of further capacitive elements (C11 , C12, C13, C14; C31 , C32, C33, C34); that includes respective electronic selection switch circuitry, composed of further transmission gates (SW11 , SW12, SW13, SW14; SW31 , SW32, SW33, SW34) responding to said selection signal stored in digital form in said respective storage location in said electronic memory, for selecting each of said further capacitive elements as a component of either the third or fourth weighting capacitor of said other pair of weighting capacitors, to be paralleliy connected with any other of said further capacitive elements selected as a component of the same weighting capacitor, such that within each said bridge connection the sum of the capacitances of the first and third weighting capacitors equals a standard value and the sum of the capacitances of the second and fourth weighting capacitors equals said standard value. 3. Apparatus for generating a number of weighted summation signals, as set forth in Claim 2 CHARACTERIZED BY: within each pair of first and second weighting capacitors in one of said bridge connections, a respective zeroeth capacitive element (CO) having between respective first and second plates thereof a respective capacitance equal to the capacitance of said first capacitive element between respective first and second plates thereof, said zeroeth capacitive element being included in the first of that pair of weighting capacitors to be paralleliy connected with any other of said first through P tπ capacitive elements selected as a component of the same weighting capacitor, the second of which pair of weighting capacitors will be essentially zero-valued when the respective electronic selection switch circuitry for that pair of weighting capacitors selects all of said first through P tπ capacitive elements as components of the first of that pair of weighting capacitors; within each pair of third and fourth weighting capacitors in one of said bridge connections, a still further capacitive element (C10) having between respective first and second plates thereof a respective capacitance equal to the capacitance of said zeroeth capacitive element between respective first and second plates thereof, said still further capacitive element being included in the fourth of that pair of weighting capacitors to be paralleliy connected with any other of said furtherelements selected as a component of the same weighting capacitor, the third of which pair of weighting capacitors will be essentially zero-valued when the respective electronic selection switch circuitry for that pair of weighting capacitors selects all of said further capacitive elements as components of the fourth of that pair of weighting capacitors. 4. Apparatus for generating a number of weighted summation signals, as set forth in Claiml CHARACTERIZED BY each pair of first and second weighting capacitors further including a respective zeroeth capacitive element (C20) having between respective first and second plates thereof a respective capacitance equal to the capacitance of said first capacitive element between respective first and second plates thereof, said respective electronic selection switch circuitry included within each said pair of said weighting capacitors together with said respective zeroeth capacitive element including a transmission gate (SW20) responding to a respective further bit of its said selection signal stored in said respective storage location in said electronic memory for selecting said zeroeth capacitive element as a component of either the first of or a second of that said pair of weighting capacitors. 5. Apparatus for generating a number of weighted summation signals, as set forth in Claim 4 CHARACTERIZED BY each said pair of first and second weighting capacitors being in bridge connection with a respective other pair of third and fourth weighting capacitors of similar construction that shares a respective storage location (WSEjj) in said electronic memory; that includes a respective plurality, P in number, of further capacitive elements (C31 , C32, C33, C34, C30); that includes respective electronic selection switch circuitry, composed of further transmission gates (SW31 , SW32, SW33, SW34, SW30) responding to said selection signal stored in digital form in said respective storage location in said electronic memory, for selecting each of said further capacitive elements as a component of either the third or fourth weighting capacitor of said other pair of weighting capacitors, to be paralleliy connected with any other of said further capacitive elements selected as a component of the same weighting capacitor, such that within each said bridge connection the sum of the capacitances of the first and third weighting capacitors equals a standard value and the sum of the capacitances of the second and fourth weighting capacitors equals said standard value. 6. Apparatus for generating a number of weighted summation signals, as set forth in Claiml CHARACTERIZED BY each pair of first and second weighting capacitors further including a respective zeroeth capacitive element (CO) having between respective first and second plates thereof a respective capacitance equal to the capacitance of said first capacitive element between respective first and second plates thereof, said zeroeth capacitive element being included in the first of that pair of weighting capacitors to be paralleliy connected with any other of said first through P tπ capacitive elements selected as a component of the same weighting capacitor, the second of which pair of weighting capacitors will be essentially zero-valued when the respective electronic selection switch circuitry for that pair of weighting capacitors selects all of said first through P tπ capacitive elements as components of the first of that pair of weighting capacitors. 7. Apparatus for generating a number of weighted summation signals, as set forth in any of Claims 1-6 CHARACTERIZED BY being included in a layer of a neural network together with non-linear amplifier circuitry (OD; NL) for generating a respective sigmoidal response to each of said weighted summation signals. 8. Apparatus for generating a number of weighted summation signals included in a layer of a neural network together with non-linear amplifier circuitry, as set forth in Claim 7, CHARACTERIZED BY said neural network including back-propagation training circuitry for use in time intervals when said neural network is being trained by application of patterns of input signals for which desired neural network responses are known, by said pairs of weighting capacitors being selectively connected within said back- propagation training circuitry to use the differences in the respective capacitances of said pairs of weighting capacitors in generating the weighted summations required in the operation of said back-propagation training circuitry during said time intervals when said neural network is being trained, and by said back- propagation training circuitry being connected to modify the selection signals in digital form stored in the respective storage locations in said electronic memory. 9. Apparatus for generating a number of weighted summation signals, as set forth in any of Claims 1 , 4 and 6 CHARACTERIZED BY being included in combination with: apparatus as set forth in Claim 1 for generating a number of weighted summation signals, each of which apparatuses is supplied the same plurality of input signals to respond to to generate their respective sets of weighted summation signals, identifiable as partial summation signals; and a plurality of further apparatuses each for generating a respective final weighted summation signal by combining with appropriate weighting corresponding ones of said respective sets of weighted summation signals identifiable as partial summation signals. 10. Apparatus for generating a number of weighted summation signals, as set forth in any of Claims 2, 3 and 5 CHARACTERIZED BY being included in combination with: apparatus as set forth in Claim 2 for generating a number of weighted summation signals, each of which apparatuses is supplied the same plurality of input signals to respond to to generate their respective sets of weighted summation signals, identifiable as partial summation signals; and a plurality of further apparatuses each for generating a respective final weighted summation signal by combining with appropriate weighting corresponding ones of said respective sets of weighted summation signals identifiable as partial summation signals. 1 1. Apparatus for generating a number of weighted summation signals, as set forth Claim 8 or 9 CHARACTERIZED BY being included in a layer of a neural network together with non-linear amplifier circuitry (OD; NL) for generating a respective sigmoidal response to each of said weighted summation signals. 12. Apparatus for generating a number of weighted summation signals included in a layer of a neural network together with non-linear amplifier circuitry, as set forth in Claim 11 , CHARACTERIZED BY said neural network including back-propagation training circuitry for use in time intervals when said neural network is being trained by application of patterns of input signals for which desired neural network responses are known, by said pairs of weighting capacitors being selectively connected within said back- propagation training circuitry to use the differences in the respective capacitances of said pairs of weighting capacitors in generating the weighted summations required in the operation of said back-propagation training circuitry during said time intervals when said neural network is being trained, and by said back- propagation training circuitry being connected to modify the selection signals in digital form stored in the respective storage locations in said electronic memory.

Inventors: ENGELER WILLIAM ERNEST, ENGELER, WILLIAM, ERNEST
Applicants: GEN ELECTRIC, GENERAL ELECTRIC COMPANY
Application year: 1991
Main classification: G06F15
IPC codes: G06F15, G06G7, G06N1, G06N3, G11C27