Method of controlling three-phase, three-level inverter

Abstract: A method of controlling a three-phase, three-level inverter comprises the steps of: judging whether the current of the output terminal of an inverter of the phase such that the electrical potential of the output terminal equals to the neutral-point terminal of the capacitor among three-output terminals of the inverter is in a positive direction in which current flows into a load connected to this output terminal or in a negative direction in which current flows from the load when another on/off mode having the same instantaneous space voltage vector as the instantaneous space voltage vector in a tentatively selected on/off mode exists; actually selecting the tentatively selected on/off mode if the result of the judgment is positive and actually selecting another on/off mode instead of the tentatively selected on/off mode when the result of the judgment is negative in the case where the electrical potential of the neutral-point terminal of the capacitor is above a preset upper-limit value; and actually selecting the tentatively selected on/off mode if the result of the judgment is negative and actually selecting another on/off mode instead of the tentatively selected on/off mode when the result of the judgment is positive in the case where the electrical potential of the neutral-point terminal of the capacitor is below a preset lower-limit value.

Description: The present invention relates to a method of controlling a three-phase, three-level inverter and, in particular, to a control method of suppressing the variation of a neutral-point electrical potential of a capacitor contained in the inverter. The article in EPE 1989 3rd European Conference on Power Electronics and Applications, Vol. 3, 9 October 1989, Aachen, pages 1267 - 1272; Steinke: "Switching frequency optimal PWM control of a three-level inverter", discloses a pulse width modulation method for controlling a three-phase, three-level inverter. By switching both thyristor pairs within each sample period, the carrier frequency has to be chosen equal to the permitted thyristor switching frequency. The article proposes an optimal switching frequency PWM method, by which only one thyristor pair of each phase of the inverter is switched per sample period. The mean switching load of the thyristor pairs becomes balanced, whereby the mean thyristor switching frequency is only one half of the carrier frequency. The method is also capable of stabilising the potential of the neutral point of the DC link capacitor without additional power disippation. Fig. 2 is a circuit diagram showing the arrangement of another conventional three-phase, three-level inverter presented, for example, in "A Current Control Scheme for Neutral-Point-clamped Voltage Source Inverters for Vector Control Systems", Thesis No. 113, Electrical Society, Industrial Application Department National Conference in 1989. In Fig. 2, the inverter includes a DC voltage source 1, a reactor 2 connected to the positive terminal of the DC voltage source 1, and a capacitor 3, one terminal P thereof being connected to the reactor 2 and the other terminal N thereof being connected to the negative terminal of the DC voltage source 1. The capacitor 3 is made up of a pair of capacitors 3a and 3b of the same rating, and a neutral-point terminal O is lead out from the point at which these capacitors are connected. The inverter has pairs of transistors 4a-4b, 4c-4d, 5a-5b, 5c-5d, 6a-6b, and 6c-6d, each transistor of each pair being connected in serial. The first transistor pair 4a-4b and the second transistor pair 4c-4d, the third transistor pair 5a-Sb and the fourth transistor pair 5c-5d, and the fifth transistor pair 6a-6b and the sixth transistor pair 6c-6d are respectively connected in series. These series circuits are connected in parallel to each other between both of the terminals P and N of the capacitor 3. To each of the transistors 4a-4d, 5a-5d, and 6a-6d, free-wheeling diodes 7a-7d, 8a-8d, and 9a-9d are respectively reversely connected in parallel. The cathodes of the first, third, and fifth diodes 10a, 11a, and 12a are respectively connected to the intermediate points of the first, third, and fifth transistor pairs. Each anode of these diodes is connected to the neutral-point terminal O of the capacitor 3. The anodes of the second, fourth, and sixth diodes 10b, 11b, 12b are respectively connected to the intermediate points of the second, fourth, and sixth transistor pairs. Each cathode of these diodes is connected to the neutral-point terminal O of the capacitor 3. Further, a U-phase output terminal T u is lead out from the connection point of the first transistor pair and the second transistor pair. A V-phase output terminal T v is lead out from the connection point of the third transistor pair and the fourth transistor pair. A W-phase output terminal T w is lead out from the connection point of the fifth transistor pair and the sixth transistor pair. Next, the operation of the conventional inverter will be explained. First, the U phase will be taken as an example. The switching state of each of the transistors 4a to 4d of the U phase, i.e., the relationship between the on/off mode and the electrical potential of the output terminal T u , is shown in Table 1. The output voltage of the DC voltage source 1 is taken to be 2E. As shown above, the electrical potential or voltage of the output terminal T u has three kinds of values corresponding to the terminals P, N, and O of the capacitor 3, the particular value depending upon the switching state of the transistor. This is the reason why the inverter is called a three-level inverter. The same can be said about the V and W phases as has been said above about the U phase. Next, the on/off mode of each transistor is in turn switched in order to take out the three phase outputs. It is considered that this on/off mode has a total of 33 = 27 kinds of modes. However, some of the on/off modes of these transistors have the same instantaneous space voltage vector (hereinafter referred to simply as a voltage vector) which is determined by the above-mentioned three kinds of electrical potentials. For this reason, there are a total 19 kinds of voltage vectors which are separate from each other. Table 2 summarizes the above relationship and shows the relationships among on/off modes M1 to M27, voltage vectors VO to V18, and the output potentials V u , V v , and V w of each of the output terminals T u , T v , and T w . It is necessary that the neutral-point terminal O of the capacitor 3 be primarily at a zero potential. In practice, however, it varies due to a load current I u supplied to the load from the output terminal T u , and so on. A technique for controlling the selection of the on/off mode in order to suppress the amount of this variation has been previously performed. That is, as can be understood from Table 2, when a voltage vector V1 is output, M4 and M5, for example, can be selected as an on/off mode. Since the connection relationship among the neutral-point terminal O and the output terminal T u differ depending upon the on/off state of each transistor in both of the modes, the influence exerted on the electrical potential of the middle point terminal O by the load current I u will differ in both of the modes. Hence, the mode in which the electrical potential variation of the neutral-point terminal O is smaller is selected. In the conventional three-phase, three-level inverter, the selection of the above-mentioned on/off mode performed in order to suppress the electrical potential variation of the neutral-point terminal O has been determined from a load current vector. That is, a load current vector is computed from the load currents I u , I v , and I w of each phase, and an on/off mode to be selected has been determined from the area of this load current vector. Accordingly, as a computation process by which a load current vector is determined is required, the apparatus for the conventional procedure becomes more complex and expensive. The present invention has the purpose of avoiding the above-mentioned problems. An object of the present invention is to provide a method of controlling a three-phase, three-level inverter, which method is capable of easily making the selection of an on/off mode to suppress an electrical potential variation of the neutral-point terminal O of a capacitor without using a complex apparatus. According to the present invention, a method of controlling a three-phase, three-level inverter is provided as defined in claim 1. Fig. 1 is a flowchart showing a control method according to the first embodiment of the present invention; and Fig. 2 is a circuit diagram showing a conventional three-phase, three-level inverter. The main circuit arrangement of an inverter controlled by this embodiment is identical to that of the conventional circuit shown in Fig. 2, thus an explanation thereof is omitted. Fig. 1 is a flowchart showing a series of operations from "Start" to "End" which are performed in a fixed sampling cycle. In Fig. 1, S1 is a step in which a voltage vector required to obtain a desired three-phase AC output is selected, which corresponds to the primary function of the inverter. To be specific, one of the voltage vectors V0 to V18 listed in Table 2 is selected, and a control signal is sent out to each transistor in accordance with the on/off modes M1 to M27 for generating the selected voltage vector. S2 is a step in which whether or not the voltage vector No. selected in step S1 is 3n+1 (where n=0 to 5) is determined. That is, as is understood from Table 2, it is determined whether or not a pair of on/off modes of two kinds exist for the same voltage vector, for example, as for V1. If the voltage vector No. does not correspond to one of these numbers, there is no room for selection, and the process is terminated without further action. If the voltage vector No. corresponds to one of these numbers, the process proceeds to step S3, where whether or not the electrical potential E c of the neutral-point terminal O of the capacitor 3 falls below a predetermined lower-limit value (Ec *- ΔE c ) is determined. E c * indicates the electrical potential instruction value of the neutral-point terminal 0, and ΔE c indicates an allowable voltage width. If it is determined in step S3 that E c is below a predetermined lower-limit value, it is judged that a charging request is made, and the process proceeds to step S4 where the capacitor 3 is brought into a charged state so that its electrical potential rises. That is, of the two kinds of on/off modes which exist for the same voltage vector, a mode in which an output electrical potential becomes zero for only one phase is tentatively selected. For example, if the case where a voltage vector is V10 is assumed, an on/off mode M17 corresponds to the one to be selected. Thus, the on/off mode M17 is tentatively selected. In the subsequent step S5, whether or not the current of the phase in which the output electrical potential is zero is negative, i.e., the current I u of the U phase is negative in the tentatively selected mode M17, is determined. At this point, the direction in which a current flows out to a load is taken to be positive. Therefore, in step S5, whether or not a current is in the direction in which it flows into the capacitor 3, i.e., whether the above-mentioned charging request is satisfied, is determined. If the result of the judgment is negative, it is judged that the charging request is satisfied, and the corresponding mode is actually selected without further action in step S6, then the process is terminated. Returning now to step S3, if it is judged that the electrical potential E c of the neutral-point terminal O is not below the lower-limit value, it is determined in step S7 whether or not this electrical potential E c is above a predetermined upper-limit value (E c * + ΔE c ). If it is determined that E c is above the upper-limit value, it is judged that the capacitor 3 is in the discharge request state. After the same mode selection is made in step S8 as in step S4, it is determined in step S9 whether or not the discharge request is satisfied at this time, i.e., whether or not the current of the corresponding phase flows out from the capacitor 3 in the positive direction. If it is the positive direction, the process proceeds to step S6, where the mode which has been tentatively selected is actually selected, and the process is terminated. When it is judged in step S5 that it is not negative, or when it is judged in step S9 that it is not positive, the process proceeds to step S10, where the other mode from among the two kinds of on/off modes is actually selected. At this point, the reason why the charge or discharge request is satisfied by the process of step S10 will be explained. As can be understood from Table 2, in the other mode, the output electrical potential of the other two phases except the phases which were taken notice of in step S4 or S8 becomes zero. That is, the output terminals of the above two phases are directly connected to the neutral-point terminal O of the capacitor 3. If the currents of each phase to a load are denoted as I u , I v , and I w , then the following relation holds: I u + I v + I w = 0. Therefore, when an explanation is made following the case of the voltage vector V10 described above, if the phase current I u of the on/off mode M17 tentatively selected in step S4 is judged to be "not", i.e., positive, from the following equation derived from the above relation: I v + I w = -I u , the current (I v + I w ) of the capacitor 3 is negative in the other on/off mode M16. Therefore, the current will flow into the capacitor 3, and the charging request is satisfied. Returning now to step S7, when it is judged that the electrical potential E c is not above the upper-limit value, the electrical potential E c of the neutral-point terminal O is seen to exist in the allowable range, after all. Any mode may be selected from the viewpoint of voltage variation. Therefore, in step S11, the on/off mode in which variation of on/off states of switching elements, such as transistors, from the previous on/off mode is smaller is actually selected. As has been explained above, in this embodiment, a proper selection of an on/off mode is made possible by a simple process of judging whether a current is positive or negative without performing a complex current vector computation. Hence, the apparatus of the present invention becomes simple, and operates more reliably and stably. In the above-described embodiment, the upper-limit value and the lower-limit value of the variation width of the neutral-point terminal O are set in such a way that an allowable voltage width ΔE c is added to or subtracted from the electrical potential instruction value E c *. These limit values may be set freely as required.

Claims: A method for controlling a three-phase, three-level inverter, in which a plurality of on/off modes are switched in turn for controlling an instantaneous space voltage vector (VO - V18) made up of a combination of the electrical potentials across terminals (P, N, O) of a capacitor pair (3a, 3b), said inverter comprising a DC voltage source (1), said capacitor pair (3a, 3b) having two terminals (P, N) connected to said DC voltage source (1) and having a neutral point terminal (O) positioned between the capacitors (3a, 3b) and between the two terminals (P, N), a plurality of switch element pairs (4a-4b, 4c-4d, 5a-5b, 5c-5d, 6a-6b, 6c-6d) connected in series between each of the two terminals (P, N) and the neutral point terminal (O) respectively and three output terminals (Tu, Tv, Tw) for each phase of the inverter, characterized in that said method comprises the steps of: a) tentatively selecting an on/off mode for the desired space voltage vector (V0 - V18) by which the output electrical potential is zero for only one of the three phases; b) judging whether the current of the output terminal (Tu, Tv, Tw) for this one phase is in a positive direction in which current flows into a load connected to the output terminal or is in a negative direction in which current flows from the load; c) when the electrical potential of the neutral point terminal (O) of said capacitor pair (3a, 3b) is above a preset upper-limit value, actually selecting the tentatively selected on/off mode, if the judgement is positive and selecting another on/off mode if the judgement is negative; or d) when the electrical potential of the neutral point terminal (O) of said capacitor pair (3a, 3b) is below a preset lower-limit value, actually selecting the tentatively selected on/off mode, if the judgement is negative and selecting another on/off mode if the judgement is positive. The control method of claim 1, wherein when the electrical potential of the neutral point terminal (O) of said capacitor pair (3a, 3b) is between the preset upper-limit value and the preset lower-limit value, the method further comprises the step of selecting the on/off mode in which the switching variation between on/off states of the switching element pairs (4a-4b, 4c-4d, 5a-5b, 5c-5d, 6a-6b, 6c-6d) from the previously selected on/off mode is the smallest. The control method of claim 1, wherein the upper-limit value comprises an allowable voltage width (ΔE c ) added to the electrical potential value (E* c ) of the neutral point terminal (O) of said capacitor pair (3a, 3b). The control method of claim 1, wherein the lower-limit value comprises an allowable voltage width (ΔE c ) subtracted from the electrical potential value (E* c ) of the neutral point terminal (O) of the capacitor pair (3a, 3b).

Inventors: MARUYAMA TAKAFUMI C O ITAMI SE, MARUYAMA, TAKAFUMI, C/O ITAMI SEISAKUSHO OF MITSUB
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1991
Main classification: H02M7
IPC codes: H02M7