Charge transfer device

Abstract: A charge transfer device comprises a charge transfer section having a charge transfer region formed in a semiconductor substrate and transfer electrodes formed on the semiconductor substrate, and a reset transistor having a floating diffusion region formed in the semiconductor substrate for receiving an electric charge transferred from the charge transfer section, a reset drain applied with a reset voltage, and a reset gate formed above a channel between the floating diffusion region and the reset drain, the reset gate being applied with a reset pulse. A a peak hold circuit is connected to the reset gate of the reset transistor for hold a peak level of the reset voltage. A potential detection circuit includes a dummy transistor having a drain connected to a voltage V DD , a source grounded through a resistor which is considerably larger than an on-resistance of the dummy transistor itself, and a gate electrode connected to an output of the peak hold circuit. The dummy transistor has the same characteristics as that of the reset transistor, and the drain of the dummy transistor is directly connected to the reset drain of the reset transistor.

Description: Background of the Invention Field of the invention The present invention relates to a charge transfer device, and more specifically, to an output circuit for a charge transfer device including an electrically floating diffusion at a substrate surface. Description of related art In general, charge transfer devices having a buried channel have comprised an output circuit requiring a high voltage for a reading of a transferred charge. On the other band, most of the present systems are of a 5V voltage supply type, and therefore, have a pumping-up circuit for generating a high voltage and a DC clamp circuit receiving the generated high voltage for supplying a calibrated high voltage to the output circuit for the charge transfer device. However, since the charge transfer devices inevitably have dispersion or variation in manufacture, for example, a potential of a channel under a reset gate also has dispersion or variation. In order to compensate the dispersion or variation of the channel potential, it has been necessary to make a complicated adjustment for a reset pulse voltage. EP-A-0292895 discloses a charge transfer device according to the pre-characterizing portions of claim 1 or claim 6. This charge transfer device includes voltage following means for causing the reset voltage of the drain to follow the channel potential detected by said potential detection means when said reset transistor is in the reseting operation. Summary of the Invention Accordingly, it is an object of the present invention to provide a charge transfer device which has overcome the above mentioned defect of the conventional one. Another object of the present invention is to provide a charge transfer device capable of automatically compensating the channel potential variation. The above objects of the present invention are achieved in accordance with the present invention by a charge transfer device as indicated in claim 1 or claim 6. The above objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings. Brief Description of the Drawings Figure 1A is a diagrammatic sectional view of a conventional buried channel type charge transfer device; Figures 1B and 1C illustrate two different conditions of potential wells formed in the charge transfer device shown in Figure 1A; Figure 2 is a graph illustrating a relation between a gate voltage and a buried channel potential; Figure 3A is a circuit diagram of a DC clamp circuit for adjusting the reset pulse  R applied to the output circuit of the charge transfer device; Figure 3B is a timing chart illustrating an operation of the clamp circuit shown in Figure 3A; Figure 4 is a circuit diagram of one embodiment of the charge transfer device in accordance with the present invention; Figure 5 illustrates a potential well in the output circuit of the charge transfer device shown in Figure 4; Figure 6 is a timing chart illustrating an operation of the charge transfer device shown in Figure 4; and Figure 7 is a circuit diagram of another embodiment of the charge transfer device in accordance with the present invention. Description of the Preferred embodiments Referring to Figure 1A, there is shown a diagrammatic sectional view of a conventional buried channel type charge transfer device. In Figure 1A, the charge transfer device includes a p-type semiconductor substrate 1 having an upper surface coated with an insulating layer 2. Transfer electrodes 2a, 2b and 2c and an output gate 3 are provided on the insulating layer 2. The transfer electrodes 2a, 2b and 2c are applied with a two-phase transfer clock, namely, are alternately applied with clocks ₁ and ₂ opposite to each other in phase, and the output gate 3 is connected to a fixed output gate voltage V OG . A floating diffusion 4 is formed at a surface region of the substrate 1 under the insulating layer 2 so as to convert a transferred signal charge into a potential change. Adjacent to the floating diffusion 4, a reset gate 5 is formed on the insulating layer 2. This reset gate 5 is connected to receive a reset pulse  R in synchronism with the transfer clock. In addition, a reset drain 6 is formed at the surface region of the substrate 1 under the insulating layer 2 and adjacent to the reset gate 5. This reset drain 6 is connected to a constant reset voltage V RD . The floating diffusion 4, the reset gate 5 and the reset drain 6 form a reset transistor of a MOS type. An n-type diffusion layer 7 is formed at the surface region of the substrate so as to form a buried channel of the charge transfer section and a channel of the reset transistor, and a plurality of p-type barrier layers 8 are formed in the n-type diffusion layer 7. Operation of the charge transfer device will be explained with reference to Figures 1B and 1C which illustrate two different conditions of potential wells formed in the charge transfer device shown in Figure 1A. (1) When the clock ₁ applied to the transfer electrodes 2a and 2c of the charge transfer device is at a high level and the clock ₂ applied to the transfer electrodes 2b is at a low level, an electric charge flows as indicated by an arrow 201 and is accumulated at a region under an output side electrode of the transfer electrodes 2a (Figure 1B). (2) When the clock ₁ applied to the transfer electrodes 2a and 2c is brought to the low level and the clock ₂ applied to the transfer electrodes 2b is brought to the high level, the electric charge accumulated at the region under the output side electrode of the transfer electrodes 2a flows into the floating diffusion 4 through a channel region under the output gate 3 applied with the fixed-output gate voltage V OG , as indicated by an arrow 202 (Figure 1C). Thus, the signal charge is detected in the form of a voltage signal. (3) When the clocks applied to the transfer electrodes 2a, 2b and 2c are brought into the same condition as the above condition (1), again, and when the reset pulse  R is brought into a high level, the signal charge flows as indicated by an arrow 203 so that the signal charge is extracted out of the reset drain 6. With repetition of the above process, signal charges which have been transferred to the output circuit are sequentially read out in the form of a signal voltage. In the above mentioned charge transfer device, the amount of charge which can be converted into a voltage by the floating diffusion 4 is determined by a difference ΔV FD between the reset voltage V RD applied to the reset drain 6 and a potential Ψ OG under the output gate 3 applied with the output gate voltage V OG . ΔV FD = | V RD - Ψ OG |. The value of ΔV FD is required to be not less than a certain constant value in order to ensure a required dynamic range. In the case of a buried channel, a gate voltage and a buried channel potential have a relation as shown in Figure 2. Namely, as seen from Figure 2, the buried channel potential Ψ G under the gate electrode is considerably higher than the gate electrode voltage V G . On the other hand, in order to ensure that the signal charge is smoothly transferred from a region under the transfer electrodes 2a through a region under the output gate electrode 3, the potential of the region under the output gate 3 is required to be deeper than the potential when transfer electrode 2a is at the low level (Ψ G = 7V). In ordinary cases, therefore, the output gate is applied with the output gate voltage of V OG = 3V, so that the potential of the region under the output gate 3 is brought into Ψ OG = 9.5V. Accordingly, in order to ensure the dynamic range of ΔV FD = 2.5V, the reset voltage V RD must be set to as a high voltage as 12V, as seen from Figure 2. If it is set that V RD = 12V, the channel potential Ψ RH when the reset pulse  R is at the high level is at least required to be higher than V RD (namely, higher than the point C in Figure 2). Therefore, the high level of the reset pulse  R is required to have as a high potential as 6.5V. In comparison with the above mentioned voltage condition, most of ordinary systems are of a 5V voltage supply type, and therefore, the reset voltage V RD is obtained by pumping up the voltage supply voltage to 12V. The reset pulse  R is obtained by a DC clamp circuit using a diode D as shown in Figure 3A. This clamp circuit operates to clamp a low level of an input pulse  R1 to a voltage V OFF determined by a voltage divider formed of resistors R₁ and R₂. Precisely, as seen from Figure 3B which is a timing chart illustrating an operation of the clamp circuit shown in Figure 3A, since the low level of the input pulse  R1 becomes lower than V OFF by a forward direction voltage drop of the diode D, the low level of the reset pulse  R is level-shifted to (V OFF - V F ) and the high level of the reset pulse  R is level-shifted to (5 + V OFF - V F ) However, the potential ψ G of the buried channel in relation to the gate voltage V G ordinarily has a manufacture dispersion or variation of ±1.5V. Therefore, the high level voltage of the reset pulse  R is required to be capable of being changed within a range from a point F to a point F in Figure 2, namely in the range of 4.5V to 8.0V. This means that the voltage V OFF in the DC clamp circuit shown in Figure 3A is required to be modified in order to compensate the manufacture dispersion or variation. For this purpose, it becomes necessary to adjust the resistance of the resistor R₁ or R₂ in the conventional circuit, which needs a very complicated adjustment. Referring to Figure 4, there is shown a circuit diagram of a first embodiment of the charge transfer device in accordance with the present invention. In Figure 4, elements corresponding to those shown in Figure 1 are given the same Reference Numerals, and explanation thereof will be omitted. The shown charge transfer device has a Ψ RH detection circuit 10 for detecting a potential Ψ RH of a channel under a reset gate 5 when the reset pulse  R is at a high level, and a clamp circuit 11 including a comparator 14, a diode D₁ having an anode connected to an output of the comparator 14, and a capacitor C₁ having one end connected to a cathode of the diode D1. The clamp circuit 11 compares a channel potential Ψ RH with a reset voltage V RD so as to automatically control a high level of the reset pulse V RD for the purpose of realizing a relation of Ψ RH = V RD . The shown charge transfer device also includes a  R peak hold circuit 12 composed of a diode D2 having an anode connected to the cathode of the diode D1 and a capacitor C2 having one end connected to an anode of the diode D2 and the other connected to ground. The  R peak hold circuit 12 operates to hold a high level of the reset pulse  R . Reference Numeral 13 designates an output circuit of a charge transfer device to be properly operated. The Ψ RH detection circuit 10 includes a MOS transistor composed of a source region 41 and a drain region 61 formed in the p-type substrate 1, and an n-type diffusion region 7 formed between the source region 41 and the drain region 61. The insulating layer 2 covers the source region 41, the n-type diffusion region 7 and the drain region 61 formed in the p-type substrate 1. A gate electrode 51 is formed on the insulating layer 2 above the n-type diffusion region 7 formed between the source region 41 and the drain region 61. The MOS transistor of the Ψ RH detection circuit 10 is a dummy transistor having the same characteristics in size, in voltage gain, in threshold and in others, as those of a MOS transistor (the reset transistor) formed of the floating diffusion 4, the reset gate 5 and the reset drain 6 in the charge transfer device output circuit 13. The drain 61 of the dummy transistor is connected to a high voltage V DD which is not less than the reset voltage V RD . On the other hand, the source 41 is grounded through a resistor R having a resistance which is several times of an on-resistance of the dummy transistor. The gate electrode 51 is connected to the cathode of the diode D2 of the  R peak hold circuit 12. An operation of the Ψ RH detection circuit 10 will be operated with reference to Figure 5 illustrating the potential well formed in the dummy transistor of the ψ RH detection circuit 10. Neglecting the forward direction voltage drop V F of the diode D₂, the high level of the reset pulse  R is outputted as an output voltage V₂ of the  R peak hold circuit 12 and applied to the gate 51. Therefore, the potential of a channel under the gate 51 becomes the same as the potential of the channel under the reset gate 5 when the reset pulse  R is at the high level. Under this situation, a source potential V₃ of the dummy transistor becomes equal to the potential ψ RH of the channel under the gate 51, as shown in Figure 5. The reason for this that electrons flows into the source 41 through the resistor R, but only a portion of the electrons flowed into the source exceeding the channel potential ψ RH under the gate electrode 51 is absorbed into the drain 61 applied with the voltage V DD . Therefore, the channel potential ψ RH can be detected in the form of the source voltage V₃ (V₃ = ψ RH ), and the detected voltage is compared with the reset voltage V RD of the charge transfer device output circuit 13 by the comparator 14 of the clamp circuit 11. Now, an operation of the clamp circuit 11 will be explained with reference to Figure 6. Assuming that V RD > V₃ at a time t₁, an output voltage V₄ of the comparator 14 rises. As shown in Figure 6, the rise of the output voltage V₄ of the comparator 14 causes to raise a DC component of an output of V₁ of the clamp circuit 11 which is a level shifted output of an input pulse  R1 . The output of V₁ of the clamp circuit 11 is applied to the reset gate 5 as the reset pulse, and a peak value of the output V₁ of the clamp circuit 11 is held in the  R peak hold circuit 12. Actually, the output voltage V₂ of the  R peak hold circuit 12 is lower than the peak value of the clamp circuit output V₁ by the forward direction voltage drop V F of the diode D₂. Therefore, the rise of the output voltage V₄ of the comparator 14 raises the output voltage V₂ of the  R peak hold circuit 12. The rise of the output voltage V₂ of the  R peak hold circuit 12 causes to raise the output voltage V₃ of the ψ RH detection circuit 10. Finally, the above mentioned feedback loop operation is repeated until it becomes V₃ = V RD . At a time t₂ when it becomes V₃ = V RD , the high level of the reset pulse  R is higher than a required minimum voltage by the forward direction voltage drop V F of the diode D₂. Since this forward direction voltage V F of the diode D₂ exists as a voltage margin, it is preferable. Thus, an ideal high level of the reset pulse  R can be set. As seen from the above, the first embodiment shown in Figure 4 operates to automatically adjust the reset pulse  R to the effect that the potential Ψ RH of the channel under the reset gate 5 is ceaselessly consistent with the reset voltage V RD (or slightly deeper than V RD ). Therefore, it is possible to avoid the disadvantage in which the channel potential Ψ RH varies in relation to the same reset pulse  R . In addition, it is also possible to avoid a troublesome or complicated procedure of a resistance adjustment for the level adjustment of the reset pulse  R . Turning to Figure 7, there is shown a circuit diagram of a second embodiment of the charge transfer device in accordance with the present invention. In Figure 7, elements corresponding to those shown in Figure 4 are given the same Reference Numerals, and a detail explanation thereof will be omitted. The second embodiment of the charge transfer device in accordance with the present invention includes the Ψ RH detection circuit 10 for detecting the potential Ψ RH of the channel under the reset gate 5 when the reset pulse  R is at the high level, the  R peak hold circuit 12 for holding the peak level of the reset pulse  R , and an output circuit 13 of the charge transfer device, similarly to the first embodiment. However, the second embodiment does not include the clamp circuit 12 provided in the first embodiment. The second embodiment is characterized in that the high level and the low level of the reset pulse  R are fixed, and the source 41 of the dummy transistor is directly connected to the reset drain 6 of the reset transistor and also grounded through a capacitor C₃. Therefore, the second embodiment does not control the high level of the reset pulse  R . As a substitution, the second embodiment is configured to cause the drain voltage V RD to follow the potential ψ RH of the channel under the reset gate when the fixed high level of the reset pulse  R is applied. Now, an operation of the second embodiment will be explained. Assuming that the reset pulse  R is supplied from an external device, the  R peak hold circuit 12 holds a high level of the reset pulse  R , and outputs an output voltage V₁₂, which is consistent with the high level of the reset pulse  R , if it is assumed that the forward direction voltage drop of the diode D₂ is zero. The output voltage V₁₂ is applied to the gate 51 of the dummy transistor. As a result, the channel potential of the dummy transistor becomes equal to the channel potential ψ RH of the reset transistor when the reset pulse  R is at the high level, similarly to the first embodiment. Therefore, this channel potential Ψ RH is outputted from the dummy transistor in the form of the source voltage V₁₁ of the dummy transistor and applied to the reset drain 6 of the reset transistor. With the above mentioned arrangement, the channel potential Ψ RH at the time of resetting can be made consistent with the potential of the reset drain. Accordingly, it is possible to avoid a troublesome level adjustment of the reset pulse  R . As seen from the above, the second embodiment has a circuit construction greatly simpler than that of the first embodiment. The above mentioned embodiments have been a buried channel type charge transfer device. However, the present invention can be applied to a surface channel type charge transfer device. In addition, even if the conduction type of the respective regions in the charge transfer devices can also be inverted, the present invention can also be applied. In the second embodiment, a buffer can be inserted between the source 41 of the dummy transistor and the reset drain of the reset transistor. In this modification, it is possible to suppress a potential variation occurring at the time of the resetting. As seen from the above, the charge transfer circuit in accordance with the present invention is characterized in that the potential of the channel under the reset gate is detected so that a minimum reset pulse voltage or reset drain voltage required for completing the resetting of the reset transistor is automatically applied to the reset gate or the reset drain. With the feature, the variation of the channel potential under the reset gate caused by the manufacture variation can be compensated, and therefore, the troublesome voltage adjustment procedure for the reset pulse can be omitted. In addition, since the channel potential and the reset drain voltage can be made substantially equal, a voltage operation margin of the device itself can be consequentially enlarged. The invention has thus been shown and described with reference to the specific embodiments. However, it should be noted that the present invention is in no way limited to the details of the illustrated structures but changes and modifications may be made within the scope of the appended claims.

Claims: A charge transfer device comprising: a charge transfer section having a charge transfer region formed in a semiconductor substrate (1) and transfer electrodes (2a, 2b, 2c) formed on said semiconductor substrate (1); a reset transistor (4, 5, 6) having a floating diffusion region (4) formed in said semiconductor substrate (1) for receiving an electric charge transferred from said charge transfer section, a reset drain (6) applied with a reset voltage (V RD ), and a reset gate (5) formed above a channel (7) between said floating diffusion region (4) and said reset drain (6), said reset gate (5) being applied with a reset pulse ( R ; V₁); and potential detection means (10) for detecting a potential of a channel of said reset transistor (4, 5, 6) when said reset transistor is in a resetting operation; characterized by voltage following means (11) for causing said potential of said channel (7) of said reset transistor to follow said reset voltage (V RD ) when said reset transistor is in said resetting operation. A charge transfer device claimed in Claim 1 further including a peak hold circuit (12) connected with its input to said reset gate (5) of said reset transistor for hold a peak level of said reset voltage and wherein said potential detection means (10) includes a dummy transistor having a drain (61) connected to receive a voltage (V DD ) having an absolute value larger than that of said reset voltage, a source (41) grounded through a resistor (R) having a resistance which is considerably larger than an on-resistance of said dummy transistor itself, and a gate electrode (51) connected to an output of said peak hold circuit (12), said dummy transistor having the same characteristics as that of said reset transistor. A charge transfer device claimed in Claim 2 wherein said peak hold circuit (12) includes a diode (D₂) having an anode connected to said reset gate (5) of said reset transistor and a cathode connected to said gate (51) of said dummy transistor, and a capacitor (C₂) having one end connected to said cathode of said diode and the other end connected to ground. A charge transfer device claimed in Claim 1 further including a clamp circuit (11) having a comparator (14) having a first input connected to said drain (41) of said dummy transistor and a second input connected to said reset drain (6) of said reset transistor, a second diode (D₁) having an anode connected to an output of said comparator (14) and a cathode connected to said reset gate (5) of said reset transistor. A charge transfer device claimed in Claim 1 wherein said voltage following means operates to make the potential of the channel (7) of said reset transistor when said reset transistor is in the resetting operation, consistent with said reset voltage (V RD ). A charge transfer device comprising: a charge transfer section having a charge transfer region formed in a semiconductor substrate (1) and transfer electrodes (2a, 2b, 2c) formed on said semiconductor substrate (1); a reset transistor having a floating diffusion region (4) formed in said semiconductor substrate (1) for receiving an electric charge transferred from said charge transfer section, a reset drain (6) applied with a reset voltage (V₁₁), and a reset gate (5) formed above a channel between said floating diffusion region (4) and said reset drain (6), said reset gate (5) being applied with a reset pulse ( R ); potential detection means (10) for detecting a potential of a channel of said reset transistor when said reset transistor is in a resetting operation; voltage following means for causing said reset voltage (V₁₁) to follow the voltage detected by said potential detection means (10) when said reset transistor is in said resetting operation; characterized by further including a peak hold circuit (12) connected to said reset gate (5) of said reset transistor for hold a peak level of said reset voltage and wherein said potential detection means (10) includes a dummy transistor having a drain (61) connected to receive a voltage having an absolute value larger than that of said reset voltage, a source (41) grounded through a resistor (R) having a resistance which is considerably larger than an on-resistance of said dummy transistor itself, and a gate electrode (51) connected to an output of said peak hold circuit (12), said dummy transistor has the same characteristics as that of said reset transistor, said drain (41) of said dummy transistor being directly connected to said reset drain (6) of said reset transistor. A charge transfer device claimed in Claim 6 wherein said peak hold circuit (12) includes a diode (D₂) having an anode connected to said reset gate (5) of said reset transistor and a cathode connected to said gate (51) of said dummy transistor, and a capacitor (C₂) having one end connected to said cathode of said diode and the other end connected to ground. A charge transfer device claimed in Claim 6 wherein said voltage following means operates to make said reset voltage when said reset transistor is in the resetting operation, consistent with the voltage detected by said potential detection means.

Inventors: MIWADA KAZUO C O NEC CORPORATI, MIWADA, KAZUO, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: G11C19
IPC codes: H01L21, H01L29, G11C19, G11C27