Avalanche photodiode having guard ring and method of manufacturing the same

Abstract: For providing an avalanche photodiode having a good guard ring effect and a high speed response, a semiconductor body is prepared, which includes a window layer (26) of n-type InP epitaxially grown on an avalanche multiplication layer (25) of n⁺-type InP. The window layer is selectively removed so as to expose the avalanche multiplication layer, thereby providing a recessed portion (36). After a p-type impurity is selectively introduced into the window layer (26) to form a guard ring (28) therein, a p-type impurity is selectively introduced into both the exposed avalanche multiplication layer (25) and the guard ring (28) to provide a PN junction (35) therein.

Description: This invention relates to an avalanche photodiode having a satisfactory guard ring effect and a high speed response, and a method of making the same. Nowadays, III-V avalanche photodiodes (abbreviated as APD) have been widely used as semiconductor light receiving devices for high speed optical communication in a long distance. The photodiode is responsive to light in a wavelength (1 to 1.6 µm) in which a transmission loss of an optical fiber is low. In the III-V avalanche photodiode (APD), a dark current flowing through an InGaAs layer is abruptly increased by a tunnelling current, when a high electric field is applied thereto. Usually, to avoid this, an InP layer having a wide band gap, in which a tunnelling current is rarely generated, is used as an avalanche region; and the InGaAs layer of a low carrier concentration (low impurity concentration) is used, so that a high electric field may not be applied to the InGaAs layer [SAM(Separated Absorption and Multiplication)-APD]. Fig. 6 shows a conventional SAM-APD, in which an n-type InP buffer layer 2, an n - -type InGaAs light absorption layer 3, an n-type InGaAsP intermediate layer 4, an n + -type avalanche InP multiplication layer 5, and an n-type InP window layer 6 are epitaxially grown in sequence on an n + -type InP substrate 1. A p + -type diffusion layer 7 and a p-type guard ring 8 are formed in the window layer 6 by selective diffusion or ion implantation techniques. An anti-reflection film 9 and a P-side electrode 10 are provided on top of the upper surface of the substrate 1, and an N-side electrode 11 is formed on the lower surface of the substrate 1. In the SAM-APD thus formed, carriers generated by optical absorption in the n - -type InGaAs layer 3 move by drift to the n + -type InP layer 5 to perform the avalanche multiplication. Therefore, the tunnel current is suppressed, whereby the APD with the low dark current is obtained. However, since a heterojunction is formed between the InGaAs layer 3 and the InP layer 5, holes generated by the light absorption are accumulated in the barrier of a valence band existing on the heterojunction, resulting in a low response. To overcome the disadvantage, the intermediate layer 4 is interposed between the n - -type InGaAs layer 3 and the n + -type InP layer 5, thereby reducing the barrier of the valence band. The composition of the intermediate layer 4 is given to have an intermediate energy gap between those of the n - -type InGaAs layer 3 and the n + -type InP layer 5. For realizing an APD of a low dark current and a high avalanche multiplication factor, it is necessary that uniform avalanche multiplication is performed over the entire light receiving surface, and that no voltage breakdown occurs in the region other than the light receiving region. Since the electric field tends to concentrate particularly in a curved portion 12 of a PN junction 15 between the n-type InP layer 6 and the p + -type InP layer 7, the voltage breakdown may occur locally (called edge breakdown). To prevent the local voltage breakdown, an APD has been proposed which includes a guard ring 8 at the peripheral portion of the PN junction 15. In general, the edge breakdown does not occur more easily in a graded junction, in which the impurity concentration of a semiconductor region near the PN junction varies linearly, than in an abrupt step junction in which the impurity concentration varies in a stepping manner. Therefore, usually, the PN junction in the light receiving portion is provided by the abrupt step junction, and that in the guard ring portion is given by the graded junction. In the conventional APD as described above, the n-type InP window layer 6 of the low carrier concentration is epitaxially grown on the n + -type InP avalanche multiplication layer 5 of the high carrier concentration. The PN junction between the layer 6 and the guard ring 8 is formed by implanting Be ions or the like into the layer 6 and annealing the implanted region at a high temperature. The PN junction 15 in the light receiving portion is formed by selective diffusion techniques, using Cd 3 P 2 as a diffusion source. In order to obtain the guard ring effect in the conventional APD, it is necessary that the PN junction of the light receiving portion be formed at a shallow position of the n-type InP window layer 6, and the PN junction of the guard ring 8 be formed at a position deeper than the curved portion of the PN junction of the light receiving portion. On the other hand, in order to obtain a high response, it is necessary that the carrier concentration of the InP avalanche multiplication layer 5 is increased to reduce the avalanche build-up time, and the electric field applied to the heterojunctions 13 and 14 is increased to prevent the storage of holes. For this reason, the PN junction of the light receiving portion is formed in a portion which enables the guard ring effect to be obtained, and as deep as possible near the n + -type InP avalanche multiplication layer 5. The thickness of the n + -type InP avalanche multiplication layer 5 is determined in accordance with the controllability and uniformity of the crystal growth, and the depth of the PN junction 15 formed in the n-type InP window layer 6 is determined by the controllability of the diffusion. Therefore, for providing an APD having a satisfactory guard ring effect and a high speed response, controllability and reproducibility of the thickness of the layer 5 and the depth of the PN junction 15 become important. At any rate, the manufacturing process is complicated and the manufacturing yield is apt to become low. As described above, in the conventional APD, in order to obtain the satisfactory guard ring effect, the depth of the guard ring must be greater than that of the flat portion of the PN junction in the n-type InP window layer. Moreover, for improving the high speed response, the PN junction in the n-type InP window layer must be formed as deep as possible near the n + -type InP avalanche multiplication layer. The depth of the PN junction and the thickness of the n + -InP avalanche multiplication layer adapted to the above conditions cannot be controlled or reproduced satisfactorily, resulting in low response and manufacturing yield. EP-A-0 343 970 shows a planar photodiode with a guard ring in a multiplication layer, to improve bandwidth and sensitivity. JP-A-61-191082 shows a recessed portion in a low impurity concentration layer in a photodiode. A guard ring is shown spaced apart from a multiplication layer. An object of the present invention is to provide an avalanche photodiode having a satisfactory guard ring effect and a high speed response. Another object of the present invention is to provide a method of making the avalanche photodiode at a high yield. According to an aspect of the present invention, there is provided an avalanche photodiode comprising: a semiconductor body including a window layer of a first conductivity type provided on an avalanche multiplication layer of the first conductivity type; a recessed portion formed in said window layer having a flat bottom and sloped sidewalls; a guard ring of a second conductivity type provided in said window layer and bordering onto said sloped sidewalls, said guard ring extending into said multiplication layer and including two regions, the first region bordering onto and extending along the whole length of said sloped sidewalls and having an impurity concentration greater than that of said second region; and a semiconductor region of the second conductivity type formed below said flat bottom of said recess and extending therefrom into said avalanche multiplication layer to define a PN junction therein, wherein the lowest point of said guard ring is formed at a greater depth than said PN junction, and wherein said semiconductor region is in contact with said first region. According to another aspect of the present invention, there is provided a method of manufacturing the avalanche photodiode defined above, as given in claim 6. The novel and distinctive features of the invention are set forth in the claims appended to the present application. The invention itself, however, together with further objects and advantages thereof may best be understood by reference to the following description and accompanying drawings in which: Fig. 1 is a cross sectional view showing an avalanche photodiode according to a first embodiment of the present invention; Figs. 2A to 2E are cross sectional views showing a process for making the avalanche photodiode of Fig. 1; Fig. 3 is a diagram schematically showing field strength of semiconductor layers in the avalanche photodiode shown in Fig. 1 and a conventional avalanche photodiode; Fig. 4 is a cross sectional view showing an avalanche photodiode according to a second embodiment of the present invention; Fig. 5 is a cross sectional view showing an avalanche photodiode according to a third embodiment of the present invention; and Fig. 6 is a cross sectional view showing a conventional avalanche photodiode. Embodiments of the present invention will now be described with reference to the accompanying drawings. Fig. 1 is a cross sectional view showing an avalanche photodiode according to a first embodiment of the present invention. An n-type InP buffer layer 22, an n - -type InGaAs light absorption layer 23, an n-type InGaAsP intermediate layer 24, an n + -type InP avalanche multiplication layer 25 and an n-type InP window layer 26 are provided in sequence on an n + -type InP substrate 21 by epitaxial growth. A recessed portion 36 having a sloped sidewall is formed in the window layer 26 to expose the surface of the avalanche multiplication layer 25. A p + -type InP layer 27 is formed in the exposed n + -type InP avalanche multiplication layer 25 to provide a PN junction 35 which serves as a light receiving portion. A p-type guard ring 28 is formed in the n-type InP window layer 26, and includes a region 281 and a region 282 defined by a dotted line 32. The region 282 has an impurity concentration greater than that of the region 281. The high impurity concentration region 282 is formed by a p-type impurity, which is introduced into the guard ring 28 during the process of forming the p + -type InP layer 27. An annular P-side electrode 30 is provided on the high impurity concentration region 282 of the p-type guard ring 28. An anti-reflection film 29 is formed on the upper surface of the semiconductor body having the light receiving portion. An N-side electrode 31 is formed on the lower surface of the semiconductor substrate 21. A method of making the avalanche photodiode of the above embodiment will now be described with reference to Figs. 2A to 2E. Referring to Fig. 2A, first, an n-type InP buffer layer 22, an n - -type InGaAs optical absorption layer 23, an n-type InGaAsP intermediate layer 24, an n + -type InP avalanche multiplication layer 25 and an n-type InP window layer 26 are grown in sequence on an n + -type InP substrate 21 by vapor phase epitaxy (VPE) techniques. Then, SiO 2 or the like is deposited on the window layer 26 to form an SiO 2 film 37, a part of which is removed by photoetching techniques, thereby forming a circular opening 38 therein. Using the SiO 2 film as a mask, the n-type InP window layer 26 is selectively removed by an etchant of Br-CH 3 OH or the like, thereby forming a recessed portion 36 having a sloped sidewall and a flat bottom to expose a portion of the surface of the avalanche multiplication layer 25. Thereafter, the SiO2 mask 37 is removed (Fig. 2B). Next, referring to Fig. 2C, an SiO 2 film 39 and a resist film 40 is formed in sequence on the window layer 26 and the exposed portion of the avalanche multiplication layer 25. Thereafter, these films are patterned to expose the window layer 26 near the recessed portion 36. A p-type impurity such as beryllium (Be) is ion implanted into the layer 26 at an acceleration voltage of 200kV and a dosage of about 1 x 10 13 cm -2 , using the patterned SiO 2 film 39 and the resist film 40 as a mask. Next, as shown in Fig. 2D, after the resist film 40 and the SiO 2 film 39 are removed, the semiconductor body is annealed in a phosphine atmosphere (10000ppm) at 700°C for 10 minutes, thereby forming a p-type guard ring 28 in the window layer 26. Thereafter, as shown in Fig. 2E, an SiNx film 41 is formed on the substrate surface, and selectively etched so as to expose the recessed portion 36. Then, a p-type impurity such as cadmium (Cd) is selectively diffused into the window layer 26, using the SiN x film 41 as the mask. In the diffusion step, the p-type impurity is diffused into the n + -type InP avalanche multiplication layer 25 as indicated by a dotted line 32, thereby forming a p + -type InP layer 27. At the same time, the region 282 having an impurity concentration higher than that of the region 281 is formed in the p-type guard ring 28 as defined by the dotted line 32. After forming an SiN x film serving as an anti-reflection film 29 as shown in Fig. 1, the SiN x film is selectively removed to expose a part of the region 282 of the p-type guard ring 28. Electrode metal is evaporated on the substrate surface by vacuum evaporation techniques, and patterned by photoengraving techniques to remove an unmasked portion of the electrode metal. As a result, a P-side electrode 30 is provided on the region 282 of the p-type guard ring 28. Subsequently, the lower surface of the InP substrate 21 is polished, and an N-side electrode 31 is formed thereon by vacuum evaporation techniques. Finally, for providing ohmic contact electrodes, heat treatment is performed. In this way, an avalanche photodiode is completed. Fig. 3 schematically shows electric field distribution of the n-type layers under the flat PN junction of the light receiving portion of the present invention. Fig. 3 also shows electric field distribution of the avalanche photodiode shown in Fig. 6 for comparison. The abscissa x represents a distance (µm) in the direction perpendicular to the substrate surface. A reference point (x = 0) is given by the PN junction of the avalanche photodiode according to the present invention. The arrangements of the semiconductor layers corresponding to the distance x are shown under the abscissa and in parallel therewith. The arrangements A and B represent the present invention and the conventional example, respectively. The ordinate represents intensity (V/cm) of the electric field. Polygonal lines A and B show a relationship between the distance x and the intensity of the electric field in the present invention and in the conventional device, respectively. As shown in Fig. 3, since the PN junction of the light receiving portion in the conventional device is formed in the n-type InP window layer, the electric field applied to the heterojunctions is lowered. Moreover, since the n-type InP window layer has a low impurity concentration in general, the avalanche buildup time therein tends to become long. In contrast, in the avalanche photodiode according to the present invention, since the PN junction is formed in the n + -InP avalanche multiplication layer, not in the n-type InP window layer, the avalanche build-up time will be reduced. Further, since the electric field applied to the heterojunctions is increased, it will be possible to prevent holes from accumulating at the heterojunctions. For these reasons, a high speed response can be obtained. Regarding the curved portion (given by the dotted line 32) of the PN junction in which edge breakdown easily occurs, since the surface in the recessed portion of the window layer is subjected to the diffusion or ion implantation, the curvature of the curved portion can be increased (the radius of curvature can be increased), even if the avalanche multiplication layer is shallowly doped with the impurity. Thus, the edge breakdown will be suppressed. Moreover, the impurity is introduced into the recessed portion through its periphery and side wall to form the curved portion of the PN junction, thereby providing the guard ring. Therefore, the curved portion having the small curvature can be formed at the position deeper than the flat portion of the PN junction. For these reasons, the satisfactory guard ring effect will be obtained, and the edge breakdown will be suppressed. More specifically, the impurity (Be) is selectively introduced into the recessed portion 36 of the window layer 26 through its periphery having the side wall (Figs. 2D and 2E), thereby forming the guard ring 28 in the window layer 26. Subsequently, the impurity (Cd) is selectively introduced into both the guard ring 28 and the avalanche multiplication layer 25 to provide the PN junction 35 in the light receiving portion. Therefore, the edge breakdown can be easily suppressed, and the satisfactory guard ring effect can be obtained. Further, since the thickness of the n + -type InP avalanche multiplication layer 25 is controlled by the selective diffusion process or ion implantation method, the satisfactory controllability and reproducibility of the thickness will be obtained. Moreover, the avalanche photodiode can be manufactured easily at the high yield. Fig. 4 is a cross sectional view showing a second embodiment of the present invention. While in the first embodiment shown in Fig. 1 the n-type InP window layer 26 is etched to form the recessed portion so as to expose the layer 25, an n-type InP window layer 46 in the second embodiment is etched to form a recessed portion therein. That is, the window layer 46 is selectively removed so as not to expose the avalanche multication layer 25. Accordingly, the controllability of diffusion of the p + -type InP layer 27 will be improved. Fig. 5 is a cross sectional view showing a third embodiment of the present invention. In this embodiment, an n-type InGaAsP layer 57 serving as a stopper in the step of selectively etching the window layer is interposed between an n-type InP window 56 and an n + -type InP avalanche multiplication layer 55. When the window layer is etched by hydrochloric acid, the InGaAsP layer stops progress of the etching, thereby improving the controllability of etching. Although the above embodiments relate to a semiconductor device formed of InGaAsP/InP system compound semiconductor, the present invention can be applied to semiconductor devices formed of AℓGaAsSb, GaAs and the like. In addition, the p-type layers and the n-type layers of the present invention may be replaced by n-type layers and p-type layers, respectively. Further, the PN junction in the light receiving portion, which is formed by diffusion in the above embodiments, can be formed by the ion implantation of zinc (Zn), magnesium (Mg), or the like. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: An avalanche photodiode comprising: a semiconductor body including a window layer (26) of a first conductivity type provided on an avalanche multiplication layer (25) of the first conductivity type; a recessed portion (36) formed in said window layer (26) having a flat bottom and sloped sidewalls; a guard ring (28) of a second conductivity type provided in said window layer (26) and bordering onto said sloped sidewalls, said guard ring extending into said multiplication layer and including two regions (281, 282), the first region (282) bordering onto and extending along the whole length of said sloped sidewalls and having an impurity concentration greater than that of said second region (281); and a semiconductor region (27) of the second conductivity type formed below said flat bottom of said recess and extending therefrom into said avalanche multiplication layer (25) to define a PN junction (35) therein, wherein the lowest point of said guard ring is formed at a greater depth than said PN junction (35), and wherein said semiconductor region (27) is in contact with said first region (282). The avalanche photodiode according to Claim 1, wherein the recessed portion (36) is formed in the window layer (26) to expose the avalanche multiplication layer (25). The avalanche photodiode according to Claim 1 or 2, wherein a P-side electrode (30) is in contact with the first region (282). The avalanche photodiode according to Claim 1, wherein a stopper layer (57) is provided between the avalanche multiplication layer (55) and the window layer (56). The avalanche photodiode according to Claim 4, wherein the recessed portion (36) is formed in the window layer (56) to expose the stopper layer (57). A method of making an avalanche photodiode according to Claim 1, comprising the steps of: preparing a semiconductor body including an avalanche multiplication layer (25) of a first conductivity type and a window layer (26) of the first conductivity type successively epitaxially grown; selectively removing said window layer (26) to provide a recessed portion of (36) therein having sloped sidewalls and a flat bottom; selectively introducing a first dopant impurity of a second conductivity type through the sloped sidewall of said recessed portion (36) to form a guard ring (28) of the second conductivity type in said window layer and extending into said avalanche multiplication layer; and selectively introducing a second dopant impurity of the second conductivity type into the sloped sidewalls and flat bottom of said recess, thereby forming regions (282) in said guard rings (28) having an impurity concentration greater than that of the remainder (281) of said guard rings, and forming a semiconductor region (27) extending from said flat bottom of said recess into said avalanche multiplication layer (25) to define a PN junction (35) therein, the lowest point of said guard ring being formed at a greater depth than said PN junction (35).

Inventors: OKAZAKI HARUHIKO, OKAZAKI, HARUHIKO, OKAZAKI, HARUHIKO, C/O INTELLECTUAL PROP. DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: H01L31
IPC codes: H01L31