Digital pulse processing device

Abstract: A digital pulse processing device is capable of selecting precision. The digital pulse processing device includes a counter group for counting pulses output from a pulse output device, the counter group having a plurality of counters 110 and 111 that can be separated from and coupled with each other, a mode control circuit 129 for instructing separation and coupling of the counters 110 and 111, and a control circuit 116 for separating and coupling the counters 110 and 111 in accordance with the instruction of the mode control circuit 129. An overflow condition of the timer 119 is detected using an overflow flag. Detection of an overflow is conducted by setting the flag when an overflow condition has occurred twice or more. The flag is reset by rewriting the state of the flag by a software. An overflow condition which has occurred for the first time is detected in the conventional manner and is treated as carry or borrow. A register 128 is provided to hold the value of the timer 119 when a microcomputer reads in the counter 111. In this way, even when ΔA(i) = 0, speed detection operation can be executed using the value of the counter 111 obtained synchronously with the counting of the counter 110.

Description: The present invention relates to a digital pulse processing device and to a microcomputer comprising such a device. The device is in particular suitable for preprocessing a detection signal representing the speed of a moving or rotating body before it is supplied to a digital motor speed control device. The pulse processing function of conventional speed detection devices is disclosed in, for example, Japanese Patent Laid-open JP-A-59-100866. This pulse processing function of the speed detection device includes a first counter A for counting a pulse train output from a pulse generator, a second counter B for counting clock pulses having a fixed higher frequency than the pulse train, and a latch for storing the count of the second counter B. This speed detection device is implemented by a hardware designed to store the counted value of the clock pulses of the second counter B each time a pulse is output from the pulse generator. In the above-described speed detecting device, counting of the pulses from the pulse generator and counting of clock pulses are synchronized so as to achieve accurate speed detection. Speed detection operation is to obtain a speed detection value Nt by executing the following expression using the pulse counted value A (i) of the first counter A, a latched value B (i) of the second counter B, the values A and B being obtained at the present reading in of a microcomputer, and the values A (i-1) and B (i-1) obtained by the previous reading in of the microcomputer: Nt = K · ΔA (i) / ΔB (i) = K · {A (i) - A (i-1)} / {B (i) - B (i-1)} where K is the constant, ΔA is a change in the first counter A, and ΔB is a change in the second counter B. When the motor is rotating at a low speed, the pulse width of the pulses output from the pulse generator is large, and the counted value of the pulses may not change in the microcomputer's reading-in intervals which is generally several msec. At that time, ΔA (i) =0, and ΔB (i) =1, and speed detection operation is made impossible. To overcome this problem, in the aforementioned conventional technique, a RD (read) signal is output from the microcomputer by the software. When the speed detecting device receives this RD signal, it forcibly stores the counted value of the clock pulses in the latch asynchronously with the counting of the pulse output device. In that case, speed detection operation is executed using the previously obtained ΔA (i) and ΔB (i) obtained by subtracting the previously obtained clock pulses counted value from the clock pulses counted values latched by the RD signal. Regarding a subsequent reading-in of the microcomputer, if no pulse is output from the pulse output device, ΔA (i) is that used in the previous operation, and ΔB (i) is the value obtained by adding to the previous ΔB (i) the value obtained by subtracting the previously read in clock pulse counted value from the clock pulse counted value latched by the RD signal. Therefore, ΔB (i) is the value obtained between the last pulse output from the pulse generator and the present reading-in of the microcomputer. In the aforementioned conventional technique, when ΔA (i) = 0, the speed detection operation requires complicating processings, such as branch processing, output of a RD signal and cumulative addition of ΔB (i), which increase the burden on the software. Furthermore, no consideration is given to the precision of the latch for storing the counted values A (i) and B (i) of the counter for counting the pulses of the pulse generator and the counter for counting the clock pulses. That is, since the number of bits for the latch is fixed, precision is also fixed. Consequently, a precision more than the required one is obtained for a certain application, while an insufficient precision is obtained for another application. As a result, the conventional latching is not versatile, and pulse processing cannot be achieved over a wide range of precision. Furthermore, no consideration is given to the overflow of the counter B (i) for counting the clock pulses. That is, although ΔB (i) can be obtained when an overflow condition occurs in the counter B (i) once, if an overflow condition occurs more than once, it is impossible to obtain an accurate ΔB (i) because there is no function of checking the number of times the overflow condition occurs. This makes accurate speed detection operation impossible. The prepublished Article "Ein schnelles digitales Drehzahlmeßgerät, published in "messen prüfen automatisieren", October 1986, page 630 and following, discloses a detection device for the numbers of revolution of a certain machine. The device comprises two counters, one for counting a reference clock signal having a comparatively high frequency (6 MHz), the other counting pulses output by the revolving machine to be detected. When the revolution speed of the machine to be detected is very low, the two counters are cascaded so that the reference clock can be counted by these two cascaded counters. The count is then taken upon occurrence of the first signal from the machine clock. An object of the present invention is to provide a digital pulse processing device which is capable of alleviating the burden on the software by detecting the value of a timer synchronously with a microcomputer's present reading-out of data from a counter and by executing the speed detection operation by a simple process. Another object of the present invention is to provide a digital pulse processing device which has a variable-precision type pulse processing function having a counter and a latch whose precision can be varied and which is capable of providing data having a required and sufficient precision for an accurate speed detection operation conducted by a microcomputer. These objects are solved in accordance with the features of the independent claim. Dependent claims are directed on preferred embodiments of the invention. What is described is a digital pulse processing device which is capable of selecting precision. The digital pulse processing device comprises a counter group for counting pulses output from a pulse output device, the counter group having a plurality of counters that can be separated from and coupled with each other, a mode control circuit for instructing separation and coupling of the counters, and a control circuit for separating and coupling the counters in accordance with the instruction of the mode control circuit. When the counters are separated, the individual counters can be separately operated to separately process the pulses from a plurality of pulse output devices. An overflow condition of the free-run counter B, which is one of the plurality of counters, is detected using an overflow flag. Detection of an overflow is conducted by setting the flag when an overflow condition has occurred twice or more. The flag is reset by rewriting the state of the flag by a software. An overflow condition which has occurred for the first time is detected in the conventional manner and is treated as carry or borrow. A register is provided to hold the value of the counter B obtained when a microcomputer reads in the counter B. In this way, even when ΔA (i) = 0, speed detection operation can be executed using the value of the counter B obtained synchronously with the counting of the counter A. In the present invention, the counter for counting the pulses from a pulse output device is made up of a pair of counters and a coupling control circuit thereof. The counter is capable of counting up, down or counting up and down the values. Which counting method is employed is determined by a mode control register. When the two counters are coupled with each other, the coupling control circuit outputs a carry or borrow signal of one of the counters to the remaining counter as a counting up or down signal. When the two counters are separately operated, the pulses output from the pulse output device to one of the counters are supplied to that counter through the coupling control circuit. Thus, precision of the counters can be varied by checking presence or absence of a carry or borrow signal and by changing over the destination of the output pulses of the pulse output device. Furthermore, the counted value of the counter for counting clock pulses is stored in a latch corresponding to the counter by a selection circuit for selecting the latch in which the value is stored. To detect that an overflow condition of the free-run counter for counting clock pulses has occurred twice or more, a flag is set on the basis of the results of logical AND between a 1-bit latch for holding a carry obtained when an overflow occurs and a similar latch which is operated when the value of that latch is 1. The flag is reset by the software. When the flag is reset, the two latches are cleared. When ΔMA = 0 is obtained during the speed detection operation, the value of a timer obtained between the last pulse output from the pulse generator and the microcomputer's reading in of the data in the counter MB is detected. To accomplish speed detection operation using this value of the timer with the least errors when ΔMA = 0, a latch is provided to store the value of the counter MB obtained when the microcomputer reads out the data from the counter MA. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of an embodiment of a digital pulse processing device according to the present invention; Fig. 2 shows a memory configuration of a mode control register MCREG; Fig. 3 is a block diagram of an example of a circuit which implements the function of coupling counters PREG; Fig. 4 is a block diagram of an example of a circuit for detecting that an overflow condition of a timer 119 has occurred twice or more before a subsequent reading-out of a latch TREG; Fig. 5 is a block diagram of an example of a storing latch selecting unit 120 associated with a microcomputer's reading out of the value of the timer 119 which is effective for speed operation when ΔMA = 0; and Fig. 6 shows an example of a general-purpose microcomputer in which a digital pulse processing device according to the present invention is incorporated. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will now be described with reference to the accompanying drawings. Fig. 1 is a block diagram of an embodiment of a digital pulse processing device according to the present invention. A pulse processing unit 100, which has the pulse processing function according to the present invention, has the following configuration. A data bus 101 is used to transmit data between a microcomputer (not shown) and the pulse processing unit 100 having the pulse processing function according to the present invention. Clock pulses 102 are used to initiate actions within the microcomputer. They are also used to initiate actions within the pulse processing unit 100. Pulses from pulse generators are received by input terminals PE0A103, PE0B104, PE1A105, PE1B106, PE2A107, PE2B108. Input terminals PE0A103 and PE0B104 constitute channel 0, input terminals PE1A105 and PE1B106 form channel 1, and input terminals PE2A107 and PE2B108 are channel 2. There are three channels in total. The pulse signal supplied to each channel is frequency multiplied and delivered to a counter PREG as a count signal by a pulse preprocessing unit 109. Frequency multiplication is the processing in which rise and fall of an input pulse are detected and a pulse signal is generated synchronously with the detected pulse. In this frequency multiplication processing, it is therefore possible to generate a pulse signal whose cycle is a submultiple (whose frequency is a multiple) of that of the pulse signal from the pulse generator. The generated pulses are supplied to counters PREG0A110, PREG0B111, PREG1A112, PREG1B113, PREG2A114 and PREG2B115 as either an counting up or down signal. Switch over between counting up and down signals is performed in accordance with the operation mode set in a mode control register MCREG129. Counting of the counting up or down signal obtained by the pulse preprocessing unit 109 is conducted by 16-bit counters PREG. Counters PREG0A110 and PREG0B111 count pulses input to the input terminals PE0A103 and PE0B104 which constitute channel 0. The present invention is characterized in that these two counters can be selectively used separately or in a coupled state. Coupling of the counters is conducted on the data designated by the mode control register MCREG 129. Counters PREG1A112 and PREG1B113 or PREG2A114 and PREG2B115 have the same function as the counters PREG0A110 and PREG0B111, and count the pulses input to the input terminals PE1A105 and PE1B106 constituting channel 1 or the input terminals PE2A107 and PE2B108 constituting channel 2. The separate or coupled use of the counters PREG0A110 and PREG0B111 is changed over by a coupling control circuit 116. Coupling control circuits 117 and 118 have the same function as the coupling control circuit 116, and control separation and coupling of the counters PREG1A112 and PREG1B113, PREG2A114 and PREG2B115, respectively. The counted value of a timer 119 is stored in 16-bit latches. Latches TREG0A121 and TREG0B122 correspond to the counters PREG0A110 and PREG0B111. When the counters PREG0A110 and PREG0B111 are used in a coupled state, data having a double precision is obtained by the two latches TREG0A121 and TREG0B122. The latches TREG0A121 and TREG0B122 store the counted value of the timer 119 synchronously with the counting operation of the counters PREG0A110 and PREG0B111 which count a counting up or down signal output from the pulse preprocessing unit 109. Latches TREG1A123 and TREG1B124 or TREG2A125 and TREG2B126 have the same function as the latches TREG0A121 and TREG0B122, and respectively correspond to the counters PREG1A112 and PREG1B113, PREG2A114 and PREG2B115. Timer 119 counts the clock pulses 102 of a microcomputer which is not shown. The clock pulses are first divided by a value designated by the mode control register MCREG129 and then counted. A storing latch selecting unit 120 makes a selection of the latches TREG121 to 126 and thus determines the latch at which the data of the timer 119 is to be stored. The control signal sent from the pulse preprocessing unit 109 to the storing latch selecting unit 120 synchronizes counting of the pulses with latching of the timer data. This control signal is also used to indicate counting or non-counting of the counter to the storing latch selecting unit 120. The mode control register MCREG129 designates the operation mode of a pulse input unit 100. An overflow status detecting unit 127 contains a status register for memorizing that an overflow condition of the timer 119 has occurred twice or more before a subsequent reading-out of the latches TREG121 to 126. When this status register is set, disability of an accurate speed detection operation is alarmed. A timer latch 128 stores the value of the timer 119 when the microcomputer reads in the value in this latch 128. Fig. 2 shows the bit configuration of a memory in the mode control register MCREG129. This register 129 has a 16-structure. Among the 16 bits, bits 2, 1 and 0 are not used. Bits 15 to 10 are used for making selection on the input pulses: bits 11 and 10, constituting an IP0 portion 200, are used for selecting coupling or non-coupling of the counters for counting the pulses input from the channel 0, the counting method and the input terminal to be used; bits 13 and 12, constituting an IP1 portion 201, are used for selecting coupling or non-coupling of the counters for counting the pulses input from the channel 1, the counting method and the input terminal to be used; and bits 15 and 14, constituting an IP2 portion 202, are used for selecting coupling or non-coupling of the counters for counting the pulses input from the channel 2, the counting method and the input terminal to be used. Allocation of the codes for the individual channels is in common and shown in Table 1. When a combination of the upper and lower bits is 00, the counters PREGA and PREGB are not coupled but operated separately, and values are counted up in both counters. At that time, both PEA and PEB terminals are used to input pulses from the pulse output device. When a combination of the upper and lower bits is 01, the same operation is performed with the exception that values are counted down in the counters. When a combination of the upper and lower bits is 10, the counters PREGA and PREGB are coupled, and an instruction indicating counting up or down is input to the PEA terminal while pulses are input to the PEB terminal. When a combination of the upper and lower bits is 11, the counters PREGA and PREGB are coupled and two-phase pulses having a directional component are input to the PEA and PEB terminals. Therefore, counting up or down is performed in accordance with the directional component. Bits 9 to 4 are used to set the frequency multiplication factor used in the process conducted by the pulse preprocessing unit 109. That is, bits 5 and 4, constituting a MP0 portion 203, are used to set the frequency multiplication factor for the pulses input to the channel 0, bits 7 and 6, constituting a MP1 portion 204, are used to set the frequency multiplication factor for the pulses Input to the channel 1, and bits 9 and 8, constituting a MP2 portion 205, are used to set the frequency multiplication factor for the pulses input to the channel 2. Examples of the frequency multiplication factors that can be set are 1, 2 and 4, as shown in Table 2. Bit 3, constituting a TCLK portion 206, is used to set the frequency demultiplication factor. In this embodiment, 1 and 1/2 can be used as the frequency demultiplication factor, as shown in Table 3. Code allocation for TCLK Bit Frequency demultiplication factor 0 x1 1 x1/2 Fig. 3 is a block diagram of an example of a circuit configuration which implements the counters PREG coupling function. Here, coupling of the counters PREG0A110 and PREG0B111 will be described. An instruction indicating coupling or non-coupling of the counters PREG0A110 and PREG0B111 is set in the mode control register MCREG129. That instruction is converted into a control signal by a decoder 304. When the counters are coupled, a carry signal 305 or a borrow signal 306 generated as a consequence of the counting operation of the counter PREG0B111 by either a counting up or down signal 300 or 301 output from the pulse preprocessing unit 109 is used as either a counting up or down signal 307 or 308 for the counter PREG0A110. When the counters are operated separately, a counting up or down signal 302 or 303, which are output from the pulse preprocessing unit 109 to the counter PREG0A110, is supplied to the counter PREG0A110 through the coupling control circuit 116 as the counting up or down signal 307 or 308 without being changed. Coupling and separation of other counters PREG are performed in the same manner. Fig. 4 is a block diagram of an example of a detection circuit for detecting that an overflow condition of the timer 119 has occurred twice or more in the latch TREG reading-out intervals. An overflow condition of the timer 119 is detected by a 32-bit carry of the counter when the counters PREG are coupled with each other and by a bit state of bit 17 when the counters PREG are separated from each other. Regarding the latch TREGA, determination is first made whether the counters are coupled with or separated from each other from a coupling output 403, and then a one-shot overflow signal is generated by a one-shot A circuit 404. Non-updated flag 402 is set by a read-out signal 400 of the microcomputer, and reset by an update signal 401 of the corresponding latch TREGA. Therefore, when the flag A402 stored in a latch 405 by the overflow signal has a value 1, it indicates that an overflow condition has occurred after the TREG is updated. A latch 406 stores the value of the latch 405 by the overflow signal. Consequently, logical AND between the latches OVF1A405 and OVF2A406 represents generation of an overflow condition twice or more, and the status register of the overflow status detecting unit 127 thus reflects the results of this logical operation. Regarding the latch TREGB, a one-shot overflow signal is generated by a one-shot circuit B408 in accordance with the bit state of bit 17. Thereafter, substantially the same operation as that regarding the latch TREGA is conducted so that a non-updating flag 407 can be set by a reading-out signal of the microcomputer 411 and an update signal 412 of the TREGB. Generation of an overflow condition twice or more is detected by the latches OVF1B409 and OVF2B410, and the status register of the overflow status detecting unit 127 thus reflects the results of the detection. Fig. 5 is a block diagram of an example of the storing latch selecting unit 120 associated with reading-out of the value of the timer 119 by the microcomputer which is effective to operate the speed when ΔMA= 0. The basic function of the storing latch selecting unit 120 is to store the data of the timer 119 in the latch corresponding to the counter designated by the mode control register MCREG129 each time the counter counts the input pulse. That is, the storing latch selecting unit 120 opens a latch switch in response to the count synchronizing signal sent from the pulse preprocessing unit 109 to send the data of the timer 119 to an aligner which distributes the timer data between latches 1 and 2 in accordance with the data from the mode control register MCREG129. Another function of the storing latch selecting unit 120 is to reduce generation of errors when no count pulse is input in the CPU's data reading out intervals, i.e., when the motor or the like is rotating at a low speed. This function is executed by a read-out signal 501 from the CPU and a signal from the timer latch (flag) 128. In this case, the timer latch 128 has another function. That is, although the fundamental function of the timer latch 128 is to store the data of the timer 119 when the motor or the like is rotating at a low speed, the timer latch 128 also serves as a flag used to determine whether the motor or the like is rotating at a high or low speed relative to the CPU's reading-out intervals. This flag is set by the read-out signal 501 from the CPU and is reset each time the counting operation is conducted. Therefore, the flag is in a reset state when the counting operation is conducted before a CPU's subsequent reading-out while it is in a set state when no counting operation is conducted. When the flag is in a reset state, it is therefore determined that the motor or the like is rotating at a high speed. When the flag is in a set state, it is determined that the motor or the like is rotating at a low speed. In the latter case, the data on the timer 119 is transferred to the aligner synchronously with the reading-out signal of the CPU and then stored in the latch designated by the mode control register MCREG129. Thus, generation of errors is prevented during the low-speed rotation. A wait signal 502 indicates that the data stored in the latch is not defined. This wait signal 502 is output only for a period of time corresponding to several clock pulses immediately after the latch switch is operated. The CPU confirms that no wait signal 502 is output when it reads in the timer latch 128, and then obtains the value of the timer 119. In this embodiment, since the microcomputer reads out the counted value of the free-run counter for counting the clock pulses synchronously with the counting operation of the counter for counting the pulses of the pulse output device, burden on the software for the speed detection operation can be alleviated. In this embodiment, the digital pulse processing device provided separately from the CPU has been described. However, a combination of the pulse processing unit 100, serving as the digital pulse processing device according to the present invention, and a CPU 503 may be fabricated as a one-chip microcomputer (Fig. 6). As will be understood from the foregoing description, since the counters for counting the pulses from the pulse output device are coupled with or separated from each other to change the precision of the data output from the counters, counting of a wider range can be made possible. This allows pulse processing at a precision suitable to the application to be made possible. Furthermore, since an overflow condition of the free-run counter for counting the clock pulses can be detected in response to the coupling or separation of the counters for counting the pulses of the pulse output device, the operations required for speed detection can be executed accurately using the obtained data. Furthermore, since the microcomputer reads out the counted value of the free-run counter for counting the clock pulses synchronously with the counting operation of the counter for counting the pulses of the pulse output device, burden on the software for the speed detection operation can be alleviated.

Claims: A digital pulse processing device including a first counter group (110, 112, 114) including at least one counter for counting pulses (103-108) output from a pulse generator, a second counter group (111, 113, 115) including at least one counter, coupling control means (116-118) for changing over the operation of the counters of said first and second counter group between independent operation of the individual counters and coupled operation of two or more counters; a timer (119) for counting clock pulses having a higher frequency than the pulses output from said pulse generator; a latch group (122, 124, 126) including the same number of latches as that of the counters in the first and second counter group, said latch group holding a value output from said timer (119), and storing latch selection means (120) for determining whether the output value of said timer (119) is held in the individual latches in response to the operation of the individual counters of said first and second counter groups or in the same number of latches coupled in the latch group as that of counters coupled in said first and second counter group. A device according to claim 1, further comprising overflow detection means (127) for detecting an overflow condition of said timer (119) in the individual latches or the plurality of coupled latches from the state of the latches corresponding to the independent or coupled operation of said first and second counters. A device according to one of the claims 1 or 2, wherein a pulse counting circuit including said timer and said latches further includes latch control means (128) for storing the value of said timer by a read-in instruction to the latch from a microcomputer, for outputting a wait signal to the external microcomputer until the value of said counter is defined, and for outputting the data to said microcomputer from the plurality of parallel operating counters synchronously with the operation of the counters. A digital pulse processing device according to one of the claims 1 to 3, further comprising a pulse preprocessing unit (109) having two pulse input terminals (103, 104, ...), said pulse preprocessing unit selecting either counting of one or two single-phase pulses, counting of two-phase pulses having a directional component or counting of the input made up of a single pulse train and a signal for designating the counting method of the single pulse train. A microcomputer comprising a digital pulse processing device (100) according to one of the claims 1 to 4, and a CPU (503), which are formed on the same substrate and connected with each other through a system bus (101).

Inventors: MINAMI RIKA, OBARA SANSHIRO, OHBA MAMORU, WATABE MITSURU, MINAMI, RIKA, OBARA, SANSHIRO, OHBA, MAMORU, WATABE, MITSURU
Applicants: HITACHI LTD, HITACHI, LTD.
Application year: 1991
Main classification: G01P3
IPC codes: H02P29, G01P3