High-speed signal multiplexing circuit for multiplexing high-speed signals

Abstract: In a high-speed signal multiplexing circuit, when data supplied to an input terminal (D₀-D₃) of a flip-flop circuit (13₀-13₃) differs from the data which has been latched in the flip-flop circuit (13₀-13₃), an exclusive OR circuit (14₀-14₃) supplies a control signal to a clock signal input terminal (CK₀-CK₃) of the flip-flop circuit (13₀-13₃). The flip-flop circuit (13₀-13₃) latches the data supplies to the input terminal (D₀-D₃) in response to the control signal. A data reading section (12) generates a read signal in synchronism with a clock signal. The data latched in the flip-flop circuit (13₀-13₃) is successively read out in response to the read signal.

Description: The present invention relates to a high-speed signal multiplexing circuit for multiplexing a signal at a high speed. Such a multiplexing circuit is described in, e.g., "A Multiplexer Employing Josephson Functional Gates", Yuji Akahori and Yoshichika Ichimiya; IEEE Transactions on Electron Devices; ISSN 0018-9383; ED-32, Nr - 6, Pg 1053-1056; 85-06-00. Further, in "Alternative Latches", Y. Pang et al; Wireless World, Vol. 89 (1983), No. 1568, Sheepen Place GB, page 63 there is described the use of "spare gates" that help to reduce the number of integrated circuits in a given circuit design. Further, in FR-A-2 573 939 there is described a multiplexer circuit having four input lines. Fig. 4 shows a further conventional high-speed signal multiplexing circuit. A shift register section 31 includes D-type flip-flop circuits (hereinafter referred to as D flip-flop circuit) 32 0 , 32 1 , 32 2 , and 32 3 , and selector circuits 34 0 , 34 1 , 34 2 , and 34 3 respectively connected to input terminals D of the D flip-flop circuits 32 0 , 32 1 , 32 2 and 32 3 . Each of the selector circuits 34 0 , 34 1 , 34 2 and 34 3 comprises AND circuits 331 and 33 2 and an OR circuit 33 3 . The selector circuits 34 1 , 34 2 and 34 3 select either data D 1 , D 2 and D 3 respectively supplied to input terminals I 1 , I 2 and I 3 or data supplied from output terminals I 1 , I 2 and I 3 or data supplied from output terminals Q of the flip-flop circuits 32 0 , 32 1 and 32 2 in response to a load signal LS supplied from a load signal generating section 35 (to be described later). The selector circuit 34 0 selects either data D S supplied to an input terminal I S or data D 0 supplied to an input terminal I 0 in response to a load signal LS. A clock signal CK is inverted by an inverter IV, and then supplied to clock signal input terminals CK 0 to CK 3 of the D flip-flop circuits 32 0 to 32 3 . Data latched by the D flip-flop circuits 32 0 to 32 3 are successively shifted in response to clock signals CK, and output through output terminal D OUT . Thus, data latched in the shift register section 31 is output through the output terminal D OUT by four shifting operations. The load signal generating section 35 generates a load signal LS for causing data D S and D 0 to D 3 supplied to the input terminals Is and I 0 to I 3 to be latched by the D flip-flop circuits 32 0 to 32 3 by every four shift operations. The load signal LS is obtained by 1/4 frequency-dividing the clock signal CK, as is shown in Fig. 5. The load signal generating section 35 includes D flip-flop circuits 36 and 37, a NOR circuit 38 for generating a load signal from outputs of the flip-flop circuits 36 and 37, and a selector circuit 40 connected to an input terminal D of the D flip-flop 36. The selector circuit 40 comprises AND circuits 39 1 and 39 2 and a OR circuit 39 3 . An output terminal Q 1 of the flip-flop circuit 36 is connected to an output terminal SO. The selector circuit 40 switches the control system of the selector circuits 34 0 to 34 3 between an external synchronous mode and an internal synchronous mode. In other words, the selector circuit 40 selects either a signal output from an output terminal Q of the D flip-flop circuit 37 or a 1/4 frequency-divided clock signal SI in response to an inhibit signal INH. The load signal generating section 35 generates a load signal LS in response to a signal SI selected by the selector circuit 40 in the case of the external synchronous mode, and in response to an output signal of the D flip-flop circuit 37 selected by the selector 40 in the case of the internal synchronous mode. In the above-described conventional high-speed signal multiplexing circuit, the selector circuits 34 0 to 34 3 is controlled by a load signal LS generated asynchronously with input data. To generate a load signal LS in the external synchronous mode, the high-speed signal multiplexing circuit must control the phases of a clock signal CK, a signal SI having a frequency of four times that of the clock signal, and data D S , D 0 to D 3 . Hence, the circuit design is complicated and it is difficult to increase the margin of the operation of the circuit. Especially in a circuit operated by a signal having a high frequency of a GHz band, since signal transmission is performed by a distributed constant circuit and the resolution of the phase control is of pico-second order, it is quite difficult to control the phase of a signal externally. On the other hand, to generate a load signal LS in the internal synchronous mode, it is only necessary to control the phases of the clock signal and data D S , D 0 to D 3 , since a load signal LS is generated from a clock signal to control the selector circuits 34 0 to 34 3 . However, in this case, to increase the operation margin of the entire circuit, the phases of the data, the load signal, and the clock signal for operating the shift register section 31 must be controlled. Therefore, the circuit design is complicated. Thus, also in the case of controlling a phase in the internal synchronous mode, an operation of a wide margin in a high-frequency band in a GHz band cannot be achieved unless the circuit is designed with defining a signal which is to be phase-controlled. It is accordingly an object of the present invention to provide a high-speed signal multiplexing circuit wherein the phases of signals are controlled easily and the margin of a circuit operation in a high-frequency band is increased, thereby improving the performance in a high-frequency signal processing. The object is achieved by a high-speed signal multiplexing circuit for multiplexing a signal at a high speed having the features of claim 1. According to the present invention, when data supplied to the latch means differs from the data which has been latched therein, the latch control means causes the latch means to latch the data supplied thereto. Hence, it is assured that the latch means latches updated data not in synchronism with a clock signal. Moreover, the generating means generates a read signal in synchronism with the clock signal, and the read signal causes the data latched in the latch means to be read. Therefore, it is easy to control the timings of latching data and reading the latched data, and the margin of the operation is increased with a simple circuit, even if the circuit is operated in a high-frequency band. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram showing an embodiment of the present invention; Fig. 2 is a timing chart for explaining an operation of the circuit shown in Fig. 1; Fig. 3 is a circuit diagram showing a modification of the latch circuit shown in Fig. 1; Fig. 4 is a circuit diagram showing a conventional high-speed signal multiplexing circuit; and Fig. 5 is a timing chart for explaining an operation of the circuit shown in Fig. 4. An embodiment of the present invention will be described with reference to the accompanying drawings. Fig. 1 shows a high-speed signal multiplexing circuit comprising a latch section 11 and a data reading section 12. The latch section 11 latches 4-bit parallel data, bit by bit, supplied from an external circuit (not shown). The latch circuit 11 is comprised of D flip-flop circuits 13 0 , 13 1 , 13 2 and 13 3 and exclusive OR circuits 14 0 , 14 1 , 14 2 and 14 3 respectively connected to the D flip-flop circuits 13 0 , 13 1 , 13 2 and 13 3 . More specifically, input terminals D 0 to D 3 of the D flip-flop circuits 13 0 to 13 3 are respectively connected to data input terminals 15 0 to 15 3 and first input terminals of the respective exclusive OR circuits 14 0 to 14 3 . Output terminals Q 0 to Q 3 of the D flip-flop circuits 13 0 to 13 3 are connected to second input terminals of the respective exclusive OR circuits 14 0 to 14 3 . The output terminals of the D flip-flop circuits 13 0 to 13 3 are connected to clock signal input terminals CK 0 to CK 3 . In the latch section 11, when data supplied to the data input terminals 15 0 to 15 3 differ from the data which has been latched in D flip-flop circuits 13 0 to 13 3 , the exclusive OR circuits 14 0 to 14 3 output a control signal CS of high level. The control signal CS is supplied to the clock signal input terminals CK 0 to CK 3 of the D flip-flop circuits 13 0 to 13 3 . The D flip-flop circuits 13 0 to 13 3 , to which the control signal CS is supplied, latch the data supplied to the data input terminals 15 0 to 15 3 . As is shown in Fig. 2, data ID supplied to the input terminals 15 0 to 15 3 is updated at every 4 clocks. With the above structure, updated data is surely latched without using a clock signal unlike in the conventional device. The data reading section 12 reads data which has been latched in the D flip-flop circuits 13 0 to 13 3 in the latch section 11, consecutively in synchronism with the clock signal CK. The data reading section 12 comprises D flip-flop circuits 16 and 17, inverters 18 and 19, AND circuits 20 0 to 20 3 , AND circuits 21 0 to 21 3 , and an OR circuit 22. The D flip-flop circuits 16 and 17 1/4 frequency-divide the clock signal CK as indicated by Q 0 and Q 1 in Fig. 2. The inverter circuits 18 and 19 generate read signals R 0 to R 3 from the signal 1/4 frequency-divided by the D flip-flop circuits 16 and 17. The AND circuits 21 0 to 21 3 consecutively fetch data from the D flip-flop circuits 13 0 to 13 3 in response to the read signals R 0 to R 3 . The OR circuit 22 outputs data fetched by the AND circuits 21 0 to 21 3 to an output terminal 24. Clock signal input terminals CK 0 and CK 1 of the D flip-flop circuits 16 and 17 are connected to a clock signal input terminal 23. An input terminal D 0 of the D flip-flop circuit 16 is connected to an output terminal Q of the D flip-flop circuit 17. An output terminal Q 0 of the D flip-flop circuit 16 is connected to an input terminal D 1 of the D flip-flop circuit 17, and first input terminals of the AND circuits 20 1 and 20 2 . The terminal Q 0 is also connected to first input terminals of the AND circuits 20 0 and 20 3 via the inverter circuit 18. An output terminal Q 1 of the D flip-flop circuit 17 is connected to second input terminals of the AND circuits 20 2 and 20 3 . It is also connected to second input terminals of the AND circuits 20 0 and 20 1 via the inverter circuit 19. The output terminals of the AND circuits 20 0 to 20 3 are respectively connected to first input terminals of the AND circuits 21 0 to 21 3 . Second input terminals thereof are respectively connected to output terminals Q 0 to Q 3 of the D flip-flop circuits 13 0 to 13 3 . The output terminals of the AND circuits 21 0 to 21 3 are connected to input terminals to the OR circuit 22, the output terminal of which is connected to the output terminal 24. As is shown in Fig. 2, the data reading section 12 generates read signals R 0 to R 3 in response to a clock signal CK supplied to the clock signal input terminal 23. The read signals R 0 to R 3 are supplied to the AND circuits 21 0 to 21 3 . The data successively read by the AND circuits 21 0 to 21 3 from the D flip-flop circuits 13 0 to 13 3 is supplied to the OR circuit 22, and thereafter output in succession through the output terminal 24. According to the above embodiment, if data supplied to the input terminals 15 0 to 15 3 differ data which has been latched in the D flip-flop circuits 13 0 to 13 3 , the exclusive OR circuits 14 0 to 14 3 cause the D flip-flop circuits 13 0 to 13 3 to latch the data supplied to the input terminals 15 0 to 15 3 . Hence, the updated data is surely latched without using a clock signal, unlike in the conventional art. Hence, the wide margin of the operation in a high-frequency band is ensured, thereby improving the reliability of the operation. Since the latch section 11 need not latch data every four clocks, it can operate at a speed four times as that the conventional device, without an additional operation. Hence, the circuit has a more simple design and consumes less power than the conventional device. Moreover, since the data reading section 12 generates merely a read signal in synchronism with a clock signal, the circuit design thereof is simple. Fig. 3 shows a modification of the latch section 11. As shown in Fig. 3, buffer circuits 30 1 and 30 2 are connected to the input terminals of each of the exclusive OR circuits 14 0 to 14 3 , and a buffer circuit 30 3 is connected to the output terminal thereof. By virtue of the buffer circuits 30 1 , 30 2 and 30 3 , the latch section 11 can be applied to a signal of a low-frequency band. The buffer circuits need not be provided to both input terminals and the output terminal of each of the exclusive OR circuit 14 0 to 14 3 , but can be provided only to the input terminals. This invention is not limited to the above embodiments, but can be applied to a circuit for latching updated data by using only the latch section 11. Further, the signal mulitplexing circuit of the present invention can basically be constituted by a pair of D flip-flop circuit and exclusive OR circuit, to latch updated data. Furthermore, various modifications can be made within the scope of the invention.

Claims: A high-speed signal multiplexing circuit for multiplexing a signal at a high-speed characterized by comprising: a) a plurality of latch means (13 0 - 13 3 ) for latching 1-bit data, each of the latch means (13 0 - 13 3 ) having an input terminal (D) connected to corresponding data input terminal (15 0 - 15 3 ), an output terminal (Q) and a control signal input terminal (CK); b) latch control means (14 0 - 14 3 ) provided for each latch means (13 0 - 13 3 ), each of the latch control means (14 0 - 14 3 ) having a first input end connected to the corresponding data input terminal (15 0 - 15 3 ), a second input end connected to the output terminal (D) of the corresponding latch means (13 0 - 13 3 ) and an output end connected to the control signal input terminal (CK) of the corresponding latch means (13 0 - 13 3 ), each of the latch control means (14 0 - 14 3 ) configured to cause the latch means (13 0 - 13 3 ) to latch the supplied data from the data input terminal, when the supplied data differs from the data which has been latched in the latch means (13 0 -13 3 ); c) generating means (16 - 19, 20 0 - 20 3 ) for generating a read signal for successively reading data latched in said latch means (13 0 - 13 3 ) in synchronism with a clock signal; and d) reading means (21 0 -21 3 ) having a first input end for receiving the read signal from the generating means and a second input end connected to the output terminal of the corresponding latch means (13 0 - 13 3 ), for successively reading data latched in said latch means (13 0 - 13 3 ) in response to said read signal. A circuit according to claim 1, characterized in that each of said latch means (13 0 - 13 3 ) is constituted by a flip-flop circuit (13 0 - 13 3 ). A circuit according to claim 1, characterized in that said latch control means (14 0 - 14 3 ) is constituted by an exclusive OR circuit (14 0 - 14 3 ). A circuit according to claim 1, characterized in that said generating means (16-19, 20 0 - 20 3 ) is constituted by first and second flip-flop circuits (16, 17) for frequency-dividing a clock signal, first and second inverter circuits (18, 19) for inverting signals frequency-divided by said first and second flip-flop circuits (16, 17), and a plurality of AND (20 0 -20 3 ) circuits for receiving outputs of said first and second inverter circuits (18, 19) and said first and second flip-flop circuits (16, 17) and generating a read signal. A circuit according to claim 1, characterized in that said reading means is constituted by an AND circuit (21 0 - 21 3 ).

Inventors: MOTOIKE KOICHI, MOTOIKE, KOICHI, Motoike, Koichi, c/o Intellectual Property Div.
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1991
Main classification: H04J3
IPC codes: H04J3