Semiconductor integrated circuit provided with emitter coupled logic input/ output buffers

Abstract: A semiconductor circuit (40) comprises a plurality of first Emitter Coupled Logic (ECL) input buffer (21₁...21 n ) and output buffers (22₁...22 n ), which are driven by a specific number (m ≧ 2) power supplies. Further it comprises a plurality of ECL test input buffers (23₁...23 n ) and test output buffers (24₁...24 n ) driven by a specific number of power supplies (m ≧ 2). The power supply lines (41a,41b,42a,42b) to the ECL input and output buffers are independent of the power supply lines of the test input and output buffers. Power is supplied to the test input and output buffers only during assembly of the integrated circut.

Description: PRIOR ART The present invention relates to a semiconductor integrated circuit. PATENT ABSTRACTS OF JAPAN, vol. 9, no. 315, (E-365), 11 Dec. 1985, & JP-A-60 148 135 discloses a semiconductor integrated circuit having an input buffer, an internal logic circuit, and an output buffer which are commonly connected to a first external power supply terminal. A test circuit connected to a second power supply terminal is also connected to the internal logic circuit. In the usual operating state of the integrated circuit, power is only supplied to the first external terminal such that the test circuit is put into a non-operating condition. US-A-4 586 242 discloses a semiconductor integrated circuit having a larger integrated circuit chip of which a chip circuit portion is a part. The chip portion comprises a first plurality of first bonding pads which are each separately connected to a buffer of a first kind that operates with a first supply voltage. The larger chip - exclusive of the chip portion - comprises a second plurality of second bonding pads which are each separately connected to a buffer of a second kind that operates with a second voltage different from the first voltage. Each buffer of the second kind is separately connected to a separate corresponding one of the first bonding pads. The chip portion is capable of performing first electrical operations in response to first signals applied to the first bonding pads, and is capable of performing second operations in response to second signals applied to the second bonding pads. After at least one of the second operations has been performed by applying the second signals to the second bonding pads, at least one of the buffers of the second kind is disconnected from its corresponding one of the first pads, by physically severing the corresponding electrically conductive path. All of the buffers of the second kind may be disconnected from all of the corresponding first pads, and the chip portion may be severed completely from the larger chip exclusive of the chip portion. The first operation is the normal operation, whereas the second operation is a test operation for the integrated circuit. For facilitating to understand the present invention the technical background thereof will be briefly explained hereinafter. BACKGROUND OF THE INVENTION This invention relates to a semiconductor integrated circuit provided with Emitter Coupled Logic (hereinafter referred to as ECL) input/output buffers, and more particularly to a semiconductor integrated circuit provided with ECL input/output buffers capable of reducing power consumption. Generally, in the case of inputting an input signal of the ECL level from the external to a device such as SRAM or CPU, etc., and outputting an output signal of the ECL level from the above-mentioned device to the external, an ECL input buffer and an ECL output buffer are used, respectively. Such ECL input buffer and ECL output buffer are shown in FIGS. 1 and 2, respectively. The ECL input buffer shown in FIG.1 serves to convert an input signal of the ECL level to an output signal of the CMOS level. This ECL input buffer comprises a CMOS circuit comprised of diodes 3a and 3b, a resistor 3c, transistors 4a, 4b, 4c, 5a, 5b and 5c, a transistor 6a, resistors 6b and 6c, and transistors 7a and 7b, and a CMOS circuit comprised of transistors 8a and 8b, and is driven by a first power supply (e.g., a power supply voltage of 0 volts) connected to the terminal 1, and a second power supply (e.g., a power supply voltage of -5.0 volts) connected to the terminal 2. On the other hand, the ECL output buffer shown in FIG. 2 serves to convert an input signal of the CMOS level to an output signal of the ECL level. This ECL output buffer comprises transistors 13a, 13b and 13d, resistors 13c and 15a, transistors 14a, 14b, 15b and 16a, a resistor 16b, and diodes 17a and 17b, and is driven by a first power supply connected to the terminal 11 and a second power supply connected to the terminal 12. In addition to the input/output buffer of the above-mentioned type, there is known an ECL input/output buffer of the type to receive an input signal of the ECL level to output an output signal of the ECL level. Further, there is also known an ECL input/output buffer of the type driven by a number m (≧ 2) of power supplies. A conventional semiconductor integrated circuit including such ECL input/output buffer is shown in FIG. 3. This semiconductor integrated circuit is provided on a Large Scale Integrated circuit (LSI) chip 20. This semiconductor integrated circuit comprises ECL input buffers 21 1 , ... 21 n used when the circuit is in an ordinary operating state after assembled into the system, ECL output buffers 22 1 , ... 22 n used when the circuit is similarly in the ordinary operating state after assembled into the system, test ECL input buffers 23 1 , ... 23 n used only when the circuit is being assembled into the system and is subject to test, and test ECL output buffers 24 1 , ... 24 n used only when the circuit is being assembled into the system and is similarly subject to test. In operation, the input buffer circuit 21 i (i = 1, ... n) is driven by a first power supply voltage delivered through a power supply pad 25a and a second power supply voltage delivered through a power supply pad 25b to apply level conversion or waveform shaping to an input signal of the ECL level inputted through a pad 26 i (i = 1, ... n) when the circuit is in an ordinary operating state after assembly to send it to a device (e.g., CPU, etc.) 27 provided at the core section. Further, the output buffer circuit 22 i (i = 1, ... n) is driven by a first power supply voltage delivered through a power supply pad 28a and a second power supply voltage delivered through a power supply pad 28b to apply level conversion to a signal sent from the device when the circuit is in the operating state after assembly to provide an output signal of the ECL level to output it to the external through a power supply pad 29 i . On the other hand, the test input buffer circuit 23 i (i = 1, ... n) is driven by a first power supply voltage delivered through a power supply pad 30a and a second power supply voltage delivered through a power supply pad 30b to apply level conversion or waveform shaping to an input signal of the ECL level inputted through a power supply pad 31 i (i = 1, ... n) to send it to the device 27. Further, a test output buffer circuit 24 i (i = 1, ... n) is driven by a first power supply voltage delivered through a power supply pad 32a and a second power supply voltage delivered through a power supply pad 32b to apply level conversion to a signal outputted from the device 27 when the circuit is subject to test to provide an output signal of the ECL level to output it to the external through a power supply pad 33 i (i = 1, ... n). Respective terminals to which the first power supply voltages are applied of the input buffers 21 1 , ... 21 n , the output buffers 22 1 , ... 22 n , the test input buffers 23 1 , ... 23 n , and the test output buffers 24 1 , ... 24 n are connected commonly to a power supply line 34a, and respective terminals to which the second power supply voltages are applied of the above-mentioned buffers are connected commonly to a power supply line 34b. As seen from FIGS. 1 and 2, the ECL input/output buffer circuit is of a structure in which a current flows therein as long as any drive voltage is applied thereto. Accordingly, in the conventional semiconductor integrated circuit provided with the test ECL input/output buffers, there was the problem that even after such a semiconductor integrated circuit has been assembled into the system, current flows in the test ECL input/output buffers, so power is uselessly consumed. SUMMARY OF THE INVENTION This invention has been made in view of the above-mentioned problems, and its object is to provide a semiconductor integrated circuit permitting the power consumption thereof to be as small as possible. A semiconductor integrated circuit according to this invention has the features indicated in independent claim 1. Preferred embodiments of the invention are indicated in dependent claims 2 to 8. In accordance with the semiconductor integrated circuit of this invention thus constructed, only when the circuit is assembled into the system and is subject to test, the test ECL input buffer circuit and the test ECL output buffer circuit are driven by normal power supply voltages. Further, when the circuit is in an ordinary use state after having been assembled into the system, the number m of drive voltages for driving the test ECL input/output buffers are equal to each other. Accordingly, no current flows in the test ECL input buffer circuit and the test ECL output buffer circuit. As a result, power can be prevented from uselessly consumed as compared to the conventional semiconductor integrated circuit. Thus, power consumption can be as small as possible. Therefore, in accordance with this invention, an increase in the power consumption can be prevented. BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings; FIG. 1 is a circuit diagram showing the configuration of an input buffer provided in semiconductor integrated circuits according to the prior art and this invention; FIG. 2 is a circuit diagram showing the configuration of an output buffer provided in semiconductor integrated circuits according to the prior art and this invention; FIG. 3 is a circuit diagram showing the outline of the configuration of a conventional semiconductor integrated circuit provided with input/output buffers; FIG. 4 is a circuit diagram showing the outline of the configuration of a semiconductor integrated circuit provided with input/output buffers according to a first embodiment of this invention; and FIG. 5 is a circuit diagram showing the outline of the configuration of a semiconductor integrated circuit provided with input/output buffers according to a second embodiment of this invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a semiconductor integrated circuit provided with input/output buffers according to this invention will now be described with reference to the attached drawings. A first embodiment of a semiconductor integrated circuit according to this invention is shown in FIG. 4. The semiconductor integrated circuit of this embodiment is provided on a LSI chip 40. This semiconductor integrated circuit comprises ECL input buffers 21 1 , ... 21 n used when the circuit is in an ordinary operating state after assembled into the system, ECL output buffers 22 1 , ... 22 n used when the circuit is similarly in in the ordinary operating state after assembled into the system, test ECL input buffers 23 1 , ... 23 n used only when the circuit is being assembled into the system and is subject to test, and test ECL output buffers 24 1 , ... 24 n used only when the circuit is being assembled into the system and is similarly subject to test. This semiconductor integrated circuit differs from the conventional semiconductor integrated circuit in that drive voltage supply lines through which drive voltages for driving the ECL input buffers 21 1 , ...21 n , the ECL output buffers 22 1 , ... 22 n , the test input ECL buffers 23 1 , ... 23 n , and the test ECL output buffers 24 1 , ... 24 n are delivered, are separately provided on the LSI chip 40, respectively. Namely, first and second drive voltages for driving the ECL input buffers 21 1 , ... 21 n are delivered to the ECL input buffers 21 1 , ... 21 n respectively through a power supply pad 25a and a first drive voltage supply line 41a, and a power supply pad 25b and a second drive voltage supply line 41b to drive the ECL input buffers 21 1 , ... 21 n . Further, first and second drive voltages are delivered to the ECL output buffers 22 1 , ... 22 n respectively through a power supply pad 28a and a third drive voltage supply line 42a, and a power supply pad 28b and a fourth drive voltage supply line 42b. On the other hand, two drive voltages for driving the test ECL input buffers 23 1 , ... 23 n are delivered to the test ECL input buffers 23 1 , ... 23 n respectively through a power supply pad 30a and a fifth drive voltage supply line 43a, and a power supply pad 30b and a sixth drive voltage supply line 43b, and two drive voltages for driving the test ECL output buffers 24 1 , ... 24 n are delivered to the test ECL output buffers 24 1 , ... 24 n respectively through a power supply pad 32a and a seventh drive voltage supply line 44a, and a power supply pad 32b and an eighth drive voltage supply line 44b. In addition, these respective first to eighth drive voltage supply lines 41a, 41b, 42a, 42b, 43a, 43b, 44a and 44b are separately provided on the LSI chip 40. In the semiconductor integrated circuit of the first embodiment, wire bonding is implemented such that only when this semiconductor integrated circuit is being assembled into the system and is subject to test, the first drive voltage is delivered to the power supply pads 30a and 32a, and the second drive voltage is delivered to the power supply pads 30b and 32b, and when this semiconductor integrated circuit is in an ordinary use state after having been assembled into the system, the first drive voltage is delivered to the power supply pads 25a and 28a, and the second drive voltage is delivered to the power supply pads 25b, 28b, 30a, 30b, 32a and 32b. By implementing wire bonding in this way, when the semiconductor integrated circuit is in an operating state except for test state (after it has been assembled), two voltages for driving the test ECL input buffers 23 1 , ... 23 n and the test ECL output buffers 24 1 , ... 24 n are equal to each other. As a result, no current flows in the test ECL input buffers 23 1 , ... 23 n and the ECL output buffers 24 1 , ... 24 n . Thus, power uselessly consumed can be reduced. It is to be noted that, in the above-described embodiment, pads 31 1 , ... 31 n and pads 33 1 , ... 33 n are not subject to wire bonding with respect to the external pads, i.e., the pads 31 1 , ... 31 n are placed in floating state and the pads 33 1 , ... 33 n are placed in an open state. A second embodiment of a semiconductor integrated circuit according to this invention is shown in FIG. 5. The semiconductor integrated circuit of this embodiment is described below. Namely, in the conventional semiconductor integrated circuit shown in FIG. 3, the drive voltage supply line 34a for delivering the first drive voltage to the ordinary ECL input buffer 21 i (i = 1, ... n), the ordinary ECL output buffer 22 i (i = 1, ... n), the test ECL input buffer 23 i (i =1, ... n) and the test ECL output buffer 24 i (i = 1, ... n) is separated on the chip 50 to provide a first group of drive voltage supply lines 41a, 42a, 43a and 44a. Accordingly, there is employed in this embodiment an arrangement such that this first group of drive voltage supply lines 41a, 42a, 43a and 44a respectively correspond to those of the first embodiment, and the other drive voltage supply line 34b corresponds to that of the prior art shown in FIG. 3. At the time of testing this semiconductor integrated circuit, the first drive voltage is applied to the power supply pads 30a and 32a, and the second drive voltage is applied to the power supply pads 30b and 32b, so respective voltages are delivered through the voltage supply lines 43a and 34b. As a result, the test ECL input buffer 23 i (i = 1, ... n) and the test ECL output buffer 24 i (i = 1, ... n) become operative. Thus, a signal of the ECL level provided through the pad 31 i from the external is sent to the device 27 (e.g., CPU, etc.) provided on the core section through the ECL input buffer 23 i . Further, a signal from the above-mentioned device 27 is converted to a signal of the ECL level by the ECL output buffer 24 i through the drive voltage supply lines 34b and 44a, and is then outputted to the external through the pad 33 i . Thus, test of the semiconductor integrated circuit is carried out. Furthermore, wire bonding is implemented such that when this semiconductor integrated circuit is in an ordinary use state after assembly into the system, the first power supply voltage is applied to the power supply pads 25a and 28a, and the second power supply voltage is applied to the power supply pads 25b, 28b, 30a, 30b, 32a and 32b. By implementing wire bonding in this way, after the semiconductor integrated circuit has been assembled into the system, the drive voltage is delivered through the drive voltage supply lines 41a and 42a and and the drive voltage supply line 34b. Accordingly, no current flows in the test ECL input buffer circuit 23 i (i = 1, ... n) and the test ECL output buffer circuit 24 i (i = 1, ... n). As a result, power uselessly consumed can be reduced. Thus, an increase in the power consumption can be prevented to a higher degree as compared to the conventional semiconductor integrated circuit. It is to be noted that while it has been described in both the above-described embodiments that the number of power supplies for the ordinary input/output buffers and the test input/output buffers is equal to 2, in the case where the number of drive power supplies is m (≧ 2), an approach described below may be employed: a) to connect one of a number m of test drive voltage supply lines for delivering drive voltages to test ECL input buffers commonly to a corresponding one of a number m of ordinary drive voltage supply lines for delivering drive voltages to the ordinary ECL input buffers, or to provide test drive voltage supply lines independently of the ordinary drive voltage supply lines, and b) to connect one of a number m of test drive voltage supply lines for delivering drive voltages to test ECL output buffers commonly to a corresponding one of a number m of ordinary drive voltage supply lines for delivering drive voltages to the ordinary ECL output buffers, or to provide test drive voltage supply lines independently of the normal drive voltage supply lines. In addition, when the semiconductor integrated circuit is in an ordinary use state after having been assembled into the system, an approach is employed such that the same voltages are delivered to the test drive voltage supply lines for delivering drive voltages to the test ECL input buffers and the test ECL output buffers, respectively. It is a matter of course that, also when such an approach is employed, effects and/or advantages similar to those of the above-described embodiments can be provided. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A semiconductor integrated circuit (40, 50) comprising: a plurality of ECL input buffers (21 1 -21 n ) for inputting a signal of the ECL level from the external and having first and second drive voltage supply lines (41a, 41b); a plurality of ECL output buffers (22 1 -22 n ) for outputting a signal of said ECL level to the external and having third and fourth drive voltage supply lines (42a, 42b); a plurality of test ECL input buffers (23 1 -23 n ) for inputting a test signal of said ECL level from the external when said semiconductor integrated circuit is being assembled and having fifth and sixth drive voltage supply lines (43a, 43b); a plurality of test ECL output buffers (24 1 -24 n ) for outputting a test signal of said ECL level to the external when said semiconductor integrated circuit (40, 50) is being assembled and having seventh and eighth drive voltage supply lines (44a, 44b); a plurality of power supplies for supplying a first drive voltage and a second drive voltage to said buffers for driving same; wherein in an ordinary use state after said semiconductor integrated circuit (40, 50) has been assembled, said first drive voltage is supplied to said first and third drive voltage supply lines (41a, 42a), and said second drive voltage is supplied to said second, fourth, fifth, sixth, seventh and eighth drive voltage supply lines (41b, 42b, 43a, 43b, 44a, 44b) by implemented wire bonding; whereas when said semiconductor integrated circuit (40, 50) is being assembled and is subject to test, said first drive voltage is supplied to said fifth and seventh drive voltage supply lines (43a, 44a), and said second drive voltage is supplied to said sixth and eighth drive voltage supply lines (43b, 44b). A semiconductor integrated circuit (50) as set forth in claim 1, wherein said second, fourth, sixth, and eighth drive voltage supply lines form a common drive voltage supply line (34b). A semiconductor integrated circuit as set forth in claim 1, wherein one of said fifth and sixth drive voltage supply lines is common with a corresponding one of said first and second drive voltage supply lines. A semiconductor integrated circuit as set forth in claim 1, wherein one of said seventh and eight drive voltage supply lines is common with a corresponding one of said third and fourth drive voltage supply lines. A semiconductor integrated circuit as set forth in claim 1, wherein said fifth and sixth drive voltage supply lines (43a,43b) are separately formed on a large scale integrated circuit (40) independently of said first and second drive supply lines (41a,41b). A semiconductor integrated circuit as set forth in claim 1, wherein said seventh and eighth drive voltage supply lines (44a,44b) are separately formed on a large scale integrated circuit (40) independently of said third and fourth drive voltage supply lines (42a,42b). A semiconductor integrated circuit as set forth in claim 1, wherein said plurality of power supplies comprises two power supplies for driving said ECL input buffers (21 1 -21 n ) and said test ECL input buffers (23 1 -23 n ), and wherein said plurality of power supplies also comprises two power supplies for driving said ECL output buffers (22 1 -22 n ) and said test ECL output buffers (24 1 -24 n ). A semiconductor integrated circuit as set forth in claim 1, wherein said ECL input buffers (21 1 -21 n ) and/or said test ECL input buffers (23 1 -23 n ) perform a logical operation on said signal of said ECL level inputted thereto thus to output a signal of the CMOS level, and wherein said ECL output buffers (22 1 -22 n ) and/or said test ECL output buffers (24 1 -24 n ) perform a logical operation on a signal of said CMOS level inputted thereto thus to output said signal of said ECL level.

Inventors: SAKAUE KENJI, SAKAUE, KENJI
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1991
Main classification: H03K19
IPC codes: H03K19, G01R31