Process for forming a buried drain or collector region in monolithic semiconductor devices

Abstract: The invention relates to a process for forming a buried drain (3) or collector region in monolithic semiconductor devices comprising an integrated control circuit and one or more power transistors with vertical current flow integrated in the same chip. The process allows optimization of the current-carrying capacity and the series drain resistance of the power stage and operating voltage in comparison with known structures by provision of one or more regions (3) of high dopant concentration defined after growth of a first epitaxial layer (2).

Description: The present invention relates to a process for forming a buried drain or collector region in monolithic semiconductor devices comprising an integrated control circuit and one or more MOS or bipolar power transistors with vertical current flow integrated in the same chip. Association in the same chip of power transistors with vertical current flow and an integrated control circuit provides a very compact and efficient device which is advantageous as compared with separate components. A recurring problem in providing such devices is minimization of the difference s between the distance separating the drain or collector junction of the power transistor from the substrate and the distance separating said substrate from the lower margin of the insulation region of the integrated control circuit for reasons which are explained below. To minimize said difference s there is usually provided a buried drain region or a buried collector region respectively by means of selective implanting of phosphorous (a highly diffusive dopant) on the substrate. During the epitaxial growth and the subsequent diffusions the phosphorous rises to the top of the chip faster than the antimony with which the substrate is doped. This technique has considerable drawbacks. A first problem consists of the large tolerances which must be respected for the layout rules because of the high side diffusion of the buried collector region. Then very thick epitaxial growths are necessary because allowance must also be made for rising of the antimony to the surface; yields are thus penalized because of the quality of the epitaxial layer. In addition there arise considerable difficulties of alignment of the subsequent photomaskings because plotting topographies through the thick epitaxial layers is a source of problems. Implantation of high quantities of phosphorous (even higher than 10 15 atom/m 2 ) then gives rise to a very high defect rate; among other things about the half of the dopant introduced diffuses to the substrate and is thus unused. Finally, because of the thermal cycles necessary for manufacturing the device, the transition between the epitaxial and diffused collector regions is not sharp but displays a trend with a low dC/dx gradient of the concentration C of dopant along the depth x in the chip with highly negative consequences for the series drain resistance (Ron) or the current-carrying capacity in the case of a bipolar power transistor. The process in accordance with the invention aims at overcoming the above drawbacks. The invention provides methods for forming a buried drain or collector region in an integrated power transistor/control circuit device as defined in claims 1 and 4. Preferred embodiments are defined in the dependent claims. The characteristics of the invention will be clearer by the description below and the annexed drawings of examples of the prior art and of nonlimiting examples of embodiments of the invention wherein: FIGS.1 and 3 show examples of known structures with bipolar or MOS power transistors and integrated control circuit integrated monolithically in the same chip, FIG.2 shows the electrical equivalent of FIG. 1, FIGGS.4, 5, 6 and 7 show examples of known structures using a buried collector region or a buried drain region, FIG.8 shows the doping profiles in the bipolar power transistor zone of FIG. 4, FIGS.9 and 10 show the doping profiles in the MOS power transistor zone of FIGS. 5 and 6, FIG.11 shows the doping profiles in the power transistor zone, when the buried layer region is placed in series with the buried drain region, FIGS.12, 13, 14 and 15 show a first example of embodiment of the process according to the invention, FIG.16 shows the doping profiles in the power transistor zone of FIG. 15, FIG.17 shows a second example of embodiment of the process in accordance with the invention, FIGS.18, 19, 20, 21 and 22 show a third example of embodiment of the process according to the invention, FIG.23 shows the doping profiles in the power transistor zone of FIG. 22, FIGS.24, 25, 26 and 27 show a fourth example of realization of the process in accordance with the invention, and FIG.28 shows the doping profiles in the power transistor zone of FIG. 27. FIG.1 shows a known example of a bipolar power transistor and integrated control circuit integrated monolithically in the same chip. For simplicity's sake only one component of the integrated control circuit (a low power npn transistor) and a single npn power transistor are shown. The device is capable of operating correctly if the type p insulation region consisting of the whole of the P1 and P2 regions is connected to the lowest potential point of those in the device. In effect, if one observes FIG. 2, which represents the electrical equivalent of the structure, it is noted that the diode having as anode the insulation region and as cathode the collector region of the power transistor is reverse biased and hence the components of the integrated pilot circuit are insulated between them and from the power stage. This circumstance makes possible the operation of the device. On the other hand, the distance d separating the lower margin of the insulation region from the substrate is less than the distance l separating the lower margin of the base region of the power transistor from the substrate. It follows that the breakdown voltage of the diode mentioned above is less than the breakdown voltage of the power transistor and hence the maximum operating voltage of the device is determined by the former rather than the latter. In designing a device it is thus obligatory to set the thickness d to withstand the maximum required voltage. The current-carrying capacity of the power stage, vice versa, depends on the collector thickness and hence on l in accordance with an inverse quadratic proportionality law. Since l = s + d > d , it is clear that said current-carrying capacity is penalized by the difference between the depth of the junction of the power transistor base and that of the horizontal insulation region P1. But if the power stage is provided by MOS technology, the most important parameter is the series drain resistance (Ron) which depends in a linear manner on l (FIG. 3). It is this magnitude which is penalized by the difference s = l - d. FIGS. 4, 5, 6 and 7 show known examples of structures which to minimize s use a buried collector or buried drain region obtained by selective implantation of phosphorous on the substrate and then diffusion (see e.g. Electronics, Nov. 20, 1980, pages 40-41, for a more detailed description of a device of the type shown by Fig.7 and US-A-4 879 584 which discloses a device of the type shown in figures 5 and 7). The concentration profile of the various kinds of dopants along the emitter, base and collector regions of the power transistor (with reference to FIG. 4) is illustrated in FIG. 8. The curves EP, BP, CE and CD refer to the dopant impurities used for the emitter, the base, the epitaxial region and the collector diffused region respectively. In FIG. 9 are shown the analogous curves for a high voltage MOS transistor (with reference to FIG. 5), i.e. SM for the source, BM for the channel region, DE and DD for the epitaxial region and the diffused drain region respectively. FIG. 10 finally summarizes the profiles for a low voltage MOS transistor (see MOS transistor of FIG. 6, remembering that analogous profiles apply also for the MOS transistor of FIG. 7); in comparison with FIG. 9, the buried layer region DB is also inserted for the power stage. For low voltage devices (FIGS. 6 and 7) introduction of buried layer region DB in series with the buried collector (drain) region DD can solve the problem because the region where the DD and DE curves join is covered by the buried layer DB (see again FIG. 10). For high voltage devices this solution does not apply. To keep higher voltages it is necessary to increase the value of d and hence the superimposition of the regions DD and DB is no longer satisfactory, as seen in the example of FIG. 11. FIGS. 12 to 15 illustrate the steps of a first example of embodiment of the process in accordance with the invention. On a monocrystalline silicon substrate 1 of n+ type having high impurities concentration there is grown a first epitaxial layer 2 of n type. Using known techniques of oxidation, photomasking, dopant implantation (arsenic or antimony) and diffusion there is provided a n+ type region 3 which constitutes the buried drain (FIG. 12). At this point a new epitaxial growth is made by means of which there is obtained the n type layer 4 having uniform impurities concentration, which extends over the entire chip surface. Again using the usual oxidation, photomasking, implantation and diffusion techniques there is provided in the layer 4 a p+ type region 5 which constitutes the horizontal insulation region of the integrated control circuit and, in the region 5, a type n+ region 6 (the so-called buried layer) designed to constitute the collector of the npn transistor of the control circuit (FIG. 13). There is then provided a third epitaxial growth by means of which is obtained the type n layer 7 having uniform impurities concentration and extending over the entire chip surface. Again using known techniques of oxidation, photomasking, implantation and diffusion there is provided formation of the type p+ regions 8, which constitute the vertical insulation regions, and creation of the type n+ region 11 which serves as the sink of the low voltage npn transistor (necessary to reduce the collector series resistance), as illustrated in FIG. 14. At this point there is provided by known techniques the base region 12 and emitter region 13 of the low voltage npn transistor, there is deposited the polycrystalline silicon for the gate region 14, and there are defined the regions 9 (type p) and 10 (type n) which constitute the channel region and the source region respectively of the MOSFET power transistor. Finally there are provided opening of the contacts and interconnection of the various element of the device by means of a metallization and photomasking process. All the terminal electrodes of the various components are placed on the front of the chip except the drain of the power MOSFET which is located on the back thereof (FIG. 15). To analyze how the structure formed by the process in accordance with the invention overcomes the problems of the known art reference is made to FIG. 16. Therein are shown the trends of dopant concentration along a cross section passing through the source 10, the channel region 9, the epitaxial drain 7 and 4, and the diffused drain 3 of the power transistor to the substrate 1. The condition l ≤ d is respected merely by adjusting the thickness of the first epitaxial layer 2, which is determined by the difference between the junction depths of the power stage and of the horizontal insulation region of the integrated control circuit. If, to provide the buried drain region 3 is used a slow diffusing dopant, e.g. antimony, the interface between the epitaxial drain and the diffused drain is very well defined, certainly sharper than in the cases contemplated by the known art (on this point compare FIG. 16 with FIG. 9 and in particular gradient dC/dx at the above mentioned interface). As already mentioned, this is advantageous. In addition, use of a slow diffusing dopant allows reduction of the thickness of the epitaxial layer 4, simplifying in this manner the alignment procedure between the region 3 and the subsequent photomaskings. It is clear that numerous variants and modifications can be made in the foregoing embodiment of the invention without thereby going beyond the scope thereof. For example it is possible to insert inside the second epitaxial layer 4, in the region reserved for the power stage, a buried layer region 15 having high dopant concentration (similar to the buried layer region 6) if it is desired to provide a low voltage and low Ron device. FIG. 17 illustrates the cross section of such a device. It is pointed out that in this case it is not necessary to consider a process sequence different from the one described above since it is sufficient to provide a different layout of the photomasking of the buried layer. In a variant of the process in accordance with the invention the first epitaxial layer 2 or both the epitaxial layers 2 and 4 can be type p, provided that the region 3 is created subsequently to the first epitaxial growth and that the region 5 is created subsequently to the second epitaxial growth. If both the epitaxial layers 2 and 4 are type p, creation of the diffused region 5 can be omitted because insulation of the control circuit is assured by the presence of the above mentioned type p epitaxial layers. The structures in accordance with the invention thus far described require three epitaxial growths. There is now illustrated a new variant which, to provide the buried drain (collector) region as the former ones, dispenses with implantations of dopant directly on the substrate but is differentiated therefrom by the presence of only two epitaxial layers. This process makes use of the growth of one epitaxial layer before implantation and diffusion of the diffused collector region, which in this case is provided by means of selective implantation of moderate quantities of a dopant having a high diffusion coefficient, e.g. phosphorous in quantities between 5·10 13 and 1·10 15 atom/cm 2 . It is described with reference to the figures from 18 to 22. A type n- epitaxial layer 22 is grown on a substrate of type n+ monocrystalline silicon 21 with high impurities concentration. By known techniques of oxidation, photomasking, implantation and diffusion there is provided a type n+ region 23 which constitutes the buried drain (FIG. 18). Again making use of the usual techniques of oxidation, photomasking, implantation and diffusion there is provided in the region 22 a type p region 24 which constitutes the horizontal insulation region of the integrated control circuit (FIG. 19). The next step is definition of the type n+ buried layer regions 25 and 26 in the regions 23 and 24 respectively, as can be seen in FIG. 20. It is noted that the regions 24, 25, 26 are all provided in the first epitaxial layer 22, differently from the previous invention imbodiments. A second epitaxial growth is then made, by means of which the type n layer 27 is obtained which extends over the entire surface of the chip. Again using known techniques of oxidation, photomasking, implantation and diffusion there are formed type p+ regions 28 which constitute the vertical insulation regions necessary for insulating the integrated control circuit components from the power stage of said integrated circuit as illustrated in FIG. 21. At this point the process continues (in accordance with the outline set forth above) with the provision of the base region 32 and emitter region 33 of the npn transistor of the control circuit, the polycrystalline silicon is deposited for the gate region 34 and there are provided the type p region 29 and the type n region 30 which constitute the channel and source regions respectively of the MOSFET power transistor. Finally there is provided opening of the contacts and interconnection of the various elements of the device by means of a metallization and photomasking process. All the terminal electrodes of the various components are placed on the front of the chip except the drain of the power MOSFET which is located on the back thereof (FIG. 22). FIG. 23 shows the doping profiles in the region reserved for the power stage along a cross section passing through the source (30), the channel region (29), the epitaxial drain (27), the buried layer (25), the buried drain (23) and the substrate (21). The advantages of this structure in comparison with those of the known art are essentially that: the quality of the first epitaxial layer, which is grown directly on the substrate and whose thickness can be reduced considerably, is significantly improved; and the quantity of phosphorous implanted is reduced by more than one order of magnitude and the dopant introduced is used entirely. Another improvement in this structure consists of replacing the first type n epitaxial growth (region 22) with an analogous type p growth (region 42 of FIG. 27). In this case there can be eliminated the steps necessary for provision of the horizontal insulation region (region 24). The thickness of this type p epitaxial layer would be further reduced with positive effects on the Ron, too. FIGS. 24, 25 and 26 visualize the process sequence and FIG 28 illustrates the doping profiles in the power MOSFET zone. The examples of embodiment described for the structures of FIGS. 15, 17, 22 and 27 refer to a power stage made up of a MOS transistor but they also apply for the case of a power stage consisting of a bipolar transistor, it being sufficient to vary in a manner obvious to those skilled in the art the layout for the photomaskings of the final steps so as to provide the base and emitter regions of the bipolar power transistor in place of the channel and source regions of the MOS transistor.

Claims: Process for forming a buried drain or collector region in monolithic semiconductor devices comprising an integrated control circuit and an MOS or bipolar power transistor respectively, with vertical current flow, integrated in the same chip, characterized in that it comprises the following initial steps: growing, on a substrate (1) having a first type of conductivity, a first epitaxial layer (2), forming in said first epitaxial layer (2) a first region (3) having high concentration of a dopant of the same type of conductivity as the substrate and low diffusion coefficient, joining with said substrate and designed to constitute a buried drain or collector region respectively of the power transistor, said first region being obtained by means of selective implanting of the dopant on the first epitaxial layer and subsequent diffusion, said initial steps being followed by these other steps: growing on the first epitaxial layer (2) a second epitaxial layer (4) having the same type of conductivity as the substrate (1) or the opposite type of conductivity, said opposite type of conductivity of the second epitaxial layer being exclusively possible when the first epitaxial layer has a type of conductivity opposite that of the substrate, defining in the second epitaxial layer (4), if the same has the same type of conductivity as the substrate, a second region (5) having conductivity of a type opposite that of the substrate (1) designed to constitute the horizontal insulation region of the integrated control circuit, forming, in case the second epitaxial layer has the same type of conductivity of the substrate, a buried layer region (6) within said second region (5), said buried layer region (6) having the same type of conductivity as the substrate (1) and being designed to constitute the collector of a transistor of the control circuit, forming, in case the second epitaxial layer has the opposite type of conductivity of the substrate, a buried layer region (6) inside said second epitaxial layer, said buried layer region (6) having the same type of conductivity as the substrate (1) and being designed to constitute the collector of a transistor of the control circuit, growing on the second epitaxial layer (4) a third epitaxial layer (7) having the same type of conductivity as the substrate (1), forming in the third epitaxial layer: vertical insulation regions (8), a collector sink region (11), a base region (12) and an emitter region (13) of said transistor of the control circuit, source regions (10) and a channel region (9) of the MOS power transistor, or respectively a base region and an emitter region of the bipolar power transistor, forming gate regions (14) above said channel regions (9) in case the power transistor is of MOS type. Process in accordance with claim 1 characterized in that during the forming of the third region (6) a buried layer region (15) is realized inside the second epitaxial layer, said buried layer region (15) having the same type of conductivity as the substrate (1) and being in series with said first region (3). Process in accordance with any one of the above claims characterized in that the substrate (1) has type n conductivity and that the dopant of the first region (3) consists of arsenic or antimony. Process for formation of a buried drain or collector region in monolithic semiconductor devices comprising an integrated control circuit and an MOS or bipolar power transistor respectively, with vertical current flow and integrated in the same chip, characterized in that it comprises the following initial steps: growing, on a substrate (21,41) having a first type of conductivity, a first epitaxial layer (22,42), forming, in said first epitaxial layer, a first region (23,43) with high dopant concentration having the same type of conductivity as the substrate (21,41) and high diffusion coefficient, joining with said substrate and designed to constitute a buried drain or collector region respectively of the power transistor, said first region being obtained by means of selective implanting of the dopant on the first epitaxial layer and subsequent diffusion, defining in said first epitaxial layer (22), if the same has the same type of conductivity as the substrate, a second region (24) having conductivity of a type opposite that of the substrate and designed to constitute the horizontal insulation region of the integrated control circuit, forming, in case the first epitaxial layer has the same type of conductivity of the substrate, a third buried layer region (25) and a fourth buried layer region (26) having the same type of conductivity as the substrate, the third region being in series with said first region (23), and the fourth region, designed to constitute the collector of a transistor of the control circuit, being inside said second region, forming, in case the first epitaxial layer has the opposite type of conductivity of the substrate, a second buried layer region (44) and a third buried layer region (45) having the same type of conductivity as the substrate, the second region being in series with said first region (43), and the third region, designed to constitute the collector of a transistor of the control circuit, being inside said first epitaxial layer (42), said initial steps being followed by these other steps: growing on the first epitaxial layer a second epitaxial layer (27,46) having the same type of conductivity as the substrate, forming in the second epitaxial layer: vertical insulation regions (28,47), a collector sink region, a base region (32,52) and an emitter region (33,53) of said transistor of the control circuit, source regions (30,50) and a channel region (29,49) of the MOS power transistor, or respectively a base region and an emitter region of the bipolar power transistor, forming gate regions (34,54) above said channel regions (29,49) in case the power transistor is of MOS type. Process in accordance with claim 4 characterized in that the substrate has type n conductivity and that the first region is obtained after implantation of phosphorous in quantities between 5·10 13 and 1·10 15 atom/cm 2 .

Inventors: ZAMBRANO RAFFAELE, ZAMBRANO, RAFFAELE
Applicants: CONS RIC MICROELETTRONICA, CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO - CORIMME
Application year: 1991
Main classification: H01L21
IPC codes: H01L21, H01L29, H01L27