Current limiting circuits

Abstract: Disclosed herein is a circuit for limiting the output current I O of a power MOSFET T₁. A resistor R₂ converts the current I O into a low voltage V O . The low voltage V O is detected by a low-voltage detecting circuit. When the low voltage V O is higher than a predetermined value V OL , the output current I O of the power MOSFET T₁ is limited. The low-voltage detecting circuit comprises bipolar transistors Q₁ to Q₄. The base and collector of the transistor Q₁ are connected to each other. The collector of the transistor Q₂ is connected to the emitter of the transistor Q₁. The base and emitter of the transistor Q₃ are connected to the bases of the transistors Q₁ and Q₂, respectively. The base and collector of the transistor Q₄ are connected to the emitters of the transistors Q₁ and Q₃, respectively. The low voltage V O is applied to the node between the emitters of the transistors Q₂ and Q₄.

Description: The present invention relates to current-limiting circuits for limiting the output current of a power device when the low voltages rises above a predetermined value. US 3,930,172 discloses an input supply independent circuit having a first transistor, whose base and connector are connected to each other, a second transistor, whose collector is connected to the emitter of said first transistor, a third transistor, whose base is connected to the base of said first transistor and whose emitter is connected to the base of said first transistor and a fourth transistor, whose base is connected to the emitter of said first transistor and whose collector is connected to the emitter of said third transistor. The circuit operates as a voltage regulator, wherein the voltage developed across a resistor in the emitter path of one of the transistors has a value other than zero, if the emitter areas of the transistors are of different values. Fig. 1 shows a power device T 1 designed to function as a main switch, and also a current-limiting circuit 11 for limiting the current flowing through the power device T 1 . The current-limiting circuit 11 comprises a lateral NPN transistor Q 1 and two resistors R 1 and R 2 (e.g., diffusion resistors, polysilicon registers, or aluminum wiring). Advantageously, this circuit 11 can be formed on a chip, by a method substantially identical to the method of manufacturing a discrete power transistor. The current-limiting circuit 11 can restrict the output current I O of the power device T 1 . More precisely, when the output current I O increases over the value I OL given below, the transistor Q 1 is turned on, thereby limiting the output current I O of the power device T 1 . I O ≧ I OL ≈ V BEQ1 R 2 To limit the output current I O of the device T 1 , the voltage drop made by the resistor R 2 must be greater than the voltage V BEQ1 which turns on the transistor Q 1 . Inevitably, the current-limiting circuit 11 has a great power loss P D , which is given as follows: P D = I OL × V BEQ1 = I OL 2 × R 2 In practice, not only the power loss P D , but also the power loss P D ' should be considered, which is made by the register R DS existing between the drain and source of he power device T 1 . The total power loss P DT in the circuit comprised of the device T 1 and the circuit 11 is, therefore, considerably large, as can be understood from the following equation (3). P DT = P D + P D ' = I OL (V BEQ1 + V DS(ON) ) = I OL 2 (R 2 + R DS ) where V DS(ON) is the drain-source voltage of the power device T 1 . Fig. 2 shows a power device T 1 designed to function as a main switch and developed to solve the problem with the circuit shown in Fig. 1, and also a current-limiting circuit 11 identical to the circuit 11 shown in Fig. 1, used for limiting the current flowing through the power device T 1 . As is evident from Fig. 2, the power device T 1 comprises a plurality of small cells. The small cells are divided into two groups, the first consisting of n times as many cells as the the second group, where n is a number greater than 1. Hence, the output current I O of the device T 1 is divided into two two parts having magnitudes n and 1, respectively. Hence, the current I O ', defined below, is supplied to the resistor R 2 . I O ' = 1 N + 1 · I O In the circuit shown in Fig. 2, when the output current I O of the power device T 1 increases above the value I OL defined by equation (5), the transistor Q 1 is turned on, whereby the current I O is limited. I O ≧ I OL ≈ (n + 1) · V BEQ1 R 2 If n >> 1, the power loss PD made by the resistor R 2 can be neglected. Therefore, it suffices to consider the power loss P D ' resulting from the drain-source resistor R DS of the power device T 1 . Hence, the total power loss P DT in the circuit comprised of the device T 1 and the circuit 11 is less than that in the circuit of Fig. 1. P DT = P D ' = I OL × V DS(ON) = I OL 2 × R DS To cause a current to flow through the power device T 1 , the following relation (7) must avail: V DS(ON) > V BEQ1 The total power loss P D in the circuit of Fig. 2 is greater than I L V BEQ1 as can be understood from the following equation: P DT = I OL × V DS(ON) > I OL × V BEQ1 In either conventional current-limiting circuit 11 described above, use is made of the base-emitter voltage V BEQ1 (about 0.6 V) of the transistor Q 1 to detect the output current I O of the power device T 1 . The power loss P DT of the circuit comprising the device T1 and the circuit 11 is inevitably large. The object of the invention is to provide a current-limiting circuit for limiting the output current of an intermediate or high power transistor with low total power loss. This object is solved by a current-limiting circuit comprising, besides a power device having a control electrode : a first resistor connected at one end to the control electrode of the power device, and at the other end to the voltage source for the low-voltage detecting circuit; a second resistor connected to the output of the power device, for detecting the output current of the power device; and a third resistor connected at one end to the voltage source, and at the other end to the collector of the first transistor of the low-voltage detecting circuit. The collector of the third transistor is connected to the control electrode of the power device. The emitter of the second transistor is connected to the first end of the second resistor. The emitter of the fourth transistor is connected to the second end of the second resistor. This object is further solved by a current-limiting circuit, comprising: a power device having a control electrode for receiving a control input; a resistor for detecting an output current of said power device, said resistor having a first end connected to the power device and a second end; a first transistor whose base and collector are connected to each other, and whose collector is connected to a current source; a second transistor whose collector is connected to the emitter of said first transistor, and whose emitter is connected to the first end of said resistor; a third transistor whose base is connected to the base of said first transistor, and whose emitter is connected to the base of said second transistor; and a fourth transistor whose base is connected to the emitter of said first transistor, whose collector is connected to the emitter of said third transistor and whose emitter is connected to the second end of said resistor, wherein an output signal is output from the collector of said third transistor when the output current of said power device increases over a predetermined value to limit the output current of said power device in response thereto. In this current-limiting device, the collector current (OUTPUT) of the third transistor can be utilized for various purposes with high efficiency. Further advantageous embodiments and improvements of the invention may be taken from the dependent claims. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figs. 1 and 2 are diagrams showing two conventional current-limiting circuits, respectively; Fig. 3 is a circuit diagram showing an example of a low-voltage detecting circuit Fig. 4 is a circuit diagram showing a modification of the low-voltage detecting circuit shown in Fig. 3; Fig. 5 is a circuit diagram showing a circuit designed to limit the output current of a power transistor and having the low-voltage detecting circuit shown in Fig. 1 according to an embodiment of the invention; Fig. 6 is a graph representing the relationship between the gate-source voltage V GS and output current I 0 of a main power transistor; Figs. 7 and 8 are circuit diagrams showing two modifications of the current-limiting circuit shown in Fig. 5 illustrating further embodiment of the invention; and Figs. 9 and 10 are circuit diagrams showing further examples of low-voltage detecting circuits. Embodiments of the present invention will now be described, with reference to the accompanying drawings. First, Fig. 3 shows an example of a low-voltage detecting circuit, which comprises four lateral NPN transistors Q 1 , Q 2 , Q 3 , and Q 4 . The transistor Q 3 has an emitter area N times greater than that of the transistor Q 1 , where N is a number other than 1. The transistor Q 2 has an emitter area M times greater than that of the transistor Q 4 . A current I 1 is supplied to the transistors Q 1 and Q 2 , operating these transistors, and also to the base of the transistor Q 3 . The low-voltage detecting circuit is designed to detect a low voltage V 0 . A control current I 2 flows through the circuit when the low voltage V 0 rises above a predetermined value V OL . The voltage V OL can be calculated as follows, from the base-emitter voltages of the transistors Q 1 to Q 4 . First, the currents I 1 and I 2 are given as follows: I 1 = I sat1 · e q kT V BEQ1 = M · I sat2 · e q kT V BEQ2 I 2 = N · I sat1 · e q kT VBEQ3 = I sat2 · e q kT V BEQ4 The base-emitter voltages of the transistors Q 1 to Q 4 have the following relationship: V BEQ1 + V BEQ4 = V BEQ3 + V BEQ2 + V OL V OL = V BEQ1 - V BEQ2 + V BEQ4 - V BEQ3 Equation (9) can be formed into the following equation (9)': V BEQ1 - V BEQ2 = kT q ℓn( M·I sat2 I sat1 ) equation (10) can be transformed into the following equation (10)': V BEQ4 - V BEQ3 = kT q ℓn( N·I sat1 I sat2 ) From equations (9)' and (10)', the voltage V OL is found to have the value given as follows: V OL = kT q ℓn(N·M) Equation (12) shows that the voltage V OL does not depend on the current I 2 . Rather, it is determined by the ratio of the emitter area of the transistor Q 1 to that of the transistor Q 3 , and also by the ratio of the emitter area of the transistor Q 2 to that of the transistor Q 4 . In other words, the low voltage V 0 (= V OL ), which is defined by equation (12), can be detected by selecting appropriate values for N and M. In addition, the power loss of the low-voltage detecting circuit can be less than that of the conventional one, since the voltage V OL can be far lower than the base-emitter voltage of, for example, the transistor Q 1 shown in Fig. 1. The control current i2 and the detected voltage V 0 can have the following relationships: (1) When V 0 < V OL , I 2 ≈ 0 (2) When V 0 = V OL , I 2 increases exponentially (3) When V 0 > V OL , I 2 keeps flowing until it reaches the maximum value determined by the current I 1 and the current ability (e.g., amplification factor) of the NPN transistors. Fig. 4 shows a modification of the low-voltage detecting circuit shown in Fig. 3. This circuit is identical to the circuit of Fig. 3, except that a resistor R 2 and a current source I 0 are used in place of the low voltage V 0 . In this circuit, when a current I 0 increases over a predetermined current I OL defined by the following equation (13), the control current I2 can flow through the transistors Q 3 and Q 4 . I OL = 1 R2 · kT q ℓn(M·N) Fig. 5 shows a circuit which is designed to limit the output current of a power transistor and having the low-voltage detecting circuit shown in Fig. 1 according to an embodiment of the invention. In this circuit, the output current I 0 of a power MOSFET T 1 is supplied to a resistor R 2 , thereby detecting the low voltage applied to a resistor R 2 . In the current-limiting circuit shown in Fig. 5, V OL = I OL × R 2 , where I OL is the maximum current the power MOSFET T 1 can output. Based on this, equation (12) can be transformed into the following equation (14): I OL = 1 R 2 · kT q ℓn(N·M) Hence, when the output current I O is less than the maximum output current I OL (namely, I O < I OL ), the current I 2 flowing through the transistors Q 3 and Q 4 are substantially nil. In other words, the gate-source voltage V GS of the power MOSFET T 1 is V 1 - R 2 × I 0 , where V 1 is the voltage applied to a terminal 12, which is higher than the voltage V GS(ON) required to turn on the power MOSFET T 1 . Since R 2 × I 0 has an extremely small value, V GS is nearly equal to V 1 . Thus, the power MOSFET T 1 is on at all times, and its output current I O is not limited at all. Conversely, when the output current I O is equal to or greater than the maximum output current I OL (namely, I O ≧ I OL ), the current I 2 flowing through the transistors Q 3 and Q 4 increases greatly. As a result, the gate voltage V G of the power MOSFET T 1 changes to V 1 - R 1 × I 2 . Hence, the gate-source voltage V GS of the power MOSFET T 1 changes to about V 1 - R 1 × I 2 . In other words. Thus, the power MOSFET T 1 is turned off when the voltage V GS falls below the voltage V GS(ON) . Then, the output current I O of the power MOSFET T 1 is limited. Fig. 6 represents the relationship between the gate-source voltage V GS and output current I 0 of the power MOSFET T 1 . As can be understood from Fig. 6, the gate-source voltage VGS abruptly falls when the output current I 0 increases over the maximum value I OL . Obviously, the output current I 0 of the power MOSFET T 1 is limited. The power MOSFET and the current-limiting circuit for limiting the output current of the MOSFET, both shown in Fig. 5, can be fabricated in one and the same step of the method of manufacturing an ordinary discrete power transistor. The resistor R 2 can be formed of an aluminum wire or a bonding wire. In addition, the power device is not limited to a power MOSFET, and can be a bipolar type transistor e.g., insulated gate bipolar transistor. Two further embodiments of the current-limiting circuit shown in Fig. 5 will now be described, with reference to Figs. 7 and 8. The circuit shown in Fig. 7 is characterized in that the small cells constituting a power transistor T1 are divided into two groups. The first consisting of n times as many cells as the second group, where n is a number greater than 1. The output current I O of the power device T 1 is, therefore, divided into two parts having magnitudes n and 1, respectively. Hence, the current I O ', defined below, is supplied to the resistor R 2 . Hence, 1/(n+1) of the current I O flows to a resistor R 2 , thereby generating a low voltage V O . In this current-limiting circuit, even if the output current I O is too large, it is unnecessary to decrease the resistance of the resistor R 2 in order to obtain the low voltage V O . This helps to reduce the difference in resistance among the resistors which are to be used as resistor R 2 . The circuit shown in Fig. 8 is characterized in that a control output is obtained from the collector of a transistor Q 3 . This current-limiting circuit serves effectively, not only to limit the output current I O of the power MOSFET T 1 , but also to utilize the output current I O with high efficiency. Figs. 9 and 10 show two further examples of low-voltage detecting circuits. In the low-voltage detecting circuit shown in Fig. 3, a low voltage V O is applied to the emitter of the transistor Q 2 , and the ground voltage is applied to the emitter of the transistor Q 4 . This circuit is, there fore, a "low positive-voltage detecting circuit." By contrast, in the low-voltage detecting circuit of Fig. 9, the ground voltage is applied to the emitter of a transistor Q 2 , and a low voltage V O is applied to the emitter of a transistor Q 4 . The circuit is, there fore, a "low negative-voltage detecting circuit." In the circuit of Fig. 9, if V O > V OL , where V O is the detected voltage and V OL is a predetermined voltage, then I DET 0; and if V O ≦ V OL , I DET > 0. The circuit can, therefore, detect the low voltage V O . The low-voltage detecting circuit shown in Fig. 10 is, so to speak, a modification of the circuit shown in Fig. 9. In this circuit, the low voltage V O generated by a resistor R 2 and a current source I O . When the absolute value of a current I O decreases to or below a predetermined value I OL , a control current I DET can flow through transistors Q 1 and Q 2 , as can be understood from equation (15). When the absolute value of a current I O increases above the predetermined value I OL , the control current I DET cannot flow through the transistor Q 1 or Q 2 , as can be understood from equation (16). When I O ≦ 1 R2 · kT q ℓn(N·M) I DET > 0, When I O > 1 R2 · kT q ℓn(N·M) I DET ≈ 0, As has been explained, the above low-voltage detecting circuit can detect the low voltage V OL which is determined by the ratio of the emitter area of the transistor Q 1 to that of the transistor Q 3 , and also by the ratio of the emitter area of the transistor Q 2 to that of the transistor Q 4 . Hence, the circuit serves to limit the output current of a power device. In addition, since the output current of the power device is limited by detecting the low voltage V OL , the power loss of the low-voltage detecting circuit is far less than that of the conventional one. For instance, if M = N = 3, the circuit can detect a voltage which is about ten times lower than the base-emitter voltage V BE of the NPN transistors Q 1 to Q 4 . Further, the power MOSFET and the current-limiting circuit, both incorporated in the embodiments of Figs. 5 and 7, can be fabricated in one and the same step of the method of manufacturing an ordinary discrete power transistor. The embodiments of Figs. 5 and 7 can, therefore, provide a power device having a current-limiting section.

Claims: A current-limiting circuit comprising: a power device (T 1 ) having a control electrode; a first resistor (R 1 ) connected at one end to the control electrode of said power device (T1), and at the other end to a potential source (V1); a second resistor (R 2 ) for detecting a current output (I0) by said power device (T1); a first transistor (Q 1 ) whose base and collector are connected to each other; a second transistor (Q 2 ) whose collector is connected to the emitter of said first transistor (Q1) and whose emitter is connected to one end of said second resistor (R2); a third transistor (Q 3 ) whose base is connected to the base of said first transistor (Q1), and whose collector is connected to the control electrode of said power device (T1) and whose emitter is connected to the base of said second transistor (Q2); a fourth transistor (Q 4 ) whose base is connected to the emitter of said first transistor (Q1), and whose collector is connected to the emitter of said third transistor (Q3) and whose emitter is connected to the other end of said second transistor (Q2); and a third resistor (R 3 ) connected at one end to said potential source (V1) and at the other end to the collector of said first transistor (Q1), wherein the output current (I0) of said power device (T1) is limited when the output current (I0) of said power device (T1) increases over a predetermined value. The circuit according to claim 1, characterized in that the ratio of the emitter area of said first transistor (Q1) to that of said third transistor (Q3) is 1:N, where N is a number other than 1, and the ratio of the emitter area of said second transistor (Q2)) to that of said fourth transistor (Q4) is M:1, where M is a number other than 1. The circuit according to claim 1, characterized in that said power device (T1) is a power MOSFET. The circuit according to claim 1, characterized in that the output current I O is divided into two parts, the first part being n times greater than the second part, where n is a number greater than 1, and a current of I O /(n+1) flows to said second resistor (R2). A circuit comprising: a power device (T1) having a control electrode for receiving a control input; a resistor (R2) for detecting an output current (I O ) of said power device (T1), said resistor (R2) having a first end connected to the power device (T1) and a second end; a first transistor (Q1) whose base and collector are connected to each other, and whose collector is connected to a current source (I); a second transistor (Q2) whose collector is connected to the emitter of said first transistor (Q1), and whose emitter is connected to the first end of said resistor (Q2); a third transistor (Q3) whose base is connected to the base of said first transistor (Q1), and whose emitter is connected to the base of said second transistor (Q2); and a fourth transistor (Q4) whose base is connected to the emitter of said first transistor (Q1), whose collector is connected to the emitter of said third transistor (Q3) and whose emitter is connected to the second end of said resistor (R2), wherein an output signal (OUTPUT) is output from the collector of said third transistor (Q3) when the output current (I O ) of said power device (T1) increases over a predetermined value to limit the output current of said power device in response thereto. The circuit according to claim 5, wherein the ratio of the emitter area of said first transistor (Q1) to that of said third transistor (Q3) is 1:N, where N is a number other than 1, and the ratio of the emitter area of said second transistor (Q2) to that of said fourth transistor (Q4) is M:1, where M is a number other than 1. The circuit according to claim 5, wherein said power device (T1) is a power MOSFET.

Inventors: YAMAKAWA ISAO, YAMAKAWA, ISAO, Yamakawa, Isao, c/o Intellectual Property Div.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: H03K17
IPC codes: G01R19, H03K5, H03K17