Semiconductor integrated circuit

Abstract: A semiconductor integrated circuit having a test circuit built therein is disclosed which comprises an A/D converter to be connected to an peripheral circuit, a digital circuit connected to the A/D converter, a digital signal switching device for connecting the output of the A/D converter and that of the digital circuit selectively and a boundary scan output circuit connected to the output of the digital signal switching device connects the A/D converter to the boundary scan output circuit in a normal mode and the signal fetched in the boundary scan output circuit are outputted therefrom in test mode. Semiconductor integrated circuits having an analog circuit built therein and an analog integrated circuit in which a test circuit is built-in are also disclosed.

Description: The present invention relates to a semiconductor integrated circuit incorporating a test circuit for mass production test (referred to as a board test hereinafter) of printed circuit boards mounting semiconductor and other devices thereon. The quantity of functions incorporated into a board has been dramatically increased owing to the recent advancement of semiconductor technology. It is accordingly most important for a semiconductor integrated circuit mounted onto the board to be designed suitable for the board test in order to secure the quality of the mass-produced board. One representative technique therefor is the boundary scan employed as IEEE standard 1149.1-1990 "IEEE Standard Test Access Port and Boundary-Scan Architecture" (refer to "Simplification of Board Test by Boundary Scan" by Peter Hansen, et al. in Nikkei Electronics dated January 8, 1990, no. 490, pp. 301-7). Hereinbelow, one example of a semiconductor integrated circuit incorporating the aforementioned boundary scan test circuit will be depicted with reference to Fig. 4. Fig. 4 is a block diagram of a board mounting a conventional semiconductor integrated circuit. In Fig. 4, reference numerals denote respectively: 401 a board, 402, 403 integrated circuits A, B mounted on the board 401, 404 a digital signal input terminal of the integrated circuit A402, 405 a digital signal output terminal of the integrated circuit A402, 406 a digital signal input terminal of the integrated circuit B403 which terminal is connected to the digital signal output terminal 405, 407 a digital signal output terminal of the integrated circuit B403, 408 a digital signal input terminal of the board 401 which terminal is connected to the digital signal input terminal 404 of the integrated circuit A402, 409 a digital signal output terminal of the board 401 and connected to the digital signal output terminal 407 of the integrated circuit B403, 410 a test switching terminal connected in common to the integrated circuits A402 and B403, 411 a test signal input terminal of the board 401, 412 a test signal output terminal of the board 401, 413 a boundary scan input circuit, 414 a boundary scan output circuit, 415 a test signal output terminal of the integrated circuit A402, and 416 a test signal input terminal of the integrated circuit B403. The operation of the board mounting the conventional semiconductor integrated circuits in the structure as above will be discussed now hereinbelow. When the test switching terminal 410 is set for the normal operation mode, the boundary scan input circuit 413 of the integrated circuit A402 operates as a normal digital signal input circuit, taking a signal through the digital signal input terminal 408 into the integrated circuit A402. On the other hand, the boundary scan output circuit 414 of the integrated circuit A402 works as a normal digital signal output circuit, with outputting a signal through the digital signal output terminal 405 to the digital signal input terminal 406 of the integrated circuit B403. The integrated circuit B403 operates in the same manner as the integrated circuit A402. Therefore, the signal input through the digital signal input terminal 408 is, on the whole of the board, processed in the integrated circuits A402 and B403 and is outputted to the digital signal output terminal 409. If the mass producing quality of the board 401, that is, whether all the input/output terminals of the integrated circuits A402 and B403 are perfectly soldered is to be confirmed in this state, a signal output to the digital signal output terminal 409, when a complicated test data is input through the digital signal input terminal 408, should be compared with an expected value. According to this method, however, it is necessary to know the input/output response of the integrated circuits A402 and B403 during the normal operation beforehand, and moreover, it is difficult to specify which of the terminals is improperly connected in the case where the expected value is not obtained. The boundary scan test circuit has been devised to solve the aforementioned disadvantages. When the test switching terminal 410 is set for the test mode, the boundary scan input circuit 413 and the boundary scan output circuit 414 operate as shift registers connected in series. In other words, the signal input through the test signal input terminal 411 is, after making a round of the input/output circuit of the integrated circuit A402, outputted to the test signal output terminal 415 of the integrated circuit A402. The signal at the test signal output terminal 415 is input to the test signal input terminal 416 of the integrated circuit B403 and output to the test signal output terminal 412 of the board 401 after making a trip of the input/output circuit of the integrated circuit B403. The board 401 will be checked in a manner as described below. (1) After the test switching terminal 410 is set to the test mode, a signal to set a desired data in the digital signal output terminals 405 and 407 of the integrated circuits A402 and B403 is input through the test signal input terminal 411. The value of the digital signal output terminal 409 is first checked. (2) Then, the test switching terminal 410 is set to the normal operation mode and the signal from the digital signal input terminal 408 is taken inside through the digital signal input terminal 404 of the integrated circuit A402. The resulting signal from the digital signal output terminal 405 is taken into the integrated circuit B403 through the test signal input terminal 406. (3) The test switching terminal 410 is switched to the test mode again. The data taken into the integrated circuits A402 and B403 in the above (2) is taken outside through the test signal input terminal 412 in series and the value is checked. In the above-described procedure, it is possible to inspect the board 401 without knowing the function of the normal operation of the integrated circuits A402 and B403. Now, the integrated circuits A402 and B403 will be described more in detail with reference to Fig. 5. Fig. 5 is a block diagram indicating the internal structure of the conventional semiconductor integrated circuit, in which reference numerals respectively designate: 501 an integrated circuit, 502 to 504 digital signal input terminals (DI), 505 to 507 digital signal output terminals (DO), 508 a test switching terminal (TS), 509 a test signal input terminal (TI), 510 a test signal output terminal (TO), 511 to 513 boundary scan input circuits (CI), and 515 to 517 boundary scan output circuits (CO). Each of the boundary scan input and output circuits 511 to 513 and 515 to 517 has a digital signal input terminal D, a clock input terminal CK, a digital signal output terminal Q, a test switching terminal TS, a test signal input terminal TI, and a test signal output terminal TO. A digital circuit 514 performs the original function of the integrated circuit 501. The semiconductor integrated circuit of the above structure operates in a manner as follows. When the test switching terminal 508 is set to the normal mode, the boundary scan input circuits 511 to 513 and the boundary scan output circuits 515 to 517 serve as flip-flops, so that an input through D is output to Q and TO. Therefore, the integrated circuit 501 functions normally. Meanwhile, when the test switching terminal 508 is set for the test mode, the boundary scan input circuits 511 to 513 work as flip-flops to input a signal from TI and output the same to TO, while the boundary scan output circuits 515 to 517 work as flip-flops to have a TI input and Q and TO outputs. The TO output of the boundary scan input circuit 513 is connected to the TI input of the boundary scan output circuit 517. Accordingly, the digital signal input through the test signal input terminal 509 of the integrated circuit 501 is, passing through the six flip-flops, outputted to the test signal output terminal 510. The operation depicted with reference to Fig. 4 is thus realized. The internal structure of the boundary scan input circuits (CI) 511 to 513 and boundary scan output circuits (CO) 515 to 517 will be described by way of example with reference to Figs. 6 and 7. Fig. 6 is a circuit diagram inside the boundary scan input circuit within the conventional semiconductor integrated circuit shown in Fig. 5, in which reference numerals denote respectively: 601 a digital signal input terminal (D), 602 a clock input terminal (CK), 603 a digital signal output terminal (Q), 604 a test switching terminal (TS), 605 a test signal input terminal (TI), 606 a test signal output terminal (TO), 607 and 608 flip-flops, and 609 a digital signal switching device. The boundary scan input circuit in the above structure operates as described hereinbelow. With the test switching terminal 604 set to the normal mode, the digital signal switching device 609 is connected to the side of the digital signal input terminal 601. A data input terminal of the flip-flop 608 is connected to the output terminal of the digital signal switching device 609. Therefore, when a clock is fed to the clock input terminal 602, the data at the digital signal input terminal 601 is outputted to the digital signal output terminal 603 and the test signal output terminal 606. If the test switching terminal 604 is switched to the test mode, the digital signal switching device 609 is connected to the side of the test signal input terminal 605, so that the data at the digital signal input terminal 601 is outputted to the digital signal output terminal 603 and the data at the test signal input terminal 605 is outputted to the test signal output terminal 606. Fig. 7 illustrates an example of a circuit diagram inside the boundary scan output circuit of the conventional semiconductor integrated circuit of Fig. 5. In Fig. 7, reference numerals indicate respectively: 701 a digital signal input terminal (D), 702 a clock input terminal (CK), 703 a digital signal output terminal (Q), 704 a test switching terminal (TS), 705 a test signal input terminal (TI), 706 a test signal output terminal (TO), 707 and 708 flip-flops, and 709 a digital signal switching device. The operation of the above boundary scan output circuit will be explained below. When the test switching terminal 704 is set to the normal mode, the digital signal switching device 709 is connected to the side of the digital signal input terminal 701. Since the data inputs at the flip-flops 708 and 707 are both connected to an output of the digital signal switching device 709, the data at the digital signal input terminal 701 is outputted to the digital signal output terminal 703 and the test signal output terminal 706 when a clock is added to the clock input terminal 702. If the test switching terminal 704 is in the test mode, the digital signal switching device 709 is connected to the side of the test signal input terminal 705, and the data at the test signal input terminal 705 is outputted to the digital signal output terminal 703 and the test signal output terminal 706. The operation discussed with reference to Fig. 5 is realized by the above-described boundary scan input/output circuits. In the foregoing prior art, all the semiconductor integrated circuits on the board are supposed to be constituted of digital circuits. However, particularly in the case of processing video signals, there may be often mounted both analog circuits and digital circuits on the same board and the boundary scan method cannot meet the board test. From an article in "Proceedings of the Custom Integrated Circuit Conference, May 1989, pages 22.4.1-22.4.4, IEEE, New York, US; P.P. Fasang: "Boundary scan and its application to analog-digital ASIC testing in a board/system environment", a testing principle is known in which an integrated circuit contains boundary scan cells placed next to the signal pins. During normal application or mission function, a signal travels from the mission input through the boundary scan cell into the application circuit. The response from the application circuit travels out to the mission output pin through a second boundary scan cell. When the integrated circuit is mounted on a printed circuit board and the pins are not physically accessible, test data can be applied to the application circuit in a serial manner via the test data input pin. Likewise, the response from the application circuit can be captured into the boundary scan cell on the output board and serially shifted out via the test data output pin. In this article, also analog-digital testing is possible, but in order to manage the testing problem, the analog circuit parts must be separated from the digital circuit parts, and demultiplexers are used to observe the digitized analog input signals via the output boundary scan cells during testing, and multiplexers are used to control the digital circuit with digital test patterns applied during testing via the input boundary scan cells. It is an object of the present invention to provide a semiconductor integrated circuit having a test circuit built therein to facilitate the board testing of mass produced printing circuit boards each having both analog and digital circuits thereon, or analog circuits only. According to the invention, a semiconductor integrated circuit is structured as defined either in claim 1 or in claim 3. A preferable embodiment is defined in dependent claim 2. These and other features of the present invention will become clear from the following description taken in conjunction with the preferred embodiments thereof with reference to the accompanying drawings throughout which like parts are designated by like reference numerals, and in which: Fig. 1 is a block diagram of a board mounting a semiconductor integrated circuit according to a first embodiment of the present invention; Fig. 2 is a block diagram of a board mounting a semiconductor integrated circuit according to a second embodiment of the present invention; Fig. 3 is a block diagram of a board mounting a semiconductor integrated circuit according to a third embodiment of the present invention; Fig. 4 is a block diagram of a board mounting a conventional semiconductor integrated circuit; Fig. 5 is a block diagram inside the conventional semiconductor integrated circuit; Fig. 6 is a circuit diagram of a boundary scan input circuit within the conventional semiconductor integrated circuit of Fig. 5; and Fig. 7 is a circuit diagram of a boundary scan output circuit within the conventional semiconductor integrated circuit of Fig. 5. A semiconductor integrated circuit according to the present invention will be discussed with reference to the accompanying drawings. Fig. 1 is a block diagram of a board mounting a semiconductor integrated circuit according to a first embodiment of the present invention. As shown in Fig. 1 there are arranged an integrated circuit 102 according to the first preferred embodiment and an analog peripheral circuit 103 on a board 101. The integrated circuit 102 is comprised of an A/D converter 104 connected to the analog peripheral circuit 103 via an A/D convension input terminal 105 and reference voltage input terminals 106 and 107, a digital circuit 108 connected to outputs of the A/D converter 104, a digital signal switching device 109 consisted of an array of switching means for selecting either of outputs 110 and 111 of the A/D converter 104 and the digital circuit 108 and a boundary scan output circuit 113 connected to outputs of the digital signal switching circuit 109. The board 101 has a control terminal 112 for controlling the digital signal switching device 109 in accordance with control signals applied therethrough, a test signal input terminal 114 for inputting test signals to the boundary scan output circuit 113 in the test mode and a test signal output terminal 115 for outputting a signal resulted in response to a test signal input from the test signal input terminal 114. The operation of the board mounting the integrated circuit of the above-described structure will be depicted hereinbelow. What is different from the conventional example is that the A/D converter 104 is built in the integrated circuit 102, and the operation of the A/D converter 104 is achieved when being connected to the analog peripheral circuit 103 through the terminals 106 to 107. If the A/D converter 104 is improperly connected to the analog peripheral circuit 103 or the integrated circuit 102, this is detected from a shift of an output data of the A/D converter 104. For inspection of the connection, first, the digital signal switching device 109 is switched by the signal switching control terminal 112 to be connected to the output 110 of the A/D converter 104. At this time, the boundary scan output circuit 113 is held in the normal mode to take the outputs of the A/D converter 104 thereinto. Then, after the boundary scan output circuit 113 is set to the test mode, the output data of the A/D converter 104 is taken out from the test signal output terminal 115 in series. The taken-out data is compared with an expected value. Although an error is generated to the expected value because of the analog processing, the error is judged acceptable so long as it is within a preset allowance. According to the present embodiment, it is easily detected whether or not the analog circuit in the periphery of the A/D converter built in the digital integrated circuit is properly mounted with use of the boundary scan circuit. Fig. 2 is a block diagram of a board mounting a semiconductor integrated circuit according to a second embodiment of the present invention. In the drawing, reference numerals respectively denote: 201 a board, 202 an integrated circuit of the instant embodiment, 203 an analog peripheral circuit of the integrated circuit 202, 204 an analog circuit built in the integrated circuit 202, 205 an analog signal switching device, 206 to 207 analog signal input terminals to the integrated circuit 202, and 208 a test switching control terminal to control the analog signal switching device 205. Reference numerals 105 to 115 have the same functions as those indicated by the same references in Fig. 1. The operation of the board mounting the integrated circuit as above will be explained hereinbelow. The difference of the board of Fig. 2 from that of Fig. 1 is that both the analog circuit 204 and the A/D converter 104 are built in the integrated circuit 202. When the test switching terminal 208 is set in the normal mode, the A/D conversion signal input terminal 105 is connected to the output of the analog circuit 204, thereby performing the normal function. Meanwhile, since the test switching terminal 208 assumes two test modes, the A/D conversion signal input terminal 105 is connected either to the analog signal input terminal 206 or to the analog signal input terminal 207. Therefore, if the output of the A/D converter 104 is checked according to the same procedure as above in Fig. 1, it becomes possible to detect whether the analog signal input terminals 206, 207 or reference voltage input terminals 106, 107 are properly connected to the analog peripheral circuit 203, or whether the analog peripheral circuit 203 connected to these terminals works properly. According to the second embodiment, it is possible to detect the connecting state of the analog signal input terminals or the analog peripheral circuit even when the terminals or the circuit are directly connected to the A/D converter. Further in Fig. 3, there is shown a block diagram of a board mounting a semiconductor integrated circuit according to a third embodiment of the present invention. In Fig. 3, reference numerals denote respectively: 301 a board, 302 an analog peripheral circuit, 303 an analog integrated circuit, 304 a digital integrated circuit, 305 and 306 analog signal input terminals, 307 an A/D converter, 308 an analog signal switching device, 311 a boundary scan output circuit, 312 an analog circuit, 313 a test signal output terminal for the analog integrated circuit 303, 314 a test signal input terminal for the digital integrated circuit 304, 315 a test signal output terminal for the digital integrated circuit 304, and 316 a test signal output terminal of the board 301. The operation of the above-described board will be explained below. The board of the instant embodiment is different in that the analog integrated circuit 303 is incorporated into the boundary scan circuit. Therefore, there are provided inside the analog integrated circuit 303 the A/D converter 307, analog signal switching device 308 and boundary scan output circuits 311 for test purpose, besides the analog circuit 312. The state of the analog signal input terminals 305, 306 each of which is a connecting terminal to the analog peripheral circuit 302 is sequentially taken into the A/D converter 307 by a test switching control terminal 310 and taken out from the test signal output terminal 313 after being parallel-series converted in the boundary scan output circuits 311. Accordingly, it is detected whether or not the analog signal input terminals 305, 306 are connected well to the analog peripheral circuit 302, or the analog peripheral circuit 302 connected to these terminals is driven properly. Therefore, the third embodiment makes the board test possible even when the analog integrated circuit is built in the boundary scan circuit. As is described hereinabove, the following advantages are achieved by the present invention: (1) In a semiconductor integrated circuit comprising a digital circuit and an A/D converter, by providing digital signal switching devices to which are input outputs from the A/D converter and the digital circuit and, boundary scan output circuits connected to outputs of the digital signal switching devices, it becomes possible to inspect the connection of the semiconductor integrated circuit with an analog peripheral circuit for the A/D converter which circuit is mounted outside the semiconductor integrated circuit or the state of the analog peripheral circuit itself. (2) In a semiconductor integrated circuit comprising an analog circuit, an A/D converter and a digital circuit, by providing an analog signal switching device to which are input outputs from the analog signal input terminals and analog circuit, the A/D converter connected to an output of the analog signal switching device, the digital circuit connected to outputs of the A/D converter, digital signal switching devices to which are input outputs from the A/D converter and digital circuit, and a boundary scan output circuits connected to outputs of the digital signal switching devices, it becomes possible to inspect the connection of the semiconductor integrated circuit with an analog peripheral circuit mounted outside the semiconductor integrated circuit, or the state of the analog peripheral circuit itself. (3) In a semiconductor integrated circuit consisting of an analog circuit alone, by providing an analog signal switching device connected to outputs of analog signal input terminals, an A/D converter connected to an output of the analog signal switching device, and boundary scan output circuits connected to outputs of the A/D converter, it becomes possible, similar to the other digital semiconductor integrated circuits, to inspect the connection of the semiconductor integrated circuit with a peripheral circuit of terminals or the state of the peripheral circuit itself according to a simple inspecting program.

Claims: A semiconductor integrated circuit (102; 202) comprising an A/D converter (104) to be connected to an analog peripheral circuit (103; 203); a digital circuit (108) connected to the output side of said A/D converter (104); a digital signal switching device (109) connected to both the output side of said A/D converter (104) and the output side of said digital circuit (108) for switching its output from the output side (110) of said A/D converter (104) to the output side (111) of the digital circuit (108), or vice versa, in accordance with a switching control signal (112); and a boundary scan output circuit (113) connected to the output of said digital signal switching device (109) which is operable in a normal mode in which outputs of said digital signal switching device (109) are fetched thereinto and in a test mode in which the fetched outputs are outputted (115) therefrom sequentially in response to a test signal (114) applied thereto. A semiconductor integrated circuit according to claim 1, characterized by an analog circuit (204) connected between the analog peripheral circuit (203) and the A/D converter (104), and an analog signal switching device (205) for switching between the outputs of said analog peripheral circuit (203) and the outputs of said analog circuit (204) in accordance with a switching control signal (208). A semiconductor integrated circuit (301) comprising an analog circuit (312) to be connected, via analog signal input terminals (305, 306), to an analog peripheral circuit (302); an analog signal switching device (308) for switching the outputs of said analog peripheral circuit and the output of said analog circuit (312) in accordance with a test switching control signal (310); an A/D converter (307) connected to the output side of said analog signal switching device (308); and a boundary scan output circuit (311) connected to the output side of said A/D converter (307), said analog signal switching device (308) connecting the output (309) of said analog circuit (312) to said A/D converter (307) in a normal mode and switching the outputs (305, 306) of said analog peripheral circuit (302) sequentially to said A/D converter (307) in a test mode in accordance with said test switching control signal (310).

Inventors: IMAI KIYOSHI, TAGUCHI SEIICHI, TAKADA TAKU, TSUJI TOSHIAKI, IMAI, KIYOSHI, TAGUCHI, SEIICHI, TAKADA, TAKU, TSUJI, TOSHIAKI, IMAI, KIYOSHI, 803, LIONSMANSION NIJOJO HIGASHI
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1991
Main classification: G06F11
IPC codes: G01R31, H03M1, G06F3