Merged current clamp in triple-input transconductor, for use in oscillator

Abstract: A clamped linear transconductance amplifier path, consisting essentially of a current clamp (M23) merged in a linear transconductance amplifier (M23, M21,M22) path, is used in a triple-input, single-output transconductor (200). In a balanced transconductor in CMOS technology, this clamped linear transconductance amplifier path is formed by a p-channel MOS transistor (M23) separately connected in series with each of a matched pair of p-channel MOS transistors (M21, M22). The clamped linear transconductance amplifier path, together with two other transconductance paths (M15-M20; M9-M14), can be interconnected to form the input side of the triple-input, single-output transconductor (200). By summing and integrating the outputs of the input side of the triple-input transconductor (200), the output (VOUT,P and VOUT,N) of the output side of the transconductor can be formed. By feeding back this output to the input side of the transconductor (200), an oscillator can obtained.

Description: This invention relates to transconductors. Transconductors may be made in integrated circuit form and may find application in oscillator circuits. Oscillator circuits are useful for providing a stable frequency for use in such devices as frequency filters and mixers. In a paper by B. Linares-Barranco et al entitled "Very High Frequency CMOS OTA-C Quadrature Oscillators," published in Proc. IEEE/ISCAS 1990, International Symposium on Circuits and Systems, May 1-3, 1990, pp. 3189-3192, a block diagram of a quadrature oscillator was disclosed which included a triple-input integrator, one of the inputs being negative feedback from a single-input integrator. Another of its inputs included a positive-input path containing a clamp connected in series with an auxiliary amplifier. The use of the clamp connected in series with the auxiliary amplifier introduces added circuitry which, in turn, undesirably dissipates power and lowers the cutoff frequency. Therefore, it would be desirable to have a quadrature oscillator without these disadvantages. Summary of the Invention This invention provides a triple-input transconductor as set forth in claim 1. In addition, it is advantageous to have an oscillator comprising the triple-input transconductor recited in claim 1 combined with second and third feedback circuitry recited in claim 2. It is further advantageous that the third feedback circuitry be arranged as recited in claim 3. It is still further advantageous that the first transconductance path is balanced as recited in claim 4. And it is yet further advantageous that the second transconductance path be arranged as recited in claim 5. Brief Description of the Drawing(s) FIG. 1 is a block diagram of an oscillator containing a balanced triple-input transconductor having a current clamp that is merged with a transconductance amplifier, and FIG. 2 is a schematic circuit diagram of the triple-input transconductor, in accordance with a specific embodiment of the invention. Detailed Description Referring now to the drawings, FIG. 1 shows an oscillator 100, in a balanced circuit configuration, comprising a balanced triple-input transconductor 10 and a balanced single-input transconductor 20, as well as a first pair of matched capacitors C11 and C12 and a second pair of matched capacitors C21 and C22. The triple-input transconductor 10 has three positive input points, +a, +b, and +c, and three negative input points -a, -b, and -c, as well as one positive output point +d and one negative output point -d. Note that because both transconductors 10 and 20 are balanced, the triple-input transconductor 10 has six physical input points, and the single-input transconductor 20 has two. That is to say, in a balanced circuit configuration the term "m-input transconductor" signifies 2m physical input points. The positive output point +d of the triple-input transconductor 10 is connected to feed the input points +a and -b, as well as to feed the input point +e of the single-input transconductor 20. In addition, this positive output point +d is connected to feed one of the capacitors C11 and a positive output terminal V OUT,P of the oscillator 100. The negative output point -d of the balanced triple-input transconductor 10 is connected to feed the capacitor C12, the negative input points -a and -e, the positive input point +b, and a negative output terminal V OUT,N of the oscillator 100. The overall output of the oscillator 100 is then equal to V OUT,P -V OUT,N . The output point +f of the balanced single-input transconductor 20 is connected to feed the capacitor C21, as well as to feed the input point -c of the triple-input transconductor 10. Conversely, the output point -f of the balanced single-input transconductor 20 is connected to feed the capacitor C22, as well as to feed the input point +c of the triple-input transconductor 10. Thus, the single-input transconductor 20 delivers negative feedback to the triple-input transconductor 10. On the other hand, the triple-input transconductor 10 delivers both positive and negative input to itself. For example, the input point +a receives positive feedback from the positive output point +d, whereas the positive input point +b receives negative feedback from the negative output point -d. The triple-input transconductor 10 has another input point k, which is optional and which can be used to adjust the amplitude of oscillation. In addition, the triple-input transconductor 10 may have yet another input point g, or plurality thereof, for adjusting (tuning) the frequency of oscillation F of the oscillator 100. Likewise, the single-input transconductor 20 may have another input point h, or a plurality thereof, for adjusting the frequency of oscillation by varying the transconductance of the transconductor 20. The oscillator 100 is a quadrature oscillator because the output of the transconductor 20 is out of phase with the output of the transconductor 10 by π/2 radians. This π/2 phase shift results from the integration of the voltage V(+e) - V(e) with respect to time by the transconductor 20 operating in combination with capacitors C21 and C22. It should be understood that the circuitry for implementing the triple-input transconductor 10 consists essentially of three balanced paths running from ±a, ±b, ±c to ±d, whereby input voltages V(+a), V(-a); V(+b), V(-b); V(+c), V(-c) applied to points ±a, ±b, ±c, respectively, are converted into balanced currents I(+a), I(-a); I(+b), I(-b); and I(+c), I(-c); respectively. These currents are then summed by a pair of current summers (not shown) into I(+a) +I(+b) +I(+c) and I(-a)+I(-b)+I(-c), which are delivered to points +d and -d, respectively. The circuitry for the conversion of V(+a) and V(-a) into I(+a) and I(-a), respectively, advantageously is a linear transconductance amplifier path in which there is merged a current clamp--i.e., essentially a linear transconductance amplifier path in which, when the input voltage exceeds a predetermined amount, linearity ceases and the output current remains fixed. The circuitry for the conversion of V(+b) and V(-b) into I(+b) and I(-b), respectively, is a linear transconductance amplifier path, as is the circuitry for the conversion of V(+c) and V(-c) into I(+c) and I(-c), respectively. Referring now to FIG. 2, a balanced triple-input transconductor circuit 200 represents a schematic drawing at the transistor level of a specific embodiment of the balanced triple-input transconductor 10 described above. Terminals and points that are similar in FIGS. 1 and 2 have been given the same reference labels. The circuit 200 is basically a complementary MOS (CMOS) circuit in which transistors M1, M2, M3, and M4 are n-channel transistors, whereas M5, M6,... through M23 are all p-channel. In addition, transconductance-tuning transistors MAB...MEB and MAC...MEC are p-channel transistors. Transistors MAB...MEB and MAC...MEC are all p-channel transistors, and serve to tune (vary) the transconductance, and hence damping, of inputs applied to points ± b and ±c, respectively, as more fully explained below. During circuit operation, voltages g b1 ...g b5 are applied to the gate terminals of MAB...MEB, respectively, and voltages g c1 ...g c5 are applied to the gate terminals of MAC...MEC, respectively. Each of these voltages determine the on vs. off state of the respective transistor to which it is applied. Hence, the set of voltages g b1 ...g b5 determine the resistance between the source terminals of transistors M15 and M16--i.e., nodes N1 and N2--whereas the set of voltages g c1 ...g c5 determine the resistance between the source terminals of transistors M13 and M14. Typically, for an oscillator frequency of about 15 MHz, the resistance of each of these transistors MAB...MEB and MAC...MEC in the on state is in the range of about 5,000 to 20,000 ohms. Typically also, the input voltages g b1 ...g b5 and g c1 ...g c5 are selected such that g b1 = g c1 ,...g b5 = g c5 . The transistors MAB...MEB, by virtue of their resistive damping, serve to control the amount of negative feedback from points ∓d to points ±b. Similarly, the transistors MAC...MEC control the amount of negative feedback from points ∓f (FIG. 1) to points ±c. In addition, the transistors MAC...MEC serve to tune (vary) the oscillation frequency F, as more fully explained below. On the other hand, the amplitude of oscillation can be vied by applying a voltage to input point k, i.e., the gate terminal of M23: The amplitude of oscillations is proportional to the source-drain current flowing in the source-drain path of transistor M23. As further shown in FIG. 2, a positive power supply voltage VDD is supplied to the source terminals of M8, M7, M10, M9, M20, M19, and M23. A positive gate bias voltage BP2 is applied to the gate terminals of M8, M7, M10, M9, M20, and M19. Another positive gate bias voltage BP1 is applied to the gate terminals of M6, M5, M12, M11, M18 and M17. A gate bias voltage BN1 is applied to the gate terminals M4 and M3; and another gate bias voltage BN2 is applied to the gate terminals of M2 and M1. The source terminals of transistors M1 and M2 are connected to ground (negative power supply). These transistors are current sources. The amounts of current supplied by these sources are respectively equal to the sums of the four currents emanating from M3, M21, M15, M13 and M4, M22, M16, M14. The p-channel transistor-pair M9 and M11 form a cascode current source, as does each of the p-channel transistor-pairs M10 and M12, M7 and M5, M8 and M6, M19 and M17, and M20 and M18. Transistor M23 forms a simple tunable current source. The n-channel transistor-pair M1 and M3 also forms a cascode current source, as does the n-channel transistor-pair M2 and M4. It should be understood that in order for the transconductor 200 to oscillate, its output points ±d are respectively connected to the input points ±e of a single-input transconductor, such as 20 (FIG. 1), whose output points, such as ±f, are connected (in negative feedback polarity) to points ±c, respectively. Typically the applied bias voltages are given approximately by VDD = 5.0 volt; BP2 = 3.7 volt; BP1 = 3.1 volt; BN1 = 1.7 volt; and BN2 = 1.1 volt. Advantageously, to balance the transconductor 200, each of the following is a matched pair: M1 and M2; M3 and M4; M5 and M6; M7 and M8; M9 and M10; M11 and M12; M13 and M14; M15 and M16; M17 and M18; M19 and M20; and M21 and M22. The transistors M21 and M22 act as current steering devices, while transistor M23 acts as a current source. In response to a small signal voltage difference applied to points ±a, the increments in difference current--the difference in currents through M21 and M22--are linear with respect to the differences in applied signal voltages. However, when this signal difference exceeds a certain level, the difference current is clamped--i.e., does not change, because all of the current flowing through transistor M23 flows either through M21 or M22. Thus the transistors M21, M22, and M23 function together as a clamped linear amplifier path in which M23 is merged and acts as a clamp. The transistors in group MAB...MEB and in group MAC...MEG serve as resistors, typically five in each group. Each of their on-off states can be separately controlled by voltages g b1 ...g b5 and g c1 ...g c 5, respectively, applied to their gate terminals. These terminals correspond to the input point g(FIG. 1) of the counterpart transconductor 10. Thus the set of transistors MAB...MEB supply a controllable resistance, as does the set of transistors MAC...MEC. To explain the function served by the set of transistors MAB...MEB acting as resistors, it is instructive to start in an initial situation where the voltages applied at points ±b are equal. Thus the currents I o through M15 and M16 then will also be equal, because of circuit symmetry. Starting with this initial situation, let an incremental voltage +ΔV be applied to point +b while an incremental voltage -ΔV is applied to point -b. Then an incremental voltage +ΔV will appear at the node N1 between M15 and M17, while an incremental voltage -ΔV will appear at the node N2 between M16 and M18, provided that ΔV is sufficiently small as explained below. Consequently, a voltage increment of ΔV-(-ΔV)=2ΔV appears across nodes N1 and N2, and hence across the transistors MAB...MEB acting as resistors, whereby an incremental current i=2ΔV/R flows through them, where R is the parallel resistance of these transistors. Thus, the currents through transistors M15 and M16 become equal to I o -i and I o +i, respectively. The difference in these currents is thus equal to 2i=4ΔV/R = (2/R)(2ΔV), whereas the difference in the applied incremental voltages was equal to ΔV-(-ΔV)=2ΔV. Thus, the transconductance, and hence the reciprocal of the effective resistive damping, with respect to inputs at points ±b is equal to 2/R. Thus, by adjusting R, this transconductance can be adjusted (tuned). Similarly, by adjusting the resistance across the transistors MAC...MEC, the transconductance, and hence resistive damping, with respect to inputs at ±c can be tuned. Note that the above requirement, that ΔV be sufficiently small, is satisfied when i is much less than I o , whereby the gate-source voltage of M15 and of M16 is fixed. The process of current summing by M1, and similarly by M2, operates as follows. In response to a negative-going signal applied to point + a, for example, the current through M21 increases, whereby the current through M3 decreases, because M1 is biased as a fixed current source. On the other hand, since the current through M3 has thus decreased, and because M5 and M7 form a fixed current source, the remaining current stemming from transistors M5 and M7 flows out of point -d into capacitor C12. Similarly, in response to a positive-going signal applied to point -a, point +d draws current from C12. Similar considerations apply to signals applied to points ±b and ±c. As mentioned above, voltages g c1 ...g c5 applied to transistors MAC...MEC tune the frequency F of oscillation of the oscillator 100 (FIG. 1). This property can be deduced from the fact that the frequency F basically is given by the transconductance of the triple-input transconductor 10 with respect to input voltages applied to points ±c divided by the series-connected capacitance of the matched capacitors C11 and C12. Thus, F is basically given by 2πF = (2/R c ) + C/2 = 4/R c C, where R c is the parallel-connected resistance of the set MAC...MEC (FIG. 2) and C = C11 = C12, assuming that the ±e inputs of transconductor 20 have the same transconductances as those of the ±c inputs of the transconductor 10 and that C21 = C22 = C11 = C12. Thus, by varying the voltages g c1 ...g c5 , the parallel resistance of MAC...MEC can be varied, and hence the oscillation frequency F can be tuned. Note that (within reasonable limits of operation), transistors M5, M6, M7, M8, M9, M10, M11, M12, M17, M18, M19 or M20 operate in their respective saturation regions, primarily because of the presence of the two bias voltages BP1 and BP2 applied to transistors ( e.g. , M17, M19) whose source-drain paths are connected in series. Although the invention has been described in detail with respect to specific embodiments, various modifications can be made without departing from the scope of the invention. For example, the transconductors 10 and 20 need not be balanced--in which case the retained points are, for example, a, -b, -c, +d, +e, and +f. Also, in the circuit 200 p- and n-channel MOS transistors can be everywhere interchanged.

Claims: A triple-input amplifier characterized by a triple-input transconductor (200) comprising (a) a first transconductance amplifier path (M21, M22, M23), the path having a first output current point and a first input voltage point (+a, -a), a current clamp (M23) being merged in the amplifier path; (b) a second transconductance amplifier path (M15, M16, M17, M18, M19, M20) comprising a second output current point and a second input voltage point (+b, -b); (c) a third transconductance amplifier path (M9, M10, M11, M12, M13, M14) comprising a third output current point and a third input voltage point (+c, -c); (d) integration circuitry (M1, C12, M2, C11) for summing and integrating first, second, and third currents flowing from the first, second, and third output points, respectively, whereby an output voltage (V OUT,P ; V OUT,N ) is produced; and (e) first feedback circuitry for positively feeding back the output voltage to the first input voltage point (+a, -a). An oscillator characterized by the triple-input transconductor recited in claim 1 and second and third feedback circuitry for negatively feeding back separately the output voltage to the second (+b, -b) and third (+c, -c) input voltage points, respectively. The oscillator of claim 2 characterized further in that the third feedback circuitry includes a single-input transconductor (20). The triple-input amplifier of claim 1 characterized further in that the first transconductance path is balanced and consists essentially of a p-channel MOS transistor (M23) whose source-drain path is connected separately in series with each of the source-drain paths of a pair of p-channel MOS transistors (M21, M2). The triple-input amplifier of claim 4 characterized further in that the second transconductance path consists essentially of at least a first MOS transistor (M17) having its source-drain path connected in series with the source-drain path of at least a second MOS transistor (M15), whereby a first node (N1) is formed between the source-drain paths of the first and second transistors, at least a third transistor (M18) having its source-drain path connected in series with the source-drain path of at least a fourth MOS transistor (M16), whereby a second node (N2) is formed between the source-drain paths of the third and fourth transistors, and at least a fifth MOS transistor (MAB) having its source-drain path connected across the first and second nodes.

Inventors: KHOURY JOHN MICHAEL, KHOURY, JOHN MICHAEL
Applicants: AT & T CORP, AT&T CORP.
Application year: 1991
Main classification: H03F3
IPC codes: H03B5, H03F1, H03B27, H03F3, H03B1