Semiconductor memory device

Abstract: A semiconductor memory device has pairs of complementary bit lines connected to pairs of complementary data bus lines via transfer elements controlled by column lines. The bit lines are arranged so that mutually adjacent pairs of bit lines are connected to the same pair of data bus lines at a pair of common nodes. The transfer elements for each such mutually adjacent pair of bit lines are controlled by different column lines.

Description: BACKGROUND OF THE INVENTION This invention relates to a semiconductor memory device, more specifically to the arrangement of its bit lines and their connections to the data bus. A semiconductor memory device has a memory cell array from which bit lines carry data to sense amplifiers, which place amplified data on an internal data bus. The bit lines and data bus lines are actually complementary pairs of lines, one carrying the data value and the other the inverse of that value. Modern semiconductor memory devices are frequently subdivided into two or more memory cell arrays, each with separate bit lines and sense amplifiers which may be shared by adjacent memory cell arrays, and have two or more pairs of data bus lines. Interconnections between the bit lines and data bus lines are controlled by switching elements, called transfer means, that operate in response to column signals. In a device with two pairs of data bus lines, for example, each column signal selects two pairs of bit lines, connecting one bit line pair to one data bus pair, and the other bit line pair to the other data bus pair. In the prior art, the bit line pairs are laid out in an order that alternates between one data bus line and the other. This scheme permits the two bit line pairs selected by the same column signal to be disposed side by side, but has the disadvantage that each bit line must be connected to the data bus at a separate node. This imposes a limitation to the reduction in the bit line pitch, and hence to the increase in the degree of integration. The article "A 46-ns- 1-Mbit CMOS SRAM" by Shimada et al in IEEE Journal of Solid-State Circuits, p. 53 to 58 discloses a semiconductor memory device according the pre-characterizing part of claim 1. This semiconductor memory device achieves a small standby power of 25 µW, an active power of 80 mW at 1-MHz write operation and a short access time of 46 ns by employing a PMOS bit-line dc load to reduce power dissipation in the write cycle and by using four-block access mode to reduce the testing time. The bit line pitch, however, is reletively large as is usual in the state of the art. SUMMARY OF THE INVENTION It is accordingly an object of the present invention to enable further reduction in the bit line pitch, and hence increase in the degree of integration. This object is achieved by a semiconductor memory device as defined in claim 1. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic diagram showing a memory device comprising two memory cell arrays with a block of sense amplifiers and transfer transistors interposed between the two memory cell arrays. Figure 2 is a circuit diagram illustrating the pertinent portion of the memory device of Figure 1. Figure 3A, Figure 3B and Figure 3C are layout diagrams illustrating respective layers of the pertinent portion of the memory device of Figure 1. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device with a novel arrangement of bit lines, their connections with data bus lines, and other elements will be described with reference first to circuit diagrams in Figure 1 and Figure 2, then to an actual layout diagrams in Figure 3A to Figure 3C. The semiconductor memory device shown will be a dynamic random access memory (RAM). The drawings depict one embodiment of the invention but do not restrict its scope, which should be Judged from the appended claims. Figure 1 shows a memory device which comprises a pair of memory cell arrays CA1 and CA2 each consisting of memory cells arranged in row and columns to form a matrix,a block ST of sense amplifiers and transfer transistors, first and second row decoders RD1 and RD2, and first and second column decoders CD1 and CD2. The sense amplifiers are shared by the two memory cell arrays CA1 and CA2. Figure 2 is a circuit diagram showing electrical connection of sense amplifiers, transfer transistors, and related components. Figure 2 shows four sense amplifiers 30 m , 30 m+1 , 30 m+2 , and 30 m+3 and their associated circuit lines. Each of the sense amplifiers 30 m to 30 m+3 comprises a pair of first and second NMOS transistors 31 x and 31 x (x = m, m+1, m+2, or m+3). A bit line BL x (x = m, m+1, m+2 or m+3) is connected to the drain of the first NMOS transistor 31 x , and the gate of the second NMOS transistor 31 x . A complementary bit line BL x is connected to the drain of the second NMOS transistor 31 x , and the gate of the first NMOS transistor 31 x . The sources of the NMOS transistors 31 x and 31 x are connected to a common sense clock (  S ) line. The function of the sense clock line  S is to activate the sense amplifier 30 x . When the clock line  S is driven active, the small potential difference between the BL and BL lines is amplified so that one of these bit lines is pulled up to the logic 1 level while the other is pulled down to the logic 0 level. The sense amplifiers 30 m , ... 30 m+3 are connected to pairs of bit lines (BL m , BL m ), ... (BL m+3 , BL m+3 ) having matching subscripts. The common clock line  S , which is connected to all the sense amplifiers 30 m , ..., 30 m+3 , crosses the bit lines BL x and BL x (x = m, ..., m+3) at right angles. The bit line pairs are arranged in the order (BL m , BL m ), (BL m+2 , BL m+2 ), (BL m+1 , BL m+1 ), (BL m+3 , BL m+3 ). The effect of the invention depends on the order of the pairs, but not on the order of the two bit lines within each pair. Each pair of bit lines (BL x , BL x ) is connected to a column of memory cells in a memory cell array. When the memory device is read, one of the memory cells in the column is selected by means of a word line (not shown as such) and a row decoder RD1 and RD2, and the data value stored in the selected memory cell appears as a slight potential difference between the bit lines BL x and BL x . This potential difference is amplified by the sense amplifier 30 x as described above. A column line CL n is disposed between the bit line pairs (BL m , BL m ) and (BL m+2 , BL m+2 ). Another column line CL n+1 is disposed between the bit line pairs (BL m+1 , BL m+1 ) and (BL m+3 , BL m+3 ). An auxiliary line CL n ' connected by bridging line CL n " is disposed between the bit line pairs (BL m+1 , BL m+1 ) and (BL m+3 , BL m+3 ). Another auxiliary line CL n+1 ' connected to a bridging line CL n+1 "is disposed between the bit line pairs (BL m , BL m ) and (BL m+2 , BL m+2 ). As transfer means, the device in Figure 2 has transfer transistors comprising NMOS transistors 40 m , 40 m , ..., 40 m+3 , 40 m+3 . The purpose of the transfer means is to connect the bit lines BL m , BL m , ..., BL m+3 , BL m+3 and sense amplifiers 30 m , ..., 30 m+3 to pairs of complementary data bus lines (DB₀, DB ₀) and (DB₁, DB ₁), disposed perpendicular to the bit lines. The transfer means are controlled by the column lines, together with the auxiliary lines, so that only one pair of bit lines is connected to a given pair of data bus lines at a time. Accordingly, transfer means that connect different bit lines to the same data bus line are controlled by different column lines. The transfer transistor 40 m is connected at its source to the bit line BL m and the sense amplifier 30 m . In like manner, the sources of the transfer transistors 40 m , ..., 40 m+3 , 40 m+3 are connected to bit lines BL m , ..., BL m+3 , BL m+3 and sense amplifiers 30 m , ..., 30 m+3 with matching subscripts. The gate electrodes of the transfer transistors 40 m and 40 m are connected directly to the column line CL n . The gate electrodes of the transfer transistors 40 m+1 and 40 m+1 are connected to the column line CL n via auxiliary line CL n '. The gate electrodes of the transfer transistors 40 m+2 and 40 m+2 are connected to the column line CL n+1 via auxiliary line CL n+1 '. The gate electrodes of the transfer transistors 40 m+3 and 40 m+3 are connected directly to the column line CL n+1 . The drains of the transfer transistors 40 m and 40 m+2 are connected to the data bus line DB₀ at the common node P m/m+2 . The transfer transistors 40 m and 40 m+2 therefore connect the data bus line DB₀ to the bit line BL m when the column line CL n is driven active, and to the bit line BL m+2 when the column line CL n+1 is driven active. Similarly, the transfer transistors 40 m and 40 m+2 connect the data bus line DB ₀ to the bit line BL m or BL m+2 at the common node P m/m+2 , the transfer transistors 40 m+1 and 40 m+3 connect the data bus line DB₁ to the bit line BL m+1 or BL m+3 at the common node P m+1/m+3 , and the transfer transistors 40 m+1 and 40 m+3 connect the data bus line DB ₁ to the bit line BL m+1 or BL m+3 at the common node P m+1/m+3 . In a write operation in which the column line CL n is driven active and the column line CL n+1 is driven inactive, data are transferred from the data bus pairs (DB₀, DB ₀) and (DB₁, DB ₁) via the common nodes P m/m+2 , P m/m+2 , P m+1/m+3 , and P m+1/m+3 and the transfer transistors 40 m , 40 m , 40 m+3 , and 40 m+3 to the sense amplifiers 30 m and 30 m+3 , respectively. The transferred data are written via the bit line pairs (BL m , BL m ) and (BL m+3 , BL m+3 ) to memory cells selected by a row decoder RD1 and RD2. A semiconductor memory device normally has many more bit lines and column lines than shown in the drawing. The other lines can be arranged in a fashion analogous to Figure 2, with two bit lines connected to each data bus line at a common node. In the above described arrangement, adjacent pairs of transfer transistors 40 m and 40 m ; and 40 m+2 , 40 m+2 are connected through common nodes to the data bus line pair DB₀ and DB ₀. Similarly, adjacent pairs of transfer transistors 40 m+1 and 40 m+1 ; and 40 m+3 , 40 m+3 are connected through common nodes to the data bus line pair DB₁ and DB ₁. Accordingly, each data bus line needs only to be connected via a contact hole to the transfer transistor at every four pairs of bit lines. This is in contrast to the prior art scheme in which each data bus line needs to be connected via a contact hole to the transfer transistor at every two pairs of bit lines. The reduction in the number of contact holes for connection with the data bus lines with the transfer transistors enables reduction in the bit line pitch, and hence increase in the degree of integration. Fuller understanding will be had from the following description made with reference to the Figure 3A to Figure 3C showing layouts of the respective layers forming the transistors and interconnections of Figure 2. Figure 3A shows, in solid lines, active regions 50 formed in the semiconductor substrate, and is comprised of doped semiconductor regions, and shows, in broken lines, polysilicon layers, and part of metal layers, in phantom lines. Figure 3B shows, in solid lines, polysilicon layers forming the bit lines BL m , BL m , BL m+2 , BL m+2 , BL m+1 , BL m+1 , BL m+3 , BL m+3 , column lines CL n , and CL n+1 , and auxiliary lines CL n ' and CL n+1 '. Figure 3B also shows, in dotted lines, the active regions 50, and part of the metal layers in phantom lines. Figure 3C shows, in solid lines, metal layers forming data bus lines DB₀, DB ₀, DB₁, and DB ₁, clock line  S 64, bridging lines CL n " and CL n+1 " for connecting the auxiliary lines CL n ' and CL n+1 ' to the column lines CL n and CL n+1 , and bridging lines 74 for connecting pieces 65 of bit lines BL m , BL m+1 , BL m+2 , and BL m+3 at portions where the bit lines pairs are "twisted", or where the bit lines of each pair are positionally exchanged for forming a flip-flop type sense amplifier. Figure 3C also shows, in broken lines, the polysilicon layers, and the active regions in dotted lines. As shown in Figure 3A, Figure 3B and Figure 3C, the bit lines are connected to the junction regions of the active regions 50 by means of junction-polysilicon ohmic contacts 61, which extend through the contact holes. As shown in Figure 3A and Figure 3C, the clock line 64 is connected to the junction regions 50 by means of junction-metal contacts 62 extending through contact holes. The metal bridging lines 74, shown in solid lines in Figure 3C and in broken lines in Figure 3B, are connected to the polysilicon bit lines BL x by metal-polysilicon contacts 75 extending through contact holes. The bridging lines CL n " and CL n+1 ", shown in solid lines in Figure 3C and in broken lines in Figure 3B, are connected to the polysilicon column lines CL n and CL n+1 and the polysilicon auxiliary lines CL n ' and CL n+1 ', by means of polysilicon-metal contacts 71 extending through contact holes. As shown in Figure 3C as well as in Figure 3A, the active regions 50 includes first and second main parts 50a and 50b extending in parallel with the data bus lines, and parts lateral projections 50e, 50f, 50g and 50h which extend laterally, i.e., in the direction of bit lines, from the first and second main parts 50a and 50b of the active region 50 at locations adjacent the drains of the transfer transistors, to form the data bus line interconnections DB₀', DB ₀', DB₁' and DB ₁' (Figure 2) which are connected to the data bus lines DB₀, DB ₀, DB₁ and DB ₁ by means of contacts 70e, 70f, 70g, 70h extending through contact holes, thereby to form the common nodes P m/m+2 , P m/m+2 , P m+1/m+3 and P m+1/m+3 . Transistors 31 m , ..., 31 m+3 forming the transfer means are formed where the bit lines BL x cross the first main part 50a of the active region. Transistors 31 m , ..., 31 m+3 forming the transfer means are formed where the bit lines BLx cross the second main part 50b of the active region. Transfer transistors 40 m , ..., 40 m+3 are formed where the column lines CL n and CL n+1 cross the first main part 50a of the active region 50. Transfer transistors 40 m , ..., 40 m+3 are formed where the column lines CL n and CL n+1 cross the second main part 50b of the active region 50. The lateral projections 50e to 50h are disposed at points intermediate between these transfer transistors. Where there are more than four pairs of bit lines, the pattern shown in Figure 3A to Figure 3C is repeated. It will be seen that the connection by contacts 70e to 70h between the data bus lines and the transfer transistors 40 x and 40 x (x = m, m+1, m+2, m+3) are provided each for the four pairs of the bit lines, and each data bus line (e.g., DB₀) is connected by the contact hole (70e) to the transfer transistors (40 m and 40 m+2 ) at every four pairs of bit lines. Thus, the space needed for the contacts (70e, 70f, etc.) is reduced. In a layout such as the one shown in Figure 3A to Figure 3C, it is necessary for the clock (  S ) contacts 62 to be on opposite sides (in the top-to-bottom direction) of the sense amplifiers 30 m , ..., 30 m+3 from the nodes (P m/m+2 , P m / m+2 , P m+1/m+3 , and P m+1/m+3 ) connecting the sense amplifiers to the data bus lines. The virtue of the novel arrangement is that it enables this condition to be satisfied without requiring a separate node for each interconnection between a data bus line and a bit line via a transfer transistor. It therefore becomes possible to lay out even a high-density VLSI memory with an extremely narrow bit line pitch. The circuits shown in the drawings can be modified in various ways without departing from the scope of the invention. For example: the sense amplifiers 30 m to 30 m+3 may have circuit configurations differeing from Figure 2; the transfer means may comprise transistors other than the transfer transistors 40 m , 40 m, ..., 40 m+3 ; the transfer means may be connected directly to the sense amplifier nodes; fabrication patterns other than those shown in Figure 3A to Figure 3C may be used; and this invention can be applied not only to dynamic RAMs but to other semiconductor memory devices as well, such as static RAMs.

Claims: A semiconductor memory device comprising: a first pair of data bus lines (DB₀, DB ₀) extending in a first direction; a second pair of data bus lines (DB₁, DB ₁) extending substantially parallel to said first pair of data bus lines; a first pair of bit lines (BL m , BL m ) extending in a second direction substantially perpendicular to said first direction; a second pair of bit lines (BL m+2 , BL m+2 ) being adjacent to said first pair of bit lines and extending substantially parallel to said first pair of bit lines; a third pair of bit lines (BL m+1 , BL m+1 ) extending substantially parallel to said first pair of bit lines; a fourth pair of bit lines (BL m+3 , BL m+3 ) being adjacent to said third pair of bit lines and extending substantially parallel to said first pair of bit lines; a first sense amplifier (30 m ) coupled to said first pair of bit lines (BL m , BL m ); a second sense amplifier (30 m+2 ) coupled to said second pair of bit lines (BL m+2 , BL m+2 ); a third sense amplifier (30 m+1 ) coupled to said third pair of bit lines (BL m+1 , BL m+1 ); a fourth sense amplifier (30 m+3 ) coupled to said fourth pair of bit lines (BL m+3 , BL m+3 ); a first pair of transfer transistors (40 m , 40 m ) connecting said first pair of bit lines (BL m , BL m ) with said first pair of data bus lines (DB₀, DB ₀); a second pair of transfer transistors (40 m+2 , 40 m+2 ) connecting said second pair of bit lines (BL m+2 , BL m+2 ) with said first pair of data bus lines (DB₀, DB ₀); a third pair of transfer transistors (40 m+1 , 40 m+1 ) connecting said third pair of bit lines (BL m+1 , BL m+1 ) with said second pair of data bus lines (DB₁, DB ₁); and a fourth pair of transfer transistors (40 m+3 , 40 m+3 ) connecting said fourth pair of bit lines (BL m+3 , BL m+3 ) with said second pair of data bus lines (DB₁, DB ₁); characterised in that said first and second pairs of transfer transistors (40 m , 40 m , 40 m+2 , 40 m+2 ) are located between said first and second pairs of bit lines (BL m , BL m , BI m+2 , BL m+2 ), and said third and fourth pairs of transfer transistors (40 m+1 , 40 m+1 , 40 m+3 , 40 m+3 ) are located between said third and fourth pairs of bit lines (BL m+1 , BL m+1 , BL m+3 , BL m+3 ). The device according to Claim 1 further comprising: a first column line (CL n ) coupled to said first pair of transfer transistors (40 m , 40 m ) and driving said first pair of transfer transistors (40 m , 40 m ); a second column line (CL n+1 ) coupled to said second pair of transfer transistors (40 m+2 , 40 m+2 ) and driving said second pair of transfer transistors (40 m+2 , 40 m+2 ); a first auxiliary line (CL n ') coupled to said third pair of transfer transistors (40 m+1 , 40 m+1 ) and driving said third pair of transfer transistors (40 m+1 , 40 m+1 ); a second auxiliary line (CL n+1 ') coupled to said fourth pair of transfer transistors (40 m+3 , 40 m+3 ) and driving said fourth pair of transfer transistors (40 m+3 , 40 m+3 ); and a first bridging line (CL n ") connecting said first auxiliary line (CL n ') with said first column line (CL n ); and a second bridging line (CL n+1 ") connecting said second auxiliary line (CL n+1 ') with said second column line (CL n+1 ). The device accqrding to Claim 2 wherein said first and second column lines (CL n , CL n+1 ) and first and second auxiliary lines (CL n ', CL n+1 ') extend substantially parallel to said first pair of bit lines (BL m , BL m ). The device according to one of the Claims 1 to 3 wherein said first pair of data bus lines (DB₀, DB ₀) include first and second data bus lines which are substantially parallel to each other, and said sense amplifiers (30 m , 30 m+2 , 30 m+1 , 30 m+3 ) and said pairs of transistors (40 m , 40 m , 40 m+2 , 40 m+2 , 40 m+1 , 40 m+1 , 40 m+3 , 40 m+3 ) are located between said first and second data bus lines, and said second pair of data bus lines (DB₁, DB ₁) include third and fourth data bus lines which are substantially parallel to each other and said first and second data bus lines are located between said third and fourth data bus lines. The device according to one of the Claims 1 to 4 wherein said first pair of transfer transistors (40 m , 40 m ) have first and second transistors, said second pair of transfer transistors (40 m+2 , 40 m+2 ) have third and fourth transistors, said third pair of transfer transistors (40 m+1 , 40 m+1 ) have fifth and sixth transistors, and said fourth pair of transfer transistors (40 m+3 , 40 m+3 ) have seventh and eighth transistors; said first to eighth transistors each having first and second electrodes; the first electrodes of said first and second transistors being respectively coupled to said first pairs of bit lines (BL m , BL m ), the second electrodes of said third and fourth transistors being respectively coupled to said second pair of bit lines (BL m+2 , BL m+2 ), and the second electrodes of said first and second transistors being respectively connected to the first electrodes of said third and fourth transistors through first and second nodes; and the first electrodes of said fifth and sixth transistors being respectively coupled to said third pairs of bit lines (BL m+1 , BL m+1 ), the second electrodes of said seventh and eighth transistors being respectively coupled to said fourth pair of bit lines (BL m+3 , BL m+3 ), and the second electrodes of said fifth and sixth transistors being respectively connected to the first electrodes of said seventh and eighth transistors through third and fourth nodes. The device according to Claim 5, wherein said first pair of data bus lines (DB₀, DB ₀) includes first and second data bus lines which are substantially parallel to each other, said first data bus line (DB₀) being connected to said first node connecting the second electrode of said first transistor (40 m ) and the first electrode of said third transistor (40 m+2 ), and said second data bus line ( DB ₀) being connected to said second node connecting the second electrode of said second transistor ( 40 m ) and the first electrode of said fourth transistor ( 40 m+2 ); and wherein said second pair of data bus lines (DB₁, DB ₁) includes third and fourth data bus lines which are substantially parallel to each other, said third data bus line (DB₁) being connected to said third node connecting the second electrode of said fifth transistor (40 m+1 ) and the first electrode of said sixth transistor (40 m+3 ), and said fourth data bus line ( DB ₁) being connected to said fourth node connecting the second electrode of said fifth transistor ( 40 m ) and the first electrode of said fourth transistor ( 40 m+2 ). The device according to Claim 1 wherein said second pair of bit lines (BL m+2 , BL m+2 ) is located between said first pair of bit lines (BL m , BL m ) and said third pair of bit lines (BL m+1 , BL m+1 ), and said third pair of bit lines (BL m+1 , BL m+1 ) is located between said second pair of bit lines (BL m+2 , BL m+2 ) and said fourth pair of bit lines (BL m+3 , BL m+3 ).

Inventors: TAKANO TSUNEO, UESUGI MASARU, TAKANO, TSUNEO, UESUGI, MASARU, TAKANO, TSUNEO, C/O OKI ELECTRIC INDUSTRY CO. LTD., UESUGI, MASARU, C/O OKI ELECTRIC INDUSTRY CO. LTD.
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY CO., LTD.
Application year: 1991
Main classification: G11C7
IPC codes: G11C11, H01L21, H01L27, G11C7