High quality active matrix-type display device

Abstract: In an active matrix-type display device where scan bus lines (S i ) and data bus lines (D j ) are formed on different substrates, two kinds of scan bus lines (SP i , SN i ) are provided. A first switching element (TFTN ij ) is connected between a reference voltage supply line (V R ) and a display electrode (E ij ), and is controlled by a first scan bus line (SN i ), and a second switching element (TFTP ij ) is connected between the reference voltage supply bus line (V R ) and the display electrode, and is controlled by a second scan bus line (SP i ). The first switching element (TFTN ij ) is turned ON by a positive or negative potential at the first scan bus line.

Description: BACKGROUND OF THE INVENTION 1. Filed of the Invention The present invention relates to an active matrix-type display device using an electro-optic material such as liquid crystal, and more particularly, to an active matrix-type display device without intersections between scan bus lines and data bus lines on the same substrate. 2. Description of the Related Art An active matrix-type liquid crystal display device as well as a simple matrix-type liquid crystal display device is thin, and therefore, is often used in various display devices. In this active matrix-type liquid crystal display device, since individual pixel elements are independently driven, the contrast is not reduced based upon the reduction of a duty ratio, and the angle of visibility is not reduced, even when the capacity of display is increased to increase the number of lines. Therefore, the active matrix-type liquid crystal display device can enable a color display in the same way as in a cathode ray tube (CRT), and is prevalent in flat display devices. In the active matrix-type liquid crystal display device, however, since one thin film transistor as a switching element is provided for each pixel, a complex manufacturing process is required, and equipment therefor is expensive. Also, the manufacturing yield is low. Thus, the active matrix-type liquid crystal display device is very expensive. Therefore, a panel formed by an active matrix-type liquid crystal display device has to be of a small size. Also, in order to improve the low manufacturing yield due to the complex configuration of the active matrix-type liquid crystal display device, there has been suggested a counter-matrix active matrix-type liquid crystal device in which scan bus lines and data bus lines are formed on different substrates, so that intersections of scan bus lines and data bus lines on the same substrate are not used (see: U.S. Patent Nos. 4,694,287, 4,717,244, 4,678,282). In any type of active matrix-type liquid crystal device (such as in EP-A-0 259 875), a liquid crystal voltage fluctuates due to the generation of a DC component therein, to reduce the quality of display. For example, flickers and residual images may be generated. Particularly, for a stationary image, a burning phenomenon may occur. Also, the life-time of active matrix-type liquid crystal devices may be shortened. SUMMARY OF THE INVENTION An object of the present invention is to improve the quality of display in an active matrix-type display device, particularly, such a as a counter-matrix type display device. According to the present invention, in an active matrix-type display device where scan bus lines and data bus lines are formed on different substrates, two kinds of scan bus lines are provided. A first switching element such as an N-channel type thin film transistor connected between a reference voltage supply line and a display electrode and is controlled by a first scan bus line, and a second switching element such as a P-channel type thin film transistor is connected between the reference voltage supply bus line and the display electrode, and is controlled by a second scan bus line. The first switching element is turned ON by a positive or negative potential at the first scan bus line. Both of the first and second switching elements are operated to compensate for a DC component. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be more clearly understood from the description as set forth below with reference to the accompanying drawings, wherein: Fig. 1 is a block circuit diagram illustrating a general liquid crystal display device including control portions; Fig. 2 is an equivalent circuit diagram illustrating a prior art active matrix-type liquid crystal device; Fig. 3 is an equivalent circuit diagram illustrating a prior art counter-matrix active matrix-type liquid crystal device; Fig. 4 is an exploded, perspective view of the device of Fig. 3; Fig. 5 is a circuit diagram illustrating an embodiment of the active matrix-type crystal display device according to the present invention; Figs. 6A, 6B, and 6C are timing diagrams showing the signals in the circuit of Fig. 5; Figs. 7A through are timing diagrams showing the signals in the circuit of Fig. 1 for generating the signals of Figs. 6A and 6B; Fig. 8 is a circuit diagram illustrating a second embodiment of the active matrix-type liquid crystal display device according to the present invention; Figs. 9A, 9B, and 9C are timing diagrams showing the signals in the circuit of Fig. 8; Figs. 10A through 10H are timing diagrams showing the signals in the circuit of Fig. 1 for generating the signals of Figs. 9A and 9B; Fig. 11 is a circuit diagram illustrating a third embodiment of the active matrix-type liquid crystal display device according to the present invention; Figs. 12A, 12B, 12C, and 12D are timing diagram showing the signals in the circuit of Fig. 11; Figs. 13A through 13H are timing diagrams showing the signals in the circuit of Fig. 1 for generating the signals of Figs. 12A and 12B; Fig. 14 is a circuit diagram illustrating a fourth embodiment of the active matrix-type liquid crystal display device according to the present invention; Figs. 15A through 15G are timing diagrams showing the signals in the circuit of Fig. 14; Figs. 16A through 16H are timing diagrams showing the signals in the circuit of Fig. 1 for generating the signals of Figs. 15A and 15B; Fig. 17 is a circuit diagram illustrating a fifth embodiment of the active matrix-type liquid crystal display device according to the present invention; Figs. 18A through 18H are timing diagrams showing the signals in the circuit of Fig. 17; Fig. 19 is a circuit diagram illustrating a sixth embodiment of the active matrix-type liquid crystal display device according to the present invention; Fig. 20 is circuit diagram illustrating a seventh embodiment of the active matrix-type liquid crystal display device according to the present invention; Figs. 21A through 21H are timing diagrams showing the signals in the circuit of Fig. 20; Figs. 22A through 22H are timing diagrams showing the signals in the circuit of Fig. 1 for generating the signals of Figs. 21A and 21B; Fig. 23 is a circuit diagram illustrating an eighth embodiment of the active matrix-type liquid crystal display device according to the present invention; Fig. 24 is a layout diagram of the device of Fig. 23; Figs. 25A through 25F are timing diagrams showing the signals in the circuit of Figs. 23 and 24; Fig. 26 is a cross-sectional view of the device of Fig. 24 taken along the line A - A′; Fig. 27 is a diagram showing an example of the transmissibility characteristic of a crystal liquid cell; Figs. 28A, 28B, and 28C are modifications of Figs. 25A, 25B, and 25C, respectively; Figs. 29A through 29H are timing diagrams showing the signals in the circuit of Fig. 1 for generating the signals of Figs. 25A and 25B; Fig. 30 is a layout diagram illustrating a ninth embodiment of the active matrix-type liquid crystal display device according to the present invention; Fig. 31 is a layout diagram illustrating a tenth embodiment of the active matrix-type liquid crystal display device according to the present invention; Figs. 32A through 32E are modifications of Figs. 25A, 25B, and 25C; Figs. 33A through 33H are timing diagrams showing the signals in the circuit of Fig. 1 for generating the signals of Figs. 32A and 32B; Figs. 34 is a layout diagram illustrating an eleventh embodiment of the active matrix-type liquid crystal display device according to the present invention; Figs. 35A through 35F are timing diagrams showing the signals in the circuit of Fig. 34; Fig. 36 is a circuit diagram illustrating a twelfth embodiment of the active matrix-type liquid crystal display device according to the present invention; Figs. 37A through 40A are layout diagrams explaining the manufacturing steps of the device of Fig. 36; Figs. 37B through 40B are cross-sectional views explaining the manufacturing steps of the device of Fig. 36; Fig. 41 is a circuit diagram illustrating a thirteenth embodiment of the active matrix-type liquid crystal display drive according to the present invention; Figs. 42A through 45A are layout diagrams explaining the manufacturing steps of the device of Fig. 41; Figs. 42B through 45B, and Figs. 42C through 45C are cross-sectional views explaining the manufacturing steps of the device of Fig. 41; Fig. 46 is a circuit diagram illustrating a fourteenth embodiment of the active matrix-type liquid crystal display device according to the present invention; Figs. 47A through 50A are layout diagrams explaining the manufacturing steps of the device of Fig. 46; Figs. 47B through 50B and Figs. 47C through 50C are cross-sectional views explaining the manufacturing steps of the device of Fig. 46, and Fig. 51 is a layout diagram illustrating a fifteenth embodiment of the active matrix-type liquid crystal device according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Before the description of embodiments of the present invention, prior art liquid crystal display devices will be explained with reference to Figs. 1 through 4. In Fig. 1, which illustrates a general liquid crystal display device including control portions, reference numeral 1 designates a liquid crystal panel having a plurality of scan bus lines S i (i = 0, 1, 2, .......) and a plurality of data bus lines D j (j = 0, 1, 2, ......) which are arranged in parallel with each other. The scan bus lines S i are scanned by two scan synchronization circuits 2 and 2′, and the data bus lines D j are driven by two data bus drivers 4 and 4′. The scan synchronization circuit 2 (2′) is formed by a shift register 21 for shifting a shift data SD₁ (SD₂) in accordance with a shift clock signal SCK₁ (SCK₂), and analog switches 22 (22′) which receives a rectangular wave signal SC OUT1 (SC OUT2 ) generated from a swith circuit 3(3′). The analog switches 22 (22′) pass the rectangular wave signal SC OUT1 (SC OUT2 ) in accordance with the outputs of the shift register 21 (21′). Two voltages V₁ and V₂ (V₁′ and V₂′) are applied to the switch circuit 3 (3′) for determining a maximum level and a minimum level of the output signal SC OUT1 (SC OUT2 ). Also, the two switch circuits 3 and 3′ are in synchronization with each other by receiving a common clock signal CK. Prior art liquid crystal display devices (panels) are explained with reference to Figs. 2 and 3. As illustrated in an equivalent circuit in Fig. 2, scan bus lines S i , S i+1 , S i+2 , ..... and data bus lines D j , D j+1 , ...... are perpendicularly formed on one of the two glass substrates (not shown) having filled liquid crystal therebetween, which substrates oppose each other. The scan bus lines S i , S i+1 , S i+2 , ......... are electrically isolated from the data bus lines D j , D j+1 , ......... at their intersections. At one intersection of the scan bus line such as S i and the data bus line such as D j , a thin film transistor TFT ij is connected between the data bus line D j and a display electrode of a liquid crystal cell CL ij , and is controlled by a potential of the scan bus line S i . That is, the thin film transistor TFT ij has a drain D connected to the data bus line D j , a gate G connected to the scan bus line S i , and a source S connected to a display electrode E ij of a liquid crystal cell CL ij whose other electrode is grounded by the common electrode (not shown) on the other glass substrate (not shown). In the above-mentioned active matrix-type liquid crystal display device of Fig. 2, since the scan bus lines S i , S i+1 , S i+2 , ........ and the data bus lines D j , D j+1 , ...... are formed and intersected on the same substrate, insulation defects or short-circuits may occur at the intersections, and also disconnections due to a stepwise configuration at the intersections may occur in the overlaying bus lines. Therefore, there is a limit in thickness of the underlying bus lines and thickness of insulating layers between the overlying and underlying bus lines. As a result, it is not easy to reduce the resistance of the underlying bus lines and increase the thickness of the insulating layers. Thus, it is difficult to completely avoid short-circuits at the intersections. Therefore, as illustrated in Figs. 3 and 4, there has been suggested a counter-matrix active liquid crystal display device in which the scan bus lines S i are formed on one glass substrate SUB₁ and the data bus lines D j are formed on the other glass substrate SUB₂ which opposes the first substrate SUB₁. Note that Fig. 3 is an equivalent circuit diagram of a prior art counter matrix active liquid crystal display device, and Fig. 4 is its exploded, perspective view. That is, liquid crystal is filled between the glass substrates SUB₁ and SUB₂. The striped data bus lines D j , D j+1 , ...... are formed on the glass substrate SUB₂, while the san bus lines S i , S i+1 , ......, the thin film transistors such as TFT ij , display electrodes such as E ij for forming liquid crystal cells such as CL ij , and reference voltage supplying bus lines V r (which are illustrated as the ground in Fig. 3), are formed on the glass substrate SUB₁. Liquid crystal is filled between the data bus lines D j , D j+1 , ....... and the display electrodes E ij , ...... to form the liquid crystal cells CL ij , ....... For example, the liquid crystal cell CL ij is connected between the data bus line D j , and the drain D of the thin film transistor TFT ij whose gate G is connected to the scan bus line S i . Also, the source S of the thin film transistor TFT ij is connected to the reference voltage supply bus line. In the above-mentioned configuration, of Figs. 3 and 4, the data bus lines D j , D j+1 , ........ and the scan bus lines S i , S i+1 , ..... are orthogonal to each other and they sandwich the liquid crystal, so it is unnecessary to form insulating layers for the intersections since the two kinds of bus lines are not formed on the same substrate. This makes the configuration simple. Also, since no short-circuit occurs between the data bus lines D j , D j+1 , ....... and the scan bus lines S i , S i+1 , ....., defects of display are reduced to improve the manufacturing yield. A shift voltage ΔV 1c may be generated at the display electrode E ij in the active matrix-type liquid crystal display devices of Fig. 2 and Figs. 3 and 4. In the active matrix-type liquid crystal device of Fig. 2, if C gp is a parasitic electrostatic capacity between the scan bus line S i to which the gate G of the thin film transistor TFT ij is connected and the display electrode E ij ; C dp is a parasitic electrostatic capacity between the display electrode E ij and the data bus line D j , i.e., a parasitic electrostatic capacity between the sources and drain D of the thin film transistor TFT ij ; C LC is an electrostatic capacity of the liquid crystal cell CL ij , then ΔV 1c = ΔV D C dp /(C gp + C dp + C LC ) where ΔV D is a fluctuation of the potential at the data bus line D j , i.e., an amplitude thereof. Conversely, in the active matrix-type liquid crystal device of Figs. 3 and 4, ΔV 1c = ΔV D ·(C gp + C cp )/(C gp + C dp + C LC ) where V dp is a parasitic electrostatic capacity between the display electrode E ij and the reference voltage supplying bus line (ground). Thus, when the data bus line D i uses a positive voltage and a negative voltage which are changed symmetrically for an odd frame and an even frame, an effective voltage applied to the liquid crystal cell CL ij is not symmetrical with respect to the positive voltage and the negative voltage, thus creating a DC component. In the liquid crystal voltage V 1c . The above-mentioned DC component generates a flicker, i.e., a residual image in a stationary image, thus reducing the quality of display, and also reducing the life time of the active-type liquid crystal display device (panel). To cope with this, a bias voltage is applied to the common electrode (ground) of the liquid crystal cell C ij , for example, to make the effective voltage of the liquid crystal cell C ij symmetric for a positive frame and a negative frame, thus reducing the DC component. In this device, however, since the capacity C 1c of the liquid crystal cell has a voltage dependency due to the anisotropy of dielectric characteristics of the liquid crystal cell C ij , the shift voltage ΔV 1c is fluctuated in accordance with the display state of the liquid crystal cell CL ij , and as a result, there is a limit to remove a DC component by only applying a bias voltage to the common electrode. As another measure, there is suggested an active-type liquid crystal panel where two complementary thin film transistors are used for one pixel electrode, and a scan signal having opposite polarities for every frame is applied to the gate electrodes of the thin film transistors thus making the effective voltage applied to the liquid crystal cell symmetrical (see: JP-A-No. 53-144297 of PAJ, vol. 3, no. [E-090], 14.02.79). Also, in this device, the shift voltage ΔV 1c is entirely canceled by the scan signal having opposite polarities which are changed for each frame, but, in each frame, the shift voltage ΔV 1c is still present. Further, in view of the above-mentioned formulae (1) and (2), the shift voltage ΔV 1c in the counter-matrix-type device of Figs. 3 and 4 is larger than the shift voltage ΔV 1c in the device of Fig. 2, due to the parasitic electrostatic capacity C gp . Thus, the counter-matrix type device has a problem in that crosstalk is large. That is, in the counter matrix-type device, when the thin film transistor TFT ij is turned OFF, the data voltage sequentially applied to the data bus line D j is applied to the liquid crystal cell C ij via the parallel electrostatic capacities C gp and C dp , and therefore, the other data voltage for other liquid crystal cells fluctuates the liquid crystal cell voltage V 1c , thus reducing the quality of display. Also, in the conventional active matrix type liquid crystal display device of Fig. 2, it is possible to lessen the ratio ΔV 1c /ΔV D by adding a storage capacity to the liquid crystal cell. Conversely, in the counter matrix type active liquid crystal display device of Figs. 3 and 4, it is difficult to lessen the ratio ΔV 1c /ΔV D , since it is difficult to add such as storage capacity to the liquid crystal cell. Further, due to the difficulty of addition of such a storage capacity, the level shift of a DC voltage immediately after the selection of the scan bus line S i connected to the gate G of the thin film transistor TFT ij causes a residual image phenomenon. Particularly, for a stationary image, a burning phenomenon occurs to reduce the quality of display. In Fig. 5, which is a first embodiment of the counter-matrix-type display device according to the present invention, a plurality of pairs of scan bus lines SN i , SP i ; SN i+1 , SP i+1 ; .... and a plurality of data bus lines D j , .... are perpendicularly arranged with each other on different glass substrates having liquid crystal filled therebetween. Also, display (pixel) electrodes E ij , E i+1 , ..... are arranged within pixel areas in a matrix partitioned by the scan bus lines SN i , SP i , .... and the data bus lines D j , ....... Further, reference voltage supply lines, which are in this case grounded, GND are arranged in parallel with the scan bus lines SN i , SP i , ...... Liquid crystal cells CL ij , .... are formed by the display electrodes E ij with liquid crystal. In order to control each of the liquid crystal cells CL ij , two kinds of thin film transistors, i.e., an N-channel type thin film transistor TFT N ij and a P-channel type thin film transistor TFTP ij are provided for each liquid crystal cell CL ij . These can be formed by a semiconductor region made of amorphous silicon or polycrystalline silicon, and source/drain electrode portions which are, for example, P-type semiconductors obtained by doping impurities such as boron, or N-type semiconductors obtained by doping impurities such as phosphorus or arsenic. Also, when manufacturing thin film transistors, photo resist material, an oxidation film, and nitride film are used as masks, and boron and arsenic are doped individually by ion plantation or diffusion into the semiconductor regions for the source/drain portions, to form the two kinds of thin film transistors. There are two scan bus lines SN i and SP i for one scan line. The gate G of the N-channel thin film transistor TFTN ij is connected to the scan bus line SN i , and the gate G of the P-channel thin film transistor TFTP ij is connected to the scan bus line SP i . Also, the drains D of the thin film transistors TFTN ij and TFTP ij are connected to the display electrode E ij of the liquid crystal cell CL ij , and the sources S of the thin film transistors TFTN ij and TFTP ij are connected to the reference voltage supply line GND. The signals of the scan bus lines SN i and SP i , and the data bus line D j of Fig. 5 are shown in Figs. 6A, 6B, and 6C. The signals of the scan bus lines SN i and SP i are pulse signals in synchronization having opposite polarities to each other, and their amplitudes are V GN and V GP , respectively. That is, the signal of the scan bus line SN i is a pulse signal having a voltage + V GN , and the signal of the scan bus line SP i is a pulse signal having a voltage-V GP . The signals of the scan bus lines SN i and SP i are delayed by using the shift registers 21 and 21′ of the scan synchronization circuits 2 and 2′ of Fig. 1 for one horizontal scanning time period it, and are sequentially applied to the downstream side scan bus lines SN i+1 , SP i+1 , ......, thus scanning all of the scan bus lines. That is, as shown in Figs. 6A and 6B, the signals applied to the scan bus lines SN i and SP i are generated from time t₀ to time t₁, the signals applied to the scan bus lines SN i+1 and SP i+1 generated from time t₁ to time t₂, and so on. As shown in Fig. 6C, the signal of the data bus line D j having an amplitude V D is generated at the same or approximately same timing as that of signals of the scan bus lines SN i and SP i . However, the polarity of the signal of the data bus line D i is reversed for every frame. Also, the pulse-width of the signal of the data bus line D j is preferably broader than that of the signals of the scan bus lines SN i and SP i , but, the present invention is not limited to this. The thin film transistors TFTN i and TFTP i at each pixel are simultaneously turned ON by the signals of the scan bus lines SN i and SP i , and therefore, the data of the data bus line D j is written into the liquid crystal cell CL ij . At this time, the voltages +V GN and -V GP are determined so as to satisfy the following relationship: (C gPN + C dPN )·V GN = (C gPP + C dPP )·V GP where C gPN is a parasitic electrostatic capacity between the scan bus line SN i and the display electrode E ij ; C dPN is a parasitic electrostatic capacity between the gate-source of the N-channel type transistor TFTN i ; C gPP is a parasitic electrostatic capacity between the scan bus line SP i and the display electrode E ij ; and C dPP is a parasitic electrostatic capacity between the gate-source of the P-channel type transistor TFTP i . Therefore, the level shift voltage ΔV 1CN by the N-channel type thin film transistor TFTN ij is counteracted by the level shift voltage ΔV eCN by the P-channel type thin film transistor TFTP ij in accordance with the above-mentioned formula (2). As a result, the total level shift voltage ΔV 1c becomes zero. Thus, the voltage ±V D written into the liquid crystal cell CL ij is maintained until the next scan signals are applied to the scan bus lines SN i and SP i . Thus, the generation of a DC component in the AC voltage applied to the liquid crystal cell C ij is avoided. The scan signals applied to the scan bus lines SN i and SP i of Figs. 6A and 6B are generated by the synchronization circuits 2 and 2′ and the switch circuit 3 and 3′ of Fig. 1. That is, the switch circuit 3 generates a signal S COUT1 as shown in Fig. 7A, and the switch circuit 3′ generates a signal S COUT2 as shown in Fig. 7E. In this case, the voltages V₁ and V₂ of the switch circuit 3 are +V GN and -V GP , respectively, and the voltages V₁′ and V₂′ of the switch circuit 3′ are also +V GN and -V GP , respectively. Shift data SD₁ as shown in Fig. 7C is supplied to the shift register 22, and shift data SD₂ as shown in Fig. 7G is supplied to the shift register 22′. Such shift data SD₁ and SD₂ are shifted within the shift registers 22 and 22′, respectively, in synchronization with shift clock signals SCK₁ and SCK₂ as shown in Figs. 7B and 7F, respectively. As a result, the signals applied to the scan bus lines SN i and SP i are obtained as shown in Figs. 7D and 7H, respectively. In Fig. 8, which is a second embodiment of the counter-matrix-type display device according to the present invention, only one scan bus line is provided for each line. That is, a scan bus line SP i-1 (SN i-2 ) is connected to the gate of the P-channel thin film transistor TFTP i-1 and to the gate of the N-channel thin film transistor TFTN i-2 . Similarly, a scan bus line SPi (SN i-1 ) is connected to the gas of the P-channel thin film transistor TFTP i and to the gate of the N-channel thin film transistor TFTN i-1 . In other words, the gate of the P-channel thin film transistor TFTP i connected to one display electrode E ij is connected to a scan bus line SP i (SN i-1 ), while the gate of the N-channel thin film transistor TFTN i connected to the same display electrode E ij is connected to a different scan bus line SP i+1 (SN i ). The signals of the scan bus lines SP i-1 (SN i-2 ), SP i (SN i-1 ), and SP i+1 (SN i ) are shown in Figs. 9A, 9B, and 9C, respectively. Each of the signals are pulse signals having opposite polarities to each other, and their amplitudes are V GN and V GP , respectively. Also, each of the signals of the scan bus lines SP i-1 (SN i-2 ), SP i (SN i-1 ), SP i+1 (SN i ), ..... are sequentially delayed by one horizontal scan time period H. A positive signal component of its previous scan bus such as SP i (SN i-1 ) is in synchronization with a positive signal component of its following scan bus line such as SP i+1 (SN i ). Also, a negative signal component of one scan bus line such as SP i (SN i-1 ) is in synchronization with a positive signal component of its following scan bus line such as SP i+1 (SN i ). Therefore, for example, the N-channel thin film transistor TFTN ki-1, j is turned ON from time t D to time t₁, and also, the P-channel thin film transistor TFTP ij is turned ON from time t₀ to time t₁. Thus, both the N-channel and P-channel thin film transistors such as TFTN ij and TFTP ij connected to one display electrode such as E ij , are simultaneously turned ON. Therefore, if the voltages +V GN and -V GP are determined so as to satisfy the above-mentioned formula (3), and the shift voltage ΔV 1c is zero, thereby avoiding the generation of a DC component in the AC voltage applied to the liquid crystal cell CL ij . Note that, for the liquid crystal cell CL ij (the display electrode E ij ), the shift voltage ΔV 1c is not zero at time t₂ when both of the thin film transistors TFTN ij and TFTP ij are tuned OFF, however, this shift voltage ΔV 1c finally becomes zero at time t₃. The signals of the scan bus lines SP i-1 (SN i-2 ) are delayed by using the shift registers 21 and 21′ of the scan synchronization circuits 2 and 2′ of Fig. 1 and are sequentially applied to the downstream side scan bus lines SP i (SN i-1 ) SP i+1 (SN i ), ......, thus scanning all of the scan bus lines. The scan signals applied to the scan bus lines SP i-1 (SN i-2 ) and SP i (SN i-1 ) of Figs. 9A and 9B are generated by the synchronization circuits 2 and 2′ and the switch circuit 3 and 3′. that is, the switch circuit 3 generates a signal S COUT1 as shown in Fig. 10A, and the switch circuit 3′ generates a signal S COUT2 as shown in Fig. 10E. In this case, the voltages V₁ and V₂ of the switch circuit 3 are +V GN and -V GP , respectively, and the voltages V₁′ and V₂′ of the switch circuit 3′ are also +V GN and -V GP , respectively. Shift data SD₁ as shown in Figs. 10C is supplied to the shift register 22, and shift data SD₂ as shown in Fig. 10G is supplied to the shift register 22′. Such shift data SD, and SD₂ are shifted within the shift registers 22 and 22′, respectively, in synchronization with shift clock signals SCK₁ and SCK₂ as shown in Figs. 10B and 10F, respectively. As a result, the signals applied to the scan bus lines SP i-1 (SN i-2 ) and SP i (SN i-1 ) are obtained as shown in Figs. 10D and 10H, respectively. Also, according to the active-type liquid crystal display device of Fig. 8, since the number of scan bus lines is reduced by 1/2, areas occupied by the scan bus lines and the connections therefor are reduced, to simply the configuration of a substrate, a control circuit, and the like. In Fig. 11, which is a third embodiment of the counter-matrix-type display device according to the present invention, the active matrix-type liquid crystal display device of Fig. 5 is modified to reduce the number of scan bus lines. That is, the scan bus lines SP i and SN i are combined with the adjacent scan bus lines SN i-1 and SP i-1 , respectively, the scan bus lines SP i+1 and SN i+1 are combined with the adjacent scan bus lines SN i and SP i , respectively, and so on. Therefore, pairs of scan bus lines such as SP i-1 (SN i ) and SP i (SN i-1 ) are arranged for every two rows of the liquid crystal cells. The pair of the signals of the scan bus lines SP i-1 (SN i ) and SP i (SN i-1 ) are in synchronization with each other as shown in Figs. 12A and 12B, but their polarities are opposite. Also, the pair of the signals of the scan bus lines SP i+1 (SN i+2 ) and SP i+2 (SN i+1 ) are in synchronization with each other as shown in Figs. 12C and 12D, but their polarities are opposite. For example, from time t₋₁ to time t₀, a negative portion of the signal of the scan bus line SP i-1 (SN i ) corresponds to a positive portion of the signal of the scan bus line SP i (SN i-1 ), while from time t₀ to time t₁, a positive portion of the signal of the scan bus line SP i-1 (SN i ) corresponds to a negative portion of the signal of the scan bus line SP i (SN i-1 ). As a result, from time t₋₁ to time t₀, the P-channel thin film transistor TFTP i-1, j and the N-channel thin film transistor TFTN i-1, j are simultaneously turned ON, and from time t₀ to time t₁, the N-channel thin film transistor TFTN ij and the P-channel thin film transistor TFTP ij are simultaneously turned ON. Similarly, from time t₁ to time t₂, a negative portion of the signal of the scan bus line SP i+1 (SN t+2 ) corresponds to a positive portion of the signal of the scan bus line SP i+2 (SN i+1 ), while from time t₂ to time t₃, a positive portion of the signal of the scan bus line SP i+1 (SN i+2 ) corresponds to a negative portion of the signal of the scan bus line SP i+1 (SN i+1 ). As a result, from time t₁ to time t₂, the P-channel thin film transistor TFTP i+1, j and the N-channel thin film transistor TFTN i+1, j are simultaneously turned ON, and from time t₂ to time t₃, the N-channel thin film transistor TFTN i+2, j and the P-channel thin film transistor TFTP i+2, j are simultaneously turned ON. The pair of the s ignals of the scan bus lines SP i-1 (SN i ) and SP i (SN i-1 ) are delayed for two horizontal scanning time periods 2H to obtain the signals of the pair of the scan bus lines SP i+1 (SN i+2 ) and SP i+2 (SN i+1) . The scan signals applied to the scan bus lines SP i-1 (SN i ) and SP i (SN i-1 ) of Figs. 12A and 12B are generated by the synchronization circuits 2 and 2′ and the switch circuit 3 and 3′. That is, the switch circuit 3 generates a signal S COUT1 as shown in Fig. 13A, and the switch circuit 3′ generates a signal S COUT2 as shown in Fig. 13E. In this case, the voltages V i and V₂ of the switch circuit 3 are +V GN and -V GP , respectively, and the voltages V₁′ and V₂′ of the switch circuit 3′ are also +V GN and -V GP , respectively. Shift data SD₁ as shown in Fig. 13 is supplied to the shift register 22, and shift data SD₂ as shown in Fig. 13G is supplied to the shift register 22′. Such shift data SD₁ and SD₂ are shifted within the shift registers 22 and 22′, respectively, in synchronization with shift clock signals SCK₁ and SCK₂ as shown in Figs. 13B and 13F, respectively. As a result, the signals applied to the scan bus lines SP i-1 (SN i ) and SP i (SN i-1 ) are obtained as shown in Figs. 13D and 13H, respectively. Also, according to the active-type liquid crystal display device of Fig. 11 since the number of scan bus lines is reduced by 1/2, areas occupied by the scan bus lines and the connections therefor are reduced, to simplify the configuration of a substrate, a control circuit, and the like. In Fig. 14, which is a fourth embodiment of the counter-matrix-type display device according to the present invention, only one scan line is provided for each row of the liquid crystal cells (i.e., the display electrodes). That is, the gates of the N-channel thin film transistors and the P-channel thin film transistors of the display electrodes belonging to one row are connected to one scan bus line such as S i . Also, there are two kinds of voltage supply lines +V R and -V R , which are arranged alternately for every row of the display electrodes such as E ij . The sources of the N-channel thin film transistors such as TFTN ij are connected to the positive voltage supply line +V R , while the sources of the P-channel thin film transistors TFTP ij are connected to the negative voltage supply line -V R . The operation of the active matrix-type liquid crystal device of Fig. 14 is explained with reference to Figs. 15A through 15G. As shown in Figs. 15A, 15B, and 15C, the signal of the scan bus line S i+1 is obtained by delaying the signal of the scan bus line S i for one horizontal scanning time period H, and the signal of the scan bus line S i+2 is obtained by delaying the signal of the scan bus line S i+1 for one horizontal scanning time period H. Also, the polarity of the signal of the scan bus line S i is opposite to that of the signal of the scan bus line S i+1 , and the polarity of the signal of the scan bus line S i+1 is opposite to that of the signal of the scan bus line S i+2 . Further, each of the signals of the scan bus lines S i , S i+1 , S i+2 , ... are reversed for every frame. That is, in an odd frame, the signal of the scan bus line S i is pulse signal of a voltage +V GN from time to to time t₁, and the signal of the scan bus line S i+1 is a pulse signal of a voltage -V GP from time t₁ to time t₂. Also, in an even frame, the signal of the scan bus line S i is a pulse signal of a voltage -V GP from time to to time t₁, and the signal of the scan bus line S i+1 is a pulse signal of a voltage +V GN from time t₁ to time t₂. As shown in Fig. 15D, the signal of the data line such as D j has an amplitude of V D , and the polarity thereof is reversed for each frame. As shown in Fig. 15E, the reference voltage supply lines +V R and -V R are always at a definite positive value and a definite negative value, respectively. First, in an odd frame, when the voltage of the scan bus line S i is +V GN , the N-channel thin film transistors such as TFTN ij connected to the scan bus line S i are turned ON. As a result, -V R , which also defines the voltage of the negative reference voltage supply line -V R , is applied as an electrode voltage V P as shown in Fig. 15F via the turned ON N-channel thin film transistor such as TFTN ij to the display electrode such as E ij . Therefore, a voltage V D + V R , which is a difference in potential between the display electrode E ij and the data bus signal D j , is applied as a write voltage (liquid crystal cell voltage V 1c ) to the liquid crystal cell CL ij . Next, when the voltage of the scan bus line S i+1 is -V GP the P-channel thin film transistors such as TFTP i+1,j connected to the scan bus line S i+1 are turned ON. As a result, +V R , which also defines the voltage of the positive reference voltage supply line +V R , is applied as an electrode voltage V p via the turned ON P-channel thin film transistor such as TFTP i+1,j to the display electrode such as E i+1,j . Therefore, a voltage -(V P + V R ), which is a difference in potential between the display electrode E i+1,j and the data bus signal D j , is applied as a write voltage (liquid crystal cell voltage V 1c ) to the liquid crystal cell CL i+1,j . Conversely, in an even frame, when the voltage of the scan bus line S i is -V GP , the P-channel thin film transistors such as TFTP ij connected to the scan bus line S i are turned ON. As a result, +V R is applied as the electrode voltage V P as shown in Fig. 15F via the turned ON P-channel thin film transistor such as TFTP ij to the display electrode such as E ij . Therefore, a voltage -(V D + V R ), which a difference in potential between the display electrode E ij and the data bus signal D j , is applied as the write voltage (liquid crystal cell voltage V 1c ) to the liquid crystal cell CL ij . Next, when the voltage of the scan bus line S i+1 is +V GN , the N-channel thin film transistors such as TFTN i+1,j connected to the scan bus line S i+1 are turned ON. As a result, -V R is applied as an electrode voltage V p via the turned ON N-channel thin film transistor such as TFTN i+1,j to the display electrode such as E i+1,j . Therefore, a voltage V D + V R , which is a difference in potential between the display electrode E i+1,j and the data bus signal D j , is applied as a write voltage (liquid crystal cell voltage V 1c ) to the liquid crystal cell CL i+1,j . That is, the signal of the data bus line such as D j is reversed for every frame, is applied to each of the liquid crystal cells, and in addition, the P-channel thin film transistors and the N-channel thin film transistors are alternately turned ON for every frame. As a result, the reference voltage -V R or +V R is applied as the electrode voltage V P via the turned-ON thin film transistors, and therefore, these differences (V D + V R ) and -(V D + V R ) are written into the liquid crystal cells such as CL ij , to obtain the liquid crystal voltage V 1c . Thus, the reference voltage V R is the same as the write voltage applied to the liquid crystal cell CL ij , i.e., a bias corresponding to the reference voltage V R is given, and therefore, it is possible to reduce the voltage ±V D of the data bus lines such as D j required to obtain a minimum liquid crystal cell voltage V 1c . In other words, the amplitude of the signal of the data bus lines is reduced. That is, if a threshold voltage of a liquid crystal cell is V th and a saturation voltage of the liquid crystal cell is V sat , the voltage V D of the data bus lines such as D j and the reference voltage V R can be V D = (V sat - V th ) /2 V R = (V sat + V th ) /2 Thus, the voltage V D can be reduced by 1/4 as compared with the devices of Figs. 5, 8, and 11 where V D ≒ V sat . Note that V th is usually half of V sat . The scan signals applied to the scan bus lines S i and S i+1 of Figs. 15A and 15B are generated by the synchronization circuits 2 and 2′ and the switch circuit 3 and 3′ of Fig. 1. That is, the switch circuit 3 generates a signal S COUT1 as shown in Fig. 16A, and the switch circuit 3′ generates a signal S COUT2 as shown in Fig. 16E. In this case, the voltages V₁ and V₂ of the switch circuit 3 are +V GN and -V GP , respectively, and the voltages V₁′ and V₂′ of the switch circuit 3′ are also +V GN and -V GP , respectively. Shift data SD₁ as shown in Fig. 16C is supplied to the shift register 22, and shift data SD₂ as shown in Fig. 16G is supplied to the shift register 22′. Such shift data SD₁ and SD₂ are shifted within the shift registers 22 and 22′, respectively, in synchronization with shift clock signals SCK₁ and SCK₂ as shown in Figs. 16B and 16F, respectively. As a result, the signals applied to the scan bus lines S i and S i+1 are obtained as shown in Figs. 16D and 16H, respectively. The above-mentioned waveforms as shown in Figs. 16A through 16H are generated in an odd frame, but in an even frame, the switch circuits 3 and 3′ generate the waveforms as shown in Figs. 16E and 16A, respectively. According to the active matrix-type liquid crystal display device of Fig. 14, since the polarity of the signals of the scan bus lines S i , S i+1 ,... is reversed for every frame, the polarity of the shift voltage ΔV 1c due to the parasitic electrostatic capacity is reversed for every frame. Therefore, the shift voltage ΔV 1c generated during an odd frame is counteracted with the shift voltage ΔV 1c generated during an every frame, so that the total shift voltage becomes zero. Thus, the generation of a DC component in the AC voltage applied to the liquid crystal cells is avoided. Also, the crosstalk due to the amplitude of the data bus lines is reduced to improve the display quality. In Fig. 17, which is a fifth embodiment of the counter-matrix-type display device according to the present invention, the device of Fig. 14 is modified to further avoid flickering. That is, the polarities of the reference voltage bus line connected to each of the N-channel thin film transistors and the P-channel transistors are reversed for very column of the liquid crystal cells, i.e., the display electrodes such as E ij . The signals of the device of Fig. 17 are the same as those of the device of Fig. 14, except that, as shown in Figs. 18D and 18E, the polarity of a signal of one data bus line such as D j is opposite to the polarity of a signal of another adjacent data bus such as D j+1 , since the electrode voltage V P of the display electrode such as E ij depends on whether or not the N-channel transistor is turned ON. As a result, voltages (V D + V R ) and -(V D + V R ) are alternately written into the liquid crystal cell for every column. According to the active matrix-type liquid crystal display device of Fig. 17, the flickering can be avoided due to the reversion of the polarity of the data bus lines for every column, in addition to the effect of the device of Fig. 14. In Fig. 19, which is a sixth embodiment of the counter-matrix-type display device according to the present invention, the device of Fig. 14 is modified. That is, each of the scan bus lines S i , S i+1 , .. of Fig. 14 is split into two pieces S i (U), S i (L); S i+1 (U), S i+1 (L); ... on both sides of each row of the display electrodes. In this case, the gates of the N-channel thin film transistors such as TFTN ij are connected to the upper side scan bus line such as S i (U), while the gates of the P-channel thin film transistors such as TFTP ij are connected to the lower side scan bus line such as S i (L). The operation of the device of Fig. 19 is the same as that of the device of Fig. 14. According to the device of Fig. 19, the length of the connections between the drains of the thin film transistors and their corresponding reference voltage supply lines +V R and -V R can be shortened, to reduce the parasitic capacity between the drains of the thin film transistor and the corresponding display electrode, thus reducing the crosstalk and increasing the ratio of openings, in addition to the effect of the device of Fig. 14. In Fig. 20, which is a seventh embodiment of the counter-matrix-type display device according to the present invention, the device of Fig. 17 is modified. That is, the modification of the device of Fig. 17 to the device of Fig. 20 is the same as that of the device of Fig. 14 to the device of Fig. 19. That is, each of the scan bus lines S i , S i+1 ,... of Fig. 17 is split into two pieces S i (U), S i (L); S i+1 (U), S i+1 (L); ... on both sides of each row of the display electrodes. In this case, the gates of the N-channel thin film transistors such as TFTN ij are connected to the upper side scan bus line such as S i (U), while the gates of the P-channel thin film transistors such as TFTP ij are connected to the lower side scan bus line such as S i (L). The operation of the device of Fig. 20 is explained with reference to Figs. 21A through 21H. As shown in Figs. 21A, 21B, and 21C, the signals of the scan bus lines S i , S i+1 , and S i+2 have the same polarity in the same frame, and this polarity is reversed for every frame. Therefore, as shown in Figs. 21D and 21E, the signals of the data bus lines D j , D j+1 have different polarities in the same frame, and these polarities are reversed for every frame. The scan signals applied to the scan bus lines S i and S i+1 of Figs. 21A and 21B are generated by the synchronization circuits 2 and 2′ and the switch circuits 3 and 3′ of Fig. 1. That is, the switch circuit 3 generates a signal S COUT1 as shown in Fig. 22A, and the switch circuit 3′ generates a signal S COUT2 as shown in Fig. 22E. In this case, the voltages V₁ and V₂ of the switch circuit 3 are +V GN and -V GP , respectively, and the voltages V₁′ and V₂′ of the switch circuit 3′ are also +V GN and -V GP , respectively. Shift data SD₁ as shown in Fig. 22C is supplied to the shift register 22, and shift data SD₂ as shown in Fig. 22G is supplied to the shift register 22′. Such shift data SD₁ and SD₂ are shifted within the shift registers 22 and 22′, respectively, in synchronization with shift clock signals SCK₁ and SCK₂ as shown in Figs. 22B and 22F, respectively. As a result, the signals applied to the scan bus lines S i and S i+1 are obtained as shown in Figs. 22D and 22H, respectively. The above-mentioned waveforms as shown in Figs. 22A through 22H are generated in an odd frame, but in an even frame, the switch circuits 3 and 3′ generate the waveforms as shown in Figs. 22E and 22A, respectively. According to the active matrix-type liquid crystal device of Fig. 20, all the effects of the devices of Figs. 14, 17, and 19 are obtained. That is, the shift voltage ΔV 1c can be compensated for, and the flickering can be avoided. Also, the connections between the sources of the thin film transistors and their corresponding display electrodes are shortened, to reduce the parasitic electrostatic capacity between the of the thin film transistors and the corresponding display electrodes. In Fig. 23, which is an eighth embodiment of the counter-matrix-type display device according to the present invention, and in Fig. 24, which is a layout diagram of the device of Fig. 23, all of the thin film transistors TFTN ij , TFTN ij ′ are of a N-channel type. Also, only one reference voltage supply line V R is provided in common to the entire device, and is switched from a first level to a second level for every horizontal scanning time period H. Also, two scan bus lines such as S i-1 ′ and S i are arranged on both sides of the reference voltage supply line V R , and the two scan bus lines such as S i-1 ′ and S i are connected at a terminal such as T i , to surrounded the reference voltage supply line V R . The gates of the N-channel thin film transistors such as TFTN ij ′ are connected to the downstream side scan bus lines such as S i , and the gates of the N-channel thin film transistors such as TFTN ij ′ are connected to the upstream side scan bus lines such as S i ′. The sources of the thin film transistors are connected to the reference voltage supply line V R and the drains of the thin film transistors are connected to the corresponding display electrodes such as E ij . The operation of the device of Figs. 23 and 24 particularly, the operation for the display electrode E ij (liquid crystal cell (L ij )) is explained with reference to Figs. 25A through 25F. When a scan voltage (+V g ) as shown in Fig. 25B is applied to the scan bus line S i+1 (S i ′), the N-channel thin film transistor such as TFTN ij ′ is turned ON, so that the display electrode E ij is electrically connected to the reference voltage supply line V R . Thus, the difference in potential between the reference voltage supply line V R as shown in Fig. 25D and the data bus line D j as shown in Fig. 25E, becomes the liquid crystal voltage V 1c as shown in Fig. 25F. On the other hand, simultaneously with the application of the san voltage (V g ) to the scan bus line S i+1 (S i ′), even when a scan voltage (-V cg ) as shown in Fig. 25A applied to the scan bus line S i (S i-1 ′), the N-channel thin film transistor TFTN ij is turned OFF. This compensates for the shift voltage ΔV ec appeared in the display electrode E ij . That is, the shift voltage ΔV ec ′ due to the change of the scan voltage applied to the scan bus line S i+1 (S i ′) from +V g to OV is compensated for by the shift voltage ΔV ec ″ due to the change of the scan voltage applied to the scan bus line S i (S i-1 ′) from -V cg to OV. Also, before the application of the scan voltage (-V cg ) to the scan bus line S i (S i-1 ′), a scan voltage (+V g ) is applied to the scan bus line S i (S i-1 ′) as shown in Fig. 25A, to turn ON the N-channel thin film transistor TFTN ij , thereby writing date into the liquid crystal cell CL ij (E ij ). Usually, this written data is immediately canceled by the application of the scan voltage V g to the scan bus line S i+1 (S i ′). However, if the N-channel thin film transistor TFTN ij is broken for some reason, a write operation is performed upon the display electrode E ij (liquid crystal cell CL ij ) via the N-channel thin film transistor TFTN ij by the scan voltage applied to the scan bus line S i (S i-1 ′). Thus, such a redundancy configuration can remedy a defective liquid crystal display device where some thin film transistors are defective. The scan voltages as shown in Figs. 25A, 25B, and 25C are sequentially generated in the same way as in the device of Fig. 8. As a result, as shown in Fig. 25F, the liquid crystal voltage V 1c between the display electrode E ij and the data bus line D j is maintained until the next scan voltages are applied to the scan bus lines S i (S i-1 ′) and S i+1 (S i ′). According to the device of Figs. 23 and 24, a parasitic electrostatic capacity between the reference voltage supply line V R and the display electrodes such as E ij can be reduced, i.e., the parasitic electrostatic capacity C dp in the formula (2) can be reduced, to lessen the shift voltage ΔV 1c thereby reducing the crosstalk. In Fig. 26, which is a cross-sectional view taken along the line A-A′ of Fig. 24, a metal layer M₁ (i.e., the display electrode E ij ) and a metal layer M₂ are formed on the glass substrate SUB₁. Reference S and D are contact layers which serve as a source electrode and a drain electrode. The contact layers S and D are formed by N⁺-type amorphous silicon, for example. Reference I designates an intrinsic semiconductor layer formed by amorphous silicon. Also, SP i and V R are metal layers formed by polycrystalline silicon, aluminium, tungsten, molybdenum, chromium, or the like. In Fig. 27, which shows an example of the transmissibility characteristic of a liquid crystal cell, if the absolute value of the liquid crystal voltage V 1c is smaller than a threshold voltage V th , the liquid crystal cell is dark, while if the absolute value of the liquid crystal voltage V 1c is larger than a saturation voltage V sat , then the liquid crystal cell is bright. Assume that V th = 2.5V and V sat = 5V. Then, the difference between the high level and low level of the reference voltage supply line V R is 12 - 4.5 = 7.5V as shown in Fig. 24D, which corresponds to a value of V th + V sat (= 7.5V). Also, when the reference voltage V R is 4.5V and the voltage of the data bus line D j is 9.5V, as shown in Figs. 25D and 25E, the liquid crystal voltage V 1c is -5V which means "bright". Conversely, when the reference voltage V R is 4.5V and the voltage of the data bus line D j is 7V, as indicated by arrows X in Figs. 25D and 25E, the liquid crystal voltage V 1c is -2.5V which means "dark". The shift voltage ΔV 1c of the liquid crystal voltage V 1c can be represented by ΔV LC = [ΔV D × (C gp + C dp ) ÷ (C gp + C dp + C LC )] + ΔV R × C dp /(C gp + C dp + C LC ) = (ΔV D + ΔV R ) × C dp /(C gp + C dp + C LC ) + ΔV D × C gp /(C gp + C dp + C LC ) where ΔV D is a fluctuation of the voltage of the data bus line such as D j , and ΔV R is a fluctuation of the reference voltage V R . Note that, the shift voltage ΔV 1c ′ in the prior art can be represented by ΔV LC = [ΔV D × (C gp + C dp ) ÷ (C gp + C dp + C LC )] = (ΔV D × C dp /(C gp + C dp + C LC ) + ΔV D × C gp /(C gp + C dp + C LC ) In the device of Figs. 23 and 24, the reference voltage V R is alternately switched from 12V to 4.5V or vice versa, so that the amplitude of the signals of the data bus lines can be reduced. For example, the liquid crystal voltage V 1c is ±5V, but the amplitude of the signal of the data bus line D j is 2.5V (=9.5-7). Further, since the reference voltage supply line V R is surrounded by the scan bus lines, the parasitic electrostatic capacity C dp between the source-drain of the thin film transistors is reduced to lessen the shift voltage ΔV 1c of the liquid crystal voltage V 1c . When the operation of the thin film transistors TFTN ij ′ and TFTN i+1,j is carried out by the scan bus lines S i ′ and S i+1 , the shift voltage ΔV 1c generated at the liquid crystal cell is represented by ΔV 1c = V g × C₂ / (C₁+C₂+C dp +C LC ) where C₁ is a parasitic electrostatic capacity between the display electrode E ij and the scan bus line S i+1 , and C₂ is a parasitic electrostatic capacity between the display electrode E ij and the scan bus line S i ′. Therefore, this shift voltage ΔV 1c can be on the whole compensated for by applying -V gp via the scan bus line SP i to the gate of the thin film transistor TFTP ij . In this case, -V cg = -V g × C₂ / C₁ Note that V g = V cg in Figs. 25A, 25B, and 25C, if C₁ = C₂. In Figs. 28A, 28B, and 28C, which are modifications of Figs. 25A, 25B, and 25C, respectively, when a scan voltage (+V g ) is applied to the scan bus line S i+1 (S i ′), a scan voltage (-V cg ) is applied to the upstream-side scan bus line S i (S i-1 ′) as indicated by X and a scan voltage (-V cg ) is applied to the downstream side scan bus line S i+2 (S i+1 ′) as indicated Y. As a result,even when the display electrode E i+1, j is operated by only the N-channel thin film transistor TFTN i+1, j ′, the shift voltage ΔVec appeared in the display electrode E i+1, j can be compensated for. The scan signals applied to the scan bus lines S i (S i-1 ′) and S i+1 (S i ′) of Figs. 28A and 28B are generated by the synchronization circuits 2 and 2′ and the switch circuit 3 and 3′ of Fig. 1. That is, the switch circuit 3 generates a signal S COUT1 as shown in Fig. 29A, and the switch circuit 3′ generates a signal S COUT2 as shown in Fig. 29E. In this case, the voltages V₁ and V₂ of the switch circuit 3 are +V g and -V cg , respectively, and the voltages V₁′ and V₂′ of the switch circuit 3′ are also +V g and -V cg , respectively. Shift data SD₁ as shown in Fig. 29C is supplied to the shift register 22, and shift data SD₂ as shown in Fig. 29G is supplied to the shift register 22′. Such shift data SD₁ and SD₂ are shifted within the shift registers 22 and 22′, respectively, in synchronization with shift clock signals SCK₁ and SCK₂, as shown in Figs. 29B and 29F, respectively. As a result, the signals applied to the scan bus lines SN i and SP i are obtained as shown in Figs. 29D and 29H, respectively. In Fig. 30, which is a ninth embodiment of the counter-matrix-type display device according to the present invention, protrusions or extensions ES are added on the downstream side scan bus lines S i , S i+1 , ..., of Fig. 24. The extensions ES are formed between the display electrodes such as E ij , E i,j+1 , .... As a result, the parasitic electrostatic capacity C₁ between the display electrode E ij and the scan bus line S i is made larger than the parasitic electrostatic capacity C₂ between the display electrode E ij and the scan bus line S i (C₁ > C₂), thus reducing the compensating voltage-V cg in the formula (7). In Fig. 31, which is a tenth embodiment of the counter-matrix-type display device according to the present invention, the device of Fig. 24 is modified. That is, the distance between the display electrode E ij and the upstream side scan bus line S i thereof is smaller than a distance between the display electrode E ij and the downstream side scan bus line S i ′ thereof. As a result, the parasitic electrostatic capacity C₁ between the display electrode E ij and the scan bus line S i is made larger than the parasitic electrostatic capacity C₂ between the display electrode E ij and the scan bus line S i (C₁ > C₂), thus reducing the compensating voltage-V cg in the formula (7). In Figs. 32A through 32E, which are modifications of Figs. 25A, and 25B, and 25C, an interlaced scanning is carried out. In an odd field, when +V g is applied to the scan bus line S i+1 (S i ′) as shown in Fig. 32C, -V cg is applied to its adjacent two scan bus lines S i (S i-1 ′) and S i+2 (S i+1 ′) as shown in Figs. 32B and 32D, and the thin film transistors TFTN ij ′ and TFTN i+1,j connected to the scan bus line S i+1 (S i ′) are turned ON, so that the data voltage of the data bus line D j is applied to two liquid crystal cells. Then, in the next scanning time period, +V g is applied to the scan bus line S i+3 (S i+2 ′) and -V cg is applied to its adjacent two scan bus lines, and the data voltage of the data bus line D j is applied to two liquid crystal cells adjacent to the scan bus lines S i+3 (S i+2 ′). In an even field, when +V g is applied to the scan bus line S i (S i-1 ′) as shown in Fig. 32B, -V cg is applied to its adjacent two scan bus lines S i-1 (S i-2 ′) (not shown) and S i+1 (S i ′) as shown in Fig. 32B, and the thin film transistors TFTN i-1,j ′ and TFTN ij connected to the scan bus line S i (S i-1 ′) are turned ON, so that the data voltage of the data bus line D j is applied to two liquid crystal cells. Then, in the next scanning time period, +V g is applied to the scan bus line S i+2 (S i+1 ′) and -V cg is applied to its adjacent two scan bus lines, and the data voltage of the data bus line D j is applied to two liquid crystal cells adjacent to the scan bus lines S i+2 (S i+1 ′). Thus, in each of the odd field and the even field, data is written into every two rows of liquid crystal cells, and in addition, the shift voltage in each of the written liquid crystal cells is compensated for by the scan voltages applied to the two adjacent scan bus lines. Also, only one row to be written is advanced at each switching from an old frame to an even frame or vice versa, thereby carrying out an interlaced scanning. Also, in this case, the voltage -V cg is selected so as to reduce the shift voltage. The scan signals applied to the scan bus lines S i-1 (S i-2 ′) and S i (S i-1 ′) of Figs. 32A and 33B are generated by the synchronization circuits 2 and 2′ and the switch circuit 3 and 3′ of Fig. 1. That is, the switch circuit 3 generates a signal S COUT1 as shown in Fig. 33 A, and the switch circuit 3′ generates a signal S COUT2 as shown in Fig. 33E. In this case, the voltages V₁ and V₂ of the switch circuit 3 are +V g and -V cg , respectively, and the voltages V₁′ and V₂′ of the switch circuit 3′ are also +V g and -V cg , respectively. Shift data SD₁ as shown in Fig. 33C is supplied to the shift register 22, and shift data SD₂ as shown in Fig. 33G is supplied to the shift register 22′. Such shift data SD₁ and SD₂ are shifted within the shift registers 22 and 22′, respectively, in synchronization with shift clock signals SCK₁ and SCK₂ as shown in Figs. 33B and 33F, respectively. As a result, the signals applied to the scan bus lines SN i and SP i are obtained as shown in Figs. 33D and 33H, respectively. In Fig. 34, which is a ninth embodiment of the counter-matrix-type display device according to the present invention, the device of Fig. 23 is modified. That is, the thin film transistors such as TFTP ig connected to the scan bus lines S i , S i+1 , S i+2 , ... are of a P-channel type, and the thin film transistors such as TFTN ij connected to the scan bus lines S i-1 ′ S i ′, S i+1 ′,... are of an N-channel type. The operation of the device of Fig. 34 is explained with reference to Figs. 35A through 35F. The reference voltage V R is changed as shown in Fig. 35D. When +V g is applied to the scan bus line S i+1 (S i ′) as shown in Fig. 35B, and -V cg is applied to the scan bus line S i (S i-1 ′) as shown in Fig. 35A, the P-channel thin film transistor TFTP ij connected to the scan bus line S i is turned ON and the N-channel thin film transistor TFTN ij connected to the scan bus line S i ′ is turned ON. As a result, the display electrode E ij is electrically connected to the reference voltage supply line V R by both of the thin film transistors TFTP ij and TFTN ij . Therefore, the liquid crystal voltage V 1c is a difference between the reference voltage V R and the data voltage of the data bus line D j as shown in Figs. 35D, 35E, and 35F. In the above-mentioned state, the N-channel thin film transistor TFTN i-1, j connected to the adjacent display electrode E i-1, j and the P-channel thin film transistor TFTP i+1,j connected to the adjacent display electrode E i+1,j are turned OFF, and accordingly, the data voltage is not applied to the display electrodes E i-1, j and E i+1,j . In the next horizontal scanning time period, when +V g is applied to the scan bus line S i+2 (S i+1 ) as shown in Fig. 35C, and -V cg is applied to the scan bus line S i+1 (S i ′) as shown in Fig. 35B, the P-channelt thin film transistor TFTP i+1, j connected to the scan bus line S i+1 is turned ON and the N-channel thin film transistor TFTN i+1, j connected to the scan bus line S i+1, ′ is turned ON. As a result, the display electrode E i+1, j is electrically connected to the reference voltage supply line V R by both of the thin film transistors TFTP i+1, j and TFTN i+1, j . Therefore, the liquid crystal voltage V 1c is a difference between the reference voltage V R and the data voltage of the data bus line D j as shown in Figs. 35D, 35E, and 35F. In the above-mentioned state, the N-channel thin film transistor TFTN i, j connected to the adjacent display electrode E i, j and the P-channel thin film transistor TFTP i+2,j connected to the adjacent display electrode E i+2,j are turned OFF, and accordingly, the data voltage is not applied to the display electrodes E ij and E i+2, j . Note that the scan signals of the scan bus lines S i (S i-1 ′), S i+1 (S i ′), ... can be generated in the same way as in Figs. 10A through 10H. Also, in Fig. 34, the P-channel thin film transistors and the N-channel thin film transistors can be exchanged with each other. In Fig. 36, which is a twelfth embodiment of the counter-matrix-type display device according to the present invention, the device of Fig. 23 is modified. In general, in Fig. 23, the gates of thin film transistors serve as one part of the scan bus lines, and they are of a multi-layer configuration. In addition, the portions of the gates of the thin film transistors are easily disconnected. Therefore, if the gates of the thin film transistors are disconnected, the scan bus lines are disconnected. Particularly, in the device of Fig. 23, the two thin film transistors such as TFTN i-1,j ′ and TFTN ij are very close to each other, so that disconnections are easily caused in the scan bus lines. Conversely, in Fig. 36, the two thin film transistors TFTN i-1,j and TFTN ij each connected to a pair of the scan bus lines such as S i and S i-1 ′, are distant from each other, thus avoiding the possible disconnection of the scan bus lines. Also, the scan signals are supplied to the pairs of the scan bus lines S i-1 ′ and S i , S i ′ and S i+1 , S i+1 ′ and S i+2 , ... from both sides thereof. As a result, unless two or more continuous disconnections occur in the scan bus lines, all of the thin film transistors can be driven by scan signals, so that no defective display is generated. The manufacturing steps for the active liquid crystal device of Fig. 36 are explained with reference to Figs. 37A through 40A and Figs. 37B through 40B, which are cross-sectional views taken along the line B-B of Figs. 37A through 40A, respectively. As shown in Figs. 37A and 37B, an ITO having a thickness of about 50 nm is deposited on the glass substrate (not shown) by a sputtering method, to obtain a transparent conductive layer (M₁, M₂), and n⁺-amorphorous silicon having a thickness of about 30 nm is deposited thereon by a plasma chemical vapor deposition (CVD) method, to obtain an ohmic contact layer (n+A) on the transparent conductive layer. Thereafter, a pattering operation using a conventional photolithography method is carried out. In Fig. 37B, the transparent conductive layer M₁ is a part of the display electrode E i,j+1 , and the transparent conductive layer M₂ is used for connecting a reference voltage supply line V R . Also, O₁ designates an opening for a thin film transistor. Next, as shown in Figs. 38A and 38B, amorphorous silicon, which is intrinsic semiconductor, is deposited, to obtain an intrinsic layer I, and a silicon nitride (S i3 N₄) layer IN is deposited thereon by using the plasma CVD method. Note that the amorphorous silicon layer I and the S i3 N₄ layer IN are about 30 nm and 50 nm in thickness, respectively. Then, a patterning operation is carried out to obtain a configuration as shown in Fig. 38B. Next, as shown in Figs. 39A and 39B, another silicon nitride (S i3 N₄) layer IN′ having a thickness of about 250 nm is deposited, and then, a patterning operation is carried out to form an opening O₂ as shown in Fig. 39B. Finally, as shown in Figs. 40A and 40B, an aluminum (Al) layer is deposited by the sputtering, and then a patterning operation is carried out to obtain the scan bus line S i and the reference voltage supply line V R . In Fig. 41, which is a thirteenth embodiment of the counter-matrix-type display device according to the present invention, the device of Fig. 23 is also modified. That is, connections N i , N i+1 , N i+2 , ... are provided for the pairs of the scan bus lines S i-1 ′ and S i , S i ′ and S i+1 , S i+1 ′ and S i+2 , .... As a result, unless two or more continuous disconnections occur in the scan bus lines, all of the thin film transistors can be driven by scan signals, so that no defective display is generated. Particularly, in the case of the thin film transistors having a top gate staggered configuration, when a conductive layer between the pair of the scan bus lines such as S i and S i-1 ′ is the same as a conductor layer of the sources and drains of the thin film transistors, the presence of the above-mentioned connections N i , N i+1 , ... hardly affects the reference voltage supply line V R at their intersections with the connection electrodes such as N i , N i+1 ,... (see Fig. 45C). That is, these intersections have a cross-sectional configuration similar to thin film transistors (see: Figs. 45B and 45C), to minimize the areas occupied by the connections between the pairs of the scan bus lines. For example, for a 480 × 640 dot color panel, an occupied area of the thin film transistors per one scan line is 5×20×640×3=192000 µm², if an occupied area of one thin film transistor is 5 × 20 µm² (see: S₁ of Fig. 43A). Contrary to this, if there are provided ten connections per one pair scan bus lines, an occupied area of the connections per one scan line (see: S₂ of Fig. 43A) is 10×10×10=1000 µm². Thus, the increased occupied area by the connections is less than 1%. The manufacturing steps for the active liquid crystal device of Fig. 41 are explained with reference to Figs. 42A through 45A, Figs. 42B through 45B, which are cross-sectional views taken along the line B-B of Figs. 42A through 45A, respectively, and Figs. 42C through 45C, which are cross-sectional views taken along the line C-C of Figs. 42A through 45A, respectively. As shown in Figs. 42A, 42B, and 40C, an ITO having a thickness of about 50 nm is deposited on the glass substrate (not shown) by a sputtering method, to obtain a transparent conductive layer (M₁, M₂, M₃), and N⁺-amorphorous silicon having a thickness of about 30 nm is deposited thereon by a plasma chemical vapor deposition (CVD) method, to obtain an ohmic contact layer (n+A) to the transparent conductive layer. Thereafter, a pattering operation using a conventional photolithography method is carried out. In Fig. 42B, the transparent conducive layer M₁ is a part of the display electrode E i,j+2 , and the transparent conductive layer M₂ is used for connecting a reference voltage supply line V R . Also, O₁ designates an opening for a thin film transistor. Further, in Fig. 42C, the transparent conductive layer M₃ serves as the connection N i . Next, as shown in Figs. 43A, 43B, and 43C, amorphorous silicon, which is intrinsic semiconductor, is deposited, to obtain an intrinsic layer I, and a silicon nitride (S i3 N₄) layer IN is deposited thereon by using the plasma CVD method. Note that the amorphorous silicon layer I and the S i3 N₄ layer IN are about 30 nm and 50 nm in thickness, respectively. Then, a patterning operation is carried out to obtain a configuration as shown in Fig. 43B and 43C. Next, as shown in Figs. 44A, 44B, and 44C, another silicon nitride (S i3 N₄) layer IN′ having a thickens of about 250 nm is deposited, and then, a pattering operation is carried out to form an opening O₂ as shown in Fig. 44B, and openings O₃ and O₄ as shown in Fig. 44C. Finally, as shown in Figs. 45A, 45B, and 45C, an aluminum (Al) layer is deposited by sputtering, and then a pattering operation is carried out to obtain the scan bus line S i and the reference voltage supply line V R as shown in Fig. 45B, and the scan bus lines S i and S i-1 ′ and the reference voltage supply line V R as shown in Fig. 45C. In Fig. 46, which is a fourteenth embodiment of the counter-matrix-type display device according to the present invention, the device of Fig. 36 and the device of Fig. 41 are combined, thus avoiding the occurrence of disconnections in the scan bus lines, and avoiding a defective display even if some disconnections occur in the scan bus lines. The manufacturing steps for the active liquid crystal device of Fig. 46 are shown in Figs. 47A through 50A, Figs. 47B through 50B, which are cross-sectional views taken along the line B-B of Figs. 47A through 50A, respectively, and Figs. 47C through 50C, which are cross-sectional views taken along the line C-C of Figs. 47A through 50A, respectively. However, the description of Figs. 47A through 50A, Figs. 47B through 50B, and Figs. 47C through 50C is omitted, since these figures can be easily understood from the descriptions with respect to Figs. 37A through 40A, Figs. 37B through 40B, Figs. 42A through 45A, Figs. 42B through 45B, and Figs. 42C through 45C. Although all the above-mentioned embodiments relate to a counter-matrix-type active liquid crystal display device as shown in Fig. 3, the present invention can be applied to a conventional active matrix-type liquid crystal display device as shown in Fig. 2. For example, if the device of Fig. 5 is applied to the conventional active matrix-type liquid crystal display device, a device as illustrated in Fig. 50 is obtained. In the above-mentioned embodiments, liquid crystal is used as an electro-optic element, however, an electroluminescence element, an electrochromic element, and the like can be also used. Various configuration, shape, material, and the like can be used for the above-mentioned active-type liquid crystal panel. As described above, according to the present invention, the shift voltage due to the various parasitic electrostatic capacities can be compensated for, to reduce the crosstalk, thereby improving the display quality. For example, the flickering can be avoided and the generation of a residual image phenomenon of a stationary image can be avoided. Also, since a redundancy in configuration is present for switching elements, it is possible to drive the switching element by one switching element even when another switching element is defective.

Claims: An active matrix-type display device, comprising: first and second insulating substrates (SUB₁, SUB₂) arranged in parallel to each other and having electro-optic material filled therebetween; a plurality of pairs of first and second scan bus lines (SP i , SN i ) in parallel formed on said first insulating substrate; a plurality of reference voltage supply bus lines in parallel formed on said first insulating substrate; a plurality of data bus lines (D j ) in parallel formed on said second insulating substrate, said data bus lines being perpendicular to said scan bus lines; a plurality of pixel electrodes (E ij ) in a matrix formed on said first insulating substrate at intersections of said first and second scan lines and said data bus lines; a plurality of first switching elements (TFTN ij ), each connected between one of said reference voltage supply bus lines and one of said display electrodes, said first switching elements being controlled by a potential at one of said first scanning bus lines and being turned ON when said potential is positive or negative; and characterized by a plurality of second switching elements, (TFTP ij , TFTN ij ), each connected between one of said reference voltage supply bus lines and one of said display electrodes, said second switching elements being controlled by a potential at one of said second scanning bus lines. A device as set forth in claim 1, wherein one pair of said first and second scan bus lines (SP i , SN i ) are provided for each row of said display electrodes. A device as set forth in claim 2, wherein said first and second scan bus lines (SP i , SN i ) are independent of each other. A device as set forth in claim 3, wherein said pair of first and second switching elements (TFTP ij , TFTN ij ) connected to one of said display electrodes are simultaneously turned ON by the potentials of the corresponding first and second scan bus lines (SP i , SN i ), respectively. A device as set forth in claim 2, wherein one scan bus line (SN i ) of one pair of said first and second scan bus lines (SP i , SN i ) for one row of said display electrodes and one scan bus lines (SP i+1 ) of another pair of said first and second scan bus lines (SP i+1 , SN i+1 ) for another row of said display electrodes adjacent to said row are integral. A device as set forth in claim 5, wherein said pair of first and second switching elements (TFTP ij , TFTN ij ) connected to one of said display electrodes are simultaneously turned ON by the potentials of the corresponding integral scan bus lines (SP i (SN i-1 ), SP i+1 (SN i )). A device as set forth in claim 2, wherein one scan bus line (SN i-1 ) of one pair of said first and second scan bus lines (SP i-1 , SN i-1 ) for one row of said display electrodes and one scan bus lines (SP i ) of another pair of said first and second scan bus lines (SP i , SN i ) for another row of said display electrodes adjacent to said row are integral, and the other scan bus line (SP i-1 ) of said one pair of said first and second scan bus lines (SP i-1 , SN i-1 ) for one row of said display electrodes and the other scan bus lines (SN i ) of said another pair of said first and second scan bus line (SP i , SN i ) for another row of said display electrodes adjacent to said row are integral. A device as set forth in claim 1, wherein said reference voltage supply lines comprise two kinds of lines (+ V R , - V R ) to which different reference voltages are applied, said first switching elements being connected to one of said two kinds of lines, and said second switching elements being connected to the other of said two kinds of lines. A device as set forth in claim 8, wherein said two kinds of lines (+ V R , - V R ) are alternately provided for every row of said display electrodes. A device as set forth in claim 1, wherein said first switching elements controlled by the potential at said first scanning bus lines are turned ON during an odd frame cycle, and said second switching elements controlled by the potential at said second scanning bus lines are turned ON during an even frame cycle. A device as set forth in claim 1, wherein each pair of said pairs of first and second scan bus lines (SP i , SN i ) is integral (S i ). A device as set forth in claim 11, wherein each of said integral scan bus lines for one row of said display electrodes is arranged on both sides thereof. A device as set forth in claim 1, wherein the potential at said reference voltage supply lines is fixed. A device as set forth in claim 1, wherein the potential at said reference voltage supply lines is switched from a first level to a second level or vice versa for each horizontal scanning time period. A device as set forth in claim 14, wherein each of said reference voltage supply bus lines is surrounded by two of said scan bus lines. A device as set forth in claim 15, wherein said two of scan bus lines surrounding one of said reference voltage supply bus lines are connected at a terminal (T i ). A device as set forth in claim 16, wherein a downstream side one of each two of said scan bus lines in a scanning direction has an extension (ES) along said data bus lines between said display electrodes. A device as set forth in claim 16, wherein a space between a downstream side one of each two of said scan bus lines in a scanning direction and its corresponding reference voltage supply bus line is larger than a space between an upstream side one of each two of scan bus lines in the scanning direction and its corresponding reference voltage supply bus line. A device as set forth in claim 14, wherein said electro-optic material is liquid crystal, and a difference between said first and second levels at said reference voltage supply bus lines is (V sat + V th ) where V sat is a voltage applied to a liquid crystal by which the display is brightest, and V th is a voltage applied to a liquid crystal by which the display is darkest. A device as set forth in claim 16, wherein a positive scan voltage V g applied to said terminal of selected two connected scan bus lines and a negative scan voltage - V cg applied to said terminal of two connected scan bus lines upstream of said selected two connected scan bus lines in a scan direction satisfy; V cg / V g ≅ C₂ / C₁ where C₁ is an electrostatic capacity between an upstream one of said two connected scan bus lines and display electrodes, and C₂ is an electrostatic capacity between a downstream one of said two connected scan bus line and said display electrodes. A device as set forth in claim 20, wherein said negative scan voltage - V cg is applied to said terminal of two connected scan bus lines downstream of said selected two connected scan bus lines. A device as set forth in claim 21, wherein an interlace scanning is carried out. A device as set forth in claim 15, wherein an arrangement of said first switching elements is asymmetrical to an arrangement of said second switching elements with respect to said reference voltage supply bus lines. A device as set forth in claim 16, wherein connections are provided to connect said two scan bus lines surrounding one of said reference voltage supply bus lines. A device as set forth in claim 1, wherein said first switching elements comprise N-channel type thin film transistors, and said second switching elements comprise P-channel type thin film transistors. A device as set forth in claim 1, wherein said first and second switching elements comprise N-channel type thin film transistors. A device as forth in claim 1, wherein said first and second switching elements comprise P-channel type thin film transistors. An active matrix-type display device, comprising: first and second insulating substrates (SUB₁, SUB₂) arranged in parallel to each other and having electro-optic material filled therebetween; a plurality of pairs of first and second scan bus lines (SP i , SN i ) in parallel formed on said first insulating substrate; a plurality of reference voltage supply bus lines in parallel formed on said second insulating substrate; a plurality of data bus lines (D j ) in parallel formed on said first insulating substrate, said data bus lines being perpendicular to said scan bus lines; a plurality of pixel electrodes (E ij ) in a matrix formed on said first insulating substrate at intersections of said first and second scan lines and said data bus lines; a plurality of first switching elements (TFTN ij ), each connected between one of said reference voltage supply bus lines and one of said display electrodes, said first switching elements being controlled by a potential at one of said first scanning bus lines and being turned ON when said potential is positive; and characterized by a plurality of second switching elements, (TFTP ij , TFTN ij ), each connected between one of said reference voltage supply bus lines and one of said display electrodes, said second switching elements being controlled by a potential at one of said second scanning bus lines. A device as set forth in claim 28, wherein one pair of said first and second scan bus lines (SP i , SN i ) are provided for each row of said display electrodes. A device as set forth in claim 29, wherein said first and second scan bus lines (SP i , SN i ) are independent of each other. A device as set forth in claim 30, wherein said pair of first and second switching elements (TFTP ij , TFTN ij ) connected to one of said display electrodes are simultaneously turned ON by the potentials of the corresponding first and second scan bus lines (SP i , SN i ), respectively. A device as set forth in claim 29, wherein one scan bus line (SN i ) of one pair of said first and second scan bus lines (SP i , SN i ) for one row of said display electrodes and one scan bus line (SP i+1 ) of another pair of said first and second scan bus lines (SP i+1 , SN i+1 ) for another row of said display electrodes adjacent to said row are integral. A device as set forth in claim 32, wherein said pair of first and second switching elements (TFTP ij , TFTN ij ) connected to one of said display electrodes are simultaneously turned ON by the potentials of the corresponding integral scan bus lines (SP i (SN i-1 ), SP i+1 (SN i )). A device as set forth in claim 29, wherein one scan bus line (SN i-1 ) of one pair of said first and second scan bus lines (SP i-1 , SN i-1 ) for one row of said display electrodes and one scan bus line (SP i ) of another pair of said first and second scan bus lines (SP i , SN i ) for another row of said display electrodes adjacent to said row are integral, and the other scan bus line (SP i-1 ) of said one pair of said first and second scan bus lines (SP i-1 , SN i-1 ) for one row of said display electrodes and the other scan bus line (SN i ) of said another pair of said first and second scan bus lines (SP i , SN i ) for another row of said display electrodes adjacent to said row are integral. A device as set forth in claim 28, wherein said reference voltage supply lines comprise two kinds of lines (+ V R , - V R ) to which different reference voltages are applied, said first switching elements being connected to one of said two kinds of lines, and said second switching elements being connected to the other of said two kinds of lines. A device as set forth in claim 35, wherein said two kinds of lines (+ V R , - V R ) are alternately provided for every row of said display electrodes. A device as set forth in claim 28, wherein said first switching elements controlled by the potential at said first scanning bus lines are turned ON during an odd frame cycle, and said second switching elements controlled by the potential at said second scanning bus lines are turned ON during an even frame cycle. A device as set forth in claim 28, wherein each pair of said pairs of first and second scan bus lines (SP i , SN i ) is integral (S i ). A device as set forth in claim 38, wherein each of said integral scan bus line for one row of said display electrodes is arranged on both sides thereof. A device as set forth in claim 28, wherein the potential at said reference voltage supply lines is fixed. A device as set forth in claim 28, wherein the potential at said reference voltage supply lines is switched from a first level to a second level or vice versa for each horizontal scanning time period. A device as set forth in claim 41, wherein each of said reference voltage supply bus lines is surrounded by two of said scan bus lines. A device as set forth in claim 42, wherein said two of scan bus lines surrounding one of said reference voltage supply bus lines are connected at a terminal (T i ). A device as set forth in claim 43, wherein a downstream side one of each two of said scan bus lines in a scanning direction has an extension (ES) along said data bus lines between said display electrodes. A device as set forth in claim 43, wherein a space between a downstream side one of each two of said scan bus lines in a scanning direction and its corresponding reference voltage supply bus line is larger than a space between an upstream side one of each two of scan bus lines in the scanning direction and its corresponding reference voltage supply bus line. A device as set forth in claim 41, wherein said electro-optic material is liquid crystal, and a difference between said first and second levels at said reference voltage supply bus lines is (V sat + V th ) where V sat is a voltage applied to a liquid crystal by which the display is brightest, and V th is a voltage applied to a liquid crystal by which the display is darkest. A device as set forth in claim 43, wherein a positive scan voltage V g applied to said terminal of selected two connected scan bus lines and a negative scan voltage - V cg applied to said terminal of two connected scan bus lines upstream of said selected two connected scan bus lines in a scan direction satisfy; V cg /V g ≅ C₂ / C₁ where C1 is an electrostatic capacity between an upstream one of said two connected scan bus lines and display electrodes, and C₂ is an electrostatic capacity between a downstream one of said two connected scan bus line and said display electrodes. A device as set forth in claim 47, wherein said negative scan voltage - V cg is applied to said terminal of two connected scan bus lines downstream of said selected two connected scan bus lines. A device as set forth in claim 48, wherein an interlace scanning is carried out. A device as set forth in claim 42, wherein an arrangement of said first switching elements is asymmetrical to an arrangement of said second switching elements with respect to said reference voltage supply bus lines. A device as set forth in claim 43, wherein connections are provided to connect said two scan bus lines surrounding one of said reference voltage supply bus lines. A device as set forth in claim 28, wherein said first switching elements comprise N-channel type thin film transistors, and said second switching elements comprise P-channel type thin film transistors. A device as set forth in claim 28, wherein said first and second switching elements comprise N-channel type thin film transistors. A device as set forth in claim 28, wherein said first and second switching elements comprise P-channel type thin film transistors.

Inventors: HAMADA TETSUYA, MISHIMA YASUYOSHI, OKI KENICHI, TAKAHARA KAZUHIRO, TANAKA TSUTOMU, YANAI KENICHI, HAMADA, TETSUYA, MISHIMA, YASUYOSHI, OKI, KENICHI, TAKAHARA, KAZUHIRO, TANAKA, TSUTOMU, YANAI, KENICHI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1991
Main classification: G09G3
IPC codes: G09G3, G02F1