Semiconductor device containing bipolar transistors

Abstract: A N⁺-type buried layer (32) is formed at the surface of a P-type semiconductor substrate (31) so as to correspond to the region in which a bipolar transistor is to be formed. Formed on the semiconductor substrate's surface containing the buried layer portion is a P-type epitaxial layer (33), in which an N-type well (34) is formed which extends from the layer's surface to the buried layer. In the well, a first diffusion layer (35) extending from the well's surface to the buried layer is formed as the collector. Also formed in the well is a P-type second diffusion layer (36), in which P⁺-type third and fourth diffusion layers (37, 38) are formed as a separate bases. An N⁺-type fifth diffusion layer (39) is formed as an emitter between the third and fourth diffusion layers. A collector electrode (42), a base electrode (43), and an emitter electrode (45) are taken from the first, third, and fifth diffusion layers, respectively, so that the fourth and fifth diffusion layers are connected to each other by an interconnection (46).

Description: This invention relates to a semiconductor device containing bipolar transistors, such as a logic circuit using Bi-CMOS (a circuit composed of bipolar transistors and complementary MOS transistors). Logic gate circuits composed of Bi-CMOS circuits, or Bi-CMOS logic gate circuits, are widely used because of the high operating speed and low power consumption. Fig. 8 shows a Bi-CMOS circuit, which contains a P-channel MOS transistor 11 and an N-channel MOS transistor 12, the gate electrodes of both transistors being supplied with an input signal. The source of the P-channel MOS transistor 11 is connected to a power supply V CC' while the drain of the transistor 11 is connected via a resistor 13 to the drain of the N-channel MOS transistor 12, whose source is connected via a resistor 14 to the ground. The drain of each of MOS transistors 11 and 12 is connected to the base of each of NPN bipolar transistors 15 and 16, respectively. This arrangement of MOS transistors 11 and 12, bipolar transistors 15 and 16, and resistor 13 and 14 provides an inverter circuit. In this inverter circuit, the resistor 13 (14) is connected across the base and emitter terminals of the NPN bipolar transistor 15 (16) as shown by a broken line. Fig. 9 shows a layout pattern of Bi-CMOS circuitry with the above-mentioned arrangement on semiconductor wafer 20. First set on this wafer 20 is an area 21 forming a basic CMOS cell, in which the P-channel MOS transistor 11 and N-channel MOS transistor 12 are formed. On both sides of the basic cell area 21, transistor areas 22 and 23 each forming bipolar transistors 15 and 16 are placed. Located adjacent to the transistor areas 22 and 23 are resistor areas 26 and 27 where resistor 13 and 14 are formed with diffused resistors 24 and 25. That is, the bipolar transistors 15 and 16 are formed in places different from places in which resistors 13 and 14 are formed. The reason for making the resistors 13 and 14 of the diffused resistors 24 and 25 is to lower production costs. The arrangement of the NPN bipolar transistors 15 and 16 and resistors 13 and 14 in separate places involves larger pattern areas for the diffused resistors 24 and 25, which, in turn, need separate well areas in which the areas 26 and 27 are set, resulting in the larger circuit layout area. From FR-A-2 341 203 corresponding to the preambule of claim 1 a semiconductor device containing bipolar transistors is known, including a resistor integrated together with a bipolar transistor, the resistor being formed in the base region below the emitter. It is an object of the invention to provide a semiconductor device containing bipolar transistors used in such as a Bi-CMOS circuit, which assures a reduction in the layout area compared with conventional equivalents. It is another object of the invention to provide a semiconductor circuit device that has similar functions to those with a circuit in which a resistor is connected across the base and emitter terminals of the bipolar transistor. It is still another object of the invention to provide a semiconductor device containing transistors in which the resistor between the base and emitter terminals of the bipolar transistor is realized by effective use of diffusion regions that are formed by diffusing impurities in wells, not by use of diffused resistors. In a semiconductor device according to the present invention, a first well for a bipolar transistor is formed at the main surface portion of a semiconductor substrate. Formed in the first well are a first diffusion fusion region acting as the collector and a second fusion region acting as the base. In the second region, a third and fourth diffusion regions are formed apart from each other. Formed between the third and fourth diffusion regions is a fifth diffusion region, which is electrically connected to the fourth diffusion region. A semiconductor device with the configuration according to claim 1 provides a bipolar transistor whose collector is the first diffusion region, whose base is the third and fourth diffusion regions, and whose emitter is the fifth diffusion region. The fourth diffusion region is electrically connected to the emitter made from the fifth diffusion region, below which the third and fourth diffusion regions are connected by the resistor element made up of the second diffusion region. Accordingly, the circuit with the resistor connected across the base and emitter of the bipolar transistor is formed, without using a diffused resistor or the like, in the region where the bipolar transistor has been formed in an ordinary way. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figs. 1 through 4 are sectional views illustrating the manufacturing processes in sequence of a semiconductor device according to an embodiment of the present invention; Fig. 5 is a sectional view of a semiconductor device thus produced, especially of a portion composing a bipolar transistor; Fig. 6 is a schematic plane view of the bipolar transistor; Fig. 7 shows a layout of a CMOS containing the bipolar transistor; Fig. 8 is a circuit diagram of a conventional Bi-CMOS circuit; and Fig. 9 illustrates a layout of the conventional Bi-CMOS circuit. A semiconductor device according to the present invention will be explained in the order of manufacturing processes. First, at the surface of a P-type semiconductor substrate 31 made from, for example, silicon, a photographic mask pattern is formed using photolithography as shown in Fig. 1. In the photographic mask pattern, an opening is made at a place where a bipolar transistor is to be formed. Through the mask pattern, antimony (Sb) is diffused into the surface of the semiconductor substrate 31 to form an N + -type buried layer 32. On the surface of the semiconductor substrate 31 in which the buried layer has been formed, a P-type silicon is grown epitaxially to form a P-type epitaxial layer 33. Then, as shown in Fig. 2, phosphorous (P) ions are implanted into a specified portion at the surface of the P-type epitaxial layer 33. Specifically, with an accelerating voltage of 160 KeV at a dose rate of 3 x 10 12 , ion implantation of phosphorous is carried out to form an N-type well 34 in the P-type epitaxial layer 33, which portion is located the N + -type buried layer 32. After the well 34 is formed at the place where a bipolar transistor is to be formed, phosphorous (P) ions are implanted into the well 34 through the photographic mask pattern. Specifically, with an accelerating voltage of 50 KeV at a dose rate of 5 x 10 15 , phosphorous ions are implanted into the region acting as the collector of the bipolar transistor so that the ions may reach the N + -type buried layer 32 to form a first diffusion region 35 of N + -type. The impurity atom concentration in the first diffusion region 35 is set at a higher value than that in the N + -type buried layer 32. After the N + -type first diffusion region 35 is formed as the collector in the well 34, boron fluoride (BF 2 ) ions are implanted through the photographic mask pattern into a portion adjacent to the first diffusion region 35 in the well 34, under conditions of an accelerating voltage of 30 KeV at a dose rate of 1 x 10 13 . By using the same mask pattern, ion implantation of boron (B) is performed into the same portion of the well 34 with an accelerating voltage of 25 KeV at a dose rate of 5.6 x 10 13 to form a second diffusion region 36 serving as an intrinsic base region. As shown in Fig. 4, boron fluoride (BF 2 ) ions are then implanted through a mask pattern into two regions opposite from each other in the second diffusion region 36, to form a P + -type third diffusion region 37 and a P + -type fourth diffusion region 38 facing and separating from each other. The FB 2 ions are implanted under conditions of, for example, an accelerating voltage of 40 KeV at a dose rate of 5 x 10 15 , to form two separate bases. After the third and fourth diffusion regions 37 and 38 are formed, arsenic (As) ions are implanted into a surface portion of the second diffusion region 36 and between the third and fourth diffusion regions 37 and 38 with an accelerating voltage of 40 KeV at a dose rate of 5 x 10 15 , to form a fifth diffusion region 39 of N + -type acting as the emitter. The impurity atom concentration in the fifth diffusion region 39 is set at a value higher than that in the P-type diffusion region 36. After the formation of the collector, bases, and emitter of a bipolar transistor is complete, as shown in Fig. 5, a silicon oxide film 40 and a PSG (silicate glass containing phosphorous) film 41 are formed on the epitaxial layer 33. In the films 40 and 41, contact holes are made which lead to the first diffusion region 35 as the collector, the third and fourth diffusion regions 37 and 38 as the bases, and the fifth diffusion region 39 as the emitter, respectively. In these holes, aluminum is embedded to form terminal electrodes 42, 43, 44, and 45. The terminal electrode 45 to the fifth diffusion region 39 and the terminal electrode 44 to the fourth diffusion region 38 are connected to each other with aluminum interconnection 46. The collector terminal C, base terminal B, and emitter terminal E are taken from the terminal electrodes 42, 43, and 45, respectively. With this arrangement where an NPN bipolar transistor is formed on the semiconductor substrate 31, there is no need for separate wells to be formed in the semiconductor wafer and for diffused resistors to be formed in the wells as shown in Fig. 9. The fourth diffusion region 38 and the fifth diffusion region 39 constituting the emitter are connected with the interconnection 46, while the third and fourth diffusion regions 37 and 38 are connected to each other via a bulk resistor R composed of the second diffusion region 36 just below the fifth diffusion region 39 constituting the emitter. That is, the resistor R is formed so as to be connected across the base and emitter of the NPN bipolar transistor. Fig. 6 is a schematic plane of an NPN bipolar transistor thus produced. In the N-type well 34, the first diffusion region 35 is formed as the collector region, next to which the P-type second diffusion region 36 is formed. The P + -type third diffusion region 37 and fourth diffusion region 38 serving as the base regions are formed at both ends of the second diffusion region 36. Formed between the third and fourth diffusion regions 37 and 38 is the fifth diffusion region 39 acting as the emitter region. In an NPN bipolar transistor of this arrangement, if the resistor R immediately below the fifth diffusion region 39 has a sheet resistance of 20 KΩ/ ▭ , the size of the fifth diffusion region 39 as the emitter is 2.4 µm x 3.9 µm, the resistance of the resistor R between the base and emitter will be: R = 20 x 2.4/3.9 = 12.3 (KΩ) To make resistance of the resistor R smaller requires broadening the width of the fifth diffusion region 39 constituting the emitter. Thus, the resistance of the resistor connected across the base and emitter of the NPN bipolar transistor can be adjusted by changing the dimension of the fifth diffusion region 39. Fig. 7 shows a layout of a Bi-CMOS circuit pattern embodying the circuit shown in Fig. 8 using the NPN bipolar transistor produced in the manner mentioned above. Set on the semiconductor substrate 31 is a basic cell area 50, in which the P-channel MOS transistor 11 and N-channel MOS transistor 12 shown in Fig. 8 are formed. On one side of the basic cell area 50, wells 341 and 342 are formed, in which NPN bipolar transistors 15 and 16 with the pattern shown in Fig. 6 are formed respectively. Here, symbol C indicated the collector corresponding to the first diffusion region 35, symbol B the base corresponding to the third and fourth diffusion regions 37 and 38, and symbol E the emitter corresponding to the fifth diffusion region 39. With this configuration where the resistor connected between the emitter and base of the NPN bipolar transistor is realized by making use of the resistor formed directly below the emitter region, the Bi-CMOS circuit requires no special diffused resistor elements, assuring a reduction in the layout area for the circuit compared with conventional equivalents. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A semiconductor device containing bipolar transistors, comprising: a semiconductor substrate (31) of a first conductivity type; a buried layer (32) of a second conductivity-type formed at the surface of said semiconductor substrate so as to correspond to the region in which a bipolar transistor is to be formed; an epitaxial layer (33) of the first conductivity type, formed on said semiconductor substrate including said buried layer region; a well (34) of the second conductivity type formed in said epitaxial layer on said buried layer region, said well (34) extending from the exposed surface of said epitaxial layer (33) to said buried layer (32), the impurity atom concentration of which is lower than that in said buried layer; a first diffusion region (35) of the second conductivity type formed as the collector so as to extend from the said well's surface to said buried layer, the impurity atom concentration of which is higher than that in said buried layer; a second diffusion region (36) of the first conductivity type formed at the surface of said well in the vicinity of said first diffusion region, the impurity atom concentration of which is higher than that in said second conductivity-type well; a third and a fourth diffusion region (37,38) of the first conductivity type each formed separately as the basis on opposite sides of and in contact with said second diffusion region, the impurity atom concentration of which is higher than that in said second diffusion region; a fifth diffusion region (39) of the second conductivity type located as the emitter between said third and fourth diffusion regions at the surface of said second diffusion region, the impurity atom concentration of which is higher than that in said second diffusion region, characterized in that: the portion of said second diffusion region (36), formed directly below said fifth diffusion region acts as a resistor (R), said resistor thus connecting said third diffusion region (37) with said fourth diffusion region (38); and an interconnection (44,45,46) directly electrically connecting said fourth diffusion region (38) with said fifth diffusion region (39) and being isolated from said second diffusion region (36) through a silicon oxide film (40) and a PSG film (41) which are formed on the surface of the second diffusion region (36). A semiconductor device according to claim 1, characterized by further comprising a basic CMOS cell region (50) containing a P-channel and/or an N-channel MOS transistor (11,12), which is formed outside and in the vicinity of said well region (34) in said semiconductor substrate (31). A semiconductor device according to claim 1, characterized in that said first conductivity type is P-type and said second conductivity type is N-type.

Inventors: TSUGARU KAZUNORI C O INTELLECT, TSUGARU, KAZUNORI, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: H01L27
IPC codes: H01L27, H01L29, H01L21