Apparatus and method of reproducing synchronization signal in disc storage system

Abstract: An apparatus and a method of reproducing a synchronization signal in a disc storage system. The apparatus includes a a disc mechanism (3) having a plurality of information storage discs in one of which a predetermined servo pattern is recorded, and a corresponding plurality of reproducing heads, one of the heads reading the servo pattern from the corresponding disc to thereby output a servo signal, a synchronization signal demodulating unit (4), responsive to the servo signal from the disc mechanism, for demodulating a synchronization signal in synchronization with a rotation of the discs, a synchronization clock generating unit (5) for generating a clock signal with a predetermined frequency in synchronization with the synchronization signal, and a gate unit (6). For a predetermined period, the gate unit prohibits a supply of the synchronization signal from the synchronization signal demodulating unit to the synchronization clock generating unit. As a result, it is possible to prevent an erroneous detection of a synchronization signal due to a spike noise, an undesirable signal by a defect of a medium, or the like, and thus realize a precise reproducing of the synchronization signal.

Description: The present invention relates to a technique of reproducing a synchronization signal in a disc storage system. More particularly, it relates to an improvement of a disc-drive apparatus in a magnetic disc storage system, which demodulates a synchronization signal based on a servo signal read from a servo disc via a servo head and generates a basic clock signal for data writing or a window signal for use of a demodulation of a position signal for head positioning. In recent years, a magnetic disc storage system has been demanded to enable high density writing and high speed head positioning, i.e., a high speed access, and morever to carry out a stable operation. To this end, it is necessary to generate a basic clock signal in precise synchronization with a synchronization signal demodulated from a servo signal. Also, it is necessary to use a window signal based on a synchronization signal demodulated from a servo signal to thereby demodulate a high quality head position signal. Accordingly, a synchronization signal demodulated from a servo signal must be prevented from being erroneously detected. Otherwise, it is necessary to suppress an erroneous detection of the synchronization signal to a minimum extent. In a known disc-drive apparatus, however, a problem occurs in the case that a spike noise, an undesirable signal, or the like, is contained in a servo signal read out by the servo head. For example, where a spike noise occurs between signal patterns forming the synchronization signal, the synchronization signal is demodulated at an unexpected timing and thus an erroneous detection thereof is carried out. This results in a fluctuation in level of a basic clock signal based on the synchronization signal, appearance of a jitter in the write signal, occurrence of a positioning error in the position servo loop, or the like. Note, the problem in what is considered to be the closest prior art will be explained in detail later in contrast with the preferred embodiment of the present invention. Synchronization signals in optically readably compact disks and video disks are considered in EP-0 220 007 and USA 4908812. An object of the present invention is to provide a disc storage system in which a synchronization signal can be precisely reproduced. Another object of the present invention is to provide a disc-drive apparatus which can prevent an erroneous detection of a synchronization signal due to a spike noise, an undesirable signal by a defect of a medium, or the like, to thereby contribute to a reliable data writing or a precise head positioning. According to a first aspect of the present invention, there is provided a disc data storage system and an apparatus for reproducing a synchronization signal contained therein comprising a magnetic disc mechanism having a plurality of disc surfaces, each disc surface having at least one head, the mechanism including a first servo disc on which at least one predetermined servo pattern for controlling the heads of the other discs is recorded, and a servo head for reading the servo pattern from the first servo disc to thereby output a servo signal; a synchronization signal demodulating means, responsive to the servo signal from the disc mechanism, for demodulating the servo pattern to form a synchronization signal which is in synchronization with the rotation of the first servo disc; and a synchronization clock generating means for generating a clock signal with a predetermined frequency, to be synchronised with the synchronization signal, the clock signal being usable for controlling further demodulating of the servo pattern; and characterised by a gate means, operatively connected between the synchronization signal demodulating means and the synchronization clock generating means, for prohibiting a supply of any pulse of the synchronization signal from the synchronisation signal demodulating means to the synchronization clock generating means for a predetermined period, thereby inhibiting the synchronisation of the clock signal with a pulse of the synchronisation signal that has been generated in error, the predetermined period being defined by the interval between when a first pulse of the synchronization signal is obtained by the synchronization signal demodulating means and when a subsequent non-erroneous pulse of the synchronization signal is obtained thereby. Furthermore, according to a second aspect of the present invention, there is provided a method of reproducing a synchronization signal in a system having a magnetic disc mechanism which includes at least one servo disc and a plurality of data discs, and generates a servo signal based on information from the servo disc, the method comprising the steps of: demodulating a synchronization signal from the servo signal extracted from the disc mechanism; generating a clock signal and setting it to be in synchronization with the demodulated synchronization signal, for controlling further demodulation of the synchronization signal; characterized by using a gate means located between a demodulating means and a clock signal generating means for prohibiting a supply of any pulse of the synchronization signal from the synchronisation signal demodulating means to the synchronization clock generating means for a predetermined period, thereby inhibiting the synchronisation of the clock signal with a pulse of the synchronisation signal that has been generated in error, the predetermined period being defined by the interval between when a first pulse of the synchronization signal is obtained by the synchronization signal demodulating means and when a subsequent non-erroneous pulse of the synchronization signal is obtained thereby. For a better understanding of the invention, and to show how the same may be carried into effect, reference will now be made, purely by way of example, to the accompanying drawings, in which: Fig. 1 is a block diagram illustrating a constitution of part of a prior art disc-drive apparatus; Figs. 2a and 2b are a block diagram and a timing chart for explaining the principle of the disc-drive apparatus according to the present invention; Fig. 3 is a block diagram illustrating a constitution of part of the disc-drive apparatus as an embodiment of the present invention; Fig. 4 is an explanatory view of the servo pattern and the servo signal used in the embodiment of Fig. 3; Fig. 5 is a timing chart for explaining the operation of the position signal demodulating circuit shown in Fig. 3; Fig. 6 is an explanatory view of the position signals generated from the position signal demodulating circuit; Fig. 7 is a circuit diagram illustrating a constitution of the synchronization signal demodulating circuit shown in Fig. 3; Fig. 8 is a timing chart for explaining the operation of the synchronization signal demodulating circuit of Fig. 7; Fig. 9 is a circuit diagram illustrating a constitution of the gate circuit shown in Fig. 3; Fig. 10 is a timing chart for explaining the operation of the gate circuit of Fig. 9; Fig. 11 is a block diagram illustrating a constitution of the PLL circuit unit shown in Fig. 3; Fig. 12 is a circuit diagram illustrating a constitution of the PLL circuit shown in Fig. 11; Fig. 13 is a circuit diagram illustrating a constitution of the counter circuit shown in Fig. 11; Fig. 14 is a timing chart for explaining the operation of the counter circuit of Fig. 13; Fig. 15 is a timing chart for explaining the operation of the PLL circuit of Fig. 12; and Figs. 16a and 16b are flow charts for explaining the processings at a power-ON start, executed by the apparatus of Fig. 3. For a better understanding of the preferred embodiment of the present invention, the problem in the prior art will be explained with reference to Fig. 1. Figure 1 illustrates a constitution of part of a prior art disc-drive apparatus. In the illustration, reference 14 denotes a disc mechanism 14, which is provided with a plurality of magnetic discs each rotated with a constant speed by a spindle motor 26. One of the magnetic discs is a servo disc 10 in which predetermined servo patterns are recorded. The servo patterns in the servo disc 10 are read out by a servo head 12 and output as a servo signal E1. The servo signal E1 from the servo head 12 is amplified by an automatic gain control (AGC) amplifying circuit 28 and then fed as a synchronization signal E2 to a synchronization signal demodulating circuit 16 and a position signal demodulating circuit 30 in a head positioning unit 24. The synchronization signal demodulating circuit 16 is constituted, for example, as shown in Fig. 7, and the operation thereof is shown in Fig. 8. Referring to Figs. 7 and 8, the synchronization signal demodulating circuit 16 first compares the synchronization signal (servo signal) E2 with a reference voltage Vref in a comparator 36 and then produces a comparison output of "H" level when the servo signal E2 exceeds the reference voltage Vref. The comparison output is converted by a monostable multivibrator (MSMV) 38 into a signal with a constant pulse width. The subsequent monostable multivibrator 42 responds to the signal with a constant pulse width and produces a window signal with a constant pulse width, which is triggered at a first rise of two successive pulses in the output of the MSMV 38. Then, the window signal and the output of the MSMV 38 are input to a logical OR gate 44, which outputs a synchronization signal E3 in synchronization with one rotation of the disc. The synchronization signal E3 demodulated by the synchronization signal demodulating circuit 16 is fed to a phase-locked loop (PLL) circuit unit 18 functioning as a synchronization clock generating circuit. The PLL circuit unit 18 then generates a clock signal E4 with a predetermined frequency in synchronization with the synchronization signal E3 by the phase control using the synchronization signal E3 as a reference signal, and outputs the signal E4 to a processor 22. The processor 22 uses the clock signal E4 as a basic signal in the data writing operation or a reference clock signal for discrimination of a data signal in the regenerative operation. Also, the PLL circuit unit 18 generates window signals E5, E6, E7 and E8 based on the synchronization signal E4 and feeds the window signals to a position signal demodulating circuit 30. The position signal demodulating circuit 30 sets peak hold timings of the servo signal based on the window signals to thereby demodulate a position signal E9 indicating a head position. The position signal E9 is fed to a servo circuit 32, which drives a voice coil motor 34 of the disc mechanism 14 using a drive signal E10 so that the head follows a target position designated by the processor 22. Note, after the rotational speed of the disc is increased by a power-ON start and then reaches a regular speed and thus a return-to-zero (RTZ) processing of positioning the servo head on a zero cylinder (e.g., outermost cylinder in the disc mechanism 14) is started, the processor 22 makes effective a lock-to-servo (LTSV) signal E11 and thereby causes the synchronization signal demodulating circuit 16 to start its demodulating operation. In the prior art apparatus, however, a problem occurs in that, where a spike noise, an undesirable signal due to a defect of the medium, or the like, is contained in the servo signal read out by the servo head, the synchronization signal is demodulated at an unexpected timing and thus an erroneous detection thereof is carried out. For example, where a spike noise occurs between signal patterns forming the synchronization signal, as shown in the servo signal E2 of Fig. 8, the synchronization signal is demodulated at an unexpected timing. When the synchronization signal is erroneously demodulated, the clock signal E4 fed to the processor 22 from the PLL circuit unit 18 and the window signals E5 to E8 fed to the position signal demodulating circuit 30 therefrom fluctuate in level. As a result, a drawback arises in that a jitter occurs in the write signal, or that the position signal cannot be demodulated and thus a positioning error occurs in the position servo loop. Figures 2a and 2b show the principle of the disc-drive apparatus according to the present invention. As shown in Fig. 2a, the disc-drive apparatus having a function of reproducing a synchronization signal according to the present invention includes: a disc mechanism 3 including a servo disc 1 in which at least one predetermined servo pattern is recorded, and a servo head 2 for reading the servo pattern from the servo disc 1 to output a servo signal; a synchronization signal demodulating unit 4, responsive to the servo signal from the disc mechanism 3, for demodulating a synchronization signal in synchronization with a rotation of the servo disc 1; a synchronization clock generating unit 5 for generating a clock signal with a predetermined frequency in synchronization with the synchronization signal; and a gate unit 6 for prohibiting a supply of the synchronization signal from the synchronization signal demodulating unit 4 to the synchronization clock generating unit 5 for a predetermined period. In the preferred embodiment of the present invention, the predetermined period is defined by a period covering from when a synchronization signal is obtained by the synchronization signal demodulating unit 4 until a subsequent synchronization signal is obtained thereby. According to the above constitution, the apparatus of the present invention functions as shown in the timing chart of Fig. 2b. Namely, even if a spike noise, an undesirable signal due to a defect of the medium, or the like, is contained in the servo signal read from the servo head 2 and thus the synchronization signal is erroneously demodulated, the gate unit 6 prohibits a supply of the demodulated synchronization signal to the synchronization clock generating unit 5 for the predetermined period, i.e., for a period other than right timings at which the demodulation is to be carried out. Accordingly, it is possible to remove a drawback in that a jitter occurs in the write signal due to an erroneously demodulated synchronization signal, and thus prevent a case that the head position signal cannot be demodulated, from happening. Namely, it is possible to reproduce a precise synchronization signal which enables a high density writing, a high speed head positioning and an extremely stable head positioning. Figure 3 illustrates a constitution of part of the disc-drive apparatus as an embodiment of the present invention. Referring to Fig. 3, the disc mechanism 14 is provided with a plurality of magnetic discs each rotated with a constant speed by the spindle motor 26. One of the magnetic discs is the servo disc 10 in which predetermined servo patterns P1 to P4 (see Fig. 4) are repeatedly recorded. The servo head 12 provided for the servo disc 10 is moved and positioned together with other heads by the voice coil motor 34 in the radial direction of the corresponding disc. The servo head 12 reads the servo patterns from the servo disc 10 and outputs the servo signal E1 to the outside of the disc mechanism 14. Details of the servo pattern in the servo disc 10 and the servo signal E1 read out by the servo head 12 will be explained with reference to Fig. 4. The portion of the left side of Fig. 4 shows a magnetic record status of servo patterns on five tracks taken from the servo disc 10. From the up side of the illustration, the servo patterns P1, P2, P3 and P4 are recorded in sequence and, thereafter in the same manner, the servo patterns P1 to P4 are repeatedly recorded in the radial direction of the disc. Also, each of the servo patterns P1 to P4 is formed in the circumferential direction (track direction) of the disc such that the respective proper magnetic record is made between each synchronization pattern consisting of three "NS"s recorded with a small pitch, and that it is repeatedly recorded in the circumferential direction of the disc. The portion of the right side of Fig. 4 shows one pattern of a signal waveform of the servo signal E1 obtained when the servo head 12 is located in the sequence of cylinders CY0, CY1 and CY2. For example, a signal waveform of the servo signal E1 obtained when the servo head 12 is located at the position of the cylinder CY2 includes three amplitude patterns having two relatively small amplitude changes and one relatively big amplitude change between two cycles of the synchronization pattern. Referring to Fig. 3 again, the servo signal E1 output from the servo head 12 is amplified by the AGC amplifying circuit 28 and then fed as the synchronization signal (servo signal) E2 to the synchronization signal demodulating circuit 16 and the position signal demodulating circuit 30 in the head positioning unit 24. The position signal demodulating circuit 30 in the head positioning unit 24 uses the window signals E5 to E8 obtained from a synchronization signal E14 (explained later) to thereby demodulate the position signal E9 indicating the head position. Figure 5 shows a timing chart representing the operation of the position signal demodulating circuit 30. Referring to Fig. 5, the signal waveform obtained when the servo head 12 is located at the position of the cylinder CY2 shown in Fig. 4 is considered as the servo signal E2. The position signal demodulating circuit 30 receives the servo signal E2 and the window pulses E5 to E8 generated based on the synchronization signal and, using a peak detecting circuit (not shown), detects peak detection signals A, B, C and D between two adjacent synchronization patterns in the servo signal E2. The position signal demodulating circuit 30 uses the peak detection signals A to D thus detected based on the window pulses E5 to E8 and a reference level signal R (see Fig. 6) and produces two kinds of position signals POSN and POSQ as the position signal E9. The position signals POSN and POSQ are expressed as follows: [POSN] = [A] - [B] + [R] [POSQ] = [C] - [D] + [R] Figure 6 shows changes of the position signals POSN and POSQ relative to the movement of constant speed of the servo head. The movement speed of the head is determined by dividing one track pitch by a period of the crossing of the position signal POSN, POSQ relative to the reference level R. Also, the head positioning control can be carried out by generating a track crossing pulse at every period of the crossing and thus subtracting an access difference between the present track and a target track. The position signal E9 consisting of the two kinds of position signals POSN and POSQ demodulated in the position signal demodulating circuit 30 is fed to the servo circuit 32. The servo circuit 32 outputs the drive signal E10 to the voice coil motor 34 and thus causes the voice coil motor 34 to move the servo head 12 together with other heads such as a data head to a target position designated by the processor 22. Namely, the servo circuit 32 effects the position servo control for positioning the heads to the target position. On the other hand, the servo signal E2 amplified by the AGC amplifying circuit 28 is fed to the synchronization signal demodulating circuit 16, which demodulates the synchronization signal E3 from the synchronization patterns in the synchronization signal E2. Figure 7 illustrates a constitution of the synchronization signal demodulating circuit 16 shown in Fig. 3, and Fig. 8 shows a timing chart representing the operation thereof. Referring to Figs. 7 and 8, the servo signal E2 from the AGC amplifying circuit 28 is fed to a comparator 36 in which a reference voltage Vref is set. The comparator 36 compares the servo signal E2 with the reference voltage Vref and, when the servo signal E2 exceeds the reference voltage Vref, produces a comparison output of "H" level. The output of the comparator 36 is input to a monostable multivibrator (MSMV) 38, which is triggered at a rise of the comparison output and thus produces a pulse output of "L" level for a constant time at the output QX. The output (QX) of the MSMV 38 is fed via an OR gate 40 to a monostable multivibrator 42. The MSMV 42 is triggered at a first rise of two successive pulses in the output of the MSMV 38 and thus generates a window signal of "L" level for a constant time, which is approximately one cycle of the synchronization pattern in the synchronization signal E2. The inverted output QX of the MSMV 42 is fed back to the OR gate 40. Since the "Q" output of the MSMV 42 (i.e., window signal) is first at "H" level, the OR gate 40 passes the first "L" level pulse output from the MSMV 38 based on the servo patterns. However, when the MSMV 42 is triggered to thereby generate the "Q" output of "L" level, the OR gate 40 prohibits a pass of the subsequent second "L" level pulse obtained by the MSMV 38. Namely, the MSMV 42 is triggered only by the first "L" level pulse of the two "L" level pulses in the output of the MSMV 38 obtained from the synchronization patterns. The "Q" output of the MSMV 42 (window signal) together with the output (QX) of the MSMV 38 is input to an OR gate 44. Accordingly, the OR gate 44 produces a logical sum of the "L" level window signal from the MSMV 42 and the "L" level pulse from the MSMV 38 to thereby output a synchronization signal E3 in synchronization with one rotation of the disc. The output of the OR gate 44 is fed to an OR gate 46 provided in the last stage, which receives a lock-to-servo (LTSV) signal E11 from the processor 22 (see Fig. 3) via an inverter 48. Accordingly, when the LTSV signal Ell is made "H" level, the output of the inverter 48 is made "L" level and thus the AND gate 46 is made effective to permit the synchronization signal E3 to be output to the outside. Note, the LTSV signal Ell is made "H" level in a predetermined time after the rotational speed of the disc driven by the spindle motor 26 is increased by a power-ON start and then reaches a regular speed (in the present example, 4340 r.p.m.) and thus a return-to-zero (RTZ) processing is started. The predetermined time is defined by a constant time in which the servo head 12 reaches a data region on the servo disc 10. Referring to the timing chart of Fig. 8, a state is shown in which a spike noise appears between the synchronization patterns in the servo signal E2. Since the level of the spike noise is above the reference level Vref, a comparison output due to the spike noise appears in the output of the comparator 36. Accordingly, the output of the MSMV 38 is generated based on the comparison output by the spike noise and the setting of the window signal is carried out. As a result, the synchronization signal E3 contains a synchronization signal erroneously detected due to the spike noise. Referring to Fig. 3 again, the synchronization signal E3 demodulated in the synchronization signal demodulating circuit 16 is fed to a gate circuit 20. Figure 9 illustrates a constitution of the gate circuit 20 shown in Fig. 3, and Fig. 10 shows a timing chart representing the operation thereof. Referring to Figs. 9 and 10, a third count signal CT3 output from a counter circuit (explained later) in the PLL circuit unit 18 is input to a clock terminal CLK of a D-type flip-flop 48. Also, a thirteenth count signal CT13 output from the counter circuit in the PLL circuit unit 18 is input to one input end of an NOR gate 50, which receives an inverted signal (*GLTSV signal E12) of a gated LTSV signal from the processor 22 at another input end. The *GLTSV signal E12 is made "L" level when the servo head 12 is positioned on the zero cylinder, i.e., brought to an on-track state, by the RTZ processing after the rotational speed of the disc reaches the regular speed (4340 r.p.m.). The output of the NOR gate 50 is input to a clear terminal CLR of the D-type flip-flop 48. A data terminal D of the D-type flip-flop 48 is fixed to "H" level pulled up to the power supply voltage Vcc. The output (QX) of the D-type flip-flop 48 is fed to one input end of a NAND gate 52, which receives the LTSV signal Ell at another input end. As previously explained, the LTSV signal Ell is made "H" level in a predetermined time after the rotational speed of the disc reaches the regular speed. The output of the NAND gate 52 forms a window signal E13, which is input to an AND gate 54 together with the synchronization signal E3. The AND gate 54 outputs a synchronization signal E14. Referring to Fig. 3 again, the synchronization signal E14 output from the gate circuit 20 is fed to the PLL circuit unit 18. Figure 11 illustrates a constitution of the PLL circuit unit 18, which is provided with a PLL circuit 56 and a counter circuit 58. In Fig. 11, the PLL circuit 56 receives the synchronization signal E14 and a seventh count signal CT7 output from the counter circuit 58. The oscillation output of the PLL circuit 56 is fed to the processor 22 (see Fig. 3) as a clock signal E4 with a predetermined frequency (in the present example, 18 MHz) in synchronization with the synchronization signal E14. On the other hand, the counter circuit 58 supplies the gate circuit 20 (see Fig. 9) with the third count signal CT3 and the thirteenth count signal CT13 and thus causes the gate circuit 20 to produce the window signal E13 for removal of an erroneously demodulated synchronization signal. Figure 12 illustrates a constitution of the PLL circuit 56. In Fig. 12, the PLL circuit 56 is constituted by a monostable multivibrator (MSMV) 60, a phase comparator (PC) 61, an integrator 62 using a low pass filter (LPF), and a voltage controlled oscillator (VCO) 63. The phase comparator 61 receives the synchronization signal E14 input via the MSMV 60 and the seventh count signal CT7 output from the counter circuit 58 (see Fig. 11), and effects a phase control of the oscillation clocks from the VCO 63 such that a phase difference between the output pulse of the MSMV 60 and the seventh count signal CT7 is made zero. Figure 13 illustrates a constitution of the counter circuit 58, and Fig. 14 shows a timing chart representing the operation thereof. In Fig. 13, reference 66 denotes a D-type flip-flop, which frequency-divides into a half the clock signal E4 input from the PLL circuit 56 via an inverter IV. Note, the D-type flip-flop 66 is cleared by a power-ON start signal E15 which is obtained as a "L" level signal at a power-ON start. The clock signal E16 frequency-divided by the D-type flip-flop 66 into a half is fed to a counter 68. The counter 68 is constituted by a binary counter and generates four count outputs CUT1, CUT2, CUT4 and CUT8 having weights of "1", "2", "4" and "8" in a decimal expression, respectively. In the embodiment of Fig. 13, the clock signal E4 from the PLL circuit 56 includes thirty-two clock pulses within one period (T) defined by the synchronization signal (see Fig. 14). Accordingly, the "Q" output of the D-type flip-flop 66 (1/2 frequency-divided clock signal E16) includes sixteen clock pulses within one period (T). The counter 68 counts the sixteen clock pulses (signal E16) in one period (T) defined by the synchronization signal, and generates the count outputs CUT1, CUT2, CUT4 and CUT8 each having the respective weight, as shown in Fig. 14. The count outputs CUT1, CUT2 and CUT4 are input in a parallel manner to decoders 70 and 72 provided in the subsequent stage. On the other hand, the count output CUT8 is fed an OR gate 74 to an enable terminal E of the decoder 70, and fed via an inverter 76 and an OR gate 78 to an enable terminal E of the decoder 72. When the counted value in the counter 68 is within 1 to 8, the count output CUT8 is at "L" level (see Fig. 14). Accordingly, the OR gate 74 is made effective and the OR gate 78 is made ineffective. As a result, the clock signal E16 from the D-type flip-flop 66 is fed via the OR gate 74 to the enable terminal E of the decoder 70 and thus the decoder 70 functions to generate its decode output of the corresponding counted value converted into the decimal digit from the binary digit. On the other hand, when the counted value in the counter 68 is within 9 to 16, the count output CUT8 is at "H" level (see Fig. 14). Accordingly, the OR gate 74 is made ineffective and the OR gate 78 is made effective. As a result, the clock signal E16 is fed via the OR gate 78 to the enable terminal E of the decoder 72 and thus the decoder 72 generates its decode output of the corresponding counted value converted into the decimal digit from the binary digit. The output at a decode terminal X2 corresponding to the third count output of the decoder 70 which generates the decode output ocorresponding to the first half (1 to 8) of the counted values is fed via an inverter 80 to the gate circuit 20 shown in Fig. 9 (third count signal CT3). On the other hand, the output at a decode terminal X4 corresponding to the thirteenth count output of the decoder 72 which generates the decode output ocorresponding to the second half (9 to 16) of the counted values is fed via an inverter 82 to the gate circuit 20 (thirteenth count signal CT13). Also, the output at a decode terminal X6 corresponding to the seventh count output of the decoder 70 is fed via an inverter 84 to the phase comparator 61 in the PLL circuit 56 shown in Fig. 12 (seventh count signal CT7). The window signal E13 (see Fig. 10) is produced by the NOR gate 50, the D-type flip-flop 48 and the NAND gate 52 (see Fig. 9) in synchronization with the rise to "H" level of the third count signal CT3 (see Fig. 14) generated in synchronization with the third clock in the sixteen clock pulses (signal E16) obtained in one period (T) defined by the synchronization signal and the rise to "H" level of the thirteenth count signal CT13 (see Fig. 14) generated in synchronization with the thirteenth clock in the sixteen clock pulses (signal E16). Figure 15 shows a timing chart representing the operation of the PLL circuit 56 of Fig. 12. Referring to Fig. 15, the seventh count signal CT7 is produced by the counter circuit 58 (see Fig. 13) in synchronization with the seventh clock in the sixteen clock pulses (signal E16) obtained in one period (T) defined by the synchronization signal. The monostable multivibrator 60 (see Fig. 12) receives the synchronization signal E14 and is triggered by the rise to "H" level of the synchronization signal E14 to thereby generate a pulse output with a pulse width T1 (see Fig. 15) corresponding to seven clocks in the sixteen clock pulses (signal E16). Accordingly, the phase comparator 61 compares a phase at the rise to "H" level of the seventh count signal CT7 with that at the fall to "L" level of the output pulse of the MSMV 60, and effects the phase control of the oscillation clocks from the VCO 63 such that the phase difference therebetween coincides with a reference phase of the output pulse of the MSMV 60. Referring to Fig. 3 again, the clock signal E4 generated based on the synchronization signal E14 in the PLL circuit unit 18 is fed to the processor 22. The clock signal E4 is used as a basic signal in the data writing, or used as a reference clock pulse for data separation for taking a data pulse from the regenerative signal in the data reading. Also, the processor 22 sets a target position for the servo circuit 32 in the head positioning unit 24 under the seek control from a magnetic disc control unit (not shown). At this time, the servo circuit 32 outputs the drive signal E10 to the voice coil motor 34 such that an error between the demodulated position signal E9 and a signal corresponding to the target position is made zero, and thus effects the position servo control for positioning the head to the target position. Furthermore, the processor 22 supplies the gate circuit 20 characterizing the present invention with the LTSV signal E11 and the *GLTSV signal E12 for making the gate function effective. Next, the operation of the apparatus of Fig. 3 will be explained with reference to the flow charts shown in Figs. 16a and 16b. Note, the illustrated processings are executed when the disc-drive apparatus is powered ON (i.e., at a power-ON start). First, at step S1, the spindle motor 26 is started. At step S2, the control judges whether the rotational speed of the disc driven by the spindle motor 26 reaches the regular speed (YES) or not (NO). If the judgment indicates NO, the control proceeds to step S3 and judges whether a predetermined time has elapsed (YES) or not (NO). If the judgment at step S3 indicates YES, the control proceeds to "ALARM ROUTINE" and, if the judgment indicates NO, the control returns to step S2. If the judgment at step S2 indicates YES, the control proceeds to step S4 and starts the RTZ processing for positioning the servo head 12 on a zero cylinder (e.g., outermost cylinder in the disc mechanism 14). At the next step S5, the control awaits a lapse of a constant time in which the servo head 12 reaches a data region on the servo disc 10, and proceeds to step S6. At step S6, the control (processor 22) makes the LTSV signal E11 "H" level, which is fed to the synchronization signal demodulating circuit 16 and the gate circuit 20. Thus, the synchronization signal demodulating circuit 16 begins to demodulate the synchronization signal E3 based on the servo signal E2. At step S7, the control executes the RTZ processing and, at the next step S8, the control judges whether the servo head 12 has been positioned by the RTZ processing on the zero cylinder, i.e., brought to the on-track state (YES) or not (NO). If the judgment at step S8 indicates NO, the control proceeds to step S9 and judges whether the number of re-try of the RTZ processing reaches a predetermined number "m" (YES) or not (NO). If the judgment at step S9 indicates YES, the control proceeds to "ALARM ROUTINE" and, if the judgment indicates NO, the control returns to step S4. If the judgment at step S8 indicates YES, the control proceeds to step S10, where the processor 22 makes the *GLTSV signal E12 "L" level, which is fed to the gate circuit 20. Thus, the gate circuit 20 shown in Fig. 9 is made effective and thus starts generating the window signal E13 for removal of an erroneously detected synchronization signal. Therefore, even if an erroneous synchronization signal due to a spike noise is contained in the synchronization signal E3 demodulated by the synchronization signal demodulating circuit 16, it can be removed by the window signal E13 produced in the gate circuit 20. As a result, only the precisely detected synchronization signal E14 is fed to the PLL circuit unit 18. After the gate circuit 20 starts its gate operation at step S10, the control proceeds to step S11 and executes various control routines. At the next step S12, the control judges whether any seek error has been detected during the execution of the various control routines (YES) or not (NO). If the judgment at step S12 indicates NO, the control returns to step S11 and, if the judgment indicates YES, the control proceeds to step S13. At step S13, the processor 22 makes the *GLTSV signal E12 "H" level and then returns to step S4. Although, in the above processings in Figs. 16a and 16b, the processor 22 makes effective the window signal E13 in the gate circuit 20 based on the detection of the on-track to the zero cylinder by the RTZ processing, it is not restrictive. For example, a modification may be provided in which the processor 22 detects that the position signal demodulating circuit 30 has demodulated the two kinds of position signals POSN and POSQ shown in Fig. 6 during the RTZ processing, and makes the *GLTSV signal E12 "L" level to thereby make effective the window signal E13 in the gate circuit 20. As to the seek error at step S12, a modified processing may be provided in which, when the position signal demodulating circuit 30 cannot demodulate the position signal E9 and thus the servo circuit 32 requests the processor 22 to effect the RTZ processing, the control returns to step S4 via step S13. Also, another modified processing as to the seek error at step S12 may be provided in which, when a time over error due to a mechanical erroneous operation occurs in the position control by the servo circuit 32 during the seek operation and thus the servo head 12 is returned to the outermost zero cylinder, the control returns to step S4 via step S13. Although, in the above embodiment, the window signal is generated at a timing between the third pulse and the thirteenth pulse among the sixteen clock pulses (E16) generated within one period T defined by the synchronization signal and thus the gate circuit 20 prohibits the supply of the demodulated synchronization signal E3 from the synchronization signal demodulating circuit 16 to the PLL circuit unit 18, it is not restrictive. The window signal can be arbitrarily selected as long as the generation timing thereof lies between the synchronization patterns in the servo signal E2. Although the present invention has been disclosed and described by way of one embodiment, it is apparent to those skilled in the art that other embodiments and modifications of the present invention are possible without departing from the scope of the appended claims.

Claims: A disc data storage system and an apparatus for reproducing a synchronization signal contained therein comprising: a magnetic disc mechanism (3, 4, 14) having a plurality of disc surfaces (1, 10), each disc surface having at least one head (2, 12), the mechanism including a first servo disc (1, 10) on which at least one predetermined servo pattern for controlling the heads (2, 12) of the other discs is recorded, and a servo head (2) for reading the servo pattern from the first servo disc to thereby output a servo signal (E2); a synchronization signal demodulating means (4, 16), responsive to the servo signal (E2) from the disc mechanism, for demodulating the servo pattern to form a synchronization signal (E3) which is in synchronization with the rotation of the first servo disc; and a synchronization clock generating means (5, 18) for generating a clock signal (E4) with a predetermined frequency, to be synchronised with the synchronization signal, the clock signal being usable for controlling further demodulating of the servo pattern; and characterised by a gate means (6, 20), operatively connected between the synchronization signal demodulating means and the synchronization clock gegerating means, for prohibiting a supply of any pulse of the synchronization signal (E3) from the synchronisation signal demodulating means to the synchronization clock generating means for a predetermined period, thereby inhibiting the synchronisation of the clock signal with a pulse of the synchronisation signal that has been generated in error, the predetermined period being defined by the interval between when a first pulse of the synchronization signal is obtained by the synchronization signal demodulating means and when a subsequent non-erroneous pulse of the synchronization signal is obtained thereby. A system system as claimed in claim 1, having a plurality of information storage discs, and a corresponding plurality of reproducing heads, one of the reproducing heads reading the servo pattern from the said first information storage disc to thereby output a servo signal. A system as claimed in any preceding claim, wherein the synchronization clock generating means (5, 18) comprises: a phase-locked loop circuit (56), responsive to the synchronization signal (E14) fed via the gate means from the synchronization signal demodulating means, for effecting a phase control of the clock signal (E4) oscillating at the predetermined frequency, on the basis of the synchronization signal; and a counter circuit (58) for repeatedly counting a predetermined plurality of clock cycles generated by the phase-locked loop circuit and supplying the gate means (20) with a first count output of a predetermined number in a first half of the repeatedly counted values and a second count output of another predetermined number in a second half thereof, to thereby cause the gate means to set the predetermined period. A system as claimed in claim 3, wherein the number of the predetermined plurality of clock cycles is sixteen, and the first count output and the second count output are selected to be a count value of three (CT3) and a count value of thirteen (CT13), respectively. A system as claimed in any preceding claim, further comprising: a head positioning means (8, 24) for generating a position signal (E9) indicating a position of the servo head based on the servo signal (E2) from the disc mechanism and window signals (E5 to E8) from the synchronization clock generating means and, based on the position signal, controlling a drive motor (34) provided in the disc mechanism to cause the servo head to follow a designated target position; and a control means (7, 22), responsive to the clock signal (E4) fed from the synchronization clock generating means, for generating control signals (E11, E12) for making the function of the gate means effective or ineffective, and controlling the head positioning means and the synchronization signal demodulating means. A system as claimed in claim 5, wherein the control means makes the function of the gate means effective when it detects that a rotational speed of the disc has reached a regular speed after a power-ON start and thereafter the head has been positioned by the head positioning means on a zero cylinder. An apparatus as set forth in claim 5, wherein the control means makes the function of the gate means effective when it detects that a rotational speed of the disc has reached a regular speed after a power-ON start and thereafter, while the head is being positioned by the head positioning means on a zero cylinder, the position signal has been demodulated from the servo signal. A system as claimed in claim 5, 6 or 7, wherein the control means makes the function of the gate means effective when the head positioning means cannot demodulate the position signal in the steady operation and thus the control means effects a control for positioning the head on a zero cylinder. A system as claimed in claim 5, 6, 7 or 8, wherein the control means makes the function of the gate means effective when the head movement by the head positioning means is not in time due to erroneous mechanical operation in the steady state and thus the control means effects a control for positioning the head on a zero cylinder. A system as claimed in any preceding claim wherein the predetermined frequency is 18 MHz. A system according to any preceding claim wherein the magnetic disc mechanism (14) includes a drive motor (34) for driving the servo head to follow a designated target position; and further comprising a head positioning circuit (24) for generating a position signal (E9) indicating a position of the servo head based on the servo signal (E2) from the disc mechanism and window signals (E5 to E8) from the synchronization clock generating circuit and, based on the position signal, controlling the drive motor to cause the servo head to follow the designated target position; and a processor (22), responsive to the clock signal fed from the synchronization clock generating circuit, for generating control signals (E11, E12) for making the function of the gate circuit effective or ineffective, and controlling the head positioning circuit and the synchronization signal demodulating circuit. A system according to any preceding claim wherein the synchronization signal demodulating means comprises a first monostable multivibrator (38) an OR gate (40) and a second monostable multivibrator (42), and wherein the second monostable multivibrator (42) is triggered by the first of two pulses of the output of the first monostable multivibrator (38) to produce an output having the duration of one synchronization cycle thereby demodulating the synchronization signal. A system according to claim 12 wherein the synchronization cycle is one cycle of the predetermined servo pattern. A system according to any preceding claim wherein the synchronization cycle comprises two peaks and wherein each position bit, disposed between adjacent synchronization cycles, comprises one peak. A system according to claim 14, wherein the synchronization signal demodulating means demodulates the synchronization signal when the two peaks in the cycle have been detected. A method of reproducing a synchronization signal in a system having a magnetic disc mechanism which includes at least one servo disc and a plurality of data discs, and generates a servo signal based on information from the servo disc, the method comprising the steps of: demodulating a synchronization signal from the servo signal extracted from the disc mechanism; generating a clock signal and setting it to be in synchronization with the demodulated synchronization signal, for controlling further demodulation of the servo signal; characterized by using a gate means located between a demodulating means and a clock signal generating means for prohibiting a supply of any pulse of the synchronization signal from the synchronisation signal demodulating means to the synchronization clock generating means for a predetermined period, thereby inhibiting the synchronisation of the clock signal with a pulse of the synchronisation signal that has been generated in error, the predetermined period being defined by the interval between when a first pulse of the synchronization signal is obtained by the synchronization signal demodulating means and when a subsequent non-erroneous pulse of the synchronization signal is obtained thereby. A method as set forth in claim 16, further comprising a step of generating control information for making the gate means effective after a rotation speed of the servo disc reaches a regular speed at which time a process for positioning the corresponding servo head on a designated cylinder in the disc mechanism is started. A method as set forth in claim 16, wherein the step of demodulating a synchronization signal comprises a step of starting the demodulating operation after a rotational speed of the servo disc reaches a regular speed and thus a processing for positioning the corresponding servo head on a designated cylinder in the disc mechanism is started. A method as set forth in claims 16, 17 or 18, further comprising a step of effecting a phase-locked loop control of the synchronization signal. A method as set forth in claim 19, further comprising a step of repeatedly counting a predetermined plurality of clock cycles generated by the phase-locked loop and, based on a result of the counting, generating part of the control information.

Inventors: HASHIMOTO SHUICHI, SHINOHARA TOHRU, HASHIMOTO, SHUICHI, SHINOHARA, TOHRU
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1991
Main classification: G11B5
IPC codes: G11B5, G11B19, G11B20