Method of controlling a self-test in a data processing system and data processing system suitable for this method

Abstract: A method is described, in which a self-test is controlled in a subsystem of a data processing system. Control patterns are transported by the data processing system via a shift register and are then passed to the subsystem via connections used for normal control in the non-testing condition. A characterization of the test result is then loaded again into the shift register via connections also intended for normal use and is subsequently transported by the data processing system. A subsystem suitable for a self-test according to this method is controllable in the self-test condition from a shift register without it being necessary that it is provided with special test connections.

Description: Method of controlling a self-test in a data processing system and data processing system suitable for this method. The invention relates to a method of controlling a self-test of a subsystem contained in a data processing system to which the subsystem is connected via input connection means for which for a normally operating condition a collection of standard control patterns are defined, which data processing system also comprises serial shift register means with parallel output means. The invention further relates to a data processing system comprising: a subsystem having input connections and at last one output connection, which subsystem in an operating condition responds to elements from a first collection of input patterns at the input connections, which are included as admissible pairs of input patterns directly succeeding each other in a second collection, i.e a collection of pairs, serial shift register means provided with parallel output means for supplying said input patterns to the input condition, a detector fed by information from the shift register means for controlling in response to previously determined information the subsystem into a self-test condition and for then supplying a test characterization at the said at least one output connection for further evaluation. Such a method and a data processing system suitable for this method are known from the I.E.E.E. Test Standard P 1149: "Standard Test Access Port and Boundary-Scan Architecture", (Draft), published by I.E.E.E. Standards Board, Institute of Electrical and Electronics Engineers, Inc.; 345 East 47 th Street, New York, N.Y. 10017, U.S.A., more particularly section 6.9. The use of a shift register, in this case indicated as "scan register", is suggested therein as a standard test method: the "(boundary) scan test". In the most frequently occurring conditions, the test is effected in that via the parallel outputs of the scan register a test pattern is supplied to the circuit to be tested. Subsequently, the response to this test pattern is loaded into the register. Test patterns and response are communicated with the environment whilst being serially shifted. The advantages of this method are: a) a small number of external connections are required to make a system testable (four in the standard P 1149), b) the test method can be uniformly applied to different systems; c) with systems comprising different subsystems, test means can be provided by series arrangement of the registers of the subsystems; d) the means required for the test are so simple that they can be added to a system design with a small risk of errors, as the case may be even automatically with a CAD program. For these reasons, the boundary scan test is a very suitable test method. In certain cases, however, the method of testing by means of test patterns is unsatisfactory, for example when for a good test a large number of different test patterns are required or when the circuit can have many different conditions, such as, for example, memories, so that a specially designed test program is necessary. In this case, the possibility is described of providing built-in self-test means in subsystems (P 1149: BIST = Built-In Self-Test). Such a subsystem carries out a self-test program specially designed for the subsystem after a pattern interpreted as start command has been received from the register. A characterization of the result is then made available via the scan register. Thus, an extensive test can be carried out rapidly, sometimes even in a number of parallel-connected subsystems. However, in certain cases an insufficient number of (or absolutely no) connections are available to subsystems specially intended for the test. For example, the interface may be standardized, for example for IC types with connections defined for the type, in which event no special test connections are possible. This makes it impossible to include such subsystems in the normal manner in the scan circuit. One of the objects of the invention is to reduce the number of connections specially required for controlling tests whilst maintaining the uniform controllability by means of a scan circuit. According to one of its aspects, this object is achieved by the invention in that it is characterized in that a self-test is controlled from the shift register means via the parallel output means and via at least part of the input connection means whilst using a further control pattern at the input connection means lying outside the defined collection. A particular embodiment of the invention is characterized in that via at least part of the output connection means, with synchronization by a predetermined succession of input patterns, the characterization is read out. The synchronizing control makes it possible to read out the characterization, as the case may be, only via one connection. Thus, connections specially intended for test output can be economized or can be rendered superfluous. A particular embodiment of the invention is characterized in that the further control pattern is a predetermined pair of standard control patterns from the collection succeeding each other in time. In this manner, if in itself there is no instantaneous pattern lying outside the collection of "normal" input patterns, a test control can be realized. It should be noted that devices which are brought into a test condition by a succession of signals are known from the published European Patent 0 317 014. The present application relates to the driving of these signals from the shift register. Figure 1 shows a data processing system with test means as described in the test standard P 1149; Figure 2 shows a data processing system with a subsystem which is connected without connections specially intended for test purposes. Figure 1 shows a system having a shift register (10) provided for test purposes, as known from test standard P 1149, and a subsystem (50) to be tested, which is, for example, a memory chip or a memory board. Under the control of a connection (16), the subsystem (50) is either in a normally operating condition or in some test condition. In the normal condition, the switch (54) is positioned so that the normal input signal (52), which may have a width of a number of lines, is received at the input (56) of the subsystem (50). In the test condition, it is possible to change over the switch (54) with control (16), as a result of which the input signal having a width of one or more lines leaves the register (10) via connections (14). The response of the subsystem (50) produced at the output (58) and representing a characterization of the result of the test can then be loaded into the register (10) via an input (18). The kind of test leading to this response is selected by a signal at the control input (16). It may be a test of the input/output relation of a part of combinatorial logic, but it may also be a "built-in self-test" (BIST), in which the subsystem carries out internally a program. Thus, for example, a test is possible in which there is written and read successively in a number of memory locations, after which the response reports locations in which reading and writing results do not correspond to each other. The control (16) and the input patterns (14) can be shifted into the register serially via a test input (12). The response can be read out, again serially, via an output (20). With the test standard P 1149, the part of the register (10) connected to the subsystem (50) is included in the subsystem so that for testing four connections are required: (TDI) (12) for loading the register, TDO (20) for reading out, TCK (22) for clocking the shift mechanism and (24) TMS for controlling the operation. Figure 2 shows a data processing system including a subsystem (150), which is connected without connections specially intended for test purposes to the remainder of the system. The input of a subsystem (150) is connected to a part (180) of the system, which actually has test connections according to the last standard P 1149. The output is connected to a second part (190), which also has test connections according to P 1149. Thus, the outputs (182) of the first part (180) can be controlled by this register, as a result of which the input (156) of the subsystem (150) are driven from the register (10). Likewise, signals at the output (158) of the subsystem (150) can be loaded into this register via an input (192) of the second part (190). The control inputs (116) are controlled by a detector (160), which derives a start command from the input signal (156). This detector (160) responds to a predetermined pair of input patterns directly succeeding each other, which in the normally operating condition of the subsystem (150) must not be used. If the test of the subsystem implies the execution of a program, a clock is required. In case the subsystem does not require a clock in the normal condition, as, for example, in static memories, a clock (170) can be internally provided in the system, which clock is activated by the detector. As an alternative, a clock input could be driven via the normal inputs (156) from the scan register (10), but because in this case the successive pulses must be loaded via the serial input (12), this leads to a lower maximum attainable clock frequency. After termination of the test, the subsystem must supply the characterization of the result. Frequently, this characterization comprises too many bits to be read out in one operation via the output (158) normally available. For example, with given memory IC's, the output has a width of only one bit. In this case, the characterization is supplied serially in a sequence of parts at the output (158), the input (156) being used as synchronization, which is then controlled via the circuit (180). Due to the means described with reference to Figure 2, a subsystem (150) is obtained, which does not require any connection specially intended for test purposes. At the same time, it can actually be tested in a scan test environment so that it also profits from the advantages of the scan test. Viewed from the scan test, it seems as if the subsystem is only a piece of a connection circuit having an input/output relation to be tested, which, however, actually represents a result calculated by a test program.

Claims: A method of controlling a self-test of a subsystem contained in a data processing system to which the subsystem is connected via input connection means for which for a normally operating condition a collection of standard control patterns are defined, which data processing system also comprises serial shift register means with parallel output means, characterized in that the self-test is controlled from the shift register means via the parallel output means and via at least a part of the input connection means whilst using a further control pattern at the input connection means lying outside the defined collection. A method as claimed in Claim 1, in which the subsystem is further connected via output connection means to further parts of the system and in which a characterization of a result of the self-test of the subsystem is read out, characterized in that the characterization is read out via at least a part of the output connection means with synchronisation by a predetermined succession of input patterns. A method as claimed in Claim 1 or 2, characterized in that the further control pattern is a predetermined pair of standard control patterns from the collection succeeding each other in time. A method as claimed in Claim 1 or 2, in which the subsystem is a memory system having a write enable input connection and an address input connection, characterized in that a beginning of the control is effected by causing the drive of the address input connection to vary, whilst at the same time the write enable input connection is continuously activated. A data processing system comprising a subsystem having input connections and at least one output connection, which subsystem in an operating condition responds to elements from a first collection of input patterns at the input connections, which are included as admissible pairs of input patterns directly succeeding each other in a second collection, i.e a collection of pairs, serial shift register means provided with parallel output means for supplying said input patterns to the input connections, a detector fed by the information from the shift register means for controlling in response to predetermined information the subsystem into a self-test condition and for then supplying a test characterization at said at least one output connection for further evaluation, characterized in that the detector is included in the subsystem and is connected to the input connections and thus responds to a predetermined pair of input patterns outside the said second collection, while the pair consists of patterns from the first said collection. A data processing system as claimed in Claim 5, characterized in that the subsystem comprises a clock, and in that, when reaching the self-test condition, the clock is started to synchronize thereby the execution of a test program. A data processing system as claimed in Claim 5 or 6, characterized in that the subsystem in the self-test condition supplies the characterization in a sequence of serially successive parts with synchronization by pairs of predetermined mutually different input patterns at the input connections. A data processing system as claimed in Claim 5, 6 or 7, characterized in that the serial shift register means comprise input means for receiving the test characterization. A data processing system as claimed in any one of Claims 5 to 8, characterized in that the subsystem is a memory system having a write enable input connection and an address input connection, and in that the said pair of input patterns to which the detector responds is a permanent activation of the write enable with a variation of the address. A data processing system as claimed in Claim 9, characterized in that the subsystem is a support with memory IC's disposed thereon, the shift register means being arranged externally of the support. A data processing system as claimed in any one of Claims 5 to 10, in which the data processing system is provided on a support with integrated circuits and the subsystem is contained in an IC housing. A subsystem as claimed in any one of Claims 5 to 10, characterized in that the subsystem is contained in a housing not comprising a connection exclusively intended for test purposes.

Inventors: DEKKER ROBERTUS WILHELMUS CORN, DEKKER, ROBERTUS WILHELMUS CORNELIS
Applicants: PHILIPS ELECTRONICS NV, PHILIPS ELECTRONICS N.V.
Application year: 1991
Main classification: G06F11
IPC codes: H04L29, G01R31