Encoding system comprising a subband coder, and a transmitter comprising an encoding system

Abstract: The encoding system comprises a subband coder (2) for subband coding a wideband digital signal and includes quantizing means (Q₁, ..., Q M , 6, 7) for quantizing block-by-block the subband signals (SB₁, ..., SB M ). The quantizing means comprise a bit need determining means (6) and a bit allocation means (7). The bit need determining means (6) are arranged for determining a bit need b m which bears a relation to the number of bits by which samples in a signal block in a subband SB m should be represented. The bit allocation means (7) is arranged for allocating a number of bits n m to the subband SB m on the basis of the bit needs b m and the available bit quantity B, where n m indicates the number of bits by which the samples in the subband SB m are represented. A new method is provided through which in the bit allocation means the bits are allocated to the subbands.

Description: The invention relates to an encoding system, comprising a subband coder for subband coding of a wideband digital signal, for example, a digital audio signal, at a specific sampling frequency F s , the subband coder including signal splitting means for generating, in response to the wideband digital signal, a plurality of P subband signals with sampling frequency reduction, for which purpose the splitting means split up the wideband digital signal into successive subbands which augment with frequency, which encoding system further comprises quantizing means for quantizing block-by-block the respective subband signals, a quantized subband signal m being composed of successive signal blocks, each signal block comprising q samples, the q samples in a signal block of the subband signal m being represented each by n m bits, the quantizing means including bit need determining means for determining a bit need b m per signal block for corresponding signal blocks in the subband signals, which bit need is related to the number of bits by which samples in a signal block in the subband signal m should be represented, and the quantizing means including a bit allocation means for allocating an available quantity of bits B to the corresponding signal blocks of the various subband signals in response to the bit need determined by the bit need determining means so as to obtain the values n m , where m ranges from 1 to P, and which encoding system further comprises accommodating means for accommodating the samples quantized with a certain number of bits in a signal block in a frame of a second digital signal having successive frames, the accommodating means further being arranged for accommodating the scale factor information in a frame, which scale factor information comprises x-bit words, an x-bit word representing a scale factor associated to the samples in a signal block, and the invention further relates to a transmitter comprising the encoding system. BACKGROUND OF THE INVENTION The encoding system of the type mentioned in the preamble is known from European Patent Application No. 289.080, prior-art document (1) in the list of documents stated at the end of the descriptions of the drawing Figures. Subband encoding of a single signal, such as a mono audio signal or a left or right signal portion of a stereo signal, may be concerned here. In that case P equals M. In each subband the splitting means then generate one subband signal. However, this may also relate to a stereo signal which is to be subband encoded. In that ease it holds that P equals 2M. The subband splitting means then generate two subband signals in each subband, i.e. a left and a right subband signal. SUMMARY OF THE INVENTION The invention specifically relates to the bit allocation means allocating the bits to the various signal blocks on the basis of the bit needs b₁ to b P for corresponding signal blocks in the subbands SB₁ to SB M and on the basis of a certain initial number of bits B to be allocated. The number of bits used in each subband for quantizing the samples in the signal blocks is to be variable with time in order to realise a highest possible perceptual quality. The invention provides a method of allocating the available bits to the quantizers according to a specific criterion. For this purpose, the encoding system according to the invention is characterized in that on the basis of the bit needs, for corresponding signal blocks in the subband signals in the subbands determined in the bit need determining means, the bit allocation means is arranged for the following operations in a specific step S₁: (a) determining b j , which is the largest of the bit needs, (b) establishing whether bits have previously been allocated to the signal block belonging to the bit need b j , and if they have not, then (c) allocating a value a₁ to n j ; subtracting a value a₂ from b j ; subtracting the value a₁.q+x from B, and if they have, then (d) adding the value c₁ to n j ; subtracting the value c₂ from b j ; subtracting the value c₁.q from B, and for performing the step S₁ at least a second time, in that q and x are integers greater than unity, in that n m and b m are variables where n m is greater than or equal to zero, a₁, a₂, c₁ and c₂ are numbers greater than zero and B is an integer greater than zero, m is a variable integer, a₁ is greater than c₁ and a₂ is greater than or equal to c₂. From prior-art document (4) a method is known which is very similar to the method proposed in this application, compare especially, chapter 4.2 "Adaptive bit allocation" in this document. However, after the maximum bit need b j is determined, the value n j is raised by unity in all cases. Contrary to this known method, a distinction is made according to the invention for the situation in which bits are allocated for the first time to a signal block j (n j =0). In that case n j is assumed to be equal to a₁, whereas if bits have already been allocated to the signal block j at an earlier instant (n j >0), n j is raised by c₁, where a₁>c₁. For example, a₁ is equal to 2 and c₁, for example, is equal to 1. In a first bit allocation to a signal block, more bits are allocated to each sample than with a second or subsequent bit allocation. Research has shown that a bit allocation as proposed by the present invention leads to a better encoding of the digital signal, so that the reconstructed digital signal has a better quality after decoding. The encoding system may further be characterized in that the bit allocation means is arranged for carrying out the following operations in a step S₀ prior to the steps S₁, for a signal block k in a subband: allocating a value A k0 to n k ; subtracting the value A k1 from b k ; subtracting the value A k0 .q+x from B, and in that A k0 and A k1 are numbers greater than zero. In this step, preceding the steps S₁, bits are allocated to signal blocks in subbands which are not to be quantized by zero bits whatever their bit need. The reason for this is that sometimes subbands cannot readily be switched off. This could then produce audible effects. The encoding system may further be characterized in that the bit allocation means is arranged for allocating a flag value in the step S₀ to a signal block in one or more subbands, which flag value indicates that no bits are to be allocated to the signal block concerned. In this respect it thus holds that some subbands must not be switched on also because this could produce audible effects. BRIEF DESCRIPTION OF THE DRAWINGS The invention will be further explained in the following descriptions with reference to a number of exemplary embodiments, in which: Fig. 1 shows an encoding system according to the invention; Fig. 1a shows the corresponding signal blocks in the subband signals SB₁ to SB M , each signal block comprising q samples; Fig. 2 shows the quantization to a three-bit binary representation; Fig. 3 shows the positions of the bit needs b₁, b₂, ..., along the value axis; Fig. 4 shows the method of determining the bit needs b₁, ..., b P ; Fig. 5 shows the method of allocating bits to the signal blocks in the subbands; Fig. 6 shows the initial bit allocation; Fig. 7 shows the correction Table to be used for number additions utilizing a logarithmic representation of the numbers; Fig. 8 shows a hardware design of the bit need determining means; Fig. 9 shows a hardware design of the bit allocation means; Fig. 10 shows the use in a transmitter in the form of a recording arrangement for recording quantized subband signals on a magnetic record carrier; Figs. 11, 12 and 13 show the different allocation stages in dependence on the power value v i , and Fig. 14 shows a diagram of the unit for generating the control signals featuring the different allocation stages. DESCRIPTION OF (PREFERRED) EMBODIMENTS The description of the drawings will in essence relate to the description of the subband encoding of a single digital signal. That is to say, the subband encoding of a mono audio signal, or the subband encoding of only the right or rather the left signal portion of a stereo audio signal. As already observed above, this implies that P equals M and that in each subband signal there is only one subband signal present. At the end of this description it will be explained how the bit need may be determined in case of subband encoding of a stereo signal, it being understood that P equals 2M. There are two subband signals in each subband. Fig. 1 shows the encoding system according to the invention. A wideband digital signal is applied to input terminal 1. An audio signal having a bandwidth of approximately 20 kHz may be considered in this respect. Input 1 receives, for example, 16-bit samples of the audio signal at a sampling frequency of 44 kHz. The audio signal is applied to a subband coder 2 which comprises signal splitting means. The subband coder 2 distributes the audio signal over M subbands by means of M filters, that is to say, a low-pass filter LP, M-2 band-pass filters BP and a high-pass filter HP. M is, for example, equal to 32. The sampling frequency of the M subband signals is reduced in the blocks referenced 9. In these blocks the sampling frequency is reduced by a factor M. The signals thus obtained are available at the outputs 3.1, 3.2, ..., 3.M. At the output 3.1 the signal is available in the lowest subband SB₁. At the output 3.2 the signal is available in the lowest but one subband SB₂. At the output 3.M the signal is available in the highest subband SB M . The signals at the outputs 3.1 to 3.M have the structure of successive samples expressed in numbers of 16 bits or over, for example 24. In the exemplary embodiment of the invention under discussion the subbands SB₁ to SB M all have the same width. This is not a necessity, however. In the prior-art publication (5), by Krasner, a subdivision into a plurality of subbands is provided whose bandwidths approximately correspond to the bandwidths of the critical bands of the human auditory system in the respective frequency areas. The operation of the subband coder 2 will not further be explained since the operation of a subband coder has already been described extensively hereinbefore. For this purpose, reference is made to the prior-art documents (1), (5) and (7) which are assumed to be incorporated in this application where necessary. The subband signals are combined to successive signal blocks of q successive samples, cf. Fig. 1a, and are applied to corresponding quantizers Q₁ to Q M . In a quantizer Q m the samples are quantized to quantized samples having a number of bits n m smaller than 16. Fig. 2 shows a quantization with a 3-bit binary representation. During the process of quantization the signal blocks (groups) of q successive samples of the subband signals are each time quantized with a number of bits (3) in the example of Fig. 2. For example, q is equal to 12. In addition, the q samples in a signal block are normalized first. This normalization is performed by dividing the amplitudes of the q samples by the amplitude of the sample having the largest absolute value in the signal block. The amplitude of the sample having the largest amplitude in the signal block of subband SB m yields the scale factor SF m , cf. documents (2a), (2b). Subsequently, the amplitudes of the normalized samples, which are now situated in an amplitude range from -1 to +1, are quantized according to Fig. 2. This implies that samples in the amplitude range between -1 and -0.71 are quantized with the 3-bit number 000, samples in the amplitude range from -0.71 to 0.42 are quantized with 001, samples in the amplitude range from 0.42 to 0.14 are quantized with 010, samples in the amplitude range from -0.14 to 0.14 are quantized with 001, samples in the amplitude range from 0.14 to 0.42 are quantized with 100, samples in the amplitude range from 0.42 to 0.71 are quantized with 101 and samples in the amplitude range from 0.71 to 1.00 are quantized with 110. In the prior-art document (2b) this three-bit quantization is extensively discussed, cf. Figs. 24, 25 and 26 and the relevant descriptions in that document. The quantized samples in the subbands SB₁ to SB M are thereafter available at the respective outputs 4.1 to 4.M. Furthermore, the outputs 3.1 to 3.M are coupled to the respective inputs 5.1 to 5.M of bit need determining means 6. The bit need determining means 6 determine the bit need b m for the time equivalent signal blocks of q samples in the subbands SB₁ to SB M . The bit need b m is a number related to the number of bits with which the q samples in a q-sample signal block in a subband signal should be quantized. The bit needs b₁ to b M , derived by the bit need determining means 6, are applied to bit allocation means 7. The bit allocation means 7 determines the actual number of bits n₁ to n M with which the q samples of the corresponding signal blocks in the subband signals SB₁ to SB M are quantized. Control signals corresponding to the numbers n₁ to n M are applied to the respective quantizers Q₁ to Q M through lines 8.1 to 8.M, so that the quantizers can quantize the samples with the correct number of bits. The following will provide an explanation of the operation of the bit need determining means 6 and the bit allocation means 7. The bit needs for the time-equivalent signal blocks of q samples in the subband signals SB₁ to SB M are derived from estimates for the power v m and the scale factor SF m in a signal block in a subband signal SB m . The power v m may, for example, be obtained by means of the following formula: where s i is the amplitude of the i th sample in the q-sample signal block in the subband SB m . The scale factor SF m was equal to the amplitude of the sample in the signal block having the largest absolute value, as has already been observed hereinbefore. It should be observed in this context that the estimate for the power v m in a signal block in the subband SB m also might have been obtained by assuming that v m was equal to the squared scale factor SF m . For all corresponding signal blocks in the subband signals SB₁ to SB M the power v m and the scale factor SF m are determined in this fashion. The powers are ordered in a vector {v}. By multiplying the vector {v} by an M x M matrix [D], one will obtain a vector {w} utilizing the following formula: {w} = [D] {v} + {w r } In this formula [D] is a matrix whose coefficients d ij denote the coefficient by which the power v j of the q-sample signal block in the subband signal SB j is to be multiplied to calculate the masked power in the subband SB i due to the signal in the q-sample signal block in the subband signal SB j and w r.i is the coefficient in the vector {w r } which denotes the masking threshold in the subband SB i . Thus, w r.m bears a relation to the maximum signal power of the signal in a subband SB m which signal is not audible. The vector {w} now has the coefficients w i which are estimates for the masked quantizing noise in each subband SB i . Quantizing-noise in subband SB i which has a power of less than w i , is thus inaudible. The coefficients d ij of the matrix [D] are to be calculated according to the literature, cf. prior-art document (4). The bit need b₁ to b M can be calculated with the aid of the following formula: b m = K₁·²log ( SF² m /3w m + 1) or more generally: b m = K ₁.²log( K ₂ SF 2 m /w m + K ₃) The former formula can simply be derived from the latter formula by assuming: K₂ = 1/√3 and K₃ = 1. K₁, K₂ and K₃ are constants, for which it holds that K₁ is preferably equal to approximately 1 and K₂ is preferably equal to approximately 1√3. K₃ has a wider range of possibilities. It may be assumed that K₃ will be less than 10, where K₃ will, for example, preferably be taken to be equal to 1 or may be neglected. In addition, in the latter case there will be a simpler implementation of the calculation. The coefficients (bit needs) b₁ to b M obtained in this fashion, are situated in a specific amplitude range. The coefficients may be negative and non-integers. A coefficient b m bears a relation to the number of bits with which the samples in the q-sample signal block of a subband signal SB m should be quantized, so that it holds that if b m1 for subband signal SB m1 is greater than b m2 for the subband signal SB m2 , the number of bits with which the q samples in a signal block in the subband signal SB m1 should be quantized will have to be greater than the number of bits with which the q samples of a time-equivalent signal block in the subband signal SB m2 should be quantized. This is shown in qualitative terms with reference to Fig. 3. In Fig. 3 seven bit needs b₁ to b₅, b max and b min are plotted along the value axis. b max is the bit need having the maximum value and b min is the bit need having the minimum value. It will be noticed that b min , b₂ and b₅ are negative and that, furthermore, the following holds: b min <b₅<b₂<b₄<b₁<b₃<b max . In terms of quality it may now be assumed that the subband signal SB m , with b m =B min , should/could be quantized with the minimum number of bits and the subband signal SB m , with b m =b max , with the maximum number of bits. Fig. 4 shows a flow chart of the operation of the bit need determining means 6. Fig. 4 shows the program for determining the bit needs b₁ to b M for time-equivalent q-sample signal blocks in the subband signals SB₁ to SB M . In this case only a single q-sample signal block in a subband signal is concerned. For a successive q-sample signal block in the subband signal, and the signal blocks of the other subband signals corresponding with the signal block (in case of a time-parallel subband signal supply), the operation represented in Fig. 4 will be performed once again. The operation starts at block 10. First, the running variable m is set to 1 (block 12). Then, the q samples S₁, ..., S q of a signal block in a subband signal SB m are inputted (block 14) and the power V m is calculated (block 16). Also the scale factor SF m (block 18) is determined. The blocks 14, 16 and 18 are repeated for all subband signals via the loop through blocks 20 and 22. If the values V m and SF m have been determined for all corresponding signal blocks, the matrix calculation will be performed in order to obtain the vector {w} (block 24). Subsequently, m is again set to 1 (block 26) and the bit need (b m ) is determined (block 28) for all subbands via the loop through the blocks 30 and 32 after which the operation is terminated (block 34). The bit needs b m are determined in block 28 according to the formula given hereinbefore, while the constants K₁, K₂ and K₃ have become equal to 1, 1√3 and 0 respectively. The method of Fig. 4 shows the time-consecutive calculations of the coefficients v m in the vector {v}, compare the loop through block 22 in the program, and the method shows the time-consecutive calculations of the bit needs b₁ to b M , compare the loop through block 32. This is a very suitable method, more specifically, if the corresponding signal blocks having the samples S₁ to S q for the successive subbands SB₁, SB₂, ..., SB M-1 , SB M , are applied serially. If the signal blocks are applied in parallel, the calculation of the coefficients v m could be performed in parallel for all subbands and thus the loop through block 22 is avoided. Likewise, the bit needs b₁ to b M may be calculated in parallel and this will render the loop through block 32 redundant. The operation of the bit allocation means 7 will now be explained. The flow chart of Fig. 5 will be used for this purpose. The program determines for time-equivalent q-sample signal blocks in the subband signals SB₁ to SB M the values n₁ to n M from the bit needs b₁ to B M . Here too it is a matter of a single signal block having q samples in a subband signal. For a directly successive q-sample signal block in the subband signal and the time-equivalent signal blocks in the other subband signals, the method of Fig. 5 will be carried out again. It is now assumed that, after quantization, B₀ bits are available for transmitting the overall information connected with the M signal blocks of q samples of, for example, 24 bits each. Assuming that after quantization, R bits are available per sample, averaged over the subbands, it holds that B₀ is equal to the largest integer smaller than M.q.R. In the prior-art documents (2a) and (2b) it is shown that not only the quantized samples are transmitted, but also the scale factors SF₁ to SF M (scale factor information) and the bit allocation information (that is to say, information which bears a relation to the number of bits with which the samples in a signal block in a subband signal are quantized i.e. the values n₁ to n M ). The bit allocation information is then represented by y=4 bits for each n m . Thus, this implies that, actually, only B=B₀-y.M bits are available for the transmission of M signal blocks of quantized subband signals and the scale factor information. The documents (2a) and (2b) further describe that the y-bit number (y=4) 0000 in the bit allocation information denotes that no samples are transmitted in the relevant subband. In that case no scale factor information for this subband will be transmitted either. The scale factor information for a subband is represented by means of an x-bit number (x=6). The method of bit allocation is now as follows. The method starts at block 40, Fig. 5. Subsequently, all numbers n m are first set to zero. Then an initial bit allocation is performed at block 44. This initial bit allocation will be explained in the following with reference to Fig. 5. Thereafter, the maximum bit need is determined. This is the bit need b j . In the example of Fig. 3 this would be b max . Then it is considered whether n j is greater than or equal to a certain value n max (block 48). In the present example n max is equal to 16. This means that the quantized samples can only be represented by binary numbers with a maximum of 16 bits. If n j is greater than or equal to n max , the q-sample signal block in the subband j will be excluded from the allocation of further bits. For this purpose, the bit need b j is made equal to a so-called "flag value" (block 66). The flag value is represented in Fig. 3 and is a value smaller than the minimum bit need b min . If c₁ in the block 56 to be discussed hereinbelow is greater than unity, n j might be greater than n max . In addition, n j will then be assumed to be equal to n max at block 66. If n j is equal to zero (block 50), the program will proceed through the blocks 52 and 54. At block 54, a₁ bits are initially allocated to the subband SB j . This means n j = a₁. The total number B of available bits now decreases by a₁.q+x. The q quantized samples of the signal block in the subband signal SB j are represented each by a₁ bits and, in addition, an x-bit-long scale factor SF j is to be added. Furthermore, in block 54 the bit need b j is decreased by a value a₂. If n j is unequal to zero, the program will proceed through block 56. The number of bits n j is now increased by c₁. The total number B of available bits now decreases by c₁.q, due to the fact that the q quantized samples of a signal block are now represented by an additional number of c₁ bits. Naturally, bit allocation only takes place if there are still sufficient bits available. Therefore, block 52 is present. Because, if there are insufficient bits available the program will proceed through block 66 at which the relevant bit need b j is again made equal to the flag value. The signal block in the subband concerned is then excluded from further bit allocation. As long as there are bit needs that have values greater than the flag value (block 58) and as long as there are still sufficient bits available (block 60), the program will return through circuit 62 to block 46 for a next calculation of the maximum bit need. If all bit needs b m are smaller than or equal to the flag value, the program will stop. The program will also stop if there are insufficient bits to be allocated (block 60). The method is characterised in that when a first bit allocation is performed (block 54), the number of allocated bits (a₁) is greater than the number of bits of one or more subsequent allocations (block 56) (c₁), worded differently a₁>c₁. Furthermore, it holds that a₂ is greater than or equal to unity. Preferably, a₁ is equal to a₂ and c₁ equal to c₂. a₁, a₂, c₁ and c₂ are numbers greater than zero. a₁ and c₁ are preferably integers. But, this is not a necessity. An example may be shown for this purpose. It is assumed that one wishes to quantize the q samples in a signal block in five levels. For this purpose, 3 bits are needed per sample. However, this is not an efficient encoding because a subdivision into seven levels of 3 bits is possible. If, however, three samples are combined, these three samples with five signal level will present 125 options. These 125 options may be represented by means of a 7-bit binary number. Thus, no more than 7/3 bits per sample. n m would in that case be equal to 7/3. This will provide a more efficient encoding. It has been indicated hereinbefore that when the quantized samples are transmitted, both scale factor information and bit allocation information are co-transmitted. The scale factor information then has the form of x-bit words, of which each x-bit word denotes a scale factor SF m that belongs to the q samples in a signal block in the subband SB m . The bit allocation information then has the form of y-bit words, of which each y-bit word denotes a number of bits n m by which each sample in a signal block in the subband SB m is represented. Previously, the prior-art documents (2a) and (2b) have already been referred to. If in the bit need determining means 6 only the scale factors SF m are used for calculating the powers v m , that is to say, because v m is assumed to be equal to the square of SF m , the bit allocation information need not be co-transmitted. On the receiver side the bit needs b₁ to b M can be derived from the transmitted scale factors SF m and on the basis of these needs the magnitudes n₁ to n M , while implementing the calculation method as discussed hereinbefore. Thus, the receiver likewise comprises bit need determining means which derive the powers v m from the scale factors SF m and derive from these powers the bit needs b m , and also includes bit allocation means which is capable of calculating the magnitudes n₁ to n M on the basis of the bit needs b m and the available bit quantity which in this case is equal to B₀. Since, as observed hereinbefore, B=B₀-y.M, the latter method is advantageous in that more bits can be allocated to the subbands. It may sometimes be necessary to pre-allocate a number of bits to a signal block in a subband SB m , for example, in the case where there are signal blocks which must not be quantized with zero bits irrespective of their bit need. The reason for this is that signal blocks must not be switched on or off in an unqualified manner. This would produce audible effects. The above also shows that it may sometimes be necessary or useful to exclude a signal block in advance from bit allocation. For this purpose, block 44 in the program of Fig. 5 is inserted. Fig. 6 shows an elaboration of block 44. Two signal blocks are represented there, that is to say, the signal blocks in the subbands SB k and SB₁ to which have been pre-allocated a number of bits A k0 or A₁₀. This implies that n k = A k0 and n₁ = A₁₀. From the bit needs b k and b₁ the respective values A k1 and A₁₁, are subtracted and the remaining number of bits B is reduced by A k0 .q-x and A₁₀.q-x respectively. Actually, for A k0 and A₁₀ the same holds as for a₁. Preferably, A k0 = A₁₀ = a₁. For A k1 and A₁₁ the same holds as for a₂. Preferably, A k1 = A₁₁ = a₂. To the signal blocks in the subbands SB k and SB₁ may naturally be allocated more bits, as required, at block 56 of the method presented in Fig. 5. Furthermore, at block 44 of Fig. 6 it is shown that the signal block in the subband SB f is excluded from bit allocation. For this purpose, the bit need b f for this signal block is made equal to the flag value. Figs. 11, 12 and 13 represent the situations in which there is initial bit allocation or no initial bit allocation to the subbands. The Figures show the consecutive time intervals ΔT in which a group of M corresponding signal blocks of the M subbands are processed. In each time interval the power v i (t) and the magnitude w i (t) are determined for each subband SB i . If V i (t) is greater than w i (t), there will be initial bit allocation to the subband SB i . As will be evident from Fig. 11, this holds for periods of time situated before t=t₁. Fig. 14 shows a circuit by means of which, on the basis of the magnitudes v i and w i , control signals may be derived which denote whether initial bit allocation is to take place, in which case the output of the SR flip-flop 140 is "high" or "logic 1", or whether no bit allocation is to take place, in which case the output of the SR flip-flop 141 is "high", or whether no initial bit allocation takes place, in which case the output of a counter 142 is "high". In the latter case bits may still be allocated to the subband in question, but the allocation then takes place at block 54 and may also take place at block 56 according to the method of Fig. 5. These control signals may thus be applied to block 44 in Fig. 6 and denote what functions are to be performed in this block. At the instant t=t₁, V i (t) becomes smaller than w i (t) The output 144 of the comparator 143 now becomes "low" whereas the output 145 of this comparator becomes "high". Through the OR-gate 147 this "high" signal is applied to the AND-gate 148 so that clock pulses are passed to the AND-gate 149 at a rate f equal to 1/ΔT. Since a "high" signal is applied to the other input of the AND-gate 149 through the inverter 150, the clock pulses are passed to the input 151. The counter 142 now counts down from the initial position 5 (decimal) under the influence of the clock pulses, cf. Fig. 11. Since the output of the counter 142 remains "low", the position of the flip-flop 140 does not change so that the initial bit allocation is maintained. One time interval later, v i (t) is again larger than w i (t). The output 144 of the comparator 143 becomes "high" again which implies that the rising edge is fed to the set input of the counter 142 through the OR-gate 152. The count of counter 142 is reset to 5 (decimal). At the instant t₂, cf. Fig. 11, v i (t) again becomes smaller than w i (t). Now, v i (t) remains smaller than w i (t) for a sufficiently long period of time to make it possible for the counter 142 to count back until the 0 count (decimal) is reached. This is reached at the instant t=t₃, cf. Fig. 11. At that moment the output of the counter 142 becomes "high". The flip-flop 140 is reset. Through inverter 150 and AND-gate 149 the counting operation of counter 142 is blocked so that it retains the 0 count. Initial bits are no longer allocated to this subband. At the instant t=t₄, V i (t) again becomes larger than w i (t) The counter 142 is reset to the count 5 and, in addition, the flip-flop 140 is set in a manner so that initial bits are again allocated. Fig. 12a represents a situation in which v i (t), prior to the instant at which the counter 142 is reset to zero, already becomes smaller than a specific threshold value v thr . At the instant t=t₅ the output 145 of the comparator 143 becomes "low" again and the output 146 "high". Since the inverter 153 applies a "high" signal to one input of the AND-gate 154, the "high" signal is conveyed to the AND-gate 148 through the AND-gate 154 and the OR-gate 147. The counter 142 continues to count. The phase of initial bit allocation is thus maintained until the count 0 (decimal) is reached. The output of the counter 142 now briefly rises. This entails that flip-flop 141 is set through the AND-gate 155. Through the AND-gate 156 and the OR-gate 152 the high output signal of the flip-flop 141 is applied to the set input of the counter 142, which immediately afterwards jumps to count 5 (decimal). In addition, the further down-counting of the counter 142 is blocked because the inverter 153 applies a "low" signal to the one input of the AND-gate 154. From instant t₆ onwards there is no bit allocation whatsoever to the relevant subband. Fig. 12b represents the situation in which v i (t) has remained in the range between v thr and w i (t) sufficiently long so that the phase of "no initial bit allocation" has commenced. At the instant t₇, v i will be smaller than V thr . At that moment the output 145 will become "low" and the output 146 "high". At that moment the flip-flop 141 is set through the AND-gate 155 and the counter 142 is reset to the count 5 through the AND-gate 156 and the OR-gate 152. The output of the counter 142 thus becomes "low" and the output of the flip-flop 141 "high". There is no bit allocation. Fig. 13 shows a situation in which v i (t) increases again. At the instant t₈, v i (t) becomes larger than V thr . The output 145 becomes "high" so that the counter 142 may count down. One time interval later v i (t) is again smaller than v thr . The output 146 becomes "high" again so that the counter is reset to the count of 5 through the AND-gate 156 and the OR-gate 152. If v i (t) is greater than v thr for a sufficientiy long period of time, the counter 142 can count down to zero. At t=t₈, the output of counter 142 becomes "high". Through the AND-gate 159, to which a "high" signal is applied through the inverter 158, the flip-flop 141 is reset, so that at this moment the phase of "no bit allocation" is terminated and changed into the phase of "no initial bit allocation". In the following a simplified calculation of the bit need b m will be explained. In this calculation a logarithmic representation is used for the various magnitudes which play a part in the calculation. This is possible because not absolute but relative precision of the bit needs is concerned with respect to the calculation of the bit needs b₁ to b M . In logarithmic representation a number g is approximated by g=r k , where r is a fixed base greater than unity and the power k is selected to be an integer. The number g is approximated in the best possible way by a right choice of k. The integer k is used as a representation of g. In the calculation for the bit need b m there are both multiplications of two numbers and additions of two numbers. Multiplications in the logarithmic representation correspond with the addition of the powers. That is to say, if g₁=r k 1 and g₂=r k 2, the logarithmic representation of g₁.g₂ will be equal to k₁+k₂. For the logarithmic representation of additions of these two numbers g₁ and g₂, the following holds. Assuming that g₁>g₂, it holds that g₁+g₂ = r k 1 + T(k₁-k₂). The logarithmic representation for g₁+g₂ is thus equal to k₁ + T(k₁-k₂). T(k₁-k₂) is a correction factor in the form of an integer which may be derived from a Table. Fig. 7 shows a Table of this type for r=2 1/16 . The value for r equalling 2 1/16 can be obtained from an accuracy analysis of the bit needs b m . It may further be inferred that the calculation of the needs b m in a logarithmic representation with a properly selected base r, in lieu of the customary calculations in a linear fixed-point representation, considerably reduces the word widths of the numbers. In addition, no multiplier-accumulator is necessary for calculating the vector {w}, but only a simple accumulator and a Table having a restricted number of entries. The Table of Fig. 7, for example, narrows down to a ROM having contents smaller than 0.5 kbit. The series of numbers stored in the ROM is relatively small. In addition, these numbers are arranged in a specific order. Therefore, it is possible to reduce the look-up Table even more at the cost of some logic. It should be observed in this context that the logarithmic representation for the addition of two numbers as described hereinbefore is known per se by the name of Zech logarithm and described in document (6), compare, more specifically, chapter 3, section 4, page 191. The bit need determining means 6 and the bit allocation means 7 may be arranged in software. However, hardware designs are also possible. For example, Fig. 8 shows a hardware design of the bit need determining means 6. Fig. 8 shows the corresponding signal blocks in the subband signals SB₁ to SB M , which are serially applied to input 70. The first sample S₁ of the subband SB₁ is applied first and the last sample S q of the subband SB M is applied last. In the largest sample determining means 71 the largest sample SF m is determined for each signal block, which value is then stored in a memory 72. In a squaring unit 73 the samples are squared and thereafter applied to an input of an adder 74. The output of the adder 74 is coupled to an input of a memory 75. The output of that memory 75 is coupled both to a second input of the adder 74 and an input of a divider 76. The elements referenced 74, 75 and 76 determine the magnitude v m for each signal block, compare block 16 in Fig. 4. To this end, the first sample s₁ of a signal block 3 is squared into the subband signal SB m in the squaring unit 73 and, in adder 74, added to the value stored in memory 75, which value is momentarily zero, and thereafter stored in the memory 75. Subsequently, the second sample s₂ is squared, added to the value stored in memory 75 and then stored in that memory. This is continued until the last sample s q is squared and added to the value stored in memory 75. The sum thus obtained in the memory 75 is equal to which then, after a division by q in the divider 76, is stored as a coefficient v m in memory 77. Similar calculations are made for the corresponding signal blocks of the further subbands until all coefficients of the vector {v} have been stored in the memory 77. The bit need determining means 6 further include a memory 78 for storing the matrix coefficient d m1 of the matrix [D] and a memory 79 for storing the coefficients w r.m of the vector {w r }. Outputs of the memories 77 and 78 are coupled to inputs of the multiplier 80. An output of the multiplier 80 is coupled to a first input of an adder 81 whose one output is coupled to the input of a memory 82. The output of the memory 82 is coupled both to a second input of the adder 81 and to a first input of an adder 83. The elements referenced 80, 81 and 82 are intended to perform the matrix multiplication [D]{v}. During this operation the value d m1 from memory 78 is multiplied by the value v₁ from memory 77 for a specific subband m and the result is added by adder 81 to the value present in memory 82 at that moment, which is zero, and then stored in memory 82. After this, d m2 is multiplied by v₂ and the result is added to the value stored in memory 82. This is continued until d mM is multiplied by v M and the result is added to the value stored in memory 82. At that moment the value is stored in memory 82. In adder 83, the value w r.m stored in memory 79 is added to this result. The value w m thus obtained is stored in memory 84. This procedure is reiterated for the corresponding signal blocks in the further subbands until all coefficients of the vector {w} are stored in memory 84. Subsequently, for each subband SB m , the magnitudes SF m and w M are read from the memories 72 and 84 and applied to the calculation unit which eventually determines the bit need b m . This bit need is stored in a memory 86. This calculation is also performed for the further subbands until all bit needs b₁ to b M are stored in the memory 86. The procedure may be reiterated for a successive series of M signal blocks. Also the arrangement shown in Fig. 8 utilises the fact that there is serial information supply. If the signal blocks were supplied in parallel, the calculation could largely be performed in parallel. This means, for example, that the circuit comprising the elements 71,73,74,75 and 76 could occur M times in the arrangement. The circuit comprising elements 80, 81, 82 and 83 could then likewise occur M times. Fig. 9 shows a hardware embodiment of the bit allocation means 7. The bit allocation means comprises a memory 90 in which the number of bits B still to be allocated have been stored, a memory 91 in which the values n₁ to n M are stored and a memory 92 in which the bit needs b₁ to b M have been stored. This memory 92 could correspond with memory 86 of Fig. 8. At the beginning of an allocation cycle the initial value for B is stored in memory 90, which value is available at terminal 94. Furthermore, the initial values for the bit needs b m have been stored in memory 92 whereas memory 91 stores all zeros fed to terminal 93 by means of reset signals. Subsequently, detector 95 determines the maximum value of the bit needs stored in memory 92. This may, for example, be realised by successively reading out all bit needs b₁ to b M at the output 96 and applying these bit needs through line 97 to the input 98 of the detector 95. At the output 99, the detector 95 provides the index of the maximum bit need b j . This index j is used as an address for addressing through line 100 the locations in the memories 91 and 92 in which the values are stored for n j , b j respectively, so that these values are available at the respective outputs 101 and 96. Output 101 is coupled to an input of an n j =0 detector 102. If the detector 102 detects n j =0, it provides at output 103 a control signal which is applied to control signal inputs of controllable switches S₁, S₂ and S₃. These switches then assume different positions from the ones shown in the drawing Figure. This implies that in a subtractor 105 the value a₁.q+k is subtracted from the value B available at output 106 of memory 90, and this new value is again applied to input 107 of this memory through line 104 so that the new value is stored in memory 90. Furthermore, through lines 108 and 109 the value a₁ which is available at terminal 110, is applied to the input 111 of memory 91. Switch S₄ then has the position shown in the drawing Figure. This value a₁ is stored in memory 91 as a new value for n j . In the subtractor 112 the value a₂ is subtracted from the value b j available at the output 96 of memory 92. The value thus obtained is applied to input 115 through lines 113 and 114, while the switch S₅ has the position shown in the drawing Figure, so that the new value for b j can be stored in the memory location b j in memory 92. The method described hereinbefore is the method as denoted in block 54 in Fig. 5. If the detector 102 detects that n j is unequal to zero, no (or a different) control signal is generated. Switches S₁, S₂ and S₃ then have the positions shown in the Figure. The value c₁q is now subtracted from the value B stored in memory 90 and the result thus obtained is stored again in memory 90. In the adder 117 the value c₁ is added to the value n j which is read from the memory 91 through output 101. Again through lines 108 and 109 the new value for n j is applied to input 111 of memory 91 to be stored in the memory 91. Furthermore, in subtractor 112 the value c₂ is subtracted from the value b j present at the output 91, and the value thus obtained is applied to input 115 through lines 113 and 114 in order to be stored in memory 92. The method described actually corresponds with block 56 of the method shown in Fig. 5. In the method of Fig. 5 there is further shown that the decision block 48, n j ≧ n max ?, provides that b j is made equal to the flag value (block 66 in Fig. 5), and n j equal to n max (should it turn out to be necessary). In the circuit of Fig. 9 this has been taken into account by means of the n j ≧ n max detector 118. If detector 118 detects a situation in which n j ≧ n max , it generates at its output 119 a control signal which is applied to the control input of the controllable switch S₄ and, through an OR-gate 120, to the control input of the controllable switch S₅, which switches then assumes the positions different from the ones shown in the Figure. The value n max , applied to the terminal 121, is now applied to the input 111 of memory 91. n max is then stored in the memory location for n j in memory 91. Accordingly, the flag value, block 122, is applied to input 115 so that the flag value is stored in the memory location for b j in memory 92. It will be evident that there is a central control unit (not shown) which detects the output signal of detector 118 and, on detection of this signal, applies only load pulses to the memories 91 and 92 for storing there n max and the flag value. No load pulse is then applied to memory 90, since the value B in the memory is to remain unchanged. Furthermore, the flag value is allocated to b j if both n j is equal to zero and B ≧ a₁.q+x, compare the blocks 50, 52 and 66 in Fig. 5. Thereto the circuit of Fig. 9 includes the detector 123 and the AND-gate 124. At the occurrence of detection signals of both detector 103 and detector 123, switch S₅ is again set to the other position than the position shown and the flag value b F is stored in memory 92 in location j. In this case the central processor will generate a load pulse only for memory 92 and no load pulses for memories 90 and 91. It will be self-evident that the initial bit allocation as described with reference to Fig. 6 may also be implemented here, for example, controlled by the necessary control and address signals from the central controller. This will not be explained any further because after the above explanation it may be assumed to be within the grasp of those skilled in the art. Fig. 10 shows the use of the subband coder as described hereinbefore, in a transmitter, especially a transmitter in the form of a recording arrangement for recording the quantized subband signals in one or more tracks on a magnetic record carrier. The section referenced 130 is the subband coder discussed hereinbefore, which produces the quantized subband signals at the outputs 4.1 to 4.M. The section referenced 131 converts these signals into a second digital signal which is available at output 132. This second digital signal comprises successive frames of which the format is extensively discussed in the prior-art documents (2a) and (2b). Also the structure of the block 131 is explained in these documents. The section referenced 133 renders the second digital signal suitable for recording on a record carrier, for example, a magnetic record carrier 134. The unit 133 thereto comprises an 8-to-10 converter. In a converter of this type 8-bit data words in the serial information stream are converted to 10-bit code words. Furthermore, interleaving may take place. All this has for its object to enable error correction of the received information on the receiver side (when reproducing the record carrier). The output signal of block 133 is applied to recording means 135 by which the signal is recorded in one or more longitudinal tracks on the record carrier 134. The recording means 135 thereto comprise one or more recording heads 136. For a further explanation of the arrangement of Fig. 10, the prior-art document (8) be referred to, which is also assumed to be incorporated where necessary in this Patent Application. It should further be observed that the invention is not restricted to the depicted exemplary embodiments only. Various modifications of the embodiments described are feasible without leaving the scope of the invention as defined in the claims. In the foregoing the bit need determination and bit allocation have been described for a number of M subband signals, while there was always a single subband signal (for example, a mono signal) in each subband. However, the invention may also be applied to a subband coder for subband encoding of a stereo signal. This implies that there are two subband signals in each subband, that is to say, a left and a right subband signal. Two optional ways of subband encoding of a stereo signal will be briefly discussed hereinbelow. A first option is to process the left and right subband signals separately in the manner described above. The M subband signals SB₁to SB M as discussed above are then, for example, the M left subband signals. The procedure discussed hereinbefore is then carried out for these left subband signals. In the bit need determining means 6 first the bit needs b₁₁ to b M1 are determined. Thereafter, the numbers of bits to be allocated, i.e. n₁₁ to n M1 , are determined in the bit allocation means 7. In the procedure discussed above and explained with reference to Fig. 5, the value B was used for the bit allocation. B was then equal to the number of available bits. It may be obvious that in the present case just half this number of available bits B is used for determining n₁₁ to n M1 . The other half of the number of available bits will then be used for bit allocation to the right subband signals. The arrangement for the stereo signal subband encoding according to the first option actually comprises twice the arrangement shown in Fig. 1. The second section of the arrangement thus comprises a subband splitter, such as the splitter 2, for generating the M right subband signals. Furthermore, a bit need determining means is present, such as unit 6, which determines the bit needs b 1r to b Mr , and a bit allocation means, such as unit 7, which derives therefrom the numbers of allocated bits n 1r to n Mr . Also for this purpose, half the actual number of available bits is available. According to a second option for subband encoding of a stereo signal the bit needs b₁₁ to b M1 and b 1r to b Mr are derived in the same manner as in the first option. In contradistinction to the first option, in which the bit allocation for the left and right subband signals was performed separately, in the second option the 2M bit needs b₁₁ to b M1 and b 1r to b Mr are applied to a bit allocation unit such as unit 7, which then naturally has 2M inputs. In this unit the 2M numbers n₁₁ and n M1 and n 1r to n Mr are derived in a manner similar to the manner described with reference to Fig. 5 on the basis of the actually available number of bits. For this purpose the bit allocation means have 2M outputs. It should further be observed that when a stereo signal is encoded, 2M values for the bit allocation information are concerned, represented each by y bits. This means that for the bit allocation procedure for a stereo signal no more than B=B₀-2.y.M bits are available. PRIOR ART: (1) European Patent Application No. 289.080 (PHN 12.108) (2a) Dutch Patent Application No. 89.01.401 (PHN 12.967) (2b) Dutch Patent Application No. 90.00.338 (PHN 13.241) (3) EBU Techn. Review, No. 230, August 1988 G. Theile et al. "Low bit rate coding of high-quality audio signal. An introduction to the MASCAM system". (4) Philips Journal of Research 44,329-343, 1989 R.N.J. Veldhuis et al. "Subband coding of digital audio signals". (5) IEEE ICASSP 80, Vol. 1, pp. 327-331, April 9-11, 1980 M.A. Krasner "The critical band coder -- Digital encoding of speech signals based on the perceptual requirements of the auditory system". (6) F.J. MacWilliams et al., "The theory of error correcting codes", North Holland publishing comp. 1983 (7) European Patent Application No. 89201408.5 (PHQ 89.018) (8) Dutch Patent Application No. 90.00.635 (PHN 13.281)

Claims: Encoding system, comprising a subband coder for subband coding of a wideband digital signal, for example, a digital audio signal, at a specific sampling frequency F s , the subband coder including signal splitting means for generating, in response to the wideband digital signal, a plurality of P subband signals with sampling frequency reduction, for which purpose the splitting means split up the wideband digital signal into M successive subbands (SB₁...SB M ) which augment with frequency, which encoding system further comprises quantizing means (Q₁...Q M , 6, 7) for quantizing block-by-block the respective subband signals, a quantized subband signal m being composed of successive signal blocks, each signal block comprising q samples, the q samples in a signal block of the subband signal m being represented each by n m bits, the quantizing means including bit need determining means (6) for determining a bit need b m per signal block for corresponding signal blocks in the subband signals, which bit need is related to the number of bits by which samples in a signal block in the subband signal m should be represented, and the quantizing means (Q₁...Q M , 6, 7) including a bit allocation means (7) for allocating an available quantity of bits B to corresponding signals blocks of the various subband signals in response to the bit need determined by the bit need determining means (6) so as to obtain the values n m , where m ranges from 1 to P, and which encoding system further comprises accommodating means for accommodating the samples quantized with a certain number of bits in a signal block in a frame of a second digital signal having successive frames, the accommodating means further being arranged for accommodating the scale factor information in a frame, which scale factor information comprises x-bit words, an x-bit word representing a scale factor associated to the samples in a signal block, characterised in that on the basis of the bit needs, for corresponding signal blocks in the subband signals in the subbands determined in the bit need determining means, the bit allocation means (7) is arranged for the following operations in a specific step S₁: (a) determining b j , which is the largest of the bit needs, (b) establishing whether bits have previously been allocated to the signal block belonging to the bit need b j , and if they have not, then (c) allocating a value a₁ to n j ; subtracting a value a₂ from b j ; subtracting the value a₁.q+x from B, and if they have, then (d) adding the value c₁ to n j ; subtracting the value c₂ from b j ; subtracting the value c₁.q from B, and for performing the step S₁ at least a second time, in that q and x are integers greater than unity, in that n m and b m are variables where n m is greater than or equal to zero, a₁, a₂, c₁ and c₂ are numbers greater than zero and B is an integer greater than zero, m is a variable integer, a₁ is greater than c₁ and a₂ is greater than or equal to c₂. Encoding system as claimed in Claim 1, characterized in that the bit allocation means is arranged for carrying out the following operations in a step S₀ prior to the steps S₁, for a signal block k in a subband allocating a value A k0 to n k ; subtracting the value A k1 from b k ; subtracting the value A k0 .q+x from B, and in that A k0 and A k1 are numbers greater than zero. Encoding system as claimed in Claim 2, characterized in that the bit allocation means is arranged for allocating a flag value in the step S₀ to a signal block in one or more of the subbands, which flag value indicates that no bits are to be allocated to the signal block concerned. Encoding system as claimed in Claim 2 or 3, characterized in that A k0 is equal to a₁ and A k1 is equal to a₂. Encoding system as claimed in one of the preceding Claims, characterized in that a₁ is equal to a₂ and c₁ is equal to c₂. Encoding system as claimed in one of the preceding Claims for subband encoding of a single digital signal, such as a mono signal or a left or right signal portion of a stereo signal, characterized in that P = M. Encoding system as claimed in one of the Claims 1 to 5 for subband encoding of a stereo signal, comprising a left and a right signal portion, characterized in that P = 2M. Transmitter comprising the encoding system as claimed in one of the preceding Claims 1 to 7. Transmitter as claimed in Claim 8, characterized in that the transmitter has the form of an arrangement for recording the quantized subband signals in a track on a record carrier. Transmitter as claimed in Claim 9, characterized in that the record carrier is a magnetic record carrier.

Inventors: KEESMAN GERRIT JOHAN, VELDHUIS RAYMOND NICOLAAS JOHA, KEESMAN, GERRIT JOHAN, VELDHUIS, RAYMOND NICOLAAS JOHAN
Applicants: PHILIPS ELECTRONICS NV, PHILIPS ELECTRONICS N.V.
Application year: 1991
Main classification: H04B1
IPC codes: G10L19, H04B1, H03M9, H04B14, H03M7, G06T9