BICMOS gate array device

Abstract: A semiconductor device has a plurality of basic cells fabricated on a single semiconductor substrate. Each of the basic cells comprises a first-conduction-type FETs (P3, P4; P5, P6), a second-conduction-type FETs (N3, N4; N5, N6), and a bipolar transistor (2, 4, 5). The collector region of the bipolar transistor is formed in a well region (2) where the first-conduction-type FETs are formed. The bipolar transistor is formed between the first-conduction-type FETs of adjacent ones of the basic cells separated by an element insulation film.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device in which bipolar transistors and FETs (field effect transistors) are merged to form basic cells. Description of the Prior Art Figure 1 shows a conventional BiCMOS logic circuit having a totem-pole output buffer for compensating the low driving capacity of a CMOS circuit. This arrangement involves a long output delay time, because MOS transistors to be used for the arrangement have been integrated in recent years, and therefore, the power source voltage of the MOS transistors is very low to increase the power source voltage dependency of the output delay time. To deal with this problem, BiNMOS and BiRNMOS logic circuits each employing n-channel MOS transistors (hereinafter referred to as the NMOS transistors) instead of a bipolar transistor on the grounding side of an output stage of the circuit are frequently used for semiconductor integrated circuits fabricated according to a design rule of about 0.5 micrometers. Figure 2 shows a 2-input NAND gate as an example of the BiNMOS logic circuits, and Fig. 3 shows a 2-input NAND gate as an example of the BiRNMOS logic circuits. The BiRNMOS circuit of Fig. 3 has, in addition to the BiNMOS circuit of Fig. 2, NMOS transistors N1 and N2 for improving the speed of discharging the base charges of an NPN bipolar transistor B1 through a resistance R. This BiNMOS or BiRNMOS circuit employs only one bipolar transistor B1 whose collector potential is always at a power source potential as shown in Figs. 2 and 3. When the BiNMOS circuit is used as an internal gate circuit of a gate array whose cells are identically arranged in a process before a wiring process, a collector region of the output NPN bipolar transistor B1 can be formed in an n-type well region where p-channel MOS transistors (hereinafter referred to as the PMOS transistors) P1 and P2 are formed. An example of this kind of arrangement is disclosed in for example, Japanese Laid-Open Patent No. 59-177945. This disclosure simply arranges an output NPN bipolar transistor and PMOS transistors in the same n-type well region. This arrangement involves, therefore, an increased circuit area compared with a CMOS gate array that employs MOS transistors only. The disclosure, therefore, hardly realizes high integration of semiconductor devices. Figure 4 is a layout showing a basic cell of the CMOS gate array, and Fig. 5 is a layout showing a cell of a logic gate that has been designed to make full use of the layout of Fig. 4. In Fig. 5, an NPN bipolar transistor is disposed on the longitudinal side of the basic cell region. This layout increases a cell area approximately 25% more than that of Fig. 4. Figures 6A and 6B are sectional and plan views showing another example of the conventional logic gates, in which an NPN bipolar transistor is merged in the source or drain region of a PMOS transistor of a basic cell of a CMOS gate array. Fig. 6B corresponds to Fig. 2 of IEEE CICC 1990, pp 421-424 "A Bipolar-PMOS Merged Basic cell for 0,8 µm BiCMOS Sea-of-Gates" In this arrangement, the base region of the NPN bipolar transistor and the source or drain region of the PMOS transistor will be formed in the same diffusion layer. An impurity concentration of the base region of the bipolar transistor must be lower than that of the source or drain region of the PMOS transistor. If this low impurity concentration of the base region of the bipolar transistor is applied to form a p-type diffusion layer in which the source or drain region of the PMOS transistor is also to be formed, the arrangement of Figs. 6A and 6B will deteriorate the properties of the PMOS transistor and thus those of the CMOS circuit. EP-A-0 133 131 shows using an additional gate electrode as an isolation device between an MOS and a bipolar transistor. A potential is applied to this electrode. IEEE Journal of solid state circuits vol 25 No.1 February 1990 p142-149 shows a bipolar transistor between FETs. Proc. IEEE 1989 custom integrated circuits conference p851-854 shows an oxide film used in a BiCMOS basic cell layout. SUMMARY OF THE INVENTION To solve these problems of the conventional techniques, an object of the invention is to provide a semiconductor device involving a BiCMOS circuit with basic cells each occupying substantially the same area as that occupied by a basic cell of a CMOS gate array. This device realises the compactness without deteriorating its properties. According to the invention there is provided a semiconductor device as set out in claim 1. Preferred features are set out in dependent claims. The area of each basic cell of the BiCMOS circuit of the invention is substantially equal to that of a basic cell of a CMOS gate array. This arrangement, therefore, contributes to high integration of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram showing a basic cell of a conventional BiCMOS logic circuit; Fig. 2 is a circuit diagram showing a basic cell of a conventional BiNMOS logic circuit; Fig. 3 is a circuit diagram showing a basic cell of a conventional BiRNMOS logic circuit; Fig. 4 is a layout showing a basic cell of a conventional CMOS logic circuit; Fig. 5 is a layout showing a basic cell of a conventional BiCMOS logic circuit; Figs. 6A and 6B are sectional and plan views, respectively, showing a basic cell of a conventional BiCMOS logic circuit; Fig. 7 is a layout showing a basic cell of a BiNMOS logic circuit according to an embodiment of the invention; Fig. 8 is a sectional view showing the basic cell of the BiNMOS logic circuit of the embodiment; Fig. 9 is a layout showing a basic cell of a BiNMOS logic circuit according to another embodiment of the invention; Fig. 10 is a comparison diagram of the input/output delay time and fan-out of basic cells of a BiNMOS logic circuit and CMOS logic circuit; and Fig. 11 is a layout showing a basic cell of a BiNMOS logic circuit not forming part of the claimed invention. DETAILED DESCRIPTION OF THE EMBODIMENTS The embodiments of the invention will be explained with reference to the drawings. Figure 7 is a layout showing a basic cell of a semiconductor device according to an embodiment of the invention, and Fig. 8 is a sectional view taken along a line I-I of Fig. 7. The embodiment of Fig. 7 relates to a BiNMOS circuit of a BiCMOS gate array formed on the basic cell of the CMOS gate array shown in Fig. 5. In Fig 7, a p-type semiconductor substrate 1 includes an n-type well region 2 in which pairs of PMOS transistors P3 and P4, and P5 and P6 are formed. Pairs of NMOS transistors N3 and N4, and N5 and N6 corresponding to the PMOS transistor pairs are formed on the longitudinal side of the PMOS transistors P3 to P6. In the BiCMOS gate array, the PMOS transistor pair P3 and P4 and the PMOS transistor pair P5 and P6 belong to different basic cells. respectively. These pairs are electrically separated from each other by an element insulation film 3 such as an oxide film. The NMOS transistors N3 and N4 are similarly separated from the NMOS transistors N5 and N6. The PMOS transistors P3 and P4 and NMOS transistors N3 and N4 belong to the same basic cell, while the PMOS transistors P5 and P6 and NMOS transistors N5 and N6 belong to another same basic cell. An NPN bipolar transistor is formed in the n-type well region 2 between the PMOS transistor pairs P3 and P4, and P5 and P6. This bipolar transistor comprises a collector region that is equal to the n-type well region 2, a p--type base region 4 formed in the n-type well region 2, and an n+-type emitter region 5 formed in the base region 4. The base region 4 of the bipolar transistor is joined with a p+-type diffusion layer region 6 serving as the source or drain of the PMOS transistor P4. A well contact 7 is formed in the n-type well region 2 between the PMOS transistor pairs P3 and P4, and P5 and P6 so that the well region 2 may have a power source potential. The well contact 7 also serves as the collector electrode of the bipolar transistor. The n-type well region 2 serving as the collector region of the bipolar transistor is connected to a power source through the well contact 7 and wiring. A resistance 8 made of, for example, an n--type diffusion layer or polycrystalline silicon is formed between the NMOS transistor pairs N3 and N4, and N5 and N6. A sub-contact 9 for setting the substrate 1 to a ground potential is formed in the vicinity of the resistance 8. The PMOS transistors P3 and P4, NMOS transistors N3 and N4, bipolar transistor, and resistance 8 are wired to constitute the BiNMOS basic cell of Fig. 3. Compared with the layout of Fig. 4 showing the basic cell of the CMOS gate array, the layout of Fig. 7 of the invention has the base region 4 and emitter region 5 of the NPN bipolar transistor in a part of the well contact region of the CMOS circuit, and the resistance 8 in a part of the sub-contact region of the CMOS circuit. The area of each basic cell of the invention is, therefore, remarkably smaller than the cell area of the conventional BiCMOS gate array in which the bipolar transistor is simply arranged on the longitudinal side of the basic cell of the CMOS gate array. Namely, the invention can form the basic cell of the BiCMOS gate array with substantially the same area as the basic cell of the CMOS gate array. In addition, according to the invention, the diffusion layer region serving as the source or drain region of the PMOS transistor and the base region of the bipolar transistor can be separately formed each at an optimum impurity concentration, so that no deterioration may occur in the properties of the transistors. Figure 9 is a layout showing another embodiment of the invention. In the figure, the BiRNMOS circuit of Fig. 3 is similarly formed on the basic cell of the CMOS gate array. In Fig. 9, the same reference marks as in Fig. 7 represent like parts, and therefore, the explanations thereof will be omitted. Similar to the previous embodiment, a bipolar transistor is formed between adjacent PMOS transistors that belong to different basic cells. NMOS transistors N7 and N8 for discharging the base of the bipolar transistor are arranged adjacent to and on the longitudinal side of NMOS transistors N3 and N4. Each basic cell of this layout occupies an area about 8% larger than that occupied by the basic cell of the CMOS gate array. In this way, this embodiment can realize a BiCMOS gate array involving BiRNMOS circuits without greatly increasing its area compared with the CMOS gate array. Figure 10 shows a relationship between input/output delay time and fan-out of a CMOS basic cell and of a BiRNMOS basic cell. As is apparent in the figure, the response speed of the CMOS basic cell is faster than that of the BiRNMOS basic cell around fan-out 1, but the BiRNMOS basic cell becomes faster than the CMOS basic cell around fan-out 2 and thereafter. To actually constitute a required circuit with the BiCMOS gate array, the CMOS basic cells are used for a part where load is small, and BiRNMOS basic cells for a part where load is large. In this way, both types of the basic cells can be used in a single gate array. If the base region of a bipolar transistor is joined to each of the diffusion layer regions of PMOS transistors. that are arranged on each side of the base region of the bipolar transistor and belonging different basic cells, the use of one of the diffusion layer regions of the PMOS transistors restricts the use of the other. It is preferable, therefore, to isolate the base region of the bipolar transistor from one of the diffusion layer regions of the PMOS transistors that belong to the different basic cells separated from each other with an element insulation region. The base region of the bipolar transistor may instead be isolated from each of the diffusion regions of the PMOS transistors disposed on each side of the base region, as shown in Fig. 11, which does not form part of the claimed invention. As explained above, the invention arranges a bipolar transistor as an element of a basic cell in a region that separates FETs belonging to different basic cells from each other. This arrangement can reduce the area of each basic cell in a BiCMOS circuit, compared with conventional circuits, without deteriorating the properties of the transistors. Namely, each basic cell of the BiCMOS circuit of the invention occupies substantially the same area as that occupied by a basic cell of a CMOS gate array. The invention thus contributes to high integration of semiconductor devices.

Claims: A semiconductor device having a plurality of basic cells fabricated on a single semiconductor substrate (1) of first conductivity type (p), each basic cell comprising: a FET (P3, P4) of first conductivity type formed in a well region (2) of second conductivity type (n) of said substrate (1); a FET (N3, N4) of second conductivity type formed in said substrate (1); a bipolar transistor being formed in said well region (2) between the FET (P3, P4) of first conductivity type of a first such basic cell and the FET (P5, P6) of first conductivity type of a second such basic cell adjacent to the first such basic cell with a collector region of the bipolar transistor in said well region (2); a base region (4) of first conductivity type of the bipolar transistor having an impurity concentration lower than the impurity concentration of a diffusion layer (6) being a source/drain region of the FET (P3, P4) of first conductivity type of the first such basic cell characterized in that: the base region (4) of the bipolar transistor is in permanent contact with the source/drain region (6) of the FET (P3, P4) of first conductivity type of the first such basic cell, and is insulated from the source/drain region of the FET (P5, P6) of first conductivity type of the second adjacent such basic cell by an element isolation film (3) separating the first such basic cell and the second adjacent such basic cell. A semiconductor device according to claim 1, further comprising a resistance (8) formed between the FET (N3, N4) of second conductivity type of the first such basic cell and the FET (N5, N6) of second conductivity type of the second adjacent such basic cell. A semiconductor device according to claim 1 or claim 2, further comprising a first contact region (7) formed in said well region (2) between the FET (P3, P4) of first conductivity type of the first such basic cell and the FET (P5, P6) of first conductivity type of the second adjacent such basic cell, the first contact region (7) being for maintaining the well region (2) at a first power source potential. A semiconductor device according to any one of claims 1 to 3, further comprising a second contact region (9) formed between the FET (N3, N4) of second conductivity type of the first such basic cell and the FET (N5, N6) of second conductivity type of the second adjacent such basic cell, the second contact region (9) being for maintaining the semiconductor substrate (1) at a second power source potential. A semiconductor device according to claim 4 depending upon claim 3, claim 3 depending upon claim 2, wherein the first contact region (7), an emitter region (5) of the bipolar transistor, the resistance (8), and the second contact region (9) are arranged in a substantially straight line.

Inventors: MOMOSE HIROSHI, NAGAMATSU TETSU, MOMOSE, HIROSHI, NAGAMATSU, TETSU
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: H01L27
IPC codes: H01L27, H01L21