High current hermetic package

Abstract: A package for a device comprises a header having a substantially flat upper surface. An insulating disk is affixed to the upper surface of the header for having the device mounted thereon. A barrel having upper and lower portions of respectively greater and smaller diameters, and having a step between the diameters, has a lower edge thereof attached to the upper surface of the header so as to surround the disk. A ceramic lid in the upper portion of the barrel abuts the step is attached thereat.

Description: The present invention relates generally to a package for an electronic device, and more particularly to a package for hermetically sealing electronic devices and circuits. It is well known in the art to use packages for enclosing electronic devices, such as semiconductor chips, power semiconductor chips and the like. Hermetically sealed devices providing connections to the enclosed device are commonly used in the art. A hermetic package arrangement of this type for large scale integrated circuits, or hybrid circuits is disclosed, for example, in U.S Patent No. 4,076,955, issued February 28, 1978 to Gates, Jr. A device, such as an integrated circuit wafer, is attached to a base and a sealing ring enclosure surrounding the device is hermetically sealed to the base. The sealing ring has a greater height than the wafer. Above the device, a lid is hermetically sealed to a sealing area provided on the sealing ring. Soldering is used to secure various lid embodiments to areas to be covered and hermetically sealed on the packages. Radial leads with conventional wire bonding are disclosed for providing connections to the device. A hermetic package for integrated circuits used in high power applications is disclosed in U.S Patent No.4,3398,621, issued July 6, 1982 to Braun. This shows an integrated circuit mounted on a surface of a multilayer ceramic member and wire-bonded to electrically conductive tabs near the periphery of the device. Input/output pins are provided on the exterior surface of a ceramic lid. The package includes a ceramic base member having an interior recess upon which an integrated circuit is mounted. The plurality of electrically conductive tabs is arranged about the circumference of the integrated circuit, for connection via wires bonded thereto at one end and to contact pads on the planer surface of the ceramic base member. The metallized lines are used to connect the pads to electrically conductive bosses on the exterior surface of the ceramic lid for providing input and output pins. Brazing is used to hermetically seal the input and output pins to the bosses, and solder reflow is used for sealing the base and cover members to each other. Also, solder reflow is used for establishing electrical connections between the die and the pins via the corresponding pads. An important consideration in the design of a package enclosing a power device is the difference in the temperature coefficient of expansion of different materials that may be utilized in adjacent parts in such a package. Problems caused by such differences are alleviated by utilizing materials having temperature coefficients as well matched as possible. Thus, U.S Patent No.4,646,129 issued February 24, 1987 to Yerman et al., for example, discloses a hermetic package including a gasket with a temperature coefficient close to that of a dielectric plate of the hermetic package. The dielectric plate has transistor electrodes on the underside thereof. Electrical access to these electrodes is provided from the top side of the dielectric plate by corresponding leads which are connected via conducting-through holes in the dielectric plate. U.S Patent No. 4,651,192 issued on March 17, 1987, to Matsushita et al. discloses a ceramic package for a semi-conductor integrated circuit device. The package includes an insulating substrate fabricated from a ceramic material, upon which is mounted one or more integrated circuits. An alumina ceramic cap is bonded to the ceramic substrate via a solder glass layer, for forming a hermetically sealed package. Terminals for providing electrical connections to the package are sandwiched between the cap and substrate, whereby interior ends of the terminals are electrically connected to the integrated circuit, with the other ends of the terminals being external to the package for providing signal and power connections. The particular ceramic materials used are specifically disclosed for providing very closely matched coefficients of thermal expansion. Various other package arrangements are disclosed, for example, in U.S Patent No. 2,990,501 issued June 27, 1961 to Cornelison et al.; U.S Patent No. 4,514,587 issued April 30, 1985 to Van Dyk Soerewyn; and U.S Patent No. 4,560,826 issued December 24, 1985 to Burns et al. Cornelison et al. discloses the use of a housing, including a dish-shaped metal header assembly in a lower portion, electrical leads having portions of the lead outside of the housing, and portions within the interior thereof for making electrical connection to a semiconductor element. Insulating material fills the lower portion of the header assembly for electrically isolating the leads from the metal header. The portions of the leads protruding from the housing are soldered to eyelets, for making electrical connections to printed circuit pads of a substrate. Cornelison et al. also discloses that the lower metal shell can be formed from a ceramic or glass disc with a metallic ring thereabout for bonding the housing to the disc. Van Dyk Soerewyn discloses a power semi-conductor package in a top-hat configuration, that includes an encapsulant within the cylindrical section of the enclosure about the integrated circuit assemblies mounted therein. Burns et al. discloses a hermetically sealed package for an integrated circuit (IC). The package includes the mounting of an integrated circuit on a substrate with all electrical connections to the IC made on top of the substrate to vias. The opposite side of the substrate includes leads electrically connected to leads on the opposite side for providing signal and power connections to the package. In this regard, a pedestal is included for electrically interconnecting the inner and outer leads. A sealing ring is provided about the circumference of the area in which the integrated circuit is mounted, for sealing to a ceramic cap via a sealing skirt about the circumference of the bottom edge of the cap. It is herein recognized that the use of, for example, aluminum wire bonds for providing connections between a device, such as an IC chip in the package and outside circuitry may require that the metallization on the chip be preferably aluminum and that such a restriction may be undesirable. Furthermore, the use of wire bonds tends to introduce a relatively high parasitic inductance in the connection. It is herein also recognized that connections utilizing straps are preferable in this regard, and that top-side connection to a device is desirable. However, it is also desirable that, in meeting such requirements, the package profile be kept low and that, in so far as is possible, conventional manufacturing processes be utilizable. A package for a semiconductor device is described in document FR-A-2,527,837 as comprising: a header having a substantially flat under surface and a substantially flat upper surface, an insulating disk of beryllium oxide fixed to said upper surface, said insulating disk having conductive patterns thereon, connection leads, conductively attached to respective ones of said conductive patterns, and a barrel having upper and lower substantially cylindric portions of respectively greater and smaller diameters having a circumferential step therebetween forming a shoulder. The package of this document is used for high voltage semiconductor devices and is an all-ceramic package. It does not use any metallic parts for the encasing. The problem underlying this document is the electric strength of such a package when a high voltage of e.g. 10,000 Volt between the semiconductor die and the metallic base occurs. Further, from the US-A-4,514,587 a high power semiconductor package is known which includes a metal header having a cylindrical section and peripheral mounting flange adapted for attachment to a mounting surface. From the Encyclopedia of Chemical Technology, Third Edition Wiley NY, US 1981, Vol. 13, it is generally known to use forsterite as a circuit substrate at microwave frequencies. Illustrative embodiments of the invention, as disclosed herein seek to provide: a device package wherein closely matched thermal coefficients of expansion are utilized while providing for good heat dissipation capability; high current carrying capacity in the connections to a device hermetically contained in the package; internal electrical isolation within the package; and/or the foregoing provisions in a package that is of light weight and has a small profile In accordance with an embodiment of the invention, a package for hermitically sealing an electronic device comprising the features of claim 1 is provided. Further advantageous embodiments of the invention are defined in the dependent claims. The invention will be more fully understood from the following detailed description of the preferred embodiments of the invention, in conjunction with the drawing, in which like items are identified by the same reference designation, whereon: Figure 1 shows an exploded assembly view, in isometric projection, of one embodiment of the invention: Figure 2 shows a exploded view in a side elevation of the embodiment of the invention of Figure 1; and Figure 3 shows an outside view, in isometric projection of the embodiment of the invention. As shown in Figure 1, a metallic header or base portion 2 has a generally flat upper surface 4 and a bottom or under surface adapted for being attached to a mounting surface. Holes 6 are provided for fastening by means of screws, rivets, or other fasteners. A ceramic isolation disk 8 is attached to upper surface 4 of header 2. Ceramic isolation disk 8 has conductive patterns 10, 10' , 10" formed thereon for having attached thereto an electronic device or circuit, such as a power device chip, and various leads for providing electrical connections to the device by way of the conductive patterns. In the present exemplary embodiment, the device is a power transistor formed in a silicon semiconductor die 12. Connection to the electrodes of semiconductor die 12 is provided by flat leads for low inductance, high current carrying capacity, and desirable physical ruggedness. Thus, a drain lead 14 is attached directly to conductive pattern 10 for thereby electrically contacting the drain electrode of die 12. A source lead 16 is attached to conductive pattern 10', for thereby contacting the source electrode by way of a source strap 18, which bridges from source lead 16 to the source contact pad on the die. In order to solder strap 18 to the source contact pad, it is desirable to place gold balls on the contact pad on the die to facilitate soldering between nickel plated copper and gold. In operation, lead 14 and source strap 16 carry the main conduction path current and are therefore of a substantial cross-section for low voltage drop under heavy current conditions and have low inductance. Nevertheless, some voltage drop will inevitably occur, including a voltage drop in metallization pattern 10'. It may sometimes be important to avoid undesirable electrical feedback effects caused by such voltage drops and to that end, a further source lead is provided as a sensing or Kelvin lead 20 which provides a connection to a point in the source circuit which does not include a portion of the voltage drop occurring in the source lead. The gate electrode of semiconductor die 12 is required to carry currents that are very small in comparison with the main source/drain current and consequently, it is adequate to make the connection between a gate lead 22 and the gate electrode contact pad on the die by way of an aluminun bond wire 24. A metallic barrel portion 26, generally tubular in form, is attached at its lower edge to top surface 4 of header 2. The diameter of the opening at the bottom of barrel portion 26 is such as to fit around ceramic isolation disk 8. Barrel portion 26 has a lower portion 28 that is generally cylindrical and an upper portion that is stepped in its circumference at a shoulder 29 so that the diameter of the opening at the top of barrel 26 is larger than the opening at the bottom. The diameter of the opening at the top of barrel portion 26 is such as to allow a fit around a ceramic lid 30 which abuts shoulder 29 in barrel portion 26. Ceramic lid 30 has therein openings or lead slots 32, 34, 36, and 38 for allowing drain lead 14, source lead 16, Kelvin lead 20, and gate lead 22 to pass through and protrude beyond the upper surface of ceramic lid 30 for allowing connections to be made thereto to external circuitry. Figure 2 will be helpful in further clarifying the arrangement of the parts and in illustrating shoulder 29 in barrel portion 26. While various choices of materials are possible, in the present exemplary embodiment, header 2 is preferably made of a clad system such as a copper-molybdenum-copper clad or copper-invar-copper clad having a total thickness in the order of 1.27 mm (0.05 inch). In this manner, high thermal conductivity is obtained together with mechanical strength for mounting. Good matching of thermal coefficients of expansion provides resistance to fatigue related damage as may result from thermal cycling. Ceramic isolation disk 8 is preferably fabricated from beryllium oxide of about 0.762 mm (0.030 inch) thickness and is direct bonded with copper on each side of about 0.254 mm (0.010 inch) thickness. The top copper layer is then etched to form conductive patterns 10, 10', and 10". High thermal conductivity and high breakdown voltage are exhibited by this material combination. The thermal coefficient of expansion is in the order of 8 parts per million per degree Celsius. Barrel portion 26 is preferably made from 0.762 mm (0.030 inch) thick 1020 steel using a stamp, coin, and pierce procedure. Such a procedure results in an inexpensive, lightweight structure having a thermal coefficient of expansion of about 12 parts per million per degree Celsius. Drain lead 14, source lead 16, Kelvin lead 20, gate lead 22, and strap lead 18 are cut and formed from 0.635 mm (0.025 inch) CDA 102 copper. This material lends itself readily to being formed and provides high current carrying capacity at low cost. The thermal coefficient of expansion is about 16 parts per million per degree Celsius. Ceramic lid 30 is preferably fabricated from pressed and sintered Forsterite TM . Only the outer circumference of lid 30 and lead slots 32, 34, 36, and 38 are metallized with lithium molybdate, and thereafter are nickel-plated for solderability. Thus, the non-metallized parts of ceramic lid 30 provide electrical isolation between leads. Forsterite TM exhibits a thermal coefficient of expansion of about 10 parts per million per degree Celsius. In assembling the package, header 2, ceramic isolation disk 8, barrel portion 26, drain lead 14, source lead 16, Kelvin lead 20, and gate lead 22 are mated together, fixtured and brazed using a silver/copper braze alloy. The assembly is then electroless nickel plated for corrosion resistance and solderability. Silicon die 12 and source strap 18 are then mounted in the package using solder alloy preforms, then reflowed in a hydrogen/nitrogen forming gas atmosphere. Gate bond wire 24 is preferably a 0.127 mm (0.005 inch) aluminum wire ultrasonically bonded from gate lead 22 to the gate electrode contact pad on die 12. Ceramic lid 30 is slid over drain lead 14, source lead 16, Kelvin lead 20, and gate lead 22 and into barrel portion 26. Solder alloy wire preforms are put in place and reflowed in a forming gas atmosphere so as to result in solder joints that form a hermetic seal around lid 30 and drain lead 14, source lead 16, Kelvin lead 20, and gate lead 22. Figure 3 shows the exemplatory assembled package. The assembled profile height is typically under 6.35 mm (0.25 inch) and the weight under 25 grams. Current carrying capacity is in the order of 100 Amperes and the voltage breakdown is in order of 1000 Volts. While the invention has been described by way of exemplatory embodiments, various changes will be apparent to one skilled in the art which do not depart from the spirit and scope of the invention.

Claims: A package for hermetically sealing an electronic device, comprising a metal header (2) and having a substantially flat under surface and a substantially flat upper surface, an insulating disk (8) of beryllium oxide affixed to said upper surface of said header (2) by brazing, said insulating disk (8) having conductive patterns (10, 10', 10") formed on the upper side thereof for mounting said electronic device (12) and connection leads (18) for said electronic device, flat connection leads (14, 16, 20, 22) respectively brazed to said conductive pattern, a metal barrel having upper and lower substantially cylindrical portions (26, 28) of respectively greater and smaller internal diameters and having a circumferential step therebetween forming a shoulder (29), a lower edge of the lower portion (26) of said barrel being attached to said upper surface of said header (2) so as to form a hermetic seal so as to surround and contain said insulating disk (8) within said lower portion (28) of said barrel, a ceramic lid (30) having a diameter slightly less than that of said upper portion (26), hermetically sealed to said shoulder via said ceramic lid (30) having a circumference plated with nickel plated lithium molybdate and being attached by soldering at said circumference to said barrel (26, 28), said ceramic lid having slots (32-38) therein through which said connection leads (14, 16, 20, 22) pass, said slots being peripherally plated with nickel plated lithium molybdate and being respectively soldered to said leads to form a hermetic seal therewith, and said electronic device (12) being mounted on said conductive pattern (10) said insulating disk (8). A package as claimed in claim 1 characterized in that said header (2) is a clad of copper, molybdenum, and copper, or is a clad of copper, invar, and copper. A package as claimed in claim 1 or 2, characterized in that the metal header (2) comprises a base with a flat top surface, and flat bottom surface, the barrel (26, 28) is attached to said top surface, the insulating disk (8) is a ceramic disc attached to said top surface and within said barrel, with first (10) and second (10') isolated conductive patterns formed on said ceramic disk, said electronic device (12) is a die having opposed planar conductive electrode surfaces, one surface being in contact with said first conductive pattern, a first flat lead (14) is conductively attached to said first conductive pattern (10) in an area outside said die (12) and extending upwardly therefrom, a second flat lead (16) is electrically and mechanically attached to said second conductive pattern (10') and extending upward therefrom, a flat metal strap (18) has one end of one surface electrically connected to said second conductive pattern (10'), and the outer end of said one surface is electrically connected to the other surface of said die (12), the ceramic lid (30) encloses said die (12), and said lid has a disk shape. A package as claimed in claim 3 characterized in that said base is made of copper, said isolation disk is made of beryllium oxide bonded with copper, and said barrel is made of steel, in which said means for hermetically sealing said lid to said barrel and said leads to said slots comprises metallization with nickel plated lithium molybdate. A package as claimed in claims 3 or 4 characterized by a third conductive pattern (10") formed on said disk, a third lead (22) conductively attached to said third conductive pattern (10"), said planar conductive electrode surfaces being respectively source and drain electrodes of said die (12), said die having a gate electrode, and an electrical connection between said third conductive pattern and said gate electrode. A package as claimed in claim 5 characterized by a fourth lead (20) electrically and mechanically attached to said conductive pattern (10). A package as claimed in one of the preceding claims, characterized by a conductive strap (18) having one end conductively attached to the other surface of said electronic device (12) and its other end conductively attached to a conductive pattern (10') other than the one (10) to which said electronic device is attached.

Inventors: SATRIANO ROBERT JOSEPH, SATRIANO, ROBERT JOSEPH
Applicants: HARRIS SEMICONDUCTOR PATENTS, HARRIS SEMICONDUCTOR PATENTS, INC.
Application year: 1991
Main classification: H01L23
IPC codes: H01L23