Spread packet communication system

Abstract: A satellite packet communication system comprising a central station and VSAT stations. The central station generates chip-rate clock pulses and transmits a series of data on timeslots of a frame to a satellite transponder, and a plurality of terminal stations. Each VSAT station receives the frame from the transponder and recovers the chip-rate clock pulses from the received frame. A pseudorandom number (PN) sequence generator is synchronized with the recovered chip-rate clock pulses for generating bits of a PN sequence which which packetized data bits are pseudorandomly modulated and transmitted in burst form to the transponder. The central station includes a correlator which is synchronized with the central station's chip-rate clock pulses to detect correlations between the pseudorandomly modulated data bits a sequence of pseudorandom numbers corresponding to the PN sequence bits of the terminal stations.

Description: The present invention relates generally to satellite packet communications systems, and more specifically to a spread packet communication system. The slotted and unslotted ALOHA packet communication systems are well known. In these systems, very small aperture terminal (VSAT) stations randomly transmit their data packets in burst form via a satellite transponder to a central station. A modified version of the ALOHA system is the spread ALOHA network which was proposed in 1986 by Norman Abramson and is described in "Spread ALOHA for VSAT Networks", Norman Abramson, Technical Report B86-4b, University of Hawaii, June, 1986 (rev. 1/87). According to this technique, packet data from each VSAT station are distributed or "spread" on the time domain using a coded sequence of pseudorandom numbers in order to reduce the probability of burst collisions and to reduce per-bit transmission power. Two spread modes are known. One is the bit spread ALOHA in which each data bit is spread into a plurality of pseudorandom code bits, and the other is the chip spread ALOHA in which each pseudorandom code bit (or chip) is spread with the data bits of a packet. No implementations of the proposed spread ALOHA system have yet been made due to anticipated hardware complexities of central station's demodulator system which must be synchronized with high-speed chip-rate clock pulses to detect correlations between received data bits and a pseudorandom number (PN) sequence see also : Proceedings of the IEEE, vol. 78, no. 7, July 1990, New York, US, pages 1267-1274; N. Abramson : "VSAT Data Network". It is therefore an object of the present invention to provide a spread packet communications system which simplifies the hardware of its central station equipment. This object is solved with the feat of the claims. A satellite packet communication system as described comprises a central station which generates chip-rate clock pulses and transmits a series of data on timeslots of a frame to a satellite transponder, and a plurality of terminal stations. Each terminal station receives the frame from the transponder and recovers the chip-rate clock pulses from the received frame. The terminal station includes a pseudorandom number (PN) sequence generator synchronized with the recovered chip-rate clock pulses for generating bits of a PN sequence whith which packetized data bits are pseudorandomly modulated and transmitted in burst form to the transponder. The central station includes a correlator which is synchronized with the central station's chip-rate clock pulses to detect correlations between the pseudorandomly modulated data bits and a sequence of pseudorandom numbers corresponding to the PN sequence bits of the terminal stations. The hardware simplification for bit spread packets is obtained by recovering the chip-rate clock pulses from the data rate of a received frame signal in each terminal station. Specifically, the central station of a bit spread packet communication system generates chip-rate clock pulses, derives data-rate clock pulses from the chip-rate clock pulses, and transmits a series of data in synchronism with the data-rate clock pulses on timeslots of a frame to a satellite transponder. Each terminal station includes a data-rate clock recovery circuit which recovers data-rate clock pulses from the frame signal received from the transponder and a chip-rate clock recovery circuit for recovering chip-rate clock pulses from the recovered data-rate clock pulses for synchronizing the pseudorandom number (PN) sequence generator. In order to compensate for different round-trip propagation delay times among the terminal stations, the central station receives its own frame signal from the transponder and recovers the data-rate clock pulses from the received frame. A first chip-rate clock recovery circuit recovers chip-rate clock pulses from the recovered data-rate clock pulses and a second chip-rate clock recovery circuit is provided for recovering chip-rate clock pulses from an output signal of the correlator. A phase detector is connected to the first and second chip-rate clock recovery circuits for detecting a phase difference between their output signals and a signal indicating the detected phase difference is transmitted on a timeslot to the transponder. Each terminal station receives the phase-difference signal on an assigned timeslot and controls the phase timing of the chip-rate clock pulses which are supplied to the PN sequence generator according to the phase-difference signal.. In order to minimize the interference caused by burst collisions,each terminal station recirculates the PN sequence generator by k bits, where k is in the range between 1 and m - 1, where m is the number of bits in the PN sequence. Packetized data bits from each terminal station are synchronized with the recovered data-bit clock pulses. The central station's correlator includes 2 × m multipliers which are divided into first and second groups, the multipliers of each group having m pseudorandom numbers. The k value of each terminal station differs from the k value of the other terminal stations. The hardware simplification for chip spread packets is obtained by recovering chip-rate clock pulses from the start timing of a received frame signal at each terminal station. Specifically, the central station generates chip-rate clock pulses corresponding to timeslots of a frame and transmitting a series of data on the timeslots to a satellite transponder. Each terminal station receives the frame from the transponder, detects the start timing of the received frame and recovers the chip-rate clock pulses from the detected frame start timing for synchronizing the PN sequence generator. The present invention will be described in further detail with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of a bit spread ALOHA satellite communication system according to a first embodiment of the present invention; Fig. 2 is a waveform diagram associated with Fig. 1; Fig. 3 is a block diagram of a bit spread ALOHA satellite communication system according to a second embodiment of the present invention; Fig. 4 is a block diagram of a bit spread ALOHA satellite communication system according to a third embodiment of the present invention; Figs. 5A and 5B are illustrations of colliding data bit streams associated with Fig. 4; Fig. 6 is a block diagram of a chip spread ALOHA satellite communication system of the present invention; and Fig. 7 is a waveform diagram associated with Fig. 6. Referring now to Fig. 1, there is shown a spread ALOHA satellite communication system according to one embodiment of the present invention. The system comprises a central station 1 and a plurality of VSAT (very small aperture terminal) stations 2-1 through 2-N interconnected with the central station via a satellite transponder 30. Central station 1 comprises a chip-rate clock generator 18 which supplies 256-kbps chip-rate clock pulses to a data-rate clock generator 16. Data-rate clock generator 16 divides the frequency of the chip-rate clock pulses by a factor 64 and supplies a 4-kbps data-rate clock pulse to a multiplexer 10 in which 4-kbps transmit data is multiplexed with frame sync codes. The multiplexed signal is applied to an M-ary PSK (phase-shift keyed) modulator 11 where it is digitally modulated upon a carrier. The output of PSK modulator 11 is coupled to an up-converter 12 in which the PSK-modulated signal is translated to a satellite's up-link frequency and passed through a high-power amplifier 13 and a diplexer 14 to the central station antenna 15 for transmission to the satellite transponder 30. A signal from each VSAT station is transmitted in burst (packet) form to transponder 30 and received at the central station by antenna 15 and applied through diplexer 14 and a low-noise amplifier 19 to a down-converter 20 where it is translated to a baseband frequency and applied to a correlator 21. Correlator 21 includes a tapped delay line 22 which is clocked by the chip-rate clock generator 18 to successively shift the PSK-modulated bit stream at the chip rate of 256 kbps. Successive taps of the delay line 22 are coupled respectively to multipliers 23-1 through 23-m which are respectively set to different values (+1 and -1) corresponding to the bits of a pseudorandom sequence with which the original packet data bits of each VSAT station have been modulo-2 summed, or "spread". The outputs of multipliers 23 are summed by an adder 24 for coupling to a PSK demodulator 25. The frame signal from central station 1 is retransmitted from transponder 30 in a broadcast mode to all VSATs. Each VSAT receives the broadcast signal by antenna 40 and applies it through a diplexer 41 and a low-noise amplifier 42 to a down-converter 43 in which it is translated to a baseband frequency. The output of down-converter 43 Is coupled to a PSK demodulator 44 to which a data-rate clock recovery circuit 45 is coupled to recover the data-rate clock pulse. The recovered data-rate clock is applied to a demultiplexer 52 to demultiplex the output of PSK demodulator into frame sync and data inserted on the timeslot assigned to the VSAT station. The output of data-rate clock recovery circuit 45 is applied to a chip-rate clock recovery circuit 46 which recovers the original 256-kbps chip-rate clock by multiplying the recovered data-rate clock frequency by a factor of 64. The output of chip-rate clock recovery circuit 46 is applied to a pseudorandom number (PN) sequence generator 47 to drive it at the chip-rate to produce a m-bit pseudorandom number sequence as specified for all VSATs of the satellite communication system. The output of PN sequence generator 47 is applied to one in put of an exclusive-OR gate 48. Transmit packet data is applied to the other input of exclusive-OR gate 48 in which each data bit is modulo-2 summed with the PM sequence. As illustrated schematically in Fig. 2, a portion of the packet data which is represented by a series of "10110" bits is modulo-2 summed with a PN sequence which is, for purposes of simplicity, shown as a sequence of "11010010" at a chip-clock rate eight times higher than the data bit rate. As a result of the modulo-2 summation, each data bit "1" of a packet is converted to a sequence of reversals of the 8-bit PN sequence and each data bit "0" is converted to a bit sequence having the same bit pattern as the 8-bit PN sequence. The spread bit stream is applied to a PSK modulator 49 where it is used to modulate a burst carrier, the modulated burst carrier being translated to an up-link frequency by an up-converter 50. After high-power amplification by amplifier 51, the up-link signal of the VSAT station is applied through diplexer 41 to antenna 40 for transmission to central station 1 via transponder 30. At the central station, the PSK-modulated carrier burst appears at the down-converter 20 and is entered into correlator 21 in which it is shifted at the chip-rate along the tapped delay line 22, successively multiplied by multipliers 23-1 through 23-m with the aforesaid pseudorandom values and the outputs of multipliers 23 are summed altogether by adder 24. Adder 24 produces a positive peak value corresponding to an original binary-1 data bit or a negative peak value corresponding to an original binary-0 data bit either when there is a match between the m-bit pattern of the bit-spread PSK-modulated signal and the bit pattern of the multipliers 23. Such peak values periodically occur at the data rate of 4 kbps and are demodulated into the original packet data by PSK demodulator 25. Since the chip-rate clock of each VSAT is synchronized with the 256-kbps reference clock of the central station, the bit-spread packet data from all VSAT stations are synchronized with that reference clock. Because of this synchronization, correlator 21 is able to detect the original data bit stream of each packet synchronously with the common chip-rate clock, thus eliminating the need for a high-speed chip-rate clock generator and complex hardware which would otherwise be required for quickly establishing synchronism with each incoming burst. Since the VSAT stations are located in different places, their round-trip propagation delays differ from each other to such a degree that a phase difference of less than one chip-clock interval occurs among the packets arriving at the central station. The embodiment of Fig. 3 eliminates the phase difference problem. The central station is provided with a polling circuit 66 which periodically sends a polling signal via transponder 30 to each VSAT station to elicit a response therefrom. A PSK demodulator 60 is connected to the output of down-converter 20 to receive and demodulate the central station's polling signal returning from transponder 30 and supplies it to a clock recovery circuit 61 where the data-rate clock component of the returning signal is detected and fed into a chip-rate clock recovery circuit 62. The latter recovers the chip-rate clock timing and applies it to a phase detector 63 as a reference phase. Another chip-rate clock recovery circuit 64 is connected to the output of PSK demodulator 25 to recover the chip-rate clock timing from a response signal sent from the polled VSAT station. The output of the chip-rate clock recovery circuit 64 is applied to phase detector 63 for comparison with the reference phase. Phase detector 63 generates a phase difference signal which corresponds to the deviation of the round-trip propagation delay of that given VSAT from that of the central station. A coded signal representing the detected phase difference is generated by a coder 65. By receiving a signal from polling circuit 66 identifying the polled VSAT, coder 65 supplies the coded phase-difference signal to multiplexer 10 so that it is transmitted on a timeslot assigned to the polled station. Each VSAT station is provided with a polling transceiver 67 and a decoder 68 both connected to demultiplexer 52. The polling signal from the central station is fed into polling transceiver 67. On receiving it, transceiver 67 applies a response signal to exclusive-OR gate 48 to cause it to be spread with the PN sequence for transmission to the central station. On the other hand, the coded phase-difference signal from the central station is demultiplexed and supplied to the decoder 68 of the polled VSAT station. A phase shifter 69 is connected between the output of chip-rate clock recovery circuit 46 and PN sequence generator 47, Phase shifter 69 receives the output of decoder 68 to introduce a delay to the chip-rate clock pulses by an amount corresponding to the round-trip propagation delay time difference of the own VSAT station with respect to the reference timing. Therefore, the chip-rate clock pulses of all VSAT stations are individually controlled at periodic intervals to compensate for their chip-rate phase timing differences. Fig. 4 shows a third embodiment of this invention. Before describing this embodiment, it is appropriate to describe the tolerant nature of the spread ALOHA system to interference when two packets are simultaneously transmitted from VSAT stations of different systems. Assume that VSAT station 72-1 sends a sequence of data bits A 1 (where i = 1, 2, 3 3 ...) and VSAT station 73-1 transmits data bits B l . The data bit of each VSAT station is spread with a pseudorandom bit sequence X 1 , X 2 , ...... X m so that their transmitted sequences are represented by A i X 1 , A l X 2 , ...... A i X m and B j X 1 , B j X 2 , ...... B j X m , It is further assumed that there is a collision between these spread bit sequences such that the sequence A i X 1 , A i X 2 , ...... A i X m overlaps (m - k) bits of the sequence B j X 1 , B j X 2 , ...... B j X m and k bits of the next sequence B j+1 X 1 , B j+1 X 2 , ...... B j+1 X m as shown in Fig. 5A (where k is in the range between 1 and m-1). Since the correlator of central station 71-1 is synchronized with the bit sequence A i X 1, A i X 2 , ...... A i X m , the following correlation output is generated by the correlator: The first term of Equation (1) corresponds to the component that is wanted and the second term corresponds to the component generated as a result of the interference. If the autocorrelation coefficient of the PN sequence X at delay time "i" is represented by C l , the latter is at a peak value if i = 0 and is much smaller than the peak value if i ≠ 0. For example, if the X sequence is a maximum length sequence, C i = m for i=0 and |C i | = 1 for i ≠ 0. By rearranging Equation (1) using the notation C i , the following Equations yield if B j = B j+1 : y(t) = A i C 0 + B j C k and if B j ≠ B j+1 : The second term of Equation (2) is significantly smaller than the first term of Equation (1), and therefore the data bit sequence A l can be correctly received. However, the second term of Equation (3) cannot be minimized. In order to minimize the second term of Equation (3), each VSAT station is provided with a pattern shifter 70 which supplies a control signal to PN sequence generator 47 for periodically and/or randomly recirculating its m-bit PN sequence by k bits. For example, if one VSAT station has the PN sequence of Fig. 2 (i.e.,"11010010"), the PN sequence of another VSAT station is recirculated as a sequence "10100101". A shift register 72 is connected to the data input of exclusive-OR gate 48 to store transmit packet data and forward it to exclusive-OR 48 in response to the output of data-rate clock recovery circuit 45. In this way, the transmit data bit timing of each VSAT station is synchronized with the other VSAT stations. The central station is provided with a correlator 73 having a tapped delay line 74 with twice as many delay units as those of the tapped delay line of the previous embodiments. Likewise, twice as many multipliers 75 l through 75 2m are provided as those of correlator 21 of the previous embodiments. Multipliers 75 l through 75 2m are equally divided into a first group of multipliers 75 l to 75 m and a second group of multipliers 75 m+1 to 75 2m and the multipliers of each group are set with the same PN sequence X 1 , X 2 , ........X m . Assume that there is a collision between the bit sequence A i X 1 , A i X 2 , ........A i X m from VSAT 2-1 and a bit sequence B i X 1+k , B j X 2+k , .... B j X m , .... B j X k from VSAT 2-2. Since the bit sequence B i is displaced by k bits with respect to the bit sequence A i , and the data bit timing of both packets is aligned with each other as shown in Fig. 5B, bit sequence A i matches its PN sequence which is set to multipliers 75 1 to 75 m . Correlator 73 produces an output signal z(t) from adder 76 for the bit sequence A l which is given as follows: Since z(t) is equal to y(t) of Equation (2), the interference caused by colliding packets can be held to a minimum and the bit sequence A l can be correctly received. Following the detection of bit sequence A i , bit sequence B j matches its PN sequence which is set to multipliers 75 1+k to 75 m+k . While mention has been made of embodiments in which each data bit is spread with an m-bit PN sequence whose clock rate is higher than the data clock rate, the present invention could equally be as well employed for applications in which the binary levels of the whole data bits of each packet are randomly reversed or not depending on the binary level of each bit of a spreading PN bit sequence using a chip-clock rate lower than the data-rate clock. As illustrated in Fig. 6, the central station is provided with a time base 80 to supply reference clock pulses to a chip-rate clock generator 81 as well as to data-rate clock generator 16. Chip-rate clock generator 81 converts the frequency of the reference clock to a lower frequency corresponding to the slot timing of the frame signal and causes correlator 21 to be synchronized with the time-slot frequency. On the other hand, each VSAT station has a chip-rate clock recovery circuit 82 which receives frame sync from demultiplexer 52 to recover the original chip-rate clock for driving a PN sequence generator 83 at the chip-rate, i.e., the time-slot frequency. The PN sequence is a maximum length sequence with a period covering a plurality of time slots. Fig. 7 shows only a portion of the PN sequence. This PN sequence is modulo-2 summed by exclusive-OR gate 48 with transmit data bits to produce packet-spread data bits as shown in Fig. 7. The foregoing description shows only preferred embodiments of the present invention. Various modifications are apparent to those skilled in the art without departing from the scope of the present invention which is only limited by the appended claims. Therefore, the embodiments shown and described are only illustrative, not restrictive.

Claims: A satellite packet communication system comprising a central station (1) and a plurality of terminal stations (2), a) wherein the central station (1) includes a1) clock pulse generating means (16,18) for generating chip-rate clock pulses and generating data-rate clock pulses from the chip-rate clock pulses, a2) up-converter means (11,12,13) for transmitting a series of data on timeslots of a frame to a satellite transponder (30), down-converter means (19,20) for receiving a carrier burst via said transponder, a3) correlator means (21;73) connected to said down-converter (19,20) for detecting correlations between pseudorandomly modulated data bits of a received carrier burst and a sequence of pseudorandom numbers, and a4) a digital demodulator (25) connected to said correlator means (21;73) for demodulating the detected correlations to generate a replica of packetized data bits, and b) wherein each of said terminal stations (2) includes b1) down-converter means (42,43,44) for receiving said frame from said transponder, b2) clock recovery means (45,46) for recovering chip-rate clock pulse from the received frame, b3) a pseudorandom number (PN) sequence generator (47) synchronized to the recovered chip-rate clock pulses for generating bits of a PN sequence, b4) pseudorandom modulator (48) connected to said PN sequence generator (47) for pseudorandomly modulating packetized data bits with said PN sequence bits, b5) a digital modulator (49) connected to the pseudorandom modulator (48) for modulating the pseudorandomly modulated packetized data bits upon a burst carrier for transmission to said transponder (30), and b6) up-converter means (50,51) for transmitting a modulated carrier burst to said transponder, characterized c) in that said central station (1) includes a multiplexer (10) for multiplexing the data-rate clock pulses with said data, d) in that said correlator means (21;73) of the central station is synchronized to the chip-rate clock pulses generated by said clock pulse generating means (18) for detecting said correlations, and e) in that said clock recovery means (45,46) of each of said terminal stations includes e1) data-rate clock recovery means (45) for detecting the data-rate clock pulses multiplexed with said transmitted data, and e2) chip-rate clock recovery means (46) for recovering said chip-rate clock pulses from the data-rate clock pulses detected by the data-rate clock recovery means (45). A system as claimed in claim 1, characterized in that the central station (1) comprises: a) a data-rate clock recovery circuit (61) for recovering chip-rate clock pulses from the carrier burst from each terminal station; b) a first chip-rate clock recovery circuit (62) for recovering chip-rate clock pulses from the recovered data-rate clock pulses; c) a second chip-rate clock recovery circuit (64) for recovering chip-rate clock pulses from an output signal of said correlator means (21); d) means (63) for detecting a phase difference between the chip-rate clock pulses recovered by said first chip-rate clock recovery circuit (62) and the chip-rate clock pulses recovered by said second chip-rate clock recovery circuit (64) and transmitting a signal representative of the detected phase difference on a timeslot to said transponder (30), e) in that each of said terminal stations includes means (52,68,69) for receiving said phase-difference signal on an assigned timeslot and controlling the phase timing said PN sequence generator (47) according to said phase-difference signal. A system as claimed in claim 2, characterized a) in that said central station (1) further includes a polling transmitter (66) for periodically transmitting a polling signal to each of said terminal stations (2) via said transponder, b) in that each of said terminal stations (2) includes a polling transceiver (67) for receiving the polling signal addressed to the terminal station and applying a return signal to said pseudorandomly modulating means (48) for transmission to said central station as a response to said addressed polling signal, and c) in that the data-rate clock recovery circuit (61) receives said polling signal to derive said data-rate clock pulses. A system as claimed in claim 1, 2 or 3, characterized in that the PN sequence of each terminal station is an m-bit sequence, and each terminal station provides a burst transmission on a random basis and comprises: means (70) for recirculating the PN sequence generator (47) by k-bits, where k is in the range between 1 and m - 1 and the integer k is unique to each of the terminal stations; and means (72) for causing said packetized data bits to synchronize with said recovered data-bit clock pulses, in that said correlator means (73) of the central station includes: a tapped delay line (74) clocked with the chip-rate clock pulse generated by said clock recovery means (18) for receiving an output signal of said down-converter means (19,20); 2 x m multipliers (75) respectively coupled to successive taps of said tapped delay line, said multipliers being divided into a first group of m pseudorandom numbers and a second group of m pseudorandom numbers; and an adder (76) for summing output signals of 2 x m multipliers to produce a summed output as said correlations.

Inventors: ENDO SHOJI, IWASAKI MOTOYA, KACHI SEIJI, KONO SHINICHI, OTANI SUSUMU, ENDO, SHOJI, IWASAKI, MOTOYA, KACHI, SEIJI, KONO, SHINICHI, OTANI, SUSUMU
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: H04L12
IPC codes: H04B7