Control device for radio communication apparatus

Abstract: Disclosed herein is a control device which is suitable for use in a radio communication apparatus employed in a radio communication system using a TDMA method. A timer circuit (20) for circulating a counted value in a period corresponding to a period of time required to transmit a TDMA frame supplies the counted value to a strobe signal generating circuit (31 - 3n). The strobe signal generating circuit (31 - 3n) supplies a strobe signal (STB) to a radio unit of the radio communication apparatus when a preset value coincides with the counted value of the timer circuit (20). Thus, since the strobe signal is generated without the intervention by a control circuit made up of a CPU (10) or the like, it can be output in strict timing.

Description: This invention relates to a control device suitable for use in a radio communication apparatus employed in a radio communication system using a time-division multiple access method. FIG. 1 is a block diagram showing the structure of a mobile station using a mobile radiotelephone system as a conventional radio communication apparatus, which is disclosed in, for example, the technical journal issued by Mitsubishi Electric Corp., Vol. 60, No. 10, p.p. 55-59, 1986. In the same drawing, there are shown a transmitting and receiving antenna 1, an antenna sharing unit 2 provided to transmit waves and receive them by a single antenna, a transmitting unit 3 for performing modulation and amplification of a transmission signal, a frequency synthesizer 4 for oscillating necessary frequencies, a receiving unit 5 for demodulating signals in a predetermined band, a control unit 6 for controlling respective units, a base-band signal processing unit 7 for processing sound signals, a microphone 8, and a speaker 9. FIG. 2 is a block diagram showing the structure of the control unit 6 constructed by a microcomputer. In the same drawing, there are shown a CPU 10, a RAM 11 from which data are read and in which the data are written, a ROM 12 in which a program is stored, a timer circuit 13, input/output ports (hereinafter called "I/O ports") 141 to 146 for interfacing to the outside, and a bus 16. The operation of the control unit 6 will now be described. The CPU 10 is operated in accordance with the program stored in the ROM 12. More specifically, the CPU 10 supplies necessary control signals to the transmitting unit 3, the frequency synthesizer 4, the receiving unit 5 (these are collectively called "a radio unit", and a unit, which is related to the transmission, in the radio unit will hereinafter called "a radio transmitting unit"), and the base-band signal processing unit 7 through the I/O ports 141 to 146, and receives necessary information from them. When the time control is required while they are being controlled by the CPU 10, the CPU 10 causes the timer circuit 13 to produce a timer interrupt signal thereby performing the real-time control in accordance with the timer interrupt signal. When it is desired to treat a transmitting-unit start signal (hereinafter called "TXON") for example, output ports each of which has been allotted to the TXON are rendered active during a predetermined period of time after radio channels are allotted. As soon as the radio communication is terminated, the output ports are thereafter rendered inactive during the predetermined period of time. The CPU 10 supplies the control signals such as TXON, etc. to the radio unit through the I/O ports 141 to 146 in the above-described manner. Thus, when the radio communication is made in accordance with a frequency division multiple access system (hereinafter called "FDMA system"), the operation of the radio unit is made regularly and hence the radio unit is activated without any problem under the above control of the CPU 10. However, when the radio communication is carried out in accordance with a time division multiple access system (hereinafter called "TDMA system") like, for example, the following mobile radiotelephone system (standard number IS-54) which has been discussed at the TIA in U.S.A., the operation of the radio communication apparatus is made intermittently. More specifically, as shown in FIG. 3, the transmission and reception must be performed only with respect to time slots allotted in one TDMA frame. FIG. 3 shows one example in which tri-multiple TDMA system is adopted. Therefore, if the TXON is taken as an example, it is necessary to output a TXON according to the time slots allotted in the TDMA frame as shown in FIG. 4. The control device suitable for use in the conventional radio communication apparatus (hereinafter called merely "control device") is constructed as described above. Therefore, the control device is accompanied by the problem that since the CPU 10 directly performs the input/output control of the control signal, the control signal required to be inputted and/or outputted in the form of a microsecond order cannot be inputted and/or outputted in the accurate timing even when the timer interrupt operations are often used where the radio communication is made by the TDMA system. Even when the control device activated at high speed as the CPU 10 or other peripheral circuit is used, a problem arises in that the power consumption is increased and the control device becomes expensive. SUMMARY OF THE INVENTION With the foregoing problems in view, it is therefore an object of the present invention to provide a versatile control device capable of processing a control signal in accurate timing even when the radio communication is made in accordance with a TDMA system and capable of easily carrying out a change in setting of the input/output timing of the control signal. It is another object of the present invention to provide a control device which can easily realize the timing control in a transmission system hard to control. According to one aspect of the present invention, there is provided a control device suitable for use in a mobile radio communication apparatus, comprising a timer circuit, for counting clock signals supplied by a master clock. This circuit continuously outputs the timer count value over a period defined by a predetermined number, which corresponds to one TDMA frame, of master clock signals. The timer circuit also provides a means for changing a preset timing value which changes the period or phase of the TDMA frame. The timer circuit further comprises a strobe signal generating circuit, which compares the timer count value of the timer circuit with said preset timing value. The strobe signal generating circuit is adapted to then output a strobe signal to a radio transceiver unit, when the values from the timer circuit and the preset timing value coincide. Further, a control circuit controls the preset timing value to change this value, which is supplied to the strobe signal generating circuit. The above and other objects, features and advantages of the present invention will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings in which preferred embodiments of the present invention are shown by way of illustrative example. The present invention is defined by Claims 1 to 21. Claims 1 to 11 relate to a:control device suitable for use in a radio communication apparatus, comprising; a timer circuit for counting clock signals supplied by a master clock (CK) and for continuously outputting the timer counter value over a period defined by a predetermined number of master clock signals; a control circuit for supplying the predetermined number of master clock signals to the timer circuit. The strobe signal generating circuit is provided for comparing the timer count value of the timer circuit with a preset timing value, the generating circuit adapted to output a strobe signal to a radio transceiver unit when the values coincide and the control circuit is adapted to supply the preset time value to the at least one comparing circuit. Claim 12 relates to a mobile radio communication station comprising as a radio unit, a transmitting unit for modulating, amplifying and transmitting data at a predetermined timing and a receiving unit for receiving data from a base station at a predetermined timing, the mobile station including the control device of any one of the Claims 1 to 11, wherein the generated strobe signals define the predetermined timings. FIG. 1 is a block diagram showing a mobile station using a mobile radiotelephone system; FIG. 2 is a block diagram depicting a conventional control device; FIG. 3 is a diagram for describing one example of a TDMA frame; FIG. 4 is a timing chart showing one example of the timing of a TXON; FIG. 5 is a block diagram illustrating a control device according to a first embodiment of the present invention; FIG. 6 is a timing chart showing the relationship between strobe signals and counted values; FIG. 7 is a block diagram depicting the structure of a timer circuit; FIG. 8 is a diagram illustrating the structure of a comparing circuit; FIG. 9 is a diagram showing a circuit used to change the pulse width of a strobe signal; FIG. 10 is a timing chart showing the relationship between strobe signals and an output of a flip-flop; FIG. 11 is diagram depicting another circuit used to change the pulse width of a strobe signal; FIG. 12 is a timing chart showing the relationship between an output of a counter circuit and an output of a flip-flop; FIG. 13 is a diagram illustrating the structure of a circuit used to output serial data therefrom; FIG. 14 is a block diagram showing a control device according to a second embodiment of the present invention; FIG. 15 is a diagram depicting the structure of a data updating circuit; FIG. 16 is a block diagram showing a control device according to a third embodiment of the present invention; FIG. 17 is a block diagram illustrating a control device according to a fourth embodiment of the present invention; FIG. 18 is a timing chart showing the relationship between a transmission start signal and an operation signal of a CPU; FIG. 19 is a timing chart for describing the propagation delay time; FIG. 20 is a block diagram showing a control device according to a fifth embodiment of the present invention; FIG. 21 is a block diagram depicting the structure of a comparing circuit; FIG. 22 is a block diagram showing the structure of a second timer circuit; FIG. 23 is a block diagram depicting the structure of a second strobe circuit; FIG. 24 is a block diagram showing a control device according to a sixth embodiment of the present invention; and FIG. 25 is a block diagram illustrating a control device according to a seventh embodiment of the present invention. A control device according to one embodiment of the present invention will hereinafter be described with reference to the accompanying drawings. In FIG. 5, there are shown a timer circuit 20 which serves to restore a counted value (value counted by a timer, i.e., timer count value) to an initial value during a period corresponding to a TDMA frame, an input line 22 for a base-band master clock (hereinafter called "master clock"), a supply line 24 for the timer count value, comparing circuits 31 to 3n used to output strobe signals therefrom respectively, and strobe output lines 41 to 4n used to output strobe signal (STB) therefrom respectively. The other components of the control device are denoted by identical reference numerals and identical to those of a conventional control device shown in FIG. 2. However, a program stored in a ROM 12 shown in FIG. 5 is different from that stored in a ROM 12 shown in FIG. 2. Incidentally, the control device according to the present embodiment is provided only with I/O ports 141, 142 each of which pass a signal not required to have the strict timing control. In the present embodiment, a strobe signal generating circuit is structurally realized by the comparing circuits 31 to 3n. A control circuit is constructed so as to be activated in accordance with a program in a CPU 10 and the ROM 12, which is different from a conventional program. Incidentally, it is only necessary to provide one comparing circuit where a strobe signal required for a radio unit may be one. FIG. 7 is a block diagram showing the structure of one example of the timer circuit 20. In the same drawing, there are shown an initial value register 202 which is connected to a bus 16 and serves to temporarily store an initial value supplied from the CPU 10, and a timer counter 204 which serves to count the number of the master clocks. FIG. 8 is a block diagram depicting the structure of one example of the comparing circuit 31. In the same drawing, there are shown an input register 302 connected to the bus 16 and supplied with a value set by the CPU 10, an output register 304 for outputting a preset value therefrom, a latch circuit 306 for latching a value counted by the timer counter 204, a comparator 308 for making a comparison between the preset value outputted from the output register 304 and the value stored in the latch circuit 306, and an output latch circuit 310 for synchronizing a coincidence detection pulse outputted from the comparator 308 with the master clock. Incidentally, the remaining comparing circuits 32 to 3n are structurally identical to the comparing circuit 31. Next, operation of the control device will now be described below. First of all, the CPU 10 initializes in the following manner. Namely, the CPU 10 sets an initial value corresponding to a value obtained by dividing one frame time of a TDMA frame by a period of the master clocks to the initial value register 202 of the timer circuit 20. The CUP 10 also establishes preset values according to various pieces of strobe timing required for the radio unit to the input register 302 of each of the comparing circuits 31 to 3n. Hereafter, the CPU 10 does not participate in the occurrence of strobe signals in the case other than the case where the change in the strobe timing, and the like are required. The timer counter 204 of the timer circuit 20 counts the number of the master clocks so as to count up, thereby generating a carry signal. Then, the initial value stored in the initial value register 202 is loaded into the timer counter 204 based on the carry signal. Hereafter, the timer counter 204 is repeatedly activated in such a manner that it starts counting from the initial value so as to count up, thereby generating the carry signal. The period for the generation of the carry signal is therefore equal to the period of the TDMA frame. In other words, in this case, the initial value corresponds to a value set such that the difference between the initial value and the counted-up value becomes a value obtained by dividing one frame time of the TDMA frame by the period of the master clocks. The carry signal also corresponds to a frame interrupt signal (INT) relative to the CPU 10. Each value counted by the timer counter 204 is outputted to the supply line 24 at all times. Thus, such a counted value is supplied to each of the comparing circuits 31 to 3n. In each of the comparing circuits 31 to 3n, the preset value in the input register 302 is delivered to the output register 304 in accordance with the frame interrupt signal. Therefore, the comparator 308 can compare the preset value and the counted value stored in the latch circuit 306. Then, the comparator 308 outputs a coincidence detection signal when they coincide with each other. The output latch circuit 310 latches the coincidence detection signal in response to the master clocks. Then, the output latch circuit 310 supplies an output thereof as a strobe signal to the radio unit. FIG. 6 shows the relationship between the counted value and the strobe signal at the time that "3" is set to the comparing circuit 31 and "10" is set to the comparing circuit 32. The strobe signal is used for the timing control required for the radio unit. When n comparing circuits 31 to 3n are provided by way of example, n kinds of strobe signals are supplied to the radio unit. As is apparent from the above description, each of the strobe signals is also generated in the same period as that of the TDMA frame. Incidentally, when it is required to provide a signal of the pulse width longer than that of the strobe signal, a RS flip-flop (FF) 50 may be provided in the following stage of the output latch circuit 310, as shown in FIG. 9. Thus, the signal having widened pulse width such as shown in FIG. 10 can be created. The timing period and pulse width of this signal are set to desired values respectively by controlling the preset values of the comparing circuits 31 to 3n, which correspond to two strobe signals used as inputs to the FF 50. It is also easy to change the timing for generating each strobe signal. More specifically, when a TDMA frame immediately before a TDMA frame received at the time the change in the timing is required is being received, the CPU 10 may set a changed preset value to the input register 302 of each of the comparing circuits 31 to 3n. If such setting is performed, a new preset value is set to the output register 304 when the following frame interrupt signal is outputted, and hence the timing for generating each strobe signal is changed. It is also easy to perform the adjustment of or the change in the phase of the TDMA frame, i.e., to shift the timing for generating the frame interrupt signal. In other words, the initial value supplied to the timer circuit 20 is set to a value corresponding to the quantity of the phase which one desires to shift, and the normal initial value may be given again to the timer circuit 20 when the frame interrupt signal is outputted. Now, a description has been made in the case where the two strobe signals have been used to generate the signal having the long pulse width. However, a counter circuit 51 may be used for the same purpose as referred to above. As shown in FIG. 11 by way of example, the CPU 10 sets count values K each corresponding to the pulse width to the counter circuit 51. As shown in Fig. 12, the CPU 10 starts to count down taking a strobe signal n as the trigger, and resets the FF 50 in response to a borrow signal. Thus, the signal having the pulse width corresponding to each count value K is produced. Incidentally, each count value K is stored inside the counter circuit 51 and loaded into a counting portion of the counter circuit 51 based on the frame interrupt signal. When it is required to transmit serial data as in the case of setting up the frequency with respect to a frequency synthesizer in the radio unit, a register 52 in which data are to be set in advance and an output circuit 54 shown in FIG. 13 may be provided in a stage after the output latch circuit 310. In this case, the CPU 10 sets prescribed data to the register 52, and the output circuit 54 receives data from the register 52 taking the strobe signal as the trigger and then outputs the prescribed data as serial data in synchronism with the master clocks. In addition, the output circuit 54 serves to make an enable signal active while the serial data is being outputted. Thus, desired serial data can be outputted to the radio unit. Further, the provision of such two circuits, i.e., the register 52 and the output circuit 54 makes it easy to monitor other channels other than channels within the TDMA frame itself. FIG. 14 is a block diagram showing a control device according to a second embodiment of this invention. In the same drawing, there are shown a comparing circuit 30 for comparing a counted value and a preset value, a data updating circuit 60 which enables to bring a plurality of preset values up to data, and a selection circuit 62 adapted to output strobe signals to predetermined strobe output lines 41 to 4n, respectively. In this case, a strobe signal generating circuit comprises the comparing circuit 30, the data updating circuit 60 and the selection circuit 62. Incidentally, designated at numeral 61 is a coincidence detection pulse outputted from the comparing circuit 30. FIG. 15 is a diagram showing one example of the structure of the data updating circuit 60. In the same drawing, designated at numeral 64 is a write control circuit connected to the bus 16 and for receiving necessary data from the CPU 10 to write the same into a RAM 66, and numeral 68 indicates a read control circuit for applying necessary data to the comparing circuit 30 and the selection circuit 62 in response to the coincidence detection pulse 61. Next, operation of the control device will now be described. Upon establishing an initial condition, the CPU 10 supplies preset values used to produce the timing for generating a necessary strobe signal and information representing the output destination of strobe signals corresponding to these preset values to the data updating circuit 60 in order of the strobe-signal generating timing. As a consequence, the write control circuit 64 writes the preset values and the information indicative of the output destination of the strobe signals into the RAM 66. The comparing circuit 30 is constructed as shown in FIG. 8 by way of example. However, the preset values in the input register 302 are immediately transferred to the output register 304 in this case. The read control circuit 68 supplies a first preset value to the comparing circuit 30 in response to the frame interrupt signal, and also supplies first information to the selection circuit 62. As a consequence, the comparing circuit 30 compares the first preset value and the value counted by the timer circuit 20, and then outputs the coincidence detection pulse 61 to the selection circuit 62 and the read control circuit 68 when the first value and the counted value coincide with each other. The selection circuit 62 selects any one of the strobe signal output lines 41 to 4n, which is indicative of the first information, and then outputs a strobe signal to the selected one of the strobe signal output lines 41 to 4n. On the other hand, the read control circuit 68 supplies the following preset value to the comparing circuit 30 in response to the coincidence detection pulse 61, and gives information corresponding to that preset value to the selection circuit 62. Hereafter, this operation is repeatedly performed, so that a necessary number of strobe signals are outputted from the selection circuit 62. The period of each strobe signal corresponds to that of the TDMA frame. Incidentally, the above-described embodiments have shown and described a mobile station. However, the embodiments described above can also be applied to a base station by fixing a setting in a transmit-receive periodic counter and providing strobe signal generating circuits by the number corresponding to a plurality of channels. When the mobile station is moved at high speed, the synchronous shift in the receiving timing takes place. However, the synchronous shift can be corrected by providing a circuit for detecting the receiving timing, which is shown in FIG. 16. A control device shown in FIG. 16 according to a third embodiment is additionally provided with a unique word detecting circuit 112 and a latch circuit 114. The unique word detecting circuit 112 is supplied with a desired one of strobe signals. The desired one strobe signal is equivalent to a signal indicative of a reference timing signal at that time. First of all, the unique word detecting circuit 112 starts its operation based on a detection command from the CPU 10. Then, the unique word detecting circuit 112 detects a unique word based on received data and a reception/regeneration clock in response to the reference timing signal. The unique word detecting circuit 112 outputs a detection pulse when the unique word is detected. This detection pulse is given to the latch circuit 114 supplied with the value counted by the timer circuit 20. The latch circuit 114 latches the counted value introduced from the timer circuit 20 in response to the detection pulse. Then, the CPU 10 reads out the value stored in the latch circuit 114. As a consequence, the receiving synchronous timing for each TDMA frame can be detected from the value thus read. The CPU 10 performs the moving average processing or the like based on the receiving synchronous timing of each TDMA frame, thereby making it possible to detect the synchronous shift in the receiving timing. The CPU 10 sets a value corresponding to the quantity of the shift thus detected to the timer circuit 20, and thereafter resets the initial value, thereby making it possible to correct the receiving timing. In the control device employed in each of the above-described embodiments, a request for the frame interrupt for each TDMA frame is made to the CPU 10 even in the case of the intermittent receiving operation. It is therefore necessary to activate the CPU 10 even when the receiving processing is unnecessary, and hence excess power consumption is made. A control device shown in FIG. 17 according to a fourth embodiment can overcome the problem referred to above. In this case, the control device is provided with a frame-number counter 122 for counting the number of received TDMA frames, an active frame detector 124 and a gate circuit 126. More specifically, a carry signal outputted from the timer circuit 20 is not used as a frame interrupt signal but used as a frame pulse (FP), and this frame pulse is then inputted to the frame-number counter 122. The frame-number counter 122 is a counter of such a type that the number of TDMA frames representing a super frame is set equal to one complete cycle. For example, when the super frame is composed of twelve TDMA frames, the count values circulate among "0" to "11". The active frame detector 124 is informed of data indicative of TDMA frame's numbers to be received, by the CPU 10 in advance. Thus, the active frame detector 124 compares a value counted by the frame-number counter 122 with data indicative of a set number, and outputs a receiving start signal while they coincide with each other. The receiving start signal is used as a gate signal for the gate circuit 126. The gate circuit 126 serves to output a frame pulse as the frame interrupt signal to the CPU 10 only during the period in which the receiving start signal is being rendered active. FIG. 18 shows the manner in which respective signals are produced at the time that three TDMA frames in the super frame are intermittently received. If the frame interrupt signal is generated only when the receiving operation is required, the CPU 10 can be brought into an inactivated state and the power consumption of the control device can be rendered low when the receiving operation is not required. Meanwhile, the propagation delay time ta occurs in the transfer of a signal between the base station and the mobile station as shown in FIG. 19. When the communication between the base and mobile stations is performed in the form of a TDMA system, it is necessary to compensate for the propagation delay time ta and output a transmission signal from the mobile station. FIG. 20 is a block diagram showing a control device according to a fifth embodiment of the present invention, which can compensate for the propagation delay time. In the same drawing, there are shown a first strobe signal generating circuit 3 for generating a strobe signal (RXSTB) to be supplied to a radio receiving unit, a comparing circuit 70 for comparing a timing correction value supplied from the CPU 10 and a value counted by a timer circuit (first timer circuit) 20, a second timer circuit 80 for making a start in the counting of the number of master clocks in synchronism with a trigger signal, and a second strobe signal generating circuit 90 for generating a strobe signal (TXSTB) to be supplied to a radio transmitting unit. Designated at numerals 91 to 9m are strobe-signal output lines connected to the radio transmitting unit. Incidentally, the strobe signal generating circuit (corresponding to one shown in FIG. 5 or FIG. 14) employed in the first embodiment or the second embodiment can be adopted in structure as each of the first strobe signal generating circuit 3 and the second strobe signal generating circuit 90 as it is. FIG. 21 is a block diagram showing one example of the structure of the comparing circuit 70. In the same drawing, there are shown an input register 702 connected to the bus 16 and in which the timing correction value is set by the CPU 10, an output register 704 for outputting the timing correction value therefrom, a latch circuit 706 for latching the value counted by the timer circuit 20, a comparator 708 for comparing the timing correction value outputted from the output register 704 and the value stored in the latch circuit 706, and an output latch circuit 710 for synchronizing a trigger signal outputted from the comparator 708 with the master clock. Incidentally, designated at numeral 709 is a trigger signal supplied to the second timer circuit 80. FIG. 22 is a block diagram showing one example of the structure of the second timer circuit 80. In the same drawing, there are shown an initial value register 802 connected to the bus 16 and for temporarily storing an initial value supplied from the CPU 10, and a timer counter 804 for counting the number of the master clocks. Next, operations of the circuits other than the timer circuit 20 and the first strobe signal generating circuit 3 will now be described. The operation of each of both the timer circuit 20 and the first strobe signal generating circuit 3 is identical to that of each of those employed in the first and second embodiments, and its description will therefore be omitted. In this case, the CPU 10 sets the comparing circuit 70, the second timer circuit 80 and the second strobe signal generating circuit 90 to their associated initial values upon establishing an initial condition. More specifically, a timing correction value created based on the amount of correction of the transmission timing designated by the base station is given to the comparing circuit 70. An initial value of, for example, "0000" is applied to the second timer circuit 80, and respective preset values (respective preset values for transmission) for generating respective strobe signals are supplied to the second strobe signal generating circuit 90. When the structure of the strobe signal generating circuit shown in FIG. 5 is adopted as that of the second strobe signal generating circuit 90, the second strobe signal generating circuit 90 is constructed as shown in FIG. 23. Thus, the respective comparing circuits 911 to 91m are structurally identical to those illustrated in FIG.8. In addition, the respective preset values are given to the respective comparing circuits 911 to 91m. Incidentally, one comparing circuit may be provided where only one strobe signal is required. In the comparing circuit 70, the timing correction value set in the input register 702 is transferred to the output register 704 based on the frame interrupt signal. As a consequence, the comparator 708 compares the timing correction value and the counted value of the first timer circuit 20, which is stored in the latch circuit 706. When they coincide with each other, the comparator 708 outputs a trigger signal through the output latch circuit 710. Accordingly, the timing correction value set by the CPU 10 is a value set in such a manner that (timing correction value - initial value of the first timer circuit 20) x (period of the master clock) becomes a correction value for the transmission timing. In the second timer circuit 80, the timer counter 804 takes in or receives a value stored in the initial value register 802 in response to the trigger signal so as to start counting. When the initial value is "0000", the timer counter 804 counts up from "0000". The counted value thereof is outputted to the second strobe signal generating circuit 90. Hereafter, the comparing circuit 70 outputs a trigger signal in the same period as that of the TDMA frame, and the counted value of the second timer circuit 80 is restored to "0000" according to the trigger signal. Incidentally, the comparing circuit 70 outputs a trigger signal only one time after the timing correction value is set by the CPU 10. The second timer circuit 80 is triggered by the trigger signal. Hereafter, the second timer circuit 80 itself may reload the initial value in the same manner as the first timer circuit 20. Then, the respective comparing circuits 911 to 91m of the second strobe signal generating 90 each compare a value counted by the second timer circuit 80 and each of the preset values. When they coincide with each other, each of the comparing circuits 911 to 91m outputs a strobe signal. The strobe signal thus outputted is supplied to the radio transmitting unit. The radio transmitting unit performs timing control according to the so-supplied strobe signal. Thus, the radio transmitting unit can carry out the transmission control in the corrected transmission timing. When information about a change in the amount of correction of the transmission timing is transferred from the base station to the mobile station when in communication, the CPU 10 serves to set the changed timing correction value to the input register 702 of the comparing circuit 70 while a frame immediately before a TDMA frame required to be changed is being received. As a consequence, a new timing correction value is transferred to the output register 704 based on the following interrupt signal. It is therefore possible to carry out the transmission control in the new correction timing from the following TDMA frame. Even in this case, the circuits shown in FIG. 9 and 11 or one depicted in FIG. 13 may be provided at a stage after the second strobe signal generating circuit 90 so as to electrically process a strobe signal. Incidentally, when the mobile station is in motion at high speed, a synchronous shift occurs in the receiving timing. However, a circuit shown in FIG. 24 for detecting the receiving timing may be added so as to correct such a shift. The operation for effecting the correction of the shift is the same as that in the third embodiment shown in FIG. 16, and its description will therefore be omitted. If a frame-number counter 122, an active frame detector 124 and a gate circuit 126 are added as shown in FIG. 25, no frame interrupt signal is produced when a TDMA frame in the supper frame not required to be received is inputted, thus making it possible to activate the CPU 10 intermittently. The operation of each of the frame-number counter 122, the active frame detector 124 and the gate circuit 126 is identical to that of those employed in the fourth embodiment, and its description will therefore be omitted. According to the present invention, as has been described above, the control device is so constructed that a comparison is made between the output of the timer circuit in which the counted value circulates in accordance with the period of the TDMA frame and the preset value so as to produce the strobe signal. Therefore, the control device can bring about advantages that the timing control can be effected without the intervention of the control unit such as a CPU, and hence the real-time control is made possible, and the change in timing can easily be made. If the control device is so constructed that a comparison is made between the counted value obtained by shifting the counted value of the first timer circuit by the amount of correction of the transmission timing and the preset value so as to produce the strobe signal to be applied to the radio transmitting unit, the control device can also bring about advantages, as well as the above-described advantages, that the timing control in the transmission system can easily be realized and the change in timing in the same system can easily be performed.

Claims: A control device suitable for use in a mobile radio communication apparatus, comprising: a timer circuit (20) for counting clock signals supplied by a master clock (CK) and for continuously outputting the timer count value over a period defined by a predetermined number corresponding to one TDMA frame, of master clock signals, said timer circuit also being a means for changing a preset timing value for changing said period or a phase of said one TDMA frame, characterized in that it further comprises a strobe signal generating circuit (31 - 3n) for comparing the timer count value of said timer circuit (20) with said preset timing value, the generating circuit (31 - 3n) adapted to output a strobe signal (41 - 4n) to a radio transceiver unit (3, 4, 5) when the values coincide; and a control circuit (10) adapted to control said preset timing value to change the preset timing value to be supplied to the strobe signal generating circuit (31 - 3n). A control device of Claim 1, wherein said predetermined number of clock signals is obtained by dividing the time interval of one TDMA frame by the period of the clock signals. A control device according to Claim 1 or 2, wherein the strobe signal generating circuit is a comparing circuit (31) comprising an input register (302) for receiving said preset timing value from said control circuit (10), an output register (304) for receiving the timing value of said input register (302) in response to an interrupt signal (INT) output by said timer circuit (20) after having counted the predetermined number of master clocks, a latch circuit (306) for latching the timer count value of said timer circuit (20), a comparator (308) for comparing the timing values stored in said output register (304) and the latched value in said latch circuit (306) so as to output a coincidence detection signal when they coincide, and an output latch circuit (310) for latching said coincidence detection signal with said master clock signals so as to output said strobe signal (41 - 4n). A control device according to Claim 3, comprising a plurality of comparing circuits (31 - 3n) for comparing the timer count value from said timer circuit (20) with a plurality of preset timing values, respectively, so as to output a plurality of strobe signals (41 - 4n), the control circuit (10) being adapted to supply said plurality of preset timing values to said comparing circuits (31 - 3n). A control device according to one of Claims 1 to 4, further comprising pulse-width expanding means (50) for producing an output signal having a pulse width broader than that of the strobe signals (41 - 4n). A control device according to Claim 5, wherein said pulse-width expanding means include a flip-flop (50) set by one of two strobe signals (STBn) and reset by the other one (STBm). A control device according to Claim 5, wherein said pulse-width expanding means comprise a counter circuit (51) to which a count value corresponding to a pulse width is set, the counter circuit (51) starting the countdown taking one of said strobe signals (STB) as a trigger, and a flip-flop (50) set by said one strobe signal and reset by a borrow signal output from said counter circuit (51). A control device according to any one of the Claims 1 to 7, further comprising serial data outputting means (52, 54) for serially outputting predetermined data from the control circuit (10) said serial data outputting means including a register (52) for storing said predetermined data, and an output circuit (54) to receive said predetermined data in response to a strobe signal (STB) taken as the trigger, so as to output said predetermined data in synchronism with said master clock signals. A control device according to Claim 1 or 2, wherein said strobe signal generating circuit comprises a data updating circuit (60) which stores a plurality of preset timing values and information representing the output destination of each strobe signal in pairs, and which outputs one of said pairs in response to a coincidence detection signal (61), a comparing circuit (30) for comparing the timer count value of said timer circuit (20) and said preset timing value from said data updating circuit (60) so as to output said coincidence detection signal (61) when they coincide, and a selection circuit (62) for outputting a strobe signal (STB) in response to said coincidence detection signal (61) to the designated output destination. A control device according to one of Claims 1 to 9, further comprising correcting means (112, 114) for correcting a shift in the receiving timing of received data, said correcting means comprising a unique word detecting circuit (112) for detecting a unique word from the received data, and a latch circuit (114) for latching the timer count value of said timer circuit (20) with a detection signal from said unique word detecting circuit (112), the latched value supplied to said control circuit (10) as a correction value. A control device according to any one of Claims 1 to 9, further comprising a frame-number counter (122) for counting a frame pulse (FP) output when said timer circuit (20) counts the predetermined number of master clocks (CK) and for supplying values counted by said timer circuit (20) taking each value equal to the number of TDMA frames in a super frame as a period, an active frame detector (124) for outputting a receive start signal when the preset timing value coincides with one of said counted values, and a gate circuit (126) for passing said signal from said timer circuit (20) so as to be supplied to said control circuit (10) as a frame interrupt signal (INT) in response to said receive start signal from said active frame detector (124) taken as a gate signal. A mobile radio communication station comprising as a radio unit (3, 4, 5) a transmitting unit (3) for modulating, amplifying and transmitting data at a predetermined timing and a receiving unit (5) for receiving data from a base station at a predetermined timing, the mobile station including the control device of any one of the Claims 1 to 11, wherein the generated strobe signals (41 - 4n) define the predetermined timings.

Inventors: NONAMI TAKAYUKI, NONAMI, TAKAYUKI, Nonami, Takayuki, c/o Mitsubishi Denki K. K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1991
Main classification: H04J3
IPC codes: H04B7, H04L7, H04J3