Method of fabricating memory cell for semiconductor integrated circuit

Abstract: According to a method of fabricating a memory cell for a semiconductor integrated circuit, a lower electrode (6) having a predetermined shape is formed on a semiconductor layer. A first insulating interlayer (8) is formed on an entire surface of the semiconductor layer such that only a top surface of the lower electrode is exposed. A dielectric (10) having a high dielectric constant such as strontium titanate is formed on the lower electrode and on the semiconductor layer. An upper electrode (11) is formed on the dielectric having a high dielectric constant. The upper electrode constitutes a capacitor with the lower electrode through the dielectric.

Description: Background of the Invention The present invention relates to a method of fabricating a dynamic random access memory for a semiconductor integrated circuit and, more particularly, to a method of fabricating a capacitor of a memory cell having a structure in which the capacitor is formed after a bit line is formed. Conventionally, a memory cell of this type is constituted by a single MOS transistor and a capacitor having a stacked structure which is composed of a silicon oxide film and a silicon nitride film and has polysilicon as an electrode. A technique for forming this capacitor after formation of a bit line is described in, e.g., "International Electron Devices Meeting Digest of Technical Papers," 1988, PP. 592 - 595. In this technique, after polysilicon serving as a lower electrode is formed, formation of a silicon dioxide film and a silicon nitride film is performed by a thermal oxidation method and a CVD (Chemical Vapor Deposition) method, respectively. Thereafter, polysilicon serving as an upper electrode is stacked, thus completing the capacitor. In order for the above conventional memory cell to meet higher degrees of integration of recent integrated circuits, however, a reduction in the area of the capacitor must be compensated by decreasing the film thickness of a dielectric film and by effectively increasing the area by means of a three-dimensional structure, in which the capacitor is formed using the upper and side surfaces of the lower electrode. Since the dielectric film for forming the conventional capacitor consists of a silicon oxide film and a silicon nitride film, its dielectric constant is at most 7. Therefore, an extremely small film thickness (silicon oxide film) of 10 nm or less is necessary to realize the capacitor required. However, it is very difficult to form a dielectric thin film layer having a current-voltage characteristic lower than a permitted leakage current. In addition, in the method in which the electrode area is effectively increased by the three-dimensional structure, a leakage current is increased because the film thickness of a silicon oxide film is decreased or electric fields are concentrated at the end of the lower electrode. Furthermore, since the physical size of steps is increased by the three-dimensional structure, it becomes more difficult to form wiring without disconnections after the formation of the capacitor. This results in a reduction in yield. JAPANESE JOURNAL OF APPLIED PHYSICS; Supplements (18th Conference on Solid State Devices and Materials, Tokyo, 20th - 22nd August 1986), pages 257 - 260; K. Yamada:"Thermodynamical approach to a new high dielectric capacitor structure: W/HfO 2 /W" discloses a method of fabricating a memory cell comprising a lower electrode on a semiconductor layer, a first insulating interlayer on the entire surface of the semiconductor layer such that the only a top surface of the lower electrode is exposed, a dielectric having a high dielectric constant provided on the lower electrode and on the semiconductor layer, and an upper electrode provided on the dielectirc. The first insulating interlayer remains on the edges of the lower electrode. On the other hand, EP-A-0 338 157 discloses the use of strontium titanate as ferroelectric dielectric with a high dielectric constant. Summary of the Invention It is a principal object of the present invention to provide a method of fabricating a memory cell for a semiconductor integrated circuit, which can realize a higher degree of integration by decreasing the film thickness of a dielectric film in a capacitor. It is another object of the present invention to provide a method of fabricating a memory cell for a semiconductor integrated circuit, which can realize a dielectric thin film layer having a current-voltage characteristic lower than a predetermined leakage current. It is still another object of the present invention to provide a method of fabricating a memory cell for a semiconductor integrated circuit, which can realize a flat structure without decreasing the film thickness of a dielectric at the end of a lower electrode. It is still another object of the present invention to provide a method of fabricating a memory cell for a semiconductor integrated circuit, which can prevent a reduction in yield due to disconnections in wiring formed after a capacitor. In order to achieve the above objects of the present invention, there is provided a method of fabricating a memory cell for a semiconductor integrated circuit according to claim 1. Claim 2 is related to an adventageous aspect of the invention. Brief Description of the Drawings Figs. 1A to 1E are sectional views showing the steps in fabrication according to an embodiment of the present invention. Detailed Description of the Preferred Embodiment An embodiment of the present invention will be described below with reference to the accompanying drawings. Figs. 1A to 1E show the steps in fabrication according to this embodiment of the present invention. In this embodiment, after a bit line is formed, polysilicon, one or more types of barrier metals, a dielectric, and an upper electrode are stacked in sequence to fabricate a capacitor. In this case, after materials up to the barrier metal are formed as a lower electrode, an insulating interlayer is formed such that the top surface of the lower electrode is exposed. Thereafter, the dielectric having a high dielectric constant and the upper electrode are stacked sequentially to fabricate the capacitor. Referring to Fig. 1, reference numeral 1 denotes a word line corresponding to the gate of a transistor made of polysilicon; 2, a bit line of a memory cell; 3, diffusion layers corresponding to the source and the drain of the transistor; 4, a silicon substrate; 5, an insulating interlayer; 6, polysilicon serving as the lower electrode of the capacitor; 7, a barrier metal; 8, an insulating interlayer; 9, a photoresist; 10, strontium titanate; and 11, an upper electrode. Fig. 1A shows a section obtained after a transistor portion of the memory cell is formed in a semiconductor layer composed of the silicon substrate 4 and the insulating interlayer 5. Next, as shown in Fig. 1B, in order to form a lower electrode of the capacitor, a contact hole 5a reaching the diffusion layer is formed in the insulating interlayer 5 by well-known photolithography and plasma etching. Thereafter, the polysilicon 6 is formed by an LPCVD method, and phosphorus is diffused to decrease the resistance at that location to 13 to 100 Ω/□. Tantalum and platinum are stacked in sequence to have a thickness of 10 to 100 nm each, thus forming the barrier metal 7. Subsequently, as shown in Fig. 1C, the barrier metal 7 and the polysilicon 6 are formed into a predetermined shape as a lower electrode by photolithography and plasma etching. After the insulating interlayer is stacked, the photoresist 9 is coated. Thereafter, as shown in Fig. 1D, by means of plasma etching mainly using CF 4 gas in which the photoresist 9 and the insulating interlayer 8 are etched away at an equal etching rate, etching is performed until the surface of the barrier metal 7 is exposed to the same level as the insulating interlayer 8. Subsequently, as shown in Fig. 1E, the strontium titanate film 10 is stacked as a dielectric having a high dielectric constant to have a thickness of 50 to 200 nm by a radio-frequency sputtering method, and polysilicon is formed as the upper electrode 11 by the LPCVD method. Alternatively, after a dielectric is stacked to temporarily have a large thickness, etching back is performed to form a dielectric layer. Therefore, a flat structure can be realized without decreasing the film thickness of the dielectric at the edge of the lower electrode. In addition, a small leakage current makes it possible to realize a capacitor having a high capacitor density.

Claims: A method of fabricating a capacitor of a memory cell which consists of a MOS transistor and a capacitor for a semiconductor integrated circuit, comprising the steps of: a) forming a lower electrode (6, 7) having a predefined shape on a semiconductor layer (4, 5); b) forming a first insulating interlayer (8) on the entire surface of said semiconductor layer, the first insulating interlayer covering the lower electrode; c) forming a photoresist (9) on the entire surface of said first insulating interlayer (8); d) etching said photoresist (9) and said first insulating interlayer (8) at an equal etching rate so as to expose only the entire top surface of said lower electrode (6, 7) at the same level as the insulating interlaver (8); e) forming a strontium titanate dielectric (10) by radio-frequency sputtering method on said exposed top surface ot the lower electrode (7) and on said insulating layer; and f) forming an upper electrode (11) on said strontium titanate dielectric, said upper electrode constituting a capacitor with said lower electrode through said strontium titanate dielectric. A method according to claim 1, wherein said lower electrode consists of polysilicon (6) on top of which a barrier metal (7) is stacked, and said first insulating interlayer (9) is formed at the same level as said barrier metal (7).

Inventors: TOSHIYUKI SAKUMA, YOICHI MIYASAKA, TOSHIYUKI, SAKUMA, YOICHI, MIYASAKA, Toshiyuki, Sakuma, c/o NEC Corporation, Yoichi, Miyasaka, c/o NEC Corporation
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: H01L27
IPC codes: H01L27, H01L21