A semiconductor device comprising a TAB tape and its manufacturing method

Abstract: A plurality of electrode pads (14) are formed on a main surface of a semiconductor chip (11). The electrode pads (14) on the semiconductor chip (11) are electrically connected to the top end of the inner leads (19) through a metal plating layer (20). To connect the electrode pads (14) of the semiconductor chip (11) to the lead frame (53) formed of conductive material, there is provided a first connect section (54) where the lead frame (53) is electrically connected to an electrode (14) on the semiconductor chip (11) by a conductive adhesive, and a second connect section (55) where the lead frame (53) is electrically connected to the electode (14) on the semiconductor chip (11) by a metal plating to cover the surroundings of the first connect section (54).

Description: The present invention relates to a semiconductor device, in which an electrical connection between electrodes on a semiconductor chip and inner leads in a TAB tape is provided according to claim 1 and its manufacturing method according to claim 5. When the semiconductor device is manufactured, there are numerous portions where an electrical connection is to be provided such as a portion between an electrical pad on a semiconductor chip and an inner lead of a lead frame, and a portion between an outer lead of the lead frame and a wiring pattern on a print circuit board. Conventionally, for example, the electrical connection between the electrode pad on the semiconductor chip and the inner lead is made by a metal bonding such as a wire bonding using AU wire or Aℓ wire, a TAB (Tape Automated Bonding) method, an ohmic contact such as a metal contact between a bump electrode on a flip chip and a lead, and the like. Regarding the connection by the wiring bonding, the shortest distance between adjacent wires is restricted by the outer shape of a bonding capillary to be used. Due to this, it is difficult to reduce the distance between the pads on the semiconductor chip to be about 100 µm. Moreover, in order to connect an Au ball or an Aℓ wire to an aluminum pad on the semiconductor chip, it is necessary to apply a physical load such as heating, pressing, ultrasonic vibration. Therefore, damage is often applied to the semiconductor chip itself under the electrode pad. Such an approach is described in Patent Abstracts of Japan, vol. 12, no. 65 (E-586), JP-A-62 208 642, describing the mounting of a semiconductor device of the tape carrier type that is composed of a plastic film and a metallic lead terminal formed thereon with a through hole containing the film. The electrode terminal is aligned with the through hole and the semiconductor element with carrier films fixed thereon is immersed in a solder bath with ultrasonic and heat impression. Another approach is described in Patent Abstracts of Japan, vol. 14, no. 348 (E-957), JP-A-02 121 359, where the bonding strength connection between a lead and a conductor circuit and the electrical reliability thereof is improved by a method wherein a plating layer is continuously formed in one piece on the surface of a lead, and electrically conductive bonding agent, and a conductor circuit; here, the plating layer does not get into direct contact to an end portion of an inner lead wire. In the case where a TAB system or the flip chip is used, it is necessary to metal-connect an Au bump or a plating bump to the inner lead. Due to this, the temperature of the above case often increases above than that of the wire bonding connection, so that physical damage due to pressure remains. In this case, the distance between the pads can be reduced to about 80 µm, however, there is a limitation in the reduction of the bump size because of the use of the metal connection. Moreover, a large number of portions are connected at the same time. Due to this, as the number of portions to be connected is further increased, it is more difficult to obtain a stable connection in view of the height of the bump, and the condition of the connection. Due to this, it is required that the process conditions be stabilized. The above-mentioned problem occurs not only in the electrical connection between the pad on the semiconductor chip or the bump and the inner lead but also the electrical connection between the outer lead and the wiring pattern on the print circuit board. A typical example is given in Patent Abstracts of Japan, Vol. 14, No. 346 (E-956), JP-A-02 119 252, describing a hybrid integrated circuit device. Here, at least one or more semiconductor elements, active elements or passive elements are mounted on a circuit board and a resin substance which electrically connects a lead of a lead frame is used to bond and fix the circuit board to input/output terminals. A method for manufacturing a semiconductor device wherein the rusting of a cap section is prevented by plating a welding ring and a cap set are seam-welded with nickel, is described in Patent Abstracts of Japan, Vol. 9, No. 240 (E-345), JP-A-60 092 636. Further, Patent Abstracts of Japan, Vol. 14, No. 502 (E-997), JP-A-02 208 957 describes the use of a metal plating for the connection of a cap and a case of a semiconductor device. Patent Abstracts of Japan, Vol. 13, No. 513 (E-847) and JP-A-1 207 938 teaches to eliminate bump electrodes of a semiconductor chip and make handling of the semiconductor chip easy by a method wherein external circuit connection electrodes are provided on the electrode pads of the semiconductor chip and an insulating film carrier with leads whose tips are arranged at the circumferences of apertures are also provided. The electrodes and leads are connected to each other with a conductive paste. An object of the present invention is to provide a semiconductor device, in which the distances between portions to be electrically connected can be reduced more than in the conventional case and high reliance can be obtained without applying physical damages due to heating, pressurizing when the electrical connection is made, and its manufacturing method. This object is achieved through a semiconductor device having the features of claim 1. Further, this object is achieved through a method having the features of claim 5. According to the invention, a bonding capillary and TAB tool, which are used for wire bonding and TAB connection are not required. Thereby, the distance between electrode pads can be reduced to 100 µm or less, for example, about 50 µm. Moreover, if each electrode pad and each inner lead are connected, no physical pressure is applied to the semiconductor chip, so that reliability due to pressure damage is not lowered. Then, since a large number of portions can be connected at the same time under the same conditions, reliance of connection can be improved. Moreover, since there is no need for heating when the connection is performed, it is possible to prevent reliability from being lowered by thermal stress, which is caused by a mismatch of the coefficient of thermal expansion of each semiconductor layer in the semiconductor chip. Since the plating layer is only formed in the absolutely necessary portion plating time can be shortened. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a cross sectional view showing the structure of a part of a device of a first embodiment of the present invention; Fig. 2 is a cross sectional view showing a general structure of the device of the first embodiment of the present invention; Fig. 3 is a cross sectional view showing a specific structure of an electrode pad of the device of the first embodiment of the present invention; Fig. 4 is a plane view showing a state of the connection between a plurality of electrode pads of the device of the first embodiment and a plurality of inner leads; Figs. 5 and 6 are plane views of a TAP tape, which is used in the device of the first embodiment of the present invention, respectively; Figs. 7 and 8 are plane views of modifications of the device of the first embodiment of the present invention, respectively; and Fig. 9 is a cross sectional view showing a device of a second embodiment of the present invention. The embodiments of the present invention will be explained with reference to the drawings. Fig. 1 shows the structure of a part of a semiconductor device of a first embodiment of the present invention wherein the present invention is used in the connection between a plurality of electrode pads on a semiconductor chip and a plurality of inner leads of a TAB tape, and Fig. 2 is the general structure thereof. In the drawings, reference numeral 11 is a semiconductor chip with an active element such as a transistor and a passive element such as a resistor and a capacity. Around the main surface of the semiconductor chip 11, there are formed a plurality of electrode pads 14, which are formed of a first metal layer 12 comprising a lower layer of aluminum (Aℓ) and a second metal layer 13 comprising an upper layer of at least one nickel layer. These electrode pads 14 are arranged in line with a predetermined distance. The portions of the semiconductor chip 11 other than the electrode pad formation position are covered with an insulating surface protection film 15 such as a silicon oxidation film. The semiconductor chip 11 is adhered to a predetermined portion of a TAB tape 17 by an epoxy adhesive 16. As shown in Fig. 1, the TAB tape 17 is made of epoxy or polyimide resin. Metal foil such as copper (Cu) foil having a thickness of about 35 µm is laminated on an organic film material 18 having a thickness of about 75 µm. Thereafter, there is formed a wiring pattern comprising a plurality of inner leads 19 to be connected to the plurality of electrode pads 14 by a selection etching technique and to the outer leads electrically connected to these inner leads (not shown). The wiring pattern forming surface is adhered to the semiconductor chip 11 by the adhesive 16. When the semiconductor chip 11 is adhered to the TAB tape 17, the positioning is performed in a state that each electrode pad 14 is positioned close to the portion where each end surface of the end portions of the plurality of inner leads 19 is exposed. Then, each electrode pad 14 on the semiconductor chip 11 and each end portion of the inner lead 19 are electrically connected through a metal plating layer 20 formed of nickel (Ni). Fig. 3 shows the specific structure of each electrode pad 14. In this embodiment, the second metal layer 13 formed on the first metal layer 12 made of aluminum (Aℓ) comprises at least two metal layers. More specifically, the lower layer contacting the first metal layer made of aluminum is formed of a titanium (Ti) layer 31 having a thickness of 1000 Å (10Å = 1nm), and the upper layer is formed of a nickel (Ni) layer 32 having a thickness of 3000 Å. The nickel layer 32, which is the upper layer of the second metal layer 13 is formed to allow the metal plating layer 20 of nickel to be formed on the electrode pad 14. Also, the titanium layer 31, which is the lower layer of the second metal layer 13, has a function as a barrier metal. Fig. 4 shows a state of the connection between the plurality of electrode pads 14 and the plurality of inner leads 19 of the TAB tape 17. In the drawing, a region in which slant lines are added shows the metal plating layer 20. In the above embodiment, each electrode pad 14 on the semiconductor chip 11 and each inner lead 19 are connected by the metal plating layer 20. Due to this, bonding capillary and TAB tool, which are used in wire bonding and TAB connection are not required. Thereby, the distance between electrode pads 14 can be reduced to 100 µm or less, for example, about 50 µm. Moreover, if each electrode pad 14 and each inner lead 19 are electrically connected, no physical pressure is applied to the semiconductor chip 11, so that reliance due to pressure damage is not lowered. Then, since a large number of portions can be connected at the same time under the same condition, reliability of connection can be improved. Moreover, since there is no need of heating when the connection is performed, it is possible to prevent reliability from being lowered by thermal stress, which is caused by a mismatch of the coefficient of thermal expansion of each semiconductor layer in the semiconductor chip. A method of forming the above metal plating layer where the electrode pads and the inner leads are electrically connected will be explained. In the TAB tape, as shown in Fig. 5, metal foil such as copper foil is laminated on the organic film material 18 in advance. Thereafter, in every semiconductor device, there are formed a plurality of lead electrodes 41 comprising the inner leads and the outer leads connected to the inner leads by the selection etching technique. At the same time when the selection etching is performed, common electrodes 42, which are electrically connected to the lead electrodes 41, are formed around each semiconductor device in a state that all common electrodes 42 are connected. Additionally, in Fig. 5, reference numeral 43 is an opening formed in the organic film material 18. Fig. 6 shows an enlarged single semiconductor device in the TAB tape of Fig. 5 In the drawing, the semiconductor chip is adhered to the TAB tape in a state that the semiconductor chip is positioned in the area shown by a single dotted chine line. In this case, the semiconductor chip is adhered to the TAB tape so that the pad of each electrode on the semiconductor chip is positioned close to the portion where each end of the end portion of the plurality of leads is exposed. Thereafter, the TAB tape is immersed in a nickel plating bath together with a plating electrode. The nickel plating bath is generally called a watt bath, and nickel sulfate, nickel chloride, and adhesive are used. After the TAB tape and the plating electrode are immersed in the watt bath, a predetermined direct voltage is applied between the common electrode 42 and the plating electrode such that the common electrode 42 serves as a positive electrode and the plating electrode serves as a negative electrode, and electrolytic plating is performed for a predetermined period of time. For example, a direct voltage to be applied was set to 2V, a current to be supplied between the positive and negative electrodes was set to 60mA, and the plating time was set to 10 minutes. As a result, a nickel plating layer having a thickness of 10 µm was obtained as metal plating layer 20. The metal plating layer grows from each end surface of the top end portion of the inner lead immediately after plating starts. Then, if the growth advances and the plating layer contacts the electrode pad on the semiconductor chip, the metal layer also grows on the electrode pad, and both the common electrode 42 and the plating electrode are finally electrically connected by the plating layer. After the end of plating, the plating layer is washed with pure water, and contaminant, which was adhered to the surface when plating, is removed. Additionally, on the surface of each lead electrode 41, which comprises the inner and outer leads, most of the surface other than the end portion of the inner lead is coated with the epoxy insulating film, which is called green coat. Thereby, it is possible to form the plating layer on only the necessary portion. Due to this, plating time can be shortened. Various modifications of the first embodiment will be explained. The above embodiment explained that the electrode pads were arranged in line with a predetermined distance. In the modified device of Fig. 7, the electrode pads 14 are arranged on the semiconductor chip in a zig-zag manner. The same reference numerals as Fig. 4 are added in the portions corresponding to the portions of Fig. 4, and the explanation thereof is omitted. Fig. 8 shows a modification of the device using a semiconductor which is the so-called free access pad layout system wherein the electrode pads are arranged on the entire surface of the semiconductor chip at random. As mentioned above, the present invention can be used with any type of chip regardless of the arrangement of the electrode pads on the chip. Fig. 9 shows the structure of the semiconductor device relating to a second embodiment of the present invention wherein the present invention is used for the connection between the outer leads of the lead frame and the wiring pattern on the printed circuit board. In the drawing, reference numeral 11 is a semiconductor chip, and reference numeral 17 is a TAB tape. In this embodiment, the end portion of the inner lead of the TAB tap and electrode pad (not shown) on the semiconductor chip 11 are electrically connected by a metal plating layer 20 similar to the first embodiment. According to the second embodiment, a wiring pattern 52, which is formed on a printed circuit board 51, and the outer lead of the TAB tape are also electrically connected by the metal plating layer 20. In the case of the first embodiment using the TAB tape, the metal plating layer can be formed in a manner that the semiconductor chip is adhered to the TAB tape by the adhesive in advance. In the case of using a lead frame formed by punching the metal thin film, the adhesive 54 is formed on each electrode pad 14 in advance by a screen printing method and the electrode pad 14 and the TAB tape are adhered by the adhesive 54. Thereafter, the plating layer 55 is formed by the same method as mentioned above, and both the electrode pad and the TAB tape can be electrically connected. As mentioned above, the present invention can be used not only for the connection between the inner lead of the TAB tape and the electrode pad on the semiconductor chip but also the connection between the outer lead and the wiring pattern on the printed circuit board, and the same effect can be obtained. Moreover, the present invention can be used in the electrical connection between a liquid crystal display and a TAB tape. The present invention is not limited to the above-mentioned embodiments. It is needless to say that the present invention can be modified. For example, the above embodiments described the case wherein the metal plating layer was a nickel plating layer. According to the present invention, an Au plating layer and a copper plating layer can be used in addition to the above case. Moreover, in the method of the above embodiments the plating layer was formed by the electrolytic plating method. However, the plating layer can be formed by an electrolessly plating method.

Claims: A semiconductor device, comprising: a) a semiconductor chip (11) having a plurality of-pad electrodes (14) on its surface, and b) a TAB tape (17) formed of an adhesive (16) a conductive material forming a plurality of inner leads (19) on the adhesive (16) and an insulating film (18) on the conductive material (19) such that the upper and lower surfaces of the conductive material (19) are covered, and only the end surfaces thereof are exposed, the semiconductor chip (11) being adhered to the TAB tape (17) via the adhesive (16) characterized in that c) said TAB tape (19) and said pad electrodes (14) are connected only by a metal (20) plated from a solution, said metal (20) contacting only the exposed end surfaces of the conductive material (19) that are directly adjacent said pad electrodes (14). Semiconductor device according to claim 1, characterized in that said plurality of pad electrodes (14) formed on the surface of said semiconductor chip (11) comprise an aluminum layer (12), a titanium layer (31) formed on said aluminum layer (12) and a metal layer (32) formed on said titanium layer (31), said metal layer (32) being a nickel layer or a copper layer. Semiconductor device according to claim 1, characterized in that said plurality of pad electrodes (14) are arranged on said surface of said semiconductor chip (11) in a zig zag manner. Semiconductor device according to claim 1, characterized in that said plurality of pad electrodes (14) are arranged on said surface of said semiconductor chip (11) in a random manner. Method of manufacturing a semiconductor device, comprising a semiconductor chip (11) having a plurality of pad electrodes (14) on its surface, and a TAB tape (17) formed of an adhesive (16) a conductive material forming a plurality of inner leads (19), on said adhesive (16) and an insulating film (18) on the conductive material (19) such that the upper and lower surfaces of the conductive material (19) are covered, and only the end surfaces thereof are exposed the method comprising the steps: a) moving the TAB tape (17) and the pad electrode (14) to be close to each other and adhering said semiconductor chip (11) to said TAB tape (17) via said adhesive (16), and b) immersing said TAB tape (17) and said semiconductor chip (11) in an electrolytic plating solution, and c) plating a metal layer (20), said TAB tape (17) thus being electrically connected only at the exposed end surfaces thereof to said pad electrode (14) of said semiconductor chip (11). Method according to claim 5, characterized in that said TAB tape (17) is formed of a plurality of lead electrodes (41), said plurality of lead electrodes being connected by a common electrode (42) so that an electrical potential can be supplied to said common electrode (42) during said plating of said metal (20).

Inventors: FUJITSU TAKAO, FUJITSU, TAKAO, Fujitsu, Takao, c/o Intellectual Property Div.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: H01L23
IPC codes: H01L23, H01L21