Process for forming multi-level coplanar conductor/insulator films employing photosensitive polyimide polymer compositions

Abstract: Disclosed is a process for producing multi-level conductor/insulator films on a processed semiconductor substrate (2) having a conductor pattern (4). The insulator layers (1, 6), each comprise a photosensitive polyimide polymer composition, and this allows the desired wiring channels and stud vias to be formed directly in the insulator layers, without the use of separate masking layers and resulting image transfer steps, thus providing a less cumbersome and costly process.

Description: This invention relates to the manufacture of VLSI semiconductor chips, boards and assemblies, and, more particularly, to a process for forming multi-level coplanar metal insulator films on a substrate. In the field of VLSI semiconductor chip processing, multi-level metal patterns are used to interconnect devices. One technique for accomplishing this is disclosed in IBM Tech. Discl. Bull., Vol. 25, No. 10 (Mar. 1983), pp. 5309-5314, where a first metal pattern is formed in an insulator layer. An insulator layer is deposited, and a series of holes are etched through this layer in locations where interconnections (or stud vias) are desired. The holes are filled with metal, excess metal is lifted off, and another insulator layer is deposited; this layer is patterned, and metal is deposited in these openings, thus making contact with the first metal pattern. This process is cumbersome and costly to carry out, however, as it involves several sequences of masking and etching steps. A simpler approach is shown in U.S. -A- 4,789,648, issued to Chow, et al. on Dec. 6, 1988, which includes the following steps: depositing an insulator layer over an underlying insulator layer containing a metal pattern; applying an etch stop layer; defining holes in the etch stop; depositing another insulator layer; etching openings (or wiring channels) in the upper insulator layer in alignment with the holes in the etch stop, and continuing the etching into the first insulator layer to form via holes; overfilling the channels and via holes with metal; and then removing the excess metal to form a coplanar metal/insulator surface. While this process is less complicated than that disclosed in the article discussed above, nevertheless, it still involves two sequences of masking and etching steps to form the via holes and the wiring channels. Another conventional technique, known as the pillar process, is exemplified in U.S. -A- 4,621,045, issued to Goodner on Nov. 4, 1986, in which a conductive pillar is provided in an insulator layer to connect two layers of metal. This process also has a high degree of complexity, however, with multiple masking and etching sequences. The article in Journal of the Electrochemical Society, vol. 137, no. 3, March 1990, New Hampshire, USA, pages 961-966 by K.K. Chakravorty et al., discloses the use of photosensitive polyimides as dielectric layers in interconnect structures. Now, in accordance with the present invention as claimed, there is provided a less cumbersome process, which employs at least two insulator layers comprising a photosensitive polyimide polymer composition. Openings are formed directly in the insulator layers, without requiring the use of masking layers and pattern transfer steps. The openings which are in at least partial alignment are simultaneously filled with a conductor material, and the material which overlies the upper insulator layer is removed to achieve a coplanar conductor/insulator film. The process steps can be repeated to form additional coplanar conductor/insulator films. In a preferred embodiment, the process involves forming multi-level coplanar conductor/insulator films on a substrate having a conductor pattern, by first applying a first layer comprising a photosensitive polyimide polymer composition to the substrate, and exposing the first layer to a pattern of ultraviolet radiation. A second layer comprising a photosensitive polyimide polymer composition is applied to the first layer, and the second layer is exposed to a pattern of ultraviolet radiation. The first and second layers are developed so as to selectively expose regions of the substrate, the openings in the first layer being in alignment with at least a portion of the openings formed in the second layer. A conductor material is deposited on the second layer and in the openings in the first and second layers, and then the conductor material which overlies the second layer is removed to coplanarize the surfaces of conductor material and the second layer. The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of the preferred embodiments of the invention. Figs. 1-7 are cross-sectional views of a semiconductor structure illustrating the structure that results at various stages of the process of a preferred embodiment of the invention. Referring to Fig. 1, the process starts by applying a first insulator layer 1 to a processed semiconductor substrate, indicated generally by the numeral 2. Typically, the substrate 2 comprises a planarized insulator layer 3 which includes a pattern of conductor material 4. In general, the insulator layer 3 is disposed over an integrated circuit chip, and the conductor material 4 is contact metallurgy to devices (not shown) formed in the chip. Preferably, the first insulator layer 1 is deposited over the substrate 2 by spin application, at about 2000 - 6000 rpm for about 20 - 60 seconds, and then baked at a temperature of about 70 - 90°C for about 10 - 30 minutes. It should be noted that it is also preferred, to improve adhesion, to apply a conventional adhesion promoter, such as 0.1% 3-aminopropyltriethoxysilane (commercially available from Union Carbide under the designation "A1100") in methanol, to the substrate before depositing the first insulator layer 1. In general, the planarized insulator layer 3 commonly comprises silicon dioxide or reflowed phosphosilicate glass, and the conductor material 4 may be, for example, copper-doped aluminum or doped polycrystalline silicon. It is an important feature of the invention, that both the first insulator layer 1, as well as a second insulator layer 6, to be described below, comprise a photosensitive polyimide polymer composition. Thus, a desired pattern of openings can be formed directly in each of the layers 1 and 6, without requiring application of separate masking layers, followed by image transfer steps. Suitable photosensitive polyimide polymer compositions are disclosed, for example, in U.S. -A- 4,629,777, issued to Pfeifer on Dec. 16, 1986; U.S. -A- 4,657,832, issued to Pfeifer on Apr. 14, 1987; U.S. -A- 4,698,295, issued to Pfeifer, et al. on Oct. 6, 1987; and U.S. -A- 4,656,116, issued to Rohde, et al. on Apr. 7, 1987, the entire disclosures of which are incorporated herein by reference. Preferably, the polymer composition comprises a fully imidized solvent soluble polyimide with a structural unit having the general formula where R represents an aliphatic group, such as methyl, and R′ represents an optional aliphatic substituent which may be the same as or different from R, and a suitable solvent for the polymer. (The R′ substituent can enhance the photospeed or increase the Tg-value of the polymer.) Such photosensitive polyimide polymer compositions are disclosed in Pfeifer, et al., "Direct Photoimaging of Fully Imidized Solvent-Soluble Polyimides", Second International Conference on Polyimides, Mid-Hudson Section SPE, Ellenville, N.Y. (Oct. 30-Nov. 1, 1985), the entire disclosure of which is incorporated herein by reference. In a particularly preferred embodiment, the "PROBIMIDE 400" series, preferably "PROBIMIDE 408", commercially available from Ciba-Geigy Corp., is employed. As shown in Fig 2, the insulator layer 1 is then exposed in a predetermined pattern to radiation, such as UV light, in a conventional manner. The region, designated as 5, represents that portion of the first insulator layer 1, which has not been exposed. Referring to Fig. 3, a second insulator layer 6 is applied to the first insulator layer 1, prior to development. Then, the second insulator layer 6 is exposed in a predetermined pattern to radiation, as described above, with the region, designated as 7 in Fig. 4, representing that portion of the second insulator layer 6, which has not been exposed. Again, in general, the method of applying and exposing the second insulator layer 6, as well as the composition, are as described above. It should be noted that in general, the first insulator layer 1 is applied to a thickness typically ranging from about 0.2 - 1 microns, preferably from about 0.6 - 0.7 microns, while the second insulator layer 6 has a thickness usually ranging from about 0.05 - 1.2 microns, preferably from about 0.2 - 0.5 microns. Next, the unexposed regions 5 and 7 of the insulator layers 1 and 6, respectively, are simultaneously removed to selectively expose regions of the substrate 2. For example, when "PROBIMIDE 408" is used as the photosensitive polyimide polymer composition, the unexposed regions 5 and 7 are removed, preferably by spraying with a conventional developer, such as, for example, gammabutylactone. In general, the development time will depend on the thicknesses of the first and second insulator layers 1 and 6, as well as other factors known to those skilled in the art. This provides the structure shown in Fig. 5. Referring again to Fig. 5, the openings formed in the first insulator layer 1 are in at least partial alignment with those formed in the second insulator layer 6. The openings in the first insulator layer 1 allow contact to be made to the pattern 4 in the substrate 2. The structure, as shown in Fig. 5, allows simultaneous formation of conductor material in the openings in the second insulator layer 6 (i.e., wiring channels) and in the openings in the first insulator layer 1 (i.e., stud vias). The structure, as shown in Fig. 5, is then subjected to a heating step so as to cure the polyimide layers 1 and 6. Generally, this step is carried out at a temperature of at least about 10°C above the temperature at which the conductor material 8 is to be applied, as discussed below. Typically, this temperature is at least about 350°C, and is usually within the range of about 350°-450°C, depending upon the conductor material 10 which is employed. Next, as shown in Fig. 6, the openings in the layers 1 and 6 are overfilled with conductor material 8, preferably metal, for example, aluminum, copper, Al-Cu, Al-Si or tungsten, preferably by physical vapor deposition, such as evaporation or sputtering, chemical vapor deposition or by plating. It should be noted that the thickness of the conductor material 8 is at least as great as the combined thicknesses of the insulator layers 1 and 6. In the next step, as shown in Fig. 7, the conductor material 8, which overlies the second insulating layer 6 is removed so as to coplanarize the surfaces of the conductor material 8 and the second insulator layer 6. A preferred method to accomplish this is by using chemical-mechanical polishing, as taught, for example, in EP-A- 0,223,920, published Jun. 3, 1987, by Beyer, et al., the entire disclosure of which is incorporated herein by reference. That process involves the concurrent chemical and mechanical polishing of an overlying layer to expose the surface of a non-planar underlying layer on which it is formed, one layer of which is a conductive film, and the other, an insulator film. Using a polishing pad and a slurry, the process removes the overlying layer at a faster rate than the underlying layer, until the upper surface of the overlying layer becomes coplanar with that of the underlying layer. As another alternative, coplanarization can be accomplished by standard sacrificial planarization methods, such as etchback, as should be apparent to those skilled in the art. If the conductor layer 8 is the final metal level of the semiconductor structure, final passivation insulator is applied over the substrate. Otherwise, if additional levels of metallization are to be formed, then the steps as described above are repeated for each level desired. Various modifications can be made in the process, as will be apparent to those skilled in the art. A sample process flow for this embodiment, prior to application and planarization of metal, is as follows: Spin apply 0.1% 3-aminopropyltriethoxysilane (commercially available from Union Carbide under the designation "A1100") in methanol to a processed semiconductor substrate containing a pattern of metallization; Spin apply "PROBIMIDE 408" at 500 rpms, then hold at 4,000 rpms for 25 sec.; Bake at 80°C for 20 min.; Expose to UV light (270 mj at 365 nm); Spin apply "PROBIMIDE 408" and bake as above; Expose to UV light (270 mj at 365 nm); Simultaneously develop first and second "PROBIMIDE 408" layers with a 45 sec. spray of gammabutylactone at 500 rpms; Rinse with a 20 sec. spray of xylene at 500 rpms; Dry with N₂; and Ramp cure to 350°C. As such, the present invention provides multi-level coplanar conductor/insulator films, by forming the desired channels and stud vias directly in the insulator layers, without the need for separate masking layers and image transfer steps. Accordingly, the need for resist stripping operations, which can damage the patterns formed in the insulator layers, is also avoided.

Claims: A process of forming a multi-level structure comprising coplanar layers of conductor and insulator films on a substrate (2) having a conductor pattern (4), comprising the steps of: applying a first layer (1) comprising a photosensitive polyimide polymer composition to said substrate; exposing said first layer to a pattern of ultraviolet radiation; applying a second layer (6) comprising a photosensitive polyimide polymer composition to said first layer; exposing said second layer to a pattern of ultraviolet radiation; developing said first and second layers so as to selectively expose regions of said substrate, the openings (5) in said first layer being in alignment with at least a portion of the openings (7) formed in said second layer; depositing a conductor material (8) on said second layer and in said openings in said first and second layers; and removing said conductor material which overlies said second layer to coplanarize the surfaces of conductor material and said second layer. The process of Claim 1, wherein said steps are repeated to form additional coplanar conductor/insulator films. The process of Claim 1 or 2, wherein said photosensitive polyimide polymer composition comprises a fully imidized solvent soluble polyimide with a structural unit having the general formula where R represents an aliphatic group, and R′ represents an optional aliphatic substituent which may be the same as or different from R, and a solvent. The process of Claim 1, 2 or 3, wherein said conductor material is a metal selected from aluminum, copper, Al-Cu, Al-Si and tungsten. The process of any one of the preceding claims, wherein said first layer has a thickness ranging from about 0.2 to about 1 microns, preferably from 0,6 to 0,7 microns; and said second layer has a thickness ranging from about 0.05 to about 1.2 microns, preferably from 0,2 to 0,5 microns. The process of any one of the preceding claims, wherein said conductor material which overlies said second layer is removed by using chemical-mechanical polishing. A semiconductor structure manufactured according to the process of any one of the preceding claims.

Inventors: CRONIN JOHN EDWARD, KAANTA CARTER WELLING, LEE PEI-ING PAUL, PREVITI-KELLY ROSEMARY ANN, RYAN JAMES GARDNER, YOON JUNG HOON, CRONIN, JOHN EDWARD, KAANTA, CARTER WELLING, LEE, PEI-ING PAUL, PREVITI-KELLY, ROSEMARY ANN, RYAN, JAMES GARDNER, YOON, JUNG HOON
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1991
Main classification: H01L21
IPC codes: H01L23, G03F7, H05K3, C08G73, H01L21