Active matrix display device

Abstract: An active matrix display device which includes a first and a second insulating substrates, a gate bus (21) and a source bus (23) arranged on the first substrate like a lattice, a pixel electrode (41) in a segment enclosed by the gate and the source buses, a switching element (31) connected to the pixel electrode, the gate bus and the source bus, wherein the source bus comprises a projection (46) extending toward the pixel electrode so as to be electrically disconnected therefrom, and the gate bus comprises a projection (43) extending toward the pixel electrode, the source bus being overlaid on the gate bus projection with an insulating layer sandwiched therebetween, the gate bus projection being provided with an electroconductive member (44) at the top thereof with an insulating layer sandwiched therebetween, the electroconductive member being electrically connected to the pixel electrode, and electrically disconnected from the source bus projection.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention: The present invention relates generally to an active matrix display device, and more particularly to an active matrix display device in which switching elements such as thin film transistors apply drive signals to pixel electrodes arranged in a matrix so as to achieve a high density display. 2. Description of the Prior Art: In the known liquid crystal display devices, EL display devices, plasma display devices, etc. the pixel electrodes arranged in a matrix are selectively driven so as to represent a pattern on a screen. The pixel electrodes are individually provided with switching elements through which the pixel electrodes are selectively driven. This is commonly called an active matrix driving system. The switching elements are made of a thin film transistor (TFT), a metal-insulator metal (MIM), a MOS transistor, a diode or a varistor. A voltage applied between the individual pixel electrodes and counter electrodes is switched on, and a liquid crystal, an EL light emitting medium, a plasma light emitting device make the display medium optically modulated. The optical modulation is observed as displayed patterns by the naked eye. The active matrix display device is suitable for display in high contrast, and finds application in liquid crystal television, word processors, and terminal display units of computers. Figures 9 and 10 show known types of active matrix liquid crystal display devices. One of a pair of substrates has gate buses 21 arranged transversely and source buses 23 perpendicular to the gate buses 21 . Every rectangular segment enclosed by the adjacent gate buses 21 and the source buses 23 has a pixel electrodes 41 . A gate bus branch 22 branched off from the gate bus 21 has a TFT 31 as a switching element. The gate bus branch 22 includes a first section which functions as a gate electrode for the TFT 31 , and a second section which is narrower than the first section. A drain electrode 33 of the TFT 31 is electrically connected to the pixel electrode 41 , and a source electrode 32 is connected to the source bus 23 . Figure 10 shows another known example in which a source bus branch 90 branched from the source bus 23 overlaps the gate bus 21 , and a TFT 31 is formed on the overlapping part. A drain electrode 33 of the TFT 31 is electrically connected to the pixel electrode 41 , and a source electrode 32 is electrically connected to the source bus 23 through the source bus branch 90 . Under this arrangement of the known active matrix display device a problem arises, for example, if any switching element malfunctions, the pixel electrode connected thereto receives no signal. This appears on the display as devoid of pixel electrode. The absence of a pixel electrode spoils the representation of the display device. This results in a lower manufacturing yield. Such faulty or defective pixel electrodes occur for the following two reasons: (1) The pixel electrodes are not fully charged until the switching elements are selected by a scanning signal (signals from the gate bus) (hereinafter referred to as "on fault"), and (2) An electric leakage occurs through the charged pixel electrodes before the switching elements are selected (hereinafter referred to as "off fault"). The "on fault" occurs owing to a defective switching element. The "off fault" occurs for a further two reasons; one is an electrical leakage through the switching element, and the other is an electrical leakage between the pixel electrodes and the buses. In either case, the voltage to be applied between the pixel electrodes and the counter electrode does not reach a required value. This causes faulty pixel electrodes to look like luminous points under the normal white mode (a mode in which the optical transmissibility reaches the maximum when the voltage applied to the liquid crystal is zero), and looks like a black point under the normal black mode (a mode in which the transmissibility is lowest when the voltage reaches zero). If these faults are found during the fabrication of a substrate in which the switching elements are arranged, they can be cured (trimmed) by laser. In fact, however, it is almost impossible to find a single faulty pixel electrode in a great number of pixel electrodes. The mass production of substrates cannot be carried out without increasing costs and prolonging the time. It is completely impossible to do so in a large size display panel having 100,000 to 500,000 pixel electrodes. It is possible to visually observe a faulty pixel electrode by overlaying a counter substrate on a substrate in question, injecting liquid crystal therebetween and applying an inspection signal to the source bus. This method requires a correction in which the source bus and the pixel electrodes are short-circuited so as to effect the charge and discharge of the pixel electrodes by a signal voltage irrespective of whether the source bus was selected or not. In the example shown in Figures 9 and 10, it is inherently difficult to do such a correction because of the arrangement of the source bus 23 and the pixel electrodes 41 . After all, the display device containing the faulty pixel electrodes has to be discarded even if other components and elements are in good condition. This is wasteful, and increases the production cost. This accounts for the decreased manufacturing yield. SUMMARY OF THE INVENTION In one aspect the invention, as defined by claim 1, provides an active matrix display device with pixel-controlling switching elements formed on an insulating substrate on which also are formed pixel electrodes and a lattice arrangement of first source bus lines extending in a column direction and second lines extending in a row direction transverse the source lines, each pixel electrode being formed in a respective section defined by a pair of said first lines and a pair of said second lines, characterised in that: for each pixel electrode there are provided first and second projections respectively from a said first and second line, one of said projections overlapping the other, and the second projection having a portion lying beneath the pixel electrode, whereby connections can be made between the first and second projections and between the second projection and the pixel electrode so as to short the pixel electrode to the first line. In another aspect the invention, as defined by claim 11, provides an active matrix display device comprising an insulating substrate on which are formed: a lattice arrangement of source bus lines extending in a column direction and gate bus lines extending in a row direction transverse the source bus lines; a respective pixel electrode within each section defined by an adjacent pair of said source bus lines and an adjacent pair of said gate bus lines; a respective switching element for applying a drive signal to each said pixel electrode, the switching element being connected to the pixel electrode, one of said pair of source bus lines and one of said pair of gate bus lines, characterised by: a structure, other than said switching element, enabling the pixel electrode to be shorted to one of said pair of source bus lines in the event of a fault preventing effective application of said drive signal to the pixel electrode, said structure including a projection from one of said pair of gate bus lines, to which projection said one source line and said pixel electrode may be individually electrically connected. The features of the preambles of claims 1 and 11 are known in combination from JP-A-62-22455. The dependent claims 2 to 10 and 12 relate to features of preferred embodiments of the invention. The invention described herein makes possible the objectives of (1) providing an active matrix display device in which one can detect and correct any faulty pixel electrodes by a simple procedure after all pixel electrodes are driven, (2) providing an active matrix display device which can be produced at low cost with a high manufacturing yield, and (3) providing an active matrix display device in which one can correct any faulty pixel electrodes without reducing the aperture ratio of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a plan view showing an active matrix display device according to the present invention; Figure 2 is a cross-sectional view taken along the line A-A in Figure 1; Figure 3 is a fragmentary plan view on an enlarged scale showing the area B of the active matrix display device shown in Figure 1; Figure 4 is a cross-sectional view taken along the line C-C in Figure 3; Figure 5 is a timing chart showing the signals input to the gate bus, source bus and pixel electrodes; Figure 6 is a cross-sectional view showing a modified example of the present invention; Figure 7 is a plan view showing another example of the present invention; Figure 8 is a plan view showing another example of the present invention; Figure 9 is a plan view showing an example of a prior art active matrix display device; Figure 10 is a plan view showing another example of a prior art active matrix display device; Figure 11 is a plan view showing a modification of the Figure 1 example of the invention; and Figure 12 is a plan view showing another modification of the Figure 1 example of the invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to Figures 1 to 4, a display panel includes a lower transmissive insulating substrate 1 and an upper transmissive insulating substrate 2 disposed with a liquid crystal 18 sandwiched therebetween. The lower substrate 1 is provided with a plurality of gate buses 21 for scanning buses, a plurality of source buses 23 so that each rectangular section enclosed by the buses 21 and 23 has pixel electrodes 41 arranged in a matrix. The gate bus 21 has a branch line 22 which is provided with a TFT 31 at its top, i.e. distal, end. The TFT 31 , functioning as a switching element, is connected to the pixel electrode 41 . In Figure 1, a gate bus 21b adjacent to a gate bus 21a connected to the pixel electrode 41 is provided with a gate bus projection 43 extending inward from the corner of the pixel electrode 41 . The projection 43 is provided with an electroconductive member 44 through a gate insulating film 13 (Figures 3 and 4). The source bus 23 is also provided with a source bus projection 46 in correspondence with the corners of the pixel electrodes 41 . The source bus projection 46 overlaps the gate bus projection 43 through the gate insulating film 13 . A process of fabricating the display panel will be described in detail: The gate bus 21 is formed on the transmissive insulating substrate 1 in a known manner. For example, metal such as Ta, Ti, Al or Cr is deposited either as a single layer or as multi-layers on the transmissive insulating substrate, and then the layer or layers are patterned. Simultaneously, the gate bus branch 22 and the gate bus projection 43 are patterned. In this example, the insulating substrates 1 are made of glass (in the drawings, one substrate only is shown for explanation convenience). It is possible to form an insulating film 11 of Ta₂O₅ or the like as a base coat as shown in Figure 4. Then, the gate insulating layer 13 is overlaid on the gate bus 21 (including the gate bus branch 22 and the gate bus projection 43 ). In this example, an SiN X film was formed to a thickness of 300 nm by a plasma CVD as the insulating layer 13 . Alternatively, it is possible to form an oxidized layer 12 of Ta₂O₅ by anodizing the gate bus 21 prior to the formation of the gate insulating layer 13 , as shown in Figure 4. A semiconductor layer 14 and an etching stopper layer 15 are successively formed on the gate insulating layer 13 by a plasma CVD method. The semiconductor layer 14 is made of amorphous silicon (a-Si) to a thickness of 30 nm, and the etching stopper layer 15 is made of SiN X to a thickness of 200 nm. The etching stopper layer 15 is patterned, and an n⁺ type a-Si layer 16 with phosphorus is deposited to a thickness of 80 nm by the plasma CVD method. The n⁺ type a-Si layer 16 is formed to enhance the ohmic contact between the semiconductor layer 14 and a source electrode 32 or a drain electrode 33 (Figure 2) which will be deposited at a later stage. Then, the n⁺ type a-Si layer 16 is patterned, and a source metal such as Ti, Al, Mo, or Cr is deposited by sputtering. In this example, Ti was used. The Ti layer is patterned so as to form the source electrode 32 and the drain electrode 33 . The finished thin film transistor (TFT) 31 is illustrated in Figure 2. At this stage, as shown in Figure 4, the source bus projection 46 and the electroconductive member 44 are simultaneously formed. The next step is to deposit a transmissive conductive substance for the pixel electrodes 41 . In this example, ITO (indium tin oxide) was deposited by sputtering and patterned so as to form the pixel electrodes 41 , each of which, as referred to above, is formed in the rectangular section enclosed by the gate bus 21 and the source bus 23. As shown in Figure 2, the end portion of the pixel electrode 41 is overlaid on an end portion of the drain electrode 33 of the TFT 31. Also, as shown in Figures 3 and 4, the pixel electrode 41 is deposited on the electroconductive member 44 . In this way, energizing can be effected through the pixel electrode 41 , the drain electrode 33 of the TFT 31 and the electroconductive member 44 . The whole surface of the glass substrate 1 is covered with a protective layer 17 of SiN X . The protective layer 17 can be provided with a hole at a central part of the pixel electrodes 41 . An orientation layer 19 is formed on the protective layer 17 . The orientation layer 19 can be also provided with a hole at its centre. As shown in Figure 2, a counter electrode 3 and an orientation layer 9 are formed on the glass substrate 2 . The reference numeral 18 denotes a layer of liquid crystal material sandwiched between the pair of insulating substrates 1 and 2 . In this way an active matrix display device is finished. A method of correcting a faulty pixel electrode will be described: The pixel electrode 41 is driven by the TFT 31 unless the TFT 31 is in abnormal condition, and the pixel electrode 41 in the segment enclosed by the gate bus 21 and the source bus 23 is put into regular operation. No problem arises on the display. If any abnormality occurs in the TFT 31 or a weak electric leak occurs between the source bus 23 and the pixel electrode 41 , the pixel electrode becomes faulty, and the result appears on the display. This faulty pixel electrode is corrected in the following manner: First, the active matrix display device is driven so as to confirm the faulty pixel electrode. As shown in Figure 3, if any abnormality is discovered, a segment 51 enclosed by dotted lines is irradiated with photo energy such as YAG laser beams so as to disperse the metal molecules in this segment 51 . In this way the gate bus 21 and the gate bus projection 43 are electrically disconnected from each other. Then a segment 52 enclosed by dotted lines is irradiated with laser beams so as to destroy the insulating layer 13 and oxidized layer 12 (if present) between the source bus projection 46 and the gate bus projection 43 . Thus the two projections 46 and 43 are melted, thereby enabling them to electrically communicate with each other. The laser beams can be irradiated either from the side of the insulating substrate 1 on which the TFT 31 is formed or from the side of the substrate 2 on which the counter electrode is provided. In this example, the laser beams are irradiated from the side of the substrate 1 because of the coverage of the substrate 2 with a light shield metal. In Figure 4, the directions of laser beams are indicated by white thick arrows. Second, laser beams are irradiated upon the segment 53 , where the gate bus projection 43 and the electroconductive member 44 overlap each other. This irradiation destroys the insulating layer 13 and oxidized layer 12 (if present), thereby enabling the gate bus projection 43 and the electroconductive member 44 to electrically communicate with each other by fusing. The two irradiations of laser beams enable the upper and lower metal wirings to electrically communicate in the segments 52 and 53 , respectively. In this way the source bus 23 and the electroconductive members 44 , that is, the pixel electrode 41 are short-circuited. Because of the short-circuit the faulty pixel is lit at an average brightness achieved by all the normal pixels connected to the source bus 23 , thereby avoiding a faulty display. The gate bus branch 22 and the TFT 31 are covered with the protective layer 17 , thereby preventing molten metal molecules from admixing with the liquid crystal 18 . This avoids the deterioration of the liquid crystal 18 . The irradiation of laser beams can be in various order for the segments 51 , 52 , and 53 as desired. Besides, the spots of irradiation need not be limited to the illustrated ones but any desired spots can be selected; for example, in the segments 52 and 53 any desired spots can be selected if they are within the overlapping portions of the upper and lower electroconductive layers. Referring now to Figure 5, explanation will be given as to how the TFT is operated when the pixel electrode 41 and the source bus 23 are short-circuited: In Figure 5, G n is a signal (voltage signal) from the (n)th gate bus 21 , S m is a signal from the (m)th source bus 23 , P n,m is a signal given to the pixel electrode 41 present at the junction of the (n)th gate bus 21 and the (m)th source bus 23 . As shown in Figure 5(a), when the potential of the signal from the gate bus 21 is Vgh (at a high level), the TFT 31 is selected, and when it is Vgl (at a low level), the TFT 31 is not selected. As shown in Figure 5(c), when the TFT 31 is selected, a pulse signal V0 is charged in the pixel electrode 41 . When the pixel electrode 41 is in a normal operation condition, the signal V0 is held for a period of time Toff when the TFT 31 is not selected, and a signal -V0 is written in the source bus 23 at a point of time Ton when the TFT 31 is selected. In Figure 5(b) the reference signal Gn+1 denotes a signal applied to the ( n+1 )th gate bus 21 . This signal Gn+1 is selected when the period of time Ton for selecting the (n)th gate bus 21 expires. At this time the signal -V1 is written in the source bus 23 (Figure 5(c)). As is evident from Figures 5(a) and 5(b), the signals applied to the gate bus 21 are consecutively delayed in the order of the line number, and the non-selection period of time continues over the period of time Toff until the (n)th gate bus 21 is selected. During the non-selective period of time signals to be written in the pixel electrodes 41 are continuously applied to the source bus 23 . As shown in Figure 5(d), the pixel electrodes 41 that are in normal condition are charged in response to the signal Sm input from the source bus 23 when the gate signal Gn is selected, thereby changing the molecular arrangement of the liquid crystal 18 at an electric potential between the counter electrode 3 on the substrate 2 and the liquid crystal 18 . In this way the display is effected. At this stage, the signals Sm input to the source bus 23 during the non-selection period of time Toff do not contribute to the display at all. When the pixel electrode 41 and the source bus 23 are short-circuited by the irradiation of laser beams, the pixel electrode 41 is subjected to electrical charging or discharging in response to all the signals Sm input from the source bus 23 irrespective of the selection and non-selection of the gate bus 21 , wherein the signal is indicated by P′n,m in Figure 5(e). The pixel electrode 41 that was corrected by the irradiation of laser beams receives the signal Sm directly from the source bus 23 during the non-selection period of time Toff . Thus, the voltage is applied to the liquid crystal 18 at its effective value. Except when the signal Sm applied to the source bus 23 becomes V0 , the effective value of the signal P′n,m cannot be V0 , but the effective value of the signal voltage P′n,m is an average value of all the pixel electrodes 41 connected to the (m)th source bus 23 . This means that the display device is lit at an average brightness of the pixel electrodes 41 arranged along the (m)th source bus 23 . Each pixel electrode is lit at such a sufficient brightness so as to maintain the quality of representation on the screen. Figure 6 shows a modified version which includes a semiconductor layer 14 , an etching stopper layer 15 and a contact layer 16 between the gate insulating layer 13 and an electroconductive member 44 , and between the gate insulating layer 13 and the source bus projection 46 , respectively. These layers 14 to 16 are provided to electrically disconnect the upper electroconductive layers from the lower electroconductive layers, and vice versa. Instead of these layers 14 to 16 , the semiconductor layer 14 and the etching stopper 15 , or the contact layer 16 alone can be inserted. Figure 7 shows a further modified version in which each pixel electrode 41 has an additive capacitance 42 which is constituted by an additive capacitance bus 24 arranged in parallel with the gate bus 21 and the gate insulating layer 13 . More specifically, the additive capacitance bus 24 and the pixel electrode 41 partly overlap one another, and the additive capacitance 42 is formed on the overlapping portion as shown by hatching in Figure 7. The additive capacitance bus 24 is formed by depositing the same metal as that of the gate bus 21 , and patterning simultaneously when the gate bus 21 is patterned. This example shown in Figure 7 is constructed so that the same signal is input to the additive capacitance bus 24 as the counter electrode 3. As a circuit the additive capacitance 42 is in parallel with the capacitance of the liquid crystal 18. The additive capacitance 42 maintains the charge of the pixel electrodes 41, thereby enhancing the performance of the display device. In this example, the projection 43 extends from the additive capacitance bus 24 and can be electrically connected to the pixel electrode 41 in the same manner as described above, whereby a faulty pixel can again be corrected. Figure 8 shows another modified version in which the additive capacitance 42 is formed by the adjacent gate bus 21. More specifically, the additive capacitance bus 24 of the previous example is integrated with the gate bus 21, and the additive capacitance 42 is formed on an overlapping portion of the pixel electrodes 41 and the gate bus 21 through the gate insulating layer 13 as shown by hatching in Figure 8. When the adjacent gate bus 21 is not selected, the same signal is input to the gate bus 21 as that applied to the counter electrode 3 on the glass substrate 2. This gate bus 21 is used as the additive capacitance bus 24. This decreases the light shading area, thereby avoiding a dark image picture. Thus the display performance is enhanced. Figure 11 shows a modification of the example shown in Figure 1. In Figure 11, the source bus 23 comprises a projection 46 extending toward-the pixel electrode 41 in such manner as to be electrically disconnected from the pixel electrode, and the gate bus 21 comprises a projection 43 extending toward the pixel electrode 41 and whose top, i.e. distal, end reaches toward a forward end of the source bus projection 46. The switching element 31 is formed toward the base end of the gate bus projection 43, a middle portion of the gate bus projection 43 being overlapped by the source bus projection 46 with an insulating layer sandwiched therebetween. The gate bus projection 43 is provided with an electroconductive member 44 at the top end thereof through an insulating layer, the electroconductive member 44 being electrically connected to the pixel electrode 41. Figure 12 shows a further modification of the example shown in Figure 1. In Figure 12, the gate bus 21 comprises a gate bus branch 22 comprising a larger end portion and smaller portion other than the end portion. The switching element 31 is formed at the top, i.e. distal, end of the gate bus branch 22 and connected to the pixel electrode 41. A gate bus projection 43 extends from the gate bus 21b adjacent to the one (21a) electrically connected to the pixel electrode 41 toward the corner of the pixel electrode. A source bus projection 43 extends from the source bus 23b adjacent to the one (23a) electrically connected to the pixel electrode 41 toward the corner of the pixel electrode. An electroconductive member is overlaid on the end of the gate bus projection 43 through insulating layers and electrically connected to the pixel electrode 41. In the illustrated embodiments the TFTs are used as switching elements, but an MIM element, a MOS transistor, a diode or a varistor can be used. The TFT is not limited to the illustrated structure but can be variously modified; for example, a source bus can be placed as a lower layer, and a gate bus can be placed as an upper layer. As is evident from the foregoing description, according to the present invention a faulty pixel can be detected after all the pixel electrodes are driven. In addition, the correction of a faulty pixel can be easily done by irradiating the display panel with laser beams from outside the insulating substrates. As a result, the manufacturing yield is increased. The invention may be embodied in other specific forms without departing from its scope, as defined by the claims.

Claims: An active matrix display device with pixel-controlling switching elements (31) formed on an insulating substrate (1) on which also are formed pixel electrodes (41) and a lattice arrangement of first source bus lines (23) extending in a column direction and second lines (21;24) extending in a row direction transverse the source lines, each pixel electrode (41) being formed in a respective section defined by a pair of said first lines (23) and a pair of said second lines (21;24), characterised in that : for each pixel electrode (41) there are provided first and second projections (46,43) respectively from a said first and second line, one of said projections overlapping the other, and the second projection (43) having a portion lying beneath the pixel electrode (41), whereby connections can be made between the first and second projections (46,43) and between the second projection (43) and the pixel electrode (41) so as to short the pixel electrode to the first line (23). An active matrix display device according to claim 1, wherein said second lines are gate bus lines (21). An active matrix display device according to claim 2, wherein each said pixel electrode (41) includes a portion (42) which overlaps a said gate bus line (21). An active matrix display device according to claim 1, wherein said second lines are additive capacitance lines (24), and further including third, gate bus lines (21) for the switching elements (31) also extending in a row direction. An active matrix display device according to claim 2 or claim 3, wherein the source bus line (23) comprises said first projection (46) extending toward the pixel electrode (41) in such a manner as to be electrically disconnected from the pixel electrode, and the gate bus line (21) comprises said second projection (43) extending toward the pixel electrode (41), the first, source bus projection (46) being overlaid on the second, gate bus projection (43) with an insulating layer (13) sandwiched therebetween, the gate bus projection (43) being provided with an electroconductive member (44) at the top thereof with an insulating layer (13) sandwiched therebetween, the electroconductive member (44) being electrically connected to the pixel electrode (41), and electrically disconnected from the source bus projection (46). An active matrix display device according to claim 4, wherein the additive capacitance line (24) is formed under the pixel electrode (41) with an insulating layer (13) sandwiched therebetween, the source bus line (23) comprises said first projection (46) extending toward the pixel electrode (41) in such a manner as to be electrically disconnected from the pixel electrode, and the additive capacitance line (24) comprises said second projection (43) extending toward the pixel electrode (41), the first, source bus projection (46) being overlaid on the second, additive capacitance projection (43) with an insulating layer (13) sandwiched therebetween, the additive capacitance projection (43) being provided with an electroconductive member (44) at the top thereof with an insulating layer (13) sandwiched therebetween, the electroconductive member (44) being electrically connected to the pixel electrode (41), and electrically disconnected from the source bus projection (46). An active matrix display device according to claim 2, wherein the source bus line (23) comprises said first projection (46) extending toward the pixel electrode (41) in such a manner as to be electrically disconnected from the pixel electrode, and the gate bus line (21) comprises said second projection (43) extending toward the pixel electrode (41) and whose top end reaches toward a forward end of the first, source bus projection (46), the switching element (31) being formed toward the base end of the second, gate bus projection (43), a middle portion of the gate bus projection (43) being overlaid by the source bus projection (46) with an insulating layer (13) sandwiched therebetween, the gate bus projection (43) being provided with an electroconductive member (44) at the top thereof with an insulating layer (13) sandwiched therebetween, the electroconductive member (44) being electrically connected to the pixel electrode (41), and electrically disconnected from the source bus projection (46). An active matrix display device according to claim 2, wherein the gate bus line (21) comprises a gate bus branch (22), said switching element (31) being formed at the top end of the gate bus branch (22) and connected to the pixel electrode (41), said second projection (43) extends from the one (21b) of said pair of second, gate bus lines other than the one (21a) connected via said switching element (31) to the pixel electrode (41), toward the corner of the pixel electrode (41), said first projection (46) extends from the one (23b) of said pair of first, source bus lines other than the one (23a) connected via said switching element (31) to the pixel electrode (41), toward the corner of the pixel electrode (41), and an electroconductive member (44) overlaid on the end of the second, gate bus projection (43) with an insulating layer sandwiched therebetween and electrically connected to the pixel electrode (41). An active matrix display device according to claim 8, wherein the gate bus branch (22) comprises a larger end portion and smaller portion other than the end portion. An active matrix display device according to any one of the preceding claims, wherein the switching element is a thin film transistor (31). An active matrix display device comprising an insulating substrate (1) on which are formed: a lattice arrangement of source bus lines (23) extending in a column direction and gate bus lines (21) extending in a row direction transverse the source bus lines; a respective pixel electrode (41) within each section defined by an adjacent pair of said source bus lines (23) and an adjacent pair of said gate bus lines (21a,21b); a respective switching element (31) for applying a drive signal to each said pixel electrode, the switching element being connected to the pixel electrode, one of said pair of source bus lines and one of said pair of gate bus lines, characterised by : a structure (43,44,46), other than said switching element, enabling the pixel electrode to be shorted to one of said pair of source bus lines in the event of a fault preventing effective application of said drive signal to the pixel electrode, said structure including a projection (43) from one of said pair of gate bus lines, to which projection said one source line and said pixel electrode may be individually electrically connected. An active matrix display device according to claim 11, wherein a portion of the pixel electrode (41) overlies said gate bus line projection (43) and sandwiches therebetween an insulating layer (13;12,13) formed on the gate bus line projection and a conductive mamber (44) formed over the insulating layer and electrically contacting said portion of the pixel electrode.

Inventors: FUJIHARA TOSHIAKI, FUJIKI HIROSHI, IRIE KATSUMI, KANEMORI YUZURU, KATAYAMA MIKIO, KATO HIROAKI, KONDO NAOFUMI, MARUMOTO HIDEJI, MITSUMOTO KAZUYORI, NAKAZAWA KIYOSHI, NEGOTO HIDENORI, OKAMOTO MASAYA, OTSU KUMIKO, YANO KOZO, FUJIHARA, TOSHIAKI, FUJIKI, HIROSHI, IRIE, KATSUMI, KANEMORI, YUZURU, KATAYAMA, MIKIO, KATO, HIROAKI, KONDO, NAOFUMI, MARUMOTO, HIDEJI, MITSUMOTO, KAZUYORI, NAKAZAWA, KIYOSHI, NEGOTO, HIDENORI, OKAMOTO, MASAYA, OTSU, KUMIKO, YANO, KOZO
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1991
Main classification: G02F1
IPC codes: G02F1