Active filter

Abstract: An input signal is supplied to the non-inverting input terminal of a current differential amplifier (11). A capacitor (Co) is connected between the output terminal of the current differential amplifier (11) and a power source (vss) and the capacitor (Co) stores charges according to an output signal of the current differential amplifier (11). The input signal and an output signal of the current differential amplifier (11) are supplied to resistors (R₅, R₆) via buffer circuits (13, 14) and signals divided by the resistors (R₅, R₆) are added together by a buffer circuit (15) and output from an output terminal (OUT) and at the same time fed back to the inverting input terminal of the current differential amplifier (11).

Description: The present invention relates to an active filter comprising a current differential amplifier (11) having an inverting input terminal, a non-inverting input terminal and an output terminal and supplied with an input signal at the non-inverting input terminal; a capacitor (C 0 ) connected between the output terminal of said current differential amplifier (11) and a power source (V SS ) for storing charges according to an output signal of said current differential amplifier (11); and an adding circuit (12) for adding the input signal and the output signal of said current differential amplifier (11) and for supplying an output signal to an output terminal of said filter and to the inverting input terminal of said current differential amplifier (11). Such active filter is disclosed in Patent Abstracts of Japan, vol. 11, No. 61 (E-483) (2508), 25 February 1987 and JP-A-61 220 517. In addition to the components mentioned above this prior art active filter requires, in addition to resistors and a capacitor, a voltage/current converting circuit, an operational amplifier, a coefficient circuit, and a multiplier circuit. These active circuits and the operational amplifier are each made up of a large number of transistors, resulting in that the prior art active filter circuit configuration is complex, and the manufacturing costs thereof are inevitably high. DE-A-38 30 410 discloses an active filter signal adjustment circuit comprising an input and an output unit, first and second operational amplifiers, a buffer amplifier, first and second adding units, and first and second capacitor units. The problem to be solved by the present invention is to provide an active filter which is simpler in circuit configuration than the prior art and can be manufactured at low costs. The problem is solved by an active filter having the features indicated in independent claim 1. According to a preferred embodiment of the invention indicated in dependent claim 2, the power source is a ground potential. For facilitating to understand the present invention the technical background thereof will be briefly outlined hereinafter. An active filter is known as a filter whose size and weight can be easily reduced. The active filter is a circuit formed of a combination of an operation amplifier, resistor element and capacitor element. Fig. 3 is an equivalent circuit diagram showing the construction of a conventional active filter. An input terminal IN is connected to the input terminal of an amplifier 31 and the non-inverting input terminal of a current differential amplifier (which is hereinafter referred to as a gm amplifier) 32. The output terminal of the amplifier 31 is connected to an output terminal of the gm amplifier 32 and an output terminal OUT via a capacitor Co. Further, the output terminal of the gm anplifier 32 is connected to the inverting input terminal of the gm amplifier 32. Fig. 4 is a circuit diagram showing the concrete construction of the above equivalent circuit and an area surrounded by broken lines on the left hand side indicates the amplifier 31 and an area on the right hand side indicates the gm amplifier 32. In the amplifier 31, the base of a transistor Q 7 is connected to the input terminal IN. The collector of the transistor Q 7 is connected to a power source Vcc and the emitter thereof is connected to the emitter of a transistor Q 8 via a resistor R 3 and to the ground potential Vss via a constant current source I 4 . The emitter of the transistor Q 8 is connected to the ground potential Vss via a constant current source I 5 and the base thereof is connected to the ground potential Vss via a reference power source Vo. Further, the collector of the transistor Q 8 is connected to the power source Vcc via a resistor R 4 and to the base of a transistor Q 9 . The collector of the transistor Q 9 is connected to the power source Vcc and the emitter thereof is connected to the ground potential Vss via a constant current source I 6 . In the gm amplifier 32, the base of a transistor Q 1 is connected to the input terminal IN. The collector of the transistor Q 1 is connected to the power source Vcc and the emitter thereof is connected to the collector and base of a transistor Q 2 via a resistor R1 and to the base of a transistor Q 3 via a resistor R1. The emitter of the transistor Q 2 is connected to the ground potential Vss via a constant current source I 1 and to the emitter of a transistor Q 6 . The collector of the transistor Q 3 is connected to the power source Vcc and the emitter thereof is connected to the emitter of a transistor Q 4 and to the ground potential Vss via a constant current source I 2 . The collector of the transistor Q 4 is connected to the emitter of the transistor Q 9 of the amplifier 31 via the capacitor Co and to the power source Vcc via a constant current source I 3 . Further, the collector of the transistor Q 4 is connected to the base of a transistor Q 5 and to the output terminal OUT. The collector of the transistor Q 5 is connected to the power source Vcc and the emitter thereof is connected to the collector and base of the transistor Q 6 via a resistor R 2 and to the base of the transistor Q 3 via a resistor R2. With the above construction, a signal voltage supplied to the input terminal IN is converted into current by means of the gm amplifier 32 and the capacitor Co is charged or discharged by the converted current. At the same time, the capacitor Co is applied with a voltage corresponding to a signal voltage supplied to the input terminal IN via the amplifier 31. As a result, a voltage obtained by adding a voltage output from the amplifier 31 to the charged voltage of the capacitor Co is output from the output terminal OUT. That is, the signal voltage supplied from the input terminal IN is applied to the base of the NPN transistor Q 1 serving as the non-inverting input terminal of the gm amplifier 32 and to the base of the NPN transistor Q 7 serving as the input terminal of the amplifier 31. Current flowing in the collector-emitter path of the transistor Q 1 permits the transistor Q 2 to be turned on via the resistor R 1 and permits the transistor Q 3 which is one of two transistors constituting the differential pair to be turned on. Further, since the transistor Q 5 is always kept in the conductive state by means of the constant current source I 3 , the transistor Q 6 is turned on by current flowing in the resistor R 2 and the transistor Q 4 which is the other of the two transistors constituting the differential pair is also turned on. The capacitor Co connected to the collector of the transistor Q 4 is charged or discharged by a current difference between the collector currents of the transistors Q 3 and Q 4 and an output signal can be derived from the output terminal OUT. Further, the output signal is fed back to the inverting input terminal of the gm amplifier 32. In the amplifier 31, the transistor Q 8 is biased by the reference voltage Vo and is always kept in the on state and the transistor Q 9 is biased by current flowing in the resistor R 4 and is turned on. If a signal is input to the input terminal IN in this state, the transistor Q 7 is turned on. Since the resistor R 3 is connected between the emitters of the transistors Q 7 and Q 8 , the current flowing in the transistor Q 8 may be varied by means of the resistor R 3 when the emitter current of the transistor Q 7 is changed according to the input signal. The operation of the transistor Q 9 biased by the resistor R 4 is controlled according to variation in the emitter current of the transistor Q 8 . An amount of charges stored in the capacitor Co varies with variation in the emitter current of the transistor Q 9 . In practice, a signal which is obtained by converting a voltage into current by means of the gm amplifier 32 may affect not only the capacitor Co but also the output terminal of the amplifier 31 via the emitter resistor r 9 (not shown) of the transistor Q 9 . As a result, a signal output from the output terminal OUT deviates from a theoretical value. Further, in a case where the capacitor Co is charged according to a signal voltage supplied to the input terminal IN and the charged voltage is added to the signal obtained by converting the voltage into the current, the signal may be made unstable by the emitter resistor r 9 of the transistor Q 9 and the collector impedance Ro of the transistor Q 4 . In order to explain the above defects, the transfer function of the circuit having the construction shown in Fig. 4 is shown by the following equation. In this case, the emitter resistor of each transistor Qn is indicated by r n (n=7, 8, 9) and the collector impedance of the transistor Q 4 is indicated by Ro. Further, if the conductance of the gm amplifier is denoted by gmo, the input voltage is denoted by Vin and the output voltage is denoted by Vout, then the relation between them can be expressed by the following equation. Vout = r 9 + (1/jωCo) gmo (Vin-Vout) + R 4 r 7 + r 8 + R 3 · Ro Ro + r 9 + (1/jωCo) · Vin The above equation (1) can be rewritten as follows: (1 + 1 + jωCor 9 jωCogmo ) Vout = ( 1 + jωCor 9 jωCogmo + R 4 r 7 + r 8 +R 3 × jωCoRo 1 + (Ro+R 9 )jωCo ) Vin If 1/jωCogmo = n/s, R 4 /(r 7 + r 8 + R 3 ) = m, R 9 /gmo = a, and jωCoRo/{1 + (Ro + r 9 )jωCo} = b, then the equation (2) can be rewritten as follows: (1 + n s + a) Vout = (a + n s + mb) Vin In this case, the transfer function Vout/Vin can be expressed as follows: Vout/Vin = n + (a + mb)s n + (1 + a)s ≒ n + ms n + s (where a = 0 and b = 1) As shown in the above equation (4), the signal becomes equal to the theoretical value only when a=0 and b=1, and this condition is satisfied when the emitter resistor r 9 of the transistor Q 9 in Fig. 4 is neglected and the collector impedance of the transistor Q 4 is regarded as being infinite. As has been described, in the conventional active filter, the amplifier 31 is connected to the gm amplifier 31 by means of the capacitor Co. The amplifiers 31 and 32 inevitably interfere with each other. Consequently, the magnitude of the signal output by the active filter deviates from the theoretical value. An advantage of this invention is to provide an active filter capable of deriving an output signal which is equal to the theoretical value. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is an equivalent circuit diagram of the construction according to one embodiment of this invention; Fig. 2 is a circuit diagram showing the concrete construction of the circuit shown in Fig. 1; Fig. 3 is an equivalent circuit diagram showing the construction of the conventional active filter; and Fig. 4 is a circuit diagram showing the concrete construction of the circuit shown in Fig. 3. There will now be described an embodiment of this invention with reference to the accompanying drawings. Fig. 1 is an equivalent circuit diagram showing the construction according to one embodiment of an active filter of this invention and shows a high-pass filter (HPF) or rig type high-pass filter. An input terminal IN is connected to the non-inverting input terminal of a current differential amplifier (gm amplifier) 11 and to the input terminal of a first buffer circuit 13. The output terminal of the gm amplifier 11 is connected to the ground potential Vss via a capacitor Co and to the input terminal of a second buffer circuit 14. The output terminals of the buffer circuits 13 and 14 are connected to the input terminal of a third buffer circuit 15 via first and second resistors R 5 and R 6 , respectively. The output terminal of the buffer circuit 15 is connected to the output terminal OUT and to the inverting input terminal of the gm amplifier 11. Fig. 2 is a circuit diagram showing the concrete construction of the circuit shown in Fig. 1, and portions which are the same as those of Fig. 1 are denoted by the same reference numerals. In the gm amplifier 11, the base of an NPN transistor Q 1 serving as the non-inverting input terminal is connected to the input terminal IN. The collector of the transistor Q 1 is connected to the power source Vcc, and the emitter thereof is connected to the base and collector of an NPN transistor Q 2 via a resistor R1 and to the base of an NPN transistor Q 3 via this resistor R1. The emitter of the transistor Q 2 is connected to the ground potential Vss via a constant current source I 1 . The collector of the transistor Q 3 is connected to the power source Vcc and the emitter thereof is connected to the emitter of a transistor Q 4 and to the ground potential Vss via a constant current source I 2 . The collector of the transistor Q 4 is connected to the ground potential Vss via the capacitor Co and to the power source Vcc via a constant current source I 3 and the base thereof is connected to the base and collector of a transistor Q 6 . The emitter of the transistor Q 6 is connected to the emitter of the transistor Q 2 and the collector thereof is connected to the emitter of an NPN transistor Q 5 via the resistor R 2 . The base of the transistor Q 5 is used as the inverting input terminal of the gm amplifier 11 and is connected to the output terminal OUT. The collector of the transistor Q 5 is connected to the power source Vcc. In an adding circuit 12, the base of an NPN transistor Q 10 constituting the first buffer circuit 13 is connected to the input terminal IN. The collector of the transistor Q 10 is connected to the power source Vcc and the emitter thereof is connected to the ground potential Vss via a constant current source I 7 and to the base of a transistor Q 12 constituting the third buffer circuit 15 via the resistor R 5 . The collector of the transistor Q 12 is connected to the ground potential Vss and the emitter thereof is connected to the output terminal OUT and to the power source Vcc via a constant current source I 9 . Further, the base of a transistor Q 11 constituting the second buffer circuit 14 is connected to the collector of the transistor Q 4 and the collector thereof is connected to the power source Vcc. The emitter of the transistor Q 11 is connected to the base of the transistor Q 12 via the resistor R 6 and to the ground potential Vss via a constant current source I 8 . Now, the operation of the circuit with the above construction is explained. The base of the transistor Q 5 in the gm amplifier 11 is supplied with current fed back from the output terminal A of the buffer circuit 15. The current flowing in the collector-emitter path of the transistor Q 5 turns on the transistor Q 6 via the resistor R 2 , thereby causing the transistor Q 4 which is one of the two transistors constituting the differential pair to be turned on. A signal voltage supplied to the input terminal IN is applied to the base of the transistor Q 1 and the base of the transistor Q 10 constituting the buffer circuit 13. The current flowing in the collector-emitter path of the transistor Q 1 causes the transistor Q 2 to be turned on via the resistor R 1 , thus causing the transistor Q 3 which is one of the two transistors constituting the differential pair to be turned on. As a result, charges of an amount corresponding to a difference between the collector currents of the transistors Q 3 and Q 4 are stored in the capacitor Co. The emitter current of the transistor Q 10 which is turned on by the signal voltage supplied to the input terminal IN and the emitter current of the transistor Q 11 which is turned on by an output of the gm amplifier 11 are supplied to the base in the buffer circuit 15 via the resistors R 5 and R 6 , respectively, so as to turn on the transistor Q 12 . That is, a signal output from the gm amplifier 11 and a signal voltage from the input term,trial IN are added together at a rate corresponding to the dividing ratio of the resistors R 6 and R 5 . As a result, a signal obtained by adding a signal of a given level to the signal which is converted into the current form is output from the output terminal OUT. According to the above embodiment, one end of the capacitor Co is grounded and it does not connect the gm amplifier 11 and adding circuit 12 to each other. Therefore, the capacitor Co will not affect the theoretical value of a signal output from the output terminal OUT and will not affect a feedback signal supplied to the inverting input terminal of the gm amplifier 11. Next, the transfer function of the circuit in this embodiment is explained. In this case, if the load resistance in each of the transistors Qn (n = 1 to 6 and 10 to 12) is denoted by r n (n = 1 to 6 and 10 to 12), the conductance gm of the gm amplifier 11 is denoted by gmo, the input voltage is denoted by Vin, and the output voltage is denoted by Vout, then the relation of these factors can be expressed by the following equation. Vout = 1/jωCo gmo (Vin - Vout) + 1/jωCo gmo (Vin - Vout) · r 10 + R 5 r 10 + r 11 + R 5 + R 6 + r 11 + R 6 r 10 + r 11 + R 5 · Vin In this case, if 1/jωCogmo = n 1 /s and (r 10 + R 5 )/(r 10 + r 11 + R 5 + R 6 ) = m 1 , then the equation (5) can be rewritten as follows: (1 + n 1 s + n 1 s m 1 ) Vout = ( n 1 s + n 1 s m 1 + 1 - m 1 ) Vin Further, the transfer function Vout/Vin can be expressed by the following equation: Vout/Vin = n 1 + (1 + m 1 ) + (1 - m 1 )s n 1 (1 + m 1 ) + s In this case, if 1 + m 1 = m and n 1 (1 + m 1 ) = n, then the equation (7) can be rewritten as follows: Vout Vin = n + ms n + s As shown by the equation (7), according to this embodiment, an active filter in which an output equal to the theoretical value can be derived can be obtained. The gm amplifier, buffer circuit and the like in the circuit of the above embodiment are not limited to those shown in the above embodiment and various modifications can be made. Further, in the above embodiment, the capacitor Co is connected between the collector of the transistor Q 4 and the ground potential Vss, but it can be connected between the collectors of the transistors Q 3 and Q 4 , for example, so as to attain the same effect of the above embodiment.

Claims: An active filter comprising: a current differential amplifier (11) having an inverting input terminal, a non-inverting input terminal and an output terminal and supplied with an input signal at the non-inverting input terminal; a capacitor (Co) connected between the output terminal of said current differential amplifier (11) and a power source (V SS ) for storing charges according to an output signal of said current differential amplifier (11); and an adding circuit (12) for adding the input signal and the output signal of said current differential amplifier (11) and for supplying an output signal to an output terminal of said filter and to the inverting input terminal of said current differential amplifier (11); characterized in that said adding circuit (12) comprises: first and second resistors (R 5 , R 6 ) for adding the input signal and the output signal of said current differential amplifier (11) at a rate corresponding to the dividing ratio of said resistors (R 5 , R 6 ); and said adding circuit (12) further comprises: a first buffer circuit (13) having an input terminal connected to the non-inverting input terminal of said current differential amplifier (11); the first resistor (R 5 ) being connected at one end thereof to an output terminal of said first buffer circuit (13); a second buffer circuit (14) having an input terminal connected to the output terminal of said current differential amplifier (11); the second resistor (R 6 ) being connected at one end thereof to an output terminal of said second buffer circuit (14); and a third buffer circuit (15) having an input terminal connected to the other end of said first and second resistors (R 5 , R 6 ) and an output terminal connected to the output terminal of said filter and to the inverting input terminal of said current differential amplifier (11). An active filter according to claim 1, characterized in that said power source is a ground potential (V SS ).

Inventors: HAGINO HIDEYUKI, HAGINO, HIDEYUKI, HAGINO, HIDEYUKI, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: H03H11
IPC codes: H03H11