Analog multiplier

Abstract: A multiplier comprises first and second squaring circuits each including first and second MOS transistors having their sources connected in common and third and fourth MOS transistors having their sources connected in common. The first and third transistors have a first gate W/L ratio and have their drains connected to each other, and the second and fourth transistors have their drains connected to each other and have a second gate W/L ratio different from the first ratio. Gates of the first and fourth transistors are connected to each other, and gates of the second and third transistors are connected to each other. A first input signal is supplied to the gates of the first and fourth transistors of each of the first and second squaring circuits, and a second input signal is supplied, without being inverted, to the gates of the second and third transistors of the first squaring circuit, and without being inverted, to the gates of the second and third transistors of the second squaring circuit. The drains of the first and third transistors of each of the squaring circuits are connected to the second and fourth transistors of the other squaring circuits. A multiplication of the first and second input signals is given by a difference between a current flowing into the drains of the first and third transistors of the first squaring circuits and the drains of the second and fourth transistors of the second squaring circuits, and another current flowing into the drains of the second and fourth transistors of the first squaring circuits and the drains of the first and third transistors of the second squaring circuits.

Description: Background of the Invention Field of the invention The present invention relates to a multiplier, and more specifically to an analog multiplier for multiplying two analog input signals. Description of related art In the prior art, one typical analog multiplier using a Gilbert's circuit as shown in Figure 1 has been known. In the circuit shown in Figure 1, a first differential circuit is composed of a pair of transistors M 21 and M 22 having their sources connected to each other, and a second differential circuit is composed of a pair of transistors M 23 and M 24 having their sources connected to each other. Drains of the transistors M 21 and M 23 are connected to each other, and drains of the transistors M 22 and M 24 are connected to each other. In addition, gates of the transistors M 21 and M 24 are connected to each other, and gates of the transistors M 22 and M 23 are connected to each other. A first input signal V 1 is applied between the gates of the transistors M 21 and M 24 and the gates of the transistors M 22 and M 23 , so that the input signal is applied to the first differential circuit in a non-inverted polarity and to the second differential circuit in an inverted polarity. The common-connected sources of the transistors M 21 and M 22 are connected to a drain of a transistor M 25 , and the common-connected sources of the transistors M 23 and M 24 are connected to a drain of a transistor M 26 . Sources of the transistors M 25 and M 26 are connected to each other, so that a third differential circuit is formed. The common-connected sources of the transistors M 25 and M 26 are connected through a constant current source 21 to ground. A second input signal V 2 is applied between the gate of the transistor M 25 and the gate of the transistor M 26 . Now, operation of the multiplier as mentioned above will be described. First, assume that gate widths of the transistors M 21 , M 22 , M 23 , M 24 , M 25 and M 26 are W 21 , W 22 , W 23 , W 24 , W 25 and W 26 , respectively, and gate lengths of the transistors M 21 , M 22 , M 23 , M 24 , M 25 and M 26 are L 21 , L 22 , L 23 , L 24 , L 25 and L 26 , respectively. The gate widths and the gates lengths of the transistors M 21 , M 22 , M 23 , M 24 , M 25 and M 26 are set as follows: W 21 L 21 = W 22 L 22 = W 23 L 23 = W 24 L 24 W 25 L 25 = W 26 L 26 In addition, by expressing a mobility of the transistors by µ n and a thickness of a gate capacitance per unit area by C ox , factors α 1 and α 2 are defined as follows: α 1 = µ n C ox 2 W 21 L 21 α 2 = µ n C ox 2 W 25 L 25 Furthermore, assume that a threshold voltage of the transistors M 21 , M 22 , M 23 , M 24 , M 25 and M 26 is V t , and gate-to-source voltages of the transistors M 21 , M 22 , M 23 , M 24 , M 25 and M 26 are V gs21 , V gs22 , V gs23 , V gs24 , V gs25 and V gs26 , respectively. Under these conditions, drain currents I d21 , Id 24 , I d23 , I d24 , I d25 and I d26 of the transistors M 21 , M 22 , M 23 , M 24 , M 25 and M 26 are expressed as follows: I d21 = α 1 (V gs21 -V t ) 2 I d22 = α 1 (V gs22 -V t ) 2 I d23 = α 1 (V gs23 -V t ) 2 I d24 = α 1 (V gs24 -V t ) 2 I d25 = α 1 (V gs25 -V t ) 2 I d26 = α 1 (V gs26 -V t ) 2 Here, the drain currents I d21 , I d22 , I d23 , I d24 , I d25 and I d26 and the gate-to-source voltages V gs21 , V gs22 , V gs23 , V gs24 , V gs25 and V gs26 have the relation expressed by the following equations: I d21 + I d22 = I d25 I d23 + I d24 = I d26 I d25 + I d26 = I 0 V gs21 - V gs22 = V gs24 - V gs23 = V 1 V gs25 - V gs26 = V 2 Thus, the following equation (16) can be derived: I d25 - I d26 = α 2 V 2 2I 0 α 2 - V 2 2 Here, assuming I d25 - I d26 = I V2 , the following equations (17) and (18) can be derived from the equations (13) and (16): I d25 = 1 2 (I 0 + I V2 ) I d26 = 1 2 (I 0 - I V2 ) On the other hand, I V1 is defined by the following equation (19): I V1 = α 1 V 1 I 0 α 2 - V 1 2 This equation (19) can be modified as follows: V 1 2 = I 0 ± I 0 2 - 4I V1 2 2α 1 Thus, the following equation (21) can be derived: This equation (21) can be simplified as follows: First, functions f(x), g(x) and h(x) of "x" can be defined as follows: f(x) = 1 + ax g(x)= 1 - ax h(x) = f(x) - g(x) The equation (24) can be developed into the form of a series: h(x) = h(0) + x 1! h'(0) + x 2 2! h"(0) + ··· = {f(0) - g(0)} + x 1! {f'(0) - g'(0)} + x 2 2! {f''(0) - g''(0)} +··· Here, f'(0), f''(0), ··· and g'(0), g''(0), ··· can be respectively obtained as follows: f'(x) = 1 2 a 1 + ax ∴ f'(0) = a 2 f"(x) = - 1 4 a 2 (1 + ax) 1 + ax ∴ f"(0) = - a 2 4 g'(x) = - 1 2 a 1 - ax ∴ g'(0) = - a 2 g''(x) = - 1 4 a 2 (1 - ax) 1 - ax ∴ g''(0) = - a 2 4 In addition, since f(0) = g(0) = 1, h(0) = 0 As a result, the equation (25) can be expressed as follows: h(x) = ax + · · · · Accordingly, similarly to the above, the equation (21) can be expressed as the following equation (32): I 1 - I 2 = I V1 I V2 · 1 2 I V2 I V1 2 {I 0 ± I 0 - 4I V1 2 } + ··· On the other hand, by referring to the equations (19) and (20), the equation (32) can be modified as the following equation (33): I 1 - I 2 = I V1 ·I V2 2 α 1 ( I 0 α 1 -V 1 2 ) + ··· Here, if the second and succeeding items (not shown) in the equation (33) are ignored, and if it is assumed that since V 1 is very small, V 1 2 ≈ 0, the equation (33) can be simplified as follows: I 1 - I 2 ≒ 2 I 0 • I V1 •I V2 Here, I V1 corresponds to a differential output current (transfer curve) of the differential amplifier driven with a half (Io/2) of the constant current Io so as to respond to the input voltage V 1 , and I V2 corresponds to a differential output current (transfer curve) of the differential amplifier driven with a half (Io/2) of the constant current Io so as to respond to the input voltage V 2 . The transfer curve of the differential amplifier can be regarded to be linear if the input voltage is small. Therefore, a multiplication characteristics can be obtained from the equation (34) in a range in which the input voltages V 1 and V 2 are small. In addition, it will be apparent from the equation (33) that a voltage range allowing the multiplier to have a good linearity is narrower in the input voltage V 1 than in input voltage V 2 . Furthermore, if the multiplier is composed of transistors having the same size, the operating ranges of the two input voltages V 1 and V 2 have a relation of V 1 = V 2 / 2 . If the equation (33) is further developed in the form of a series, the following can be obtained: I 1 - I 2 = I V1 ·I V2 · 2 I 0 {1 + α 1 I 0 V 1 2 + α 1 2 I 0 2 V 1 4 + ···} = α 1 I 1 V 1 {1 + α 1 2I 0 V 1 2 - α 1 2 4I 0 2 V 1 4 + ···} × 2α 2 I 0 V 2 {1 + α 2 4I 0 V 2 2 - α 2 2 16I 0 2 V 2 4 + ···} × 2 I 0 {1 + α 1 I 0 V 1 2 + α 1 2 I 0 2 V 1 4 + ···} = 2 2α 1 α 2 V 1 {1 + α 1 I 0 V 1 2 + α 1 2 4I 0 V 1 4 + ···} × V 2 {1 - α 2 4I 0 V 2 2 - α 2 2 16I 0 2 V 2 4 + ··· } Here, if all of items including a second-order and higher orders of the input voltages V 1 and V 2 are neglected, the equation (35) can be expressed as the following equation (36): I 1 - I 2 ≒ 2 2α 1 α 2 • V 1 • V 2 Therefore, this multiplier can give the result of multiplication of the input voltages V 1 and V 2 in the form of I 1 - I 2 . Soo, D.C. et al.: "A four quadrant NMOS Analog Multiplier" IEEE Journal of Solid-State Circuits, Vol. SC-17, No. 6, December 1982, pages 1174-1178 discloses a conventional four-quadrant NMOS analog multiplier based on cascaded MOS differential pairs. Referring to Figure 2, there is shown a circuit diagram of another conventional multiplier, which was disclosed in "A Four-Quadrant MOS Analog Multiplier", Jesus Pena-Finol et al, 1987, IEEE International Solid-State cct, Conf. THPM17.4. A first input voltage V 1 is applied between gates of input transistors M 31 and M 32 having their sources connected to each other, and the common-connected sources of the transistors M 31 and M 32 are connected to a low voltage V SS through a transistor M 55 acting as a constant current source. Drains of the transistors M 31 and M 32 are connected to a high voltage V DD through transistors M 35 and M 36 , respectively. A second input voltage V 2 is applied between gates of input transistors M 33 and M 34 having their sources connected to each other, and the common-connected sources of the transistors M 33 and M 34 are connected to the low voltage V SS through a transistor M 54 acting as a constant current source. Drains of the transistors M 33 and M 34 are connected to the high voltage V DD through transistors M 37 and M 38 , respectively. A gate of the transistor M 37 is connected to a drain of the transistor M 37 itself and a gate of the transistor M 38 is connected to a drain of the transistor M 38 itself. Sources of the transistors M 37 and M 38 are connected to gates of the transistors M 35 and M 36 , respectively. The above mentioned transistors constitute a first differential input summing circuit. Furthermore, the first input voltage V 1 is also applied between gates of input transistors M 41 and M 42 having their sources connected to each other, and the common-connected sources of the transistors M 41 and M 42 are connected to the low voltage V SS through a transistor M 51 acting as a constant current source. Drains of the transistors M 41 and M 42 are connected to the high voltage V DD through transistors M 45 and M 46 , respectively. In addition, there is provided a pair of transistors M 43 and M 44 having their sources connected to each other. The common-connected sources of the transistors M 43 and M 44 are connected to the low voltage V SS through a transistor M 52 acting as a constant current source. Drains of the transistors M 43 and M 44 are connected to the high voltage V DD , respectively, through transistors M 47 and M 48 connected in the form of a load in such a manner that a gate of the transistor M 47 is connected to a drain of the transistor M 47 itself and a gate of the transistor M 48 is connected to a drain of the transistor M 48 itself. Sources of the transistors M 47 and M 48 are connected to gates of the transistors M 45 and M 46 , respectively. The above mentioned transistors constitute a second differential input summing circuit. The second input voltage V 2 is inverted by a differential circuit composed of transistors M 59 , M 60 , M 61 , M 62 and M 63 connected as shown. Outputs of this differential circuit are applied as a second input for the second differential input summing circuit. Thus, the first differential input summing circuit receives the input voltages V 1 and V 2 , and outputs (V 1 + V 2 ). On the other hand, the second differential input summing circuit receives the input voltages V 1 and -V 2 , and outputs (V 1 - V 2 ). These outputs of the first and second differential input summing circuits are supplied to a double differential squaring circuit composed of the transistors M 39 , M 40 , M 49 and M 50 and resistors R L11 and R L12 . An output Vo of this double differential squaring circuit is expressed by the following equation (37): V 0 = K [(V 1 + V 2 ) 2 - (V 1 - V 2 ) 2 ] = µ n C ox 2 (W/L) 3 (W/L) 1 (W/L) 2 V 1 • V 2 where (W/L) 1 is a ratio of a gate width to a gate length in the transistors M 31 to M 34 and M 42 to M 44 ; (W/L) 2 is a ratio of a gate width to a gate length in the transistors M 35 to M 38 and M 45 to M 48 ; (W/L) 3 is a ratio of a gate width to a gate length in the transistors M 39 , M 40 , M 49 and M 50 . It will be seen from the equation (37) that a result of multiplication between the input voltages V 1 and V 2 can be obtained from the circuit shown in Figure 2. The above mentioned conventional multipliers have the following disadvantages: The multiplier using the Gilbert circuit as shown in Figure 1 is disadvantageous in that the linearity to the first input voltage V 1 is not so good, as seen from the equation (33). Turning to Figure 3, there is shown a graph illustrating the result of simulation of the characteristics of the multiplier shown in Figure 1. This simulation was made under a condition in which a processing condition is Tox = 320Å (Tox is gate oxide thickness) and W/L=50µm/5µm. The result of simulation shows that the linearity can be obtained in a range of -0.2V < V 1 < 0.2V. In the multiplier shown in Figure 2, the differential input summing circuits are not so good in linearity, because of unbalance in circuit structure between the differential input summing circuits corresponding to the input voltages V 1 and V 2 , respectively. In addition, a range of the double differential squaring circuit having a square-law characteristics is determined by a circuit structure, and is limited to an extent of -0.5V < V 1 , V 2 < 0.5V. Summary of the Invention Accordingly, it is an object of the present invention to provide a multiplier which has overcome the above mentioned defect of the conventional one. Another object of the present invention is to provide a multiplier having an excellent linearity and an enlarged range of the multiplication characteristics. The above and other objects of the present invention are achieved in accordance with the present invention by a multiplier comprising: a first squaring circuit including first and second transistors having a first gate width-to-gate length ratio and having their drains connected to each other, and third and fourth transistors having their drains connected to each other and having a second gate width-to-gate length ratio different from the first gate width-to-gate length ratio, gates of the first and fourth transistors being connected to each other and connected in common to receive a first input signal, and gates of the second and third transistors being connected to each other and connected in common to receive an inverted signal of a second input signal, sources of the first and third transistors being connected to each other and sources of the second and fourth transistors being connected to each other, so that two sets of unbalanced differential circuits are formed, and a squared value of a difference between the first input signal and the inverted signal of the second input signal is outputted; a second squaring circuit including fifth and sixth transistors having a third gate width-to-gate length ratio and having their drains connected to each other, and seventh and eighth transistors having their drains connected to each other and having a fourth gate width-to-gate length ratio different from the third gate width-to-gate length ratio, gates of the fifth and eighth transistors being connected to each other and connected in common to receive the first input signal, and gates of the sixth and seventh transistors being connected to each other and connected in common to receive the second input signal, sources of the fifth and seventh transistors being connected to each other and sources of the sixth and eighth transistors being connected to each other, so that two sets of unbalanced differential circuits are formed, and a squared value of a difference between the first input signal and the second input signal is outputted; and a subtracting circuit receiving the outputs of the first and second squaring circuit for subtracting the output of the second squaring circuit from the output of the first squaring circuit. Here, assuming that the first input signal is V 1 and the second input signal is V 2 , the first squaring circuit outputs (V 1 + V 2 ) 2 , and the second squaring circuit outputs (V 1 - V 2 ) 2 . Therefore, the subtracting circuit outputs 4V 1 V 2 corresponding to a multiplied value between the first and second signals. The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings. Brief Description of the Drawings Figure 1 is a circuit diagram of one typical analog multiplier using a Gilbert's circuit; Figure 2 is a circuit diagram of another conventional multiplier; Figure 3 is shown a graph illustrating the result of simulation of the characteristics of the multiplier shown in Figure 1; Figure 4 is a block diagram of the analog multiplier in accordance with the present invention; Figure 5 is a circuit diagram of one embodiment of the the analog multiplier in accordance with the present invention; and Figure 6 is shown a graph illustrating the result of simulation of the characteristics of the multiplier shown in Figure 5. Description of the Preferred Embodiments Referring to Figure 4, there is shown a block diagram of the analog multiplier in accordance with the present invention. The shown multiplier includes first and second squaring circuits 1 and 2 and a subtracting circuit for obtaining a difference between outputs of the squaring circuits 1 and 2. Each of the squaring circuits 1 and 2 includes first and second pairs of unbalanced differential circuits each of which is composed of a pair of transistors having different ratios of a gate width (W) to a gate length (L) and having their sources connected to each other, a gate of each transistor of the first unbalanced differential circuit being connected to a gate of a transistor which is included in the second differential circuit and which has the W/L ratio different from that of that transistor of the first unbalanced differential circuit, and a drain of each transistor of the first unbalanced differential circuit being connected to a drain of a transistor which is included in the second differential circuit and which has the same W/L ratio different as that of that transistor of the first unbalanced differential circuit. The first squaring circuit 1 is connected to receive, as a differential input signal, a first input voltage V 1 , and an inverted voltage -V 2 of a second input voltage V 2 . On the other hand, the second squaring circuit 2 is connected to receive the first input voltage V 1 and the second input voltage V 2 as a differential input signal. The output of the first and second squaring circuits 1 and 2 are connected to the subtracting circuit 3, which generates an output voltage Vo indicative of the result of multiplication. With the above mentioned arrangement, the first and second squaring circuits 1 and 2 receive differential input signals (V 1 + V 2 ) and (V 1 - V 2 ), respectively, and therefore, output (V 1 + V 2 ) 2 and (V 1 - V 2 ) 2 , respectively. Accordingly, the outputs of the squaring circuits 1 and 2 are subtracted by means of the subtracting circuit 3, so that the result of multiplication as shown in the following equation (41) can be obtained; Vo = (V 1 + V 2 ) 2 - (V 1 -V 2 ) 2 = 4 V 1 V 2 Referring to Figure 5, there is shown a detailed circuit diagram of a second embodiment of the multiplier in accordance with the present invention. In the circuit shown in Figure 5, the first input signal V 1 is applied to a first differential amplifier circuit 4, which includes a pair of transistors M 1 and M 2 having their sources connected to each other. More specifically, the first input signal V 1 is applied between gates of the transistors M 1 and M 2 . The first differential amplifier circuit 4 also includes a constant current source 11 (Io) connected between the common-connected sources of the transistors M 1 and M 2 and ground, and resistors R L1 and R L2 connected between a high voltage supply voltage V DD and drains of the transistors M 1 and M 2 , respectively. On the other hand, the second input signal V 2 is applied to a second differential amplifier circuit 5, which includes a pair of transistors M 3 and M 4 having their sources connected to each other. More specifically, the second input signal V 2 is applied between gates of the transistors M 3 and M 4 . The second differential amplifier circuit 5 also includes a constant current source 12 (Io) connected between the ground and the common-connected sources of the transistors M 3 and M 4 , and resistors R L3 and R L4 connected between the high voltage supply voltage V DD and drains of the transistors M 3 and M 4 , respectively. A non-inverted output of the first differential amplifier circuit 4 is connected to a first input of each of a first squaring circuit 6 and a second squaring circuit 7. A non-inverted output of the second differential amplifier circuit 5 is connected to a second input of the second squaring circuit 7. On the other hand, an inverted output of the second differential amplifier circuit 5 is connected to a second input of the first squaring circuit 6. The first squaring circuit 6 includes two pairs of transistors M 5 and M 6 and M 7 and M 8 , each pair constituting an unbalanced differential transistor pair having common-connected sources. The first squaring circuit 6 also includes a constant current source 13 (I 01 ) connected between the ground and the common-connected sources of the transistors M 5 and M 6 , and another constant current source 14 (I 01 ) connected between the ground and the common-connected sources of the transistors M 7 and M 8 . Drains of the transistors M 5 and M 7 are connected to each other, and drains of the transistors M 6 and M 8 are connected to each other. In addition, gates of the transistors M 5 and M 8 are connected to each other, and gates of the transistors M 6 and M 7 are connected to each other. The gates of the transistors M 5 and M 8 are connected to receive the non-inverted output of the first differential amplifier circuit 4, and the gates of the transistors M 6 and M 7 are connected to receive the inverted output of the second differential amplifier circuit 5. The second squaring circuit 7 includes two pairs of transistors M 9 and M 10 and M 11 and M 12 , each pair constituting an unbalanced differential transistor pair having common-connected sources. The second squaring circuit 7 also includes a constant current source 15 (I 01 ) connected between the ground and the common-connected sources of the transistors M 9 and M 10 , and another constant current source 16 (I 01 ) connected between the ground and the common-connected sources of the transistors M 11 and M 12 . Drains of the transistors M 9 and M 11 are connected to each other, and drains of the transistors M 10 and M 12 are connected to each other. In addition, gates of the transistors M 9 and M 12 are connected to each other, and gates of the transistors M 10 and M 11 are connected to each other. The gates of the transistors M 9 and M 12 are connected to receive the non-inverted output of the first differential amplifier circuit 4, and the gates of the transistors M 10 and M 11 are connected to receive the non-inverted output of the second differential amplifier circuit 5. Outputs of the two squaring circuits 6 and 7 are connected to each other in an inverted phase. Namely, the drains of the transistors M 5 , M 7 , M 10 and M 12 are connected in common, and the drains of the transistors M 6 , M 8 , M 9 and M 11 are connected in common. Now, operation of the above mentioned multiplier will be described. First, assume that gate widths of the transistors M 1 , M 2 , M 3 and M 4 are W 1 , W 2 , W 3 and W 4 , respectively, and gate lengths of the transistors M 1 , M 2 , M 3 and M 4 are L 1 , L 2 , L 3 and L 4 , respectively. The gate widths and the gates lengths of the transistors M 1 , M 2 , M 3 and M 4 are set as follows: W 1 L 1 = W 2 L 2 = W 3 L 3 = W 4 L 4 In addition, by expressing a mobility of the transistors by µ n and a thickness of a gate oxide film by Cox, a factor α 1 is defined as follows: α 1 = µ n C ox 2 W 1 L 1 Furthermore, assume that a threshold voltage of the transistors M 1 , M 2 , M 3 and M 4 is V t , and gate-to-source voltages of the transistors M 1 , M 2 , M 3 and M 4 are V gs1 , V gs2 , V gs3 and V gs4 , respectively. Under these conditions, drain currents I d1 , I d2 , I d3 and Id 4 of the transistors M 1 , M 2 , M 3 and M 4 are expressed as follows: I d1 = α 1 (V gs1 - V t ) 2 I d2 = α 1 (V gs2 -V t ) 2 I d3 = α 1 (V gs3 - V t ) 2 I d4 = α 1 (V gs4 - V t ) 2 Here, the drain currents I d1 , I d2 , Id 3 and Id 4 and the gate-to-source voltages V gs1 , V gs2 , V gs3 and V gs4 have the relation expressed by the following equations: I d1 + I d2 = I 0 I d3 + I d4 = I 0 V gs1 - V gs2 = V 1 V gs3 - V gs4 = V 2 From the equations (44) to (51), an equation indicating a transfer curve of a differential MOS transistor pair can be obtained as follows: I d1 - I d2 = α 1 V 1 2I 0 α 1 - V 1 2 I d3 - I d4 = α 1 V 2 2I 0 α 1 - V 2 2 Therefore, assuming that the values of all the resistors R L1 , R L2 , R L3 and R L4 are equal to each other and expressed by R L , an input voltage ΔV IN1 applied to the first squaring circuit 6 composed of the transistors M 5 , M 6 , M 7 and M 8 is expressed by the following equation (54). ΔV IN1 = (V DD - R L ·I d2 ) - (V DD - R L ·I d3 ) = R L ·(I d3 - I d2 ) Similarly, an input voltage ΔV IN2 applied to the second squaring circuit 7 composed of the transistors M g , M 10 , M 11 and M 12 is expressed as follows: ΔV IN2 = (V DD - R L ·I d2 ) - (V DD - R L ·I d4 ) = R L ·(I d4 - I d2 ) Next, explanation will be made about the fact that the circuit composed of the transistors M 5 , M 6 , M 7 and M 8 functions as a squaring circuit. First, assume that gate widths of the transistors M 5 , M 6 , M 7 and M 8 are W 5 , W 6 , W 7 and W 8 , respectively, and gate lengths of the transistors M 5 , M 6 , M 7 and M 8 are L 5 , L 6 , L 7 and L 8 , respectively. The gate widths and the gates lengths of the transistors M 5 , M 6 , M 7 and M 8 are set to fulfil the following condition: W 6 /L 6 W 5 /L 5 = W 8 /L 8 W 7 /L 7 = k (> 1) On the other hand, α 2 is defined as follows: α 2 = µ n C ox 2 W 5 L 5 In addition, assume that a threshold voltage of the transistors M 5 , M 6 , M 7 and M 8 is V t , and gate-to-source voltages of the transistors M 5 , M 6 , M 7 and M 8 are V gs5 , V gs6, V gs7 and V gs8 , respectively. Under these conditions, drain currents I d5 , I d6 , I d7 and I d8 of the transistors M 5 , M 6 , M 7 and M 8 can be expressed as follows: I d5 = α 2 (V gs5 - V t ) 2 I d6 = kα 2 (V gs6 - V t ) 2 I d7 = α 2 (V gs7 - V t ) 2 I d8 = kα 2 (V gs8 - V t ) 2 Here, the drain currents I d5 , I d6 , I d7 and I d8 and the gate-to-source voltages V gs5 , V gs6 , V gs7 and V gs8 have the relation expressed by the following equations (62) to (64): I d5 + I d6 = I 01 I d7 + I d8 = I 01 V gs5 - V gs6 = V gs8 - V gs7 = ΔV IN1 From the equations (58) to (64), the following equation can be derived: Accordingly, a differential output current (Ip - Iq) 1 of the squaring circuit 6 can be obtained as follows: (I p - I q ) 1 = (I d5 + I d7 ) - (I d6 + I d8 ) = (I d5 - I d6 ) + (I d7 - I d8 ) = - 2 (1 + 1 k ) 2 (1 - 1 k ) {(1 + 1 k ) I 01 - 2α 2 (Δ V IN1 ) 2 } It will be seen from the equation (67) that the differential output current is in proportion to a square of the input voltage ΔV IN1 . Similarly, a differential output current (Ip - Iq) 2 of the squaring circuit 7 formed of the transistors M 9 , M 10 , M 11 and M 12 can be obtained as follows: (I p - I q ) 2 = (I d9 + I d11 ) - (I d10 + I d12 ) = (I d9 - I d10 ) + (I d11 - I d12 ) = - 2 (1 + 1 k ) 2 (1 - 1 k ) {(1 + 1 k ) I 01 - 2α 2 (Δ V IN2 ) 2 } As mentioned hereinbefore, since the differential output currents (Ip - Iq) 1 and (Ip - Iq) 2 of the squaring circuits 6 and 7 are summed in an inverted phase or polarity to each other, a different output current ΔIo is expressed as follows: ΔI 0 = I 1 - I 2 = (I p - I q ) 2 - (I p - I q ) 2 = - 2 (1- 1 k ) {(1 + 1 k ) I 01 - 2α 2 (Δ V IN1 ) 2 } (1 + 1 k ) 2 + 2 (1- 1 k ) {(1 + 1 k ) I 01 - 2α 2 (Δ V IN2 ) 2 } (1 + 1 k ) 2 = 2(1- 1 k ) (1+ 1 k ) 2 2α 2 {(ΔV IN1 ) 2 - (ΔV IN2 ) 2 } Here, if this equation (69) is substituted with the equations (54) and (55), the following equation (70) can be obtained. ΔI 0 = 2(1- 1 k ) (1+ 1 k ) 2 2α 2 [{R L (I d3 - I d2 )} 2 - {R L (I d4 - I d2 )} 2 ] = 4α 2 R L 2 (1- 1 k ) (1 + 1 k ) 2 (I d3 - I d4 ) (I d3 + I d4 - 2I d2 ) In addition, if the equation (49) is substituted into the equation (70), the following equation (71) can be obtained: ΔI 0 = 4α 2 R L 2 (1- 1 k ) (1 + 1 k ) 2 (I d3 - I d4 ) (I 0 - 2I d2 ) Furthermore, if the equation (48) is substituted into the equation (71), the following equation (72) can be obtained: ΔI 0 = 4α 2 R L 2 (1- 1 k ) (1 + 1 k ) 2 (I d3 - I d4 ) (I d1 - I d2 ) In addition, if the equations (52) and (53) are substituted into the equation (72), the following equation (73) can be obtained: ΔI 0 = 4α 2 R L 2 (1- 1 k ) (1 + 1 k ) 2 (α 1 V 1 2I 0 α 1 - V 1 2 ) (α 1 V 2 2I 0 α 1 - V 2 2 ) It will be seen from this equation (73) that the differential output current ΔIo includes a product of the input first voltage V 1 and the second input voltage V 2 by the transfer curves of the two differential MOS transistor pair, and is in proportion to the product of the input first voltage V 1 and the second input voltage V 2 if the input first voltage V 1 and the second input voltage V 2 are small. Namely, the shown circuit has a multiplication characteristics. This could be understood from the fact that the equation (69) can be simplified to the following equation (74) by substituting ΔV IN1 = V X + V Y and ΔV IN2 = V X - V Y to the equation. ΔI 0 = 16α 2 (1- 1 k ) (1 + 1 k ) 2 V X V Y It would be understood from the equation (74) that the circuit shown in Figure 5 has the multiplier characteristics Furthermore, the equation (73) can be modified as follows: ΔI 0 = 4α 2 R L 2 (1- 1 k ) (1 + 1 k ) 2 α 1 2 V 1 V 2 4I 0 2 α 1 2 - 2I 0 α 1 (V 1 2 + V 2 2 ) + V 1 2 V 2 2 Here, the items of V 1 2 and V 2 2 are neglected, the following equation (76) can be obtained ΔI 0 ≒ 8α 1 α 2 I 0 R 2 L (1- 1 k ) (1 + 1 k ) 2 V 1 V 2 It is also understood from the equation (76) that the shown circuit has the multiptier characteristics. The inventor conducted simulation of the multiplier shown in Figure 5 under the condition of R L = 10KΩ, I 0 = 100µA, I 01 = 100µA, W 1 = 20µm, L 1 = 5µm, W 5 = 10µm, L 5 = 5µm, k = 5, Tox = 320Å. The result of the simulation is shown in Figure 6. It would be understood from Figure 6 that the multiplier in accordance with the present invention can considerably improve the linearity of the circuit in comparison with the conventional ones. In addition, since the shown embodiment has no unbalance in circuit structure fo the pair of input voltages V 1 and V 2 , even if the input voltages V 1 and V 2 are exchanged, the same characteristics can be obtained. As seen from the above, the multiplier in accordance with the present invention includes two squaring circuits each of which is composed of a pair of unbalanced differential circuits, so that the first and second input signals are supplied to the pair of unbalanced differential circuits as a differential input signal. Therefore, no unbalance in the circuit structure exists for the two input signals, so that the multiplier characteristics for the first input signal is the same as the multiplier characteristics for the second input signal. As a result, a multiplier having an excellent linearity and a wide dynamic range can be executed.

Claims: A multiplier comprising: a first squaring circuit (1;6) including first and second transistors (M 5 ,M 7 ) having a first gate width-to-gate length ratio and having their drains connected to each other, and third and fourth transistors (M 6 , M 8 ) having their drains connected to each other and having a second gate width-to-gate length ratio different from said first gate width-to-gate length ratio, gates of said first and fourth transistors (M 5 ,M 8 ) being connected to each other and connected in common to receive a first input signal (V 1 ), and gates of said second and third transistors (M 7 ,M 6 ) being connected to each other and connected in common to receive an inverted signal of a second input signal (V 2 ), sources of said first and third transistors (M 5 ,M 6 ) being connected to each other and sources of said second and fourth transistors (M 7 ,M 8 ) being connected to each other, so that two sets of unbalanced differential circuits are formed, and a squared value of a difference between said first input signal (V 1 ) and said inverted signal of said second input signal (V 2 ) is outputted; a second squaring circuit (2;7) including fifth and sixth transistors (M 9 ,M 11 ) having a third gate width-to-gate length ratio and having their drains connected to each other, and seventh and eighth transistors (M 10 ,M 12 ) having their drains connected to each other and having a fourth gate width-to-gate length ratio different from said third gate width-to-gate length ratio, gates of said fifth and eighth transistors (M 9 ,M 12 ) being connected to each other and connected in common to receive said first input signal (V 1 ), and gates of said sixth and seventh transistors (M 11 ,M 10 ) being connected to each other and connected in common to receive said second input signal (V 2 ), sources of said fifth and seventh transistors (M 9 ,M 10 ) being connected to each other and sources of said sixth and eighth (M 11 ,M 12 ) transistors being connected to each other, so that two sets of unbalanced differential circuits are formed, and a squared value of a difference between said first input signal (V 1 ) and said second input signal (V 2 ) is outputted; and a subtracting circuit (3) receiving said outputs of said first and second squaring circuit (1,2;6,7) for subtracting said output of said second squaring circuit (2;7) from said output of said first squaring circuit (1;6). A multiplier as claimed in Claim 1 further including a first differential amplifier (4) connected to receive said first input signal (V 1 ) and for outputting said first input signal (V 1 ) to the gates of the first, fourth, fifth and eighth transistors (M 5 ,M 8 ,M 9 ,M 12 ), and a second differential amplifier (5) connected to receive said second input signal (V 2 ) and for outputting said second input signal (V 2 ) to the gates of said sixth and seventh transistors (M 11 ,M 10 ), and said inverted input signal to the gates of said second and third transistors (M 7 , M 6 ). A multiplier according to Claim 1 or Claim 2, characterized by the drains of said first, second, fifth and sixth transistors (M 5 ,M 7 ,M 9 ,M 11 ) being connected to each other and also connected in common to receive a first drain current (I 1 ), and the drains of said third, fourth, seventh and eighth transistors (M 6 ,M 8 ,M 10 ,M 12 ) being connected to each other and also connected in common to receive a second drain current (I 2 ) so that a difference between said first and second drain currents (I 1 ,I 2 ) indicates a multiplication of said first and second input signals (V 1 ,V 2 ).

Inventors: KIMURA KATSUJI, KIMURA, KATSUJI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: G06G7
IPC codes: G06G7