Information signal processing method and apparatus

Abstract: In an information signal processing arrangement, an information signal, to which an error detecting code has been added and a part of which other than the error detecting code has been set to a code indicating a predetermined value, is received. Error detection capability is increased by detecting an error in the information signal according to the error detecting code added to the received information signal, and detecting whether or not the part of the information signal set to the predetermined value has changed.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to an information signal processing method and apparatus, and more particularly, to an information signal processing method and apparatus which detects an error in an information signal. 2. Description of the Prior Art An error detection method using CRCC (cyclic redundancy check code) has been known as a method to detect an error in information data which is generated on a transmission channel in transmission or recording/reproduction of an information signal, particularly digital information data. The principle of the error detection for information data using the CRCC comprises dividing the information data by a predetermined formula to generate a polynominal and using the remainder of the division as check data. That is, when the transmitted information data to which the CRCC has been added are divided at the reception side, the data are divisible with a remainder "0" if no error is gererated in the information data on the transmission channel, and the data are not divisible with a remainder of "0" if an error is generated in the information data on the transmission channel. Hence, by using the remainder, it is possible to detect an error in the information data which has been generated on the transmission channel. As for the data error detection capability of the CRCC, when check data of m (m is a positive integer) bits have been added, the generation of a burst error of m bits or less can be detected with a probability of 100 %, and the generation of a burst error of (m + 1) bits or more cannot be detected with a probability of about 1/2 m. That is, if it is assumed that a data error of any pattern is generated with the same probability, the probability that the detection of a data error becomes impossible can be considered to be about 1/2 m in total. As described above, in data error detection using only the CRCC, the detection of a data error is not always possible with a predetermined probability. Particularly, when check data comprise m bits as described above, it is impossible to detect whether or not an error is generated in data for about 1/2 m of the data if a burst error having a bit length longer than m bits has been generated, causing a misoperation in an apparatus at the reception side when the information data are identification information (ID) data or the like. There is disclosed in EP-A-0 176 218 an error correcting system in which unused bits in the transmitted word are set to a predetermined parity value and then checked at the receiving end in addition to the checking of the error detection code, the parity bit varying its value according to the content of the information being transmitted. SUMMARY OF THE INVENTION The present invention relates to an information data processing apparatus and method as set out in claims 1 and 8. How the invention may be carried out will now be described by way of example only and with reference to the accompanying drawings in which: FIG. 1 is a drawing showing the schematic configuration of an information signal processing apparatus according to an embodiment of the present invention; FIG. 2 is a diagram showing the schematic configuration of an information signal processing apparatus according to another embodiment of the present invention; and FIG. 3 is a diagram showing an example of the configuration of information data. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will now be explained in detail. In the transmission of a digital information signal, information data corresponding to information and check data used as a CRCC are usually processed in units of 4 bits or 8 bits, and an information data length and a check data length are also set to the number of bits equal to a multiple of 4 or 8. However, the number of bits of data actually used as information data or check data is in most cases shorter than the set number of bits. In such cases, data which are not used as information data or check data are set to fixed data having a predetermined data pattern. Even within data which are actually used as information data or check data, data which can be considered pseudo-fixed data because an invariable data pattern is maintained for a long period, may be present in some cases. For example, significant-bit data in address data constituting data representing address information have a longer period for the change of its data pattern than lower-bit data, and therefore can be considered as pseudo-fixed data with respect to the lower-bit data. Hence, in an information signal processing apparatus shown in the present embodiments, by paying attention to the above-described unused data and pseudo-fixed data, and utilizing these data for error detection in data, the data error detection capability of the apparatus can be increased. FIG. 1 is a diagram showing the schematic configuration of an information signal processing apparatus according to an embodiment of the present invention. In FIG. 1, information data to which check data used as a CRCC have been added are supplied to input terminal 101 via a transmission channel (not shown). The information data input to the input terminal 101 is supplied to a CRCC calculation circuit 102, which detects whether or not an error is present in the information data by a well-known method using the check data added to the information data, and outputs the result of detection to a determination circuit 107. In a conventional apparatus, error detection in data has been performed utilizing only the result of detection by the CRCC calculation circuit 102. In the FIG.1 apparatus according to the embodiment of the present invention, however, by performing error detection in data by the following method in addition to the result of detection by the CRCC calculation circuit 102, the data error detection capability of the apparatus is increased. That is, the information data input to the input terminal 101 is also supplied to a data separation circuit 103, which separates data coinciding with the above-described unused data or pseudo-fixed data from the input information data and supplies the separated data to a comparison circuit 106. On the other hand, data corresponding to the unused data or pseudo-fixed data are supplied from a comparison value setting circuit 105 to the comparison circuit 106, which compares whether or not the unused data or pseudo-fixed data separated by the data separation circuit 103 coincide with the data supplied from the comparison value setting circuit 105, and supplies the result of comparison to the above-described determination circuit 107. The configuration comprises the comparison circuit 106 and the comparison value setting circuit 105 will now be termed a data determination circuit 104. When plural kinds of unused data or pseudo-fixed data have been set in the information data supplied to the input terminal 101, it is necessary to provide data determination circuits 104 the number of which equals the number of the kinds. If the result of detection that no error is present in the data has been obtained from the CRCC calculation circuit 102, and the result of detection that the unused data or pseudo-fixed data separated by the data separation circuit 103 coincide with the data supplied from the comparison value setting circuit 105 has been obtained from the data determination circuit 104, the determination circuit 107 determines that no error is generated in the formation data supplied to the input terminal 101, and outputs a signal indicating the result of determination from output terminal 108. As described above, while the probability of not detecting data errors for the generation of a burst error longer than the bit length (m bits) of check data is about 1/2 m in the error detection method which uses only the CRCC, it is possible to increase the detection rate of a data error according to the method using the configuration as shown in FIG. 1. An explanation will now be provided of another embodiment of the present invention with reference to FIGS. 2 and 3. FIG. 2 is a diagram showing the schematic configuration of an information signal processing apparatus according to the other embodiment of the present invention. The information signal processing apparatus shown in FIG. 2 detects the generation of a data error in information data as shown in FIG. 3. FIG. 3 is a diagram showing an example of the configuration of information data used in the present embodiment. The information data shown in FIG. 3 comprise ID data (ID 0 and ID 1 ) in a unit of two symbols (one symbol comprises 8 bits) and CRCC check data in a unit of one symbol. The most significant bit (at the MSB side) in the ID 1 of the ID data is unused data which is fixed data indicating "0". In FIG. 2, the information data as shown in FIG. 3 are serially supplied from the MSB side shown in FIG. 3 to input terminal 201 via a transmission channel (not shown). The information data input to the input terminal 201 are supplied to the CRCC calculation circuit 202, which detects whether or not an error is present in the information data according to a well-known method using the CRCC check data added to the information data. The CRCC calculation circuit 202 outputs a "1" signal (a high level) if an error has beer detected in the information data, and outputs a "0" signal (a low level) if no error has been detected in the information data. The information data input to the input terminal 201 are supplied also to a serial/parallel conversion circuit 203, which converts the serially supplied information data into 8-bit parallel data and outputs the converted data. The ID 0 data, the ID 1 data, and the CRCC check data are sequentially output as 8-bit parallel data from the serial/parallel conversion circuit 203. The most-significant-bit data in the 8-bit parallel data output from the serial/parallel conversion circuit 203 as described above is supplied to a comparison circuit 206. In FIG. 2, a control signal for setting a comparison value has been input from a system controller (not shown) to input terminal 205. A comparison value setting circuit 204 outputs comparison value data "a" indicating "0" if fixed data "0" has been set to the most significant bit in the ID 1 data as shown in FIG. 3, and outputs comparison value data "a" indicating "1" to an exclusive OR gate 207 within the comparison circuit 206 if fixed data "1" has been set to the most significant bit in the ID 1 data. In accordance with the control signal input to the input terminal 205, the comparison value setting circuit 204 outputs an effective-data indicating signal "b" indicating "1" only while the ID 1 data are output from the serial/parallel conversion circuit 203, and outputs an effective-data indicating signal "b" indicating "0" while the ID 0 data or the CRCC check data are output from the parallel/serial conversion circuit 203, to an AND gate 208 within the comparison circuit 206. Accordingly, the exclusive OR gate 207 within the comparison circuit 206 outputs a signal indicating "0" when the most-significant-bit data output from the serial/parallel conversion circuit 203 coincides with the comparison data "a" output from the comparison value setting circuit 204 (that is, when no error is generated in the data), and outputs a signal indicating "1" when the two data do not coincide (that is, when an error is generated in the data), and supplies the signal to the AND gate 208 in the following stage. An effective-data indicating signal "b" has been supplied from the comparison value setting circuit 204 to the AND gate 208 within the comparison circuit 206. The AND gate 208 outputs a signal indicating the result of comparison between the most-significant-bit data in the ID 1 data output from the exclusive OR gate 207 and the comparison value data to a latch circuit 209 in the following stage only while the effective-data indicating signal "b" output from the comparisor value setting circuit 204 indicates "1", that is, while the ID 1 data are output from serial/parallel conversion circuit 203. As described above, the comparison circuit 206 outputs a signal indicating "1" only when an error is generated in the most-significant-bit data in the ID 1 data, and outputs a signal indicating "0" for all other cases. The signal output from the comparison circuit 206 is latched by the latch circuit 209 in order to adjust its timing with a signal output from the CRCC calculation circuit 202, and is supplied to an OR gate 210 together with the signal output from the CRCC calculation circuit 202. The OR gate 210 outputs a signal indicating "0" only when the both signals output from the CRCC calculation circuit 202 and the comparison circuit 206 are signals indicating "0", that is, only when both the data error detection method by the CRCC and the data error detection method using unused data detect that no error is generated in the data, and outputs a signal indicating "1", which indicates that an error is generated in the data, for other cases. As described above, in the embodiment shown in FIGS. 2 and 3, since the CRCC check data comprise 8 bits, a generated error cannot be detected with the probability of 1/2 8 = 1/256 in the CRCC error detection method if a burst error longer than 8 bits is generated. However, by also using the error detection method using unused data, the probability of not detecting data error is less than half of that for the conventional method, and it is therefore possible to greatly increase the error detection capability. An increase in the amount of hardware in this case is very small, as shown in FIG. 2. In the foregoing embodiment shown in FIGS. 2 and 3, an explanation has been provided only for the case wherein the most significant bit in the ID 1 data is unused data. If a plurality of unused data are present, a comparison circuit 206 arid a comparison value setting circuit 204 may be provided for each bit data of 8-bit parallel data output from the serial/parallel conversion circuit 203 shown in FIG. 2, and each comparison value setting circuit 204 may output a comparison-value data "a" and an effective-data indicating signal "b" in accordance with a control signal input to input terminal 205. Data error detection may be performed by making only the result of comparison by the comparison circuit 206 effective for information data wherein unused data are present. In the embodiment shown in FIGS. 2 and 3, if the ID data are, for example, ID data corresponding to image information, information relative to a field number, a line number and the like may be considered as the ID data. In this case, ID data indicating a field number have a longer period for the change of the contents of data than ID data indicating a line number, and therefore can be considered as the above-described pseudo-fixed data. Hence, by controlling the comparison value setting circuit 204 by a control signal supplied from the input terminal 205 so that the comparison value setting circuit 204 outputs comparison-value data corresponding to the pseudo-fixed data, it is possible to increase the data error detection capability even if no unused data are present unlike the information data shown in FIG. 3. As explained above, according to the present invention, it is possible to provide an information signal processing method having a higher data error detection capability than a conventional method.

Claims: An information data processing apparatus, comprising: information data receiving means (101, 201) for receiving data to which has been added error detecting data (CRCC) by means of which transmission errors can be detected, said information data also including specific data of a predetermined value; first error detection means (102, 202) which uses the added error detection data to detect transmission errors in the received data; second error detecting means (103-106, 203-206) also for detecting transmission errors, and characterised in that the second error detecting means comprise comparison means (106, 206) for comparing the specific data with check data which corresponds to an expected value in the specific data; and means (105, 204) for supplying the check data to the comparison means independently of the data received by the receiving means. Apparatus according to claim 1, wherein the check data supplied to the comparison means corresponds to data in the information signal which is either invariant with time or is pseudo-fixed data. Apparatus according to either claim 1 or claim 2, and including separating means (103, 203) for separating the specific data from the received information data and supplying the separated specific data as one input to the comparison means. Apparatus according to any one of claims 1 to 3 for processing an information data signal and added error detection data having the format of two data bytes (ID0, ID1) and error detection data (CRCC), and wherein the specific data supplied to the comparison means corresponds to at least the most significant bit of one of the data bytes. Apparatus according to claim 4 when dependent on claim 3, wherein the separating means comprise a serial-to-parallel conversion circuit (203) and the comparison means (206) is adapted to compare at least one check bit with a selected output of the conversion circuit. Apparatus according to any one of the preceding claims, wherein the first and second detecting means are connected to determination means (107) operative to indicate in response to the signal applied thereto that no error has been detected. Apparatus according to any one of the preceding claims, wherein the comparison means are supplied in operation with more than one set of data, the sets of data corresponding to a plurality of sets of specific data in the information data. A method of processing information data comprising: receiving (101, 201) data to which has been added error detecting data (CRCC) by means of which transmission errors can be detected, said information data also including specific data of a predetermined value; using first error detection means (102, 202) which use the added error detection data to detect transmission errors in the received data; and using second error detecting means (103-106, 203-206) to detect transmission errors, and characterised in that the second error detecting means (106, 204) uses comparison means to compare the specific data with check data which corresponds to the expected value of the specific data; and supplying (105, 204) the check data to the comparison means independently of the data received by the receiving means. A method according to claim 8, wherein the check data supplied to the second detecting means corresponds to data in the information signal which is either invariant with time or is pseudo-fixed data. A method according to either claim 8 or claim 9, and including separating (103, 203) the specific data from the received information data and supplying the separated specific data as one input to the comparison means. A method according to any one of claims 8 to 10, wherein the signal processed is a signal having information data and added error detection data in the format of two data bytes (ID0, ID1) and error detection data (CRCC), and the specific data supplied to the comparison means corresponding to at least the most significant bit of one of the data bytes. A method according to claim 11 when dependent on claim 10, wherein the specific data is separated from the signal by separating means comprising a serial-to-parallel conversion circuit (203), and the comparison means (206) compares at least one check bit with a selected output of the conversion circuit. A method according to any one of claims 8 to 12, comprising supplying the outputs of the first and second detecting means to determination means (107) which indicate in response to the signals applied thereto that no error has been detected. A method according to any one of claims 8 to 13, comprising supplying to the comparison means more than one set of data, the sets of data corresponding to a plurality of sets of specific data in the information data.

Inventors: SHIKAKURA AKIHIRO, YAMASHITA SHINICHI, SHIKAKURA,AKIHIRO, YAMASHITA, SHINICHI, SHIKAKURA,AKIHIRO, C/O CANON KABUSHIKI KAISHA, YAMASHITA, SHINICHI, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1991
Main classification: H03M13
IPC codes: H03M13