Memory circuit

Abstract: A FIFO type buffer circuit (3) is positioned to hold write-data between a random access memory (1) and a system data bus (100). A shift circuit (7,8) is positioned between an address calculation circuit (6) and a pointer circuit (2). The system data bus is connected to an output of the FIFO buffer circuit or to a read-data circuit of the random access memory, dependent on the operation mode, namely writing or reading mode, and the pointer circuit is connected to the address calculation circuit or to the shift circuit dependent on the operation mode. Accordingly, pipe line control is realized, even if the data transfer and the memory processing are reversed in order between the writing and reading modes.

Description: This invention relates to a memory circuit, and more particularly to a memory circuit adapted for high speed memory access in which pipeline processing is realized. Logic devices are these days required to operate with high speed. For this purpose, pipeline processing has been widely adopted in logic circuits etc. In a known memory circuit in which a RAM (random access memory) is directly connected to a data bus for a logic device controlled by the pipeline control system, transfer of data to be written on the data bus and writing of the transferred data into memory are carried out in one operation stage. In the same manner, reading of data from memory and transfer of the read data onto the data bus are also carried out in one operation. That is, the transfer of the data is carried out without dividing the functions of writing of the data into the memory and reading of the data from the memory, respectively, into different stages of the pipeline control. This is because the write processing and the read processing are opposite to each other in order, so that the continuity of the pipeline processing is not maintained if the transfer of the data is separated from the data writing into memory and the data reading from memory. In this known memory circuit, there is a disadvantage in that the average access time is not shorted to be less that the sum of the data transfer time and the memory processing (writing or reading) time at each stage of the pipeline control, because the data transfer and the memory processing are carried out in one operation stage. This disadvantage will be explained in more detail in the description below to be made by referring to the drawings. European Patent Application EP-A-0 355 560 describes a memory architecture which is designed to provide a means for the safe, premature, aborting of a write cycle without an additional read cycle. To this end, the memory is provided with multiplexers and registers configured to store the address and data signals developed during a write cycle, and to store in a RAM array the stored data at the stored address during the next write cycle. A comparator compares each stored address with each current address. Also a multiplexer is included which, during a read cycle, provides from the RAM array the currently-addressed data when the current address is different from the stored address, and provides the register stored data when the current address matches the stored address. The invention is defined in claim 1 below, to which reference should now be made. Advantageous features are set forth in the appendant claims. The invention will be explained in more detail by way of example in conjunction with the appended drawings, wherein: Fig. 1 is a block diagram showing a known memory circuit; Fig. 2 is a timing chart illustrating the operation of the known memory circuit; Fig. 3 is another timing chart illustrating the operation of the known memory circuit; Fig. 4 is a block diagram showing a memory circuit of a first preferred embodiment according to the invention; Fig. 5 is a timing chart illustrating the operation of the memory circuit of the first preferred embodiment according to the invention; Fig. 6 is another timing chart illustrating the operation of the memory circuit of the first preferred embodiment according to the invention; and Fig. 7 is a block diagram showing a memory circuit of a second preferred embodiment according to the invention. Before describing a memory circuit of the first preferred embodiment of the invention, a known memory circuit will be explained. Fig. 1 shows the known memory circuit which uses pipeline control, in which the data transfer and the memory processing (the writing of data into a memory and the reading of data from the memory) are carried out in the same operation stage. The known memory circuit comprises a RAM 41 connected with a R/W (read/write) control signal line 42, an address pointer 43 for designating an address of the RAM 41, and a data bus 44 connected to the RAM 41. In the known memory circuit, data transferred on the data bus 44 are written into addresses of the RAM 41 designated by the address pointer 43, in accordance with a write control signal supplied from the R/W control signal line 42 at pipeline control stages "n", "n+1" and "n+3", as shown in Fig. 2 On the other hand, data stored in the RAM 41 are read from addresses of the RAM 41 designated by the address pointer 43, to be transferred onto the data bus 44 in accordance with a read control signal supplied from the R/W control signal line 42 at the pipeline control stages "n+2" and n+4", as also shown in Fig. 2. As is apparent from Fig. 2, the data transfer and the memory processing (writing into the RAM 41 or reading from the RAM 41) are carried out in the same operation stage. On the other hand, Fig. 3 shows the operation of the known memory circuit, in which the data transfer and the memory processing are carried out at different stages of the pipeline control. As shown therein, the reading of data D4 from the RAM 41 is carried out between the writing of data D1, D2 and D3 and the writing of data D5 and D6, so that the writing of the data D3 and the reading of the data D4 are carried out without data transfer at the pipeline stages "n+3" and n+4", and the transfer of the data D4 and D5 is carried out without memory processing at the pipeline stages "n+5" and "n+6". As understood from this operation, in which the data transfer and the memory processing are carried out at different stages, the average access time of the RAM 41 is considerably shortened, if one of the writing and reading processing is consecutively carried out. For instance, if the data transfer and the memory processing (writing or reading) take the same time T, the average access time S is calculated by the equation: S = [(N + 1) / N] × T where N is the number of times for which the writing or reading of data is carried out consecutively. If the number N is indefinitely large, the average time S becomes nearly equal to the time T. On the contrary, when the writing and reading processing are carried out alternately, stages for carrying out only one of the writing and reading processings occur very often, so that the average access time S is not appreciably shortened, in spite of the adoption of the pipeline control. For this reason, the data transfer and the memory processing are carried out in the known memory circuit at one stage, in spite of the fact that the average access time could be shortened to a great extent by separating the data transfer and the memory processing into adjacent stages. As described before, the time necessary for each stage is the sum of that for the data transfer and the memory processing in the known memory circuit. Therefore, the average access time is not shortened to be less than the value of the above described sum. For instance, when the data transfer on the data bus 44 takes 30 ns, and the memory processing (writing into the RAM 41 or reading from the RAM 41) takes 30 ns, each stage is not shortened to be less than 60 ns in the pipeline control operation. Therefore, even if a high speed operation is realized in logic devices other than the RAM 41 by the pipeline control, the known memory circuit hinders the high speed operation of a pipeline control system. In fact, the high speed operation of the pipeline control system is not hindered by logic devices such as logic calculation circuits, etc., but is hindered by memory circuits and buses. Accordingly, a memory circuit which is accessed with high speed is required as realized in logic calculation circuits. A memory circuit of the first preferred embodiment of the invention will now be explained with reference to Fig 4. In this memory circuit, a 24-bit RAM 1 having memory cells of 1024 words is provided, the addresses of which are designated by a predecoder 14, in which an address signal from an address pointer 2 positioned on an address bus 109 is decoded to be supplied to the RAM 1, to which data is written and from which data is read, respectively, in 40 ns. A first-in and first-out type ("FIFO") buffer 3 is also of 24 bits and has a two-stage structure, and latches 24-bit data supplied from a data bus 100 at the front stage thereof in response to an output signal from an AND gate 4 (FIFO input clock). When the back stage of the FIFO buffer 3 becomes a vacant state (no effective data held), the 24-bit data latched at the front stage of the FIFO buffer 3 is shifted to the back stage thereof. Data is output from the FIFO buffer 3 in response to an output signal from an AND gate 5 (FIFO output clock), so that data latched at the back stage of the FIFO buffer 3 is transferred to the RAM 1, and the back stage of the FIFO buffer 3 enters a vacant state upon the occurrence of the rising edge of the output signal of the AND gate 5. Signal lines 102 and 103 are provided to supply clock signals CL1 and CL2 having cycles of 40 ns to the predecoder 14 and other circuits, wherein the memory processing is carried out in the RAM 1 in synchronization with the clock signal CL2, and a latch 13 latches data read from the RAM 1 during the period from the rising edge of the clock signal CL2 to the next following rising edge thereof. A read/write (R/W) control signal line 104 is provided to supply a R/W control signal 104 (same reference numeral used) to a multiplexer 11, so that a 10-bit address signal 105 supplied from an address calculation circuit 6 is determined for the data writing or the data reading. That is, a "low" R/W control signal 104 instructs a data reading operation, while a "high" R/W control signal 104 instructs a data writing operation. Write-address buffers 7 and 8 are provided to latch 10-bit address signals on address buses 107 and 105 by the rising edges of output signals supplied from AND gates 9 and 10. The write-address buffers 7 and 8 and the pointer 2 function as 10-bit shift registers at the time of the data writing (the R/W control signal being "high"). A multiplexer 11 is provided to transfer an address signal on the address bus 105 to the pointer 2 at the time of the data reading (the R/W control signal being "low"), and to transfer an address signal on the address bus 106 to the pointer 2 at the time of the data writing. A comparator 140 is provided to supply a coincidence signal 110 to a D-type flip-flop 150 as a result of the comparison between one of address signals 106 and 107 latched in the write-address buffers 7 and 8 and an address signal 109 of the pointer 2, and the comparison is carried out by a rising edge of the clock signal CL2. The coincidence signal 110 is of a bit arrangement (1,0) when the address signals 106 and 109 coincide with each other, and the coincidence signal 110 is (1,1) when the address signals 107 and 109 coincide with each other, while the coincidence signal 110 is (0,x) when neither of the address signals 106 and 107 coincides with the address signal 109, where the bit "x" may be either "1" or "0". The coincidence signal 110 is delayed in the D-type flip-flop 150 by one clock, and is transferred to a multiplexer 12, to which the input R/W control signal 104 is supplied through D-type flip-flops 151 to 153 to be delayed as a delayed signal 115 by 1.5 clocks. When the delayed signal 115 is "0" to instruct the data reading, and the coincidence signal 111 is of the bit arrangement (0,x) to indicate that both the address signals 106 and 107 do not coincide with the address signal 109, the multiplexer 12 selects a data bus 114 connected to the latch 13. On the other hand, when the delayed signal 115 is "0", and the coincidence signal 111 is (1,0), the multiplexer 12 selects a data bus 113, and when the delayed signal 115 is "0", and the coincidence signal 111 is (1,1), the multiplexer 12 selects a data bus 112. On the other hand, when the delayed signal 115 is "high" to instruct a data writing operation, the multiplexer is at a high impedance state. The D-type flip-flop 151 is supplied with the R/W control signal 104 to generate a mode designating signal which is "0" to shift the RAM 1 to the reading mode, and "1" to shift the RAM 1 to the writing mode. The address calculation circuit 6 calculates an address in accordance with address data on an address bus 101, so that an address signal thus calculated is supplied on the address bus 105 to indicate a write-address or a read-address. The operation of the memory circuit will now be explained with reference to Figs. 5 and 6. At the times A, B and C, addresses a, b and c are calculated in the address calculation circuit 6 by receiving data on the address bus 101, and the addresses a, b and c are supplied on the address bus 105 as read-addresses, because the R/W control signal 104 is low. Consequently, the multiplexer 11 selects the address bus 105 in response to the R/W control signal 104 being "0", so that the read-addresses a, b and c are supplied through the multiplexer 11 to the address pointer 2. The read-addresses a, b and c are supplied from the pointer 2 through the address bus 109 to the predecoder 14, so that address signals thus decoded are delayed to be supplied to the RAM 1 by 0.5 clock. The R/W control signal 104 is latched in the D-type flip-flop 151 in synchronization with the clock signal CL2, so that the mode designating signal 120 goes low. As a result, the RAM 1 is assumed to be in the reading mode, so that data a, b and c are read from the addresses a, b and c at the times A', B' and C'. This, the read data a, b and c are latched in the latch 13 by rising edges of the clock signal CL2, and transferred to the multiplexer 12. The delayed signal 115 goes low in accordance with the "low" R/W control signal 104, so that the multiplexer 12 selects the data bus 114 to transfer the data a, b and c from the latch 13 to the data bus 100. As described above, it takes 1.5 clocks at the data reading mode to generate the addresses a, b and c of the RAM 1 in the address calculation circuit 6, and read the data a, b and c from the generated addresses a, b and c of the RAM 1. Next, it is assumed that the writing mode is designated at the time D, when the R/W control signal 104 goes high. In this first preferred embodiment, it is also assumed that address data of "3FF H " is stored in the write-address buffers 7 and 8 at the initial state prior to operation, and that the address "3FF H " of the RAM 1 is an exclusively occupied area which is not used for effective data. At the times D, E and F, addresses d, e and f are generated in the address calculation circuit 6 to be supplied on the address bus 105, and the multiplexer 11 selects the address bus 106 in response to the "high" R/W control signal. Thus, the pointer 2 and the write-address buffers 7 and 8 function as shift registers. That is, the pointer 2 latches data of the write-address buffer 7 at the time D, the write-address buffer 7 latches data of the write-address buffer 8 at a time which is behind the time D by a short time, and the write-address buffer 8 latches the address d. In the similar manner, data shift is repeated in the pointer 2 and the write-address buffers 7 and 8 at the times of E and F. Subsequently, the address d is held at the time F. The R/W control signal 104 makes the mode designating signal 120 high, so that the RAM 1 is controlled to be in the data writing mode. Consequently, the data d on the data bus 100 is written into the address d of the RAM 1 during the time of F' to G'. In more detail, the data d is transferred onto the databus 100 after 1.5 clocks from the time when the address calculation circuit 6 generates the address d, and is latched at the front stage of the FIFO buffer 3 at the time F'. In this state, the back stage of the FIFO buffer 3 is vacant, so that the data d is instantly transferred to the back stage thereof to be supplied on the data bus 113. At this moment, the RAM 1 is in the data writing mode, so that the data d is written into the address d of the RAM 1 before the time G'. At the time G', the data d held at the back stage of the FIFO buffer 3 is invalidated to make it a vacant stage. Therefore, the next data e is supplied from the data bus 100 to be latched at the front stage of the FIFO buffer 3 at this time, and is instantly latched at the back stage thereof. Consequently, the data e is supplied on the data bus 113 at a time which is behind the time G' by a short time. On the contrary, the R/W control signal goes low again at the time G, so that the RAM 1 is again in the data reading mode. As a result, the data e is supplied to the data bus 100 at a time behind the time G' by a short time. On the other hand, the addresses e and f which are generated in the address calculation circuit 6 at the times E and F are held in the write-address buffers 7 and 8, and the pointer 2 holds the next read-address g at this time. The write-data f is supplied on the data bus 100 during the time G' to H', and is latched at the front stage of the FIFO buffer 3 at the time H'. The data e has been already been latched at the back stage of the FIFO buffer 3, so that the data f is kept latched at the front stage thereof. The RAM 1 is now in the data reading mode, so that the data g and h read from the addresses g and h which are supplied from the address calculation circuit 6 to the pointer 2 are supplied on the data bus 100 with the delayed time of 1.5 clocks. Accordingly, during this period, write-addresses are held in the write-address buffers 7 and 8, and write-data are held at the front and back stages of the FIFO buffer 3. When the R/W control signal 104 goes high again at the time I, the addresses held in the write-address buffers 7 and 8 are supplied to the pointer 2, so that the write-data held in the FIFO buffer 3 are supplied to be written in the RAM 1. In the memory circuit of this first preferred embodiment, a consecutive timing relation is obtained between the address calculation and the data transfer, even if the data transfer and the memory processing are separated, as described above. As a result, the data writing mode and the data reading mode which are instructed alternately are carried out without time-loss, to realize high speed operation in a pipeline control system. In Figs. 5 and 6, the writing mode and the reading mode are alternately instructed to be carried out at times following the time H, wherein no change is necessary in timings of the address calculation and the data transfer. As described above, data to be stored is once held in the FIFO buffer 3, and thereafter written into the RAM 1 in the memory circuit of the first preferred embodiment of the invention. Ordinarily, data is written into the RAM 1 in accordance with a trigger signal which is an address signal for data to be written into the RAM 1 at a writing stage coming after the next writing stage. At this moment, there is a situation where data held in the FIFO buffer 3 has to be loaded onto the data bus 100 prior to the writing thereof into the RAM 1. This occurs when a calculated read-address coincides with write-addresses in the write-address buffers 7 and 8. In this case, data to be written is reloaded on the data bus 100 in accordance with the comparison result from the comparator 140 before writing the data into the RAM 1. For this data processing, the data of the FIFO buffer 3 is not invalidated to be written into the RAM 1. In this preferred embodiment, read-data or write-data for a calculated address is delayed to be transferred onto or from the data bus 100 by 1.5 clocks after the generation of the address. In addition, the timing does not depend on which mode is carried out between the writing and reading modes, or on the order of the two modes. Furthermore, access to data of the RAM 1 can be carried out by each 40 ns in this preferred embodiment. This can be achieved because the writing of data into the RAM 1 and the transfer of data to be written into the RAM 1 on the data bus 100 are separated and interposed. Such a separation of the transfer processing and the memory processing enhances the effectiveness of the pipeline control, and the average access time is halved as compared to the known memory circuit. The memory capacity of the RAM 1, the bit width of the buffers, the pointer, the buses, etc., and the frequency of the clock signals, etc., may be different from those of the preferred embodiment. Fig. 7 shows a memory circuit of a second preferred embodiment according to the invention, wherein like parts are indicated by like reference numerals, and a fixed value output circuit 31 and a multiplexer 32 are additionally provided. The fixed value output circuit 31 supplies a fixed value "3FF H " of 10 bits to the multiplexer 32, by which the output of the address calculation circuit 6 is selected when a memory selection signal (SEL) 300 is "0", and the output of the fixed value output circuit 31 is selected when the memory selection signal 300 is "1". As different from the first preferred embodiment, the R/W control signal 104 is supplied to an OR gate 33, to which the memory selection signal 300 is also supplied. In this second preferred embodiment, when the memory circuit is not selected in the presence of the memory selection signal 300 being "1", the memory circuit operates in the same manner as in the writing mode, so that data is written into a fixed value address of "3FF H " of the RAM 1, and no access is carried out to the RAM 1 other than the fixed value address. In the first preferred embodiment, a data source (not shown) supplies all data to be written on the data bus 100, and dummy writing processing must be carried out twice. This is because the data are written into the RAM 1 without being left n the FIFO buffer 3. In the second preferred embodiment, however, there is an additional advantage in that data in the FIFO buffer 3 is automatically written into the RAM 1 when the memory circuit is not selected. As described above, the memory circuit comprises the shift registers and the FIFO buffer to absorb the alteration of the order of the data transfer and the memory processing dependent on the difference between the writing and reading modes, so that the effectiveness of the pipeline control is enhanced. Accordingly, the processing time is considerably reduced at each pipeline stage to shorten the average access time to the RAM. For instance, if the time necessary for the data transfer and the time necessary for the memory processing are assumed to be equal, the processing time is halved at each stage of the pipeline control. In the present system, the difference between the writing and reading modes is automatically absorbed in hardware, so that there is an advantage in that an address is designated and data is supplied to a system data bus, respectively, at a constant timing without depending on the difference between the writing and reading modes. Therefore, the writing and reading modes can be arranged in an arbitrary order, and the memory processing can be carried out, as if only the reading mode is carried out, because the writing mode is carried out as in the reading mode by the pipeline processing. This means that the memory access speed is increased without doubling the memory administration load, as compared the known memory circuit, because the output of the address calculation circuit, the data transfer on the system data bus, and the change of the R/W control signal may be controlled at each stage of the pipeline control, as shown in Figs. 5 and 6. Although the invention has been described with respect to specific embodiments for complete and clear disclosure, the appended claims are not thus limited and comprise alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.

Claims: A memory circuit, comprising: a first-in first-out type buffer circuit (3) provided between a random access memory (1) and a system data bus (100), said first-in first-out type buffer circuit (3) holding data successively supplied from said system data bus (100) in a data writing mode; an address calculation circuit (6) for calculating an address in accordance with data on an address bus (101); an address pointer (2) for designating an address of said memory (1) by holding an address; a first selection circuit (12) for selecting one of a read data bus (114) connected to said memory (1) and a data bus (112, 113) connected to an output of said first-in first-out type buffer circuit (3) to be coupled to said system data bus (100) in response to first and second selection signals (115, 111); a shift circuit (7, 8) for holding an address, said shift circuit receiving an output from said address calculation circuit (6); a second selection circuit (11) for selecting one of an address bus (105) connected to the output of said address calculation circuit (6) and an address bus (106, 107) connected to an output of said shift circuit (7, 8) in response to a read/write control signal (R/W), an output of said second selection circuit (11) being coupled to an input of said address pointer (2); a generating circuit (151, 152, 153, 154, 4, 5, 9, 10) for generating: a mode designating signal (120) supplied to said memory (1), a first control signal supplied to said first-in first-out type buffer circuit (3), said first selection signal (115) supplied to said first selection circuit (12), and a second control signal supplied to said shift circuit (7, 8), respectively, in response to said read/write control signal (R/W); and a comparison circuit (140) for comparing an address on said address bus (106, 107) connected to said shift circuit (7,8), and said address of said address pointer (2), to generate said second selection signal (111) supplied to said first selection circuit (12). A memory circuit according to claim 1, wherein said generating circuit (151, 152, 153, 154, 4, 5, 9, 10) generates: said mode designating signal (120) and said first selection signal (115) by delaying said read/write control signal (104), said first control signal by logical combination of delayed signals obtained by delaying said read/write control signal (104), and said second control signal by selectively masking a clock signal. A memory circuit according to claim 1, wherein said first-in first-out type buffer circuit (3) is supplied with data on said system data bus (100) at a timing determined by said first control signal, and supplies said data at least to said first selection circuit (12). A memory circuit according to claim 2, wherein said comparison circuit (140) compares addresses supplied from said shift circuit (7, 8) and said address pointer (2) to provide said second selection signal (111) in dependence on the coincidence or non-coincidence between them. A memory circuit according to claim 4, wherein said first selection circuit (12) selects said data bus (100) to be connected to said memory (1) in accordance with said first and second selection signals (115, 111) when said first selection signal (115) is at a low level and said second selection signal (111) indicates non-coincidence; and said first selection circuit (12) selects said data bus (100) to be connected to said first-in first-out type buffer circuit (3) in accordance with said first and second selection signals (115, 111) when said first selection signal (115) is at said low level and said second selection signal (111) indicates coincidence.

Inventors: TOYOO KIUCHI, TOYOO, KIUCHI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: G06F5
IPC codes: G06F12, G06F5, G11C11, G06F9, G11C7