Method for manufacturing a double-gated MOS transistor

Abstract: A method for manufacturing a semiconductor apparatus, providing steps of (i) laminating a first polysilicon layer on the whole surface of a semiconductor substrate through a first oxide layer, (ii) removing the first polysilicon layer and first oxide layer in an element separation region so as to form a trench therein and to treat the residual first polysilicon layer and first oxide layer as a bottom gate electrode and an insualating film respectively, (iii) forming a monocrystalline silicon layer by epitaxial growth on the whole surface of the semiconductor substrate including the trenches, (iv) removing the monocrystalline silicon layer in the element separation region, laminating a second oxide layer on the whole surface of the semiconductor substrate including the removing portion, and making the second oxide layer remain as an element separation film (6) in only the element separation region, and (v) forming a gate oxide film and a top gate electrode (9, 15) on the bottom gate electrode through the residual monocrystalline silicon film, and forming a source/drain region on the residual monocrystalline silicon film.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a Double-Gated MOS Transistor. 2. Description of the Prior Art MOS Transistors are widely used as components in Integrated Circuits (IC) due to their low power dissipation and possibility for high density integration. However, several problems arise in the following respects: (i) short-channel effects, and (ii) isolation between opposite polarity MOSFETs. To solve the first problem, very shallow junctions and higher channel concentrations are required. These are very difficult to be realized because of breakdown limitations. The isolation between devices of opposite polarity is limited by latch-up in the conventional technology. As a result, the separation between devices is limiting the device scaling. Proceedings of IEEE SOS/SOI Technology Conference, 3rd-5th October 1989, Stateline, Nevada, US, pages 134-135, R.P. Zingg et al: "Dual-Gate SOI CMOS Technology by Local Overgrowth (LOG)" discloses the fabrication of dual-gate SOI CMOS devices having oxidized polysilicon gates on a thermally oxidized wafer. EP-A-O 364 393 discloses a power semiconductor device comprising a layered first insulating region formed on a first major surface of a semiconductor layer, a first conductive layer formed on the first insulating region and having the same conductivity type as that of the semiconductor layer, a layered second insulating region formed on the first conductive layer, a vertical power transistor having the semiconductor layer as one of its components and formed on the first major surface of the semiconductor layer, a third insulating region for dielectrically isolating the first conductive layer from the other conductive layer, and a control MIS transistor, formed on the second insulating region, for controlling the vertical power transistor. SUMMARY OF THE INVENTION The present invention provides the method defined by claim 1 for manufacturing a semiconductor device. The sub-claim 2 is directed to an embodiment of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a view showing manufacturing steps according to an embodiment of the present invention; and Figure 2 is a view for explaining the structure of main portions according to the embodiment of the present invention. DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT According to the present invention, a monocrystalline silicon layer is grown so as to completely bury trenches by an epitaxial technology. As finally shown, transistors are laterally separated from each other by a CVD oxide film which is filled in the trench. Consequently, the characteristics of a Double-Gated MOS Transistor can be improved. A SiO 2 insulating film and a bottom gate electrode are formed in a region other than a region (R). Consequently, the upper portion of a device is separated from a semiconductor substrate by a bottom gate electrode 3a in the lower portion of the device. Thus, a noise resistance can be enhanced. Double-Gated MOS Thin Film Transistors (DGTFT) and a new isolation and epitaxial growth process are proposed to realize a CMOS process which eliminates the limitations of the conventional technology. For the Double-Gated structure using lateral selective epitaxial growth, (i) transistors can be isolated from the substrate by the insulating effect of the bottom gate electrode, (ii) the isolation between the transistors can be performed by the trench, and (iii) the characteristics of the transistors can be enhanced by Double-Gated connection. A preferred embodiment of the present invention will be described in more detail with reference to the drawings. The present invention is not limited to the following embodiment. A manufacturing method will be described below. Fig. 1 shows steps of forming a Double-Gated CMOS device. As shown in Fig. 1 (a), a SiO 2 film (first oxide film) 2 having a thickness A of 100 nm (1000 Å) is formed on a silicon substrate 1 so as to isolate a bottom gate electrode from the silicon substrate 1. A polysilicon layer 3 having a thickness B of 100 nm (1000 Å) is laminated as the bottom gate electrode on the SiO 2 film 2. And, an about 20 nm (200 Å) thermal SiO 2 layer 100 is grown on the polysilicon layer 3. Then, the SiO 2 film 2 and polysilicon layer 3 in an element separation region (R) are patterned by a photoetching technology so that the silicon substrate 1 in the region (R) is exposed. A trench 4 having a depth T of 200 nm (2000 Å) and an opening diameter M of 500 nm (5000 Å) is formed in the region (R) on the silicon substrate 1. A SiO 2 insulating film 2a and a bottom gate electrode 3a are formed in regions other than the region (R) [see Fig. 1 (b)]. Subsequently, a SiO 2 oxide film 20 having a thickness C of 10 nm (100 Å) is formed by thermal oxidation on the whole surface of the silicon substrate 1 including the trenches 4. Then, the thermal oxide film formed on the bottom of the trench 4 is removed by anisotropic dry-etching. The thermal oxide film 20 formed on the side portions of the trench 4 is made to remain. A monocrystalline silicon layer 5 having a thickness D of 100 nm (1000 Å) is grown on the whole surface of the silicon substrate 1 including the thin SiO 2 films 20 and trenches 4 in order to completely bury the trenches 4 by the epitaxial technology [see Fig. 1 (c)]. The monocrystalline silicon layer 5 forms a CMOS device body. Then, using a photoresist mask, the monocrystalline silicon layer 5 is etched in the element separation region (R) between devices so as to form a monocrystalline silicon film 5a. A trench 24 having a depth E of 300 nm (3000 Å) is formed again. In this case, etching is carried out until a surface la of the silicon substrate 1 is exposed. Thereafter, a SiO 2 thermal oxide film 7 having a thickness F of 10 nm (100 Å) is formed by thermal oxidation on the whole surface of the silicon substrate 1 including the trenches 24. A SiO 2 CVD oxide film 6 having a thickness G of 300 nm (3000 Å) is formed as an element separation film in the region (R) by deposition, reflow and etchback technologies using a CVD oxide film [see Fig. 1 (d)]. Consequently, device separation is performed. In that case, the element separation film 6 buries the trench 24. As a result, the transistors are laterally separated from each other in the direction of an arrow A by the CVD oxide film 6 which is filled in the trench 24. The lower portions of the devices are separated from each other by the bottom gate polysilicon electrode 3a. As shown in Fig. 2, a contact window 8 is formed as a stack contact between the bottom gate polysilicon electrode 3a and a top gate polysilicon electrode to be formed hereafter. As shown in Fig. 1 (e), a polysilicon layer having a thickness H of 200 nm (2000 Å) is laminated as a top gate electrode on the whole surface of the silicon substrate 1 including the element separation film 6. Then, the polysilicon layer is patterned. Consequently, top gate polysilicon electrodes 9 and 14 remain on only the monocrystalline silicon film 5a which remains beneath the SiO 2 film 7. Then, ions are selectively doped on the whole surface of the silicon substrate 1 including the top gate electrodes 9 and 14 by the known ion implantation using photoresist masks (not shown). Consequently, there are respectively formed sources and drains 12 and 13 of a NMOS Transistor 10 and a PMOS Transistor 11 [see Fig. 1 (e)]. As shown in Fig. 1 (f), insulating layers 15 having a thickness I of 500 nm (5000 Å) are laminated on the whole surface of the silicon substrate 1 including the top gate electrodes 9 and 14. A contact hole 16 is formed on the insulating layer 15. A metal layer having a thickness J of 400 nm (4000 Å) is laminated on the whole surface of the silicon substrate 1 including the contact holes 16. Then, the metal layer is patterned to form a metal film 17. Consequently, device interconnection is formed. Thus, there can be produced a Double-Gated CMOS Inverter shown in Fig. 2. According to the present embodiment, the monocrystalline silicon layer 5 is grown so as to completely bury the trenches 4 by the epitaxial technology as shown in Fig. 1 (c). Finally, the transistors 10 and 11 are laterally separated from each other in the direction of the arrow A by the CVD oxide film 6 which is filled in the trench 24 as shown in Fig. 1 (f). Consequently, the characteristics of the Doubie-Gated MOS Transistor can be improved. The SiO 2 insulating film 2a and bottom gate electrode 3a are formed in the regions other than the region (R) [see Fig. 1 (b)]. Consequently, the upper active element of the device is separated from the silicon substrate 1 by the bottom gate electrode 3a in the lower portion of the device. Thus, the noise resistance can be enhanced. In conventional CMOS technologies, the transistors are formed within the silicon substrate and are isolated by PN junctions (wells) and thick oxide films (LOCOS films). These technologies are limited by latch-up, shallow junction formation and breakdown. According to a novel manufacturing method of the present invention, there can be realized a Double-Gated CMOS device. Consequently, the following effects can be obtained. (i) The Double-Gated CMOS Thin Film Transistors are superior to Single-Gated devices in the following respects; 1. a drive current can be enhanced, 2. a higher punchthrough voltage resistance can be obtained, and 3. short-channel degradation effects are reduced. (ii) The bottom gate electrodes of the transistors are provided beneath the active elements in order to insulate each active element, making this structure resistant to substrate noise. (iii) The transistor has the element separation film (for example, a CVD oxide film) in the minimum size trench. Consequently, the latch-up can be reduced and a packing density can be increased. The invention may be embodied in other specific manners without departing from its scope as defined by the claims.

Claims: A method for manufacturing a semiconductor device, comprising the steps of: (i) forming a first oxide layer (2) on the whole surface of a semiconductor substrate (1) and laminating a first polysilicon layer (3) on said first oxide layer (2), (ii) growing a thermal oxide layer (100) on said first polysilicon layer (3), and removing said thermal oxide layer (100), first polysilicon layer (3) and first oxide layer (2) in an element separation region (R) so as to form a trench (4) therein, the residual first polysilicon layer (3) and first oxide layer (2) forming a bottom gate electrode (3a) and an insulating film (2a) respectively, (iii) growing a thermal oxide layer (20) on the whole surface of the structure, removing said thermal oxide layer (20) from the bottom of said trench (4), and forming a monocrystalline silicon layer (5) by epitaxial growth, on the whole surface of the structure, (iv) removing the monocrystalline silicon layer (5) only in the element separation region (R), forming a gate oxide film (7) by thermal oxidation on the residual monocrystalline silicon film (5a), laminating a second oxide layer (6) by CVD on the whole surface of the structure, and patterning the second oxide layer (6) such that it remains as an element separation film in only the element separation region (R), and (v) forming a top gate electrode (9, 14) over the residual monocrystalline silicon film (5a), and forming a source/drain (12, 13) region in the residual monocrystalline silicon film (5a). A method for manufacturing a semiconductor device according to claim 1, wherein said first oxide layer (2) is a SiO 2 film.

Inventors: ADAN ALBERTO OSCAR, HORITA MASAYOSI, ADAN, ALBERTO OSCAR, HORITA, MASAYOSHI, HORITA, MASAYOSI
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1991
Main classification: H01L21
IPC codes: H01L21, H01L27, H01L29