A device with an oscillator and a circuit for phasing the oscillator

Abstract: A circuit device (1) for phasing an oscillator (2), which comprises a multivibrator (3) having a transistor pair (Q1,Q2) with the emitters (E1,E2) coupled through a capacitor (C), comprises a normally open electronic switch (SW) controlled by a drive signal (IN) to close and inhibit the oscillator (2). This switch connects a voltage divider to the base of a transistor (Q7) connected to one (E2) of the emitters to interrupt the loop positive feedback of the oscillator (2) upon the voltage across the capacitor reaching a predetermined value.

Description: This invention relates to a device with an oscillator and a circuit for phasing the oscillator, which oscillator comprises a multivibrator having a transistor pair with their emitters coupled through a capacitor. Voltage-controlled oscillators, or VCO's, are widely employed in a number of electronic apparatus, particularly for modulating and de-modulating RF signals. In most instances, such oscillators are implemented, as integrated circuits, with RC multivibrators wherein the capacitor charge current is varied in response to a control pulse. A typical example of a device of this kind is described, for example, in "Analysis and Design of Analog Integrated Circuits", pages 590-593, published by Wiley, 1977. A requisite with such devices is an ability to stop the oscillation at a selected time, to then re-start it in a known pre-determined state of phasing. No prior art approach has been known which can fill this demand. The underlying technical problem of this invention is to provide a circuit device which has such structural and functional features as to allow of the oscillator being temporarily blocked and then re-started in a predetermined phase condition. This technical problem is solved by a device as defined and generally characterized in the first of the claims appended to this specification. The features and advantages of a device according to the invention will become more clearly apparent from the following detailed description of an embodiment thereof, given by way of example and not of limitation with reference to the accompanying drawings. In the drawings: Figure 1 is a diagramatic representation in principle of the device according to this invention; Figure 2 is a further diagramatic representation of a preferred embodiment of the device shown in Figure 1; and Figures 3 and 4 are respective waveform diagrams of signals present in the inventive device. With reference to the drawing figures, generally and schematically shown at 1 is a circuit embodying this invention and being intended for phasing an oscillator 2. The oscillator 2 is of the VCO (Voltage-Controlled Oscillator) type and conventional construction, it comprising a multivibrator 3 which includes a pair of transistors Q1, Q2 whose emitters E1, E2 are coupled together through a capacitor C which establishes a positive feedback path between the two transistors. An example of such an oscillator 2 is described on page 591 of the book "Analysis and Design of Analog Integrated Circuits, published by Wiley, 1977. The oscillator transistors Q1, Q2 are driven by corresponding transistors Q3, Q4 which are connected as emitter followers between a positive supply pole Vcc and two current sources I identical with each other. The device 1 of this invention is implemented as a circuit portion associated with the oscillator and comprises a first leg 4 with a bipolar transistor Q7 of the npn type having its collector C7 connected to the positive pole Vcc and its emitter E7 connected to the emitter E2 of the oscillator transistor Q2. A second circuit leg 5 comprises a series of two bipolar transistors Q8, Q9 connected, in a diode configuration between the positive pole Vcc and a current source I1 to provide substantially a division of voltage Vcc. The collector C8 of transistor Q8 is connected to the emitter E9 of transistor Q9 having its collector C9 connected to the pole Vcc. The emitter E8 of transistor Q8 is connected to the source I1, as well as to the base B7 of transistor Q7, through a normally open electronic switch SW which has a control terminal adapted to receive a make drive signal IN for inhibiting operation of the oscillator upon the voltage at the emitter E2 of transistor Q2 reaching a predetermined value. The operation of the circuit device according to the invention will be now described with reference to a starting condition wherein the oscillator 2 is in a state of discharge of capacitor C as shown in Figure 3 by the broken line segment included between the times t1 and t2. Shown in Figure 3 is a graph of the voltage value Vc(t) across the capacitor C versus time. Denoted by t1, t2 and t3 are the times when the charge of the capacitor C undergoes switching. Where the signal IN on the switch SW input is activated at a time within the t1 to t2 range, the oscillator 2 would be in a condition wherein transistor Q1 is off, while Q2 is on. Consequently, transistor Q7 of the device 1 would be held off because of its base 87 being at a lower voltage value than the base of transistor Q2. In such a circumstance, the oscillator 2 would keep operating normally as specified. Where, on the other hand, the signal IN is received within the t2 to t3 range, transistor Q1 would be active and the other transistor, Q2, cut off, with the voltage on the emitter E2 decreasing with a derivative of I1/C. By making the emitter area of transistor Q7 larger than the emitter area of transistor Q2, transistor Q7 is turned on at time t3, that is before the voltage on the emitter E2 reaching, at time t*, a value which enables Q2 to be turned on. From time t3 onwards, therefore, Q2 is prevented from being turned on by breaking the positive feedback loop between the transistors Q1 and Q2. This situation is depicted diagramatically in Figure 4, showing the segmental waveform of the voltage Ve(t) on the emitter E2, with the same time base of the voltage Vc(t) on the capacitor C as shown in Figure 3. If the area occupied in the integrated circuit by transistor Q7 is denoted by A', and the area occupied by each of transistors Q1 and Q2 is denoted by A, then the difference between the turn-on voltage of transistor Q7 and that of transistor Q2 can be obtained from the following formula: ΔV = Vt + lnA'/A where Vt is the voltage value tied to thermal drift. It may be appreciated that, the moment the signal IN is cancelled, thereby removing the block on the oscillator 2, the voltage on the emitter E2 is bound to further drop by ΔV before transistor Q2 can be turned on again, which inevitably involves a time delay for phasing the oscillator. In order to minimize this time delay equal to t* - t3 = Δt = ΔV* C/I it becomes convenient to compute the percent value of the delay with respect to the oscillation period T. In our case, the period T is obtained from the following formula: 1/T = I/4*C*Vbe where Vbe is the base-emitter voltage of transistor Q2. Thus, the following relation is arrived at: Δt/T = ΔV/4*Vbe = (Vt* lnA'/A)/4*Vbe which, with Vbe = 0.7 V, Vt = 26 mV, and A'/A = 1.5, yields Δt/T = 0.004, the equivalent of a phase error of 0.025 radians, which is independent, however, of the device thermal drift. Since Vbe = Vt*lnI/Is, the above relation will be independent of Vt, which is the single temperature-dependent term. The foregoing formulae lead to conclude that the phase error can be reduced by decreasing the value of the A'/A ratio to the point that, should that ratio equal one, no delay would occur in re-starting and phasing the oscillator further to switching the switch SW. However, it would be unwise to reduce the A'/A ratio of the areas down to unit if uncontrolled re-starting of the oscillator is to be avoided. In a preferred embodiment, shown in Figure 2, the switch SW is comprised of a field effect transistor M1 of the MOS type. This transistor M1 is connected in the device with its source S1 connected to the base of transistor Q7, and its drain D1 associated with the voltage divider consisting of the diode-transistors Q8 and Q9. Understandably, proper sizing of the circuit requires that the internal voltage drop across the transistor M1 be taken into account. The device of this invention also affords the advantage that it does not interfere with the normal operation of the oscillator whenever its intervention is not required.

Claims: A device comprising an oscillator (2) and a circuit (1) for phasing the oscillator (2), which oscillator comprises a multivibrator (3) having a pair of bipolar transistors (Q1,Q2) with their emitters (E1,E2) coupled through a feedback path including a capacitive means (C), characterized in that the circuit (1) comprises an electronic switch (SW) having a control terminal adapted to receive an oscillator inhibit signal (IN) and circuit means (Q7,4,5) connected to the oscillator (2) and responsive to the state of the electronic switch (SW) to de-activate the emitter (E1,E2) coupling of the transistor pair (Q1,Q2) upon an inhibit signal (IN) being applied to the control terminal of the electronic switch (SW) and the voltage (Ve) at the emitter (E 2 ) of one of the bipolar transistors (Q1,Q2) in the pair connected to the capacitive means (C) attaining a predetermined value, by maintaining said emitter (E 2 ) at the predetermined value. A device according to Claim 1, characterized in that the electronic switch (SW) is normally open and the circuit means comprise a transistor (Q7) connected between said emitter (E2) of one of the transistor in the pair (Q1,Q2) and a supply pole for the device, and having a control terminal (87) connected serially to the electronic switch (SW). A device according to Claim 2, characterized in that said circuit means comprise a voltage divider connected to the control terminal of the transistor (Q7) through the electronic switch (SW). A device according to Claim 3, characterized in that said voltage divider comprises a series of diodes (Q8,Q9) connected between a positive supply pole (Vcc) and a grounded current source (I1). A device according to Claim 4, characterized in that said series of diodes is comprised of a transistor pair (Q8,Q9) in a diode configuration. A device according to Claim 2, characterized in that said transistor (Q7) is of the bipolar type with the collector (C7) connected to a supply pole (Vcc), the emitter (E7) connected to said emitter (E2) of the transistor in the pair (Q1,Q2), and the base connected to the electronic switch (SW). A device according to Claim 6, characterized in that said bipolar transistor (Q7) is arranged to have a larger emitter area than the emitter area of the transistor (Q2) in the transistor pair (Q1,Q2) whereto it is connected. A device according to Claim 1, characterized in that said electronic switch (SW) is a field effect transistor (M1) of the MOS type. A device according to Claim 2, characterized in that said electronic switch (SW) is a field effect transistor (M1) of the MOS type having its source (S1) connected to the control terminal (B7) of said transistor (Q7).

Inventors: BETTI GIORGIO, MOLONEY DAVID, SACCHI FABRIZIO, VAI GIANFRANCO, ZUFFADA MAURIZIO, BETTI, GIORGIO, MOLONEY, DAVID, SACCHI, FABRIZIO, VAI, GIANFRANCO, ZUFFADA, MAURIZIO
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1991
Main classification: H03K3
IPC codes: H03K3, H03K4