Non contact type IC-card

Abstract: An IC card of the present invention is capable of preventing an internal battery from being rapidly consumed and internal data from being volatilized due to frequent use or erroneous starts caused by external noise. The number of starts of the card and the number of erroneous starts thereof are respectively counted by registers formed in an RAM (4). When one of these start numbers reaches a set value, the receiving circuit (11) selected is switched to another receiving circuit (12) having a higher threshold value and requiring no bias current, or the threshold value of the receiving circuit is increased by an inhibit circuit so that the internal power consumption of the card is suppressed, and the card is not affected by external noise. In addition, when the value of one of the registers reaches a set value, the external device informs the user of the fact that the value reaches a set value, using sound or a display.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a non-contact type IC card which contains a power source and which enables data communication with an external device such as a terminal device or the like using electric waves. Description of the Related Art Fig. 12 is a block diagram showing a conventional non-contact type IC card. In the drawing, reference numeral 1 denotes the body of an IC card. The IC card body 1 comprises a CPU 2 for controlling signals and processing data in the card, an ROM 3 for storing a program therein, an RAM 4 serving as a data memory, a battery 5, an input/output circuit 6 for parallel-serial conversion/serial-parallel conversion, an antenna 10 and so on. The CPU 2, the ROM 3, the RAM 4 and the input/output circuit 6 are connected to each other through a bus 7 so that data can be transmitted to and received from each other. A modulator/demodulator 8 is interposed between the input/output circuit 6 and the antenna 10, and a transmitting circuit 9 and a receiving circuit 11 are interposed between the modulator/demodulator 8 and the antenna 10. The data output from the input/output circuit 6 is modulated by the modulator/demodulator 8, passed through the transmitting circuit 9 and then output as an electric wave from the antenna 10. The data received by the antenna 10 is amplified by the receiving circuit 11. A trigger signal is input directly to the CPU 2, and the data signal is modulated and converted into a logic level by the modulator/demodulator 8, passed through the input/output circuit 6 and the bus 7 and input to the CPU 2 in which the signal is processed. The battery 5 serves as a power source for each of the circuits. The connection of the battery 5 is not shown in the drawing. The operation of the conventional IC card is described below. Although electricity is usually constantly supplied to the receiving circuit 11 and so on from the battery 5, when the IC card does not communicate with an external device such as a card reader or the like, an oscillation circuit in the CPU 2 is stopped so that the IC card assumes a stand-by state. When a trigger electric wave for activating the CPU 2 is output from the external device and is received by the antenna 10, an analog signal corresponding to the electric wave received is output to the receiving circuit 11 from the antenna 10. If the voltage of the signal exceeds the threshold voltage of the receiving circuit 11, the receiving circuit 11 generates a trigger signal at the logic level and inputs it to the CPU 2. When the trigger signal is input to the CPU 2, the oscillation circuit in the CPU 2 is operated, and the data signal is converted into a digital signal by the receiving circuit 11, demodulated by the modulator/demodulator 8 and then input to the input/output circuit 6. The data input to the input/output circuit 6 is read by the CPU through the bus 7. An operation clock is also supplied to each of the circuits, and the data signal is processed according to the program stored in the ROM 3. During data processing, the data required to be temporarily stored is stored in the RAM 4. The receiving circuit 11 comprises a differential amplifier circuit or the like and has a threshold voltage of several hundreds mV which is generated in the IC card. On the other hand, during or after data processing, transmit data to be transmitted to the external device is input to the input/output circuit 6 through the bus 7. The input/output circuit 6 inputs the data of a digital signal to the modulator/demodulator 8 which modulates the digital signal and inputs it to the transmitting circuit 9. The transmitting circuit 9 converts the digital signal to an analog signal and outputs the analog signal to the antenna 10 which outputs as electromagnetic waves the signal to the external device. Fig. 13 shows the output signal of each of the antenna 10, the receiving circuit 11 and the modulator/demodulator 8. The antenna 10 inputs the analog signal shown in Fig. 13A to the receiving circuit 11. In the receiving circuit 11, for example, a threshold value V TH is set so that the analog signal is converted into the digital signal shown in Fig. 13B on the basis of the threshold value. The digital signal is sent from the receiving circuit 11 to the modulator/demodulator 8, demodulated to the digital signal shown in Fig. 13C by the modulator/demodulator 8 and then sent to the input/output circuit 6. When a single pulse is missing in a fine pulse group, as shown on the right side of the drawing, pulses are generated so as to make up the pulse missing. Conversely, when the IC card sends a signal from the antenna 10, the digital signal shown in Fig. 13C which is sent from the input/output circuit 6 is modulated to the signal shown in Fig. 13B by the modulator/demodulator 8 and converted into the analog signal shown in Fig. 13A by the transmitting circuit 9. The analog signal is supplied to the antenna 10 and then sent to the external device. When communication with the external device is completed, the oscillation circuit of the CPU 2 is again stopped so as to bring the IC card into a stand-by state, thereby suppressing power consumption. However, in the stand-by state, a bias current is constantly passed through the receiving circuit 11 due to the need for receiving the trigger electromagnetic waves. The power consumption of such a type of IC card includes the bias current constantly flowing and the large current of several mA which is consumed for starting the operation of the CPU 2 by the trigger signal generated if the voltage generated in correspondence with the intensity of the electromagnetic waves received by the antenna 10 exceeds the threshold voltage of the receiving circuit 11. However, such a voltage above the threshold voltage is generated by not only the trigger electromagnetic waves output from a predetermined external device but also the noise generated by other electronic devices and sometimes activates the IC card in the same way as that described above. In an environment generating much noise, the battery is therefore early consumed before the end of the guarantee period due to the frequent activation of the CPU 2. This cases the danger of producing a problem with respect to data volatilization or the like. In addition, the battery 5 has a small capacity because the IC card body 1 has a thin plate-like form, and the battery 5 cannot be replaced by a new battery because the battery 5 is sealed by the outer package provided on the IC card body 1. The conventional IC card has the above-described problems. The document EP-A1-0 170 716 relates to an information medium which may have a function similar to a tag and is chiefly used for discriminating one from others. The object in this document is to provide an information medium which is free of poor electrical contact of the medium to an external device. This object is achieved by a medium which uses radio wave, sonic wave or light for receiving or transmitting signals and in which the power consumption of a battery of the medium is minimized. In this medium a decoder determines which circuit elements are to be energized meanwhile all unused circuit elements are not powered. However, this prior art document does not show any features through which is dealt with the problem of a noisy environment which triggers the circuit and promotes an useless discharge of the battery. SUMMARY OF THE INVENTION The present invention has been achieved in consideration of the above circumferences, and it is an object of the invention to provide an IC card which is capable of preventing a battery from being consumed before the end of the garantee period due to the operation error produced by external noise or the like so as to prevent the occurence of a problem with respect to the volatilization of internal data or the like. The problem is solved by an IC card according to claim 1 and an IC card system according to claim 12. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing the arrangement of an IC card in accordance with a first embodiment of the present invention; Fig. 2 is a drawing explaining the register formed in the RAM shown in Fig. 1; Fig. 3 is a schematic drawing showing the first receiving circuit shown in Fig. 1; Fig. 4 is a schematic drawing showing the second receiving circuit shown in Fig. 1; Fig. 5 is a flow chart showing the operation of the IC card in accordance with the first embodiment of the invention; Fig. 6 is a block diagram showing the arrangement of an external device used together with an IC card of the invention; Fig. 7 is a block diagram showing the arrangement of an IC card in accordance with another embodiment of the invention; Fig. 8 is a schematic drawing showing the inhibit circuit shown in Fig. 7; Fig. 9 is a flow chart showing the operation of an IC card in accordance with a second embodiment of the invention; Fig. 10 is a flow chart showing the operation of an IC card in accordance with a third embodiment of the invention; Fig. 11 is a flow chart showing the operation of an IC card in accordance with a fourth embodiment of the invention; Fig. 12 is a block diagram showing the arrangement of a conventional IC card; and Fig. 13 is a drawing showing waveforms for explaining the operation of the IC card shown in Fig. 12. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Embodiments of the present invention are described below with reference to the accompanying drawings. Fig. 1 is a block diagram showing an IC card in accordance with a first embodiment of the present invention. In the drawing, reference numeral 1 denotes a card body. The card body 1 contains a CPU 2 serving as data processing means for controlling the whole card, an ROM 3 serving as non-volatile storage means for storing a program, an RAM 4 serving as volatile storage means for storing data, a battery 5 serving as a power source, and an input/output circuit 6 for parallel-serial conversion/serial-parallel conversion and an antenna 10. The CPU 2, the ROM 3, the RAM 4 and the input/output circuit 6 are connected to each other through a bus 7 so as to transmit and receive data to and from each other. The arrangement of the IC card is substantially the same as that of the conventional IC card shown in Fig. 12. However, the IC card according to the present invention comprises a start number register 4a for counting and storing the total number of starts of the CPU 2, and an erroneous start number register 4b for counting and storing the number of continuous erroneous starts, both of which are provided in the RAM 4. The IC card further comprises a modulator/demodulator 8 interposed between the input/output circuit 6 and the antenna 10, and a transmitting circuit 9, a first receiving circuit 11, a second receiving circuit 12 and a change-over switch 13, which are interposed between the modulator/demodulator 8 and the antenna 10. The transmitting circuit 9 is the same as that provided in the conventional IC card. Although the first and second receiving circuits 11 and 12 will be described below, the second receiving circuit 12 has a higher threshold value than that of the first receiving circuit 11. The change-over switch 13 comprises an electronic switch such as a transistor or the like and is switched according to the switching signal output from the CPU 2. The input/output circuit 6, the modulator/demodulator 8, the transmitting circuit 9, the first receiving circuit 11, the second receiving circuit 12 and the change-over switch 13 constitute input/output controlling means. The data signal subjected to serial-parallel conversion by the input/output circuit 6 is modulated by the modulator/demodulator 8, converted into an analog signal by the transmitting circuit 9 and then output as electromagnetic waves to an external device from the antenna 10. On the other hand, when electromagnetic waves are received by the antenna 10, an analog signal corresponding to the electromagnetic waves received by the antenna 10 is converted into a digital signal by one of the first and second receiving circuits 11 and 12, demodulated by the modulator/demodulator 8, input to the input/output circuit 6 where the signal is converted into a parallel digital signal, and then input to the CPU 2. Figs. 2A and 2B are conceptual drawings showing the bit arrangements of the start number register 4a and the erroneous start number register 4b, respectively, in the RAM 4. The start number register 4a comprises, for example, a 8-bit register in which bits 0 to 7 are used as a counter. Each time the card is started by the trigger signal received, the count value is read, and incremented by 1 and then written so that the number of starts of CPU 2 including the number of erroneous starts thereof is counted and stored. The erroneous start number register 4b similarly comprises a 8-bit register in which bits 0 to 6 are used as a counter, and bit 7 is used for showing continuous operation errors. When an erroneous start occurs, bit 7 is set to "1" and, when the UPC 2 is normally started, it is cleared to "0", and the count value of the register 4b is also cleared to zero. The bit 7 which is presently set to "1" shows the preceding erroneous start. When an erroneous start presently occurs, the count value of the erroneous start number register 4b is read, incremented by 1 and then written, whereby the number of continuous erroneous starts of the CPU 2 can be counted and stored. Fig. 3 is a schematic diagram showing an example of the first receiving circuit 11. In the circuit, two p-channel MOS transistors 31, 32 of the same size form a current mirror, n-channel MOS transistors 33, 34 of the same size form a differential portion, and an n-channel transistor 35 forms a constant-current source. The output terminal of a reference voltage generating circuit comprising a p-channel MOS transistor 36 and an n-channel MOS transistor 37 is connected to the gate of the n-channel MOS transistor 33 to form a differential amplifier on the whole. Reference numerals 38, 39 respectively denote CMOS inverters. When the receiving circuit 11 is selected by the CPU 2, the contact point 13a of the change-over switch 13 is closed, and a signal "H" of high level is supplied to terminal T 6 . At this time, the n-channel MOS transistor 35 is turned on, and a predetermined bias current flows through a circuit comprising the transistors 31 to 35. On the other hand, when a reversed signal "L" of low level is supplied to the gate of the p-channel MOS transistor 36 from the CMOS inverter 38, the p-channel MOS transistor 36 and the n-channel MOS transistor 37 are turned on, and a reference voltage (threshold voltage) is supplied to the gate of the n-channel MOS transistor 33 which constitutes the differential portion. A terminal T 5 is connected to the antenna 10 so that when electromagnetic waves are received by the antenna 10, the output of the antenna 10 is supplied to the gate of the n-channel transistor 34 which constitutes the differential portion. The differential portion thus compares the reference voltage supplied to the gate of the n-channel transistor 33 with the output of the antenna 10 supplied to the gate of the n-channel transistor 34. If the output from the antenna 10 is higher than the reference voltage, a signal "H" of high level is output to a terminal T 4 through the CMOS inverter 39. If the output is lower than the reference voltage, a signal "L" of low level is output to the terminal T 4 . Since the reference voltage is generally as low as several hundreds mV, the receiving circuit 11 can convert the small voltage received by the antenna 10 into the logic level. On the other hand, when the receiving circuit 11 is not selected, the contact point 13b is closed, and the contact point 13a is opened. At this time, the n-channel MOS transistor 35 is turned off, and the bias current is cut off. Further, a reversed signal "H" of high level is supplied to the gate of the p-channel MOS transistor 36 from the CMOS inverter 38, and both the p-channel MOS transistor 36 and the n-channel MOS transistor 37 are turned off. A signal "L" of low level is output from the terminal T 4 . Fig. 4 is a schematic diagram showing an example of the second receiving circuit 12 having a threshold value higher than that of the first receiving circuit 11. The receiving circuit 12 is provided with CMOS trigger inverters 41, 42, 43 which constitute a Schmitt trigger circuit, an n-channel MOS transistor 45 which constitutes a circuit for fixing the input at "L" for the Schmitt trigger circuit when the circuit 12 is not selected, and a CMOS inverter 46 connected to the gate of the n-channel MOS transistor 45. When the receiving circuit 12 is not selected, a signal "L" of low level is supplied to a terminal T 3 from the CPU 2 and is inverted by the CMOS inverter 46 to generate a signal "H" of high level. The signal "H" is supplied to the gate of the n-channel MOS transistor 45 so as to turn the MOS transistor 45 on, and the input to the Schmitt trigger circuit is made "L" level. This causes the the signal "L" of low level to be output to the output terminal T 1 regardless of the signal input to the terminal T 2 from the antenna 10. On the other hand, when the receiving circuit 12 is selected, a signal "H" of high level is supplied to the terminal T 3 from the CPU 2 and is inverted by the CMOS inverter 46 to generate a signal "L" of low level. The signal "L" is supplied to the gate of the n-channel MOS transistor 45 so as to turn the transistor 45 off. The signal input from the terminal T 2 connected to the antenna 10 is thus input to the Schmitt trigger circuit, and a signal corresponding to the input signal is output to the terminal T 1 . The threshold value of the receiving circuit 12 is the CMOS level and is significantly higher than that of the receiving circuit 11. In addition, since the receiving circuit 12 comprises the CMOS inverters 41, 42, 43, 46, no bias current is required, and the battery 5 is not consumed unless a trigger signal higher than the threshold value of the receiving circuit 12 is input. Fig. 5 is a flow chart showing the operating sequence of an IC card in accordance with a first embodiment of the present invention. The IC card is operated according to the program (not shown) stored, for example, in the ROM. The operation is described below with reference to the drawing. In the state where the IC card is normally used, the CPU 2 and the oscillation circuit (not shown) contained therein are stopped. The contact point 13a of the change-over switch 13 shown in Fig. 1 is closed by the operation of the CPU 2, and the receiving circuit 11 is selected. In addition, the bias current flows through the receiving circuit 11 in order to receive the weak trigger electromagnetic waves. In this stand-by state, since the circuit of the IC card comprises a CMOS logic circuit, the consumed current includes only the bias current flowing through the receiving circuit 11. When the trigger electromagnetic waves is sent from an external device and is received by the antenna l0 shown in Fig. 1, the trigger signal is supplied to the CPU 2 through the receiving circuit 12 and the change-over switch 13, and the oscillation circuit in the CPU 2 is operated so as to start the CPU 2 (Step S1). When the operation of the CPU 2 is started, the value of the start number register 4a, which is formed in the RAM 4, is counted up regardless of whether the UPU 2 is normally or erroneously started (Step S2). In this state, the IC card waits for identification information supplied from the external device. For example, when a receive signal such as an identification code or the like is sent from the external device, a decision is made by collation as to whether or not the identification code is regular. When the identification code or the like is not received within a predetermined time, a decision is made as to whether or not it is time out (Step S3). If it is decided that the received signal is regular, the count value of the erroneous start number register 4b is cleared (Step S4), data is sent to and received from the external device (Step S5). On the other hand, if it is decided in Step S3 that the received data is incorrect, or if regular data is not received within a predetermined time, a decision is made as to whether the value b 7 of the erroneous start number register 4b, which is shown in Fig. 2, is "1" or "0" (Step S6). If the value b 7 of bit 7 is "0", it is set to "1", and an operation error is indicated (Step S7). The count value of the erroneous start number register 4b is then counted up (Step S8). If it is decided in Step S6 that the bit value b 7 of the erroneous start number register 4b is "1", since erroneous starts occur at this time and the preceding time, i.e., continuous erroneous starts occur, the count value of the erroneous start number register 4b is immediately counted up (Step S8). In the case of a normal start, after communication with the external device is completed, a decision is made as to whether or not the count value of the start number register 4a reaches the set value (Step S9). In the case of an erroneous start, after the erroneous start number register 4b is renewed, the above decision is made. If the count value does not reach the set value, a decision is made as to whether or not the count value of the erroneous start number register 4b reaches a set value (Step S10). If the count value does not reach the set value, the first receiving circuit 11 is selected (Step S11), and the CPU2 and the oscillation circuit therein are then stopped to return the IC card to the stand-by state (Step S13). On the other hand, if it is decided in Steps 9, 10 that the count value of one of the start number register 4a and the erroneous start number register 4b reaches the set value, the CPU 2 supplies a control signal to the change-over switch 13 so as to select the second receiving circuit 12 (Step S12), and the CPU 2 and the oscillation circuit therein are then stopped so as to return the IC card to the stand-by state (Step S13) When the second receiving circuit 12 is selected, the threshold value becomes the CMOS level. Hence the IC card is not started by the usual trigger electromagnetic waves output from the external device, and it is necessary for driving the IC card to use an external device sending a high level of transmit signal or send trigger electromagnetic waves from the external device which is brought close to the antenna of the IC card. This informs the user of the fact that the consumption of the battery 5 of the IC card proceeds. Even in the state where the user does not use the IC card, the erroneous start of the CPU 2, i.e., the IC card, is suppressed by the second receiving circuit 12, and the consumption of the battery proceeds no more because no bias current is required. In this state, the CPU 2 is started by the card publisher using another external device having a high transmit signal level so that the contents can be read. If the start number register 4a overflows, a new IC card is published, and if the erroneous start number register 4b overflows, after the receiving circuit 12 is changed to the receiving circuit 11, the IC card is reissued to the user. The CPU 2 supplies the control signal to the the change-over switch 13 so as to select the second receiving circuit 12 when one of the total number of starts and the number of continuous erroneous starts reaches the set value. However, if a control signal (second control signal) is supplied to the change-over switch 13 so as to select the first receiving circuit 11 each time the CPU 2 is started by the trigger signal output from the external device, the IC card having a high threshold value can be easily returned to the IC card having a normal threshold value and reproduced by supplying the trigger signal to the CPU 2 from an external device having a high transmit signal level. Although the above-described embodiment concerns the case where the start number register 4a and the erroneous start number register 4b are provided in the RAM 4, an electrically rewritable memory or another counter logic may be provided. Although, in the embodiment, a bit showing continuous operation errors is set at bit 7 in the erroneous start number register 4b, a bit may be provided as another register. In addition, although the embodiment concerns the data transmission to and reception from an external device using electromagnetic waves, the embodiment can be of course applied to the case where data is transmitted and received by using as a medium light. These changes apply to the embodiments below. Fig. 6 is a block diagram schematically showing the structure of the external device used together with the IC card of the present invention. An external device 100 is generally a terminal device, a sensor or the like of a computer system and has substantially the same structure as that of the IC card. The external device 100 includes a CPU 102, a memory 103 having ROM and RAM, a bus 107, an antenna 110, a transmitting circuit 109, a receiving circuit 111, a modulator/demodulator 108 and an input/output circuit 106. Since the configuration of these circuits is the same as that of the IC card, it is not described below. The external device 100 used in the present invention further comprises a display 121 and an alarm generating section 123, both of which are particularly used in the embodiment described below. The display 121 and the alarm generating section 123 are connected to the bus 107 through input/output interfaces 120, 122, respectively. For example, the alarm generating section 123 is a sound source which generates sound. Fig. 7 is a block diagram showing an IC card in accordance with a second embodiment of the present invention. The hardware of this IC card is different from the IC card shown in Fig. 1 in the point that a transmitting circuit 9, a receiving circuit 11a and an inhibit circuit 14 are interposed between a modulator/demodulator 8 and an antenna 10. The transmitting circuit 9 and the receiving circuit 11a are the same as conventional circuits. For example, the receiving circuit 11a may be the same as the receiving circuit shown in Fig. 3 in which a signal "H" of high level is constantly supplied to the terminal T6. The inhibit circuit 14 is controlled by the CPU 2 so as to suppress the voltage received by the antenna 10. This is described below. In this embodiment, the input/output circuit 6, the modulator/demodulator 8, the transmitting circuit 9, the receiving circuit 11a and the inhibit circuit 14 constitute input/output controlling means. Either the start number register 4a for counting and storing the number or starts of the CPU 2 or the erroneous start number register 4b for counting and storing the number of continuous erroneous starts, both of which are provided in the RAM 4, may be provided. This applies to the first embodiment shown in Figs. 1 to 5. In the second embodiment, the data signal which is converted from a serial signal to a parallel signal by the input/output circuit 6 is modulated by the modulator/demodulator 8, converted into an analog signal from a digital signal by the transmitting circuit 9 and then output as electromagnetic waves to the external device from the antenna 10. On the other hand, when electromagnetic waves are received by the antenna 10, an analog signal corresponding to the received electromagnetic waves is sent to the inhibit circuit 14 and the receiving circuit 11a in which the signal is converted directly into a digital signal, and then demodulated by the modulator/demodulator 8. The digital signal is converted into a parallel digital signal by the input/output circuit 6 and then input to the CPU 2. Since the operations of the two registers 4a, 4b provided in the RAM 4 are the same as those described above with reference to Fig. 2, the operations are not described below. Fig. 8 shows an example of the circuit comprising the antenna 10 and the inhibit circuit 14. The antenna 10 comprises a resonance circuit formed by a coil 10a and a capacitor 10b. The inhibit circuit 14 comprises a p-channel MOS transistor 14a and a flip flop 14b for setting and resetting on the basis of the inhibit signal/inhibit release signal output from the CPU 2. When the inhibit signal which is a low level signal "L" is input to the set terminal S from the CPU 2, the flip flop 14b is set. This brings the output Q of the flip flop 14b into the level "L" and the transistor 14a is in a conducting (on) state so as to inhibit the receiving voltage of the antenna 10. On the other hand, when the inhibit release signal of the low level "L" is input to the reset terminal R from the CPU 2, the flip flop 14b is reset. This brings the output Q of the flip flop 14b into the "H" level, and the transistor 14a is in the non-conducting (off) state so as to release the inhibition of the voltage received by the antenna 10. When the CPU 2 is started, the CPU 2 invariably outputs the inhibit release signal. It is also necessary to use the transistor 14a having a low threshold voltage (about 0.1 V) and set the resistance in the on state to a value which allows the receiving circuit 11a to receive the trigger signal only in the case where the IC card and the external device are extremely close to each other. Fig. 9 is a flow chart showing the operation sequence of the IC card in accordance with the second embodiment of the present invention. The IC card is operated according to the program (not shown) which is stored, for example, in the ROM in the IC card. This embodiment does not use the erroneous start number register 4b. The operation of the second embodiment is described below with reference to Figs. 2 and 6 to 9. When the IC card is used in the normal state, the CPU 2 and the oscillation circuit (not shown) contained therein are stopped. However, since a bias current flows through the receiving circuit 11a in order to receive the weak trigger electromagnetic waves. In this stand-by state, the current consumed by the IC card includes only the bias current flowing through the receiving circuit 11a. When the trigger electromagnetic waves are sent from the external device and received by the antenna 10 shown in Fig. 7, the trigger signal is supplied to the CPU 2 through the receiving circuit 11, the oscillation circuit in the CPU 2 is operated so as to start the CPU 2 (Step S1). When the CPU 2 is started, the count value of the start number register 4a, which is formed in the RAM 4, is counted up regardless of whether the CPU 2 is started normally or erroneously (Step S2). The CPU 2 further outputs the inhibit release signal (second control signal) to the flip flop 14b of the inhibit circuit 14 so as to reset the flip flop 14b and turn the transistor 14a off, thereby stopping the inhibit function. However, it is a matter of course that when the inhibit function has been already stopped, no change occurs even if the inhibit release signal is output. A decision is then made as to whether or not the value of the start number register 4a is the set value or more (Step S3). If the value does not reach the set value, the flow moves to Step S4, the IC card waits for the identification data supplied from the external device. In this state, when an identification code or the like is supplied from the external device, a decision is made as to whether or not the received signal such as the identification code or the like is regular. When no identification code is received within a predetermined time, it is decided as time-out (Step S4). If it is decided that the received signal is regular, data is transmitted and received (Step S7). If it is decided that the identification code is wrong, or if it is time out, the oscillation circuit in the CPU 2 is immediately stopped so that the IC card is in the stand-by state (Step S8). On the other hand, if it is decided in Step S3 that the value of the start number register 4a is the set value or more, the flow moves to Step S5 in which the CPU 2 outputs the inhibit signal (control signal) to the flip flop 14b of the inhibit circuit 14 so as to turn the transistor 14a on and inhibit the voltage received by the antenna 10 (Step S5). Code A showing that the number of starts becomes the set value or more is then sent to the external device (Step S6). The oscillation circuit of the CPU 2 is then stopped in Step S8, and a series of operation steps are completed. When the external device receives the code A, the display 121 shown in Fig. 6 displays or the alarm generating section 123 generates alarm sound to notify the user of the end of the life of the IC card. Fig. 10 is a flow chart showing the operation sequence of an IC card in accordance with a third embodiment of the present invention. Although this embodiment uses the external device 100 shown in Fig. 6 and the IC card 1 shown in Fig. 7, the program stored in the IC card 1 is different from that in the second embodiment. In addition, the IC card of this embodiment employs both the start number register 4a and the erroneous start number register 4b. The operation of the third embodiment is described below with reference to Figs. 2, 6 to 8 and 10. In Fig. 10, since Step 1 to Step 3 in which a decision is made on the start number register 4a are the same as those in the second embodiment, and since the operations in the steps (S5 - S6 - S8) when it is decided in Step S3 that the value of the register 4a reaches the set value are also the same as those in the second embodiment, these steps are not described below. If it is decided in Step S3 that the value of the register 4a is less than the set value, the flow moves to Step S4 in which the IC card waits for identification data supplied from the external device. In this state, when an identification code is supplied from the external device, a decision is made as to whether or not the received signal of the identification code is regular, and when no identification code is received within the predetermined time, it is decided as time-out (Step S4). If it is decided that the received signal is regular, the erroneous start number register 4b is cleared (reset) (Step S9), and data is transmitted and received (Step S7). When data is completely transmitted and received, the oscillation of the oscillation circuit of the CPU 2 is stopped so that the IC card is again in the stand-by state (waits for the trigger) (Step S8). If it is decided in Step S4 that the identification code is wrong or that it is time-out, a decision is made as to whether the value b 7 of bit 7 of the erroneous start number register 4b, which is shown in Fig. 2, is "1" or "0" (Step S10). If the value b 7 is "0", it is set to "1" for indicating that an erroneous start occurs (Step S11), and the count value or the erroneous start number register 4b is then counted up (Step S12). If it is decided in Step S10 that the bit value b 7 of the erroneous start number register 4b is "1", since erroneous starts occur at the preceding time and this time, i.e., continuous erroneous starts occur, the value of the erroneous start number register 4b is immediately counted up (Step S12). A decision is then made in Step S13 as to whether or not the value of the continuous erroneous start number register 4b reaches the set value. If the value is less than the set value, the oscillation is stopped so that the IC card is in the stand-by state in Step S8. If it is decided in Step S13 that the value reaches the set value, the inhibit signal is supplied to the inhibit circuit 14 (refer to Fig. 8) so as to make the inhibit function to work (Step S5), and the oscillation of the oscillation circuit in the CPU 2 is then stopped so that the IC card is in the stand-by state (Step S8). Fig. 11 is a flow chart showing the operation sequence of an IC card in accordance with a fourth embodiment of the present invention. Although this embodiment uses the external device 100 shown in Fig. 6 and the IC card 1 shown in Fig. 7, the program stored in the IC card 1 is different from that in the above embodiment. The IC card 1 of this embodiment employs only the start number register 4a. The operation of the fourth embodiment is described below with reference to Figs. 2, 6 to 8 and 11. In the flow chart of the fourth embodiment, Steps S14 and S15 are added to the flow chart of the second embodiment shown in Fig. 9. If it is decided in Step S3 that the value of the start number register 4a reaches the set value, the flow moves to Step S14 in which the IC card waits for a dump command from the external device. If no dump command is received within a predetermined time, the flow moves to Step S5, and the processing in the same steps (Steps S5 - S6 - S8) as those in the second embodiment is performed. On the other hand, when the dump command is received from the external device within the predetermined time in Step S14, the data stored in the memory (RAM 4) is dumped or transmitted. The flow then moves to Step S5. In this embodiment, the IC card has as means for protecting the IC card from trouble the function to read the data stored therein when periodically receiving the dump command from the external device. Although the four embodiments are described above, the functions of the respective embodiments can be combined as occasion demands. The present invention is not limited to the four embodiments, but the invention is limited by the Claims. As described above, in the IC card of the present invention, since the total number of starts of the card (CPU) and the number of continuous erroneous starts are counted and stored so that the lower threshold value of the received signal level, which allows the card to receive a signal, is increased when one of the two start numbers reaches the set value, the card is falsely started no more by external noise or the like. In addition, since the bias current flowing through the receiving circuit is made unnecessary at the same time as the increase in the threshold value, the data stored in the IC card is not lost due to consumption of the battery. Further, if the threshold value is extremely increased, the IC card cannot be started by a usual external device. In this case, the card can be reproduced (returned to the original state) by supplying the trigger signal to the card from a dedicated external device which has a high transmit signal level and which is brought close to the card. It is also possible to add the alarm function and dump function to the card and obtain the IC card having high reliability.

Claims: An IC card for transmitting and receiving data and signals to and from an external device using electromagnetic waves , said IC card comprising: data processing means (2) to be started to operate from a stand-by state by a trigger signal output from said external device; non-volatile storage means (3) for storing a programm; volatile storage means (4) for storing data; start number counting/storing means (4a, 4b) for counting and storing at least the number of starts of said data processing means (2); wherein said data processing means (2) controls the whole card and processes data in said card according to said program, and generates a control signal when the count value of said start number counting/storing means (4a, 4b) reaches a set value; a bus (7) for connecting said processing means (2), said non-volatile storage means (3), said volatile storage means (4) and said start number counting/storing means (4a, 4b) to each other; an antenna (10) for converting an electrical analog transmit signal to be output from said card into electromagnetic waves and sending said electromagnetic waves to the outside of said card, and converting electromagnetic waves received from the outside of said card into an electrical analog receive signal; input/output controlling means (6, 8, 9, 11, 12, 13; 6, 8, 9, 11a, 14) connected between said antenna (10) and said bus (7) so as to increase the lower threshold value of a receivable signal level to make the IC card insensitive to the trigger signal according to said control signal supplied from said data processing means (2) on the basis of the fact that the count value of said start number counting/storing means (4a, 4b) reaches said value; and a battery (5) serving as a power source for each of said means. An IC card according to claim 1, wherein said input/output controlling means (6, 8, 9, 11, 12, 13) comprises a transmitting circuit (9), a first receiving circuit (11) requiring a bias current, a second receiving circuit (12) having a threshold value higher than that of said first receiving circuit (11), and a change-over switch (13) for connecting said second receiving circuit (12) between said antenna (10) and said bus (7) in place of said first receiving circuit (11) according to said control signal supplied from said data processing means (2) when the count value of said start number counting/storing means (4a, 4b) reaches said set value, said bias current flowing through said receiving circuit (11) being stopped when said first receiving circuit (11) is switched to said second receiving circuit (12); and said start number counting/storing means (4a, 4b) comprises a start number register (4a) formed in said volatile storage means (4) so as to count the total number of starts, said register (4a) being counted up by one under control of said data processing means (2) each time said data processing means (2) is started. An IC card according to Claim 2, wherein said input/output controlling means (6, 8, 9, 11, 12, 13) further comprises a modulator/demodulator (8) connected to said transmitting circuit (9) and said change-over switch (13) and an input/output circuit (6) for serial/parallel conversion connected between said modulator/demodulator (8) and said bus (7). An IC card according to Claim 1, wherein said input/output controlling means (6, 8, 9, 11a, 14) comprises a transmitting circuit (9), a receiving circuit (11a) requiring a bias current, and an inhibit circuit (14) connected between said receiving circuit (11a) and said antenna (10) so as to earth said antenna (10) through a predetermined resistance according to said control signal supplied from said data processing means (2) when the count value of said start number counting/storing means (4a) reaches said set value; and said start number counting/storing means (4a, 4b) comprises a start number register (4a) formed in said volatile storage means (4) so as to count the total number of starts, said register (4a) being counted up by one under control of said data processing means (2) each time said data processing means (2) is started. An IC card according to Claim 4, wherein said input/output controlling means (6, 8, 9, 11a, 14) further comprises a modulator/demodulator (8) connected to said transmitting circuit (9) and said receiving circuit (11a) and an input/output circuit (6) for serial/parallel conversion connected between said modulator/demodulator (8) and said bus (7). An IC card according to Claim 1, wherein when the count value of said start number counting/storing means (4a, 4b) reaches said set value, said data processing means (2) generates said control signal to said input/output controlling means (6, 8, 9, 11a, 14) and simultaneously generates a code for informing said external device of the fact that the count value reaches said set value through said antenna (10). An IC card according to Claim 1, wherein said start number counting/storing means (4a, 4b) counts and stores the total number of starts of said data processing means (2) and the number of continous erroneous starts thereof so that said data processing means (2) generates said control signal when one of said total number of starts and number of continuous erroneous starts reaches respective set values. An IC card according to Claim 7, wherein when one of said total number of starts and said number of continous erroneous starts, which are stored in said start number counting/storing means (4a, 4b), reaches respective set values, said data processing means (2) generates said control signal to said input/output controlling means (6, 8, 9, 11a, 14) and, when said total number of starts reaches said set value, said data processing means (2) further generates a code for informing, through said antenna (10), the outside of said card of the fact that said total number reaches said set value. An IC card according to Claim 8, wherein said start number counting/storing means (4a, 4b) comprises a start number register (4a) for counting and storing said total number of starts and an erroneous start register (4b) for counting and storing said number of continuous erroneaus starts, both of which are formed in said volatile storage means (4) and which are counted up or cleared under control of said data processing means (2). An IC card according to Claim 9, wherein said start number register (4a) contains a plurality of bits for counting said total number of starts of said processing means (2), and said erroneous start number register (4b) contains a plurality of bits for counting said number of continuous erroenous starts and a single bit for showing that an erroneous start occurs at the preceding time; and said data processing means (2) counts up said start number register (4a) by one each time it is started by receiving a trigger signal through said antenna (10), and when the identification code sent from said external device after the trigger signal is irregular, and when no identification code is received within a predetermined time, if an erroneous start occurs at the preceding time, said data processing means (2) then counts up said erroneaus start counting bits of said erroneous start number register (4b) by one, while when said identification code is regular, said data processing means (2) clears said erroneous start counting bits of said erroneous start number register (4b). An IC card according to Claim 1, wherein said data processing means (2) further generates a second control signal for returning the threshold value of said receivable signal level of said input/output controlling means (6, 8, 9, 11, 12, 13; 6, 8, 9, 11a, 14) to a normal value each time said data processing means (2) is started by said trigger signal. An IC card system in which data and signals are transmitted and received, by using electromagnetic waves, between an external device and an IC card comprising data processing means (2) started to operate from a stand-by state by a trigger signal output from said external device, said IC card system comprising: an external device (100) having means for generating an identification code after generating a trigger signal for starting an IC card, periodically generating a dump command and displaying or indicating by sound the fact that the total number of starts of said IC card reaches a set value according to a code sent from IC card; and an IC card comprising non-volatile storage means (4) for storing a program, volatile storage means for storing data (3), start number counting/storing means (4a, 4b) for counting and storing the total number of starts of said data processing means (2) and the number of continuous erroneous starts thereof, the data processing means (2) for controlling the whole card and processing data in said card according to said program, and for generating a control signal when one of the count values of said start number counting/storing means (4a, 4b) reaches respective set values, and when said total number of starts reaches a set value, reading all data stored in said volatile storage means (4) according to said dump command generated from said external device (100) and then generating said code showing the fact that the number of starts reaches a set value to said external device (100), a bus (7) for connecting said processing means (2), said non-volatile storage means (3), said volatile storage means (4) and said start number counting/storing means (4a, 4b) to each other, an antenna (10) for converting an electrical analog transmit signal to be output from said card into electromagnetic waves and sending said electromagnetic waves to the outside of said card, and converting electromagnetic waves received from the outside of said card into an electrical analog receive signal, input/output controlling means (6, 8, 9, 11, 12, 13; 6, 8, 9, 11a, 14) connected between said antenna (10) and said bus (7) so as to increase the lower threshold value of a receivable signal level to make the IC card insensitive to the trigger signal according to said control signal supplied from said data processing means (2) on the basis of the fact that one of the count values of said start number counting/storing means (4a, 4b) reaches a set value, and a battery (5) serving as a power source for each of said means.

Inventors: FURUTA SHIGERU, TAKEBAYASHI ETSUSHI, FURUTA, SHIGERU,, TAKEBAYASHI, ETSUSHI,, Furuta, Shigeru, c/o Mitsubishi Denki K.K., Takebayashi, Etsushi, c/o Mitsubishi Electric
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1991
Main classification: G06K19
IPC codes: G06K19, G06K7