Circuital arrangement for preventing latch-up phenomena in vertical PNP transistors with insulated collector

Abstract: A circuital arrangement which comprises a vertical PNP transistor (15) with insulated collector, which has a P-type collector structure (6) surrounded by an N-type well (2') and forms a junction therewith. In order to prevent latch-ups of the parasite SCR (17) which is formed by the structure of the vertical transistor (15) with insulated collector without limiting the voltage which can be applied between the collector and the emitter thereof to values below the intrinsic breakdown ones, the circuital arrangement comprises an auxiliary PNP transistor (25) the emitter whereof is short-circuited with the emitter (E) of the vertical PNP transistor (15), the base whereof is connected to the base (B) of the vertical PNP transistor (15) and the collector whereof is connected to the N-type well (2'), and operates as a switch which biases the N-type well (2') at a voltage which is close to the voltage of the emitter (E) of the vertical PNP transistor (15) when the latter is saturated, reverse-biasing the collector/N-well junction (6,2'), and opens when the vertical PNP transistor (15) is off, limiting the voltage applied to the collector/N-well junction (6,2').

Description: The present invention relates to a circuital arrangement for preventing latch-up phenomena in vertical PNP transistors with insulated collector. As is known, in vertical PNP transistors with insulated collector, an N-type epitaxial well is present around the collector structure and must be connected to an appropriate voltage in order to avoid problems in the operation of said PNP transistor. On this subject, reference should be made to figure 1, which is a transverse sectional view of a portion of a wafer of semiconductor material which integrates an insulated-collector PNP transistor. Such an arrangement is described in the document "Power Integrated Circuits: Physics, Design, and Applications", Editor: Paolo Antognetti, McGraw-Hill Book Company, 1986, pages 5.2-5.6. In this figure, the P-type substrate is indicated by 1, whereas 2 indicates the epitaxial layer, in which P-type insulation regions 3, which extend from the substrate to the main surface 4 of the device which integrates, among other devices, the PNP transistor, separate the well 2' from the other portions of the epitaxial layer. An N-type buried layer (a so-called "bottom N-well") 5 extends astride the substrate 1 and the epitaxial layer 2 (within the region delimited by the insulations 3), and the P-type collector layer 6 extends above the buried layer 5 and is connected to the main surface 4 of the device by means of a deep region 7, again of the P type, which extends in a ring-like shape and delimits a further well 2" of the epitaxial layer, which defines the base of the transistor. A region 8 (which defines the so-called "top N-well") is indicated inside said second well 2", and an enhanced N-region 10, at the base contact B, and the P-type emitter region 11 are formed therein. The figure furthermore illustrates the emitter, base and collector contacts, respectively E, B and C, of the vertical PNP transistor, and a contact S for connecting the well 2' to an appropriate voltage; said contact is provided at an enhanced region which faces the main surface 4. Figure 1 furthermore illustrates the electrical equivalents of some components which are the result of the illustrated structure, which comprise: the required vertical PNP transistor, which is indicated by 15 and is formed by the emitter layer 11, by the base layers 2", 8, 10 and by the collector layers 6, 7; a parasite NPN transistor 16 formed by the collector emitter 2", by the base layer 6 and by the emitter base 5; a parasite SCR 17, which is formed by the transistors 15 and 16; and a further parasite PNP transistor 18 formed by the emitter layer 6, the base layers 5 and 2' and the collector layer 1. In order to prevent the parasite PNP transistor 18 from having an open base and to prevent the occurrence of unwanted latch-up phenomena affecting the SCR 17, due for example to voltage gradients (dV/dt) which can occur across it, it is therefore necessary to connect the N-well 2' to an appropriate voltage. For this purpose, it has already been thought to connect the N-well 2', which also is the emitter of the parasite NPN transistor 16, to the emitter of the vertical PNP transistor, which is usually connected to the highest voltage (V cc ), short-circuiting the contacts E and S. The equivalent electrical layout is shown in figure 2, in which only the vertical PNP transistor 15 and the parasite NPN transistor 16 have been illustrated for the sake of clarity. However, although this solution is very simple and suitable for avoiding the latch-up of the SCR 17, it is not free from disadvantages, since the breakdown voltage which can be withstood between the emitter and the collector of the vertical transistor 15 is limited by the breakdown voltage of the junction formed by the layers 5 and 6 (i.e., by the breakdown of the base-emitter junction of the parasite NPN transistor 16, which, as is clearly illustrated in figure 2, by means of the indicated connection, is parallel-connected to the emitter-collector portion of the vertical PNP transistor 15). This limitation does not create problems for low-voltage processes (up to 10 V), but is unacceptable in case of high-voltage processes. Another solution consists in connecting the N-well 2' to the collector of the vertical PNP transistor 15 (connecting the contact S to the contact C), thus short-circuiting the base-emitter junction of the parasite NPN transistor 16. However, this solution entails only a local short-circuit, and in the presence of high currents, due to the drop on the collector layer 6, said base-emitter junction can become forward-biased, causing on the average the latch-up of the parasite SCR 17. Given this situation, the aim of the present invention is to provide a circuital arrangement for preventing latch-up phenomena in vertical PNP transistors with insulated collector which can solve the disadvantages of the prior art, and in particular can prevent, effectively and in any operating condition, even in the presence of high currents and/or rapid voltage variations, the latch-up of parasite devices which are intrinsic to the structure of vertical insulated-collector transistors. Within the scope of this aim, a particular object of the present invention is to provide a circuital arrangement which can also be used in high-voltage processes and in particular is such as not to entail limitations in the operation of the vertical transistor due to early breakdown with respect to the breakdown values of the vertical transistor itself. An important object of the present invention is to provide a circuital arrangement of the indicated type which is simple both conceptually and from the point of view of execution and is thus highly reliable. Still another object of the present invention is to provide a circuital arrangement of the indicated type which does not require a large number of components and in particular does not have a large area occupation. Not least object of the present invention is to provide a circuital arrangement which can be easily integrated and which does not require, for its manufacture, devices or processes which differ from those commonly used in the electronics industry and thus has modest manufacturing costs. This aim, these objects and others which will become apparent hereinafter are achieved by a circuital arrangement for preventing latch-up phenomena in vertical PNP transistors with insulated collector, as defined in the accompanying claims. The characteristics and advantages of the invention will become apparent from the description of a preferred embodiment, illustrated only by way of non-limitative example in the accompanying drawings, wherein: figure 1 is a transverse sectional view taken through a silicon wafer which integrates a vertical PNP transistor with insulated collector; figure 2 is a simplified equivalent circuit layout of the arrangement, in which the N-well which is external to the collector of the vertical PNP transistor is short-circuited with the emitter of said transistor; figure 3 is a combined view, partially representing a transverse cross-section and partially illustrating an electric equivalent, of the arrangement according to the invention; figure 4 is a simplified circuit layout of the arrangement according to the invention. Figures 1 and 2 are not described hereinafter; reference is made to the preceding description for said figures. With reference to figure 3, the arrangement according to the invention comprises, besides the vertical PNP transistor with insulated collector, which is provided in a known manner (and for which the same reference numerals used for figure 1 have therefore been kept), an auxiliary PNP transistor 25 which has the function of biasing the N-well 2' (which is external with respect to the collector of the vertical PNP transistor 15) at a voltage which is very close to the voltage of the emitter of the vertical PNP transistor 15 (and is therefore higher than the collector voltage of said transistor), avoiding the problems of direct connection to said emitter. Essentially, the auxiliary PNP transistor 25 defines a switch which, during the saturated operation of the transistor 15, electrically connects the emitter thereof to the N-well and, when the vertical PNP transistor 15 is off and has a high emitter-collector drop, opens in turn, preventing the entire emitter-collector drop from being applied to the base-emitter junction of the parasite NPN transistor 16 (junction between the collector of the vertical PNP transistor and the buried N-type layer 5). In detail, the structure of figure 3 furthermore comprises a P-type substrate 1 and an N-type epitaxial layer 2, which accommodate, inside them, the insulation layer or region 3, the N-type layer 5 which defines the bottom N-well, the collector layers 6 and 7, the base layer 2" and the emitter layer 11 of the vertical PNP transistor 15. The N + -type enhanced regions 10 and 20 are again furthermore provided, and the emitter, base and collector contacts E, B and C of the vertical PNP transistor 15 and the contact S of the N-type well 2' are furthermore represented on the surface 4. According to the invention, an auxiliary PNP transistor 25 is defined in a well which is insulated from the well 2' which accommodates the vertical PNP transistor 15 (e.g. a well 2"' adjacent to the well 2'), and the emitter of said auxiliary transistor is connected to the emitter E of the vertical PNP transistor 15, its base is connected to the base of said transistor by means of a resistor R 1 , and its collector is connected to the N-well 2' which surrounds the collector of the transistor 15. The auxiliary transistor 25 and the resistor R 1 can be executed according to any appropriate method (e.g., the auxiliary transistor can be provided as a lateral or vertical PNP, whereas the resistor R 1 can be provided as a diffused or implanted resistor). The resistor R 1 , the value whereof depends on the current levels which circulate in the circuit and in any case is not critical, has the function of limiting the current which flows in the auxiliary transistor 25 to very low levels, so that said auxiliary transistor can have a minimal area, so as not to increase in practice the area occupation of the circuit which comprises the vertical PNP transistor 15. By virtue of the described connection, and in particular of the common driving between the vertical PNP transistor 15 and the auxiliary PNP transistor 25, said two transistors are driven together so as to saturate or switch off, and therefore, when the vertical PNP transistor 15 saturates, the auxiliary transistor is also saturated, raising the N-well 2' to a voltage which is close to that of the emitter E of the vertical transistor 15 and thus reverse-biasing the base-emitter junction of the parasite transistor 16 (see also on this subject figure 4, which illustrates the electrical connections between these three components), which thus cannot switch on. By way of example, consider the case of a vertical PNP power transistor 15 which has a saturation resistance of 0.3 Ω at a collector current of 3 A. In this condition, the transistor 15 has a drop of 0.9 V between the emitter and the collector. The auxiliary PNP transistor 25 has, between the emitter and the collector, a drop of 10-20 mV (emitter-collector saturation voltage for a zero collector current), and therefore the N-well which surrounds the collector of the vertical PNP transistor 15 (illustrated by the contact S in figure 4) is at a voltage which is very close to the emitter voltage of the vertical PNP transistor. Therefore, the junction between the N-well 2' and the collector 6, 7 of the vertical PNP transistor (base-emitter junction of the NPN transistor 16) is reverse-biased by approximately 0.9 V. Instead, when the vertical PNP transistor 15 is off, part of its emitter-collector drop is withstood by the auxiliary transistor 25, which is also off, so that the base-emitter junction of the parasite NPN transistor 16 is not raised to its breakdown voltage and thus does not limit the collector-emitter drop which can be applied to the vertical PNP transistor and allows to use it even in high-voltage circuits. As can be seen from the above description, the invention fully achieves the intended aim and objects. A circuital arrangement has in fact been provided which can also be applied to high-voltage devices without having unwanted latch-ups of parasite structures. The invention is furthermore circuitally simple, is reliable, does not require a high area expenditure (since, as mentioned, the auxiliary transistor 25 can be executed with a minimal area) and can be easily integrated, without requiring modifications in known manufacturing processes, so that it has manufacturing costs comparable with those of known solutions. Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included for the sole purpose of increasing the intelligibility of the claims and accordingly such reference signs do not have any limiting effect on the scope of each element identified by way of example by such reference signs.

Claims: Circuital arrangement for preventing latch-up phenomena in vertical PNP transistors with insulated collector, comprising a vertical PNP transistor (15) which comprises a P-type substrate (1), a N-type buried layer (5) extending astride said substrate (1), and N-type well (2') positioned above said N-type buried layer (5), an insulated collector region surrounded by said N-type well (2') which forms a junction therewith and being defined by a P-type layer (6) extending above said N-type buried layer (5) and within said N-type well (2') and by a P-type deep region (7) connecting said P-type layer (6) to the surface of said PNP transistor (15), a N-type base region (2") surrounded by said insulated collector region, and a emitter region (11) defined by a P-type region formed within said N-type base region (2"), said emitter, base and insulated collector regions being electrically connected to emitter, base and collector terminals, respectively, characterized in that it comprises an auxiliary PNP-type transistor (25) having its emitter terminal electrically connected to the emitter terminal (E) of the vertical PNP transistor (15), having its base terminal electrically connected to the base terminal (B) of the vertical PNP transistor (15), and having its collector terminal electrically connected to said N-type well (2'), said auxiliary transistor (25) being able to connect said N-type well (2') to said emitter region (11) when said vertical PNP transistor (15) is in the saturated on state and for opening when said vertical PNP transistor (15) is in the off state. Circuital arrangement according to claim 1, characterized in that it comprises a resistor (R 1 ) which is interposed between the base terminals (B) of said vertical PNP transistor (15) and of said auxiliary PNP transistor (25). Circuital arrangement according to claims 1 or 2, characterized in that said auxiliary PNP transistor (25) is integrated in an epitaxial well (2''') which is insulated with respect to said vertical PNP transistor (15).

Inventors: BERTOTTI FRANCO, FERRARI PAOLO, BERTOTTI, FRANCO, FERRARI, PAOLO
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1991
Main classification: H01L27
IPC codes: H01L27, H01L21, H01L29