MULTICASTING IN A FPS SWITCH

Abstract: A system and network are disclosed for providing multicasting capability within a packet switched network, such as FPS or ATM. Each packet's header includes a type indicator bit or bits. One form of type indicator indicates normal port to port switching: a second form indicates switching to a single port, and then to each of a set of outputs defined by the address portion of the header via a separate connection. Contention is thereby reduced in the switching fabric itself.

Description: MULTICASTING IN A FPS SWITCH HELP OF INVENTION The present invention relates to the provision of multicasting or broadcasting capability within a fast packet switched (FPS), asynchronous transfer mode (ATM) or similar communications network. BACKC3RCXJND in the course of switching packetised data, it is often desirable to enable a single data stream comprising one or more packets to be sent to more than one address. This is known as multicasting. If all destinations are addressed, it is termed a broadcast. One means of providing such a facility is to simply insert many packets into the switch inputs, each addressed to a desired output but carrying the same data. This creates a large demand on switching capacity for what is, essentially, one data stream. Known packet broadcast or multicast arrangements such as that shown in US Patent Nos. 4991171 and 5001702 to Terasiinna et al, generally require replication of packets within the switching fabric. This leads to increased complexity of the switching fabric in requiring additional stages within the fabric and/or different internal switching elements which have more functional complexity. The replication of packets leads to greater contention and congestion within the fabric. It is therefore an object of the present invention to provide a multicasting capacity without placing unacceptable demands on the switching fabric. SUMMARY OF INVENTION According to one aspect the present invention comprises a packet switching network comprising switching means having a plurality of inputs and a plurality of outputs, and port control means associated with each output and with each input, wherein packets comprise a header including an address, and a payload, characterised in that each header further comprises a type indicator, such that each packet having a first type indicator is switched to a one of said outputs defined by the address portion, and is then communicated directly to the port control means associated with the addressed output, and each packet having a second type indicator is switched to a single one of said outputs, and is then communicated via a separate communications connection to one or more of said port control means. According to another aspect the present invention comprises a method of multicasting within a packet switching network, said network comprising switching means having a plurality of inputs and outputs, port control means associated with each output, and means for communicating independent of said switching means connecting a defined output of said switching means and a plurality of said port control means, said packets comprising a header including a type indicator and an address, and a payload, wherein packets having a unicast type indicator are switched by said switching means to an output defined by the respective address and then to the respective port control means, and packets having a multicast type indicator are switched by said switching means to said defined output and communicated via said means for communicating to a set of output port control means defined by the respective address. BRIEF DESCRIPTION QF PRAWINGS The invention will be described in more detail with reference to the accompanying figures, in which: Figure 1 is a schematic block diagram of one embodiment of the inventive arrangement; Figure 2 shows one suitable packet format for the inventive arrangement; and Figure 3 illustrates in block form an output switch port controller. PETAILEP DESCRIPTION Referring to Figure 1, this illustrates a 4-port system 10 capable of switching 4 inputs to any of 4 outputs, via switching Fabric unit (SFU) 20. It should be appreciated that the exact switching fabric implementation, except in so far as it must be capable of the functions defined below, is not an essential element of the invention. Similarly, a 4-port unit is illustrated only from the point of view of simplicity: practical switching units generally involve at least 16 x 16 units, and may be of much greater complexity, indeed, the present invention becomes more advantageous as complexity is increased. SFU 20 has 4 ports 0 - 3, each with an associated switch port controller (SPC) 300 - 303. SPC's provide an interface between various data formats and the packetised data switched by SFU 20. Preferably, the SFU 20 is adapted to switch fixed- length packets, although the present invention is also applicable to variable length packets. SPC's 300 - 303 also control the input and output packet flows to and from SFU 20. Each SPC according to this embodiment of the invention has at least 2 connections to the SFU 20: a multicast address connection, and a unicast address connection. The exception is SPC 300, in which these connections may share the same physical connection. SPC's 301 - 303 are connected to unicast addressed ports by connections 25, and to multicast output from the switch by connections 28. The switching system will be better understood with reference to Figure 2. Each packet comprises a payload 12 and header 13, the header including a tag bit indicating whether the packet has a unicast or multicast address (U/M), and an address field. SPC's 300 - 303 generate a header 13 for each incoming packet as described so as to facilitate switching according to the present invention. This header 13 is generated by reference to a look-up table and the existing header and address of the external packet. The table includes instructions as to whether header 13 should have a unicast or multicast tag bit. It should be appreciated that an important distinction between the present invention and prior art techniques is that the switch per se has only to switch one packet - multicast packets are disseminated via one port to a separate communications path for this purpose alone. Following is a description which uses a simple bit set/not set technique to determine addressing within the multicast path of the switching system. However, the invention may be used with a wide range of other addressing techniques, as will be apparent to the reader. For instance an implementation is possible where the multicast address must be compared with a software - set table to determine whether given ports are addressed, so that multicast groups can be defined in advance. Such an implementation is particularly applicable to larger number of ports switched. According to the embodiment illustrated, the meaning of the address depends upon the setting of the U/M bit. If the U/M bit indicates unicast, the address is the binary value of the destination switch port. In the multicast case each bit of the address will indicate that a particular switch port is addressed. An example of single address and multicast addressing is provided to clarify the system operation. A packet with a U/M tag indicating unicast address of 2 is input by SPC to SFU 20, where it is switched to port 2, to the unicast port of SPC 302, and then outputs. A packet with a U/M tag indicating a multicast address in which bits 0 and 2 are set is input by an SPC to SFU 20. All packets with a multicast address tag are switched by SFU to port 0, and presented by multicast connection 28 to the multicast ports of each SPC. Each SPC 300 - 303 sees the packet on the multicast connection 28 and reads it in only if there is a match between the number of the SPC and a bit set in the multicast address. SPC's 300 and 302 therefore read in the packet and send it to their respective outputs. SPC 300 is preferably chosen to be a port having comparatively low levels of traffic, as it receives any packets which are unicast to it, and the link between port 0 and SPC 300 additionally carries all multicast addressed traffic. SPC 300 only reads packets unicast to it or packets with a multicast address in which bit 0 is set. Figure 3 illustrates the output part of an SPC, such as SPC 301 : what we may term the output switch port controller (OSPC) 30, as it handles packets output by SFU 20 from a port. FIFO 40 receives unicast addressed packets over the unicast connection 25 from a port of SFU 20. FIFO 41 receives multicast addressed packets via multicast connections 28 from port 0. In the case of SPC 300, connections 25 and 28 are joined at the input to the OSPC 30. Each packet arriving at FIFO 40 is forwarded to comparator 44 which checks that the packet contains a write address which matches the SPC number contained in register 45. If so, the input is accepted and sent to the corresponding output. Each packet arriving at FIFO 41 is forwarded to comparator 42, which checks that the packet contains a multicast address, and that there is a match between the bit specified in register 43 as designating that port and the corresponding address bit. It will be appreciated that the embodiment described is illustrative only, and that variations and additions are possible within the scope of the invention.

Claims: THE CLAIMS DEFINING THE INVENTION ARE AS FOLLOWS: 1 . A packet switching network comprising switching means having a plurality of inputs and a plurality of outputs, and port control means associated with each output and with each input, wherein packets comprise a header including an address, and a payioad, characterised in that each header further comprises a type indicator, such that each packet having a first type indicator is switched to a one of said outputs defined by the address portion, and is then communicated directly to the port control means associated with the addressed output, and each packet having a second type indicator is switched to a single one of said outputs, and is then communicated via a separate communications connection to one or more of said port control means. 2. A network according to claim 1, wherein said second type indicator defines the packet as a multicast packet directed to a set of port control means defined by the address. 3. A method of multicasting within a packet switching network, said network comprising switching means having a plurality of inputs and outputs, port control means associated with each output, and means for communicating independent of said switching means connecting a defined output of said switching means and a plurality of said port control means, said packets comprising a header including a type indicator and an address, and a payioad, wherein packets having a unicast type indicator are switched by said switching means to an output defined by the respective address and then to the respective port control means, and packets having a multicast type indicator are switched by said switching means to said defined output and communicated via said means for communicating to a set of output port control means defined by the respective address.

Inventors: ANIDO GARY J, FOLLETT DOUGLAS JAMES, ANIDO, GARY, J., FOLLETT, DOUGLAS, JAMES
Applicants: OTC LTD, OTC LIMITED
Application year: 1991
Main classification: H04L12
IPC codes: H04L12, H04Q3