Method of producing semiconductor device including Schottky barrier diode

Abstract: A method of producing a semiconductor device including a Schottky barrier diode (SBD) comprising the steps of: selectively forming an insulating layer (26) having a first contact hole and a second contact hole, on a (100) silicon semiconductor substrate (21); selectively forming a polysilicon layer (33A, 33B, 33C) extending from the first contact hole to the second contact hole, the polysilicon layer (33A) having an viahole (32) within the first contact hole for selectively exposing the silicon semiconductor substrate (21); and selectively depositing a refractory metal (tungsten or molybdenum) layer (41) on the polysilicon layer and an exposed portion of the substrate within the viahole (32) by a selective CVD process, so that the SBD is formed between the exposed portion and the metal layer (41). The refractory metal layer (41) is formed on the silicon of the exposed portion of the substrate (21) and the polysilicon layer (33A, 33B, 33C) and is not formed on the insulating layer (26), and thus it is unnecessary to perform a photolithography process for patterning the refractory metal layer.

Description: The present invention relates to a semiconductor device, and more particularly, to a method of producing a semiconductor device comprising a Schottky barrier diode (SBD). An increase of the number of elements per semiconductor chip and miniaturization of semiconductor device is now required, and thus it is necessary to reduce the areas (dimensions) of an SBD and an electrode of a semiconductor device. In a conventional process of producing a semiconductor device shown in, e.g., Fig. 1, a metal electrode for forming an SBD and extending to a transistor is made of aluminum or alloy thereof (Al-Si, Al-Cu, Al-Si-Cu or the like), indicated as "Al" hereinafter. In this case, the semiconductor device is produced in the following manner. As shown in Fig. 1, a silicon semiconductor substrate 1 comprises a P-type silicon wafer 2, an N + -type buried layer 3, and an N-type epitaxial silicon layer 4. The silicon wafer 2 usually has a <111> orientation, and the silicon substrate 1 is selectively and thermally oxidized to form a SiO 2 insulating layer 5 thereon. Regions of the substrate 1 corresponding to the SBD and doped regions of a bipolar transistor are not oxidized, and a trench isolation region 6 reaching the silicon wafer 1 is formed in a conventional process. The trench isolation region 6 comprises a SiO 2 insulating layer 7 coating a trench wall, a filler 8 of, e.g., a polysilicon, and a cap SiO 2 insulating layer 9. Then, a polysilicon is deposited on the whole surface by a chemical vapor deposition (CVD) method to form a polysilicon layer, and the layer is patterned by a photolithography technique to form polysilicon layers 11A, 11B and 11C which become a portion of an SBD electrode, a portion of an electrode for the doped region, and a portion of an interconnection (a wiring), respectively. Thus, the polysilicon layer 11A has a through hole corresponding to the SBD region. The polysilicon layers 11A and 11C are doped with acceptor (p-type impurities) by an ion-implantation process, and the polysilicon layers 11B and 11C are doped with donor (n-type impurities) by an ion-implantation process. The doped impurities are then diffused into the substrate 1 (i.e., the epitaxial silicon layer 4) by a thermal diffusion process to form a P-type guard ring 12 and an N + -type region (e.g., a collector region) 13, respectively. An insulating layer (e.g., SiO 2 ) is deposited on the whole surface by a CVD process, to form an insulating layer 14, and the layer 14 is patterned by a photolithography technique to form openings for contact regions. Al (or Al alloy) is then deposited on the whole surface by a sputtering process (or a vapor deposition process) to come into contact with an exposed surface of the substrate 4 in the polysilicon layer 11A, the polysilicon layers 11A, 11B and 11C in the openings, and thus a Schottky barrier diode is formed at the interface between the Al and the silicon indicated as "SBD" in Fig. 1. The deposited Al layer is patterned by a photolithography technique to form Al wirings (i.e., a conductor line 15A including an electrode of the SBD and interconnecting the SBD and the doped region, and another conductor line 15B). Thereafter, another insulating material (e.g., SiO 2 ) is deposited on the whole surface to form a passivation insulating layer 16, and the layer 15 is selectively etched to form a contact hole, and then a metal Al (or Al alloy) or a combination of a barrier thin metal (TiN, TiW or the like) and Al (or Al alloy) is deposited on the whole surface and is patterned by a photolithography technique to form a predetermined metal wiring (conductor line) 17, whereby a semiconductor device with the SBD is obtained. Where the SBD is formed by using Al (or Al alloy), the properties of the SBD depend upon the orientation [<100> or <111>] of the silicon single crystalline substrate (wafer). The use of a <100> oriented silicon substrate makes the SBD area larger than that in a <111> oriented silicon substrate, and the SBD level does not match a demanded level of a device property, and thus the <111> oriented silicon substrate is widely used. For a miniaturization of the semiconductor device, there is a need to reduce the area (dimensions) of the SBD, and as it is preferable to use a silicon substrate (wafer) having less crystal defects, preferably the <100> oriented silicon substrate is adopted. Furthermore, the use of the Al wiring (the conductor lines 15A and 15B) requires a photomask alignment step and an etching step in the photolithography technique, with the result that it is necessary to take into account an alignment deviation and an etching shift, which prevent the required miniaturization. In the paper EXTENDED ABSTRACTS. vol. 82-2, October 1982, PRINCETON, NEW JERSEY US pages 270 - 271; N.G. ANANTHA et al.: 'A Schottky Barrier Diode with Very Narrow Self-Aligned Guard Ring' a method of fabricating an SBD is disclosed where a doped polysilicon sidewall is formed on all vertical edges of the contact hole. The structure is annealed to diffuse the dopant and the Schottky metal is deposited. Thus a guard ring is formed around the anode of the SBD. An object of the present invention is to provide an improved method of producing a semiconductor device including an SBD, which method contributes to a miniaturization of the device. Another object of the present invention is to provide a semiconductor device including an SBD which is smaller than a conventional SBD. The above mentioned objects and other objects of the present invention are attained by providing a method of producing a semiconductor device including a Schottky barrier diode (SBD) according to claim 1. After the refractory metal layer deposition step, the method preferably further comprises the steps of forming a second insulating layer having a third contact hole on the whole surface; and forming a conductor layer on the second insulating layer to come into contact with the refractory metal layer. Preferably, the refractory metal layer is made of tungsten or molybdenum, when the refractory metal layer is formed on the silicon of the exposed portion of the substrate and the polysilicon layer and is not formed on the insulating layer at the deposition step, it is unnecessary to perform a photolithography process for patterning the refractory metal layer. Also, preferably, the substrate is a <100> oriented silicon substrate (wafer), as when the SBD is formed by depositing the refractory metal compound (e.g., WF 6 ) is reacted with silicon of the substrate and the refractory metal elements penetrate the silicon, with the result that the refractory metal layer joints with the <111> plane of silicon causes the Schottky-barrier height to be lower than the <100> plane. Therefore, although the <100> oriented silicon substrate is used, the SBD is substantially formed on the <111> plane, so that the area (dimensions) of the SBD depends upon the <111> oriented silicon. The polysilicon layer formation step comprises the steps of: depositing the polysilicon layer over the whole surface, and selectively etching the polysilicon layer in accordance with a predetermined pattern, so that the polysilicon layer in the first contact hole does not coat the center part of the hole corresponding to an SBD area, and thus the portion of the silicon substrate for the SBD is exposed in the first contact hole. After the patterning of the polysilicon layer (prior to the refractory metal layer deposition step), impurities are doped into the polysilicon layer and are thermally diffused therefrom to the substrate, to form a guard ring for the SBD at the first contact hole and a doped region (e.g., a collector region of a bipolar transistor) at the second contact hole. According to the production method of the present invention, it is possible to produce a semiconductor device including a Schottky barrier diode according to claim 7. The present invention will be more apparent from the description of the preferred embodiments set forth below, with reference to the accompanying drawings, in which: Fig. 1 is a schematic sectional view of a conventional semiconductor device including an SBD; Fig. 2A to 2H are schematic sectional views of a semiconductor device including an SBD in various stages of production in accordance with first embodiment of the present invention; Fig. 3A to 3C are schematic sectional view of a semiconductor device including an SBD in various stages of production in accordance with a second embodiment of the present invention; Fig. 4 is a graph showing a relationship between a Schottky-barrier height and a layer-construction of an SBD electrode; and Fig. 5 is a graph showing a relationship between a forward breakdown voltage of the SBD and area of the SBD. Example 1 Referring to Figs. 2A to 2H, a semiconductor device including an SBD is produced in accordance with the first embodiment of the present invention as follows. Note that the production steps shown in Figs. 2A to 2E are similar to those of a conventional semiconductor device. As shown in Fig. 2A, an N-type <100> oriented silicon substrate 21 comprises a P-type <100> oriented silicon wafer 22, an N + -type buried layer 23, and an N + -type silicon layer 24. In this case, the wafter 21 is selectively doped with donor (n-type impurities) to form the buried layer 23, and the N + -type silicon layer 24 is then epitaxially grown on the substrate 21, so that the layer 24 has the same orientation as the wafer 22. A silicon nitride (Si 3 N 4 ) is deposited on the whole surface of the substrate 21 by a CVD process, and is patterned by a photolithography process to form a silicon nitride layers 25A and 25B at predetermined locations. Such a photolithography process comprises the steps of coating a resist layer, exposing the layer through a photomask (or by an electron beam), developing to leave a resist mask, and etching the silicon nitride layer not covered by the resist mask. Next, as shown in Fig. 2B, the silicon substrate 21 is subjected to a thermal oxidation treatment, to oxidize a portion of the silicon epitaxial layer 24 not covered by the silicon nitride layers 25A and 25B, and as a result, an SiO 2 (insulating) layer 26 is formed on the substrate 21. The portions of the silicon epitaxial layer 24 covered with the silicon nitride layers 25A and 25B are not oxidized and correspond to a SBD region and a doped region of a transistor (e.g., a collector region of a bipolar transistor). A trench isolation region 28 reaching the silicon wafer 22 is formed in accordance with a conventional process, and comprises a SiO 2 insulating layer 29 coating a trench wall, a filler 30 of, e.g., a polysilicon, and a cap SiO 2 insulating layer 31. The SiO 2 layer 26 and the silicon substrate 21 are selectively and anisotropically etched to form a trench, and the inside wall of the silicon substrate 21 in the trench is thermally oxidized to form the SiO 2 insulating thin layer 29. The polysilicon is deposited in trench and an upper portion of the filled polysilicon 30 is thermally oxidized to form the cap SiO 2 insulating layer 31, which is combined with the SiO 2 layer 26. The silicon nitride layers 25A and 25B are removed by a suitable etchant to form a first contact hole at a location of the layer 25A and a second contact hole at a location of the layer 25B, in which holes portions of the silicon substrate 21 are exposed. Then, as shown in Fig. 2C, a polysilicon is deposited on the whole surface by a CVD process and is patterned by a photolithography process to form polysilicon layers 33A and 33B having a predetermined pattern and a thickness of, e.g., 300 nm. The polysilicon layer 33A extends from the first contact hole to the second contact hole and comes into contact with the exposed portion of the silicon substrate 21. The polysilicon layer 33A fills the second contact hole completely but partially fills the first contact hole except for a center part thereof. Namely, a viahole 32 for an electrode of a SBD is formed in the polysilicon layer 33A. The polysilicon layer 33B serves as a wiring (interconnection). As shown in Fig. 2D, a resist mask 34 is formed to expose the polysilicon layer 33B and a predetermined portion of the polysilicon layer 33A by coating a resist layer on the whole surface, exposed same through a photomask (not shown), and then developing same. Then, the exposed polysilicon layers are doped with donor (n-type impurities, e.g., P, As) 35 by an ion-implantation process. After the removal of the resist mask 34, as shown in Fig. 2E, another resist mask 36 is formed to expose a predetermined portion of the polysilicon layer 33A by coating a resist layer on the whole surface, exposing same through another photomask (not shown), and developing same. Then, the exposed polysilicon layer 33A is doped with acceptor (p-type impurities, e.g., B) 37 by an ion-implantation process. After a removal of the resist mask 36, the impurities contained in the polysilicon layer 33A are diffused into the epitaxial silicon layer 24 by a heat-treatment, with the result that an N + -type region 38 (a collector region) and a P-type region (i.e., guard ring) 39 for the SBD are formed, as shown in Fig. 2F. The P-type guard ring 39 exists around the periphery of the SBD, to raise the reverse-breakdown voltage thereof, since the guard ring reduces the electric field at sharp corners of the SBD. After a conventional cleaning step is performed, in accordance with the present invention, tungsten (W) is deposited on the polysilicon layers 33A and 33B and the exposed surface of the silicon layer 24 by a selective CVD process, to form a tungsten layer 41 having a thickness of, e.g., 100 nm, as shown in Fig. 2F. In the CVD process, a WF 6 gas, a SiH 4 gas and a H 2 gas are used and the silicon substrate 21 is heated at 300°C with an infrared ray lamp arranged under the substrate 21, so that tungsten is deposited on silicon only by utilizing a reducing reaction. The tungsten layer comes into contact with the exposed silicon surface of the substrate 21 to form the Schottky barrier diode (SBD). Then, as shown in Fig. 2G, an insulating material (e.g., SiO 2 , PSG) is deposited on the whole surface by a CVD process, to form an insulating layer 42. The layer 42 is selectively etched in accordance with a photolithography process to form (open) a contact hole 43 in which a portion of the tungsten layer 41 is exposed. Next, as shown in Fig. 2H, a conductor (metal) material (e.g., Al) is deposited on the whole surface by a vacuum vapor deposition process or a sputtering process to form a conductor layer, and the conductor layer is patterned by a photolithography process to form a conductor line (interconnection) 44. It is possible to form the conductor layer of a combination of a barrier metal layer (TiN, TiW and the like) and an Al layer thereon. The conductor line 44 becomes into contact with the tungsten layer 41 through the contact hole 43. Thus, the semiconductor device including a SBD is obtained. Example 2 Referring to Figs. 3A to 3C, a semiconductor device including an SBD and a polysilicon resistor is produced in accordance with the second embodiment of the present invention as follows. Note that the semiconductor device except the polysilicon resistor is produced in the same manner as Example 1, and a conductor line consisting of the polysilicon layer 33B and the tungsten layer 41 coated thereon in Example 1 is changed to the polysilicon resistor of Example 2. When the polysilicon layers 33A and 33B (Fig. 2C) are formed in Example 1, a resistor as a polysilicon layer 33C for a resistor is formed instead of the layer 33B, as shown in Fig. 3A. Then, an insulating material (e.g., SiO 2 , PSG) is deposited on the whole surface by a CVD process to form an insulating layer 45 having a thickness of, e.g., 300 nm. As shown in Fig. 3B, the insulating layer 45 is selectively etched by a photolithography process to expose a portion of the silicon substrate 21 for an SBD and the polysilicon layer 33A except the end portions thereof and to open contact holes 46 for electrodes of the polysilicon resistor. End portions of the polysilicon layer 33C appear in the contact holes 46. As shown in Fig. 3C, tungsten (W) is deposited on the exposed surface of the silicon substrate 21, the polysilicon layer 33A and the exposed portions of the polysilicon layer 33C by the selective CVD process explained in Example 1 (cf. Fig. 2F), to form a tungsten layer 41 and tungsten filling layers 41C having a thickness of, e.g., 100 nm, and as a result, the SBD is formed between the tungsten layer 41 and the silicon substrate 21. Then, an insulating material is deposited over the whole surface to form the insulating layer 42, in the same manner as that shown in Fig. 2G. The insulating layer 42 is selectively etched to form contact holes for the tungsten layer 41 and a window (hole) covering the resistor, and then a conductor (metal) material (e.g., Al) is deposited on the whole surface to form a conductor layer, and the conductor layer is patterned by a photolithography process to form a conductor line (interconnection) 44 and electrodes (conductor lines) 44C. The conductor layer 44 comes into contact with the tungsten layer 41 through the contact hole 43, and the electrodes 44C come into contact with the tungsten filling layers 41C through the contact holes 46. The tungsten filling layers 41C in the contact holes 46 reduces the contact resistance and improve the step coverage. Thus, the semiconductor device including an SBD is obtained. The above-mentioned Examples 1 and 2 explain the production processes of the semiconductor device including the SBD. Next, the properties of SBDs formed in a silicon single crystalline substrate (wafer) are explained with reference to Figs. 4 and 5. In Figs. 4 and 5, "Al/TiN/CVD-W" corresponding to a method of the present invention means that a tungsten layer is formed on the silicon substrate by the selective CVD process, a TiN (barrier metal) layer is formed on the tungsten layer and an aluminum layer is formed on the TiN layer, with the result that an SBD electrode is formed. "Al/TiN/Al" corresponding to a conventional method means that an aluminum layer, a TiN layer and another aluminum layer are successively formed on the silicon substrate, to form an SBD electrode. "Al/TiN/PVD-W" corresponding to a comparative method means that a tungsten layer is formed on the silicon substrate by a sputtering process, i.e., a physical vapor deposition (CVD) process, instead of the selective CVD process used in the "Al/TiN/CVD-W" case. Schottky-barrier heights (eV) of the SBDs were detected, depending on structural differences of the SBD electrodes and an orientation difference of the silicon substrates, and the obtained data is shown in Fig. 4. As can be seen from Fig. 4, the barrier height of the SBD with the electrode comprising the CVD-W layer does not depend on the substrate orientation. Namely, the barrier height at the "Al/TiN/CVD-W" is not varied, although a (111) silicon substrate and a (100) silicon substrate are used. Figure 5 shows a relationship between a forward breakdown voltage (at 10 µA) of the SBD and an area of the SBD formed by using the (100) silicon substrate. For example, properties of 10 µA and 400 mV of the SBD are attained by the electrode of "Al/TiN/CVD-W" having a 1 µm 2 area, but are attained by the electrode of "Al/TiN/Al" having a 25 µm 2 area. Thus, when the "Al/TiN/CVD-W" electrode is adopted, the SBD properties meeting a required level of device properties can be attained by a smaller electrode area than in a conventional case. Therefore, when a semiconductor device including an SBD is produced in accordance with a method of the present invention, the (100) silicon substrate can be used and the area of the SBD is smaller than that of a conventional SBD with an Al electrode. As mentioned above, according to an embodiment of the present invention, a refractory metal for forming an SBD is formed in a predetermined pattern by a selective CVD process, without using a photolithography process including an etching step, and thus it is not necessary to take into account a requisite gap and tolerance for the photolithography technique. The refractory metal improves a conductivity of a conductor line comprising a polysilicon layer, to further contribute a reduction of the dimensions of the conductor line. Furthermore, the use of the refractory metal layer formed by the selective CVD method enables a reduction of the SBD area and permits the use of the (100) silicon substrate. The (100) silicon substrate has less crystalline defects than the (111) silicon substrate, and thus the properties of a semiconductor device of the (100) silicon substrate are superior to those of the (111) silicon substrate device. Therefore, the present invention contributes to the miniaturization of and an increase of the degree of integration of the semiconductor device, particularly a bipolar transistor type RAM device. In addition to the above-mentioned embodiments for connecting the SBD and the collector of the bipolar transistor, the present invention can be applied on a connection between SBDs in a RAM device.

Claims: A method of producing a semiconductor device including a Schottky barrier diode comprising the steps of: selectively forming an insulating layer (26) on a silicon semiconductor substrate (21), the insulating layer (26) having a first contact hole and a second contact hole for exposing the silicon semiconductor substate (21); depositing a polysilicon layer on the whole surface selectively etching the polysilicon layer to form a polysilicon pattern (33A, 33B, 33C), a first portion (33A) of the polysilicon pattern extending from the first contact hole to the second contact hole; where the second contact hole is completely filled with polysilicon and a viahole (32) is formed within the first contact hole through which the silicon semiconductor substrate (21) is exposed; and selectively depositing a refractory metal layer (41) on the polysilicon pattern (33A, 33B, 33C) and the exposed portion of the substrate (21) within the viahole (32) by a selective CVD process, whereby a Schottky barrier diode is formed between the exposed portion and the refractory metal layer (41). A method according to claim 1 further comprising, after the refractory metal layer deposition step, the step of forming a second insulating layer (42) having a third contact hole on the whole surface; and forming a conductor layer (44) on the second insulating layer (42) to come into contact with the refractory metal layer (41). A method according to claim 1 or 2, wherein the refractory metal layer (41) is made of a metal selected from the group consisting of tungsten and molybdenum. A method according to any preceding claim, wherein the exposed portion of the silicon semiconductor substrate (21) is placed at the centre part of the first contact hole. A method according to any preceding claim, further comprising, prior to the refractory metal layer deposition step, the steps of doping impurities into the first portion of the polysilicon pattern (33A) at the first contact hole; and diffusing the impurities into the silicon semiconductor substrate (21) by an annealing treatment to form a guard ring (38) of the Schottky barrier diode. A method according to any preceding claim, wherein the silicon substrate (21) has a <100> orientation. A semiconductor device, formed according to the method given in any one of claims 1-6 including a Schottky barrier diode comprising: a <100> silicon semiconductor substrate (21); an insulating layer (26) formed on the substrate (21) and having a first contact hole and a second contact hole; a first portion of a polysilicon pattern (33A) extending over the insulating layer from the first contact hole to the second contact hole and covering the second contact hole; a viahole (32) within the first contact hole through which the substrate (21) is exposed; and a refractory metal layer (41) deposited on the first portion of the polysilicon pattern (33A) and the exposed portion of the substrate (21) and forming a Schottky barrier diode between the refractory metal layer (41) and the exposed portion of the substrate within the first contact hole.

Inventors: INOUE KENICHI, INOUE, KENICHI, Inoue, Kenichi c/o Fujitsu Limited
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1991
Main classification: H01L21
IPC codes: H01L21, H01L29