A method for burying low resistance material in a contact hole

Abstract: In a method for burying a contact hole according to the present invention, first, a polycrystalline silicon film (106) is formed on a region including a contact hole (105). Impurities are introduced into the polycrystalline silicon film (106). Next, a metal film is formed on the polycrystalline silicon film (106). Next, a polycrystalline silicon film (108) is formed on the metal film. Impurities are introduced into the polycrystalline silicon film (108). Next, a metal film is formed on the polycrystalline silicon film (108). A polycrystalline silicon film (110) is formed on the metal film, and the contact hole is completely buried. Thereafter, a heat treatment is performed, thereby the impurities are diffused to the above two polycrystalline silicon films and all or a part of the metal film is changed to a metal silicide film (111, 112). Next, an etchback is performed, thereby the polycrystalline silicon film and the metal silicide film are kept in only the contact hole.

Description: The present invention relates to an improvement of a method for burying low resistance material in a contact hole. Conventionally, in a case where a metal wire is connected to a diffusion layer in a semiconductor substrate, the following methods are used. An insulating layer is formed on the entire surface of the semiconductor substrate. A contact hole is formed in the insulating layer. Then, a metal film is formed by a sputtering method. Thereafter, the metal film is patterned, thereby forming a metal wire. However, in a case where the above method is used, the elements are fined. Then, the step coverage of the metal wire in the contact hole worsens if an aspect ratio of the contact hole increases. In recent years, much attention has been paid to a method for burying low resistance material (e.g., polycrystalline silicon) in the contact hole, and such a method has been studied. In a case where polycrystalline silicon is buried in the contact hole, it is required that a large amount of impurities be doped in polycrystalline silicon and the resistance of polycrystalline silicon be decreased. Generally, the above impurities are doped in polycrystalline silicon by an ion-implantation. However, an extremely high accelerating voltage is needed in order to implant an ion into a deep portion in the polycrystalline silicon. Due to this, there is a problem in that cost of an ion implantation device increases. In a case where a plurality of contact holes are formed, and the contact holes are different in the depth, it is difficult to implant the ion into polycrystalline silicon in the all contact holes at the same time. In other words, it is impossible to evenly implant the ion into the polycrystalline silicon in the contact holes. This is because the ion cannot reach to the lower portion of polycrystalline silicon in the deep contact holes if the accelerating voltage is included in the shallow contact holes. For this reason, it is impossible to reduce the resistance value of the polycrystalline silicon in the deep contact holes. For example, Unexamined Japanese Patent Application No. 1-205525 discloses the following points. The disclosure will be explained with reference to Figs. 1A to 1F. First of all, as shown in Fig. 1A, an impurity region, for example, a source region 303 of a MOS transistor is formed in a semiconductor substrate 301. An interlayer insulating film, for example, a silicon oxidation film 302 is formed on the entire surface of the semiconductor substrate 301. In the silicon oxidation film 302, there is formed a contact hole 304 reaching to the source region 303. Next, as shown in Fig. 1B, a polycrystalline silicon film 305 is formed on the entire surface of the silicon oxidation film 302 to be thinner than the half width of the contact hole 304. Then, as shown in Fig. 1C, impurities are doped in the polycrystalline silicon film 305 in the contact hole 304, so that the resistance value of a polycrystalline silicon film 305a in the bottom portion of the contact hole. Next, as shown in Fig. 1D, impurities are applied onto a polycrystalline silicon film 305b in order to reduce the resistance value of the polycrystalline silicon film 305b in the side wall of the contact hole 304. Then, as shown in Fig. 1E, a polycrystalline silicon film 306 is formed on the polycrystalline silicon film 305 by a CVD method, so that the contact hole is completely buried. Next, as shown in Fig. 1F, the polycrystalline silicon films 305 and 306 are etched back, so that the polycrystalline silicon films 305 and 306 is left in only the contact hole 304. Also, impurities, which are applied onto the polycrystalline silicon film 305b of the side wall portion in the contact hole 304, are thermally diffused to reduce the resistance value of the polycrystalline silicon film 306 in the contact hole 304. Thereby, polycrystalline silicon having low resistance is buried in the contact hole. Thereafter, a metal wire 307 is formed on the polycrystalline silicon films 305 and 306, and the source region 303 and the metal wire 307 are connected to each other. According to the above method, the polycrystalline silicon films 305 and 306 are formed in the contact hole 304. Since the polycrystalline silicon films are thin, impurities can be easily doped into the polycrystalline films 305 and 306. However, since impurities are doped into the polycrystalline silicon film 305, a natural oxidation film is formed on the surface of the polycrystalline silicon film 305 before the polycrystalline silicon film 306 is formed. Moreover, in general, there is formed the natural oxidation film between the semiconductor substrate 301 and the polycrystalline silicon film 305. Therefore, in the semiconductor device, which is formed by the above-mentioned method, two high resistors are sandwiched between the source region 303 and the metal wire 307, so that the contact resistance value is increased. From EP-A-0 055 161 a multi-layer metal silicide interconnection for integrated circuits is known. In this known structure, a layer of polycrystalline silicon is deposited across the surface of oxide partially masking a selected region to which an Ohmec electrical connection is desired. A layer of metal is then deposited on the polycrystalline silicon layer which metal may be a refractory metal which will react with a part of the polycrystalline silicon layer forming a metal silicide layer. Following the formation of the metal silicide layer, another polycrystalline silicon layer is deposited on the upper surface of the silicide layer, and the combination of the thus established three layers forms a conductor connected to said selected region to which an Ohmec electrical connection is desired. An object of the present invention is to lower a contact resistance by burying low resistance material in a contact hole. This object is achieved by the method according to Claim 1. Preferred embodiments are listed in the dependent claims. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figs. 1A to 1F are cross sectional views showing conventional methods; Figs. 2A to 2H are cross sectional views showing a method relating to a first embodiment of the present invention; Fig. 3 is a cross sectional view showing a method relating to a modification of the first embodiment; Fig. 4 is a cross sectional view showing a semiconductor device to which the method relating to the first embodiment is applied; Figs. 5A to 5C are cross sectional views showing a method relating to a second embodiment of the present invention; and Figs. 6A to 6C are cross sectional views showing a method relating to a third embodiment of the present invention. The embodiments of the present invention will be explained with reference to drawings. Figs. 2A to 2H are cross sectional views showing a method relating to a first embodiment of the present invention. As shown in Fig. 2A, an N type impurity region 102 (for example, source region of MOS transistor) is formed on a surface region of a P type semiconductor substrate 101. An interlayer insulating film 103 (for example, silicon oxidation film) is formed on the entire surface of the semiconductor substrate 101. An insulating film 104 (silicon oxidation film) is formed on the interlayer insulating film 103. Thereafter, on the insulating films 103 and 104 there is formed a contact hole 105, which reaches to the impurity region 102. As shown in Fig. 2B, a polycrystalline silicon film 106 having a thickness of about 500Å (10Å=1nm) is formed on the entire surface exposed on the substrate by an LPCVD method. Additionally, the deposition of the polycrystalline silicon film 106 is performed a plurality of times. Thereafter, arsenic (As) is implanted into the polycrystalline silicon film 106. As a result, impurities are doped in the polycrystalline silicon film 106, and a natural oxidation film, which is formed between the impurity region 102 and the polycrystalline silicon film 106, is mixed, and disappears. In the polycrystalline silicon film in the contact hole, which reaches to a P type impurity region, BF2 is implanted (not shown). In order to implant the above ions (As, BF2), the following method is useful. More specifically, the incident angle of the ion is set to be inclined against a normal line of the semiconductor substrate 101 at more than several degrees. Then, the ion is implanted as the semiconductor substrate 101 is rotated in its plane, In this case, impurities can be doped in the polycrystalline silicon film 106 in the contact hole 105 at the same time. Additionally, the formation of the polycrystalline silicon film 106 and the implantation of impurities is performed a plurality of times. As shown in Fig. 2C, by use of a sputtering method, a titanium (Ti) film 107 having a thickness of about 200Å is formed on the polycrystalline silicon film 106. On the surface of the polycrystalline silicon film 106, there is formed a natural oxidation film (SiO 2 ) (not shown). In other words, a natural oxidation film is formed between the polycrystalline film 106 and the titanium film 107. As shown in Fig. 2D, by use of LPCVD method, a polycrystalline silicon film 108 having a thickness of about 2000Å is formed on the entire surface exposed on the substrate. Thereafter, phosphorus (P) is implanted to the polycrystalline silicon film 108. At this time, the incident angle of phosphorus is set to be inclined against a normal line of the semiconductor substrate 101 at more than several degrees. Then, phosphorus is implanted as the semiconductor substrate 101 is rotated. In the polycrystalline silicon film in the contact hole, which reaches to the P type impurity region, boron (B) is implanted. This ion-implantation aims to reduce the resistance value of the polycrystalline film (described later in a heating treatment process described later. Next, as shown in Fig. 2E, by use of the sputtering method, a titanium (Ti) film 109 having a thickness of about 2000Å is formed on the polycrystalline silicon film 108. On the surface of the polycrystalline silicon film 108, there is formed a natural oxidation film (SiO 2 ) (not shown). In other words, a natural oxidation film is formed between the polycrystalline film 108 and the titanium film 109. Next, as shown in Fig. 2F, by use of LPCVD method, a polycrystalline film 110 is formed on the entire surface exposed on the substrate, thereby the contact hole 105 is completely buried. As shown in Fig. 2G, annealing is performed at temperature of about 850°C in nitrogen atmosphere. Thereby, impurities, which are introduced by the above two-ion implantation, are diffused to the polycrystalline silicon films 106, 108 and 110. At this time, since the titanium films 107 and 109 silicide-react with the polycrystalline silicon films 106, 108 and 110, titanium silicide films (TiSi 2 ) 111 and 112 are formed. As a result, the natural oxidation film (SiO 2 ), which is formed between the titanium films 107, 109 and the polycrystalline silicon films 106, 108, is broken and disappears. The film thicknesses of the titanium films 107 and 109 and the heat treatment time are controlled in order that the silicide reaction does not advance to the impurity region 102, that is, the junction breakage of the impurity region 102 does not occur. Next, as shown in Fig. 2H, the polycrystalline silicon films 106, 108, 110, and the titanium silicide films 111 and 112 are etched back, so that the polycrystalline silicon films and the titanium silicide films are kept in only the contact hole 105. At the time of etching back, the insulting film 104 prevents the polycrystalline silicon films and the titanium silicide films from being over-etched. In this case, as the insulating film 104, there is used material (for example, oxidation silicon) whose etching selection ratio is different from the material (for example, polycrystalline silicon) buried in the contact hole 105. Thereby, the material having low resistance is buried in the contact hole 105. Thereafter, a general wiring process is performed. That is, a metal wire (for example, wiring of the layers of Al - Si - Cu/TiN/Ti) 113 is formed on the contact hole 105, and the impurity region 102 and the metal wire 113 are connected to each other. In the heat treatment process according to the above-method, the titanium films 107 and 109 silicide-react with the polycrystalline silicon films 106, 108 and 110, so that titanium silicide films 111 and 112 are formed. Due to this, the natural oxidation film, which is formed between the titanium films 107, 109 and the polycrystalline silicon films 106, 108, is broken and disappears. Also, since the resistance values of the titanium silicide films 111 and 112 are low, the contact resistance value can be decreased. In the above-mentioned first embodiment, a titanium film can be formed between the semiconductor substrate 101 and the polycrystalline silicon film 106. However, in this case, the titanium silicide film often enters the impurity region 102 by the silicide reaction between the semiconductor substrate 101 and the titanium film. This causes the induction of the junction leakage. Therefore, it is favorable that the natural oxidation film, which is formed between the semiconductor substrate 101 and the polycrystalline silicon film 106, disappear by the mixing using the ion-implantation as mentioned above. Moreover, according to the first embodiment, the etchback is performed after the impurities are thermally diffused. This is because the impurities are diffused from the polycrystalline silicon films 106 and 108 in the vicinity of the contact hole 105, thereby increasing the concentration of the impurity of the polycrystalline silicon film 110 of the upper portion of the contact hole 105. As a result, the contact resistance value can be decreased as compared with the case in which the impurities are thermally diffused after the etchback is performed. Moreover, as shown in Fig. 3, in the heat treatment process, since the titanium films 107 and 109 cannot be completely silicide-reacted with the polycrystalline silicon films 106, 108, 110, the titanium films 107 and 109 may be partially left. However, the silicide reaction is performed until the natural oxidation film, which is formed between the polycrystalline silicon films 106, 108 and the titanium films 107 and 109, is completely broken. Fig. 4 is a case to which the method of the above-mentioned first embodiment to a MOS transistor is applied. In this drawing, reference numeral 114 is a field oxidation film, and reference numeral 115 is a gate electrode. According to the present invention, the material having low resistance can be buried in contact holes 105A and 105B having a different depth, and the contact resistance value is not increased by the natural oxidation film. Figs. 5A to 5C show a method relating to a second embodiment of the present invention. As shown in Fig. 5A, the formation of the polycrystalline film 106 is performed by the same method as that of the above-first embodiment. Next, as shown in Fig. 5B, the polycrystalline silicon film 108 is formed on the entire surface exposed on the substrate by LPCVC method. Also, phosphorus (P) is implanted to the polycrystalline film 108. Thereafter, by use of the sputtering method, the titanium film 109 is formed on the polycrystalline silicon film 108. Also, by use of LPCVD method, the polycrystalline silicon film 110 is formed on the entire surface exposed on the substrate, thereby the contact hole 105 is completely buried. Next, as shown in Fig. 5C, the heat treatment process is performed, so that the impurities in the polycrystalline silicon films 106 and 108 are diffused to the polycrystalline silicon film 110. At this time, the titanium film 109 is silicide-reacted with the polycrystalline silicon films 106 and 108, thereby the titanium silicide film (TiSi 2 ) 112 is formed. The thickness of the titanium film 109 is decided by the condition in which the titanium silicide film 112 reaches to the boundary surface between the polycrystalline silicon film 106 and the polycrystalline silicon film 108. As a result, the natural oxidation film (SiO 2 ), which is formed between the polycrystalline silicon film 106 and the polycrystalline silicon film 108, and the natural oxidation film, which is formed between the polycrystalline silicon film 108 and the titanium film 109, are broken and disappear. Thereafter, the polycrystalline silicon films 106, 108, 110 and the titanium silicide film 112 are etched back (not shown). Also, the metal wire (for example, wiring of the layers of Al - Si - Cu/TiN/Ti) 113 is formed on the contact hole 105, and the impurity region 102 and the metal wire 113 are connected to each other. According to the method, the same effect as that of the first embodiment can be obtained. In the above second embodiment, the titanium film 109 may be formed between the polycrystalline silicon films 106 and 108. Also, if the impurities are introduced into the polycrystalline silicon film 106, the impurities may also be introduced into the polycrystalline silicon film 108 at the same time. In this case, there is not performed the process for introducing the impurities to only the polycrystalline silicon film 106. In the above-mentioned first and second embodiments, the titanium film is formed on the polycrystalline silicon film in order to form the titanium silicide film. In place of the above methods, a refractory metal ion is implanted and a refractory metal silicide film may be formed in the heat treatment process performed later. More specifically, as shown in Fig. 6A, for example, the titanium ion is implanted in the polycrystalline silicon film 106, and a titanium ion layer 107I is formed in the surface region of the polycrystalline silicon film 106. Thereafter, as shown in Fig. 6B, the polycrystalline silicon film 108 is formed on the entire surface exposed on the substrate. Also, for example, the titanium ion is implanted in the polycrystalline silicon film 108, and a titanium ion layer 109I is formed in the surface region of the polycrystalline silicon film 108. Thereafter, as shown in Fig. 6C, the burial of the contact hole 105 is performed by the same method as that of the abovementioned first embodiment. As a resole, the impurity region 102 and the metal wire 113 are connected to each other. Moreover, in the above-mentioned first and second embodiments, the titanium film is formed on the polycrystalline silicon film. In place of this formation, other refractory metal such as tungsten (W), molybdenum (Mo), cobalt (Co) and the like may be formed thereon. Also, a refractory metal silicide film such as TiSi 2 , WSi 2 , MoSi 2 and the like may be formed thereon. Moreover, a refractory ion may be implanted in place of the point that the refractory metal film is formed. Furthermore, the present invention is not limited to the case in which the contact hole on the impurity region is buried. The present invention can be applied to the case in which the contact hole is buried in order to connect a lower layer wire to an upper layer wire in a multi-layer wiring structure.

Claims: A method of providing a contact to a conductive region (102) of a semiconductor device, the method comprising the steps of: a) a first step of forming an insulating film (103, 104) on said conductive region (102) of said semiconductor device; b) a second step of forming a contact hole (105) in said insulating film (103, 104) exposing said conductive region (102); c) a third step of forming a first polysilicon film (106, 108) on said insulating film (103, 104) and said contact hole (105), introducing impurities into said first polysilicon film (106, 108) by ion implantation, and forming a conductive film (107, 109) comprising a metal on or in said first polysilicon film (106, 108), said third step being performed at least one time without filling completely the contact hole; d) a fourth step of forming a second polysilicon film (110) on an upper surface of said conductive film (107, 109) to completely bury said contact hole (105); e) a fifth step of heating to diffuse said impurities and to form a metal silicide film (111) breaking down respective natural oxidation films between said first polysilicon film (106, 108) and said first conductive film (107, 109) and between said conductive film (107, 109) and said second polysilicon film (110); and f) a sixth step of etching back said first polysilicon film (106, 108), said second polysilicon film (110), and said metal silicide (111, 112) film to provide said contact within said contact hole (105). The method according to claim 1, characterized in that, in said fifth step, said metal silicide film (111, 112) is formed between said first and second polysilicon films (106, 108, 110) by reaction of said conductive film (107, 109) with said first and second polysilicon film (106, 108, 110). The method according to claim 1, characterized in that, in said fifth step, said metal silicide film (111, 112) is formed between said first polysilicon film (106, 108) and said conductive film (107, 109) and between said conductive film (107, 109) and said second polysilicon film (110), respectively, by reaction of said conductive film (107, 109) with said first polysilicon film (106, 108) and said second polysilicon film (110). The method according to claim 1, wherein said conductive film (107, 109) is formed by a sputtering method. The method according to claim 1, wherein said conductive film (107, 109) is a refractory metal film. The method according to claim 1, wherein said conductive film (107, 109) is a metal silicide film. The method according to claim 1, wherein said conductive region is (102) a semiconductor region in a semiconductor material (101). The method according to claim 1, wherein said conductive region (102) is a gate electrode. The method according to one of the preceding claims, characterized in that the two contacts in two contact holes (105A, 105B) are simultaneously provided, and depths of said two contact holes (105A, 105B) are different from each other.

Inventors: OHSHIMA YOICHI, OHSHIMA, YOICHI, OHSHIMA, YOICHI, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: H01L21
IPC codes: H01L21