Method of field effect transistor fabrication for integrated circuits

Abstract: A method of forming a transistor is disclosed. Conventional fabrication techniques direct an ion implantation beam toward a substrate (11) upon which a gate stack (17) has already been formed. If the gate stack is too low relative to the incident beam energy, the dopant species may channel through the gate stack, adversely affecting transistor performance. The present invention prevents channeling through this gate by covering the gate with a protective layer (35) before ion implantation. The protective layer (35) is an oxide layer which is formed on both the gate stack (17) and the substrate (11) but is thicker on the gate stack than on the substrate.

Description: Technical Field This invention relates to a method of semiconductor integrated circuit fabrication. Background of the Invention Semiconductor integrated circuits are often fabricated by creating raised topographic features upon a substrate. Then a dopant species is introduced into the substrate with the raised topographic feature serving to mask a portion of the substrate. For example, in the fabrication of semiconductor integrated circuits using field effect transistors (FETs), a gate stack (typically including a gate oxide with an overlying body of polysilicon) is formed upon a silicon substrate. Then a dopant species is introduced into the silicon substrate by diffusion or ion implantation to create the source and drain regions on both sides of the gate stack. As the dopant species is introduced, the gate stack serves as a self-aligned mask shielding the channel under the gate from the dopant species. Of course, during the above-described dopant introduction, the gate stack is subjected to the same environment as that to which the to-be-formed source and drain regions are subjected. For example, if ion implantation techniques are employed to create the source and drain, the gate stack is exposed to ion implantation of the same dopant species as the to-be-formed source and drain regions. In the past, exposure of the gate stack to ion implantation species has not generally created a problem because the implanted species have been completely absorbed by the gate polysilicon. However, as integrated circuit geometries continue to shrink, the thickness of gate stacks also shrink. If the thickness of the gate is too low relative to the implant dose energy, the implanted species may penetrate through the gate. Penetration of the implanted species through the gate is often termed "channeling." If the energy of the implanted species is great enough and the polysilicon grains are oriented with the direction of the implant species, then the range of implanted species becomes greater than the thickness of the gate stack, and the implanted species may arrive at the gate oxide-silicon interface with enough energy to penetrate into or perhaps through the gate oxide. Thus, channeling depends upon the size and orientations of the polysilicon as well as the energy of the implant species. A single large grain, if oriented parallel to the implant direction can permit channeling. When channeling occurs, the silicon surface beneath the gate may be inverted, leading to transistor leakage and/or shifts in the threshold voltage. In addition, channeling may cause flatband voltage shifts in polysilicon capacitors. Heretofore the channeling problem has not posed a series obstacle to integrated circuit designers because gate stacks in previous generation integrated circuits have been thick enough to prevent channeling. EP-A-0244 607 discloses the manufacture of n-channel and p-channel transistors in a CMOS process which involves employing gate spacer oxide layers for reducing the under-diffusion of the implanted source-drain regions under the gate areas. The spacer oxide widths for the n-channel and the p-channel transistor are set differently so that both transistor types can be optimized independently of one another and without an additional expenditure for more masking steps. The method is employed for the manufacture of large scale integrated circuits for fast switching speeds. EP-A-0193 117 teaches to prevent channeling by converting polycrystalline silicon into amorphous silicon. More specifically, it discloses a method of manufacturing a semiconductor device which has the steps of forming an insulating film on a semiconductor substrate, forming a polycrystalline silicon layer on the insulating film, converting either all of the polycrystalline silicon layer or a portion of predetermined thickness of the polycrystalline silicon layer into an amorphous silicon layer, patterning the polycrystalline silicon layer, either all of which or a portion of predetermined thickness of which has been converted into an amorphous silicon layer, and ion-implanting an impurity in the semiconductor substrate using the patterned layer as a mask. EP-A-0315 229 discloses a two-step procedure for creating gate sidewall spacers in fabricating a field-effect transistor using a protective material such as silicon nitride to prevent gate-electrode oxidation. In the first step, a layer of insulating material is conformally deposited and then substantially removed except for small spacer portions adjoining the sidewalls of a doped non-monocrystalline semiconductor layer destined to become the gate electrode. The second step consists of performing an oxidizing heat treatment to increase the thickness of the spacer portions. No significant gate dielectric encroachment occurs. Also, the spacers achieve a profile that substantially avoids electrical shorts. Summary of the Invention The invention is as set out in the claim. Detailed Description The following example provides an illustration of an embodiment of the present invention. This example illustrates several applications of the inventive technique to a portion of an LDD CMOS twin-tub process having an n-channel coded gate length of approximately 0.9µm. First, moats are defined for both a p-tub and an n-tub. A thermally grown gate oxide layer of approximately 150Å (1Å = 10 -10 m) is grown on both tubs. The oxide layer is covered with a polysilicon layer having a thickness of 3800Å. The polysilicon is phosphorous doped by furnace doping to a resistivity of 75 ohms per square at 900°C (to enhance gate conductivity). Any oxide created above the polysilicon by furnace doping is stripped to expose the polysilicon. Patterned photoresist is formed above the polysilicon to define gates. Then gates are etched by reactive sputter etching. A sidewall etch is next performed to clean the gate sidewalls. Then a plasma photoresist strip is performed. A 100:1 HF gate sidewall etch is performed. Next a 5:1 HF clean is performed to remove any residual oxide on the moat surface. Then the first differential oxidation is performed. The wafer is exposed to dry oxygen at 800°C for 20 minutes. Approximately 55Å of oxide is grown upon the silicon and approximately 120Å is grown upon the polysilicon. Then the p-tub lightly doped drain (LDD) implant is performed. A blanket phosphorous implant at 50 KEV, 4E13 is performed to form the p-tub LDD. (In order to save a mask, this phosphorous also goes into the n-tub sources and drains. The n-tub devices will be counter doped later.) Then a thermal drive-in is performed at 900°C. The drive-in step incidentally grows some additional silicon dioxide upon bare silicon and additional silicon dioxide on the polysilicon gate. The p-tub is covered with photoresist. Then a BF 2 implant is performed at 50 KEV, 8E14 to counter dope the already implanted phosphorous, thus forming the p-channel LDD in the n-tub. Then the photoresist is removed from the p-tub, a clean is performed, and TEOS spacers are formed adjacent to both the n and p tub gates. The initial differential oxide is removed as a consequence of the etch which forms the TEOS spacer. A new differential oxide layer is grown at 850°C for 45 minutes in dry oxygen, producing approximately 245Å above the gates and approximately 125Å above the source/drain regions adjacent the spacers. The n tub is then covered with photoresist. Then arsenic is implanted at 100 KEV, 3E15. Photoresist is removed from the n tub; the p tub is then covered with photoresist. Then a BF 2 source/drain implant is performed over the n tub at 50 KEV, 5E15 to create an n-tub source/drain. The photoresist is then removed. The process thereby produces an LDD structure in both the p tub and the n tub. The second differential oxidation prevents arsenic from channeling in the n-gates and reduces boron counter doping in the p-channel gates.

Claims: A method of semiconductor fabrication comprising: forming an n-tub and a p-tub in a silicon substrate; forming at least one gate stack including gate oxide and doped polysilicon in each tub; forming a first oxide layer by differential oxidation upon each said gate stack and upon said substrate within each tub, said first oxide layer having thickness over said gate stacks which is greater than its thickness over said substrate; performing a blanket n-type implant for p-tub lightly doped drain into both exposed tubs; covering said p-tub with first photoresist; performing a blanket p-type implant for n-tub lightly doped drain to counterdope the n-type implant in the exposed n-tub; removing said first photoresist; forming spacers adjacent each said gate stack in said p-tub and said n-tub; forming a second oxide layer by differential oxidation upon each gate stack and upon said substrate within each tub, said second oxide layer having a thickness over said gate stacks which is greater than its thickness over said substrate; covering said n-tub with second photoresist; performing a blanket n-type implant; removing said second photoresist; covering said p-tub with third photoresist; performing a blanket p-type source/drain implant into the n-tub; removing said third photoresist.

Inventors: CHITTIPEDDI SAILESH, COCHRAN WILLIAM THOMAS, KELLY MICHAEL JAMES, CHITTIPEDDI, SAILESH, COCHRAN, WILLIAM THOMAS, KELLY, MICHAEL JAMES
Applicants: AT & T CORP, AT&T CORP.
Application year: 1991
Main classification: H01L21
IPC codes: H01L29, H01L21