Diversity circuit and frame phase (or sampling timing) estimation circuit using the diversity circuit

Abstract: A diversity circuit is disclosed which includes CIR estimation circuits (31,32), error computers (33,34) for computing the ratios of the estimated CIR power to the error power between the estimated and actual received signal for respective received signals, (12,13) a comparator (10) for comparing respective ratios, and a selector (11) for outputting the received signal (15) and the CIR (16) corresponding to the maximum power ratio. A frame phase (or sampling timing) estimation circuit using the diversity circuit further includes a delay circuit (21) for providing a received signal with different delays, whereby the selector (11) outputs the delayed received signal (15) and the CIR (16) corresponding to the maximum power ratio.

Description: The present invention relates to a diversity circuit and a frame phase (or sampling timing) estimation circuit which uses the diversity circuit, in digital radio communication. Fig. 1 is a block diagram illustrating a diversity circuit according to a prior art such as the one disclosed in the literature titled "A New Post-detection Selection Diversity with MLSE ( M aximum L ikelihood S equence E stimation) Equalization" (Autumnal National Session of the Institute of Electronics, Information and Communication Engineers, 1989, B-502, pp. 2 - 172). In Fig. 1, numeral 10 designates a comparison circuit adapted to compare a power ratio, numeral 11 a selection circuit adapted to output the optimum received signal and an estimated value of the channel characteristics such as an estimated channel impulse response (CIR) respectively to output terminal 15 for selected received signal and output terminal 16 for the selected estimated CIR value, numerals 31, 32 respectively a first CIR estimation circuit and a second CIR estimation circuit adapted to estimate CIR on the basis of the received signals input to the input terminals 12, 13 and a transmission pattern which is known, and numerals 33, 34 respectively a first power ratio computing circuit and a second power ratio computing circuit adapted to obtain the power ratio of the estimated CIR. Operation of the diversity circuit will next be explained by referring to a flow chart shown in Fig. 2. The signals which have been received by antennas (not shown) installed at different locations spaced from each other are detected by respective detection circuits (not shown) and then input to the input terminals 12, 13 as the received signals. The first CIR estimation circuit 31 and the second CIR estimation circuit 32 receive the respective received signals and compute estimated CIR values for the respective input systems and output the computed values (Step ST21). Then the first power ratio computing circuit 33 and the second power ratio computing circuit 34 are adapted to receive the respective estimated CIR values and compute the ratio of the power component to be used in the maximum likelihood sequence estimation (MLSE) section at the later stage (not shown) (i.e., the power within the processing range) relative to the power out of the range of MLSE equalization (i.e., the power out of the processing range) (Step ST22). The comparison circuit 10 is adapted to receive the respective power ratios and output a selected signal designating the received signal which corresponds to the largest power ratio or the received signal which is supposed to have the largest equivalent S/N ratio. The selection circuit 11 is then adapted to output the received signal and the estimated CIR value corresponding to the selection signal. Fig. 3 is an explanatory diagram showing an example of the relationship between the estimated CIR and the actual CIR. In Fig. 3, the solid line designates the estimated CIR while the dotted line designates the actual CIR. In the case as illustrated by symbol (A) of Fig. 3, the power ratios of the CIR power within the processing range relative to the CIR power out of the processing range are computed and the power ratio designating that the power is most concentrated in the processing range is selected. Here consideration is made in respect of the case that the estimated CIR values for the received signals input to the two input terminals 12, 13 have exactly the same values but only the noise power respectively corresponding to these received signals are different from one another. In this case, the received signal corresponding to the smaller noise power should be selected. However, according to the comparison method of power ratios in the diversity circuit as above explained, the probability of such a selection being made is 0.5. Another consideration is also made in respect of the case in which the estimated CIR values for the received signals are exactly the same but the relationship between the estimated CIR values and the actual CIR values are respectively as illustrated by symbols (A) and (B) of Fig. 3. In this case, the received signal corresponding to the smaller error in CIR estimation shown by symbol (A) of Fig. 3 should be selected, but the probalility of such a selection being made 0,5. Since the diversity circuit according to a prior art is constituted as above described and no consideration has been made with regard to the noise power and CIR estimation error upon selection of the received signal, there has been such a problem as no proper selection could be made when the noise power and CIR estimation error were considerable. The present invention is directed to eliminate the problem as mentioned above and an object of the present invention is to provide a diversity circuit capable of selecting a proper received signal even when the noise power and CIR estimation errors are considerable and a frame phase (or sampling timing) estimation circuit using the diversity circuit. This object is achieved by the combination of the features of claim 1. The error computing circuit according to the present invention computes the estimated CIR power from the estimated CIR value, for example by calculating the squared value of the estimated CIR value, estimates a received signal based on the estimated CIR value and the known transmission pattern, computes the error power between the power of the actual received signal and the power of the estimated received signal, and computes the power ratio of the estimated CIR power to the error power to output this power ratio which has taken the noise power and CIR estimation error into consideration for each received signal. A frame phase (or sampling timing) estimation circuit using the diversity circuit according to the present invention comprises, at the front stage of the diversity circuit, a delay circuit for providing a received signal with a plurality of different delays to output a plurality of different delayed received signals to transmission channel characteristic estimation circuits of said diversity circuit, whereby the respective delayed received signals are treated as respective received signals in said diversity circuit. These and other objects and advantages will become clear by reading the following description of the invention with reference to the accompanied drawings. Fig. 1 is a block diagram showing a diversity circuit according to a prior art; Fig. 2 is a flow chart illustrating an operation of a CIR estimation circuit and a power ratio computing circuit according to a prior art; Fig. 3 is a diagram illustrating the relationships between the estimated CIR values and the actual CIR values; Fig. 4 is a block diagram showing a diversity circuit according to an embodiment of the present invention; Fig. 5 is a block diagram showing a constitution of one of the arithmetic circuits shown in Fig. 4; Fig. 6 is a flow chart illustrating an operation of the arithmetic circuit shown in Fig. 5; Fig. 7 is a diagram showing the relationships between the estimated CIR values and the actual CIR values; and Fig. 8 is a block diagram showing a frame phase (or sampling timing) estimation circuit using the diversity circuit shown in Fig. 4, according to an embodiment of the present invention. An embodiment of the present invention will now be explained by referring to the drawings. In Fig. 4, numerals 7, 8, 9 designate respectively a first arithmetic circuit, a second arithmetic circuit and a third arithmetic circuit which are adapted to output the estimated CIR value, and the power ratio of the estimated CIR power relative to the error power. The rest of the elements in Fig. 4 are the same as those designated by the same numerals as those in Fig. 1. Fig. 5 is a block diagram illustrating the constitution of the first arithmetic circuit 7. In Fig. 5, numeral 1 designates a transmission channel characteristic estimation circuit adapted to output such estimated transmission channel characteristic as estimated CIR values to an output terminal 5 and an error computing circuit 2 which outputs the power ratio to an output terminal 4. It is to be noted that the constitution of the second arithmetic circuit 8 and the third arithmetic circuit 9 is identical to that of the arithmetic circuit shown in Fig. 5. Fig. 6 is a flow chart illustrating an operation of the respective arithmetic circuits 7, 8, 9. Operation of the present apparatus will next be explained by referring to the flow chart in Fig. 6. The CIR estimation circuit 1 of the first arithmetic circuit 7 estimates the CIR on the basis of the received signal input to the input terminal 12 in the conventional manner and outputs the estimated CIR value (Step ST11). Next, the error computing circuit 2 calculates the squared value of the estimated CIR value as the estimated CIR power (Step ST12). Received signals are estimated on the basis of the actual received signals and the known transmission pattern such as preambles of frames (Step ST13). The squared value of the error between the actual received signal and the estimated received signal is computed as error power (Step ST14). The power ratio of the estimated CIR power relative to the error power is computed (Step ST15). This power ratio is then output to the comparison circuit 10 via the output terminal 4. The second arithmetic circuit 8 and the third arithmetic circuit 9 also receive the received signals at the respective input terminals 13, 14 and output the power ratio and estimated CIR value respectively by a similar operation to that of the first arithmetic circuit 7. The comparison circuit 10 is adapted to compare the respective power ratios and output to the selection circuit 11 the selection signal specifying the received signal corresponding to the largest power ratio. The selection circuit 11, in turn, selects the received signal specified by said selection signal, and the estimated CIR value acquired from this received signal and outputs them to the output terminals 15, 16. Fig. 7 illustrates an example of the relationship between the estimated CIR and the actual CIR. In the case as illustrated by symbol (A) of Fig. 7 according to operation of the above-described diversity circuit, CIR within the processing range alone becomes the estimated CIR and CIR out of the processing range contributes to the error power. Consideration is here made in respect of the case in which estimated CIR values for the received signals input to the two input terminals 12, 13 are exactly equal but the noise powers related to these received signals are different each other. In this case, the received signal corresponding to the smaller error power should be selected, thus the received signal having a small noise power is selected. Next, consideration is made in respect of the case wherein estimated CIR values are exactly equal, but the relationships between the estimated CIR values and the actual CIR values are respectively as shown by symbols (A) and (B) of Fig. 7. In this case, since the error power between the estimated CIR and the actual CIR in the case as designated by symbol (A) of Fig. 7 is smaller than that in the case as designated by symbol (B) of Fig. 7, the received signal corresponding to the case as designated by symbol (A) of Fig. 7 is also selected. Fig. 8 is a block diagram showing a frame phase (sampling timing) estimation circuit according to an embodiment of the present invention. In Fig. 8, numeral 20 designates an input terminal for the received signals, numeral 21 designates a delay circuit such as a shift register adapted to provide received signals with sequential delays and the other elements are the same as those shown in Fig. 4. In this instance, the delayed received signals output from the respective taps of the delay circuit 21 are input to the input terminals 12, 13, 14. It is to be noted here that the delayed received signal input to the input terminal 13 is delayed by ΔT from the received signal input to the input terminal 14 and the delayed received signal input to the input terminal 12 is delayed by 2ΔT from the received signal input to the input terminal 14. As the delay ΔT, the inverse of the symbol rate of the signal to be transmitted is established. The respective arithmetic circuits 7, 8, 9, and the selection circuit 11, which have respectively input the respective delayed received signals, and the comparison circuit 10 are caused to operate in a manner similar to that of the apparatus shown in Fig. 4 and output the received signal having an optimum delay and the estimated CIR value to the output terminals 15, 16. Thus, if the circuit provided at the later stage (not shown) could demodulate the selected delayed received signal, then receiving can be carried out from the top of the frame. Although the respective embodiments as described above had three input terminals 12, 13, 14, the number of said input terminals can be increased. If the input terminals are increased, then the effect of diversity can be enhanced and the estimation range of the top phase of a frame can be further extended. Since the present invention has been so constituted that the diversity circuit and the frame phase (sampling timing) estimation circuit using the diversity circuit are adapted to estimate the input signals from estimated CIR values, and select the optimum input signal by using the power ratio of the estimated CIR power relative to the error power between the estimated input signals and the actual input signals, even if the noise power and CIR estimation error are considerable, proper input signal may be selected. The present invention has been described in detail with reference to certain preferred embodiments thereof, but it will be understood that variations and modifications can be effected within the scope of the invention.

Claims: A diversity circuit for receiving a plurality of received signals which have been propagated through a plurality of different signal paths and for selecting an optimum received signal, said diversity circuit comprising transmission channel characteristic estimation means (1) for computing the estimated value of the transmission channel characteristics representing the estimated characteristics of the transmission channel of the signal path on the basis of the received signal, for each of said plurality of received signals; means (2) for computing the power of the estimated transmission channel characteristics on the basis of said estimated value for each received signals; means (2) for estimating a received signal on the basis of said estimated value and the transmission pattern which is known in advance, for each received signal; means (2) for computing power ratios and means (10,11) for comparing respective power ratios for selecting and outputting the received signals corresponding to the maximum power ratio, characterized by means (2) for computing the error power between the power of the estimated received signal and the power of said corresponding received signal for each received signal and said means (2) for computing power ratios computing the power ratio of said power of the estimated transmission channel characteristics to said corresponding error power for each received signal. A diversity circuit according to claim 1, characterized by having a plurality of input terminals (12-14) for receiving respective received signals, transmission channel characteristic estimation circuits (1) provided to correspond to said plurality of input terminals (12-14), error computing circuits (2) provided to correspond to said respective transmission channel characteristic estimation circuits and forming said means for computing the power of the estimated transmission channel characteristics, said means for estimating a received signal, said means for computing the error power and said means for computing power ratios, said means for comparing respective power ratios and for selecting and outputting the received signal comprising, a comparison circuit for comparing the respective power ratios respectively output from said error computing circuits, to output the selection signal designating the signal path corresponding to the maximum power ratio, and a selection circuit (11) for outputting the received signal and the estimated value of the transmission channel, which correspond to said signal path designated by said selection signal, out of said respective received signals and said respective estimated values of the transmission channel characteristics. A diversity circuit as defined in claim 1, characterized in that said means (10,11) for selecting and outputting the received signal corresponding to the maximum power ratio further selects and outputs the estimated value of the transmission channel corresponding to the maximum power ratio. A diversity circuit as defined in one of claims 1 to 3, characterized in that said transmission channel characteristics comprise a channel impulse response. A diversity circuit as defined in claim 1, characterized in that said transmission channel characteristics estimation means (1), said means (2) for computing the power of the estimated transmission channel characteristics, said means (2) for estimating a received signal, said means (2) for computing the error power, and said means (2) for computing the power ratio are provided to respective received signals. A frame phase (or sampling timing) estimation circuit using a diversity circuit according to one of claims 1 to 5, comprising a delay circuit (21) for generating said plurality of received signals having different delays.

Inventors: KUBO HIROSHI, KUBO, HIROSHI, KUBO, HIROSHI, C/O TSUSHIN SYSTEM KENKYUSHO
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1991
Main classification: H04L1
IPC codes: H04L1, H04L25