Method for fabricating a semiconductor device having a capacitor with polycrystalline silicon having micro roughness on the surface

Abstract: A method for fabricating a polycrystalline silicon having a roughed surface, which is useful for a capacitor electrode is disclosed. The method is featured by depositing a polycrystalline silicon layer in such a manner that grains of silicon are caused at the surface of the polycrystalline silicon layer. The polycrystalline silicon layer thus obtained has a large effective surface area and is suitable for a capacitor electrode because of its increased effective surface area.

Description: The present invention relates to a method of fabricating semiconductor devices, and more particularly to fabrication methods of forming polycrystalline silicon layers suitable for use as electrodes for capacitors. In recent years, the memory cell size has been reduced accompanying the increase in the degree of integration of DRAMs, and along with it the area of storage capacitors used for the cells tends to be decreased. For this reason, stacked capacitors or trench stacked capacitors that have a large effective area for the capacitor part, an excellent α-ray resistance characteristic and a small interference between the capacitor parts have been employed in order to secure sufficiently high capacitances. However, for 64 Mbit DRAMs now under development each cell area is anticipated to become smaller than 1.5 µm 2 , so that there is required a capacitor insulating film with a thickness of less than 50 Å 10Å = 1 nm when converted to equivalent thickness of silicon dioxide (SiO 2 ) film, even with the use of the aforementioned structures. It is extremely difficult to form such a thin capacitor insulating film uniformly and without defect all over the chip. In order to resolve the above-mentioned problem, there is conceived an idea of increasing the effective areas of the opposing electrodes of a capacitor by providing a micro roughness on the surface thereof to obtain a larger electrostatic capacity for a capacitor of the same size. A method for increasing the opposed electrode areas, that is, for enlarging the effective surface areas, of polycrystalline silicon electrodes is disclosed in "Capacitance-Enhanced Stacked-Capacitor with Engraved Storage Electrode for Deep Submicron DRAMs, Solid State Devices and Materials, 1989, pp. 137-140. According to this method, the surface of a polycrystalline silicon is coated with spin-on-glass (SOG) containing photoresist particles. Then the effective surface area of the polycrystalline silicon film is increased by providing a micro roughness the surface thereof by etching the SOG film, whereby etching the polycrystalline silicon surface using the resist particles as the mask. However, this method has the following problems. Namely, there are required strict control of the size of the resist particles and distribution of the resist particles on the wafer with uniform density at the time of coating, in addition to the complexity of the process involved. Further relevant prior art is as follows. From US-A-4905072 is known a semiconductor device which comprises a semiconductor layer of a polycrystalline silicon thin film containing not more than 3 atomic % hydrogen atoms and having a surface unevenness of not more than 800 Å at its maximum. It may also have an etching rate of 20 Å/sec. when etched with a mixture of HF, HNO 3 and glacial acetic acid (1:3:6). From GB-A-2130009 is known a semiconductor device containing one or more layers of polycrystalline silicon having a root mean square roughness of not more than 20 angstroms. The device is made by forming the silicon layers in the amorphous state by low pressure chemical vapor deposition in the temperature range 560-580°C and annealing to convert them to the polycrystalline state. The layers so formed are superior in smoothness, lack of strain and precision of photolithographic definition to layers of silicon formed in the polycrystalline state. An interconnect may be produced. In addition to disclosing the transition of amorphous silicon to polysilicon this document also explains the silicon growth at different temperatures. It is an aim of the present invention to provide a simple and mass-producible fabrication method of a semiconductor device having at least one polycrystalline silicon layer having micro roughness on its surface. It is another aim of the present invention to provide a fabrication method which enables to control the size and/or the density of the micro roughness on the surfaces of the polycrystalline silicon layers. According to the present invention, there is provided a method of fabricating a semiconductor device having a capacitor, comprising the steps of: forming on a substrate a silicon layer serving as a first electrode of said capacitor by depositing silicon on said substrate at a transition temperature from an amorphous phase to a polycrystalline phase of silicon, said silicon layer thereby having a micro-roughness surface caused by grains of silicon; forming a dielectric film of said capacitor on said micro-roughness surface of said silicon layer with such a thickness that the surface of said dielectric film has a micro-roughness imparted by said micro-roughness surface of said silicon layer; and forming on said micro-roughness surface of said dielectric film a conductive layer serving as a second electrode of said capacitor. In contrast to the method in the above-mentioned reference in which the micro roughness is formed on the surface of a polycrystalline silicon layer by means of selective etching that uses the resist particles as the mask, micro roughness on the surface of a polycrystalline silicon layer is formed based on the grain growth of silicon in this invention. The present inventors discovered that a polycrystalline silicon layer having a surface with micro roughness can be formed based on the grain growth of silicon in accordance with the method that follows. The method is that when silicon is deposited on a substrate in accordance with an LPCVD method or the like, the deposition of silicon is carried out at the temperature (referred to as transition temperature) at which the crystal state of the deposited film makes transition from the amorphous phase to the polycrystalline phase. In accordance with such a method it is possible to form a polycrystalline silicon film having a surface with micro roughness by an exclusive use of a CVD method or the combination of a CVD method and annealing that are well-known techniques in the fabrication of semiconductors. The above and other aims, advantages and features of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which: Fig. 1 shows scanning electron microphotographs and the corresponding reflection high energy electron diffraction (RHEED) photographs at the surface of the deposited film for different deposition temperatures; Fig. 2 is a graph showing the dependence of the capacitance of a fabricated capacitor, the surface area of the silicon film and the deposition temperature of silicon; Fig. 3 is an electron microphotograph showing the surface condition of a silicon film with micro roughness taken after phosphorus diffusion; Fig. 4 shows a distribution diagram of the relative magnification at the surface area of silicon film deposited at the temperature of 590°C within a 4-inch wafer; Fig. 5 is a graph showing the dependence of the leakage current on the applied voltage for the stacked capacitors formed at different silicon film deposition temperatures (590 and 640°C); Fig. 6 is a graph showing the dependence of the leakage current at the applied voltage for stacked capacitors with different silicon film deposition temperatures; Fig. 7 is a frequency distribution diagram for the breakdown voltage of stacked capacitors for different silicon electrode deposition temperatures; Fig. 8 is a scanning electron microphotograph of the film surface according to an embodiment 2 after annealing of a silicon film formed at the transition temperature; Fig. 9 is a scanning electron microphotograph showing the surface condition according to an embodiment 3 of a film formed by depositing a compact polycrystalline film at a temperature above the transition temperature, on a silicon film formed at the transition temperature; Fig. 10 shows sectional views for different fabrication processes of stacked capacitors having a micro roughness also on the side faces according to an embodiment 4; and Fig. 11 shows scanning electron microphotographs of the cross-sections of a stacked capacitor formed in accordance with the fabrication method illustrated in Fig. 10. The fact that a polycrystalline silicon film having a surface with micro roughness can be formed based on the grain growth of silicon when silicon is deposited at the transition temperature has already been mentioned in the above. This phenomenon can be described as in the following. Namely, during the deposition of silicon at the transition temperature, silicon deposited is principally of amorphous type. If the temperature inside the furnace tube is kept at the transition temperature even after the completion of the deposition, silicon atoms that have been migrating in the surface of the deposited amorphous silicon film start to form crystalline nuclei. Silicon atoms that are migrating in the vicinity of the crystal nuclei are captured by the nuclei and contribute to the growth of the nuclei and to the increase of the size of the grains. As a result, there is formed a polycrystalline silicon film having surface with a micro roughness. On the other hand, when silicon is deposited at a temperature below the transition temperature, the deposited film remains as amorphous as is, with its surface being very smooth. When a film is deposited at a temperature above the transition temperature, it means the formation of an ordinary polycrystalline silicon film. The surface of the deposited polycrystalline silicon has too many nuclei, so that they can not grow each other, as a result, the surface remains smooth all the same. As in the above, one should recognize that it is important to deposit silicon at the transition temperature. However, it is difficult to determine the transition temperature. This is because the transition temperature depends to some extent on the formation conditions. Nonetheless, the present inventors discovered that surface with a micro roughness can be obtained if silicon is deposited at a temperature in the range of the transition temperature of 550 ± 10°C. It should be noted, however, that the temperature of 550°C is the temperature on the outside of the furnace tube and the actual temperature of the wafer at this time was found to be 590°C as examined by an infrared sensor. Accordingly, if silicon is deposited at a wafer temperature in the range of 590 ± 10°C (the temperature outside the furnace tube being in the range of 550 ± 10°C), there can be formed a polycrystalline silicon film having surface with a micro roughness. In the description that follows the temperature indicated will invariably refer to the wafer temperature, and the temperature outside the furnace tube will be indicated in parentheses following the wafer temperature. Referring to Fig. 1, the surface condition and the crystallinity of the silicon films formed at various deposition temperatures are shown. The deposition was carried out by a low pressure chemical vapor deposition (LPCVD) method on a silicon substrate whose surface is covered with an SiO 2 film. The gas used is the mixture of SiH 4 and He ( at 20% of SiH 4 and 80% of He), and the pressure is 1 Torr. Figs. 1AA, 1BA, 1CA, 1DA and 1EA are the scanning electron microscopy (SEM) photographs, with magnification of 100,000, of the surface of 2500 Å-thick silicon films deposited at the temperatures of 550°C (510°C), 580°C (540°C), 590°C (550°C), 600°C (560°C) and 650°C (610°C), respectively. The space between the adjacent dots among a group of dots shown at the botton of the photographs is 30 nm, and hence the distance from one end dot to the other end dot of the arrayed 11 dots is 300 nm. The acceleration voltage of the electron micrograph is 20 kV. Further, Figs. 1AB, 1BB, 1CB, 1DB and 1EB are RHEED photographs that show crystallinity corresponding to Figs. 1AA, 1BA, 1CA, 1DA and 1EA, respectively. As shown in Fig. 1AA, the surface of the silicon film deposited at 550°C (510°C) is very smooth, and no grain growth is observed. In addition, no ringlike patterns are visible in the RHEED photograph, Fig. 1AB, indicating that the film is amorphous. In the film deposited at 580°C (540°C) shown in Fig. 1BA, a partial growth of grains is observable, coexisting with the amorphous phase. Ringlike patterns appear in the RHEED photograph, Fig. 1BB, confirming a partial formation of crystals. When the deposition temperature is slightly raised to 590°C (550°C), hemispherical grains with diameter in the range of 300 to 1700 Å, centered around 700 Å, are formed at high density, generating a micro roughness on the surface, drastically increasing the surface area of the film. In the RHEED photograph shown in Fig. 1CB there are observable ringlike patterns, showing the occurence of crystallization. As the deposition temperature is further raised to 600°C (560°C) the surface roughness becomes somewhat gentle as shown in Fig. 1DA. In the RHEED photograph shown in Fig. 1DB, dots of reflection electron diffraction become visible, indicating the formation of polycrystalline silicon with high orientation. When the deposition temperature is further raised to 650°C (610°C), which is close to the deposition temperature of the ordinary polycrystalline silicon used for LSIs or the like, the grain diameter becomes further increased with smooth surface as shown in Fig. 1EA, and there are observed the dots of reflection electron diffraction with the formation of polycrystalline silicon as shown in Fig. 1EB. As is clear from the above result, at the temperature (transition temperature) in the range where the crystal condition of the deposited silicon film makes a transition from the amorphous phase to the polycrystalline phase, a very fine roughness is generated on the film surface and the surface area is increased compared with at other temperatures. A silicon film which is grown at the transition temperature where the crystal condition changes from the amorphous phase to the crystalline phase is considered to lack compactness to some extent. This is estimated from the fact that the etching rate, for example, by a wet etching method, of a silicon film grown at the transition temperature is higher than that of a polycrystalline silicon film deposited at an ordinary deposition temperature (a temperature higher than the transition temperature). When an extremely thin capacitor insulating film with thickness of 50 Å is formed on the silicon film, there is a possibility of generating pin holes in the insulating film. In order to make a silicon film deposited at the above-mentioned temperature to be more compact, it only needs to subject it to a heat treatment given at a temperature higher than the transition temperature, for example, a temperature higher than 640°C (600°C). This heat treatment will not affect the micro roughness in any substantial manner. Generation of pin holes can be precluded if a capacitor insulating film is formed subsequently. This heat treatment may be accomplished as included in the heat treatment on the occasion of impurity doping. Further, instead of giving a heat treatment at a temperature above the transition temperature, a compact polycrystalline silicon film may be deposited on the above-mentioned silicon having micro roughness to such an extent of thickness that will not fill in the micro roughness. The compact polycrystalline silicon may be deposited at a temperature above 600°C (560°C). In accordance with the above-mentioned method it is possible to form a silicon film with large surface area and small irregularity of characteristics by means of a simple fabrication process. By using such a silicon film as, for example, the electrode for the capacitor part of a semiconductor memory it becomes possible to increase the surface area, and hence the capacitance, of the capacitor for the same volume that is occupied by the capacitor part. As has been mentioned in the above the transition temperature has a certain range. When a silicon film is deposited at a temperature on the lower side of the range of the transition temperature, the grain diameter becomes large because the density of generation points of silicon nuclei on the surface of amorphous silicon is low. When a silicon film is deposited at a temperature on the higher side of the transition temperature range, the grain diameter becomes small because the density of generation points of silicon nuclei on the surface of amorphous silicon is high. The present inventors discovered that it is possible to control the size and the density of the grains by controlling the temperature within the range of the transition temperature as described in the above. Moreover, the size and the density of grains can also be controlled by varying the growth pressure of the silicon film within the range of the transition temperature. This is because the generation of the silicon nuclei on the surface of amorphous silicon is suppressed due to the mixing of hydrogen into the silicon film if the silicon film is deposited at a low wacuum. Because of this, the grain size becomes large. On the other hand, if a silicon film is deposited at a high vacuum, the mixing of hydrogen into the silicon film is decreased and the density of nucleus generation on the surface of amorphous silicon becomes high. Because of this, the grain size becomes small. As in the above, it was discovered that the size and the density of the grains can be controlled by controlling the deposition pressure and the density of hydrogen for the silicon film within the range of transition temperature as described in the above. Further, even if the pressure is constant, it is possible to control the grain size and the grain density by changing the hydrogen concentration in amorphous silicon by varying the partial pressure of the material gases. Moreover, it was also found that it is possible to control the generation density of silicon nuclei on the surface of amorphous silicon by controlling the hydrogen concentration within the silicon film by adding hydrogen gas at the time of depositing the silicon film at the transition temperature. Now, embodiments that employ the aforementioned methods will be described along with the effect of the present invention. Embodiment 1 A stacked capacitor was trially manufactured. A thick SiO 2 film was formed on a silicon substrate, a silicon film was formed on top of it in accordance with the method illustrated in Fig. 1, and the product was used as the lower electrode of the capacitor. Phosphorus was diffused into the silicon film obtained under the conditions of 820°C and 60 minutes, a capacitor insulating film was formed on the surface and a polycrystalline silicon film that is to become the upper electrode was formed on top of it. The formation of the capacitor insulating film was accomplished by first forming an Si 3 N 4 film on the silicon film by an LPCVD method, then by oxidizing the surface on the Si 3 N 4 film. The Si 3 N 4 film was deposited to a thickness of 120 Å at a temperature of 780°C and a pressure of 30Pa using a mixed gas of SiH 4 and NH 3 (with SiH 4 /NH 3 = 1/100), and the surface was oxidized at 900°C by wet 1:1 pyrogenic oxidation to the extent where there is obtained a thickness of 20 Å when converted to equivalent oxide film, in the 120 Å of the Si 3 N 4 film. Under the above-mentioned conditions the capacitor insulating film becomes 100 Å (labeled as deff) when converted to an equivalent SiO 3 film. If a smaller thickness of the capacitor insulating film, for example deff = 50 Å, is desired, it is only needed to form an Si 3 N 4 film of 60 Å and oxidize the film to the extent of an increase of 10 Å when converted to an oxide film. It is preferable that the thickness of the capacitor insulating film is in the range of 30 to 500 Å so as to enable the replication of the micro roughness of the lower layer silicon film onto the upper surface of the capacitor insulating film. After the formation of a capacitor insulating film of deff = 100 Å, then a polycrystalline silicon film is deposited on top of it at 640°C (600°C) and phosphorus was diffused into it. Following that, stacked capacitors were obtained by dividing the sample into the dimensions of 1 mm x 1 mm by means of a lithography technique and a dry etching technique. As a result, the dependences of the surface area and the capacitance of the silicon film on the deposition temperature of the lower silicon film as shown in Fig. 2 were obtained. Namely, for the deposition temperature of Fig. 1A the surface area remains at 1 mm 2 and the capacitance is accordingly at a small value of 3.5 nF. For the deposition temperature of Fig. 1B the capacitance was slightly increased to 3.8 nF corresponding to a partial growth of the grain. For the deposition temperature of Fig. 1C both of the surface area and the capacitance became more than twice the original values, namely, 2.1 mm 2 and 7.3 nF, respectively. For the deposition temperature of Fig. 1D a surface area of 1.07 mm 2 and a capacitance of 3.6 nF were obtained reflecting the gentleness of the surface roughness. For the deposition temperature of Fig. 1E the situation barely differs from that of Fig. 1A. Note that the results obtained at deposition temperatures other than those of Fig. 1 are also included in the figure. In either case, it is possible to obtain a capacitance that is more than twice as large that of an ordinary stacked capacitor with the same dimensions if a stacked capacitor uses a silicon film deposited at the transition temperature. The surface condition of a silicon film with a micro roughness formed once on its surface will not be changed substantially by a heat treatment in the subsequent stage. An SEM photograph of the surface condition when phosphorus is diffused under the conditions of 820°C and 60 minutes into the film deposited at 590°C (550°C) shown in Fig. 1C is shown in Fig. 3. Fig. 4 shows the surface area distribution (representative points only) within a four-inch wafer when phosphorus was diffused into the silicon film formed at 590°C (550°C). The measurement was taken using the stacked capacitor of Embodiment 1. The numerical values which indicate the ratio of the surface area with respect to that of the wafer formed at 550°C (510°C) show that the surface area increase is very uniform all over the wafer surface. In addition, its reproducibility was also found to be satisfactory. This uniformity prevails also between wafers and between lots, and the reproducibility is also high. In Fig. 5 is shown the leakage current characteristic of the stacked capacitors obtained at the deposition temperatures of 590°C (550°C) and 640°C (600°C). It can be seen that the result for the former case is somewhat inferior to the latter case. However, in the use for semiconductor memories the maximum voltage applied to a capacitor is 5 V (lately, 3.3 V). Therefore, there arises substantially no problem since there exist hardly any difference in the leakage current between the two cases up to the voltage of 5 V, and the applied voltage can be reduced to one half by the use of the well-known 1/2 Vcc cell plate technique. Here, the leakage current characteristic will be compared when the same capacity is secured. For the construction of a 64 Mbit DRAM with the ordinary stacked capacitor structure it is said that a capacitor insulating film of about 50 Å thickness when converted to equivalent oxide film (deff) is required if a polycrystalline silicon film deposited at the conventional temperature of about 640°C (600°C) is used as a storage electrode. However, by employing a silicon film in accordance with the present invention it becomes possible to use a capacitor insulating film with thickness of 100 Å. In Fig. 6 are shown the leakage current characteristic for two representative cases. As can be seen from the figure, the voltage by which the leakage current can be suppressed to below 1 x 10 -8 A/cm 2 where a capacitor is usable as a device is 2.0 V for the conventional capacitor. In contrast, the corresponding voltage can be increased to 5.4 V in the case of using silicon of the present embodiment, sharply improving the leakage current characteristic. In Fig. 7 is shown the breakdown voltage distribution for the same cases of deposition at 590°C (550°C) and 640°C (600°C) that are given in the lower and upper portions of the figure, respectively. The results shown correspond to the measurements results taken by using stacked capacitors with the same structure as in Embodiment 1 for several sheets of wafer. The thickness of the capacitor insulating film at this time was 100 Å. The peak value of the breakdown electric field intensity for the case of Si electrode deposition temperature at 590°C (550°C) is 8.7 MV/cm while the peak value for the case of 640°C (600°C) is 9.5 MV/cm so that the deterioration of the former case is 0.8 MV/cm relative to the latter. However, in the actual use such a difference is of no particular concern. Moreover, the scatter of the breakdown electric field intensity value is comparable for both samples, and is very satisfactory. Embodiment 2 The stacked capacitor used in the present embodiment was trially manufactured in the same way as in Embodiment 1. In Embodiment 1 the quality of the silicon film deposited at the transition temperature was made compact by a heat treatment at the time of phosphorus diffusion. In the present embodiment, however, the film quality was made compact by subjecting the sample to an annealing at a temperature above the transition temperature prior to the formation of the capacitor insulating film. In Fig. 8 is shown an SEM photograph of the surface of a silicon film deposited at the transition temperature of 590°C (550°C), then annealed at 740°C (700°C) in a nitrogen atmosphere. There is little change in the surface condition from that at the time of the film deposition. Subsequently, phosphorus was diffused similar to Embodiment 1, a capacitor insulating film was formed, a polycrystalline silicon film that is to become the upper electrode was deposited to form a stacked capacitor similar to that of Embodiment 1. Capacitance and surface area of a capacitor same as those of Embodiment 1 were obtained. They are extremely uniform within the wafer, from one wafer to another and from one lot to another as in Embodiment 1, with satisfactory reproduciblity. As to the leakage current characteristic and the breakdown voltage, the result obtained was satisfactory, being substantially the same as at the deposition temperature of 640°C (600°C). Now, it is to be noted that the annealing was carried out at 740°C (700°C) in the present embodiment, but the compactification of the silicon film may be accomplished by an annealing for a long time at a low temperature such as 650°C (610°C) or by an annealing at a high temperature of 840°C (800°C). Embodiment 3 In the present embodiment, instead of the annealing in Embodiment 2, a compact silicon film was deposited at a temperature above the transition temperature on a silicon film formed at the transition temperature. Here, a polycrystalline silicon film was deposited to a thickness of 300 Å at the temperature normally used. Figure 9 is an SEM photograph showing the surface condition of the surface after the deposition. There is observed little change in the surface condition. Following the above, a stacked capacitor was formed in the same way as in Embodiment 2, and the capacitance and the surface area of the capacitor formed were measured. The result is similar to that of Embodiment 1, their value distribution within the wafer, between wafers and between lots was extremely uniform, and its reproducibility was excellent. Further, the leakage current characteristic and the breakdown voltage were satisfactory, being substantially the same as those for the deposition temperature of 640°C (600°C). It is to be noted that it is necessary to limit the thickness of the silicon film to a degree which will not bury the micro roughness on the surface of the underlying silicon film. Embodiment 4 In the present embodiment, a stacked capacitor having a capacitor part also on the sides faces will be described. First, as shown in Fig. 10a, a silicon oxide film 2 is formed on a silicon substrate 1 with a transfer gate and the like formed thereon, resist 3 is applied to be patterned and the oxide film 2 is etched by dry etching (Fig. 10b). Then, as shown in Fig. 10c, a polycrystalline silicon film 4 is deposited, and an impurity such as phosphorus or arsenic is doped by thermal diffusion. The polycrystalline silicon film 4 is deposited by an LPCVD method under the normal conditions of the temperature of 640°C (600°C), reaction gas which is a mixture of SiH 4 and He (at 20 vol % of SiH 4 and 80 vol % of He) and pressure of 1 Torr. A silicon oxide film 5 is formed by a CVD method on the polycrystalline silicon film 4, and another polycrystalline silicon film 6 is formed on top of it under the same conditions as for the polycrystalline silicon film 4. A resist 7 is applied on top of it to be patterned (Fig. 10c), and by using the resist as a mask dryetching is given up to the polycrystalline silicon film 4 (Fig. 10d). Following the removal of the resist 7 a silicon film 8 having surface with a micro roughness is deposited at 595°C (555°C) (Fig. 10e). The deposition conditions are the same as for the polycrystalline silicon film 4 except for the temperature. Then, the sample is annealed at 740°C (700°C) for 30 minutes in a nitrogen atmosphere. Next, phosphorous or arsenic is doped into the silicon film 8 by thermal diffusion. Subsequently, the same is subjected to a reactive ion etching (RIE) that uses Cℓ 2 gas to obtain a lower electrode 8 for a stacked capacitor as shown in Fig. 10f. The top portion and the side faces of the silicon film 18 have even after the RIE a roughness with large area that reflects the roughness before the etching of the silicon film 8. In other words, the top portion and the side faces of the silicon film 18 are given a roughness by the replication of the roughness of the silicon film 8 onto the polycrystalline silicon film 6. Note that in the absence of the polycrystalline silicon film 6 the top portion of the stacked capacitor will be lost at the time of RIE and there will be left only its side faces. Next, a capacitor insulating film 9 is formed under the same conditions as for Embodiment 1, and further a phosphorus-doped polycrystalline silicon film 10 is deposited (Fig. 10g). In this manner, a stacked capacitor that has a capacitor parts formed also on the side faces and has a very large capacitance can be obtained. By increasing the thickness of the oxide film 5 it is possible to augment the area of the side faces and increase the capacitance accordingly. In Figs. 11a and 11b are shown the SEM photographs of the stacked capacitor formed. The magnifications of Figs. lla and llb are 40,000 and 25,000, respectively, showing approximately the same location of the capacitors. One of the forefront capacitors is revealing its cross section. From the figure it can be seen that there still remains a sufficiently well-defined roughness on the surface of the silicon film even after the dry etching. It should be mentioned here that phosphosilicate glass (PSG) , borophosphosilicate glass (BPSG), an impurity-doped polycrystalline silicon film, a silicon nitride film, a laminated film of some of the foregoings, or the like may be employed in place of the oxide film 5. Further, in the present embodiment the silicon film 8 having a micro roughness in Fig. 10f was subjected as it is to an RIE. However, if there should be any apprehension about losing the micro roughness on the side faces in the etching, it is possible to certainly protect the micro roughness on the side faces by thinly covering the entire surface with an SiO 2 film by means of high temperature oxidation (HTO) CVD prior to subjecting the sample to the RIE. The SiO 2 film that remains on the side faces after the RIE needs only be removed by wet etching or the like method. Further, in the present embodiment described in the above, the polycrystalline silicon film 6 formed at the temperature of 640°C (600°C) was used as a film for replicating the micro roughness on the silicon film 8, but the film 6 may be replaced by a silicon film deposited at or below the transition temperature. Moreover, in Embodiments 1 to 4, thermal diffusion was employed invariably for the doping to the silicon film, but there may be used ion implantation or a method in which a dopant gas such as PH 3 or AsH 3 is included in the material gas at the time of-deposition may also be employed. Moreover, the dopant may be boron besides phosphorus and arsenic. Furthermore, in Embodiments 1 to 4, an example has been shown in which a micro roughness is formed all over the surface of the portions of the silicon films 6 and 8 that are to become a capacitor, but the capacitance will become larger than the case of the conventional flat polycrystalline silicon film even when the micro roughness is formed even in a portion of the film. It should be mentioned that the shape of the storage electrode with a micro roughness for a stacked capacitor may be a plain cubic structure, a cylindrical structure, a fin-type structure or a stacked trench type.

Claims: A method of fabricating a semiconductor device having a capacitor, comprising the steps of: forming on a substrate (1, 2, 4, 5) a silicon layer (8) serving as a first electrode of said capacitor by depositing silicon on said substrate at a transition temperature from an amorphous phase to a polycrystalline phase of silicon, said silicon layer thereby having a micro-roughness surface caused by grains of silicon; forming a dielectric film (9) of said capacitor on said micro-roughness surface of said silicon layer with such a thickness that the surface of said dielectric film has a micro-roughness imparted by said micro-roughness surface of said silicon layer; and forming on said micro-roughness surface of said dielectric film a conductive layer (10) serving as a second electrode of said capacitor. The method as claimed in Claim 1, wherein said transition temperature is in the range 580 to 600°C. The method as claimed in Claim 1 or 2, wherein said dielectric film has a thickness in the range 3 to 50 nm (30 to 500 angstroms). The method as claimed in Claim 1, 2 or 3, wherein a size of each of said grains of silicon is in the range 30 to 170 nm (300 to 1700 angstroms) in diameter.

Inventors: TATSUMI TORU, WATANABE HIROHITO, TATSUMI, TORU,, WATANABE, HIROHITO,, TATSUMI, TORU, C/O NEC CORPORATION, WATANABE, HIROHITO, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: H01L29
IPC codes: H01L21, H01L29, H01L27