A solid-state imaging device

Abstract: A solid-state imaging device includes a plurality of light receiving elements, transfer gates for controlling reading-out of signal charges detected in the light receiving elements, a charge coupled device for transferring the signal charges in the light receiving elements successively by the ON operation of the transfer gates, and a charge input means provided at the initial stage of the charge coupled device. This charge input means is constituted by a charge input source, and a first and a second electrodes for controlling the quantity of input charges from the charge input source. The first electrode of the charge input means is arranged in contact with the charge input source. The second electrode is arranged in contact with the first electrode and connected with the light receiving element via the transfer gate or another charge coupled device. In this structure, the second electrode serves as an electrode for controlling the quantity of input charges by applying a dc voltage thereto at the charge input mode while it serves as a first stage transfer electrode by applying a clock pulse thereto at the imaging mode. Thus, operations at both modes can be performed without changing the array pitch of the light receiving elements at the charge input part.

Description: FIELD OF THE INVENTION The present invention relates to a solid-state imaging device and, more particularly, to a structure of a charge input means of a charge coupled device (hereinafter referred to as CCD). BACKGROUND OF THE INVENTION In linear image sensors, signal charges generated in a plurality of light receiving elements arranged on a one-dimensional array are read out by one CCD. Recently, needs for higher resolution have been increased and the number of light receiving element has been increased. However, as the number of light receiving element increases, the stage of CCD increases, resulting in a deterioration in overall transfer efficiency, a high-speed data rate or the like. In order to solve these problems, a solid-state imaging device shown in figure 6, in which light receiving elements are divided in the middle and signal charges are read out by two CCDs arranged in serial, has been proposed. In figure 6, which depicts a not published prior art device, a plurality of photodiodes (light receiving elements) 4 constituting a light-to-electricity conversion part are arranged in a line on a semiconductor substrate 3, and two CCDs 5 are arranged in parallel with the photodiode array. Respective photodiodes 4 are connected to the charge transfer part of the CCD 5 via transfer gates 6 and signal charges stored in the photodiodes 4 are transferred to the CCD 5 by the ON operation of the transfer gates 6. In addition, output amplifiers 7 are provided at the ends of the CCDs 5 and signal charges transferred through the CCDs 5 are amplified in the output amplifiers 7 and output from the solid-state imaging element 1. A charge input means 2 is provided between the initial stages of the CCDs 5, whereby charges, other than the charges from the photodiodes, are injected into the CCDs 5 from outside. This charge input means 2 electrically supplies charges to the CCDs 5 at a time other than during the imaging mode thereby to check and calibrate the CCDs 5 and the output amplifiers 7 or to test the respective transfer electrodes constituting the CCD 5 in the production process of the CCD 5. Figure 7 is a plan view showing the structure of the charge input means 2 in detail. In figure 7, reference numeral 10 designates a charge input terminal. Charge input controlling gates 8 and 9, which control the quantity of charges input from the charge input terminal 10, are provided at both sides of the charge input terminal 10. Reference numerals 11 and 12 designate transfer electrodes of the CCD 5. Operation at the time of charge input mode will be described hereinafter. Figure 8 (a) is a diagram schematically showing a cross-section taken along a line C - C' of figure 7 and the potential at times t 1 to t 4 at the charge input mode. Figure 8(b) schematically shows waveforms of signals that are applied to the respective terminals. Clock pulses I, 1, and 2 are applied to the charge input terminal 10, and signal input terminals of the transfer electrodes 11 and 12, respectively, and dc voltages V GIL and V GIH are applied to the signal input terminals of the charge input controlling gates 8 and 9, respectively. First, at time t 1 , the charge input terminal 10 and the transfer electrode 12 are at "H" level while the transfer electrode 11 is at "L" level. At time t 2 , the input signal I of the charge input terminal 10 becomes "L" level and charges are transferred from the charge input terminal 10 to the potential well beneath the input controlling gates 8 and 9. At time t 3 , the charge input terminal 10 again becomes "H" level and the input charges Q 0 are stored in the potential well beneath the input controlling gate 9. At time t 4 , 1 is at "H" level while 2 is at "L" level and then the transfer electrode 11 becomes "H" level and the transfer electrode 12 becomes "L" level, whereby measured charges Q 0 are transferred to the potential well beneath the CCD transfer electrode. Next, operation at the time of imaging mode will be described hereinafter. Figure 9 (a) is a diagram schematically showing a cross-section taken along a line C-C' of figure 7 and the potential at times t 1 to t 3 at the imaging mode. Figure 9(b) schematically shows waveforms of signals applied to the respective terminals. Clock pulses 1 and 2 are applied to the signal input terminals of the transfer electrodes 11 and 12, respectively, and dc voltages V GIL and V GIH are applied to the signal input terminals of the charge input controlling gates 8 and 9, respectively. Between times t 1 and t 2 , the transfer gate (TG) 6 is opened and the signal charges Q 1 and Q 2 detected respectively in the light receiving elements 4-1 and 4-2 are transferred to the potential wells beneath the corresponding transfer electrodes 11. At time t 3 , the signal 1 of the transfer electrode 11 is set to "H" level and the signal 2 of the transfer electrode 12 is set to "L" level, whereby the signal charges Q 1 and Q 2 are transferred to the potential wells beneath the transfer electrodes 12 at the next stage. Thereafter, by repeating this operation, the signal charges are synchronized with the clock pulses and successively transferred. Since the charge input part 2 of this linear image sensor is constituted as described above, the array pitch of the light receiving element 4 at the charge transfer part 2 is unfavorably larger than elsewhere. More specifically, in a case where the width of the transfer electrodes 11 and 12 is 8 µm and the interval between the adjacent light receiving elements 4-1 and 4-2 (in figure 7, ℓ 1 ) is 16 µm, the interval between the light receiving elements 4-1 (in figure 7, ℓ 2 ) is required to be 31 µm when the width of the charge input terminal is 4 µm and the widths of the charge input controlling gates 8 and 9 are 3 µm and 4 µm, respectively. When the space of the charge input part 2 is large and the array pitch of the light receiving element 4 corresponding to this part is large, resolution is sharply lowered at the charge input part 2, so that a uniform resolution over the chip cannot be obtained. US-A-4 647 977 discloses a solid state imaging device comprising a pair of horizontal charge coupled devices (CCD's) arranged in series with a multiplex output section arranged therebetween. Each element of a linear array of light-receiving elements is coupled to a respective stage of the horizontal CCD's via vertical CCD shift registers. These latter have a fanned arrangement so that a uniform element spacing is possible for the linear array. Other features of this disclosure are recited in the preamble of the main claim appended hereto. The solid state image device according to the present invention is characterised in that the charge input means comprises a first electrode and second electrode adjacent to, and downstream of, the first electrode; a first one of the light receiving elements coupled to a region under the second electrode which the first region is part of the initial stage of the charge-coupled device; and supply means is arranged to supply, to the first electrode, a first dc voltage during charge input and image read-out modes, and to the second electrode, a second dc voltage during the charge input mode, and a clock signal synchronised with one of the clock pulses during the image read-out mode. The aforesaid structure is of particular advantage when the charge coupled device and another are arranged with the charge input means therebetween. Since the second electrode of the charge input means is also provided as a first stage transfer electrode to transfer image charge, the structure is compact and the light-receiving elements can be arranged at a uniform spacing - i.e. without a larger spacing between the elements adjacent to the charge input means. In the accompanying drawings: Figure 1 is a plan view showing an input part of a one-dimensional solid-state imaging device in accordance with a preferred embodiment of the present invention; Figure 2(a) is a diagram showing a cross-section taken along a line A-A' of figure 1 and the potential at the time of charge input mode and figure 2(b) is a diagram schematically showing waveforms of signals applied to the respective terminals; Figure 3(a) is a diagram showing a cross-section taken along a line A-A' of figure 1 and the potential at the time of an imaging mode and figure 3(b) is a diagram schematically showing waveforms of signals applied to the respective terminals; Figures 4(a) and 4(b) respectively are plan views showing a two-dimensional solid-state imaging device, and an input part thereof in accordance with the preferred embodiment of the present invention; Figure 5 is a plan view showing an alternative of the two-dimensional solid-state imaging device in accordance with the preferred embodiment of the present invention; Figure 6 is a plan view showing a one-dimensional solid-state imaging device in accordance with not published prior art; Figure 7 is a plan view showing a charge input part of the device shown in figure 6; Figure 8(a) is a diagram showing a cross-section taken along a line C-C' of figure 7 and the potential at the time of charge input mode and figure 8 (b) is a diagram schematically showing waveforms of signals applied to the respective terminals; and Figure 9 (a) is a diagram showing a cross-section taken along a line C-C' of figure 7 and the potential at the time of imaging mode and figure 9 (b) is a diagram schematically showing waveforms of signals applied to the respective terminals. A preferred embodiment of the present invention will be described in detail with reference to the drawings. Figure 1 is a plan view schematically showing a structure of a solid-state imaging device in accordance with a preferred embodiment of the present invention, in which a charge input means is provided at the centre of the structure and two CCDs are serially arranged with the charge input means therebetween. In figure 1, a light-to-electricity conversion part 4 is constituted by a plurality of light receiving elements 4-1, 4-2, 4-3, 4-4 ... . Signal charges detected in the light-to-electricity conversion part 4 are transferred to the CCDs 5 via the transfer gates 6 by the ON operation of the transfer gates 6. Reference numerals 11 and 12 designate transfer electrodes of the CCDs 5 and numerals 1 and 2 are input signals applied to the transfer gates 11 and 12. Reference numeral 10 designates an electrode input terminal for electrically injecting charges into the CCDs 5 from outside. First charge input controlling gates 13 are provided adjacent to the charge input terminal 10 and control the charges input from the charge input terminal 10. Common gates 14 are provided adjacent to the first charge input controlling gates 13 and serve both as second charge input controlling gates and initial stage transfer electrodes. The common gates 14 serve as the second input controlling gates at the time of charge input mode and as the transfer gates like the transfer electrodes 11 at the time of imaging mode. Operation at the charge input mode will be described hereinafter. As described above, in the charge input mode, the common gates 14 serve as the second charge input controlling gates with the first charge input controlling gates 13 and they function in the same way as the charge input controlling gates 8 and 9 of the prior art device. Figure 2(a) shows a cross-section taken along a line A-A' of figure 1 and the potential at times t 1 to t 4 . Figure 2(b) schematically shows waveforms of signals applied to the respective terminals. Clock pulses I, 1 and 2 are applied to the charge input terminal 10 and the transfer electrodes 11 and 12, respectively, while dc voltages V GIL and V GIH are applied to the first charge input controlling gate 13 and the common gate 14, respectively. The quantity of the input charge is measured by the difference in voltages applied to the gates 13 and 14 and controlled to be a desired value. Between times t 1 and t 2 , charges are transferred from the charge input terminal 10 to the potential well beneath the input controlling gate 13 and the common gate 14. At time t 3 , the charge input terminal 10 becomes "H" level again and the measured input charges Q 0 are stored in the potential well beneath the common gate 14. At time t 4 , the transfer electrode 12 becomes "H" level and the charges Q 0 are transferred to the potential well beneath the CCD transfer electrode 12. Thus, the charge input operation can be performed in the same way as in the prior art device. Operation in the imaging mode will be described hereinafter. Figure 3(a) shows a cross-section taken along a line A-A' of figure 1 and the potential at times t 1 to t 3 . Figure 3(b) schematically shows waveforms of signals applied to the respective terminals. A clock pulse having the same phase as that applied to the transfer electrode 11 is applied to the common gate 14 and a dc voltage is applied to the charge input controlling gate 13. Between times t 1 and t 2 , the transfer gates 6 are opened and signal charges Q 1 and Q 2 stored in the light receiving elements 4-1 and 4-2, respectively, are transferred to the potential wells beneath the common electrode 14 and the transfer electrode 11, respectively. Thereafter, the transfer electrode 11 and the common electrode 14 are set to "L" level and the transfer electrode 12 is set to "H" level by applying clock pulses and then the signal charges Q 1 beneath the common electrode 14 are transferred to the potential well beneath the transfer electrode 12 and the charges Q 2 beneath the transfer electrode 11 are transferred to the potential well beneath the next stage transfer electrode. In this way, signal charges synchronized with the clock pulses are successively transferred like the prior art image sensor. In this embodiment of the present invention, since the electrode 14 serves both as the second electrode for controlling the quantity of input charge and the initial stage transfer electrode for transferring signal charges, the array pitch of the light receiving elements at the charge input part is as follows with employing the conventional design basis as it is. In case where the width of the transfer gates 11 and 12 is 8 µm and the interval ℓ1 between adjacent light receiving elements other than those at the charge input part is 16 microns like the prior art device, by setting the width of the charge input terminal 10 to 4 µm and the widths of the charge input controlling gate 13 and the common gate 14 to 3.5 µm and 5 µm, respectively, the interval ℓ2 between the light receiving elements 4-1 at the charge input part 2 can also be 16 µm. Accordingly, in this embodiment, the spacing of the charge input part 2 can be reduced without changing the scale of the electrode input terminal and the charge input controlling gate, and the array pitch of the light receiving elements corresponding to the charge input part can be equal to the array pitch of the light receiving elements at the other parts. As described above, the charge input controlling electrode and the transfer electrode are constituted by the same electrode 14. A dc voltage is applied to the electrode 14 at the time of charge input mode so that it may serve as the second charge input controlling electrode and a clock pulse is applied thereto at the time of imaging mode so that it may serve as the transfer electrode. Therefore, the space of the charge input part 2 can be reduced and the array pitch of the light receiving elements corresponding to the charge input part can be equal to the array pitch of the light receiving elements corresponding to the other parts, whereby the pattern design can be simplified. In addition, no reduction in resolution occurs at the charge input part and a uniform resolution can be obtained in the chip. While a one-dimensional solid-state imaging device has just been described, the present invention also can be applied to a two-dimensional solid-state imaging device. Figure 4(a) is a plan view showing a two-dimensional solid-state imaging device in which the charge input part 2 of the above embodiment is applied to a horizontal CCD, and figure 4(b) is a plan view showing the charge input part 2 and its vicinity in detail. In these figures, the same references as those shown in figure 1 designate the same parts, and reference numerals 5a and 5b designate vertical CCDs and horizontal CCDs, respectively. The structure of the charge input part 2 is similar to that shown in figure 1 according to the first embodiment except that image signals are input from light receiving elements via vertical CCDs 5a. In this structure, the two-dimensional solid-state imaging device is divided in the middle and signal charges detected in the light receiving elements 4 are transferred to the vertical CCDs 5a through the transfer gates 6. Signal charges transferred from the vertical CCDs 5a are read out simultaneously by the two horizontal CCDs 5b. Also in this structure, the common gates 14 are provided in the charge input part 2 between the horizontal CCDs 5b, and a dc voltage is applied to the common gates 14 at the time of charge input mode so that they may serve as charge input controlling gates and a clock pulse synchronized with the transfer electrode 11 is applied thereto at the time of imaging mode so that they may serve as transfer electrodes of the CCDs 5. Thus, similarly as discussed above, the space of the charge input part 2 can be reduced and the array pitch of the light receiving elements corresponding to this part can be equal to the array pitch of light receiving elements corresponding to the transfer electrode parts. As a result, a reduction in resolution, which is caused by the provision of the charge input part, can be prevented. Figure 5 is a plan view showing another structure of two-dimensional solid-state imaging device, in which two two-dimensional solid-state imaging devices shown in figure 2 are symmetrically arranged on the semiconductor substrate 3. Also in this structure, when the charge input part 2 of the preferred embodiment is employed, all the light receiving elements 4 can be arranged at the same pitch, whereby the pattern production can be simplified and an uniform resolution can be obtained in the chip.

Claims: A solid state imaging device comprising: a first charge-coupled device (5); a first plurality of light receiving elements (4-1 to 4-4), each coupled through a transfer gate (6) to a respective stage of said first charge-coupled device (5), charge input means (2) for controlling a quantity of charge input from a charge input source (10) to the initial stage of said first charge-coupled device; and clocking means arranged to supply clock pulses ( 1 ,  2 ) to the transfer electrodes (11,12) of said first charge-coupled device to transfer charges (Q 0 ,Q 1 ,Q 2 ) along said first charge-coupled device, characterised in that: said charge input means (2) comprises a first electrode (13) and a second electrode (14) adjacent to, and downstream of, said first electrode (13); a first one (4-1) of said light receiving elements (4-1) is coupled to a region under said second electrode (14) which region is part of the initial stage of said first charge-coupled device (5); and supply means is arranged to supply, to the first electrode (13), a first dc voltage (V GIL ) during charge input and image read-out modes, and to the second electrode (14), a second dc voltage (V GIH ) during the charge input mode, and a clock signal synchronised with one of said clock pulses ( 1 ,  2 ) during the image read-out mode. A solid state imaging device according to claim 1 including: a second charge-coupled device (5) arranged in series with said first charge-coupled device (5) with said charge input means (2) therebetween; and a second plurality of light receiving elements (4-1 to 4-4) each coupled through a transfer gate (6) to a respective stage of said second charge-coupled device; wherein the transfer electrodes (11,12) of said second charge-coupled device are connected to said clocking means to receive said clock pulses ( 1 , 2 ); said charge input means (2) includes another first electrode (13) and another second electrode (14) adjacent to and downstream of said another first electrode (13) in the transfer direction of said second charge-coupled device away from said input means (2); said another first and second electrodes (13,14) are connected to said supply means likewise to receive said first and second dc voltages (V GIL ,V GIH ) and said synchronised clock signal; and a first one (4-1) of the light receiving elements (4-1 to 4-4) of said second plurality is coupled to a region under said another second electrode (14), which region is part of the initial stage of said second charge-coupled device (5). A solid state imaging device according to claim 2, wherein the spacings (ℓ 1 ) of said light receiving elements of each first and second plurality and the spacing (ℓ 2 ) between said first one (4-1) of said first plurality and said first one (4-1) of said second plurality are equal. A solid state imaging device according to any preceding claim, wherein respective third charge-coupled devices (5a) are interposed between respective stages of said first, or of said first and second, charge-coupled devices (5b) and respective ones of said light receiving elements (4) with respective transfer gates(6).

Inventors: MASUDA TAKESHI, MIYACHI YUJI, SHIRAISHI TADASHI, YASHIRO KIYOTAKA, MASUDA, TAKESHI, MIYACHI, YUJI, SHIRAISHI, TADASHI, YASHIRO, KIYOTAKA, Masuda, Takeshi, c/o National Space Dev. Agency, Miyachi, Yuji, c/o National Space Dev. Agency, Shiraishi, Tadashi, c/o Mitsubishi Denki K.K., Yashiro, Kiyotaka, c/o National Space Dev. Agency
Applicants: MITSUBISHI ELECTRIC CORP, NAT SPACE DEV AGENCY, MITSUBISHI DENKI KABUSHIKI KAISHA, NATIONAL SPACE DEVELOPMENT AGENCY OF JAPAN
Application year: 1991
Main classification: H01L27
IPC codes: H01L27, H01L29, H04N5, H01L21