Flash A/D converter with test circuit

Abstract: Apparatus and procedure for testing a flash analog-to-digital converter on a chip (80) including a first NOR gate (70) having a plurality of inputs, one each connected to each normal output (36) of the comparators (10) and a second NOR gate (72) having a plurality of inputs, one each connected to each inverted output (35) of the comparators (10). The output currents of the NOR gates (70, 72) are monitored to determine the states of the comparators (10) when various input voltages are supplied. All comparators (10) are tested for operation.

Description: The present invention pertains to an analog-to-digital (A/D) converter including a test circuit and more specifically to a fast apparatus and method for testing A/D converters on an integrated circuit. Background of the Invention Flash A/D converters, semi-flash A/D converters, parallel-sequence A/D converters, and some other types of A/D converters contain large numbers of matched comparators, which number is fixed by the number of bits in the system and the structure of the system. In the case of an 8-bit flash A/D converter, the number of matched comparators is 256. All of the comparators in the converter must be tested to guarantee the performance of the converter. Normally, A/D converters can be tested by several methods, but all of these methods require multiple test steps for each comparator in the converter. If a resolution of 0.05 for a least significant bit (LSB) is required for the converter, the test steps for each comparator becomes 20. Thus, the total number of steps required to fully test the converter are 5120. If, for example, one millisecond is needed for one test step, the total time required to complete the test of the converter is 5.1 seconds. This test time is very long in mass production. Reducing this test time is a key to production cost reduction. An analog-to-digital converter including test apparatus in accordance with the pre-characterizing portion of claim 1 is known from patent publication EP-A-0,092,808. Summary of the Invention In accordance with a first aspect of the invention there is provided an analog-to-digital converter including test apparatus as claimed in claim 1. In accordance with a second aspect of the invention there is provided a method of testing an analog-to-digital converter as claimed in claim 5. Brief Description of the Drawings Referring to the drawings: FIG.1 is a schematic diagram of an A/D converter integrated circuit embodying apparatus portions of the present invention; FIG.2 is a schematic diagram of a typical comparator that is used in the structure of FIG.1; FIG.3 is a schematic diagram of a portion of a logic circuit illustrated in FIG.1; FIG.4 is a schematic/block diagram of a test set-up for the structure of FIG.1; and FIGS.5 through 7 are graphical representations of histograms produced by the test set-up of FIG.4. Description of the Preferred Embodiment FIG.1 illustrates a schematic diagram of an analog-to digital (A/D) converter integrated circuit embodying portions of the apparatus for the present invention, which portions are included on a single semiconductor chip. In this specific embodiment the A/D converter is the flash type but it will be understood by those skilled in the art that other types, such as parallel-sequence, etc., might be utilized. The A/D converter of FIG.1 includes a plurality of comparators, generally designated 10, connected to a priority encoder 40 and binary encoder 50 in the usual manner. The analog input is supplied to one terminal of each of the comparators 10 by way of an input terminal V X . A reference voltage is supplied to input terminals V T and V B , which are opposite ends of a resistance ladder 60. The reference voltage connected across the resistance ladder provides a voltage ladder, the various steps of which provide a plurality of particular reference voltages V R which are connected a to second input of each of comparators 10 Referring specifically to FIG.2, a typical two stage, chopper type voltage comparator 10 is illustrated. A first stage 12 of voltage comparator 10 includes an inverter 14 and a coupling capacitor 16 connected to an input thereof. A transmission gate switch 18 is connected from the output to the input of inverter 14. One terminal of capacitor 16 is connected to the input of inverter 14 and the other terminal is connected to a comparator input node 19 of the first stage 12. A transmission gate switch 20 is connected between the node 19 and a signal input terminal 21. A transmission gate switch 22 is connected between the node 19 and a reference voltage (V R ) input terminal 23. Comparator 10 has a second stage 25 which includes an inverter 27 and a coupling capacitor 29 connected to an input of inverter 27. A transmission gate switch 30 is connected from the output to the input of inverter 25. One terminal of capacitor 29 is connected to the input of inverter 27 and the other terminal is connected to a comparator input node 31 of the second stage 25. Voltage comparator 10 may have additional inverters 33 and 34 connected in series with the second stage 25, if additional amplification of the output signals is desired. The final, or normal, output signal is available at an output terminal 36 and an inverted output is available at an output terminal 35. In the operation of voltage comparator 10, switches 18, 20 and 30 are closed while switch 22 remains open. An unknown signal voltage (V X ) on input terminal 21 is supplied to voltage comparator 10 (sampled) and stages 12 and 25 are autozeroed to their toggle points. That is, switches 18 and 30 are closed so that first stage 12 and second stage 25 are zeroed at the unknown signal voltage (V X ), which is the toggle point for further operation. Switches 18, 20 and 30 are then opened and switch 22 is closed, which supplies the reference voltage (V R ) on input terminal 23 to node 19. Since stages 12 and 25 are at their toggle point, if the reference voltage (V R ) is greater than the unknown signal voltage (V X ) stages 12 and 25 will toggle in a first direction and a one, in this example a positive output, will be available at output 36, while a zero or ground potential signal will be available at output terminal 35. If the reference voltage is less than the unknown signal voltage stages 12 and 25 will toggle in a second direction and a zero will be available at output 36 while a one will be available at output terminal 35. Inverters 14 and 27 operate to provide some signal gain, with one stage being on the order of 12.5 and two stages being approximately 120. Thus a comparison between the unknown signal voltage and a reference voltage is provided by voltage comparator 10 and the amount of signal gain required will determine the number of stages utilized. While the above explained operation is correct, it will be understood that each comparator 10 may have slightly different characteristics, even though they are all formed on the same semiconductor chip and are considered to be matched. Because of these potential differences, production limitations are normally specified. These specifications include limits for V X >V R and V X <V R .at which the comparator will provide an output. Thus a test must be made on each comparator 10 to determine if it comes within the production limitations. If a comparator in an integrated circuit does not come within the specified limitations the integrated circuit must be discarded. The test apparatus included in the integrated circuit and the procedure described below is capable of completely testing each comparator 10 in the integrated circuit in a minimum number of steps. All of the normal output terminals 36 of comparators 10 are connected to inputs of a logic circuit, which in this embodiment is a NOR gate 70, having a separate input for the normal output of each comparator 10. In the previously stated example, an eight bit converter requires 255 comparators and, in that example, NOR gate 70 has 255 inputs. Similarly, each inverted output terminal 35 of comparators 10 is connected to a separate input of another logic circuit 72. In the present embodiment, each of the NOR gates 70 and 72 include a plurality of field effect transistors (FETs) 78 connected in parallel, as illustrated in FIG.3. FETs 78 each have a drain connected to an external voltage supply, which is actually the output of the logic circuit, and a source connected to a reference potential, in this embodiment ground. NOR gates 70 and 72, and the connections to comparators 10 are included in the integrated circuit and outputs of NOR gates 70 and 72 are output terminals 74 and 76, respectively, of the integrated circuit. The gates of FETs 78 are the input terminals to each of NOR gates 70 and 72, which are connected to the output terminals of comparators 10. In this embodiment, the particular FETs utilized each draw 10 microamperes when turned on. Thus, in the above example, 255 FETs will draw a total of 2.55 milliamperes when they are all turned on. Referring specifically to FIG.4, a histogram current monitor test circuit is illustrated. In this particular arrangement the integrated circuit of FIG.1, designated 80, has a variable voltage source 81 connected to the signal input terminal V X thereof. A reference voltage source 82 is connected to both of the reference voltage source input terminals V T and V B of integrated circuit 80. One side of an ammeter 84 is connected to output terminal 74 of integrated circuit 80 and the other side is connected to a power supply 88. Also, one side of a second ammeter 86 is connected to output terminal 76 of integrated circuit 80 and the other side is connected to power supply 88. The usual timing and power connections to integrated circuit 80 are not shown since these are well known in the art and do not form a portion of this invention. To fully test each of the comparators in integrated circuit 80 the following procedure is followed. NOR gate 70 provides an "all zero" output, i.e. only comparators that recognize V X >V R and provide a positive (1) output will turn on one of FETs 78 in NOR gate 70 and contribute current to output 74. Similarly, NOR gate 72 provides an "all one" output since only comparators that recognize V X <V R and provide a low (0) output will turn on one of FETs 78 in NOR gate 72 and contribute current to output 76. Since all of the signal input terminals of comparators 10 are connected to variable voltage supply 81 and since all of the reference voltage input terminals of comparators 10 are connected to voltage source 82, to test all of comparators 10 variable voltage source 81 is simply stepped through a range of voltages from the lowest acceptable production limit to the highest acceptable production limit. The variation can be, for example, from V R -1.0LSB equivalent voltage to V R +1.0LSB equivalent voltage. Further, the test may consist simply of three steps, the upper production limit, the center and the lower production limit, or the test may consist of as many as 20 steps with a minimum test step of 0.05LSB being selected. FIG.5 is a histogram of the output currents measured in ammeters 84 and 86 as variable voltage source 81 is varied from a point V X <V R to a point V X >V R , with N representing the number of comparators that are turned on. If all comparators are operating correctly, N will be maximum at V X =V R and drop to zero within the production limits. Since the operator will know the amount of current drawn by one of FETs 78 in logic gate 70 or 72, it is a simple matter to determine the number of comparators 10 that are turned on (or off) at any setting of variable voltage source 81. This test can easily be computerized and made either automatic or virtually automatic. FIGS,6 and 7 illustrate histograms for outputs 74 and 76, respectively. A high speed go/no-go test can easily be developed by utilizing such histograms. Output current in output terminal 74 will be turned on by the most positive offset comparator 10 when V X <V R +offset is applied to signal input V X . The output current in output terminal 74 can be used as an "underflow" indicator. Similarly output current in output terminal 76 will be turned on by the most negative offset comparator 10 when V X >V R -offset is applied. The output current in output terminal 76 can be used as an "overflow" indicator +/-offset or +/- DNL (differential nonlinearity) is specified by the production limitations or the data sheets of the integrated circuit. Therefore, two tests can guarantee the DNL at a V R . Multiple points are needed to guarantee the common mode range, which is the same as V T and V B reference voltage of the A/D converter. Three points, however, are enough for the common mode operation test. Thus, a new and improved A/D converter incorporating logic circuitry for the high speed test thereof has been disclosed. Further, additional apparatus and improved methods of testing the A/D converter are disclosed. The prior art methods of testing A/D converters required multiple tests on each comparator which could result in, for example, 5120 tests for a simple 8-bit flash A/D converter. The present apparatus and methods can fully test the same converter in 1/256 of the steps. Assuming a test time of 1 microsecond per step, the present apparatus and method can test an A/D converter in 20 microseconds versus 5.1 seconds for the prior methods. This is a substantial improvement and can greatly reduce production time and costs. While we have shown and described specific embodiments of this invention, further modifications and improvements will occur to those skilled in the art. We desire it to be understood, therefore, that this invention is not limited to the particular forms shown and we intend in the appended claims to cover all modifications which do not depart from the scope of this invention.

Claims: An analog-to-digital converter including test apparatus and comprising a reference voltage ladder (60) adapted to have a reference voltage connected thereacross and a plurality of matched comparators (10) each having a first input terminal (23) adapted to be connected to a predetermined reference voltage on said ladder (60), a second input terminal (21) adapted to receive an input signal to be converted to a digital signal and a normal output terminal (36) , the analog-to-digital converter further characterized by: each of the matched comparators further having an inverted output terminal (35); a first logic circuit (70) having a plurality of input terminals, one each connected to each of the normal output terminals (36) of said comparators (10); a second logic circuit (72) having a plurality of input terminals, one each connected to each of the inverted output terminals (35) of said comparators (10); and one of said first and second logic circuits (70, 72) providing a signal on an output terminal(74, 76) thereof indicative of the number of said comparators (10) in which the applied reference voltage exceeds the input signal and the other of said first and second logic circuits (70, 72) providing a signal on an output terminal (74, 76) thereof indicative of the number of said comparators (10) in which the applied reference signal is less than the input signal. An analog-to-digital converter including test apparatus as claimed in claim 1 further characterized in that the reference voltage ladder (60), plurality of comparators (10), first and second logic circuits (70, 72) and the connections therebetween are provided on a single semiconductor chip (80). An analog-to-digital converter including test apparatus as claimed in claim 1 further characterized in that the first logic circuit (70) has a plurality of input terminals, one each connected to each normal output (36) of the plurality of comparators (10) for providing an output signal indicative of the underflow current of the converter for a specific input signal and the second logic circuit (72) has a plurality of input terminals, one each connected to each inverted output (35) of the plurality of comparators (10) for providing an output signal indicative of the overflow current of the converter for the specific input signal. An analog-to-digital converter including test apparatus as claimed in claim 3 further characterized in that the first logic circuit (70) includes a first NOR gate (70) and the second logic circuit (72) includes a second NOR gate (72). A method of testing an analog-to-digital converter including a plurality of comparators (10) characterized by the steps of: providing normal (36) and inverted (35) outputs from each of the comparators (10); providing a first logic circuit (70) having a plurality of input terminals connected to receive one each of the normal output signals (36) from the plurality of comparators (10); providing a second logic circuit (72) having a plurality of input terminals connected to receive one each of the inverted output signals (35) from the plurality of comparators (10); supplying a reference voltage and a predetermined number and variety of input signals to each of the plurality of comparators; and monitoring the amount of output current at outputs (74, 76) of each of the first and second logic circuits (70, 72) for each of the predetermined number and variety of input signals supplied to the comparators (10). A method of testing an analog-to-digital converter including a plurality of comparators (10) as claimed in claim 5 further characterized in that the comparators (10), first and second logic circuits (70, 72) and the connections therebetween are provided on a single semiconductor chip (80) and one output terminal (74) is provided on the chip (80) for an output of the first logic circuit (70) and a second output terminal (76) is provided on the chip (80) for an output of the second logic circuit (72). A method of testing an analog-to-digital converter including a plurality of comparators (10) as claimed in claim 5 further characterized in that the step of supplying the reference voltage and the predetermined number and variety of input signals includes the step of supplying the same reference voltage and the same input signals to each of the comparators (10) simultaneously.

Inventors: KASE KIYOSHI, SEKIGUCHI HISASHI, KASE, KIYOSHI, SEKIGUCHI, HISASHI, SEKIGUCHI, HISASHI, 253-40 AZA NAKAMURA-HIGASHI
Applicants: MOTOROLA JAPAN, NIPPON MOTOROLA LTD.
Application year: 1991
Main classification: H03M1
IPC codes: H03M1