Cell library method for semiconductor integrated circuit design

Abstract: A cell library for a semiconductor integrated circuit design, comprises a CMOS cell (3) comprising two power source wires (5 and 7) and a CMOS circuit (9) placed between the two power source wires (5 and 7) with a predetermined distance, and a BiCMOS cell (11) comprising two power source wires (15 and 17) which are placed at a distance equal to the distance between the power source wires (5 and 7) in the CMOS cell (3), a CMOS circuit (13) placed between the two power source wires (15 and 17) in the BiCMOS cell (11), and bipolar transistor circuits (14 and 16) placed at both outsides of the two power source wires (15 and 17) in the BiCMOS cell (11).

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention relates to a cell library for a semiconductor integrated circuit design, more particularly a cell library for gate array or standard cell including BiCMOS cells. Description of the Prior Art There are three types of conventional design methods for LSIs. The first is the method wherein all processes, from positioning the elements to the wiring for a transistor or the like, are performed anew each time on a semiconductor substrate. this is known as the full custom method and exhibits the features of high performance and good efficiency in forming a small chip. On the other hand, this method has the drawback that development requires a long time and much labor. The second method is the opposite of the first, in as much as the elements of the transistor or the like are provided in advance in the form of an array on the substrate of the semiconductor, already prepared as a wafer, and only the wiring between the elements must be decided, according to the application. This is referred to as the gate array method. The wiring for forming the necessary blocks (cells) to provide the various functions using this array is designed in advance and preperated in the form of a library. The designer combines the appropriate cells with reference to the library, and designs the intercell wiring. Following this, the actual wiring is done to required with this method is extremely short. Intermediate to these two methods is the third method, known as the standard cell method. In this case, the arrangement of the elements and the wiring within one cell are designed as the optimum for each cell, and the designer, as a result, requires a shorter development period than for the full custom because only the combining of the cells and their interwiring need be performed. However, the arrangement of the cells on the semiconductor substrate from the stage of preparing the wafer, and more time is required to complete the LSI than for the gate array. A conventional CMOS gate array or CMOS standard cell is illustrated in Fig. 1. A basic cell 101 is arranged to form a plurality of rows between which a wiring field 103 is interposed. A power source wiring 105 and a power source wiring 107 are formed on the upper and lower ends respectively of the individual cells, and the power wiring is connected automatically between the sudjoining cells so that two series of power wiring 105 and 107 are formed, running through the respective rows. In the development of conventional gate array or standard cells as described above, the utilization of the design method is limited to the circuitry around which the CMOS is centered. If a decision is made to use a circuit including a bipolar element (BiCMOS) as a gate array or standard cell, respectively, in the case where a bipolar element is incorporated in the cell, one cell becomes rather large in size. To add this cell with a bipolar element to a conventional library, certain means are required. In the most common means considered, the design is modified to adapt each cell of a CMOS library to the BiCMOS size. However, in this case the entire cell library must be rebuilt, which necessitates a great deal of time and trouble. Furthermore, the necessity is produced for separately administering a library for CMOS use and a library for BiCMOS use, which is very inefficient. Proc. IEEE 1990 Custom Integrated Circuit, Conf. pp. 421-424 discloses a high integrated density BiCMOS sea-of-gates in which bipolar and PMOS transistors are merged to form compact basic cells and increase the number of bipolar transistors. In EP-A-0 189 183, a semiconductor integrated circuit device is disclosed having a plurality of basic cells in a particular layout. In one particular integrated circuit device, the elements of each basic cell together constitute a bipolar-CMOS composite circuit. A particular wiring layout is disclosed in which Vcc and ground wirings extend above and below the cells. SUMMARY OF THE INVENTION An object of the present invention is to provide an improved method of making a semiconductor integrated circuit using a cell library, the integrated circuit including CMOS and BiCMOS cells. According to the invention from one aspect there is provided: A method of making a semiconductor integrated circuit using a cell library, said method comprising the steps of: forming a CMOS cell (3) comprising: a first pair of power wires (5 and 7) separated from each other by a predetermined distance; and a CMOS circuit (9) selected from the cell library, positioned between the first pair of power wires (5 and 7); and forming a BiCMOS cell (11) comprising: a second pair of power wires (15 and 17) which are placed at a distance apart equal to said predetermined distance; a CMOS circuit (13) selected from the cell library, positioned between the second pair of power wires (15 and 17); and bipolar transistor circuits (14 and 16) selected from the cell library, positioned at both outsides of the second pair of power wires (15 and 17), the first pair of power wires (5 and 7) being connected to the second pair of power wires. According to the invention from another aspect there is provided: A method of making a semiconductor integrated circuit using a cell library, said method comprising the steps of: forming a CMOS cell (29) comprising: a first pair of power wires (25 and 27) separated from each other by a predetermined distance; and a CMOS circuit selected from the cell library, positioned between the first pair of power wires (25 and 27); and forming a BiCMOS cell (23) comprising: a second pair of power wires (31 and 33) which are placed at a distance apart greater than said predetermined distance; a CMOS circuit selected from the cell library, positioned between the second pair of power wires (31 and 33); and bipolar transistor circuits (14 and 16) selected from the cell library, positioned at both insides of the second pair of power wires (31 and 33), the first pair of power wires (25 and 27) being connected to the second pair of power wires (31 and 33) . These and other objects, feature and advantages of the present invention will be more apparent from the following description of a preferred embodiment, given by way of example and taken in conjunction with the accompanying drawing. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view of a conventional integrated circuit in which conventional CMOS cells are used; Fig. 2 is a plan view of an integrated circuit in which BiCMOS cell and CMOS cell in a cell library according to the present invention are used; Fig. 3 is a plan view of a sea of gate array cell according to the present invention; Figs. 4 and 5 are circuit diagrams of a conventional inverter; Fig. 6 is a plan view of an integrated circuit in which another type BiCMOS cell, CMOS cell, and a connecting cell in a cell library according to the present invention are used; and Fig. 7 is a plan view of an integrated circuit in which another type BiCMOS cell and CMOS cells in a cell library according to the present invention are used. DETAILED DESCRIPTION OF THE EMBODIMENTS Fig. 2 illustrates the configuration of an integrated circuit using a cell library as a first embodiment of the present invention. This circuit can be applied in the case of both a gate array and a standard cell. Specifically, in the case of a gate array, a plurality of elements is methodically formed in rows on a semiconductor substrate 1 and the function of each cell is provided by then forming the appropriate wiring. In the case of a standard cell the arrangement of the elements on the semiconductor substrate is determined for each cell. A plurality of CMOS cells 3 is provided. Each CMOS cell 3 comprises a 5V power wire 5 and a 0 V power wire, specifically, a ground wire 7, and a CMOS circuit 9, formed between the power wire 5 and the ground wire 7. A BiCMOS cell 11 comprises the power wire 15, the ground wire 17, and a CMOS circuit 13 formed between the power wire 5 and the ground wire 7. In addition to these, bipolar transistor circuits 14 are provided external to the power wire 15 and the ground wire 7. All the power wires 15 and the ground wires 17 are formed at the same height so that if the CMOS cells 3 and the BiCMOS cell 11 are lined up in a row as shown in the drawing, the power wires 5 and 15 and the ground wires 7 and 17 are all formed running in common. An interval between the adjacent cell rows is a wiring field to connect these cells. As can be clearly understood from the drawing, as compared to the case where the CMOS cells only are formed, only the part of the BiCMOS cell which extends outside of the power wires and the ground wires (a bipolar transistor circuits 14, 16) infringes on the area of the wiring field. However, the circuit actually occupied by the BiCMOS is only about 10 % of the total area, so this does not become a problem. A specific example of the adaptation of a gate array known as a sea of gate array to the present invention will now be explained. With this type of array, the elements are also formed in the wiring field 10. As known in Fig. 3, the CMOS and the bipolar transistor and the like take up the entire semiconductor substrate. Specifically, a row 21 in which an NMOS row 37, a PMOS row 39, a bipolar transistor, and a resistance are lined up in that order and methodically repeated is formed. A PMOS transistor P, an NMOS transistor N, a bipolar transistor B, and a resistance I are respectively shown in Fig. 3. The same reference numerals are used for the power wires, the CMOS cell, and the BiCMOS cell as in Fig. 2. This type of cell library is design in the case where bipolar transistors are used on the output part OUT of a logic circuit shown in Fig. 4 and Fig. 5. Fig. 6 shows a second embodiment of the present invention. Here, all the elements of a BiCMOS cell 23 are formed between a power wire 25 and a ground wire 27. In addition, a power wire 31 and a ground wire 33 are formed running completely on the outside of a CMOS cell 29. The power wire 25 can be connected to the power wire 31 and the ground wire 27 can be connected to the ground wire 33 by preparing a connecting cell 30 having two connecting wires 135 and 137. To obtain the same effect of the embodiment as shown in Fig. 6, connecting wires 135 and 137 for connecting the wires 25 and 27 in the CMOS cell to the wires 31 and 33 in the BiCMOS cell as shown in Fig. 7 can also be provided between the CMOS cell 29 and the BiCMOS cell 23 instead of the connecting cell 30 shown in Fig. 6. Accordingly, in this case also the CMOS cell library of the present invention can be used without modification. The preferred embodiments are explained in the foregoing discussion, but the present invention is not limited to these embodiments. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A method of making a semiconductor integrated circuit using a cell library, said method comprising the steps of: forming a CMOS cell (3) comprising: a first pair of power wires (5 and 7) separated from each other by a predetermined distance; and a CMOS circuit (9) selected from the cell library, positioned between the first pair of power wires (5 and 7); and forming a BiCMOS cell (11) comprising: a second pair of power wires (15 and 17) which are placed at a distance apart equal to said predetermined distance; a CMOS circuit (13) selected from the cell library, positioned between the second pair of power wires (15 and 17); and bipolar transistor circuits (14 and 16) selected from the cell library, positioned at both outsides of the second pair of power wires (15 and 17), the first pair of power wires (5 and 7) being connected to the second pair of power wires. A method according to claim 1, wherein an output portion of the BiCMOS cell (11) comprises a said bipolar transistor circuit (14 and 16). A method of making a semiconductor integrated circuit using a cell library, said method comprising the steps of: forming a CMOS cell (29) comprising: a first pair of power wires (25 and 27) separated from each other by a predetermined distance; and a CMOS circuit selected from the cell library, positioned between the first pair of power wires (25 and 27); and forming a BiCMOS cell (23) comprising: a second pair of power wires (31 and 33) which are placed at a distance apart greater than said predetermined distance; a CMOS circuit selected from the cell library, positioned between the second pair of power wires (31 and 33); and bipolar transistor circuits (14 and 16) selected from the cell library, positioned at both insides of the second pair of power wires (31 and 33), the first pair of power wires (25 and 27) being connected to the second pair of power wires (31 and 33). A method according to claim 3, wherein said first and second pair of power wires (25 and 27, 31 and 33) are connected by connecting wires (135 and 137) of a connecting cell (30).

Inventors: HARA HIROYUKI, SETA KATSUHIRO, HARA, HIROYUKI, SETA, KATSUHIRO
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: H01L27
IPC codes: H01L27, H01L21