Barrel shifter

Abstract: A barrel shifter comprises a plurality of shift selecting sections respectively connected in series to one another to form a plurality of stages, wherein each of the shift selecting sections includes a wiring network for shifting a reference data composed of a series of binary codes by a predetermined number of bits, and a data selecting circuit for receiving shifted data obtained from the wiring network and the reference data in parallel, selecting either of the two kinds of data and providing the selected data as a new reference data, and a data selecting circuit being at least one of the shift selecting sections has waveform shaping means for correcting the distortion of the potential waveform of the data which are selected and provided from the other data selecting circuit.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a barrel shifter in which the operating time can be greatly reduced and increase of the cell array area can be suppressed at the minimum value. 2. Description of the Background Art Recently, a barrel shifter in which data composed of a binary code series are received in parallel and provided in parallel after shifted at will by a desired number of bits has been utilized for an arithmetical unit for LSI (Large Scale Integration). The article by S.M. Kang, entitled "Domino-CMOS Barrel Switch for 32-Bit VLSI Processors", IEEE Circuits and Devices Magazine, Vol. 3, No. 3, May 1987, New York, US, pp. 3 to 8, describes a full-fledged CMOS 32-Bit barrel switch. With an extensive use of domino-CMOS circuits with undecoded control signals, a high-speed, area-efficient barrel switch was designed to shift or rotate 32-bit data to the left or right by any number of bit positions between 0 and 31. The barrel switch circuit disclosed therein comprises waveform shaping means for correcting the distortion of the potential waveform of the data. The waveform shaping means are implemented by using domino-CMOS circuits having similar inverters. Due to such an arrangement the waveform distortion of binary codes is reduced and the chip area is minimized. US-Patent No. 4,839,840 discloses a highly responsive barrel shifter. The barrel shifter for shifting an input data in response to each of shift signals, respectively, by a given shift count through a plurality of series-connected semiconductor switching elements arranged between an input terminal and an output terminal thereof, comprises means for precharging the output terminal to a supply voltage level before shifting an input data; and means for turning off a rearmost semiconductor switching element when the input data is at a high level, in order to output the precharged supply voltage through the output terminal as a high level shifted output data and for turning on the same rearmost semiconductor switching element when the input data is at a low level, in order to output a ground voltage from the same output terminal as a low level shifted output data, irrespective of a threshold voltage of the semiconductor switching element. Further, Patent Abstracts of Japan, Vol. 13, No. 436 (page-938), Sept. 29, 1989, entitled "Adder", is aimed to reduce a high speed pattern area by replacing the transmission gate part of an adder circuit with the buffer of a clocked inverter constitution, giving driving ability to the part, and making unnecessary an inverter for driving. Fig.1 shows a block diagram of a cell array section of a conventional barrel shifter having i stages (i is an integer satisfying 1 ≦ i). As shown in Fig.1, in the barrel shifter composed of i stages, a plurality of selectors 1 are arranged in parallel correspondingly to each bit of an input data formed of a binary code series of D1, D2, ··· , further interconnected in series so as to construct i stages. To each of the selectors 1, a corresponding binary code and another binary code different from the former binary code by a predetermined bit number are received, and one of these two codes is selected and provided in such a manner as described later. For example, a k-bit-shifting (k is an optional integer and satisfies 1 ≦ k) control signal for the m-th stage, an inverted-k-bit-shifting control signal obtained by inverting the k-bit-shifting signal, a reference code from a selector 1 of the (m+1)th stage located just above the selector 1 of the m-th stage in Fig.1 and a binary code (k-bit-shifted code) different from the reference code by k bits and given from a selector 1 which is located at the k-th position in the right direction from the selector 1 of the (m+1)th stage in Fig.1 and provides the reference code, are received to a selector 1 of the m-th (1 ≦ m ≦ i) stage. Moreover, the selector 1 of the m-th stage provides a binary code selected by its operation to a selector 1 of the (m-1)th stage located just below in Fig.1 and a selector 1 located at the j-th position (j is an optional number and satisfies 1 ≦ j) in the left direction from the selector 1 of the (m-1)th stage in Fig.1. To each of selectors 1 of the i-th stage located at the top stage in Fig.1, a corresponding binary code,that is, a reference code and another binary code different from the reference code by n bits, that is, an n-bit-shifted code are selectively received from the binary code series of D1, D2, ···. On the other hand, a binary code series of OUT1, OUT2, ···, provided from respective selectors 1 of the first stage located at the bottom stage in Fig.1, composes an output data. For example, as shown in Fig.2, the selector 1 of the m-th stage is composed of a transfer gate in which two N channel MOS type FET transistors (hereinafter called Nch) 2, 3 are connected in parallel. And the k-bit-shifted code is received to a source of the Nch2, while the k-bit-shifting control signal is received to a gate of the Nch2. On the other hand, the reference code is received to a source of the Nch3, while the inverted-k-bit-shifting control signal is received to a gate of the Nch3, In such construction of the selector 1, when the k-bit-shifting control signal is at the "H" level (for example, at a positive power-source potential), only a channel between the source and the drain of the Nch 2 to which the signal is received is turned on, so that the k-bit-shifted code is provided. To the contrary, when the k-bit shifting control signal is at the "L" level (for example, 0 potential), since the inverted-k-bit-shifting control signal is at the "H" level, only a channel between the source and the drain of the Nch 3 to which the inverted signal is received is turned on, so that the reference code is provided. Namely, the selector 1 selects and provides the k-bit-shifted code or the reference code under control of the k-bit-shifting control signal. Returning to Fig.1, the operation of a barrel shifter in which the selectors 1 operated in the above manner are respectively arrayed in series so as to construct i stages is explained. Each of selectors 1 of the i-th stage located at the top stage receives the reference code and the n-bit-shifted code which is different from the reference code by n bits in the binary code series of D1, D2, ···. In other words, the group of selectors 1 of the i-th stage receives a reference data composed of the binary code series of D1, D2, ··· and a n-bit-shifted data which is shifted by n bits from the reference data, Then, each selector 1 of the i-th stage selects the reference code or the n-bit-shifted code under control of the n-bit-shifting control signal or the inverted-n-bit-shifting control signal. In other words, since all of the selectors 1 of the i-th stage receive the same n-bit-shifting control signal and the same inverted-n-bit-shifting control signal, the group of selectors 1 selects either the reference data or the n-bit-shifted data. Then, each selector 1 of the i-th stage provides each selected binary code to each selector 1 of the (i-1)th stage located just below in Fig.1 and each of another selectors 1 located at the h-th position (h is an optional integer satisfying 1 ≦ h) in the left direction from the former selector 1 of the (i-1)th stage in Fig.1. Namely, each of the selectors 1 of the (i-1)th stage receives the binary code selected and provided from the selector 1 in the i-th stage just above in Fig.1 as a new reference code and another binary code provided from a selector 1 of the i-th stage located at the h-th position in the right direction from the former selector 1 of the i-th stage in Fig.1 as an h-bit-shifted code which is shifted from the reference code by h bits. In other words, the group of selectors 1 of the i-th stage provides a data selected by its operation as a new reference data and an h-bit-shifted data respectively shifted by h bits from the new reference data to the group of selectors 1 of the (i-1)th stage. In such a manner, each selector 1 of each stage selects either the received reference code or the k-bit-shifted code under control of the k-bit-shifted control signal and the inverted k-bit-shifted control signal, and provides the selected binary code as a now reference code to a selector 1 in the following stage and provides the same code as a j-bit-shifted code to another different selector from the former selector in the same following stage. In other words, each group of selectors 1 of each stage selects either the reference data or the shifted data shifted by on optional number of bits from the reference data, and provides the selected data and the shifted data shifted by on optional number of bits from the selected data to the following stage one after another. Moreover, the group of selectors 1 of the bottom stage provides the selected data composed of the binary code series of OUT1, OUT2, ··· as on output data. The output data coincides with the data obtained by shifting the input data composed of the binary code series of D1, D2, ··· by the total bit number defined by summing up each predetermined bit number shifted by every group of the selectors 1 in each stage. Accordingly, by using the above-mentioned construction in which the selectors 1 respectively composed of transfer gates of Nch are arranged in order in a matrix form, it becomes possible to form a barrel shifter having a compact shape and it is capable of shifting a data by a desired number of bits. As shown in Fig.3, it is possible to use a pass transistor as each selector 1 in place of the transfer gate shown in Fig.2. Namely, in such a pass transistor, P channel MOS type FET transistors (called Pch hereinafter) 4, 5 are respectively connected in parallel with the Nch 2, 3 to compose circuits 6, 7 which are connected in parallel to each other. In this case, since the pass transistor has the Pch in which the so-called back gate effect is not generated, when a binary code received to the selector 1 is at the "H" level (for example, a power-source potential), the electric potential of a code to be provided therefrom reaches the power-source potential so that the binary code can be transmitted rapidly and reliably. However, in such a barrel shifter as composed of selectors each of which uses the transfer gate or the pass transistor, when the number of stages of the selectors arranged in series is increased, the distortion of output codes becomes remarkable. As a result, the operating time of the barrel shifter is greatly increased and the processing speed of the input data is declined. For example, Fig.4a shows input/output waveforms when an edge signal is received from a pass transistor of the sixth stage in a barrel shifter composed of six stages. As shown in Fig.4a, the horizontal axis shows the elapsed time (nsec), and the vertical axis shows the voltage (volt) of output signals obtained in each stage. Moreover, a signal e1 designates an input edge signal, a signal e2 designates a signal provided from the pass transistor of the sixth stage in which the signal e1 is received. In other words the signal e2 designates an input signal to a pass transistor of the fifth stage. Similarly, a signal e3 designates an output signal from the pass transistor of the fifth stage. In other words, the signal e3 designates an input signal to a pass transistor of the fourth stage, and e4 designates an output signal from a pass transistor of the third stage.In other words, the signal e4 designates an input signal to a pass transistor of the second stage, moreover a signal e5 designates an output signal from a pass transistor of the first stage which is the final stage of the barrel shifter Each of the Nch has a channel length of 1µ m and a channel width of 3µ m, While each of the Pch has a channel length of 1µ m and a channel width of 5µ m. Moreover, the power source voltage is 4.5 volt. As shown in Fig.4a, the signal e1 rises up sharply. However, it is also seen from the same drawing that the each waveform of the signals is gradually distorted every time the signal passing through each stage. For example, as the logic criteria in this case, when the voltage set in the range from 0 to 2.5 volt is an "L" level, while the voltage set in the range from 2.5 to 4.5 volt is an "H" level, the input signal e1 which starts to rise up at t0 = 15nsec exceeds the voltage of 2.5 volt at t1 = 17nsec, while the output signal e5 exceeds the voltage of 2.5 volt at t5 = 26nsec. Accordingly, the operating time in the six stages of selectors is obtained as 9nsec defined by the value of t5 - t1. The reason why each signal waveform rises relatively sharp in the vicinity of 2.4 volt is because the Pch cause no back gate effect. Moreover, the reason why the waveform is gradually distorted is that each of the transistors respectively forming the selectors has an internal resistance, an internal electrostatic capacitance and a wiring capacitance. Hereinafter, the influence of the resistance and the capicitance is explained in detail with reference to Figs.5a and 5b. Fig.5a is an explanatory diagram to show a transmission route of a shifted data when the barrel shifter is composed of selectors using the pass transistors. For convenience, the same drawing shows a circuit in which only the circuits 7 in the circuits 6, 7 composing the series of selectors are connected in series. As shown in Fig.5a, in the circuit connecting selectors in series, shifting control signals S1, S2, ··· are respectively received to the gates of Pch 5, and the inverted signals IS1, IS2, ··· obtained by inverting the control signals are respectively received to the gates of Nch 3. In such a state, the binary code D1 is received to a source of a pair of Nch-Pch of the top stage in Fig.5a, then the binary code OUT1 is provided from a drain of the pair of Nch-Pch of the bottom stage in Fig.5a. From the viewpoint of the internal resistance, the internal electrostatic capacitance and the wiring capacitance, the circuit connecting selectors in series can be regarded as a circuit composed of RC circuits connected in series with each other as shown in Fig.5b. Accordingly, when the number of stages composed of selectors is increased, the delay time caused by the respective RC circuits is increased, so that the distortion of the output code OUT1 becomes considerably large. The improvement to optimize the size of the transistor and reduce the delay time has been tried. However, when the signal of the "H" level is transmitted rapidly, it is necessary to enlarge the size of the Pch transistor reasonably. Accordingly, though the optimization of size is possible to some extent, it is necessary to increase the area of the barrel shifter drastically on the whole. Moreover, to avoid the distortion of the binary code transmitted through the stages of the selectors, there is a known method in which for example, two stages of drivers 8 are inserted in the series of stages as shown in Fig.6 to shape the waveform of the binary code. However, when this method is used, since the layout area of the drivers 8 is required in the cell array section of the barrel shifter the method is inconsistent with reality. SUMMARY OF THE INVENTION The present invention was made to solve the problem of the prior art, and it is an object to provide a barrel shifter in which the operating time can be greatly reduced even when the number of stages of the selectors is increased, and the increase of the cell array area can be suppressed at the minimum value. To achieve the above object, the barrel shifter according to the present invention comprises a plurality of shift selecting sections respectively connected in series to one another to form a plurality of stages, each of the shift selecting sections including (a) a wiring network for shifting a reference data composed of a series of binary codes by a predetermined number of bits; and (b) a data selecting circuit for receiving shifted data obtained from the wiring network and the reference data in parallel respectively, selecting either of the two kinds of data and providing the selected data as a new reference data; in which a data selecting circuit of at least one of the shift selecting sections has waveform shaping means for correcting the distortion of the potential waveform of the data which are selected and provided from the other data selecting circuit; and wherein data received to the shift selecting section of the first stage are respectively shifted by a predetermined number of bits through each shift selecting section of the stages following the first stage one after another, and the resultant shifted data are provided in parallel from the shift selecting section of the final stage, characterized in that said waveform shaping means is composed by arranging a group of complex clocked inverters every bit of the input data, and each of the complex clocked inverters is constructed by connecting a first clocked inverter and a second clocked inverter in parallel, and each of the first and second clocked inverters is formed by connecting in series an N channel transistor connection section in which two N channel transistors are connected in series to each other with a P channel transistor connection in which two P channel transistors are connected in series to each other; and each complex clocked inverter inverts and drives either the reference data to be received to gates of the first clocked inverter or the shifted data to be received to gates of the second clock inverter, and provides codes having zero potential or the power-source potential from a node connecting between the N channel transistor connection section and the P channel connection section. Preferably, the waveform shaping means is composed by arranging a group of complex clocked inverters every bit of the input data, and each of the complex clocked inverters is constructed by connecting a first clocked inverter and a second clocked inverter in parallel, moreover each of the first and the second clocked inverter is formed by connecting in series an N channel transistor connection section in which two N channel transistors are connected in series to each other with a P channel transistor connection section in which two P channel transistors are connected in series to each other. Moreover, each complex clocked inverter inverts and drives either the reference data to be received to gates of the first clocked inverter or the shifted data to be received to gates of the second clocked inverter, and provides codes having zero potential or the power-source potential from a node connecting between the N channel transistor connection section and the P channel connection section. In the barrel shifter having the above-mentioned construction, each of the shift selecting sections obtains a shifted data by shifting the data received thereto as the reference data by a predetermined number of bits at the wiring network thereof, selects either the shifted data or the reference data and provides the selected data as a new reference data. Moreover, the shift selecting sections are connected in series to form a plurality of stages so that the reference data are successively received to the respective shift selecting sections. As a result, either the reference data or the shifted data obtained by shifting the reference data by a predetermined number of bits are provided. Namely, each stage of the shift selecting sections independently judges whether the input data are to be shifted or not, so that data shifted by a desirable number of bits is provided in parallel from the data shift section of the bottom stage. In the binary codes respectively composing the data to be transmitted through the array of the shift selecting sections, the distortion is caused by the internal resistance and the wiring capacitance of transistors constructing the respective data selecting circuits. Accordingly, when the number of serial stages of the shift selecting sections is increased, the processing time required for the binary codes to be changed between the "H" level and the "L" level is increased. This means that the processing speed for the input data is sharply declined in such a case. Therefore, the waveform shaping means formed by setting the group of the complex clocked inverters are provided in the middle of the series of stages of the shift selecting sections so as not only to select either the series of the binary codes composing the reference data or the series of the binary codes composing the shifted data and provide the selected binary codes, but also to shape each waveform of the binary codes by driving them to correct the distortion of the waveform. Accordingly, by using the group of the complex clocked inverters, it becomes possible to shape each waveform of the binary codes transmitting each shift selecting section without providing a special area for shaping separately. BRIEF DESCRIPTION OF THE DRAWINGS Figs.1 to 6 respectively show the prior art of a barrel shifter, wherein Fig.1 shows a block diagram of the hardware, Fig.2 is a circuit diagram of a selector composed of a transfer gate, Fig.3 is a circuit diagram of a selector composed of a pass transistor, Fig.4a shows waveforms respectively showing the change of an edge signal transmitted through pass transistors connected in series to form six stages, Fig.4b shows a serial six stages of selectors used for obtaining the waveforms shown in Fig.4a. Fig.5a is an explanatory diagram to show a state where a plurality of circuits 7 shown in Fig.3 are connected in series to form a plurality of stages, Fig.5b is an RC circuit diagram based on a respective internal resistance and a wiring capacitance of the pass transistors shown in Fig.5a, Fig.6 is an explanatory diagram to show a state where a plurality of drivers are inserted in a series of the pass transistors shown in Fig.5a, Figs.7 to 10 respectively show a barrel shifter related to one embodiment of the present invention, wherein Fig.7 is a circuit diagram of the hardware, Fig.8 is a circuit diagram of a complex clocked inverter, Fig.9 is an explanatory diagram to show the operation of the complex clocked inverter shown in Fig.8, and Fig.10a shows waveforms,as shown Fig.4a, to explain the improvement of the distortion of output codes when the complex clocked inverter shown in Fig.8 are used in the embodiment. Fig.10b shows a serial six stages of selectors used for obtaining the waveforms shown in Fig.10a. DESCRIPTION OF THE SPECIFIC EMBODIMENT Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. Fig.7 shows a block diagram of a cell array portion of a barrel shifter composed of i stages, which is related to one embodiment of the present invention. As shown in the drawing, the barrel shifter of i stages in this embodiment has the construction in which the selectors 1 of the second stage in the conventional barrel shifter shown in Fig.1 are replaced with a complex clocked inverter 9, and all the other selectors 1 are replaced with selectors 10 respectively composed of pass transistors. Fig.8 shows a circuit diagram of the complex clocked inverter 9. As shown in Fig.8, the complex clocked inverter 9 has the construction in which a source of an Nch connection section formed by connecting a source of an Nch 11 to a drain of an Nch 12 is connected in series to a drain of a Pch connection section formed by connecting a source of a Pch 13 to a drain of a Pch 14 so as to respectively form a first and second clocked inverters 15, 16 having in common an output node P1 respectively, moreover the first and second clocked inverters 15, 16 are connected to each other in parallel through the output node P1. In addition, the drains of the Nch 11 in the first and second clocked inverters 15, 16 are respectively grounded, and the sources of Pch 14 are respectively connected to the power source. In this case, a reference code is received to the respective gates of the Nch 12 and the Pch 13 in the first clocked inverter 15, while a 2-bit-shifted code is received to the respective gates of the Nch 12 and the Pch 13 in the second clocked inverter 16. Moreover, an inverted-2-bit-shifting control signal is received to the gate of the Nch 11 in the first clocked inverter 15 and the gate of the Pch 14 of the second clocked inverter 16, while a 2-bit-shifting control signal is received to the gate of the Pch 14 in the first clocked inverter 15 and the gate of the Nch 11 in the second clocked inverter 16. Furthermore, an output code as a new reference code is provided from the respective output nodes P1 of the first and second clocked inverters 15, 16. In such a construction, the operation of the complex clocked inverter 9 is explained with reference to Fig.9. As shown in Fig.9. when the 2-bit-shifting control signal is at the "H" level (a positive power-source potential), the inverted-2-bit-shifting control signal is at the "L" level (the zero potential), so that the Nch 11 and the Pch 14 in the first clocked inverter 15 are turned off. As a result, the output code from the first clocked inverter 15 is not determined. On the other hand, the Nch 11 and the Pch 14 in the second clocked inverter 16 are turned on. Thus, when the 2-bit-shifted code is changed from the "L" level to the "H" level, the Nch 12 in the second clocked inverter 16 is turned on while the Pch 13 therein is turned off. Namely, the potential level of the output node P1 of the second clocked inverter 16 becomes the zero potential rapidly, so that the output code is changed into the "L" level with the potential change of the node P1. Conversely, when the 2-bit-shifted code is changed from the "H" level to the "L" level the Nch 12 of the second clocked inverter 16 is turned off while the Pch 13 thereof is turned on. Namely, the potential level of the output node P1 of the second clocked inverter 16 changes to the power-source potential rapidly, so that the output code is rapidly changed into the "H" level with the potential change of the node P1. To the contrary, when the 2-bit-shifting control signal is at the "L" level, the inverted-2-bit-shifting control signal is at the "H" level, so that the Nch 11 and the Pch 14 in the first clocked inverter 15 are turned off. As a result, an output code from the second clocked inverter 16 is not determined. On the other hand, the Nch 11 and the Pch 14 in the first clocked inverter 15 are turned on. Thus, when the reference code is changed from the "L" level to the 'H" level, the Nch 12 in the first clocked inverter 15 is turned on while the Pch 13 therein is turned off. Namely, the output node P1 of the first clocked inverter 15 changes to the zero potential rapidly, so that the output code is changed into the "L" level rapidly. Conversely, when the reference code is changed from the "H" level to the "L" level, the Nch 12 in the second clocked inverter 16 is turned off while the Pch therein is turned on. Namely, the output node P1 of the first clocked inverter 15 changes to the power-source potential rapidly, so that the output code is changed into the "H" level rapidly. Accordingly, in such a complex clocked inverter 9, when the 2-bit-shifting control signal is at the "H" level, an output code having the potential level defined by inverting the potential level of the 2-bit-shifted code can be obtained. To the contrary, when the 2-bit-shifting control signal is at the "L" level, an output code having the potential level defined by inverting the reference code can be obtained. Moreover, the output code is rapidly changed into a potential level equal to the power-source voltage (corresponding to the "H" level) or the zero potential (corresponding to the "L" level). In other words, the complex clocked inverter 9 has a function for selecting and providing the 2-bit-shifted signal or the reference code under control of the 2-bit-shifting control signal in the same manner as described about the conventional selector 1 shown in Fig.2 or Fig.3. Besides, the complex clocked inverter 9 has not only an inverting function for providing the output code defined by inverting the input code but also a drive function for correcting the distortion of the waveform of the output code and determining the potential level thereof at the power-source potential or the zero potential. Therefore, in the barrel shifter of this embodiment in which the plurality of complex clocked inverters 9 are provided to form the second stage, in the same manner as in the conventional barrel shifter shown in Fig.1, the input data composed of a binary code series of D1, D2, ··· are shifted by a predetermined number of bits when a shifting control signal is at the "H" level in the selectors 10 or the complex clocked inverter 9. While, when the shifting control signal is at the "L" level, the input data are transmitted to lower stages without being shifted. Then, the selectors 10 of the first stage designated at the bottom in the drawing respectively provide a binary output code series of OUT1, OUT2, ···. In the binary code series transmitted from the i-th stage to the third stage, the waveform distortion is caused at each stage by the internal resistance and the internal electrostatic capacitance of the Nch and the Pch included in the selectors 10. The waveform distortion is corrected by the drive function of the complex clocked inverter 9 at the second stage, so that the potential level of the binary codes is rapidly changed, then these codes are transmitted to the pass transistors of the first stage. Fig.10a shows the operation for correcting the waveform distortion by the complex clocked inverter 9. In the example shown in Fig.10a, each change of waveforms of input/output signals is shown similarly to the waveforms as shown in Fig.4a. However, in this example, the pass transistors of the third and the fourth stage in the conventional pass-transistor group of serial six stages shown in Fig.4a, are respectively replaced with the complex clocked inverter 9. Namely, as shown in Fig.10b,a signal c6 shows an edge signal received to the pass transistor 10 of the sixth stage, a signal e7 shows an output signal from the pass transistor 10 of the sixth stage, a signal e8 shows an output signal from the pass transistor 10 of the fifth stage,that is, an input signal to the complex clocked inverter 9 of the fourth stage, s signal e9 shows an output signal from,the complex clocked inverter 9 of the third stage ,that is, an input signal to the pass transistor 10 of the second stage, and a signal e10 shows an output signal from the pass transistor 10 of the first stage which is the final stage. The channel length of the Nch used in the example is 1µ m and the channel width thereof is 3µ m, while the channel length of the Pch used in the example is 1µ m and the channel width thereof is 5µ m. Moreover, the power-source voltage is 4.5 volt. As clearly seen from the comparison with the conventional measurement data shown in Fig.4a, though the waveform of the signal e8 passing through the selectors of the sixth and the fifth stage is distorted, the waveform of the signal e9 passing through the complex clocked inverter 9 provided to the fourth and the third stages is sharply recovered, so that the operating time can be reduced so much. Namely, the input signal e7 which starts to rise up at t0=15nsec exceeds 2.5 volt at t1 = 17nsec, while the output signal e10 exceeds 2.5 volt at t10 = 23.5nsec. Thus, the operating time in the serial six stages of selectors can be reduced to a value of t10 - t1 = 6.5nsec. Accordingly, since the barrel shifter of i stages is provided with the complex clocked inverters 9 for correcting the waveform distortion in the binary codes at the second stage thereof, the logical level of the binary codes can be rapidly changed even when the number of serial stages of the selectors is increased. In other words further the operating time of the barrel shifter can be greatly reduced. On addition, similarly to each of the conventional selectors 1, since a suitable binary code can be selected from a plurality of binary input codes in each of the complex clocked inverter 9, the complex clocked inverter 9 composing the barrel shifter can be used in place of the conventional selectors 1. Also, the increase of the cell array area of the barrel shifter can be reduced to the minimum value. In the above construction of the barrel shifter according to the present invention, the selectors 10 respectively composed of pass transistors are connected to form many stages so as to select a desired binary code from a plural of binary codes. However, in place of the pass transistors, it is possible to use transfer gates in the same manner as shown in the conventional barrel shifter as far as the cell array portion can be formed in a small scale. However, in this case, it is thinkable that the processing speed of the data is lowered a little. Moreover, as described in the barrel shifter presenting the measurement data shown in Fig.10a, it is possible to replace a plurality of stages of the conventional barrel shifter with a plurality of the complex clocked inverters so as to suppress the delay time and enhance the data processing speed. In this case, since the output signal is not inverted on the basis of the input signal when the complex clocked inverters 9 are so arranged as to form an even number of stages, it is not necessary to provide a group of inverters still more. Thus, such a barrel shifter can be made at low cost in a relatively small scale.

Claims: Barrel shifter, comprising: a plurality of shift selecting sections respectively connected in series to one another to form a plurality of stages, each of the shift selecting sections including (a) a wiring network for shifting a reference data comprised of a series of binary codes by a predetermined number of bits; and (b) data selecting circuit (10) for receiving shifted data obtained from the wiring network and the reference data in parallel respectively, selecting either of the two kinds of data and providing the selected data as a new reference data, in which a data selecting circuit (10) of at least one of said shift selecting sections has waveform shaping means for correcting the distortion of the potential waveform of the data which are selected and provided from the other data selecting circuit; and wherein data received to the shift selecting section of the first stage are respectively shifted by a predetermined number of bits through each shift selecting section of the stages following the first stage one after another, and the resultant shifted data are provided in parallel from the shift selecting section of the final stage, characterized in that said wave form shaping means is composed by arranging a group of complex clocked inverters (9) every bit of the input data, and each of the complex clocked inverters (9) is constructed by connecting a first clocked inverter (15) and a second clocked inverter (16) in parallel, and each of the first and second clocked inverters (15, 16) is formed by connecting in series an N channel transistor connection section in which two N channel transistors are connected in series to each other with a P channel transistor connection in which two P channel transistors are connected in series to each other; and each complex clocked inverter (9) inverts and drives either the reference data to be received to gates of the first clocked inverter (15) or the shifted data to be received to gates of the second clocked inverter (16), and provides codes having zero potential or the power-source potential from a node connecting between the N channel transistor connection section and the P channel connection section.

Inventors: OMOTE KAZUYUKI, OMOTE, KAZUYUKI
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1991
Main classification: G06F5
IPC codes: G06F5, G06F7