Device for estimating the carrier frequency of a digital signal

Abstract: The present invention relates to a method of estimating the carrier frequency of a digital signal, in which method two estimates of the carrier phase are carried out in successive instants and the estimated carrier frequency is obtained from the comparison of the above two estimates. The invention concerns also a device using an estimator (22) for estimating phases of said carrier at successive instants, a circuit (24) for storing the estimates and a circuit (27) for comparing two successive estimates. In an embodiment, both the phase estimator and the comparison circuit are implemented through multipliers and adders.

Description: The present invention relates to a device for estimating the carrier frequency of a digital signal, in particular a QAM or PSK modulated signal. At present, in digital transmission systems, various estimators for the carrier frequency are used. Said estimators have the common feature of correctly operating only when the power spectral density associated with signaling has even symmetry with respect to the carrier frequency. Such feature is due to the fact that all known estimators make an estimate of the spectrum centroid. When the spectrum is non-symmetrical, its centroid does not coincide with the carrier frequency, and conventional systems make an uncorrect estimate therefore. In radio link transmissions, unfavorable propagation phenomena, in particular the so-called "selective fading", cause dissymmetries in the spectrum, these making conventional estimators unusable. The conventional technique used in radio links consists in generating an estimate of the carrier that changes periodically in the frequency intervall to which the signal carrier a priori is supposed to belong. When the estimated carrier frequency is equal to the signal carrier frequency, a suitable detector indicates correctness of the estimate and interrupts the periodic variation of the estimate. Such technique presents the problem of realising such detector; moreover, in conventional systems, in order to obtain a satisfactory operation of said detector, it is necessary to keep low the rate in the estimate variation, thus slowing down the process of recognizing the signal carrier frequency. EP-A-0 373 802 discloses a device for estimating a signal frequency in accordance with the first part of claim 1. There, instantaneous signal phase values are obtained at a succession of time intervals by a process known as "phase unwrapping", and the gradient of a straight line which would best pass through a plot of such values against time is determined as an estimate of the signal frequency. A first object of the invention is to provide a device of estimating the carrier frequency which is unaffected by dissymmetries in the signal power spectral density. Another object is to provide a circuitry that is simple and effective for implementing such a method. According to the invention, at each signaling interval (time distance of two successive transmitted data), a phase estimate for said carrier and a comparison between two successive estimates are made. Said comparison, suitably filtered, provides a control signal to be fed to the circuit which generates the estimated carrier. It has been found, inter alia, that unaffectedness against dissymmetries in the signal power spectral density is advantageous in radio link connections, since it involves a simplification of the circuitry and an increase in the rate of recognition of the signal carrier frequency. The solution of the invention is based upon the estimate of phase ϕ k in the kth signaling interval. If is the received complex signal at the kth signaling interval, it may be expressed by equation (I): where ã k is the complex data transmitted at the kth signaling interval and is the complex disturbance overlapped to the data and including noise, interference from other transmissions and intersymbolic interference. If ã k is the complex data estimated by the receiver at , an estimate of the term e jϕ k, designated with is obtainable through equation (II): where ã and k * denotes the complex conjugate of the estimated data ã and k According to the invention, the estimate is stored whilst the phase estimator goes on in producing the estimate relative to the successive signaling intervals. After N signaling intervals, the estimate will also be available. Since the carrier frequency is defined as the derivative of the carrier phase with respect to time, an approximation of said frequency is obtainable by determining the difference between two phases extracted at successive times. Operatively such difference is realized by multiplying the term relative to the (k+N)th interval with the complex conjugate of the term relative to the kth interval and taking only the imaginary part of the product as indicated in equation (III): where f and k+N denotes the frequency estimate at the (k+N)th interval whilst Im denotes the imaginary part. The process of the f and k+N estimate processing is synthetically illustrated in the schematic block diagramm of fig. 1. In said figure there are shown: a phase estimator device 22; at signaling instant k+N, said estimator 22 has at its inputs the received complex signal (line 20) and the complex data ã and k+N locally estimated e.g. in a decision circuit 30 of the receiver (line 21), and it provides the output signal (line 23) by operating in accordance with equation II (referred to signaling instant k+N); a storage device 24 which receives the phase estimate at its input (line 25), buffers the same, and provides at its output the estimate processed by phase estimator at the previous signaling instant k (line (26); and a comparison device 27 which receives at its input two estimates (line 26) and (line 28) and outputs the frequency estimate f and k+N (line 29) by operating in accordance with equation III. The frequency estimate obtained according to the invention on line 29 is applied to conventional circuitry of the receiver comprising substantially a filter 32, a generator 34 (VCO) connected to said filter via a line 33 and generating the estimated carrier, and a demodulator 36 (DEM) receiving said estimated carrier signal via a line 35. In a particularly advantageous embodiment of the invention, the device according to the invention comprises: four multipliers and two adders for carrying out the complex product generating process indicated by equation II; and a storage circuit, two multipliers and an adder for carrying out the operation indicated in equation III. The various aspects an advantages of the invention will be more apparent from the description of an embodiment thereof illustrated as a not limitative example in the attached drawing (Fig. 2). Signals c k+N,p and c k+N,q represent respectively the real (or in phase) part and the imaginary (or in quadrature) part of the complex signal Blocks 4, 5, 14 and 4', 5', 14' marked with X represent multiplier circuits; blocks 8, 8', 18 marked with + represent adder circuits; blocks 12, 12' marked with memory represent memory banks designed to produce a delay of N signaling intervals; and block 16 marked with sign inverter represents a sign change. As it can be seen in the figure, signals c k+N,p and c k+N,q go through analogous processes respectively marked by numerals with apostrophe and numerals without apostrophe. Signal c k+N,p is applied to line 1 and is then fed through lines 2 and 3 respectively to multipliers 4 and 5. Fed to the input of multiplier 4 is also the signal â k+N,p which represents the real (or in phase) part of the complex signal ã and k+N . Fed to the input of multiplier 4 is also the signal â k+N,q which represents the imaginary (or in quadrature) part of the complex signal ã and k+N. Similarly, signal c k+N,q is applied to line 1' and is then fed through lines 2' and 3' respectively to multipliers 4' and 5'. Fed to the input of multiplier 4' is also the signal â k+N,p whilst signal â k+N,q with its sign reversed is fed to the input of multiplier 5'. The output signals of multipliers 5 and 4' are fed to the inputs of adder 8 through lines 6 and 7', respectively. The output signals of multipliers 5 and 4' are fed to the inputs of adder 8' through lines 7 and 6', respectively. The output signal of adder 8 is applied via line 9 and then lines 10 and 11 simultaneously to delay blocks 12 (through line 10) and to multiplier 14' (through line 11). Similarly, the output signal of adder 8' is simultaneously fed via line 9' and then lines 10' and 11' to delay block 12' (through line 10') and to multiplier 14 (through line 11'). The outputs signals of delay blocks 12 and 12' are fed respectively to multipliers 14 and 14' through lines 13 and 13'. Through line 15, the output signal of multiplier 14 is fed to sign change block 16 whose output is fed to adder 8 through line 17. Through line 15', the output signal of multiplier 14' is fed to adder 18. The output signal of adder 18 is the frequency estimate f and k+N and is outputted through line 19. All the elements of the circuit in Fig. 1 are realisable by using components available on the market, such as MOS, HCMOS logic, analog circuits, and so on. These realisations will suggest themselves to those of skill in this art.

Claims: A device for estimating the carrier frequency of a digital signal in modulation transmission, particularly QAM or PSK transmission, including means for obtaining values of the instantaneous signal phase at subsequent instances and means for forming differences between the phase values thus obtained, characterised in that said means for obtaining signal phase values includes a first circuit (22) for estimating the signal phase at two instances k and (k+N) in accordance with the equations and wherein is the composite complex signal, comprising complex signal data and noise, at the k-th instant, ã and k* is the complex conjugate of the signal data at the k-th instant, is the composite complex signal, comprising complex signal data and noise, at the (k+N)-th instant, and ã and k+N* is the complex conjugate of the signal data at the (k+N)-th instant, that a second circuit (24) is provided for storing the estimates of the signal phase obtained at the k-th instant, and that said difference forming means includes a circuit (27) for calculating the difference between the phase estimate obtained at the (k+N)-th instant and the estimate stored in the second circuit (24) in accordance with the equation wherein f and k+N is an estimate of the carrier frequency of the signal at the (k+N)-th instant and Im is the imaginary part of the product The device of claim 1, wherein said first circuit (22) includes a first multiplier (4) for multiplying the real part of with the real part of ã and k+N* to generate a first product, a second multiplier (5) for multiplying the real part of with the imaginary part of ã and k+N* to generate a second product, a third multiplier (4') for multiplying the imaginary part of with the real part of ã and k+N* to generate a third product, a fourth multiplier (5') for multiplying the imaginary part of with the imaginary part of ã and k+N* to generate a fourth product, a first adder (8) for adding the first and fourth products, and a second adder (8') for adding the second and third products. The device of claime 2, wherein the second circuit (24) includes a first memory (12) connected to the output of the first adder (8) and a second memory (12') connected to the output of the second adder (8'). The device of claim 3, wherein said circuit (27) for calculating the difference includes a fifth multiplier (14) for multiplying the output of the first memory (12) with that of the second adder (8'), a sixth multiplier (14') for multiplying the output of the second memory (12') with that of the first adder (8), a sign inverter (16) for inverting the output of the fifth multiplier (14), and a third adder (18) for adding the output of the sign inverter (16) and that of the sixth multiplier (14').

Inventors: GUGLIELMI FRANCO, SPALVIERI ARNALDO, GUGLIELMI, FRANCO, SPALVIERI, ARNALDO
Applicants: ALCATEL ITALIA, ALCATEL ITALIA S.P.A.
Application year: 1991
Main classification: G01R23
IPC codes: H04L27, G01R23