METHOD AND APPARATUS FOR IMPROVING VERTICAL SHARPNESS OF PICTURE TUBES

Abstract: Large format TV tubes must produce a high peak brightness in order to be acceptable to the user. This results in a large beam current in bright areas of the picture and in a subsequent defocussing of the resulting spot on the display and in a loss of the sharpness of vertical and horizontal transitions. The apparent sharpness of a vertical transition is gained by modifying the deflection of the TV receiver such that, at vertical transitions, the line on the bright side of the transition is deflected away from the transition region. Advantageously the amount of vertical scan modulation corresponds to a multi-level control signal and depends on the grey levels of the transition.

Description: Method and apparatus for improving vertical sharpness of pic¬ ture tubes The present invention relates to a method and an apparatus for improving vertical sharpness of images displayed on pic¬ ture tubes. Background Large format TV tubes must produce a high peak brightness in order to be acceptable to the user. This results in a large beam current in bright areas of the picture and in a subse¬ quent defocussing of the resulting spot on the display. Fig. 1 illustrates this effect. The horizontal axis 10 scales the vertical line distances and the vertical axis scales the brightness amplitude. A high brightness spot 12 has a signif¬ icantly increased diameter compared to a low brightness spot 13. The sharpness of a transition between bright and dark areas is therefore impaired due to an overlapping of the bright spot 22 into a dark region as shown in Fig. 2. The dashed line 25 shows the overall response and the hatched area is a region of impairment 24, whereby line 26 marks the position of the edge in the picture. Invention It is an object of the invention to improve the apparent ver¬ tical sharpness in transitions between bright and dark pic- tui-e areas when displayed on TV tubes. This object will be reached by the features of claim 1. Ad¬ vantageous additional embodiments are described in the sub- cLaims. A picture improvement method using a modified vertical def¬ lection is described in the article "Line Flicker Reduction by Adaptive Adjustment of Vertical Deflection in TV Recei¬ vers", H.A. Petersen, H.D. Bach, R. Nielsen, IEEE 1990 ICCE Proceedings, FA 17.3, June 1990. Apparent line flicker is reduced by adaptive adjustment of the vertical deflection. But sharpness impairments caused by varying dot sizes are not eliminated. An improvement in the apparent sharpness of a vertical tran¬ sition may be gained by modifying the vertical deflection of a TV receiver such that, at vertical transitions, the line on the bright side of the transition is deflected away from the transition region as shown in Fig. 3. This additional deflection may be provided by means of an additional amplifi¬ er and deflection coil on the TV tube. The amount of deflec¬ tion illustrated in Fig. 3 is of the order of one scan line, but may be less depending upon the characteristics of the display tube. The amount of deflection may also be varied depending upon the characteristics of the video signal, but primarily additional deflections are carried out with a fixed distance either up or down. Drawings Preferred embodiments of the invention will now be described with reference to the accompanying drawings, in which: is a different-amplitude spot profile; shows edge blurring caused by a high brightness spot; shows the edge when using the scan modulation according to the invention; is an example of a vertical cross section of a TV signal; Fig. 5 is a block diagram of a control signal genera¬ tor; shows waveforms associated with Fig. 5; is an alternative implementation using one full and one 1-bit line delay; shows the principle modifications for 4-(or greater-) level comparisons; shows a block diagram of an improved control signal generator. Preferred embodiments Due to the additional vertical deflection in Fig. 3 the spot 22 in Fig. 2 has now the same location as spot 27 in Fig. 2, so that in Fig. 3 there is only one high brightness dot 32. Superimposing of the both dots results in a higher overall response 35 at this line. The brightness gradient at the edge has increased. A dashed line 36 again marks the edge position. This method also improves picture quality if the field fre¬ quency is higher than 50 or 60 Hz. An example of a vertical cross-section through an image is shown in Figure 4. Each line and point represents the ampli¬ tude of the video signal at one pixel on each line 1 - 14 of the cross-section. It can be seen that in order to improve the display the scan on lines 3, 7, and 9 should be deflect¬ ed in the direction indicated by the arrows. Transitions al¬ so exist at lines 11 and 13, but as this represents a high vertical frequency, no improvement can can be made by modify¬ ing the scan, and so the lines should remain undeflected. A block diagram of a system to implement this processing is shown in Fig. 5. The incoming video signal 50 is passed through two line de¬ lays 511 and 512 to give access to the line following (at the input of the first line delay 511) and to the line pre¬ ceding the current line. The line preceding is available at the output of the second line delay 512 and the current line is available at the output of the first line delay 511. Differences are formed between the current line and the fol¬ lowing line and between the current line and the previous line. These differences are then passed to a first compara¬ tor 521 and to a second comparator 522, respectively, where they are thresholded and converted to binary signals A and B. Then they are combined in a logic circuit 53 to form an output control signal C. The video signal at the output of the first line delay 511 is fed to an amplifier or multiplier 54, respectively. The gain of this amplifier 54 is controlled by signal C. If C is "0", the gain of amplifier 54 is 1.0, if C is not "0", the gain is about 0.9 in order to reduce the brightness at its output 55. Signal C is also directed to a deflection circuit 56 which supplies a vertical deflection coil 57. Figure 6 shows the values of the signals through the process¬ ing for the example cross-section of Figure 4, at the point when this signal 61 appears at the output of the first line delay 511. Signal 63 at the input of the first line delay 511 and and signal 62 at the output of the second line delay 512 appear one line later and earlier, respectively. The dif¬ ference signals 64 and 65 after thresholding appear at points A and B. It can be seen that point A indicates a signal 66 of lines which should be shifted upwards and point B indicates a sig¬ nal 67 of lines which should be shifted downwards. Both sig¬ nals 66 and 67 indicate the same lines in the area of high detail. To provide a control signal output, the signals 66 and 67 are applied to a look-up table in logic circuit 53. The output of this circuit is +1 if only signal A is active or -1 if only signal B is active. If both signals A and B are "0" (no edge detected), or both "1" (a single bright line), the output is "0" as no improvement can be made by modifying the deflection. An alternative implementation using only one full resolution video line delay 711 is shown in Figure 7. In this implemen¬ tation the signals 70, 75, A, B, C and the circuits 711, 721, 722, 73, 74, 76 and the coil 77 correspond to the sig¬ nals 50, 55, A, B, C, and the circuits 511, 521, 522, 53, 54, 56, and the coil 57 in Figure 5. An unity gain inverting amplifier 78 is added, but the line delay 712 has only 1-bit resolution. The 1-bit control sig¬ nal at the output of the second comparator 722, correspond¬ ing to signal A in Figure 5, is delayed by one line before being applied to the lookup table within logic circuit 73. When the control signal C deflects the scanning beam, this results in perceivable increase in brightness on the display for the part of the image for which the original and deflect¬ ed parts of scan lines overlap. For both implementations, a reduction of the amplitude of the video signal within switched gain amplifier 54, 74 may be made when the control signal C is active. If the reduction in brightness is too great, visible edge busyness results along contours near the threshold. A value of about 0.9 appears to provide a good compromise between edge busyness and a suitably reduced in¬ crease in brightness of the overlapping parts of the scan. At the expense of greater hardware complexity in the line delays and decision circuitry, the control signal C can be made to have an amplitude depending on the video contour. Then the output of the comparators 521, 721, 522, 722 is a multi-level signal, which is applied to the logic circuit 53, 73. An example transfer characteristic of a 4-level comparator is shown in Figure 8a. Obviously, the 1-bit line delay 712 in Figure 7 now requires the number of bits neces¬ sary to represent the comparator output. The look-up table in logic circuit 53, 73 is now expanded and is shown in tabu- lar form in Figure 8b. To illustrate the principle, compara¬ tor outputs with 2-bit resolution are shown. Essentially, the control signal C increases in proportion with the comparator's values for the case of a single edge. In the case of high frequency detail (output from both comparators at A and B) the control signal is inhibited in the normal way. Control signal C can also be obtained by using the informa¬ tion available during a field rate upconversion process. Fig. 9 depicts a block diagram on basis of the block diagram of Fig. 5. Incoming video signal 90, line delays 911 and 912, comparators 921 and 922, logic circuit 93, amplifier 94, deflection circuit 96 and deflection coil 97 respect the corresponding ,circuits and signals of Fig. 5. The output control signal C generated in logic circuit 93 is fed also to a second logic circuit 98 and to staircase cir¬ cuit 99. Deflection circuit 96 is not controlled by output control signal C but by the according output signal OUT of staircase circuit 99. The inputs of comparators 922 and 921, respectively, are connected to the inputs INI and IN2, re¬ spectively, of second logic circuit 98. The output of this circuit is either the signal at input INI or at input IN2 or at input IN3 (= 0) and is fed with relation to output con¬ trol signal C to input IN of staircase circuit 99. The out¬ put of second line delay 912 is fed to a third comparator 981 and input video signal 90 is fed to a fourth comparator 982. The second input of each of these comparators is con¬ nected to a voltage INGREY. The output signals of these comparators are inputted to an AND circuit 983 which is con¬ nected to a switch 984. The output signal of switch 984 is also fed to staircase circuit 99. The applied additional vertical deflection (of ±1 line) may destroy the equally spaced scanning grid and introduces holes at the darker side of a transition after the postfil- tering by the beam current. Obviously these holes remain unvisible if at the darker side of the edge the beam current remains nearly zero. But for grey levels the holes coming up may be annoying. This effect becomes even more disturbing if the vertical transition extends not over one but two lines as it is the case after a vertical upconversion by an inter¬ polating filter. With an interpolated value halfway between the value of both sides of the edge corresponds a smaller cross section of the electron beam and therefore less over¬ lapping with the adjacent lines. Therefore in case of vertical transitions between grey and white levels the deflection amplitude will be reduced. Al¬ though the holes cannot be avoided a good compromise between edge enhancement and artefacts can be achieved with a cir¬ cuit according to Fig. 9. Depending on the actual values of output control signal C, of the signal at input IN and the output signal of switch 984 different staircase functions are generated within staircase circuit 99. The signal at input IN represents the transition amplitude. When this amplitude increases continuously the signal at out¬ put OUT will increase stepwise if C > 0 or C < 0. If one or both input signals of the third and the fourth comparators 981 and 982 are less than voltage level MINGREY the output signal of switch 984 will be zero, i.e. graph 'DIV = 0' in staircase circuit 99 is valid. If both compa¬ rator input signals are greater than MINGREY the output of AND circuit 983 will go high and switch 984 passes a divid¬ ing value DIV > 0 to staircase circuit 99. According to val¬ ue DIV the slope of the generated staircase function is changed. Six different graphs (one half of each graph, the graphs are symmetrical to axis OUT = 0) corresponding to val¬ ue DIV are shown in Fig. 9. If DIV > 6, the signal at output OUT is zero regardless of the level at input IN. Preferred values are: MINGREY = 160 ... 200 within the full range 0 ... 255 (8 bit) of video signal 90 DIV = 2 For improving noise immunity with respect to output control signal C this signal can be a multilevel control signal of at least three bit resolution in conjunction with an horizon¬ tal low pass filter. Thereby 'busy edges' are avoided. The line delays, comparators, logic circuits and the staircase circuit are then made matching for such higher resolution. In order to also avoid an additional deflection in uniform picture parts, which can happen due to transients of a usual lowpass filter after the electron beam has passed a horizon¬ tal edge, an edge preserving filter, e.g. a median filter, is applied (not depicted) .

Claims: Claims 1. Method for improving vertical sharpness of pictures dis¬ played with a line structure on a picture tube, charac¬ terized in that the beam of said tube is deflected in vertical direction in relation to vertical bright-ness transitions. 2. Method according to claim 1, characterized in that said deflection in vertical direction is composed of a known vertical deflection and an additional vertical deflec¬ tion. 3. Method according to claim 2, characterized in that said additional vertical deflection is such that within bright areas (22) at vertical brightness transitions the beam is deflected away to the bright side of said transition region. 4. Method according to claim 3, characterized in that said additional vertical deflection is active if said bright area has a height of more than one line. 5. Method according to any of claims 2 to 4, characterized in that the amount of said additional vertical deflec¬ tion relates to the slope of said transition. 6. Method according to any of claims 2 to 5, characterized in that the amount of said additional vertical deflec¬ tion relates to the grey levels of said transition. 7. Method according to any of claims 2 to 6, characterized in that the amount of said additional vertical deflec¬ tion is a staircase function relating to the grey lev¬ els of said transition. 8. Apparatus using a method according to any of claims 1 to 7, characterized in that said apparatus comprises two or more line delays (511, 512, 711, 712, 911, 912) which are followed by two or more comparators (521, 522, 721, 722, 921, 922), forming binary output signals (A, B), combining said output signals in one or more logic circuits (53, 73, 93, 98) which forms a control signal (C) consisting of at minimum three levels and using said control signal for generating said addition¬ al vertical deflection and for reducing the amplitude of said brightness signal in a multiplier (54, 74, 94). 9. Apparatus according to claim 8, characterized in that one (712) of said two or more line delays (711, 712) is located between one (722) of said comparators (721, 722) and one of said logic circuits (73). 10. Apparatus according to claim 8 or 9, characterized in that said comparators (521, 522, 721, 722, 921, 922) generate said output signals (A, B) with more than two levels and that said logic circuit (53, 63) accordingly generates said control signal (C) with more than three levels. 11. Apparatus according to any of claims 8 to 10, characte¬ rized in that said control signal (C) is fed to a stair¬ case circuit (99) wherein said control signal is changed corresponding to the grey levels of said transi¬ tion.

Inventors: BOIE WERNER, BOLENDER NADINE, HACKETT ANDREW DENYS, BOIE, WERNER, BOLENDER, NADINE, HACKETT, ANDREW, DENYS
Applicants: THOMSON CONSUMER ELECTRONICS, THOMSON CONSUMER ELECTRONICS S.A.
Application year: 1991
Main classification: H04N3
IPC codes: H04N3