Pattern forming system

Abstract: There is provided a pattern forming system of the present invention comprising a reticule (26) on which a pattern is formed corresponding to one or more chips, an apparatus for preliminarily arranging a plurality of shot regions on a main surface of a wafer (28) in a matrix manner in a case where regions where the pattern is formed by one shot are used as shot regions, an apparatus for calculating the number of the shot regions, which constitutes the matrix after sequentially moving the position of the shot regions to be a center of the matrix in a state that wafer is fixed, and the number of the chips wherein the pattern is completely formed in the main surface of the wafer, an apparatus for selecting a case in which the number of the shot regions constituting the matrix is the smallest and the number of the chips in which the pattern is completely formed in the main surface of the wafer is the largest, and an apparatus for forming the pattern, which is formed on the reticule, on each shot region constituting the matrix.

Description: The present invention relates to a pattern forming system for maximising the number of shot regions to be completely formed on the main surface of a wafer. Such a system will be described hereinbelow with reference to Figures 1 to 4. An embodiment of the invention will be described in which a pattern formed on a reticule is demagnified and projected onto the surface of a wafer by a step-and repeat phototlithographic system with demagnification (hereinafter called stepper). A pattern forming system (for use in manufacturing plural semi-conductor chips from a single wafer) is disclosed in US-A-45 30 587. The system comprises: means for exposing a main surface of a wafer step-wise to a single shot region formed by a pattern formed on a reticule, so as to cover said main surface of the wafer progressively according to a particular arrangement of successive shot regions, where shot regions are completely formed on said main surface of the wafer and other are not, each completely formed shot region having a plurality of chip regions, the particular arrangement including a basic shot region positioned proximate the centre of the matrix arrangement wherein the basic shot region has a central point; calculating means for calculating the number of the shot regions which constitute said matrix arrangement by repeatedly operating the exposing means according to further arrangements of the shot regions on the main surface of the wafer so that the central point of the basic shot region for the several arrangements have different positions in a two-dimensional coordinate system comprised of a X axis and a Y axis having an origin defined at a centre of the wafer; said calculating means being for further calculating a number of chip regions to be completely formed on said main surface of said wafer for each shot region arrangement ; selecting means for selecting that shot region arrangement in which the time required for forming the shot regions constituting said shot region arrangement is smallest and the number of chip regions to be completely formed on said main surface of said wafer is largest; and forming means for forming said pattern, which is formed on said reticule, on the main surface of the wafer for each shot region of the selected shot region arrangement. Conventionally, where a pattern formed on a reticule is demagnified and projected on the surface of a wafer, the pattern formed on the reticule is formed on the surface of the wafer in one shot. Generally, a plurality of shots can be performed on one wafer, and a plurality of identical patterns are formed on the surface of the wafer in a matrix manner. As a method for forming the plurality of identical patterns on the entire surface of the wafer by a plurality of shots, the following four cases can be considered as shown in Table 1. Array Method X Direction Even Number Even Number Odd Number Odd Number Y Direction Even Number Odd Number Even Number Odd Number Fig. 7 Fig. 8 Fig. 9 Fig. 10 The above four cases can be considered based on a two-dimensional coordinate system in the surface of the wafer. As shown in Fig. 1, the first case relates to shot regions 1 to 38, and shows an even number of shot regions in which the patterns formed on the reticule exist in the respective X and Y directions from an origin of the coordinate axes. As shown in Fig. 2, the second case relates to shot regions 1 to 40 and shows an even number of shot regions in the X direction and an odd number of shot regions in the Y direction. As shown in Fig. 3, the third case relates to shot regions 1 to 39, and shows an odd number of shot regions in the X direction and an even number of shot regions in the Y direction. As shown in Fig. 4, the fourth case relates to shot regions 1 to 37, and shows an odd number of shot regions in the respective X and Y directions. In the mentioned cases, assuming that, for example, the diameter of the wafer is 5 inches andthesize of one shot region is 15 mm × 15 mm, the number of complete patterns to be formed in the wafer will be 38 according to the first case of Fig. 1, 40 according to the second case of Fig. 2, 39 according to the third case of Fig. 3, and 37 according to the fourth case of Fig. 4. Therefore, if the pattern to be formed by one shot constitutes one integrated circuit (IC), the maximum number of IC to be obtained from one wafer can be obtained with the array of shot regions shown in Fig. 2. In other words, if the pattern on the reticule is formed on the surface of the wafer by using the array of the shot regions shown in Fig. 2, the maximum number of ICs can be obtained from one wafer, and efficiency of IC production can be improved. Where the pattern formed on the reticule is actually formed on the surface of the wafer, it is necessary to choose the case in which the maximum number of ICs can be obtained from one wafer. In this case, conventionally, workers must actually count the number of ICs to be obtained from one wafer in each case in order to select the case in which the maximum number of ICs can be obtained. However, if the IC size is reduced, and the number of ICs to be obtained from one wafer is increased, counting the number of ICs is extremely difficult for the workers. Fig. 5 shows the relationship between the size of the chip and the chip gross relating to an experimental value and a theoretical value. The theoretical value shown by the broken line of Fig. 5 is a number obtained by dividing the main surface area of the wafer by the area of one IC. The chip gross shown by the solid line in Fig. 5 is the number of ICs actually formed on the main surface of the wafer in a complete shape if the patterns are formed on the surface of the wafer by a predetermined array method. In other words, if the size of the IC is 3 mm × 3 mm, both the experimental value of the chip gross and the theoretical value are about 1300, respectively. Due to this, it is impossible for workers to count the number of ICs formed on the surface of the wafer one by one. An object of the invention is to provide a pattern forming system wherein a pattern formed on a reticule, is demagnified and projected on a surface of a wafer according to an array method in which the number of shots is minimized and the number of ICs to be formed on the surface of the wafer is automatically selected while demagnifying and projecting the pattern thereon. According to the invention, there is provided a pattern forming system according to claim 1. An application of the invention is where the apparatus is used for exposing photoresist formed on the wafer in a step and repeat system. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figs. 1 to 4 are plan views of a wafer showing one of the conventional array methods; Fig. 5 is a view showing the relationship between a chip gross and a chip size; Figs. 6 to 8 are plan views showing the wafer on which a pattern on a reticule is formed by the pattern forming system of the present invention; Fig. 9 is a block diagram showing the pattern forming system relating to an embodiment of the present invention; Fig. 10 is a view showing the relationship of the scattering between the chip size and the chip gross; and Fig. 11 is a plan view showing a wafer on which the pattern on the reticule is formed by the pattern forming system of the present invention. The pattern forming system relating to an embodiment of the present invention will be explained with reference to the drawings. In the above description of the related art, it was explained that four cases can be considered to expose photoresist formed on the wafer in the step and repeat system. In the case where a plurality of identical patterns are formed on the surface of the wafer in a matrix manner, the array method of the regions (shot regions) where one pattern is formed is not limited to the above-mentioned four cases. In other words, the present invention provides a apparatus for automatically determining an array method of completely and incompletely formed shot regions wherein the number of times of demagnifying and projecting the pattern of the surface of the wafer is minimised and the number of ICs to be formed on one wafer is maximised. With reference to Figs. 6 to 9, there will be explained the method for forming the maximum number of ICs on the surface of one wafer, the method for calculating the shot gross and the chip gross where a plural it of identical patterns is formed on the surface of the waf in a matrix manner. First, a wafer size WS is selected from any one of 3, 4, 5, or 6 inches. Thecenter of the wafer (shown by a mark x in Figs. 6 to 8) is determined, and defined as an origin O. Then, an X axis and an Y axis being at right angles-to the X axis are determined based on the origin O, thereby defining a two-dimensional coordinate system. Next, the shot size S and chip size CS will be explained. The shot size S means a size of one pattern (shot region) to be formed on the surface of the wafer by one shot. The chip size CS means size of the region to be as one chip formed on the surface of the wafer. In other words, it is possible that a plurality of chip patterns are formed on the surface of the wafer by one shot, or it is possible that a pattern of one chip is formed on the surface of the wafer by one shot. In the latter case, the shot size S and the chip size CS are equal to each other. The following explanation will be based on the assumption that the shot size S and the chip size CS are equal to each other in order to make the explanation simple. A basic shot region can be formed as follows. In the surface of the wafer, a plurality of the shot regions in which one pattern is formed are arranged in a matrix manner (regions 1 to 32 of Figs. 6 to 8, regions 1 to 37 of Fig. 7). The basic shot region is one of the plurality of shot regions which is positioned close to the center of the wafer and serves as a center of the arrangement. Moreover, the central point of the basic shot region is defined asthecentral point of the arrangement. The central point of the arrangement is sequentially moved in the vicinity of the origin O of the two-dimensional coordinate system. At this time, the position of the central point of the arrangement is separated from the origin O by a distance R (x, y) shown in the following equation (1): R (x, y) = (x 2 + y 2 ) The central point of the arrangement can move in the range shown in the following inequalities (2) and (3): -CS x /2 ≦ x ≦ CS x /2 -CS y /2 ≦ y ≦ CS y /2 In the range shown in the inequalities (2) and (3), the central point is sequentially moved from the points (-CS x /2, -CS y /2) by 1/10 of the chip size CS. Then, the shot gross and the chip gross are calculated according to the array method of the shot region at each point. The calculation method of the shot gross and the chip gross will be explained as allows: For example, the distance from the origin O to four corners of each shot region is calculated. Then, the number of shot regions in which all four corners of the shot region are within a radius of the wafer (WS/2) is counted. In other words, even if one of four corners is positioned out of the radius of the wafer, such a region is not counted. Moreover, a defect area can be formed in the periphery of the wafer. In this case, a surround cut region SC may be formed in the periphery of the wafer. Furthermore, in the calculation of the shot gross and the chip gross, the wafer size WS' can be determined by the following equation (4): WS' = WS - 2 × SC Moreover, it is possible to form a data area LM in an orientation flat portion of the wafer. In this case, the data area LM may be assumed to be a peripheral portion of the wafer. In addition, various data on the wafer can be recorded in the data area LM. Fig. 9 shows the basic structure of a pattern forming system relating to an embodiment of the present invention. In Fig. 9, reference numeral 211 is a mask aligner. The mask aligner 211 comprises a mercury lamp 22, an ellipitic mirror 23, an integrator 24, a condenser lens 25, a reticule 26, and a reduction lens (l/m magnification) 27. On a wafer 28, for example, a SiO 2 film is formed. In order to pattern the SiO 2 film, a photoresist film is formed on the SiO2 film. Thereafter, light is applied to the reticule 26 by the mercury lamp 22. As a result, the pattern formed on the reticule 26 is demagnified and projected on the surface of the wafer 28, and the photoresist film is exposed. Generally, the pattern forming system has a plurality of aligners. For example, in Fig. 9, the plurality of aligners 211, 212 are formed. Reference numerals 291, 292, ... are microcomputers, which are formed in each mask aligners 211, 212 and controls the operation of the mask aligners. The microcomputers 291, 292 are controlled by a host computer 30. In order to calculate the shot gross and the chip gross according to the the array method of the plurality of the shot regions, data on the shot size S, chip size CS, data area LM of the orientation flat portion, wafer size WS, and surround cut SC are input to the host computer 30 as a parameter. The host computer 30 calculates the shot gross and the chip gross according to the the array method of each shot region based on these data. Moreover, the host computer 30 selects from the available methods an array method of the shot region in which the number of the ICs to be formed on one wafer is maximised. By use of the array method, the pattern on the reticule is formed on the surface of the wafer. According to the above-mentioned embodiment, it is clarified that the chip gross CG is different depending on the array method of the shot regions. Fig. 10 shows the relationship of the scatter between the array method of the shot regions and the chip gross. In Fig. 10, CC MAX and CG MIN are respectively a maximum value of the chip gross and a minimum value thereof when the chip area is parameter. As is obvious from Fig. 10, the scatter of the chip gross increases as the chip size CS increases. That is, the number of ICs to be obtained in the complete form in the wafer changes depending on the array method of the shot regions. According to the present invention, in a short period of time, it is possible to automatically determine the array method of the shot regions in which the number of shots is the smallest and the chip gross is the largest. According to this array method, the pattern formed on the reticule can be demagnified and projected on the surface of the wafer. Fig. 11 shows a wafer on which a chip of 4 megabytes of DRAM is formed. In this case, the number of chips, which is formed on the surface of the wafer by one shot, is two. Therefore, according to this embodiment of the present invention, the shot size and the chip size are different. In Fig. 11, a portion enclosed with a solid line shows one shot line, and two chip patterns, which are divided by a broken line, are formed in one shot region. A mark X shows a center of the wafer, and a black circle mark shows a center of the shot array. Moreover, a space between the center of the wafer and the black circle mark is a map off-set. The size of the map off-set of Fig. 11 is 0. 654 mm in the X direction and 12 mm in the Y direction.

Claims: A pattern forming system for maximising the number of shot regions to be completely formed on the main surface of a wafer, characterised in that it comprises: arranging means for preliminarily arranging a plurality of shot regions on a main surface of a wafer in a matrix arrangement where each shot region is formed by one shot of a pattern formed on a reticule and where some of the shot regions are completely formed on said main surface of the wafer and others are not, each completely formed shot region having one or more chip regions, the matrix arrangement including a basic shot region positioned proximate the centre of the matrix arrangement wherein the basic shot region has a central point; calculating means for calculating the number of the shot regions which constitute said matrix arrangement by sequentially moving the matrix arrangement on the main surface of the wafer to move the central point of the basic shot region in a two-dimensional coordinate system comprised of an X axis and a Y axis having an origin defined at a centre of the wafer; said calculating means being for further calculating the number of shot regions to be completely formed on said main surface of said wafer after each sequential movement of the central point of the basic shot region from the origin; selecting means for selecting that matrix arrangement in which the number of shot regions constituting said matrix arrangement is smallest; and forming means for forming said pattern, which is formed on said reticule, on the main surface of the wafer for each shot region of the matrix arrangement. The system according to claim 1, wherein a defect region is formed in a periphery of said wafer, and shot regions are arranged in regions other than said defect region. The system according to claim 1, wherein a data area is formed in the periphery of said wafer and shot regions are arranged in regions other than said data area.

Inventors: NAKAMURA HATSUO, NAKAMURA, HATSUO, Nakamura, Hatsuo, c/o Int. Property Div.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: G03F7
IPC codes: G03F7, H01L21