Heterojunction bipolar transistor

Abstract: In a semiconductor device, a depletion region is provided in a part of an emitter region by pinning Fermi level at Schottky junction or an interface with a high-resistivity semiconductor layer or surface thereof. The depletion region is extended throughout a full thickness of the emitter layer (8), thereby to prevent electrons from being diffused in the direction of the interface with the high-resistivity semiconductor layer so as to recombine through crystalline defects. Thus, the current gain of the device is greatly increased.

Description: The present invention relates to a semiconductor device and more particularly, to element isolation in a heterojunction bipolar transistor using III-V compound semiconductor such as gallium arsenide (GaAs). Description of the Related Art. A heterojunction bipolar transistor (HBT) has very promising prospects as a transistor for use in a microwave circuit and a high-speed logical circuit because of its excellent performances in high frequency and switching operations compared with silicon bipolar transistors. An HBT using GaAs, in particular, is being developed as a superhigh speed device for the next generation. In order to realize a high-speed and low-power consumption transistor, miniaturizing techniques are required. However, the miniaturizing techniques have big problems, which must be solved in future. For example, an Al x Ga 1-x As/GaAs heterojunction bipolar transistor comprises a wafer as shown in Fig. 6. The wafer is formed by epitaxially growing an n - type GaAs layer as a collector layer 102, a p + type GaAs layer as a base layer 103, and an n type Al x Ga 1-x As layer as an emitter layer 104 sequentially on an insulating GaAs substrate 101 with the use of a molecular beam epitaxy (MBE) technique, a metal organic chemical vapor deposition (MOCVD) technique or the like techniques. The wafer thus formed is then subjected to a mesa etching to expose the collector layer 102 and the base layer 103. Subsequently, a collector electrode 105, a base electrode 106 and an emitter electrode 107 are formed thereon, and protons or boron are implanted to thereby form an element isolation region 108 having a high resistance as shown in Fig. 7. A heterojunction bipolar transistor thus prepared is shown by a plan view in Fig. 8. In the connection of the transistor to other elements or pads located outside the transistor, the base and collector electrodes 106 and 105 can be led directly onto the element isolation region 108 of a semi-insulated high-resistance layer. Therefore, these electrodes can be easily connected to other outside elements. On the other hand, when the emitter electrode 107 is to be led out outwards in the same manner, it is short-circuited with the p type GaAs layer surrounding the mesa portion of the emitter. For the purpose of avoiding the short circuit, the surface of the emitter electrode 107 is coated with an insulating film such as a silicon oxide film, a contact hole H is provided on the emitter electrode 107, and a leading wire 109 is formed through the contact hole as shown in Fig. 9. However, this structure requires space for the contact hole and allowance for positioning with respect to the contact hole in the emitter electrode 107, which unfavorably impedes the miniaturization of the device. For eliminating this problem, it has been exercised that the top surface of the emitter mesa is also subjected to the implantation of proton or boron ions so as to form a high resistance top surface, and the side surface of the emitter region 104 is made contacted with the high-resistance region as shown in Fig. 10 (refer to the Japanese patent application No. 62-159464). With this structure, the emitter electrode 109 can be lead out outside of the emitter region 104 without requiring any contact hole and the device can be miniaturized because the area of the emitter electrode can be reduced without space for contact hole and allowance for the positioning of the contact hole. The above-described method for providing a high resistance on the top of the emitter mesa by the implantation of proton or boron ions therein is effective in simplifying the miniaturizing process. This method, however, has a problem that, since crystalline defects introduced by the ion implantation are directly contacted with the interface of the emitter-base junction, an electric current created by the generation and recombination is increased in the interface region, whereby the current gain of the transistor is decreased. Referring to Fig. 11 which is a cross-sectional view taken along line A-A in Fig. 10, recombination centers (shown by marks x in Fig. 11) are induced by the ion implantation in the junction between the p type GaAs layer of the base layer 103 and the n type Al x Ga 1- x As layer of the emitter layer 104, and electrons injected through the emitter are recombined in the recombination centers. Table 1 shows leak currents on the mesa isolation end surface and ion implantation isolation end surface when the base-emitter voltage is applied such that the collector current density becomes 10 4 A/cm 2 in the heterojunction bipolar transistor. Mesa isolation type 0.1µA/um Ion implantation isolation type 30µA/um As shown in Table 1, the leak current on the mesa isolation end face is 0.1µA/µm whereas the leak current on the ion implantation end face is 30µA/µm, which is 300 times of that flowing on the mesa isolation end face. The leak current on the mesa isolation end face is mainly the surface recombination current. Assuming that in Fig. 10, emitter length is the length of the mesa isolation end face and emitter width is the length of the ion implantation isolation end face, Fig. 12 shows the current gain of the transistor when the emitter length of the transistor is varied with the emitter width W being 2 µm. It will be seen from Fig. 12 that as the emitter length is decreased, the influence of the recombination current on the ion implantation isolation end face becomes greater and thus the current gain of the transistor is decreased. Accordingly, it is practically impossible to reduce the emitter length, which impedes the miniaturization of the device. As discussed above, providing a high resistance to the emitter/base end face for isolation by the ion implantation in the heterojunction bipolar transistor has a problem that, as the emitter length is decreased, the influence of the recombination current on the ion implantation isolation end face is increased and the current gain of the transistor is decreased. Applied Physics Letters, Vol. 47, No. 8, October 1995, pages 839-841 (Lin et. al.) describes a super-gain AlGaAs/GaAs heterojunction bipolar transistor, in which the emitter layer is made thinner at its peripheral portion in order to block current from the emitter periphery and inhibit leakage current, thereby improving current gain, especially at low operating current. European patent application number 0 164 517 describes a heterojunction transistor having an electrode forming an ohmic contact with the base region and a Schottky barrier contact with either the collector region or the emitter region. It is an object of the present invention to provide a small heterojunction bipolar transistor having excellent performance capable of preventing increase of recombination current on an ion implantation isolation end face. According to the present invention, there is provided a heterojunction bipolar transistor comprising: a collector layer; a base layer; an emitter layer, the collector layer, the base layer and the emitter layer being sequentially laminated on a semiconductor substrate, said emitter layer having a peripheral portion in direct contact with said base layer; and a high-resistivity layer formed by ion implantation, said high-resistivity layer being in direct contact with said peripheral portion of the emitter layer and with a junction between said peripheral portion and said base layer; characterised in that an emitter electrode is disposed on the emitter layer, extending to said peripheral portion, in that the emitter electrode forms a Schottky junction with the peripheral portion, and in that said peripheral portion of the emitter layer has a thickness such that said peripheral portion is completely depleted in operation by said Schottky junction throughout the full thickness thereof to said junction between said peripheral portion and said base layer. If the emitter and base end faces are subjected to ion implantation, high resistance is imparted, so as to form a high-resistance isolation region. With such an arrangement in which the emitter layer is completely depleted throughout the full thickness thereof along the end face of the high-resistance isolation region, electrons injected through the emitter to the base are prevented from reaching recombination centers which are induced in the previous ion implantation, and the increase of the recombination current on the ion implantation end face and the decrease of the current gain of the transistor can be prevented. Thus, even in the miniaturized transistor area, the reduction of the current cain factor can be prevented. According to another modification, a high-resistivity layer is formed by the ion implantation on the part of the emitter layer along the peripheral end face of the high-resistance isolation region so that the film thickness of that emitter layer part is practically reduced. Assume that the thickness-reduced emitter layer part has a thickness of T E , a pinned Fermi level is qV Φ (eV) from the bottom of the conduction band, the emitter layer has a doping concentration of N D (cm -3 ), the base layer has a doping concentration N A (cm -3 ), and base-emitter voltage is V BE . Then, it is preferable that T E is determined to satisfy the following relationship (1). T E ≦ 2εV Φ qN D + 2ε {(kT/ q)1n(N D N A /n 2 )-V BE } qN D where ε denotes the dielectric constant of the emitter layer, q denotes charge elementary quantity, kT is thermal energy, and n is intrinsic carrier concentration. As the base-emitter voltage BE (V) increases, the upper limit value of the film thickness T E of the emitter layer decreases. However, when the thickness of the emitter layer is previously set to satisfy the following relationship (2), T E ≦ 2εV Φ qN D a variation in the performances caused by a biasing voltage can be made small, and thus more preferable performances can be obtained. Fig. 1 shows a heterojunction bipolar transistor in accordance with a first embodiment of the present invention; Figs 2(a) and 2(o) show steps of fabricating the transistor respectively; Figs. 3 and 4 are diagrams for explaining an energy band structure for the transistor respectively; Fig. 5 is a diagram showing relationships between emitter length and current gain with respect to the transistor of the present invention and a conventional transistor; and Figs. 6 to 12 show a conventional heterojunction bipolar transistor. Embodiments of the present invention will be detailed with reference to the accompanying drawings. An Al x Ga 1-x As/GaAs heterojunction bipolar transistor in accordance with an embodiment of the present invention is featured, as shown in Fig. 1, by comprising an n + type GaAs layer 5 as a collector contact layer, an n - type GaAs layer 6 as a collector layer, a p + type Al x Ga 1-x As graded-composition layer 7 as a base layer, an n - type Al x Ga 1-x As 8 as an emitter layer, and an n + type In y Al x Ga (1-x-y) As layer 9 as an emitter contact layer sequentially formed as laminated on a semi-insulating GaAs substrate 1, and further comprising a high-resistivity layer 11 for isolation between a base and a collector formed through boron ion implantation and a high-resistivity region 14 for inter-element isolation formed through proton implantation; wherein that part of the emitter layer which is contacted with an end face of the high-resistivity isolation region 14 forms a Schottky junction together with an emitter electrode 16 to completely deplete the emitter layer throughout its full thickness. In the present embodiment, the p + type Al x Ga 1-x As graded-composition layer 7 as the base layer has a film thickness of 100nm and a doping concentration of 8x10 19 cm -3 and for the purpose of establishing such a pseudo electric field as to accelerate electrons, the Al x Ga 1-x As composition of the base is set to have Al 0.1 Ga 0.9 As in its emitter side and GaAs in its collector side. The n - type AlGaAs as the emitter layer is set to have a film thickness of 100nm and a doping concentration of 5x10 17 cm -3 . Further, the InAlGaAs layer as the emitter contact layer is set to have a doping concentration of 3x10 19 cm -3 , to have the AlGaAs composition of the emitter in its emitter side and In 0.5 Ga 0.5 As in its surface side and to vary in composition gradually from its emitter side to the surface, thus preventing generation of such a potential barrier as to block an electron flow. Explanation will next be made as to how to fabricate the heterojunction bipolar transistor. First of all, as shown in Fig. 2(a), an n + type GaAs layer 5 as a collector contact layer, an n - type GaAs layer 6 as a collector layer 6, a p + type Al x Ga 1-x As graded-composition layer 7 as a base layer, an n - type Al x Ga 1-x As layer 8 as an emitter layer and an n + type In y Al x Ga 1-x-y As layer 9 as an emitter contact layer are sequentially formed as laminated on a semi- insulating GaAs substrate 1 by a molecular beam epitaxy (MBE) technique, a metalorganic chemical vapor deposition (MOCVD) technique, or the like technique. Then, as shown in Fig. 2(b), a silicon oxide layer 10 is formed on the emitter contact layer 9 by the CVD technique and subjected to a patterning operation by a photolithographic process, the emitter contact layer 9 is subjected to an etching operation and then to ion implantation with use of the silicon oxide layer 10 as a mask to form a high-resistivity layer 11 for isolation between the base and collector. Thereafter, the silicon oxide layer 10 is removed, a silicon oxide film 12 is deposited thereon, a resist pattern 13 is formed thereon, and then the obtained wafer is subjected to a proton implantation with use of the resist pattern 13 as a mask to form a high-resistivity layer 14 for isolation between the base and collector as shown in Fig. 2(c). Fig. 2(d) is a planar positional relationship between the silicon oxide layer 10 used as a mask at the time of forming the high-resistivity layer 11 of the base/collector isolation and the resist pattern 13 used for the formation of the high-resistivity region 14 of the inter-element isolation. Fig. 2(c) is a cross-sectional view taken along line A-A' in Fig. 2(d) and Fig. 2(e) is a cross-sectional view taken along line B-B' in Fig. 2(d). The silicon oxide film 12 is subjected to etching with use of the resist pattern 13 as a mask and buffered hydrofluosilic acid. In this step, the etching time is adjusted such that the silicon oxide film 12 provides a side etching of about 0.2µm with respect to the mask 13. Subsequently, as shown in Figs. 2(f) and 2(g), the emitter contact layer 9 and the emitter layer 8 are subjected to etching with use of the silicon oxide film 12 as a mask to be partially removed. Figs. 2(f) and 2(g) are cross-sectional views taken along lines A-A' and B-B' in Fig. 2(d). In this step, the etching time is adjusted such that a part 8' of the emitter 8 which is contacted with the proton-implanted high-resistivity region 14 becomes about 40 - 50 nm when the etching is completed. Then, as shown in Fig. 2(h) which is a cross-sectional view taken along line A-A', the resist pattern 13 is removed by an ashing process with use of oxygen plasma, the silicon oxide film 12 is removed with use of the buffered hydrofluosilic acid, and then a silicon oxide film 19 of 500 nm is deposited by the CVD technique. Next, as shown in Fig. 2(i), the silicon oxide film 19 as a base electrode formation region is etched by the photolithographic process, and the emitter layer 8 and the emitter contact layer 9 are further etched to expose the base layer 7. Formed on the exposed region is a base electrode 15 by a deposition technique and a lift-off method. Further, as shown in Fig. 2(j), a polyimide film 18 is coated on the entire surface of the thus-obtained wafer by a spin coating technique. In this step, the polyimide film 18 is coated substantially flat on the wafer because of its viscosity. As shown in Fig. 2(k), the polyimide film 18 is subjected to etching in a plasma atmosphere using a mixture gas of CF 4 and O 2 , and the etching process is stopped at the moment the polyimide film is left selectively on the base electrode so that the base electrode and the side wall of the emitter mesa are covered with the polyimide film 18. Thereafter, as shown in Fig. 2(l), the silicon oxide film 19 is removed by etching and an emitter electrode 16 is formed on the exposed emitter contact layer 9. Further, as shown in Figs. 2(m), 2(n) and 2(o), the wafer is then subjected to etching to make a hole reaching the collector contact layer 5 and a collector electrode 17 is formed in the hole by use of a combination of the deposition and lift-off techniques. Figs. 2(m) and 2(o) are cross-sectional views taken along lines A-A' and B-B' in Fig. 2(n) respectively. In this step, the emitter electrode is made up of a laminated film of a titanium layer of 100 nm thickness, a platinum layer of 100 nm thickness and a gold layer of 400 nm thickness. Fig. 3 shows an energy band structure of an epitaxially grown film at a position shown by an arrow (a) in Fig. 2(o) in its laminated layer direction. In Fig. 3, the emitter/base junction is forward biased and the transistor is put in its active state. Since a Schottky potential barrier level between the emitter electrode 16 and the emitter contact layer 9 is as low as about 0.3eV and the doping concentration of the contact layer is as high as 3x10 19 cm -3 , electrons can pass through the potential barrier and move from the emitter electrode 16 to the emitter contact layer 9 by the tunnel effect and thus a good ohmic contact can be obtained. Fig. 4 shows an energy band structure of the epitaxially grown film at a position shown by an arrow (b) in Fig. 2(o) in its laminated layer direction. At the point (b), the emitter electrode 16 has no emitter contact layer 9 therebelow and is contacted directly with the emitter AlGaAs layer 88 having a film thickness of about 40 - 50 nm. In this case, a Schottky barrier level between the titanium emitter electrode 16 and the AlGaAs layer 8 forming the emitter layer is about 0.8eV and the contact layer has a doping concentration of 5x10 17 cm -3 , so that the thickness of the Schottky barrier is as sufficiently large as 46 nm and thus the emitter layer is completely depleted at the point (b) even in the active state, Such a region is shown by a complete depletion region 20 in Fig. 1 and thus the injection of electrons through the emitter electrode 16 is carried out only from that part of the emitter electrode which is contacted at its bottom side with the emitter contact layer 9, as already explained above. When compared with the conventional transistor of Fig. 13, it will be appreciated that the transistor of the present invention is remarkably different from the conventional transistor in the influence of the proton-implanted high-resistivity region 14 or crystalline defects contained therein on the device characteristics. With the structure of the conventional transistor, recombination of electrons and positive holes actively takes place at such crystalline defects and the current gain is largely reduced. With the structure of the present embodiment of the invention, on the other hand, crystalline defects present in the emitter layer are isolated from the emitter layer 8 of the active region having electrons therein with a spacing of about 0.2µm and thus the defects do not act as recombination centers. Accordingly, an increase in the leak current resulting from the crystalline defects present in the high-resistivity region 14 can be made zero in principle, and therefore the current gain can be improved to a large extent. As in the foregoing embodiment, the emitter width is 2µm, and transistors having different emitter lengths based on the foregoing embodiment were fabricated as samples and subjected to measurements of current gains. The measurement results are given in Fig. 5 in which a curve a represents the measurement results for the transistors of the present embodiment and a curve b represents the measurement results of the conventional transistor. It will be seen from the drawing that the current gain remarkably decreases as the emitter length decreases in the conventional transistor, whereas no reduction in the current gain is observed even when the emitter length decreases from 30µm to 2µm and a very high level of current gain of about 80 can be obtained in the transistor of the present embodiment of the invention. Thus in the transistor according to this embodiment, since crystalline defects in the high-resistivity region 14 are isolated from the active emitter region by the completely depleted emitter layer, the performances of the transistor are not influenced by the crystalline defects. Therefore, excellent transistor performances are obtained. In addition, since the emitter electrode can be directly wired to the outside of the emitter region without intervention of any contact hole, miniaturization of the transistor device can be easily realized. In the foregoing embodiment, the thickness of the emitter layer is reduced for the purpose of the isolation between the active emitter region and the crystalline defects, and the thickness-reduced emitter layer is directly contacted with the emitter electrode and depleted by the Schottky barrier.

Claims: A heterojunction bipolar transistor comprising: a collector layer (6); a base layer (7); an emitter layer (8), the collector layer (6), the base layer (7) and the emitter layer (8) being sequentially laminated on a semiconductor substrate (1), said emitter layer (8) having a peripheral portion in direct contact with said base layer (7); a high-resistivity layer (14) formed by ion implantation, said high-resistivity layer (14) being in direct contact with said peripheral portion of the emitter layer (8) and with a junction between said peripheral portion and said base layer (7); and an emitter electrode (16) disposed on the emitter layer (8), extending to said peripheral portion; characterised in that the emitter electrode (16) forms a Schottky junction with the peripheral portion, and in that said peripheral portion of the emitter layer (8) has a thickness such that said peripheral portion is completely depleted in operation by said Schottky junction throughout the full thickness thereof to said junction between said peripheral portion and said base layer (7). A transistor according to claim 1, further characterised in that said peripheral portion of the emitter layer (8) is reduced in thickness relative to portions of the emitter layer (8) other than the peripheral portion. A transistor according to any one of claims 1 or 2, further characterised in that the emitter electrode (16) is extended onto the high-resistivity layer (14) beyond the depleted peripheral portion of the emitter layer (8) whereby said emitter electrode (16) can be connected to another element or a pad region. A transistor according to any one of claims 1 to 3, characterised in that an emitter contact layer (9) is formed on the emitter layer (8) under said emitter electrode (16), the area of the emitter contact layer (9) being smaller than the area of the emitter layer (8), part of the emitter layer (8) which is uncovered with the emitter contact layer (9) forming said peripheral portion of the emitter layer (8). A transistor according to any one of claims 1 to 4, further characterised by comprising an n + type GaAs layer as a collector contact layer (5), an n - type GaAs layer as the collector layer (6), a p + type Al x Ga 1-x As graded-composition layer as the base layer (7), an n - type Al x Ga 1-x As as the emitter layer (8), and an n + type In y Al x Ga (1-x-y) As layer as an emitter contact layer (9) which are sequentially laminated on a semiinsulating GaAs substrate (1); a high-resistivity layer (11) isolating the base layer (7) from the collector layer (6), the high-resistivity layer (11) being formed by boron ion implantation; a collector electrode (17) contacted with the collector contact layer (5); and a base electrode (15) contacted with the base layer (7).

Inventors: MORIZUKA KOUHEI, MORIZUKA, KOUHEI, MORIZUKA, KOUHEI, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: H01L29
IPC codes: H01L29, H01L21