Differential amplifying circuit

Abstract: A differential amplifying circuit includes two transistors (Q6;Q7) which are connected at collectors respectively to first terminals of two load resistances (R3;R4) and at emitters respectively to a constant current source (I3). An emitter follower transistor (Q5) is connected at a collector to second terminals of the two resistances commonly and to a positive terminal of a direct current power supply (Vs) and at an emitter to a base of one of the two transistors. An input signal is supplied to the base of the emitter follower transistor and then supplied to the base of the transsitors which is connected therewith. A differential output is picked up at the collectors of the two transistors. In this circuit, the emitter follower transistor is biased by the constant current source which also biases the two transistors of the differential amplifying circuit.

Description: This invention relates to a differential amplifying circuit, and more particularly to, a differential amplifying circuit provided with at least one emitter follower circuit connected to an input thereof. A conventional differential amplifying circuit includes first and second transistors, first and second load resistances and a first constant current source, and it is usually provided with an emitter follower circuit connected to an input of the circuit for increasing an input impedance thereof. The first and second transistors are connected at emitters with the first constant current source commonly, and at bases with emitters of first and second emitter follower transistors, respectively. The first and second load resistances are connected at first terminals to collectors of the first and second transistors, respectively, and at second terminals to a positive terminal of a direct current power supply commonly. The first and second emitter follower transistors are connected at collectors to the positive terminal of the direct current power supply commonly, at bases to a signal source in which positive and negative components are supplied to the bases of the first and second emitter follower transistors respectively, and at emitters to second and third constant current sources, respectively. The first to third constant current sources are connected to a negative terminal of the direct current power supply commonly. In operation, an input signal is supplied differentially to the bases of the emitter follower transistors with bias voltage, and is amplified by the first and second transistors to be supplied to first and second output terminals provided at the collectors of the first and second transistors, respectively. In general, the outputs of the terminals may be amplified differentially in a differential amplifying circuit of the next stage. According to the conventional differential amplifying circuit, however, there is a disadvantage in that the second and third constant current sources for driving the emitter follower transistors consume a considerable value of power which is a multiple of currents flowing through the constant current sources and a voltage of the direct current power supply. In case of the circuit used in a high frequency (1 GHz, for example) range, the constant current sources are required to make currents sufficient for discharging a suspended capacity of the differential amplifying circuit and an input capacity of a differential amplifying circuit of the next stage, so that the currents may become 10 mA in some cases. In case of the circuit used as a low noise amplifier, the constant current sources are required to make currents sufficient for reducing shot noises to a predetermined level (it is known that the noise power level is inversely proportional to the current). Further, a problem may occur, if the input bias current thereof is large. If the input signal source is an output of a magnetic head of a magnetic recording device such as a floppy disk driver, miss writing operation may occur in reproducing mode, so that recorded signals may be unable to reproduce, because of an offset of the input bias current. Therefore, the input bias current should be a low level. On the other hand, the constant current of the constant current source which supplies a bias current of the differential amplifying circuit is required to be a sufficiently large current in considering the gain, and noise and frequency characteristics. Such a disadvantage may cause a short-life of batteries in a set driven by batteries or decrease of integration of LSIs to reduce a power consumption within an allowable loss thereof. Accordingly, it is an object of the invention to provide a differential amplifying circuit in which a consumption power is reduced. According to a feature of the invention, a differential amplifying circuit comprises: first and second transistors for differentially amplifying an input signal; first and second load elements; a constant current source; and an emitter follower transistor; wherein: the first and second transistors are connected at emitters to the constant current source commonly, and at collectors to first terminals of the first and second load elements, respectively; the first transistor is connected at a base to an emitter of said emitter follower transistor; the first and second load elements are connected at second terminals to an emitter of the emitter follower transistor commonly; and the emitter follower transistor is connected with a signal source for supplying the input signal thereto with a bias voltage. The invention will be explained in more detail and by way of example, in conjunction with appended drawings wherein: Fig. 1 is a circuit diagram of a conventional differential amplifying circuit; Fig. 2 is a circuit diagram of a differential amplifying circuit in a first preferred embodiment according to the invention; Fig. 3 is a circuit diagram of a differential amplifying circuit in a second preferred embodiment according to the invention; Fig. 4 is a circuit diagram of a differential amplifying circuit in a third preferred embodiment according to the invention; Fig. 5 is a circuit diagram of a differential amplifying circuit in a fourth preferred embodiment according to the invention; Fig. 6 is a circuit diagram of a differential amplifying circuit in a fifth preferred embodiment according to the invention; and Fig. 7 is a circuit diagram of a differential amplifying circuit in a sixth preferred embodiment according to the invention. Before describing a differential amplifying circuit in preferred embodiments according to the invention, the conventional differential amplifying circuit described before will be explained in conjunction with Fig.1. The conventional differential amplifying circuit includes first and second transistors Q ₁ and Q ₂, first and second load resistances R ₁ and R ₂, and a first constant current source I ₀. The first and second transistors Q ₁ and Q ₂ are connected at emitters with the first constant current source I ₀ commonly, and at bases with emitters of first and second emitter follower transistors Q ₃ and Q ₄ , respectively. The first and second load resistances R ₁ and R ₂ are connected at first terminals to collectors of the first and second transistors Q ₁ and Q ₂ , and at second terminals to a positive terminal of a direct current power supply V CC commonly. The first and second emitter follower transistors Q ₃ and Q ₄ are connected at collectors to the positive terminal of the direct current power supply V CC commonly, at bases with a signal source V S in which positive and negative components are supplied to the bases of the first and second emitter follower transistors Q ₃ and Q ₄ respectively, and at emitters to second and third constant current sources I ₁ and I ₂ respectively. The first to third constant current sources I ₀ to I ₂ are connected to a negative terminal of the direct current power supply V CC commonly. Outputs of first and second output terminals T ₁ and T ₂ provided at the collectors of the first and second transistors Q ₁ and Q ₂ respectively are supplied to an external circuit. In operation, an input signal V S is applied differentially to the bases of the emitter follower transistors Q ₃ and Q ₄ with a bias voltage. Though the input signal is attenuated slightly at the first and second emitter follower transistors Q ₁ and Q ₂, however, the input signal is amplified at the first and second transistors Q ₁ and Q ₂ , and is supplied to the first and second output terminals T ₁ and T ₂ differentially. In general, the outputs of the terminals T ₁ and T ₂ are amplified differentially by a differential amplifying circuit of the next stage. Next, a differential amplifying circuit in a first preferred embodiment will be explained in conjunction with Fig. 2. The differential amplifying circuit includes first and second transistors Q ₆ and Q ₇ , first and second load resistances R ₃ and R ₄ , and a first constant current source I ₃ . The first and second transistors Q ₆ and Q ₇ are connected at emitters with the first constant current source I ₃ commonly. The first and second load resistors R ₃ and R ₄ are connected at first terminals to collectors of the first and second transistors Q ₆ and Q ₇ respectively. The first transistor Q ₆ is connected at a base to an emitter of an emitter follower transistor Q ₅. The emitter follower transistor Q ₅ is connected at a collector to the positive terminal of the direct current power supply V CC commonly, at a base to a signal source V S in which a positive component is supplied thereto, and at an emitter to second terminals of the first and second resistances R ₃ and R ₄ commonly. The second transistor Q ₇ is connected at a base to a bias power supply V S from which a predetermined level of a bias voltage is applied thereto. A negative terminal of the direct current power supply V CC is connected to the constant current source I ₃. In operation, an input signal V S is applied to the base of the emitter follower transistor Q ₅ with a bias voltage. The input signal is amplified by the first transistor Q ₆ and supplied to first output terminal T ₁ provided at the collectors of the first and second transistors Q ₆ and Q ₇. In this differential amplifying circuit, there occurs direct current drop in the first and second resistances R ₃ and R ₄ . Therefore, a value of the first resistance R ₃ should be determined so that a voltage V CE between the collector and the emitter of the first transistor Q ₆ becomes at least 0.1 V (preferably in the range of 0.2 V to 0.5 V). The voltage V CE is obtained by the following formula: V CE = V BE - I₃ R ₃ /2 where V BE is a voltage between the base and the emitter of the first transistor Q₅ . Such a condition can be realized by setting the same conditions as like in an internal gate circuit of an ECL (Emitter Coupling Logic). In this embodiment, a sum of collector currents of the first and second transistors Q ₆ and Q ₇ , which is a bias current of the emitter follower transistor Q ₅, is approximately equal to a sum of emitter currents thereof which is equal to the constant current flowing through the constant current source I ₃, because each of base currents thereof is minimum in compared with the collector currents. Therefore, the emitter follower transistor Q₅ is biased by the constant current source I₃ , so that it is not necessary to provide an additional current source for biasing the emitter follower transistor Q ₅. Though there is no problem when the outputs are picked up from the first and second output terminals T ₁ and T ₂ differentially, the outputs become values of (gain - 1) in the first terminal T ₁ and (gain + 1) in the second terminal T ₂ respectively if the output is picked up from only one of either of the first and second terminals T ₁ and T ₂ , because an alternative signal corresponding to the input signal is supplied to both terminals. Next, a differential amplifying circuit in the second preferred embodiment will be explained in conjunction with Fig. 3. The circuitry structure of the differential amplifying circuit is the same as that in Fig. 2, except that the circuit is further provided with a transistor Q ₈ and two resistances R ₅ and R ₆ . The transistor Q ₈ is connected at a base to ground, at a collector to a positive terminal of a direct current power supply V CC , and at an emitter to first terminals of the resistances R ₅ and R ₆ commonly. The resistors R ₅ and R ₆ are connected at second terminals to collectors of the first and second transistors Q ₆ and Q ₇. In this differential amplifying circuit, proportion of a bias currents of the emitter follower transistor Q ₅ and that of the first and second transistors Q ₆ and Q ₇ are adjusted to be adequate by providing the transistor Q ₈ and the resistances R ₅ and R ₆. Now, tt is supposed that the adequate level of the bias current of the emitter follower transistor Q ₅ is 2.5 mA and a constant current of the constant current source I ₃ is 2.5 mA. Such a condition can be realized by setting the base voltage level of the transistor Q ₈ as the same level of the DC bias voltage level of that of the emitter follower transistor Q ₅ and setting each of the resistances R ₃ to R ₆ to have the same resistance, when the differential amplifying circuit is biased. In such a case, the same amount of current, that is 1.25 mA, flows through each of the resistances R ₃ to R ₆ , so that the current of the emitter follower transistor Q ₅ becomes 2.5 mA, which is a sum of currents flowing the resistances R ₃ and R ₄. Consequently, the adequate level of current flows through the emitter follower transistor Q ₅ , so that the emitter follower transistor Q ₅ does not consume an excess power. Next, a differential amplifying circuit in a third preferred embodiment will be explained in conjunction with Fig. 4. In this embodiment, first and second units each composing a differential amplifying circuit are provided in parallel. The first unit includes two transistors Q ₁₁ and Q ₁₂ , two load resistances R ₇ and R ₈ and a constant current source I ₄, while the second unit includes two transistors Q ₁₃ and Q ₁₄ , two load resistances R ₉ and R ₁₀ and a constant current source I ₅. Each of the two units has the same circuitry structure which is the same as the differential amplifying circuit in Fig. 2. Emitter follower transistors Q ₉ and Q ₁₀ are also provided. The emitter follower transistors Q ₉ and Q ₁₀ are supplied at bases with an input signal differentially as like in Fig. 1, in which a positive component of the input signal to the base of the emitter follower transistor Q ₁₀ and a negative component thereof to the base of the emitter follower transistor Q ₉ . The emitter follower transistor Q ₉ is connected at an emitter to bases of the transistors Q ₁₁ and ₁₃ and the resistances R ₇ and R ₈ . On the other hand, the emitter follower transistor Q ₁₀ is connected at an emitter to bases of the transistors Q ₁₂ and Q ₁₄ and the resistances R ₉ and R ₁₀ . A direct current power supply V CC is connected at a positive terminal to collectors of the emitter follower transistors Q ₉ and Q ₁₀ , and at a negative terminal to the constant current sources I ₄ and I ₅ . Output terminals T ₃ to T ₆ are provided at collectors of the transistors Q ₁₁ to Q ₁₄ , respectively, from which outputs of the differential amplifying circuit are picked up. In this embodiment, there are several ways for picking up outputs of the differential amplifying circuit. In the first way, a differential voltage level between the output terminals T ₃ and T ₄ and a differential voltage level between the output terminals T ₅ and T ₆ are picked up, respectively, and then the two differential voltage levels are summed to be an output of the circuit. In practical, the differential outputs of the output terminals T ₃ and T ₄ are supplied to inputs of a first differential amplifying circuit of the next stage, while the differential outputs of the output terminals T ₅ and T ₆ are supplied to inputs of a second differential amplifying circuit of the next stage. Then outputs of the first and second differential amplifying circuit of the next stage are summed. In the second way, an output picked up from the output terminals T ₃ and T ₅ which are connected each other and an output picked up from the output terminals T ₄ and T ₆ which are connected each other are differentially picked up. In the third way, only one differential output of either the output terminals T ₃ and T ₄ or the output terminals T ₅ and T ₆ is picked up. In the fourth way, only one differential output of either the output terminals T ₄ and T ₅ or the output terminals T ₃ and T ₆ is picked up. In the fifth way, only one output of either of the four terminals T ₃ to T ₆ are picked up. In any case, the circuit may have the same power consumption and frequency and noise characteristics as those in Fig. 2 on conditions that constant currents of the constant current source I ₄ and I ₅ are both equal to half of the constant current of the constant current source I ₅ in Fig. 2, resistances of all of the load resistances R ₇ to R ₁₀ are equal to a doubled value of the load resistance R ₃ in Fig. 2, and each size of all of the transistors Q ₁₁ to Q ₁₄ is equal to half of that of the transistor Q ₆ in Fig. 2. Next, a differential amplifying circuit in a fourth preferred embodiment will be explained in conjunction with Fig. 5. The circuitry structure of the differential amplifying circuit is the same as that in Fig. 4, except that the circuit is further provided with two transistors Q ₁₅ and Q ₁₆ and four resistances R ₁₁ to R ₁₄. The transistor Q ₁₅ is connected at a base to ground, at a collector to a positive terminal of a direct current power supply V CC , and at an emitter to first terminals of the resistances R ₁₁ and R ₁₂ commonly. The resistances R ₁₁ and R ₁₂ are connected at second terminals to the collectors of the transistors Q ₁₁ and Q ₁₂ . On the other hand, the transistor Q ₁₆ is connected at a base to ground, at a collector to the positive terminal of the direct current power supply V CC , and at an emitter to first terminals of the resistances R ₁₃ and R ₁₄ commonly. The resistances R ₁₃ and R ₁₄ are connected at second terminals to the collectors of the transistors Q ₁₃ and Q ₁₄. In this differential amplifying circuit, proportion of bias currents of the emitter follower transistors Q ₉ and Q ₁₀ and those of the transistors Q ₁₁ to Q ₁₄ are adjusted by providing the transistors Q ₁₅ and Q ₁₆ and the resistances R ₁₁ to R ₁₄ as like the transistor Q ₈ and resistance R ₅ and R ₆ in Fig. 3. Next, a differential amplifying circuit in a fifth embodiment will be explained in conjunction with Fig. 6. In this embodiment, the circuitry structure is the same as that in Fig. 4, except that the transistors Q ₁₁ and Q ₁₃ and the transistors Q ₁₂ and Q ₁₄ are short-circuited respectively and the two constant current sources I ₄ and I ₅ are replaced by a constant current source I ₆ . In Fig. 4, the common signals are supplied to the transistors Q ₁₁ and Q ₁₃ and the transistors Q ₁₂ and Q ₁₄, respectively, so that the same signals are generated at the emitters of the the transistors Q ₁₁ and Q ₁₃ and at the emitters of the transistors Q ₁₂ and Q ₁₄ . Therefore, the differential amplifying circuit has the same equivalent circuit structure as that in Fig. 4, so that operation thereof is the same as that in Fig. 4. Next, a differential amplifying circuit in a sixth embodiment will be explained in conjunction with Fig. 7. In this embodiment, the circuitry structure is the same as that in Fig. 6, except that the differential amplifying circuit is further provided with a transistor Q ₁₅ and four load resistances R ₁₅ to R ₁₈. The transistor Q ₁₅ is connected at a base to ground, at a collector to a positive terminal of a direct current power supply V CC , and at an emitter to first terminals of the resistances R ₁₅ to R ₁₈ commonly. The resistances R ₁₅ to R ₁₈ are connected at second terminals to the collectors of the transistors Q ₁₁ to Q ₁₄ . The transistor Q ₁₅ functions at a by-pass as like the transistor Q ₈ in Fig. 3 or the transistors Q ₁₅ and Q ₁₆ in Fig. 5. The operation thereof is the same as that in Fig. 6. Although the invention has been described with respect to specific embodiment for complete and clear disclosure, the appended claims are not to thus limited and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.

Claims: A differential amplifying circuit, comprising: first (Q₆) and second (Q₇) transistors for differentially amplifying an input signal; first (R₃) and second (R₄) load elements; a constant current source (I₃); and an emitter follower transistor (Q₅); wherein: said first and second transistors are connected at emitters to said constant current source commonly, and at collectors to first terminals of said first and second load elements, respectively; said first transistor is connected at a base to an emitter of said emitter follower transistor; said first and second load elements are connected at second terminals to an emitter of said emitter follower transistor commonly; and said emitter follower transistor is connected with a signal source (V s ) for supplying said input signal thereto with a bias voltage. A differential amplifying circuit, according to claim 1, further comprising: a third transistor (Q₈) connected at a base to ground and at a collector with a collector of said emitter follower transistor; and third (R₅) and fourth (R₆) load elements connected at first terminals to an emitter of said third transistor commonly and second terminals to collectors of said first and second transistors.

Inventors: SUGAWARA MITSUTOSHI C O NEC CO, SUGAWARA, MITSUTOSHI, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: H03F3
IPC codes: H03F3, H03F1