Dynamic RAM and process for producing same

Abstract: A FEC-DRAM of 3 elements/2 bits type having a stacked capacitor of increased capacitance to ensure integration with an increased density. The stacked capacitor is formed as embedded in a trench, and local wiring is provided to form an electric contact on an element isolation region. When required, the stacked capacitor is made to extend onto a word line region.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to dynamic RAMs (DRAMs) and a process for producing the same, and more particularly to a floating electrode capacitor DRAM and a process for producing the same. 2. Description of the Related Art DRAM cells are already in wide use which comprise one MOS transistor and one capacitor as shown in FIG. 22. To meet a demand for higher packing densities and reduced cell sizes, a floating electrode capacitor DRAM (FEC-DRAM) cell has recently been proposed which comprises two MOS transistors and one capacitor as seen in FIG. 23. The FEC-DRAM cell, which is of three-element structure, is capable of storing 2 bits of data in one capacitor and therefore has a greater storage capacity per element (1.5 elements/bit) than the conventional cell of the 2 elements/bit type. However, the conventional FEC-DRAM cell has a stack capacitor wherein a floating capacitor C is provided between an upper electrode UP and a lower electrode LP which have respective contacts for electric connection to the Source/Drain active regions A, B of the pair of MOS transistors Q 1 , Q 2 , so that the contacts and the floating capacitor require an area on the substrate. Accordingly, the FEC-DRAM cell occupies a relatively large area over the substrate and is not always advantageous in ensuring a higher packing density. For example, if the cell is adapted to occupy approximately the same area as cells of the 1 element/bit type, the cell has the disadvantage of being insufficient in capacitance. The cell further has the problem of necessitating a complex process when the stack capacitor is to be formed on the substrate with minimized misalignment. Patent Abstract of Japan, vol. 15, no. 78 (& JP-A-2297962) discloses a DRAM having two access transistors and a capacitor for access memorizing two-bit information. One of the two transistors is a thin film transistor. The capacitor may be formed in a substrate trench. IBM Technical Disclosure Bulletin, vol. 31, no. 7, Dec 1988, pp 409-417 also discloses a DRAM cell structure which incorporates a pair of access transistors and a capacitor. A reactive ion etched trench defines the storage capacitor region. SUMMARY OF THE INVENTION The main object of the present invention, which has been accomplished in view of the above situation, is to provide a FEC-DRAM which occupies a small area on the substrate and which nevertheless has a great capacitance, and to provide a process for producing the same. Accordingly, the present invention provides a FEC dynamic RAM comprising: (a) a pair of capacitively coupled MOS transistors formed side by side on a substrate, the first of said pair of MOS transistors having a source impurity region A and the second of said pair having a drain impurity region B, said impurity regions A and B being in adjacent portions of the respective first and second MOS transistors, (b) a trench with an insulating layer lining formed in the substrate between said impurity regions A and B, and (c) a stack capacitor comprising a first electrode layer connected to the source impurity region A, a capacitor insulating layer and a second electrode layer connected to the drain impurity region B through the intermediary of a contact strap, said layers being formed one over another with said capacitor insulating layer sandwiched between said electrode layers, and embedded in said trench. The present invention further provides a process for producing a FEC dynamic RAM as defined in the preceding paragraph comprising the steps of: (a) forming a trench in a substrate between a source impurity region A and a drain impurity region B which lie adjacent to each other and which belong to respective ones of a pair of MOS transistors provided side by side on the substrate, (b) forming an insulating layer on the inner surface of said trench, (c) forming a local wiring strap on one of the impurity regions, B, (d) forming a first electrode layer on the other impurity region A and over the insulating layer covering the inner surface of the trench, said first electrode layer being insulated from the local wiring strap, (e) forming a capacitor insulating layer over the first electrode layer, and (f) forming on the capacitor insulating layer a second electrode layer to be connected to the local wiring strap. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view partly in section and showing a FEC-DRAM cell embodying the present invention; FIG. 2 is a layout diagram corresponding to FIG. 1; FIG. 3 is a perspective view showing the cell in the course of production process; FIG. 4 is a plan view corresponding to FIG. 3; FIG. 5 includes a view (a) in section taken along the line B-B' in FIG. 4, and a view (b) in section taken along the line A-A' in FIG. 4; FIG. 6 to FIG. 16 are diagrams illustrating the production process of the invention stepwise and subsequent to FIG. 5; FIG. 17 is a perspective view showing the cell being produced and resulting from the step of FIG. 15; FIG. 18 to FIG. 21 are layout diagrams showing some steps of the process of the invention in sequence; FIG. 22 is an equivalent circuit diagram of a DRAM cell of the 2 elements/bit type; and FIG. 23 is an equivalent circuit diagram of a DRAM cell of the 3 elements/2 bits type. DESCRIPTION OF THE PREFERRED EMBODIMENTS The dynamic RAM of the present invention comprises two MOS transistors and one stack capacitor connected therebetween. Since the stack capacitor is embedded in a trench formed between the adjacent ends of the transistors so as to extend along the trench inner wall, the DRAM can be given a sufficient capacitance. The trench can be formed between the word lines in the DRAM layout as self-registered with the lines without misalignment. This assures DRAM cells of a great capacitance with improved reproducibility. Furthermore, the stack layer can be easily made to extend, as centered at the stack capacitor within the trench, onto the word lines adjacent thereto. This permits a further increase in capacitance. EXAMPLES An embodiment of the FEC-DRAM of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a perspective view partly in section and showing a FEC-DRAM cell embodying the invention. FIG. 2 is a layout diagram corresponding to FIG. 1 and showing two FEC-DRAM cells arranged as a group. As seen in the drawings, the FEC-DRAM cell 1 of the invention comprises a pair of MOS transistors Q1, Q2 fabricated by forming on the p-type silicon substrate 1' active regions 11, bit lines BL and BL , and word lines WL as arranged in a matrix. The Opposed N + impurity regions at one side of the pair of transistors Q1, Q2 are connected to the bit lines BL BL and BL , respectively, through contact holes 10. A trench 2 is formed in the substrate between the adjacent N + impurity regions A, B at the other side shown. The trench is used for forming a capacitor between the impurity regions A, B. The capacitor comprises a first electrode layer 4 of polysilicon, capacitor insulating layer 5 of SiO 2 /SiN and a second electrode layer 6 of polysilicon which are formed one over another in this order over the inner surface of the trench 2 coated with an SiN insulating film 3 and which are thus embedded in the trench. The first electrode layer 4 has a specified area to extend through the trench opening end over the impurity region A in direct contact therewith and to extend over the word lines WL to the central portion of each line. On the other hand, the second electrode layer 6 is so formed as to cover the entire area of the first electrode layer 4 with the capacitor insulating layer 5 interposed therebetween and to contact through an upper silicon electrode 9 with a contact strap 8 (polysilicon) formed, as insulated from the first electrode layer, on the impurity region B. Thus, a stack capacitor of a specified square form including the interior of the trench and also partly including the word line regions is formed across the impurity regions A, B to provide the FEC-DRAM circuit. The FEC-DRAM realized is of the three-element two-bit storage type as shown in FIG. 23. In FIG. 1, indicated by FOX is a field oxide film, at 7 a surface protecting layer (SiO 2 ) for the capacitor, and at 15 an interlayer insulating film. The FEC-DRAM can be produced, for example, by the process shown in FIGS. 3 to 17 as will be described in detail below. With reference to FIG. 3, there is first formed on a silicon substrate 1' an active region including N + impurity regions A, B patterned by a field oxide film. Word lines WL (about 0.5 µm in width) are then formed on the active region to provide MOS transistors Q1, Q2. In this example, the impurity regions A, B correspond to the drains of the respective transistors. FIG. 4 is a plan view showing this state. FIG. 5, (a) is a view in section taken along the line B-B' in FIG. 4, and FIG. 5, (b) is a view in section taken along the line A-A' in FIG. 4. Indicated at 12 in FIG. 5 is the side wall (SiO 2 ) of the word line WL serving as a gate, and at 13 an oxide surface film which is a thermal oxide film. As shown in Fig. 6(a) and Fig. 6(b), the formation of the word lines is followed by coating with a resist 14, and a major portion of the oxide film 13 on the impurity region B is removed (width X: about 1 µm). As shown in FIG. 7, a contact strap 8 (about 1000 angstroms in thickness, about 1 x about 1 µm) of polysilicon is then formed to cover the removed portion. Next as shown in FIGS. 8 and 9, an SiN layer 16 is formed by LPCVD, and the layer is etched back to form a side wall 16' for protecting the side portions of the word lines WL. A rectangular trench 2 is then formed in the substrate between the impurity regions A, B and between the word lines WL,WL by anisopropic etching using a resist 17 as shown in FIG. 10. In view of the capacitance, it is suitable that the trench be usually 0.5 to 1 µm in width and about 2 to about 5 µm in depth although the width and depth are dependent on the cell size. After the trench has been formed, the resist 17 is removed, and the resulting surface is subjected to thermal oxidation to thereby form an insulating oxide film 19 primarily over the contact strap. SiN is thereafter deposited on the entire surface by LPCVD to form an SiN insulating film 3 (about 1000 anstroms in thickness) over the inner surface of the trench as shown in FIG. 11. Subsequently, a masking SOG layer (or resist layer) 18 is formed over the entire surface. Next as seen in FIG. 12, the SOG layer (or resist layer) 18 is etched back to the level of the trench opening to expose the SiN insulating film 3 except the film portion inside the trench. The exposed portion of the SiN insulating film is removed by isotropic etching, and the SiN insulating film 3 and the oxide surface film 13 are then removed from the impurity region A and the surrounding portion thereof using a resist 20 as seen in FIG. 13 to provide a contact portion for the impurity region A. A first electrode layer 4 (about 0.1 µm in thickness) of polysilicon is thereafter formed over the entire surface. The first electrode layer is removed from the surface of the contact strap 8 except the end thereof adjacent to the trench using a resist 21 as shown in FIG. 14. Over the first electrode layer 4 is then formed a capacitor insulating layer 5 (about 100 angstroms in thickness) of SiO 2 or Si 3 N 4 , followed by the deposition of a second electrode layer 6 (about 0.1 µm in thickness) of polysilicon on the entire surface. In this state, the impurity region A is in contact with the first electrode layer 4, but the impurity region B is held out of contact with the second electrode layer 6 by the presence of the oxide film 19. Next, a surface protecting layer 7 of SiO 2 is formed over the entire surface by CVD, and the upper portion adjacent to the impurity region B is etched away to expose the second electrode layer 6. A contact hole 22 is formed in the portion of the exposed region to be connected to the contact strap 8 as seen in FIG. 17. An upper silicon electrode 9 is thereafter formed by deposition to fill up the contact hole as shown in FIG. 16, whereby a stack capacitor is constructed according to the invention. The first and second electrode layers and the upper electrode may be doped with an electrically conductive impurity element, such as P or As, when desired for giving improved conductivity. After the stack capacitor cell has been thus formed, an interlayer insulating film, bit line, bit line contact, etc. are formed by conventional methods to afford a FEC-DRAM according to the invention as seen in FIG. 1. FIGS. 18 to 21 show the layout of the device stepwise during the above process. FIG. 18 shows the device when the contact strap 8 is formed, FIG. 19 shows the trench 2 formed, FIG. 20 shows the stack capacitor layer and the upper silicon electrode layer formed, and FIG. 21 shows the DRAM as completed. With the FEC-DRAM of the present invention, the presence of the trench realizes a stack capacitor having a sufficient capacitance between the impurity regions A and B. Consequently, the DRAM of the 3 elements/ 2 bits type can be constructed within a smaller area than conventionally possible. This leads to a higher packing density. In fact, the cell utility factor CUF (capacitor area/cell area) achieved by the above example is as high as 50% in contrast with the conventional factor which is up to about 40%. This substantiates the improvement achieved by the invention in packing density. As described above, the present invention readily provides FEC-DRAMs of the 3 elements/2 bits type which are reduced in the area occupied. The present invention is therefore very useful in the field of DRAMs which are expected to have a still higher packing density.

Claims: A FEC dynamic RAM comprising: (a) a pair of capacitively coupled MOS transistors (Q 1 ,Q 2 ) formed side by side on a substrate (1'), the first of said pair of MOS transistors (Q 1 ) having a source impurity region A and the second of said pair (Q 2 ) having a drain impurity region B, said impurity regions A and B being in adjacent portions of the respective first and second MOS transistors, (b) a trench (2) with an insulating layer lining (3) formed in the substrate between said impurity regions A and B, and (c) a stack capacitor comprising a first electrode layer (4) connected to the source impurity region A, a capacitor insulating layer (5) and a second electrode layer (6) connected to the drain impurity region B through the intermediary of a contact strap (8), said layers being formed one over another with said capacitor insulating layer sandwiched between said electrode layers, and embedded in said trench. A FEC dynamic RAM according to claim 1 wherein the stack capacitor extends so as to partly cover a word line region (WL) serving as the gate of each of the MOS transistors (Q 1 ,Q 2 ). A process for producing a FEC dynamic RAM as defined in claim 1 comprising the steps of: (a) forming a trench (2) in a substrate (1') between a source impurity region A and a drain impurity region B which lie adjacent to each other and which belong to respective ones of a pair of MOS transistors (Q 1 ,Q 2 ) provided side by side on the substrate (1'), (b) forming an insulating layer (3) on the inner surface of said trench, (c) forming a local wiring strap (8) on one of the impurity regions, B, (d) forming a first electrode layer (4) on the other impurity region A and over the insulating layer covering the inner surface of the trench, said first electrode layer being insulated from the local wiring strap, (e) forming a capacitor insulating layer (5) over the first electrode layer (4), and (f) forming on the capacitor insulating layer (5) a second electrode layer (6) to be connected to the local wiring strap (8). A process as defined in claim 3 wherein the first electrode layer (4), the capacitor insulating layer (5) and the second electrode layer (6) are each so formed as to partly cover a word line region (WL) serving as the gate of each of the MOS transistors (Q 1 ,Q 2 ).

Inventors: ADAN ALBERTO OSCAR, ADAN,ALBERTO OSCAR
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1991
Main classification: H01L27
IPC codes: H01L27, H01L21