Semiconductor device having multilayered wiring structure and method of manufacturing the same

Abstract: An amorphous silicon layer (14) is formed on the side wall of a first wiring layer (13) having a predetermined wiring width and formed in a predetermined shape by patterning. A silicon oxide layer (15) is covering the first wiring layer and the amorphous silicon layer, and a through-hole is formed in the silicon oxide layer so that a portion of the first wiring layer is exposed. A tungsten layer (17) is filling the through-hole, and a second wiring layer (18) connected to the tungsten layer is formed on the silicon oxide layer.

Description: The present invention relates to a semiconductor device having a multilayered wiring structure and a method of manufacturing the same and, more particularly, to a semiconductor device in which different wiring layers are connected to each other via a through-hole, and a method of manufacturing the same. US-A-4 807 013 discloses an integrated circuit manufacturing technique that relies on the use of polysilicon fillets. Therein, a polysilicon fillet is provided in the corner formed by a steep sidewall of a patterned polysilicon layer and a layer supporting the latter, said fillet having a rounded surface. A conventional method of manufacturing a semiconductor device having a multilayered wiring structure in which respective wiring layers are connected to each other via a through-hole will be described below with reference to Figs. 1A to 1D. As shown in Fig. 1A, a silicon oxide film 32 as an insulating interlayer is formed on a silicon substrate 31 by a CVD (Chemical Vapor Deposition) method. Subsequently, a first aluminum layer is deposited on the entire surface of the silicon oxide film 32 and patterned to form a first wiring layer 33. As shown in Fig. 1B, a thick silicon oxide film 34 is formed on the entire surface of the resultant structure at a low temperature of 300°C to 380°C by a plasma CVD method. Subsequently, as shown in Fig. 1C, the silicon oxide film 34 formed on the first wiring layer 33 is selectively removed by an RIE (Reactive Ion Etching) method using a predetermined mask, thereby forming a through-hole 35. Thereafter, a second aluminum layer is deposited on the entire surface and patterned to form a second wiring layer 36. In the above conventional method, however, upon formation of the through-hole performed by RIE in the step shown in Fig. 1C, a formation position of the through-hole 35 may be deviated from a correct position on the first wiring layer 33, as shown in a plan view of Fig. 2, due to a mask misalignment or a process variation. If the through-hole 35 is deviated from the correct position in this manner, the silicon oxide film 32 is etched to a portion located below the first wiring layer 33. In this case, a leakage current is produced between the second wiring layer 36 and an underlying polycrystalline silicon wiring layer (not shown) or the silicon substrate 31, or inconveniences such as a short circuit occur in the worst case. When the second wiring layer 36 is etched to be deviated from the through-hole 35, the first wiring layer 33 is etched to cause a reliability or disconnection defect. In order to form a through-hole, therefore, as shown in a plan view of Fig. 3, the wiring width of the first wiring layer 33 at a prospective formation posltion of the through-hole 35 is set to be much larger than a minimum width of the first wiring layer. That is, a predetermined size margin which can allow a mask misalignment or a process variation is set between the through-hole 35 and the first wiring layer 33. As a result, the above inconveniences do not occur even if the through-hole 35 is deviated from the prospective formation position. When the wiring width of the first wiring layer at the prospective formation position of the through-hole is increased, as shown in Fig. 3, however, a wiring pitch is inevitably increased to lead to an increase in chip area. It is, therefore, an object of the present invention to provide a semiconductor device which can connect different wiring layers without increasing a wiring pitch and therefore has a high-density multilayered wiring structure and a method of manufacturing the same. According to a first aspect of the present invention, there is provided a semiconductor device having a multilayered wiring structure having the features of claim 1. According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a multilayered wiring structure, comprising the steps listed in Claim 9. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figs. 1A to 1D are sectional views showing a conventional manufacturing method in an order of steps; Fig. 2 is a plan view showing a pattern of a semiconductor device manufactured by the conventional method shown in Figs. 1A to 1D; Fig. 3 is a plan view showing a pattern of a conventional semiconductor device different from that shown in Fig. 2; Figs. 4A to 4F are sectional views showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention in an order of steps; Fig. 5 is a plan view showing a pattern of a semiconductor device of the present invention manufactured by the method shown in Figs. 4A to 4F; Figs. 6A to 6E are sectional views showing a method of manufacturing a semiconductor device according to the second embodiment of the present invention in an order of steps; and Fig. 7 is a plan view showing a pattern of a semiconductor device according to the third embodiment of the present invention. Embodiments of the present invention will be described below with reference to the accompanying drawings. In a method according to an embodiment shown in Figs. 4A to 4F, a semiconductor device is manufactured as follows. As shown in Fig. 4A, a silicon oxide layer 12 as an insulating interlayer is deposited on a silicon substrate 11 by a normal- or reduced-pressure CVD method. A silicon oxide layer containing phosphorus or phosphorus and boron is used as the silicon oxide layer 12. The thickness of the layer 12 is about 1 µm. As shown in Fig. 4B, an aluminum-containing layer having a thickness of about 400 to 800 nm is formed on the silicon oxide layer 12 by a sputtering method. This aluminum-containing layer is any one of, e.g., a layer consisting of only aluminum, an alloy layer consisting of aluminum and silicon, and an alloy layer consisting of aluminum, silicon, and copper. Subsequently, the aluminum-containing layer is selectively removed by a PEP (Photoengraving Process) and RIE to pattern a first wiring layer 13 having a predetermined wiring width and a predetermined shape. Subsequently, as shown in Fig. 4C, an amorphous silicon layer 14 is deposited to have a thickness of about 200 to 400 nm on the entire surface at a low temperature by a CVD method. As shown in Fig. 4D, the amorphous silicon layer 14 is selectively removed by an anisotropic RIE method to remain on only the side wall of the first wiring layer 13. The width of the remaining layer 14 is substantially the same as its thickness, i.e., about 200 to 400 nm. Subsequently, as shown in Fig. 4E, a thick silicon oxide layer 15 is formed as an insulating interlayer on the entire surface. Since the first wiring layer 13 as an underlying layer contains aluminum, the silicon oxide layer 15 is generally formed by a low-temperature plasma CVD method at a temperature of about 300°C to 350°C. After formation of the silicon oxide layer 15, the surface of the layer 15 is flattened by, e.g., an etch-back method. Subsequently, a through-hole 16 is formed in the layer 15 by PEP and RIE by using a predetermined mask. The opening width of the through-hole 16 is equal to or larger than the wiring width of the first wiring layer 13. As shown in Fig. 4F, a layer consisting of tungsten as a high-melting metal is selectively grown in the through-hole 16 by a reduced-pressure CVD method using a reduction reaction between WF6 (tungsten hexafluoride) gas and H₂ (hydrogen) gas or a reduction reaction between WF6 gas and SiH4 (silane) gas, thereby forming a buried metal layer 17. Thereafter, an alloy layer consisting of aluminum and silicon or an alloy layer consisting of aluminum, silicon, and copper is formed on the entire surface by a sputtering method, and the formed alloy layer is patterned by PEP and RIE, forming a second wiring layer 18. Fig. 5 is a plan view showing a pattern of the semiconductor device manufactured by the above method and corresponding to Fig. 4F. In the method of the above embodiment, the amorphous silicon layer 14 is formed on the side wall of the first wiring layer 13. For this reason, upon formation of the through-hole 16, even if a formation position of the through-hole is deviated from the first wiring layer 13, as shown in Fig. 4F or 5, due to a mask misalignment or a process variation, the amorphous silicon layer 14 serves as a stopper to prevent the underlying silicon oxide layer 12 from being etched. For example, with the present standards of technology, a positional deviation amount including a conversion error upon formation of a through-hole is about 200 to 300 nm. When the amorphous silicon layer 14 is formed to have a thickness of about 400 nm, therefore, the layer 14 can be left with a width of about 400 nm corresponding to the film thickness on the side wall of the first wiring layer 13 in the subsequent etching step. Therefore, even if the above degree of positional deviation occurs, the through-hole 16 is not deviated from the remaining amorphous silicon layer 14. As a result, a leakage current between the second wiring layer 18 and a polycrystalline silicon wiring layer or the silicon substrate 11 or a short circuit between the second wiring layer 18 and another wiring layer can be prevented. In addition, when etching is to be performed to pattern the second wiring layer 18, the buried metal layer 17 having a satisfactory selectivity with respect to the second wiring layer 18 is formed in the through-hole 16. For this reason, even if the second wiring layer 18 is formed to be deviated from the through-hole 16, the first wiring layer 13 is not etched by the presence of the buried metal layer 17. Furthermore, in the method of the above embodiment, since no size margin need be set between the first and second wiring layers 13 and 18 and the through-hole 16, an increase in wiring pitch can be prevented to prevent a chip area from being increased. In the above embodiment, the amorphous silicon layer 14 is formed on the surface of the silicon oxide layer 12 as an insulating interlayer. Since, however any conductive layer having a satisfactory selectivity with respect to the silicon oxide laver 15 upon etching of the layer 15 may be used, a polycrystalline silicon layer, for example, can be used instead of the amorphous silicon layer. In addition, in the above embodiment, the buried metal layer 17 for connecting the first and second wiring layers 13 and 18 is formed by a reduced-pressure CVD method. The layer 17, however, may be formed by forming a tungsten layer on the entire surface by a CVD method and then performing an etch-back method. The second embodiment of the present invention will be described below. A manufacturing method according to the second embodiment is performed in the same manner as that of the first embodiment until a silicon oxide layer 12 as an insulating interlayer is formed on a silicon substrate 11, as shown in Fig. 4A. As shown in Fig. 6A, an aluminum-containing layer 13 having a thickness of about 400 to 800 nm is formed on the silicon oxide layer 12 by a sputtering method, and a tungsten layer 19 is formed thereon. Subsequently, the two metal layers, i.e., the aluminum-containing layer 13 and the tungsten layer 19 as a high-melting metal layer are selectively removed by PEP and RIE to form a first wiring layer 20 having a predetermined wiring width and a predetermined shape by patterning. That is, in this embodiment, the two metal layers are used as the first wiring layer 20. Thereafter, as in the case of the first embodiment, an amorphous silicon layer 14 havin a thickness of about 200 to 400 nm is deposited on the entire surface at a low temperature by a CVD method, as in Fig. 6B. As shown in Fig. 6C, the amorphous silicon layer 14 is selectively removed by an anisotropic RIE method to remain on only the side wall of the first wiring layer 20. Subsequently, as shown in Fig. 6D, a thick silicon oxide layer 15 as an insulating interlayer is formed on the entire surface. Since one of the two layers constituting the first wiring layer 20 as an underlaying layer contains aluminum, formation of the silicon oxide layer 15 is generally performed by a low-temperature plasma CVD method at a temperature of 300°C to 350°C. After the formation of the silicon oxide layer 15, the surface of the layer 15 is flattened by, e.g., an etch-back method. Subsequently, a through-hole 16 is formed in the silicon oxide layer 15 by PEP and RIE by using a predetermined mask. The opening width of the through-hole 16 is equal to or larger than the wiring width of the first wiring layer 20. As shown in Fig. 6E, an alloy layer consisting of aluminum and silicon or an alloy layer consisting of aluminum, silicon, and copper is formed on the entire surface by a sputtering method and patterned by PEP and RIE, thereby forming a second wiring layer 18. That is, in the method of the second embodiment, unlike in the first embodiment, the second wiring layer 18 is directly formed in contact with the first wiring layer 13 without burying a conductive layer in the through-hole 16. In the second embodiment, the first wiring layer 20 is formed of two layers, i.e., the aluminum-containing layer 13 and the tungsten layer 19. Nevertheless, according to the invention, the first wiring layer 20 can be formed of the tungsten layer 19 only. Fig. 7 shows a semiconductor device according to the third embodiment of the present invention. In the semiconductor device of this embodiment, first and second wiring layers 21 and 23 each consisting of polycrystalline silicon are formed instead of the first and second wiring layers 13 and 18, respectively, of the first embodiment. Although the buried metal layer 17 consists of tungsten in each of the above embodiments, any metal can be used as long as it is a high-melting metal and has a low resistivity. As has been described above, according to the present invention, since a through-hole can be formed without increasing a wiring pitch, a semiconductor device having a high-density multilayered wiring structure and a method of manufacturing the same can be provided. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A semiconductor device having a multilayered wiring structure, comprising: a first wiring layer (13; 20; 21) having a predetermined wiring width and formed into a predetermined shape by patterning; a protecting fillet (14) formed on a side wall of said first wiring layer (13; 20; 21); an insulating layer (15) covering said first wiring layer (13; 20; 21) and said protecting fillet (14); an opening (16) formed in said insulating layer (15), and having a width equal to or larger than the wiring width of said first wiring layer; and a second wiring layer (18; 22) formed over the insulating layer (15), patterned in a predetermined shape and connected to said first wiring layer (13; 20; 21). A semiconductor device according to claim 1, further comprising a conductive layer (17) filling said opening (16). A device according to claim 1 or 2, characterized in that said first wiring layer (13) is constituted by one of the following materials aluminum, an alloy consisting of aluminum and silicon, and an alloy consisting of aluminum, silicon, and copper. A device according to claim 1 or 2, characterized in that said fillet (14) is of silicon. A device according to claim 1 or 2, characterized in that said fillet (14) is of amorphous silicon. A device according to claim 2, characterized in that said conductive layer (17) is constituted by a high-melting metal layer. A device according to claim 1 or 2, characterized in that said first wiring layer (20) is constituted by two metal layers including a lower aluminum layer (13) and an upper high-melting metal layer (19). A device according to claim 1 or 2, characterized in that said first wiring layer (20) is constituted by a high-melting metal layer. A method of manufacturing a semiconductor device having a multilayered wiring structure, comprising the steps of: forming a first wiring layer (13; 20; 21) having a predetermined wiring width and a predetermined shape on a first insulating layer (12); forming a protecting fillet (14) on a side wall of said first wiring layer; forming a second insulating layer (15) on the entire surface; forming an opening (16) reaching a surface of said first wiring layer (13; 20; 21) in said second insulating layer (15) said opening (16) having a width equal to or larger than the wiring width of said first wiring layer; and depositing a conductive layer (18) on the entire surface and patterning said conductive layer (18), thus partially filling said opening (16) and thereby forming a second wiring layer (18; 22) connected to said first wiring layer (13; 20; 21). A method according to claim 9, further comprising the step of forming a first conductive layer (17) filling said opening (16) before depositing said conductive layer (18; 22). A method according to claim 9 or 10, characterized in that said step of forming said protecting fillet (14) on said side wall of said first wiring layer (13; 20; 21) includes the substeps of: forming a silicon layer on the entire surface including said first wiring layer (13; 20; 21); and etching said silicon layer by an anisotropic etching method, leaving said silicon layer on only said side wall of said first wiring layer (13; 20; 21). A method according to claim 10, characterized in that said first conductive layer (17) is formed by a reduced-pressure CVD method.

Inventors: IKEDA NAOKI C O INTELLECTUAL P, MATSUOKA FUMITOMO C O INTELLEC, IKEDA, NAOKI, C/O INTELLECTUAL PROPERTY DIV., MATSUOKA, FUMITOMO, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1991
Main classification: H01L21
IPC codes: H01L23, H01L21