Data processor with interleaved DRAM memory

Abstract: A data processor which includes a central processing unit (CPU) coupled to an address bus for supplying an address to an external memory and a data bus for supplying data to the external memory and receiving data from the external memory, and a control logic for controlling data exchange between the CPU and the external memory with a predetermined unit amount of data processing of the central processing unit. The external memory includes first and second DRAMs and the CPU executes the data exchange with units of four words. Each DRAMs has a memory area divided into a number of sub-areas each have four continuous addresses, so that the sub-areas of the first DRAM and the sub-area of the second DRAM are alternately assigned in continuous addresses in one memory space formed of the first and second DRAMs. When an continuous addresses are supplied, a controller controls so that the first and second DRAMs are alternately accessed.

Description: The present invention relates to a data processor, and more specifically to an arrangement locating and controlling external memory devices provided in the data processor. A typical conventional data processor includes a central processing unit (CPU) for executing data processing. The CPU is coupled to an address bus used to supply an address to an external device and a data bus for transferring data between the CPU and the external device. In addition, the CPU is coupled to a control bus used for controlling the external device. A typical CPU is adapted to handle a memory space in such a manner that a plurality of consecutive memory areas are treated as one block. In this CPU, the width of an internal data bus is larger than the width of an external data bus. Therefore, a plurality of external bus cycles can be generated in response to one internal bus cycle. This type of CPU can be exemplified by Intel's microprocessor i8088 and a CPU including a cache controller therein. As known, the cache controller has adopted a data exchange procedure in which a memory space is divided into a plurality of blocks, and data exchange or transfer between a cache memory and an external memory is collectively executed in units of blocks. In addition, the data bus is coupled to a plurality of DRAMs (dynamic random access memory), which constitute external memories for the CPU. Each of the DRAMs is controlled by one corresponding DRAM controller coupled to the address bus. Each DRAM controller is controlled by a control logic which is coupled to the CPU through a control bus in order to interface an operating timing between the control bus and the external device such as the DRAMs and the DRAM controller. Typically, the control logic supplies a common memory read signal and a common memory write signal to all the DRAM controllers. The DRAM controllers are also controlled by a decoder coupled to the address bus so that one of the DRAM controllers is selectively activated in response to a chip select signal generated by the decoder on the basis of the result of decoding of an address on the address bus. The DRAM is configured to be capable of executing a high speed page mode operation, in which if a row address does not change, a data exchange can be executed by changing only a column address and activating a column address strobe again. In a normal access mode, a row address and a column address are applied to the DRAM by executing an address input twice. Therefore, since the input of the row address is unnecessary, the data exchange can be correspondingly executed at a high speed. On the other hand, the DRAM has one restriction in which once a row address strobe is activated, a precharge period in which the row address strobe is made inactive is required. If the precharge period is not satisfied, the content of the DRAM will be lost. Now, assuming that the address bus is composed of 32 bits, and two 1M DRAMs are used, an address of 0000 0000h to 000F FFFFh is assigned to a first DRAM, and an address of 0010 0000h to 001F FFFF h is assigned to a second DRAM, in a memory map of the data processor. Here, the suffix "h" means a hexadecimal notation. In addition, the CPU can access the external device with units of blocks each of which includes a plurality of units of processing, similarly to the type including the cache memory therein. Here, the unit of processing is called a "word". For example, one block includes four words. Under the above mentioned conditions, an operation of the conventional data processor will be discussed. At a T1 clock of a first bus cycle, an address is supplied to the address bus, and decoded by the decoder. If the supplied address designates the first DRAM, the decoder outputs an active chip select signal to a first DRAM controller associated with the first DRAM. On the other hand, a memory access is outputted to the control bus and converted by the control logic into an active memory read signal or into an active memory write signal. Now, assume that the memory read signal has been activated. In response to the active chip select signal and the active memory read signal, the first DRAM controller associated with the first DRAM is activated. As a result, at a falling of the T1 clock, the row address strobe supplied to the first DRAM is activated by the first DRAM controller and thereafter maintained in an active condition. Then, the first DRAM controller supplies an address signal to the first DRAM during a high level period of the T1 clock. At a rising of a T2 clock following the T1 clock, the column address strobe supplied to the first DRAM is activated, so that the content of the first DRAM is outputted to the data bus. At the end of a low level period of the T2 clock, the data exchange is completed, and a first TB clock following the T2 clock rises. The TB clock is used in the high speed page mode operation, and makes it possible to execute the data exchange with only one clock. At rising of the first TB clock, the column address strobe supplied to the first DRAM is inactivated, and a next address is supplied to the first DRAM during a high level period of the TB clock. At falling of the first TB clock, the column address strobe supplied to the first DRAM is activated, and a second data exchange is executed during a low level period of the TB clock. Succeeding to the first TB clock, second and third clocks are generated so that the same memory reading operation (the data exchange) is executed three times. As a result, the data exchange is executed four times in total by the T1 and T2 clocks and the succeeding first to third TB clocks. Following the first bus cycle, a second bus cycle starts, and a T1 clock of the second bus cycle rises at an end of the low level period of the third TB clock of the first bus cycle. At the T1 clock, a next address is supplied to the address bus so that a memory access will be started. However, at falling of the T1 clock of the second bus cycle, the row address strobe supplied to the first DRAM is inactivated, and maintained in an inactive condition for a period corresponding to one clock period, since the period for the precharging is required to have one clock period. As a result, the row address strobe supplied to the first DRAM is activated at falling of the T2 clock of the second bus cycle. Namely, the starting of the memory access in the second bus cycle is delayed from the starting of the memory access in the first bus cycle by a period of time corresponding to one clock. Because of this, a TW clock is inserted between the T2 clock and the first TB clock in the second bus cycle, so that the CPU is brought into a wait condition so as to adjust the timing. This adjustment is controlled by the control logic. As seen from the above, when the same bank of the memory is continuously accessed by the CPU, the data exchange, which will be completed with five clocks in ordinary cases, requires six clocks. As a result, the processing capacity of the data processor will correspondingly decrease. If first and second accesses are made to different banks, respectively, a second access can be completed with five clocks. However, considering a processing situation of the CPU, an instruction reading operation is of course executed for consecutive memory banks, and data processed by the CPU are collectively stored in some region of the memory (localization of access region). Therefore, the possibility of access to the same bank is higher than the possibility of access to different banks. As a result, the possibility of the six clock access is increased. The above mentioned operation timing was made on the basis of clocks. In fact, however, various operating timings of different DRAMs coupled to the CPU must be satisfied. For example, an access period of time from the activation of the column address strobe until the completion of the data exchange must be ensured. Therefore, if the processing capacity of the data processor is increased by increasing the frequency of the clock, the operation based on the T1 and T2 clocks can be adjusted by inserting the TW clock for waiting, but it is not possible to adjust the operation of the TB clock by inserting the TW clock. As a result, there occurs a situation in which the operating timing (for example, the access period of time starting from the activation of the column address strobe) cannot be satisfied. In this situation, the data processor cannot properly operate. In addition, the DRAM has rapid access mode such as the high speed page mode which is higher than the ordinary access operation. However, ROMs (read only memory) and SRAMs (static random access memory) always require the same access time. In the case that these memories are coupled to the CPU, if the CPU is adapted to execute a first memory access by the T1 and T2 clocks and each of succeeding memory accesses by one TB clock as in the conventional example explained hereinbefore, it is required that the memory access can be completed by only one clock. As a result, expensive ROMs or SRAMs are required. Furthermore, if ROMs or SRAMs are used, these memory resources are often located at the outside of the cache coverage. In addition, it is necessary to generate various control signals so that the data exchange between the DRAM and the CPU is executed in the high speed access mode (T1, T2, TB, TB and TB clocks) and the data exchange between the ROM or SRAM and the CPU is executed in a normal access mode (four sets of T1 and T2 clocks). However, if the ROMs or SRAMs are located at the outside of the cache coverage, the performance of the data processor inevitably degrades. If the CPU operates in different modes, the control circuit becomes complicated. A typical conventional DRAM controller as mentioned in the opening part is disclosed in JP-A-1-224850. IBM Technical Disclosure Bulletin, Vol. 22, No.11, April 1980, New York (US), pages 5183-5186 discloses a split cache with variable interleave boundary, wherein the correlation between the cache memory and the main memory is described. US-A-4740911 discloses a data processing system with interleaving. The interleaving is carried out on a double-word-basis, and a memory interleave/non-interleave access is selected depending on the state of the double-word bit of an address. It is an object of the invention to provide a data processor which has overcome the above mentioned defects of the conventional one. Another object of the present invention is to provide a data processor capable of continuously accessing the same region of an external memory with the same period as that required when a different region is accessed. Still another object of the present invention is to provide a data processor capable of accessing a low access speed external memory device apparently as quickly as the data processor accesses a high access speed external memory device. The above mentioned objects are achieved by a data processor as defined in claim 1; the dependent claims are related to preferred embodiments of the invention. The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings. Figure 1 is a block diagram of a data processor useful for understanding the present invention; Figure 2 shows a memory map realized in the data processor shown in Figure 1; Figure 3 is a timing chart showing an operation of the data processor shown in Figure 1, in which two banks of memory are provided and a number of blocks each of which includes four words are located in the interleaved manner; Figure 4 is a block diagram of an embodiment of the data processor in accordance with the present invention; Figure 5 shows a memory map realized in the data processor shown in Figure 4; Figure 6 is a timing chart showing an operation of the data processor shown in Figure 4, in which two groups of memory banks are provided and each of the groups of memory banks includes two banks; Figure 7 is a block diagram of a second embodiment of the data processor in accordance with the present invention; Figure 8 is a truth table illustrating an operation of the selector shown in Figure 7; Figure 9 shows a memory map realized in the data processor shown in Figure 7; Figure 10 is a timing chart showing an operation of the data processor shown in Figure 7, in which two groups of memory banks are provided and each of the groups of memory banks includes four banks; Figure 11 is a logic diagram of the address decoder shown in Figure 1; and Figure 12 shows a memory map realized in a typical conventional data processor. Referring to Figure 1, there is shown a block diagram of a data processor useful for explaining the present invention. The shown data processor includes a central processing unit (CPU) 1 for executing data processing. The CPU is coupled to an address bus 2 used to supply an address to an external device and a data bus 3 for transferring data between the CPU and the external device. In the shown structure, the address bus 2 has a width of 32 bits, and respective bits of the address bus are designated by A 0 , A 1 , ··· A 31 , where the suffix added to the letter "A" shows the bit position. Here, the CPU has a width of an internal data bus which is larger than a width of an external data bus. Therefore, a plurality of external bus cycles can be generated in response to one internal bus cycle. As mentioned hereinbefore, this type of CPU can be exemplified by Intel's microprocessor i8088 and a CPU including a cache controller therein. In addition, the data bus 3 is coupled to a plurality of DRAMs 8-1 DRAMO and 8-2 DRAM1, which constitute external memories for the CPU. DRAMO 8-1 and DRAM1 8-2 are controlled by DRAM controllers (DRAMC) 7-1 and 7-2 coupled to the address bus 2. Each of the DRAM controllers 7-1 and 7-2 is controlled by a control logic 5 which is coupled to the CPU through a control bus 4 in order to interface an operating timing between the control bus 4 and the external device such as the DRAMs and the DRAM controller. The control logic 5 supplies a common memory read signal MRD 9 and a common memory write signal MWR 10 to all the DRAM controllers 7-1 and 7-2 in parallel. The DRAM controllers are also controlled by an address decoder 6 coupled to the address bus 2. The address decoder 6 decodes a portion of an address on the address bus 2 and generates chip select signals MEM0CS and MEM1CS , which are supplied to a chip selection input CS of the DRAM controllers 7-1 and 7-2, respectively. Here, the chip select signals MEM0CS and MEM1CS are active low signals in which the signal is active when it is "0" and inactive when it is "1". In this specification, an upper bar means an active low signal. The control logic 5 receives a bus cycle request from the CPU 1 through the control bus 4, and activates the memory read signal MRD 9 if the memory read is requested, and the memory write signal MWR 10 if the memory write is requested. In addition, when the memory (the external device to the CPU) completes the data exchange, the control logic 5 notifies it to the CPU 1 through the control bus 4. For example, the address decoder 6 is constituted of inverters 12-1 to 12-12, 11-input AND gate 13 and 2-input NAND gates 14-1 and 14-2, connected as shown in Figure 11. Address inputs DA 0 to DA 10 are respectively supplied through the inverters 12-1 to 12-11 to the AND gate 13, whose output is connected to the NAND gates 14-1 and 14-2. A bank input BNK is supplied through the inverter 12-12 to the NAND gate 14-1 and directly to the NAND gate 14-2. With this arrangement, if all of address inputs DA 0 to DA 10 are of "0" and the BNK input is also of "0", the NAND gate 14-1 activates the chip select signal MEM0CS . When all of address inputs DA 0 to DA 10 are of "0" and the BNK input is of "1", the NAND gate 14-2 activates the chip select signal MEM1CS . The DRAM controllers 7-1 and 7-2 have the same construction, and therefore, inputs and outputs are shown only for the DRAM controller 7-1. When a chip select input CS is active and when either the memory read signal MRD 9 or the memory write signal MWR 10 is active, the DRAM controller operates to control the associated DRAM. The DRAM controller has address inputs RA 0 to RA 19 , and operates to supply the address inputs RA 10 to RA 19 (often called a "row address") to address outputs MA 0 to MA 9 , coupled to an address input port of the associated DRAM. At the same time, the DRAM controller activates the row address strobe RAS . At this time, if the memory write signal MWR is active, the DRAM controller activates a write enable signal WE . Thereafter, the DRAM controller operates to supply the address inputs RA 0 to RA 9 (often called a "column address") to the address outputs MA 0 to MA 9 and at the same time, activates the column address strobe CAS . Each of the DRAMs 8-1 and 8-2 is configured to be capable of executing the high speed page mode operation as already explained hereinbefore The above mentioned arrangement and construction are fundamentally the same as those of the conventional data processor. However, here the BNK input of the address decoder 6 is connected to the address bit A 2 of the address bus 2, and the address inputs DA 0 to DA 10 of the address decoder 6 are connected to the address bits A 21 to A 31 . On the other hand, the address inputs RA 0 to RA 19 of each DRAM controller are connected to the address bits A 0 , A 1 , A 3 to A20. (For reference, in a typical conventional data processor, the BNK input of the address decoder 6 is connected to the address bit A 20 of the address bus 2, and the address inputs RA 0 to RA 19 of each DRAM controller are connected to the address bits A 0 to A 19 .) Referring to Figure 2, there is shown a memory map realized in accordance with the above mentioned connection between the address bus and the address decoder and the DRAM controllers. As shown in Figure 2, addresses 00000000 h to 00000003 h , 00000008 h to 0000000B h , 00000010 h to 00000013 h , 00000018 h to 0000001B h , ··· are assigned to the DRAMO 7-1. On the other hand, addresses 00000004 h to 00000007 h , 0000000C h to 0000000F h , 00000014 h to 00000017 h , 0000001C h to 0000001F h , ··· are assigned to the DRAM1 7-2. Namely, the memory banks are located by units of 4 words in the interleaved manner, differently from the conventional data processor in which, for example, memory banks are continuously located as shown in Figure 12. Referring to Figure 3, there is shown a timing chart illustrating the operation of the data processor shown in Figure 1. Assume that the address "0" is outputted to the address bus at a T1 clock in a first cycle. The address decoder 6 decodes the address "0" and activates the chip select signal MEM0CS . In response to this signal, the DRAM controller 7-1 activates the row address strobe RAS at a falling of the T1 clock, so that access to the DRAM 8-1 starts. Thereafter, the row address strobe RAS is maintained in the active condition. Then, the DRAM controller 7-1 supplies an address signal of MA 0 to MA 9 to the DRAM 8-1 during a high level period of the T1 clock. At a rising of a T2 clock following the T1 clock, the column address strobe CAS supplied to the DRAM 7-1 is activated, so that a data exchange between the DRAM 7-1 and the CPU 1 is executed through the data bus 3. At an end of a low level period of the T2 clock, the data exchange is completed, and a first TB clock following the T2 clock rises. At a rising of the first TB clock, the column address strobe CAS supplied to the DRAM 8-1 is inactivated, and a next address of MA 0 to MA 9 is supplied to the DRAM 8-1 during a high level period of the TB clock. At a falling of the first TB clock, the column address strobe CAS supplied to the DRAM 8-1 is activated, and a second data exchange is executed during a low level period of the TB clock. Following the first TB clock, second and third clocks are generated so that the same memory reading operation (the data exchange) is executed three times. As a result, the data exchange is executed four times in total by the T1 and T2 clocks and the succeeding first to third TB clocks. Thus, data are read from or written to the addresses of 00000000 h to 00000003 h in the memory map shown in Figure 2. Now, assume that an address of "4" is outputted to the address bus 2 in a T1 clock of a second cycle succeeding to the first cycle. In this situation, the chip select signal MEM0CS is inactivated and the chip select signal MEM1CS is activated. As a result, the access to the DRAM1 8-2 is executed completely similarly to the above mentioned access to the DRAMO 8-1. At this time, the DRAM controller 7-1 inactivates the row address strobe RAS , so that the precharging period can be ensured for the DRAMO 8-1. As a result, data are read from or written to the addresses of 00000004 h to 00000007 h in the memory map shown in Figure 2. As seen from the above, although the data are read from or written to apparently continuous addresses in the memory, the memory access is alternately executed to the DRAMO 8-1 and the DRAM1 8-2, so that the delay of the access time caused for the precharging will not occur. The above mentioned structure is such that, in the memory space, memory blocks each composed of four words are located in the interleaved manner. The reason for this is that the CPU under consideration can access four words as one block. For example, if the CPU is adapted to access sixteen words as one block, memory blocks each composed of sixteen words are located in the interleaved manner. In this case, the BNK input of the address decoder 6 is connected to the address bit A4 of the address bus 2, and the address inputs DA 0 to DA 10 of the address decoder 6 are connected to the address bits A 21 to A 31 . On the other hand, the address inputs RA 0 to RA 19 of each DRAM controller are connected to the address bits A 0 , A 1 ,A 2 ,A 3 , A 5 , to A 20 . Referring to Figure 4, there is shown an embodiment of the invention. This first embodiment is adapted to adjust a mismatching of the operating timing with the TB clocks, which is the second problem of the prior art discussed hereinbefore. In Figure 4, elements similar to those shown in Figure 1 are given the same Reference Numerals and explanation thereof will be omitted. In the first embodiment, four DRAMs 8-1 to 8-4 are provided, and each of these DRAMs is similar to the DRAMs shown in Figure 1. The embodiment includes inverters 15-1 to 15-4, two-input NAND gates 16-1 to 16-4, bidirectional buffers 17-1 to 17-4 having a latch function. When an input E is active, the buffer is open. On the other hand, if an input D is "1", data are supplied from the data bus 3 to the DRAM, and when the input D is "0", data are supplied from the DRAM to the data bus 3. DRAM controllers 18-1 to 18-4 are associated to the DRAMs 8-1 to 8-4. These DRAM controllers 18-1 to 18-4 operate basically similarly to the conventional DRAM controller and the DRAM controller shown in Figure 1. However, the DRAM controllers 18-1 to 18-4 have a different high speed page mode, an operating timing of which will be explained hereinafter. The BNK input of the address decoder 6 is connected to the address bit A 2 of the address bus 2, and the address inputs DA 0 to DA 9 of the address decoder 6 are connected to the address bits A 22 to A 31 . The address input DA 10 of the address decoder 6 is grounded. On the other hand, the address inputs RA 0 to RA 19 of each of the DRAM controllers 18-1 to 18-4 are connected to the address bits A 1 and A 3 to A 21 . The E input of the buffer 17-1 is connected to receive the output of the NAND gate 16-1 receiving the output of the inverter 15-2 receiving the MEM0CS signal and the output of the inverter 15-1 receiving the address bit A 0 . The E input of the buffer 17-2 is connected to receive the output of the NAND gate 16-2 receiving the address bit A 0 and the output of the inverter 15-2. The E input of the buffer 17-3 is connected to receive the output of the NAND gate 16-3 receiving the output of the inverter 15-3 receiving the MEM1CS signal and the output of the inverter 15-4 receiving the address bit A 0 . The E input of the buffer 17-4 is connected to receive the output of the NAND gate 16-4 receiving the address bit A 0 and the output of the inverter 15-3. On the other hand, the D input of each of the buffers 17-1 to 17-4 is connected to receive the memory write signal 10. Referring to Figure 5, there is shown a memory map realized in the first embodiment. As shown in Figure 5, addresses of 00000000 h , 00000002 h , 00000008 h , 0000000A h ; ··· are assigned to the DRAM00 8-1. Addresses of 00000001 h , 00000003 h , 00000009 h , 00000008 h ,··· are assigned to the DRAM01 8-2. Addresses of 00000004 h , 00000006 h , 0000000C h , 0000000E h , ··· are assigned to the DRAM10 8-3. Addresses of 00000005 h , 00000007 h , 0000000D h , 0000000F h ; ··· are assigned to the DRAM11 8-4. Referring to Figure 6, there is shown a timing chart illustrating the operation of the first embodiment of the data processor shown in Figure 4. The address on the address bus changes at a T1 clock in a first cycle. The address decoder 6 activates the chip select signal MEM0CS . In response to this signal, the DRAM controllers 18-1 and 18-2 activate the row address strobe RAS , so that access to the DRAM00 8-1 and DRAM01 8-2 starts. Thereafter, at a rising of a T2 clock following the T1 clock, the column address strobe CAS of the DRAM controllers 18-1 and 18-2 is activated, so that a data exchange between the DRAM00 8-1 and the DRAM01 8-2 and the CPU 1 becomes possible. At this time, the E input of the buffer 17-1 is activated, a data exchange between the DRAM00 8-1 and the CPU 1 is executed. At a first TB clock, the address changes, with the result that the E input of the buffer 17-2 is activated, a data exchange between the DRAM01 8-2 and the CPU 1 is executed. On the other hand, at a rising of the first TB clock, the column address strobe CAS is inactivated. At a rising of a second TB clock, the column address strobe CAS is activated, again. The DRAM10 and the DRAM11 sequentially execute the data exchange, similarly to the DRAM00 and the DRAM01. After the end of the third TB clock, and at a T1 clock of a second cycle, the address changes, the chip select signal MEM0CS is inactivated and the chip select signal MEM1CS is activated. Therefore, the first embodiment can ensure the precharging time, similarly to the data processor of fig. 1. In the first embodiment, the transition timing of the column address strobe CAS from the active condition to the inactive condition and vice versa is expanded to one clock, while the transition timing is a half clock in the structure of fig. 1. Therefore, the controlling timing of the DRAMs can be relaxed. Referring to Figure 7, there is shown a second embodiment. In Figure 7, elements similar to those shown in Figures 1 and 4 are given the same Reference Numerals and explanation thereof will be omitted. In the second embodiment, the memory includes eight banks. The second embodiment includes selectors 22-1 and 22-2. The operation of each selector is illustrated in the truth table shown in Figure 8. When a G input of each selector is inactive, Y 0 , Y 1 Y 2 and Y 3 outputs are inactive ("1"). When the G input is active, if A and B inputs are "0, 0", Y 0 is active, and if A and B inputs are "0, 1", Y 2 is active. If A and B inputs are "1, 0", Y 1 is active, and if A and B inputs are "1, 1", Y 3 is active. DRAM controllers 19-1 to 19-8 will be explained hereinafter when the operating timing is explained. These DRAM controllers 19-1 to 19-8 are associated to eight DRAMs 20-1 to 20-8 (DRAM00 to DRAM03 and DRAM10 to DRAM13). Buffers 21-1 to 21-8 have the same function as the buffer 17 shown in Figure 4. The BNK input of the address decoder 6 is connected to the address bit A 2 of the address bus 2, and the address inputs DA 0 to DA 8 of the address decoder 6 are connected to the address bits A 23 to A 31 . The address inputs DA 9 and DA 10 of the address decoder 6 are grounded. On the other hand, the address inputs of each DRAM controller are connected to the address bits A 3 to A 22 . In addition, the A and B inputs of each selector are connected to the address bits A 0 and A 1 . The G input of the selector 22-1 is connected to receive the MEM0CS signal, and the G input of the selector 22-2 is connected to receive the MEM1CS signal. Referring to Figure 9, there is shown a memory map realized in the third embodiment. As shown in Figure 9, addresses of 00000000h, 00000008 h , ··· are assigned to the DRAM00. Addresses of 00000001h, 00000009 h , ··· are assigned to the DRAM01. Addresses of 00000002 h , 0000000A h , ··· are assigned to the DRAM02. Addresses of 00000003 h , 0000000B h , ··· are assigned to the DRAM03. Addresses of 00000004 h , 0000000C h , ··· are assigned to the DRAM10. Addresses of 00000005h, 0000000D h , ··· are assigned to the DRAM11. Addresses of 00000006h, 0000000E h , ··· are assigned to the DRAM12. Addresses of 00000007 h , 0000000F h , ··· are assigned to the DRAM13. Referring to Figure 10, there is shown a timing chart illustrating the operation of the second embodiment of the data processor shown in Figure 7. If the address on the address bus changes at a T1 clock in a first cycle, the address decoder 6 activates the chip select signal MEM0CS . In response to this signal, the DRAM controllers 19-1 to 19-4 activate the row address strobe RAS , so that access to the DRAM00 to DRAM03 starts. In response to the address outputted in synchronism to the Tl clock, the Y 0 output of the selector 22-1 is activated, so that a data exchange between the DRAM00 and the CPU 1 is executed at the end of the T2 clock, namely at a rising of a first TB clock. Similarly, at the first TB clock, the Y 1 output of the selector 22-1 is activated, so that a data exchange between the DRAM01 and the CPU 1 is executed. The Y 2 output of the selector 22-1 is activated at the second TB clock, so that a data exchange between the DRAM02 and the CPU 1 is executed. The Y 3 output of the selector 22-1 is activated at the third TB clock, so that a data exchange between the DRAM03 and the CPU 1 is executed. In the second embodiment, since the four DRAMs (DRAM00 to DRAM03 or DRAM10 to DRAM13) are driven at the same one-time timing, the DRAM high speed page mode access is not used. Therefore, the DRAMs and the DRAM controllers can be replaced by memories which have a constant access speed.

Claims: A data processor with high speed memory access comprising: a central processing unit (CPU, 1); an external memory composed of 2 n dynamic random access memory banks (DRAM, 8,20) having the same structure where n ≥2, data stored in said external memory being divided into blocks of data having a plurality of words and stored in said DRAM banks in an interleaved manner; said central processing unit performing block transfers to and from the external memory, a plurality of DRAM controllers (18, 19), one for each of said DRAM banks, for generating a row address strobe ( RAS ), a column address strobe ( CAS ) and a write enable strobe ( WE ) to control a corresponding one of said DRAM banks; an address bus (2) connected to said CPU and said plurality of DRAM controllers for supplying an address to said external memory; an address decoder (6) connected to said address bus for decoding a portion of said address related to the block size and generating two chip select signals (11) for selecting alternate groups of 2 n-1 DRAM banks in said external memory; wherein words belonging to the same block are stored in the same group of memory banks, a plurality of buffers (17, 21), one for each of said DRAM banks, connected to receive data from or supply data to a corresponding one of said DRAM banks, data from DRAM banks within a group being simultaneously accessed by one of said chip select signals; a data bus (3) connected to said CPU and said plurality of buffers for supplying blocks of data to said external memory and receiving blocks of data from said external memory; control logic connected to said CPU for generating memory read and memory write signals (9, 10) to said DRAM controllers to control data exchange between the CPU and the external memory; and selecting logic (15, 16, 22) connected to said address bus and responsive to said chip select signals (11) for generating enable signals to said buffers for sequentially enabling data exchange between said buffers for a group of DRAM banks and said data bus. The data processor recited in claim 1 wherein the number of DRAM banks is four (n=2) and the CPU executes a data exchange with blocks of four words, each DRAM bank (8) having a memory area divided into a number of sub-areas each having contiguous addresses, so that the sub-areas of a first pair of DRAM banks and the sub-areas of a second pair of DRAM banks are alternately assigned in contiguous addresses in one memory space formed of the four DRAM banks, and when contiguous addresses are supplied, the first and second pairs of DRAM banks are alternately accessed by said DRAM controllers, and said selecting logic comprises: first and second inverters (15-2, 15-3) connected to receive respective ones of said chip select signals (11) and generating an inverted output signal; third and fourth inverters (15-1, 15-4) connected to receive a selected bit of said address and generating an inverted output signal; first and second NAND gates (16-1, 16-2) each connected to receive the inverted output signal from said first inverter (15-2), said first NAND gate also receiving the inverted output signal from said third inverter (15-1) and said second NAND gate also receiving the selected address bit input to said third inverter (15-1), said first NAND gate generating an enable signal to a first one (17-1) of said plurality of buffers and said second NAND gate generating an enable signal to a second one (17-2) of said plurality of buffers; and third and fourth NAND gates (16-3, 16-4) each connected to receive the inverted output signal from said second inverter (15-3), said third NAND gate also receiving the inverted output signal from said fourth inverter (15-4) and said fourth NAND gate also receiving the selected address bit input to said fourth inverter, said third AND gate generating an enable signal to a third one (17-3) of said plurality of buffers and said fourth NAND gate generating an enable signal to a fourth one (17-4) of said plurality of buffers. The data processor recited in claim 1 wherein the number of DRAM banks is eight ( n =3) and the CPU executes a data exchange with blocks of four words, each DRAM bank (20) having a memory area divided into a number of sub-areas each having contiguous addresses, so that the sub-areas of a first four DRAM banks (20-1 - 20-4) and the sub-areas of a second four DRAM banks (20-5 - 20-8) are alternately assigned in contiguous addresses in one memory space formed of the eight DRAM banks, and when contiguous addresses are supplied, the first four and second four DRAM banks are alternately accessed by said DRAM controllers (19), and said selecting logic (22) comprises: first and second logic circuits (22-1, 22-2) connected to receive respective ones of said chip select signals (11-1, 11-2) and first and second bits (A, B) of said address to generate four enable signals ( Y 0 , Y 1 , Y 2 , Y 3 ), said first logic circuit (22-1) controlling a first four (21-1 - 21-4) of said buffers and said second logic circuit (22-2) controlling a second four (21-5 - 21-8) of said buffers, said first and second logic circuits being defined by the following truth table: INPUT OUTPUT G B A Y 0 Y 1 Y 2 Y 3 0 0 0 0 1 1 1 0 0 1 1 0 1 1 0 1 0 1 1 0 1 0 1 1 1 1 1 0 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 where G represents one of said chip select signals (11-1, 11-2).

Inventors: KOIKE TSUNEO, KOIKE, TSUNEO, KOIKE, TSUNEO, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: G06F12
IPC codes: G06F12