System for transferring data between IC chips

Abstract: The invention relates to a system for transferring data via a data transfer bus (102) between IC chips (e.g. 104) which internally utilize signals at first and second CMOS logic voltage levels. The system includes means (114, 116) for charging the data transfer bus (102) to a voltage representing a third logic level, and pull-down means (118) for pulling the voltage on said data transfer bus (102) down to a voltage representing a fourth logic level, the voltage swing between said third and fourth logic levels being lower than the voltage swing between said first and second logic levels, thereby increasing the data transfer speed.

Description: The present invention as it is defined in the appended claims relates to a system for transferring data via a data transfer bus between integrated circuit (IC) chips, such as microprocessor chips. IC chips using complementary metal-oxide-semiconductor (CMOS) technology have advantages when compared to those using emitter-coupled logic (ECL) technology. Among the advantages are lower power consumption and hence lower cooling requirements, and lower construction cost. However, CMOS chips are inferior to ECL chips in both intra-chip and inter-chip operation speeds. The aforementioned advantages of ECL chips are mainly due to a lower voltage swing between logic low and logic high levels (-1.7 to -0.9 volts for ECL, 0 to 5 volts for CMOS), and fewer transmission line effects resulting from impedance matching. Prior art CMOS data transfer systems exist for intra-chip communication which limit data bus swings to ECL levels, and employ CMOS-to-ECL converters, and vice versa. What is desired is a CMOS inter-chip data transfer system which limits voltage swings to increase data transfer speed, but without the need for CMOS-to-ECL converters. The documents Patent Abstract of Japan, Vol. 12, no. 268 (E-638)(3115) 27 July 1988 and JP-A-63 050 209 disclose a device for limiting the output voltage swing of a logic circuit. Thus, it is an object of the present invention to provide an inter-chip data transfer system with high data transfer speed, but without the need for a significant increase in circuitry. According to the invention there is provided a system for transferring data via a data transfer bus between IC chips which internally utilize signals at first and second logic voltage levels, characterized by means for charging said data transfer bus to a voltage representing a third logic level, and pull-down means for pulling said data transfer bus down to a voltage representing fourth logic level, the voltage swing between said third and fourth logic levels being less than the voltage swing between said first and second logic levels. One embodiment of the present invention will now be described by way of example with reference to the accompanying Figs. 1A and 1B which together represent a detailed schematic diagram of a data transfer system in accordance with the invention. The drawing shows the preferred embodiment for a high speed inter-IC chip data transfer system 100 implemented using CMOS technology and having a data transfer bus or transmission line 102 that transfers data in the form of logic high and logic low voltages. All transistors are of the junction field-effect type (JFET), with a bubble at the gate indicating a p-channel device, and the absence of a bubble at the gate indicating an n-channel device. A group of presently inventive identical transceivers 104, 106, 108 and 110 capable of transmitting and receiving data signals connect to the transmission line 102, which transmission line has a characteristic impedance Z 0 of 100 ohms, for example. The number of transceivers included in the system 100 is a matter of design choice. Since all of the transceivers are identical, only the one numbered 104 will be described in detail. The logic levels on the transmission line 102 are 2.5 volts for logic high, and 1.6 volts for logic low, in the preferred embodiment. This allows for low voltage swings, and hence faster transmission line transition times between the two logic states. Recall that this differs from the normal ECL logic levels of -0.9 volts and -1.7 volts. The transceiver 104 is connected to the transmission line 102 at a node 112, and is terminated by a 100 ohm resister 114. The resistor (R1) 114 is connected to a voltage terminal 116 which is in turn connected to a 2.5 volt voltage source. The voltage source at 116 acts as a transmission line pre-charger to pre-charge the transmission line 102 to 2.5 volts. A node 190, resistor (R2) 192 and a terminal 194 connected to a 2.5 volt voltage source at the other end of the transmission line 102 also serve to terminate the transmission line, and are identical in function to elements 112, 114 and 116, respectively. By terminating the transceivers in the transmission line characteristic impedance as described above, data signal reflections and "ringing" are eliminated. In addition to the low voltage swings, the impedance matching further increases the data transfer speed. The two major components of the transceiver 104 are a transmitter 118 and a receiver 138. All voltage sources internal to the transceiver 104 are at the CMOS levels, i.e. 5 volts representing the logic high level, and 0 volts representing the logic low level. A logical NOR gate 120 along with two transistors 128 and 132 make up the transmitter 118, the transistor 128 serving as a switch. The input signals to the NOR gate 120 are an "enable data" signal ED1/ (active low) on input line 122, and a "data" signal D1 on the input line 124. When the signal ED1/ is high, the NOR gate 120 outputs a low signal over the line 126 to the transistor 128. This in turn keeps the transistor 128 off (non-conducting) so that the transmitter 118 is off. Thus, the transmission line 102 is at the relative logic high level of 2.5 volts, and transceivers other than the one numbered 104 are free to send data over the transmission line 102. When the signal ED1/ is low, however, the output of the transmitter is directly related to the signal D1. (If D1 is a logic high signal of 5 volts, the output of the transmitter is a relative logic high signal of 2.5 volts; if D1 is logic low signal of 0 volts, the output of the transmitter is a relative logic low signal of 1.6 volts.) This action is accomplished as follows. When D1 is a logic high signal the transistor 128 stays in the non-conducting state; therefore the transmission line 102 stays at the relative logic high level. When D1 is a logic low signal, the transistor 128 assumes the conducting state. Transistor 132 is connected at its gate and drain to the node 130, and at its source to ground at 134. Initially, the 2.5 volts being passed by the transistor 128 to the node 130 causes the transistor 132 to conduct, thereby pulling down the transmission line voltage. Transistor 132 is sized such that as the voltage appearing at the node 130 is lowered by the pull-down effect, the transistor 132 ceases to conduct at 1.6 volts rather than 0 volts. Therefore, the transmission line voltage cannot fall below 1.6 volts in the preferred embodiment. The receiver 138 has a reference voltage generator 140 and a differential receiver or amplifier 154. The reference voltage generator 140 consists of a transistor pair 144, 150 which generates a reference or threshold voltage V out on node 146 in a manner well-known in the art. As can be seen from Fig. 1A, the transistor 144 is connected to a voltage source V ss at terminal 142, and the transistor 150 is connected to ground at 152, and the gates of the transistors 144 and 150 are connected to a node 148 which is connected to the node 146. The reference voltage is 2 volts in the preferred embodiment, which is approximately at the centre of the transmission line voltage swing. That is to say, all voltages received from the transmission line 102 which are greater than 2 volts are presumed to reflect logic high signals, and all voltages received from the transmission line which are below 2 volts are presumed to reflect logic low signals. The reference voltage V out is supplied to the differential receiver 154, primarily consisting of transistors 156, 160, 168, 174, 178, and 182, which differential receiver 154 compares the data signals received from the transmission line 102 via line 113 with the reference value so that when the reference value is exceeded, the output of the receiver 138 on line 188 is CMOS logic high, and when the reference value is not exceeded, the output of the receiver 138 on line 188 is CMOS logic low. The transistors 168 and 174 are connected by their terminals 166 and 172, respectively, to the voltage source V ss . The signal ER1/ (active low) on line 164 is an "enable read" signal which enables the receiver 154 to receive data signals when it is active, and disables the receiver 154 when it is inactive. In the enabled state, if the data signal received on line 113 is below the reference voltage the transistor 156 is turned off, while the transistor 178 is turned on by the threshold voltage. The output of the differential receiver 154 is at a node 158. The conduction of the transistor 178 pulls the gate voltage of the transistor 168 low via node 176 and line 170, thereby causing the transistor 168 to turn on. Thus 5 volts (V ss ) connected to the terminal 166 is passed by the transistor 168 to the output node 158. When the data signal received on line 113 is above the reference value, the transistor 156 turns on to pull the output node 158 low, while the transistors 178 and 168 are turned off. It should be noted that when ER1/ is inactive the transistor 160 conducts to pull the output node 158 low. The transistor 182 is a current limiter which limits the amount of current which can flow through the transistors 156, 160 and 178. In addition to inverting the output of the receiver 154, an inverter 186 also aids in driving low voltages which are below approximately 0.9 volts, because of limitations of the preferred embodiment of the receiver. The inverter 186 is connected to the output line 188 of the receiver 138. The data signals which appear at the output of the receiver 138 are designated "DINl/" in the drawing. Variations and modifications to the present invention are possible given the above disclosure. For example, a voltage other than 2.5 volts can be used to pre-charge the transmission line. Also, the transistor 132 can be sized such that it cuts off at a voltage other than 1.6 volts. Additionally, the threshold voltage generated by the reference voltage generator can be different from the 2 volts disclosed if the voltage swing on the transmission line is other than that for the preferred embodiment.

Claims: A system for transferring data via a data transfer bus (102) between IC chips (104-110) which internally utilize signals at first and second logic voltage levels, characterized by means (114,116) for charging said data transfer bus (102) to a voltage representing a third logic level, and pull-down means (118) for pulling said data transfer bus down to a voltage representing a fourth logic level, the voltage swing between said third and fourth logic levels being less than the voltage swing between said first and second logic levels. A system according to claim 1, characterized in that all said logic levels are of the same algebraic sign. A system according to either claim 1 or claim 2, characterized in that said first and second logic levels represent the logic levels of complementary metal-oxide-semiconductor (CMOS) technology. A system according to claim 3, characterized in that said third and fourth logic levels substantially equal 2.5 volts and 1.6 volts, respectively. A system according to any one of the preceding claims, characterized in that said pull-down means (118) includes a transistor (132) which is arranged to conduct during pull-down of the voltage on said data transfer bus (102), and which is arranged to cease to conduct when the voltage on said data transfer bus reaches said fourth logic level. A system according to claim 5, characterized in that said transistor (132) is an n-channel device connected via switch means (128) to said data transfer bus (102). A system according to claim 6, characterized in that the source of said transistor (132) is connected to ground, and in that the gate and drain of said transistor are connected together and to said data transfer bus (102) via said switch means (128). A system according to either claim 6 or claim 7, characterized in that said switch means is formed by a further transistor (128). A system according to any one of the preceding claims, characterized by differential amplifier means (154, 186) arranged to receive data from said data transfer bus (102) and arranged to convert received data at said third and fourth logic levels to said first and second logic levels. A system according to claim 9, characterized by reference voltage generator means (140) arranged to generate a reference voltage which is between said third and fourth logic levels, said differential amplifier means (154, 186) being arranged to compare a voltage received from said data transfer bus (102) with said reference voltage, and arranged to generate said first logic level if the received voltage is greater than said reference voltage and to generate said second logic level if the received voltage in less than said reference voltage.

Inventors: DONAHUE JAMES A, SANWO IKUO J, DONAHUE, JAMES A., SANWO, IKUO J.
Applicants: NCR INT INC, NCR INTERNATIONAL INC.
Application year: 1991
Main classification: G06F13
IPC codes: H03K19, G06F3