Synchronizing circuit

Abstract: The horizontal synchronous signal and the vertical synchronous signal included in a composite synchronous signal which is output from one TV camera are separated from the composite synchronous signal. A plurality of TV cameras are controlled on the basis of the horizontal synchronous signal and the vertical synchronous signal so as to produce synchronized video signals from the plurality of TV cameras. These synchronized video signals are easy to compound. In the blanking period of the vertical synchronous signal, the rise period of the synchronous signal is 1/2 of the period of the vertical synchronous signal. Pulses are eliminated alternately in the blanking period by a half killer circuit including a counter and a decoder and having a simple structure, thereby generating a horizontal synchronous signal appropriate for driving the TV cameras. The counter composed of Johnson counters connected in multiple stages reduces the amount of current flowing to the counter, thereby eliminating the deleterious influence on the TV cameras.

Description: The present invention relates to an image pickup system for transmitting a video signal including a synchronous signal from a device on the transmission side to a device on the reception side and reproducing the video signal on the reception side and, more particularly, to a synchronous signal generator for generating a synchronous signal on the transmission side and a synchronizing circuit for synchronizing the operation on the transmission side with the synchronous signal. In the case of constituting an image pickup system by a plurality of TV cameras as a monitor system by monitor cameras, it is required to synchronize the operations of the TV cameras with each other in order to enable the synchronous processing of a plurality of images. The timings for the operations of the respective cameras are generally set on the basis of the reference clocks from oscillators which are provided in the respective TV cameras. The TV cameras are operated at their own timings unless they are caused to agree with each other in advance. In order to synchronize the operations of the TV cameras, a synchronous signal common to these cameras is conventionally provided in a conventional image pick up system. Fig. 1 shows the waveform of a composite synchronous signal CSY for obtaining the timing for the operation of a TV camera of an NTSC system. The composite synchronous signal CSY is input to a TV camera from an external circuit and includes a horizontal synchronous signal HSY, a vertical synchronous signal VSY and equalizing pulses EQP. These horizontal synchronous signal HSY, vertical synchronous signal VSY and equalizing pulse EQP are arranged in a predetermined order in time series. The horizontal synchronous signal HSY and the vertical synchronous signal VSY are separated from the composite synchronous signal CSY by a differentiator and an integrator. That is, the horizontal synchronous signal HSY is obtained by differentiating the composite synchronous signal CSY to detect the trailing edge of the signal and the vertical synchronous signal VSY is obtained from a change in the integrated value of composite synchronous signal CSY. Fig. 2 is a block diagram of the structure of a known synchronizing circuit for obtaining the horizontal synchronous signal HSY and the vertical synchronous signal VSY from the composite synchronous signal CSY. A hybrid signal HYB input from an external circuit is separated into a video signal VDO for a video component and a composite synchronous signal CSY for a synchronous component by a synchronous signal separator 1, and the composite synchronous signal CSY is further input to a vertical/horizontal separator 2. The vertical/horizontal separator 2 detects the trailing edge of the signal by differentiating the composite synchronous signal CSY, thereby obtaining a horizontal synchronous signal HSY 0 and integrates the composite synchronous signal CSY and obtains a vertical synchronous signal VSY from a change in the integrated value. A voltage-controlled oscillator (VCO) 3 generates a reference clock MCK in accordance with the output PDO of a later-described phase comparator 4. A counter 5 counts the reference clocks MCK. The counter is reset by the vertical synchronous signal VSY and outputs the count value to a decoder 6. The decoder 6 generates the horizontal synchronous signal HSY from the count value of the counter 5. The horizontal synchronous signal HSY is input to the phase comparator 4 together with the horizontal synchronous signal HSY 0 output from the vertical/horizontal separator 2. The phase comparator 4 compares the phases of the horizontal synchronous signal HSY 0 and the horizontal synchronous signal HSY and supplies the output PDO to the VCO 3, thereby constituting a PLL (Phase Locked Loop). In this way, the horizontal synchronous signal HSY is synchronized with the horizontal synchronous signal HSY 0 which is separated from the composite synchronous signal CSY. In an image pickup system using a plurality of TV cameras, the hybrid signal HYB including a synchronous component is output from a reference TV camera and input to the respective TV cameras. In the reference camera for generating the hybrid signal HYB, a TV synchronous signal having a predetermined format is generated in the TV camera, and the scanning timing for an image sensor is set on the basis of the synchronous signal. A driving circuit for driving the image sensor of the TV camera is composed of a circuit of a synchronizing system for generating synchronous signals and a circuit of a driving system for generating an image sensor driving clock. These circuits are composed of one chip as a single integrated circuit. However, when these circuits are composed of one chip, there are problems of beat noise generated by the difference in oscillators and the periodical noise generated by the operation of the counter provided in the circuit of the synchronizing system. Although the beat noise can be eliminated by using an oscillator in common to both circuits, it is impossible to eliminate the periodical noise because the operation of the counter itself causes the power source noise. In the synchronizing circuit on the side of receiving the hybrid signal HYB, since analog circuits such as the differentiator and the integrator are mainly used in order to obtain the horizontal synchronous signal HSY and the vertical synchronous signal VSY by separating them from the composite synchronous signal CSY, it is necessary to take the delays of these analog circuits into adequate consideration. However, since the delays of these analog circuits are dependent on a temperature, it is very difficult to determine various parameters with due consideration for the delays. In obtaining the horizontal synchronous signal HSY, in order to discriminate the equivalent pulse EQP having a period equivalent to 1/2 of the period of the horizontal synchronous signal HSY, a strobe pulse is set by using a counter which operates with the horizontal scanning period H in accordance with the trailing edge of the composite synchronous signal CSY, thereby eliminating the equivalent pulse EQP. However, since the counter which operates during the horizontal scanning causes beat noise, the periodical noise is superimposed on the video signal and vertical fringes are produced on the reproduced picture. If the oscillation range of the VCO 3 is narrow, the time required for the PLL to be locked, in other words, the time required for the horizontal synchronous signal HSY to be synchronous with the horizontal synchronous signal HSY 0 is long, which sometimes delays the synchronisation of the apparatus. Accordingly, it is an object of the present invention to eliminate the above-described problems in the related art and to stably separate the horizontal synchronous signal HSY and the vertical synchronous signal VSY from the composite synchronous signal CSY, shorten the synchronisation time of the apparatus and easily synchronize the operation of a TV camera with the composite synchronous signal CSY without using an analog circuit. To achieve this aim, there is provided a synchronizing circuit having the features indicated in claim 1 or 5. The invention is further developped by the features mentioned in the subclaims. In this way, it is possible to separate the horizontal synchronous signal from the composite synchronous signal by the half killing operation of a circuit with a simple structure and, hence, to expect a stable operation. If the half killer pulse is latched at each timing of the vertical synchronous signal, it is possible to obtain a field identification signal which is inverted in each field, so that the field is quickly identified and the operation of each circuit is quickly synchronized with the composite synchronous signal, thereby shortening the time required for rising the device. The above and other features and advantages of the present invention will become clear from the following description of the preferred embodiment thereof, taken in conjunction with the accompanying drawings. Fig. 1 shows the waveform of a composite synchronous signal; Fig. 2 is a block diagram of a conventional synchronizing circuit; Fig. 3 is a block diagram of the structure of a system having a camera and a monitor; Fig. 4 shows the structure of a system having a plurality of cameras; Fig. 5 is a block diagram of a first embodiment of a synchronizing circuit according to the present invention; Fig. 6 is a timing chart of the operation of the first embodiment shown in Fig. 5; Fig. 7 is a block diagram of the structure of a half killer circuit; Fig. 8 is a timing chart of the operation of the half killer circuit shown in Fig. 7; Fig. 9 is a block diagram of a second embodiment of a synchronizing circuit according to the present invention; Fig. 10 is a timing chart of the operation of the second embodiment shown in Fig. 9; Fig. 11 shows the structure of a fall detector; and Fig. 12 shows the structure of a half killer pulse generator. Fig. 3 is a block diagram of the structure of an image pickup system for transmitting an image obtained by a camera 20 to a monitor 30 in the form of a hybrid signal HYB and reproducing the image by the monitor 30. The camera 20 is provided with a CCD solid-state image sensor 21 for receiving the image of an object, a synchronous signal generator 22 for setting the scanning timing for the CCD 20 and a signal processor 23 for subjecting the output signal of the CCD 21 to a predetermined processing. The camera 20 outputs a hybrid signal HYB including a video component and a synchronous component to the monitor 30. The monitor 30 for receiving the hybrid signal HYB is provided with a synchronous signal separator 31 for taking out the synchronous component from the hybrid signal HYB, a horizontal/vertical separator 32 for separating a horizontal component and a vertical component from a composite synchronous signal CSY and a display driver 34 for driving a display unit 33 such as a cathode ray tube. The monitor 30 displays the video obtained by the camera 30 on the display unit 33. The synchronous signal generator 22 for generating synchronous signals is composed of a horizontal scanning timing generator 22a which is operated with a horizontal scanning period of the CCD 21 and a vertical scanning timing generator 22b which is operated with a vertical scanning period of the CCD 21 and supplies a timing signal having a horizontal scanning period which is represented by a horizontal driving signal HD and a timing signal having a vertical scanning period which is represented by a vertical driving signal VD to the signal processor 23 and a CCD driving circuit (not shown). These timing signal generators 22a, 22b have counters for counting reference clocks and the horizontal driving signals HD, respectively, and decoders for decoding the outputs of the respective counters. These counters are reset with a horizontal scanning period and a vertical scanning period, respectively. The frequency of the reference clock having a high frequency is divided with a predetermined period so as to generate various timing signals. The signal processor 23 subjects the output of the CCD 21 to processings such as sample holding and the correction of the level, and further superimposes a composite synchronous signal CSY including a horizontal synchronous component and the vertical synchronous component on the output of the CCD 21, thereby generating the hybrid signal HYB. The synchronous signal separator 31 of the monitor 30 takes out only the synchronous signal component as the composite synchronous signal CSY by eliminating the signal of a higher level than the level of the pulse of the synchronous signal from the hybrid signal HYB and supplies the composite synchronous signal CSY to the horizontal/vertical separator 32. The horizontal/vertical separator 32 separates a horizontal synchronous signal HSY and a vertical synchronous signal VSY from the composite synchronous signal CSY including a horizontal component and a vertical component and supplies these synchronous signals to the display driver 34. The display driver 34 drives the display unit 33 such as a cathode ray tube and a liquid crystal panel in accordance with these synchronous signals and reproduces the image obtained by the CCD 21 of the camera 20 on the display unit 33. The counters adopted in the synchronous signal generator 22 of the camera 20 are unlikely to cause periodic noise, as will be described later, so that the probability of the superimposition of periodic noise on the video component of the hybrid signal HYB is lessened. As the horizontal/vertical separator 32 of the monitor 30, a circuit having few analog circuit portions is used, as will be described later, so that the change in the characteristics due to a temperature change and the like is suppressed. Fig. 4 shows a system in which the hybrid signal HYB from the reference TV camera 20 is supplied to other TV cameras 20', 20'' so as to drive these three TV cameras 20, 20', 20'' in accordance with the same synchronous signal. The hybrid signals HYB, HYB' and HYB" obtained from these three cameras 20, 20' and 20'' are therefore based on the same synchronous signal, and they are easily compounded by a composite signal generator 40. It is therefore possible to compound three hybrid signals HYB, HYB' and HYB" into one hybrid signal and display it on a TV monitor 41. If the video components from the TV cameras 20, 20' and 20'' are superimposed on only a part of the synchronous signal at different positions from each other, it is possible to display the three images from the respective TV cameras 20, 20' and 20'' at three different positions on the TV monitor 41 merely by superimposing the three hybrid signals HYB, HYB' and HYB". A camera body 24 of the reference TV camera 20 is driven by the synchronous signal generator 22 which is unlikely to produce periodic noise. In the TV cameras 20' and 20", camera bodies 24' and 24'' are driven in accordance with synchronous signals HSY', VSY', HSY" and VSY" output from synchronous signal separators 25' and 25'' which have few analog circuits. Fig. 5 is a block diagram of the structure of a first embodiment of a synchronizing circuit according to the present invention and Fig. 6 is a timing chart of the operation thereof. In this embodiment, the NTSC system is adopted. The composite synchronous signal CSY including the horizontal synchronous signal HSY, the vertical synchronous signal VSY and the equalizing pulses EQP is input to a fall detector 110 after the separation of the video signal therefrom. The fall detector 110 detects the trailing edge of the composite synchronous signal CSY on the basis of a local reference clock MCK and the output CSY' of the fall detector 110 is supplied to a half killer circuit 111. The half killer circuit 111 counts with a horizontal scanning period in accordance with the reference clock MCK, and eliminates the signal having a period equivalent to 1/2 of the horizontal scanning period so as to output the horizontal synchronous signal HSY. If the reference clock MCK has a frequency of 14 MHz, one horizontal scanning period is 908 clocks in the PAL system and 910 clocks in the NTSC system. A vertical synchronous signal separator 112 separates the vertical synchronous component represented by VSY in Fig. 1 from the output CSY' of the fall detector 110. The vertical synchronous signal separator 112 then detects the timing of the trailing edge of VSY and generates a reset signal RES. The reset signal RES is used as the reset signal for a counter 113 for generating the vertical synchronous signal VSY. The vertical synchronous signal separator 112 is so constructed as to sample the composite synchronous signal CSY in accordance with a strobe signal which corresponds to the output signals CSY' of the detector 110 and is delayed by a predetermined time in relation to the trailing edge of the composite synchronous signal CSY. The timing for the leading edge of the composite synchronous signal CSY changes in the blanking period (the period in which the signal is "L") of the vertical synchronous signal VSY, as shown in Fig. 1. Therefore, if the composite synchronous signal CSY is sampled at a timing delayed by a predetermined period which is shorter than the period in which the vertical synchronous signal VSY is "L" and the composite synchronous signal CSY is continuously "L", it is possible to obtain the vertical synchronous signal VSPY from the composite synchronous signal CSY. The counter 113 is reset by the reset signal RES, counts the horizontal synchronous signals HSY and supplies the output CNT to a decoder 114. In this embodiment, [3] is set at the counter 113 at a timing of the reset signal RES, and the counter 113 is so designed that when the output CNT of the counter 113 reaches [262], the counter 113 is reset (by decoder 114). The decoder 114 generates the vertical synchronous signal VSPY which outputs [L] only while the count values CNT are 3, 4 and 5, falls at a timing of the reset signal RES (produced by 112) and rises after a predetermined time. The decoder 114 also generates an enable signal ENB which outputs [H] only while the count values CNT are 0 to 8 and enables the operation of the half killer circuit 111 only in the blanking period of the vertical synchronous signal scanning operation (vertical equalizing period VEP in Fig. 1 and 6). The half killer circuit 111, which operates in accordance with the enable signal ENB, operates in the blanking period of the vertical scanning operation in which the equalizing pulses EQP are existent. In the NTSC system, the enable signal ENB is set so that the half killer circuit 111 operates for 9H periods in which the equalizing pulses EQP are existent. Since the counting operation of the half killer circuit 111 is limited to the blanking period of the vertical scanning operation in this way, power noise due to the counting operation is not produced during the video output effective period. Fig. 7 is a block diagram of the structure of the half killer circuit 111 and Fig. 8 is a timing chart of the operation thereof. The half killer circuit 111 is composed of a counter 121, a decoder 122 and a gate circuit 123 and so constructed as to supply the output of the counter 121 which counts the reference clocks MCK while the enable signal ENB is [H] to the decoder 122 and open or close the gate circuit 123 in accordance with the output DEC of the decoder 122. The decoder 122 generates the output DEC which inverts at intervals of a period equivalent to 1/2 of the horizontal scanning period. The output DEC is supplied to the gate circuit 123. Therefore, the equalizing pulses EQP having a period equivalent to 1/2 of the period of the horizontal synchronous signal HSY are eliminated so as to produce the horizontal synchronous signal HSY. In the NTSC system, there is a difference of half the horizontal scanning period between the horizontal synchronous signal HSY and the vertical synchronous signal VSY in an even field and those in an odd field. It is therefore possible to identify the field by latching the output DEC of the decoder 122 which inverts at intervals of 1/2 of the horizontal scanning period at the timing of the reset signal RES. The decoder 122 is connected to a flip-flop 124 which receives the output DEC of the decoder 122 at the input D and the reset signal RES is supplied from the vertical/horizontal separator 112 (Fig. 5) to the input T of the flip-flop 124, thereby obtaining a field identification signal FLD from the output Q of the flip-flop 124. Since the identification signal FLD is obtained directly from the composite synchronous signal CSY in this way, it is possible to identify the field more quickly than in the case of identifying the field by comparing the phases of the horizontal synchronous signal HSY and the vertical synchronous signal VSY. As a result, each circuit which operates after identifying the field quickly gets ready for operation in synchronism with the composite synchronous signal CSY, so that the time required for the initialize period of the device is shortened. A second embodiment of the present invention will now be explained with reference to Figs. 9 to 12. Fig. 9 is a block diagram of the structure of a second embodiment of a synchronizing circuit according to the present invention, and Fig. 10 is a timing chart of the operation thereof. A trailing edge detector 210 detects the trailing edge of the composite synchronous signal CSY in accordance with the reference clock MCK and outputs a detection signal CSY 1 which becomes [L] after the detection of the trailing edge in the period corresponding to the pulse width of the reference clock MCK. The detection signal CSY 1 is used as a resetting signal of a counter 211 for counting the reference clocks MCK. The counter 211 is reset with the horizontal scanning period and repeats the counting operation. The counting period is synchronized with the composite synchronous signal CSY. A decoder 212 is so constructed as to output [H] when the output of the counter 211 is a predetermined value and supplies a detection signal CSY 2 which is delayed by a predetermined period in relation to the trailing edge of the composite synchronous signal CSY and a latch pulse to a later-described half killer pulse generator 214 and a latch circuit 213, respectively. The detection signal CSY 2 is delayed by about 1/10 of the horizontal scanning period in relation to the detection signal CSY 1 and determines the timing for starting the half killer pulse generator 214. The latch circuit 213 separates the vertical synchronous signal VSY from the composite synchronous signal CSY and detects the trailing edge of the vertical synchronous signal VSY by latching the composite synchronous signal CSY at a timing a predetermined time behind the trailing edges of the composite synchronous signal CSY. A counter 217 for counting in accordance with the output of a VCO 216 is reset by the horizontal synchronous signal HSY for initiating the counting operation and supplies the count value to a decoder 218. The decoder 218 decodes the count value of the counter 217 and outputs horizontal synchronous signals HSY 1 to HSY 4 having different phases. In other words, when the count values becomes predetermined four values, the four signal lines are set at [L]. These phase differences are set at a substantially equal value, and the horizontal synchronous signals HSY 1 to HSY 4 are compounded by a HAND gate 219 to generate a time-sharing clock CLK for dividing the horizontal scanning period into four portions. The half killer pulse generator 214 is started in accordance with the detection signal CSY 2 and generates a half killer pulse KLR which executes half killing operation in a predetermined period in accordance with the clock pulse of the time-sharing clock CLK. The half killer pulse KLR is so designed as to rise at the timing of the leading edge of the time-sharing clock CLK subsequent to the leading edge of the detection signal CSY 2 and to fall at a timing of the leading edge of the time-sharing clock CLK subsequent to the reception of a predetermined number (one in this embodiment) of clock pulses of the time-sharing clock CLK. The half killer pulse KLR and the detection signal CSY 1 are compounded by a gate 220, whereby the [L] pulse of the detection signal CSY 1 is eliminated at every other period so that the half killer pulse KLR executes half killing operation. In this way, signals having a shorter period than the horizontal scanning period, namely, the equalizing pulses EQP are eliminated from the detection signal CSY 1 , and a horizontal synchronous signal HSY 0 is obtained. The phase of the horizontal synchronous signal HSY 0 separated from the composite synchronous signal CSY is compared with the phase of the HSY1 signal which is output from the decoder 218 by a phase comparator 215 and the output is supplied to the VCO 216, thereby constituting a PLL. The horizontal synchronous signals HSY 1 to HSY 4 are therefore synchronized with the composite synchronous signal CSY. In this embodiment, the horizontal synchronous signal HSY 1 is output as the horizontal synchronous signal HSY. Since HSY 1 and HSY 0 are fundamentally the same signal, either may be output, but HSY 1 is preferable because the pulse width thereof is controllable. Fig. 11 shows the structure of the fall detector 210. A flip-flop 226 receives the composite synchronous signal CSY at the input D and supplies the output Q to the input D of a flip-flop 227 at a timing in accordance with the reference clock MCK. The flip-flop 227 inputs the output Q to an OR gate 228 together with the composite synchronous signal CSY at a timing in accordance with the inverted signal of the reference clock MCK. The detection signal CSY 1 is output from the OR gate 228. Accordingly, when the composite synchronous signal CSY falls, the OR gate 228 is inverted and the detection signal CSY 1 falls. At the subsequent leading edge of the reference clock MCK, the output Q of the flip-flop 226 rises and at the subsequent trailing edge of the reference clock MCK, the output Q of the flip-flop 227 rises. The OR gate 228 is then inverted and the detection signal CSY 1 rises. Fig. 12 shows an example of the half killer pulse generator 214 in the state in which the time-sharing clock CLK divides the horizontal scanning period into four portions. The supply potential is applied to the input D of a flip-flop 221, which supplies the output Q to a flip-flop 222 in accordance with the detection signal CSY 2 . The flip-flop 222 supplies the output Q to the input D of a flip-flop 223 and an OR gate 225 in accordance with the time-sharing clock CLK. The flip-flop 223 shifts the output Q of the flip-flop 222 in accordance with the time-sharing clock CLK and supplies the output Q of the flip-flop 223 to the OR gate 225. Alternately, the half killer pulse generator 214 may be constituted by a counter having an appropriate number of bits for counting in accordance with the time-sharing clock CLK. The half killing operation will now be explained. Fig. 10 is a timing chart of the half killing operation of a half killer circuit having a four-phase structure such as that shown in Fig. 12. The horizontal synchronous signals HSY 1 to HSY 4 having four phases are generated by the decoder 218 for decoding the output of the counter 217 and they have a substantially equal phase difference between each other. In the case of the NTSC system, for example, since the counter 217 counts 910 clocks in one horizontal scanning period, the decoder 218 is so constructed as to receive the output of the counter 217 at any time that the counter 217 outputs 0, 228, 454 or 683. The time-sharing clock CLK which is generated by the NAND gate 219 generates four clock pulses in one horizontal scanning period so as to divide one horizontal scanning period into four portions. When the output Q of the flip-flop 221 rises at the leading edge of the detection signal CSY 2 a predetermined time behind the detection signal CSY 1 , the supply potential is input to the input D of the flip-flop 222 and the output Q of the flip-flop 222 rises at the subsequent leading edge of the time-sharing clock CLK. Therefore, the half killer pulse KLR rises at the leading edge of the time-sharing clock CLK subsequent to the leading edge of the detection signal CSY 2 . At the second leading edge of the time-sharing clock CLK, the output Q of the flip-flop 223 rises, the output Q thereof falls and the output Q of the flip-flop 221 fall. In this state, when the output Q of the flip-flop 222 falls at the third leading edge of the time-sharing clock CLK, the OR gate 225 is inverted and the half killer pulse KLR falls. At the next leading edge of the CLK, the output Q of the flip-flop 223 rises. In this way, the half killer pulse KLR sets the half killing period at the two time-sharing clock periods after the leading edge of the detection signal CSY 2 . By obtaining the OR of the half killer pulse kLR and the detection signal CSY 1 , it is possible to eliminate the equalizing pulses EQP having a shorter period than the period of the horizontal synchronous signal HSY and to obtain the horizontal synchronous signal HSY 0 . The VCO 216 constituting the PLL is so controlled as to be synchronized with the composite synchronous signal CSY by comparing the phase of the horizontal synchronous signal HSY 0 with the phase of one of the horizontal synchronous signals HSY 1 to HSY 4 . To prevent an error in the half killing operation the detection signal CSY 2 which is delayed in relation to the composite synchronous signal CSY is used in determining the timing for starting the half killer pulse generator 214. In this way, the error in the period caused until the horizontal synchronous signals HSY 1 to HSY 4 are synchronized with the composite synchronous signal CSY is compensated. For example, when the period of any of the horizontal synchronous signals HSY 1 to HSY 4 is shorter than the intrinsic horizontal scanning period, if the leading edge of the detection signal CSY 1 is input immediately before the trailing edge of the time-sharing clock CLK, there is a fear of the half killer pulse KLR falling before the trailing edge of the detection signal CSY 1 , thereby making it impossible to eliminate the equalizing pulses EQP. To prevent this, the timing for starting the half killing operation is set in accordance with the detection signal CSY 2 which is delayed in relation to the composite synchronous signal CSY. That is, if the timing for starting the half killing operation is set at a timing delayed in relation to the composite synchronous signal CSY, (the timing for starting the half killing operation is delayed by 1 clock of the time-sharing clock CLK when the leading edge of the detection signal CSY 1 is input immediately before the trailing edge of the time-sharing clock CLK), the half killer pulse KLR never falls before the detection signal CSY 1 . It is in the case in which a horizontal synchronous signals HSY n has four to five phases that the detection signal CSY 2 which is delayed in relation to the composite synchronous signal CSY is used in determining the timing for starting the half killing operation. In a not less than six-phase structure, the detection signal CSY 1 without the need for delay may be used in determining the timing for starting the half killing operation.

Claims: A synchronizing circuit which receives a composite synchronous signal (CSY) including vertical synchronous pulses (VSY), horizontal synchronous pulses (HSY) having a horizontal scanning period and equalizing pulses (EQP) and generates as an output horizontal synchronous pulse signals (HSPY) and vertical synchronous pulse signals (VSPY) synchronized with said composite synchronous signal, said synchronizing circuit comprising an edge detector (110) for detecting a trailing edge of every pulse of said composite synchronous signal and outputting a pulse signal (CSY') at every edge, a half killer circuit (111) for eliminating in said pulse signal pulses having a shorter period than a predetermined period from said edge detector and thereby outputting only said horizontal synchronous pulse signals, a vertical synchronous signal separator (112) for sampling a level of said composite synchronous signal in the vicinity of said trailing edges in accordance with said pulse signal (CSY') which is delayed by a predetermined time in relation to said trailing edges of said composite synchronous signal (CSY), and for outputting a reset signal (RES), when said sampled level has a predetermined value representing the occurrence of said vertical synchronous pulses (VSY), a counter (113) which is reset by said reset signal generated by said vertical synchronous signal separator and counts in synchronism with said horizontal synchronous pulse signals, and a decoder (114) for producing a vertical synchronous pulse signal (VSPY) at every occurrence of said reset signal, and an enabling pulse (ENB) for enabling said half killer circuit (111) only during a vertical equalizing period (VEP) comprising said equalizing pulses (EQP) and said vertical synchronous pulses (VSY) of said composite synchronous signal (CSY), wherein said enabling pulse begins after said counter (113) has reached a predetermined count value corresponding to the start of said vertical equalizing period (VEP) and is reset by said decoder (114), so that said half killer circuit (111) eliminates said vertical synchronous pulses (VSY) and said equalizing pulses (EQP) from said composite synchronous signal (CSY) and thus produces said regularly occurring horizontal synchronous pulses (HSY) before, during and after said vertical equalizing period (VEP). A synchronizing circuit according to claim 1, wherein said half killer circuit (111) includes: a counter (121) for counting predetermined reference clocks (MCK); and a gate means (122, 123, 124) supplied by said pulse signal (CSY') and provided for stopping the passing of said pulse signal (CSY') from said edge detector (110) at predetermined intervals on the basis of the count value of said counter (121). A synchronizing circuit according to claim 2, wherein said gate means includes: a decoder (122) for decoding said count value of said counter (121) and outputting a decode signal (DEC in Fig. 10) which inverts at intervals of ½ of the horizontal scanning period of said horizontal synchronous pulses; and a gate (123) for controlling the passing of said pulse signal (CSY') of said edge detector on the basis of said decode signal. A synchronizing circuit according to claim 3, further comprising a latch circuit (124) for latching said decode signal with said reset signals (RES) as a trigger, whereby the field of said composite synchronous signal (CSY)is identified by the data (FLD in Fig. 10) in said latch circuit (124). A synchronizing circuit which receives a composite synchronous signal (CSY) including vertical synchronous pulses (VSY), horizontal synchronous pulses (HSY) having a horizontal scanning period and equalizing pulses (EQP) and generates as an output horizontal synchronous pulse signals (HSY) and vertical synchronous pulse signals (VSPY) synchronized with said composite synchronous signal, said synchronizing circuit comprising: a counter (217) for counting predetermined reference clocks, having a cycle which is substantially shorter than that of the composite synchronous signal, said counter being reset by said horizontal synchronous pulse signal (HSY) output by said synchronizing circuit, and supplying the count value to a decoding circuit (218, 219) for generating a time-sharing clock signal (CLK) (in Fig. 12) including a plurality of pulses in one horizontal scanning period; an edge detector (210) for detecting a trailing edge of every pulse of said composite synchronous signal (CSY) and outputting detection pulse signals (CSY1) after every edge detection; a half killer pulse generating circuit (214) to which said detection pulse signals in undelayed (CSY1) or delayed (CSY2) form and said time-sharing clock signals are input and which controls a gate (220) for stopping the passing of said detection pulse signals (CSY1 or CSY2) at a predetermined time determined by the time-sharing pulse input through said gate (220) so as to eliminate output pulses having shorter periods than said horizontal scanning period from said detection pulse signals and to output said regularly occurring horizontal synchronous pulse signals (HSY); and a vertical synchronous signal separator (213) for separating said vertical synchronous pulse signals (VSPY) from said composite synchronous signal (CSY) and outputting the separared pulse signals wherein said vertical synchronous signal separator detects a level of the composite synchronous signal at a timing a predetermined time behind the trailing edges of the composite synchronous signal (CSY), said timing being determined by said delayed detection pulse signals (CSY2). A synchronizing circuit according to claim 5, wherein said decoding circuit includes: a decoder (218) for decoding the count value of said counter (217) and outputting a plurality of signals (HSY n ) having different phases from each other, each of said signals consisting of pulses occurring regularly at intervals of one horizontal scanning period; and a gate (219) for compounding said plurality of signals output from said decoder to generate said time-sharing clock signal (CLK) having said plurality of pulses in one horizontal scanning period. A synchronizing circuit according to claim 6, further comprising: a means (215) for comparing the phase of said horizontal synchronous pulse signals (HSY) which are output from said gate (220) with the phase of one of said plurality of signals (HSY n ) output from said decoder (218) of said decoding circuit (218, 219) so as to adjust the period of said predetermined reference clock in accordance with the phase difference obtained, thereby synchronizing the operation of said decoding circuit (218, 219) with said composite synchronous signal (CSY). A synchronizing circuit according to claim 5, wherein said half killer pulse generating means (214) includes: a shift register (222, 223) clocked by said time-sharing clock signal (CLK) and supplied by pulses timed with said delayed detection pulse signals of said edge detector (210), said delay being shorter than said horizontal scanning period; and a decoder (225) connected to said shift register for outputting a half killer pulse (KLR) which controls said gate (220).

Inventors: HIGASHITSUTSUMI YOSHIHITO, HIGASHITSUTSUMI, YOSHIHITO
Applicants: SANYO ELECTRIC CO, SANYO ELECTRIC CO., LTD.
Application year: 1991
Main classification: H04N5
IPC codes: H04N5