Lateral MOSFET and manufacturing method thereof

Abstract: In a lateral MOS FET, a back gate region a part of whose surface is a channel region is formed to surround the drain region, while being in contact with a part of the periphery of the drain region. With this configuration, if a high voltage electrostatic surge invades the drain electrode, a surge current will disperse from the drain region toward the surrounding back gate region. As a result, a rise in the electric potential at the drain region is suppressed smaller. Thus the electric potential hardly exceed the dielectric strength of the gate insulating film, thereby suppressing a breakdown of the gate insulating film and an electrostatic breakdown of the device.

Description: The present invention relates to a lateral MOS FET and a manufacturing method thereof and, more particularly, to a double diffused lateral MOS FET (insulated-gate field effect transistor) applicable to a high withstand-voltage Bi-CMOS and manufacturing method thereof. In general, when a double diffused lateral MOS FET is composed of complementary MOS (CMOS), either p-channel MOS transistor or n-channel MOS transistor is formed as lateral MOS FET. Fig. 1A shows a pattern layout of a conventional lateral p-channel MOS transistor, and Fig 1B is a sectional view taken along a line B-B of Fig. 1A. In Figs. 1A and 1B, numeral 50 denotes an n - -type semiconductor substrate; 51, a p-type diffused layer for drain region; 52, a p + -type diffused layer for drain electrode connecting layer; 53, an n-type diffused layer for channel and back gate regions; 54, a p + -type diffused layer for source region; 55, a gate insulating film; 56, a gate electrode; 57, an interlayer insulating film; 58, a drain electrode; and 59, a source/back gate common electrode. The pattern is designed so that the gate electrode 56 may invariably exist between the contact portion 59a of the source/back gate common electrode 59 and drain contact portion 58a. In such a conventional lateral MOS FET, when an electrostatic surge of high-voltage enters the drain electrode 58, a surge current flows in the forward direction of the parasitic diode, as shown by the arrow in Fig. 2, i.e., flows through the path from the p-type diffused layer 51 as the drain region to the n-type diffused layer 53 as the channel and back gate regions. At that time, an electric potential of the p-type diffused layer 51 is caused to rise due to the resistance R of the n-type diffused layer 53. A breakdown of the gate insulating film 55 occurs when the rised potential exceeds its dielectric strength. Thus an electrostatic breakdown of the device also occurs. The present invention is made to overcome the aforementioned drawbacks, and it is an object of the present invention to provide a lateral MOSFET and a manufacturing method thereof, in which a resistibility to electrostatic surge is improved and which can be used in a high withstand-voltage Bi-CMOS. Reference is made to EP-A-0 386 779, which discloses a lateral MOSFET comprising: a first impurity diffused layer of a second conductivity type formed at a part of the surface of either a semiconductor substrate of a first conductivity type, a second impurity diffused layer of the second conductivity type located in said first impurity diffused layer and formed so as to have a lesser depth from the surface of the substrate to the junction and a higher impurity concentration than those of said first impurity diffused layer, a third impurity diffused layer of a first conductivity type with a higher impurity concentration than said semiconductor substrate, which is formed at a part of the surface of said semiconductor substrate so as to surround said first impurity diffused layer and said second impurity diffused layer, while being in contact with the entire periphery of said first impurity diffused layer, a fourth impurity diffused layer of the second conductivity type located in said third impurity diffused layer in the area where said third impurity diffused layer contacts said first impurity diffused layer, and formed to have a lesser depth from the surface of the substrate to the junction than that of said third impurity diffused layer and have a higher impurity concentration than that of said first impurity diffused layer, a gate electrode formed via a gate insulating film on the surface of said third impurity diffused layer intervened between said fourth impurity diffused layer and first impurity diffused layer, a drain electrode formed in contact with said second impurity diffused layer, and a source/back gate common electrode in electrical connection with both said third impurity diffused layer and fourth impurity diffused layer. According to the invention from a first aspect, there is provided a lateral MOSFET comprising: a first impurity diffused layer of a second conductivity type formed at a part of the surface of either a semiconductor region of a first conductivity type, a second impurity diffused layer of the second conductivity type located in said first impurity diffused layer and formed so as to have a lesser depth from the surface of the semiconductor region to the junction and a higher impurity concentration than those of said first impurity diffused layer, a third impurity diffused layer of a first conductivity type with a higher impurity concentration than said semiconductor region, which is formed at a part of the surface of said semiconductor region so as to surround said first impurity diffused layer and said second impurity diffused layer, while being in contact with a first part of the periphery of said first impurity diffused layer, a second part of the periphery of layer being in contact with the semiconductor region, a fourth the first impurity diffused impurity diffused layer of the second conductivity type located in said third impurity diffused layer in the area where said third impurity diffused layer contacts said first impurity diffused layer and formed to have a lesser depth from the surface of the semiconductor region to the junction than that of said third impurity diffused layer and have a higher impurity concentration than that of said first impurity diffused layer, a gate electrode formed via a gate insulating film on the surface of said third impurity diffused layer intervened between said fourth impurity diffused layer and first impurity diffused layer, a drain electrode formed in contact with said second impurity diffused layer, and a source/back gate common electrode formed in contact with both said third impurity diffused layer and fourth impurity diffused layer. One form of high withstand-voltage Bi-CMOS transistor device in accordance with the invention comprises: a semiconductor substrate of a second conductivity type, a buried layer of a first conductivity type with a high impurity concentration, which is formed to be buried in said semiconductor substrate, an epitaxial layer of the first conductivity type formed in said semiconductor substrate and above said buried layer, a connecting layer of the first conductivity type, that is formed along the periphery of said epitaxial layer to reach said buried layer and has the impurity concentration equal to that of said buried layer and higher than that of said epitaxial layer, and a lateral MOSFET as defined in the preceding paragraph, formed in the epitaxial layer wherein the first impurity diffused layer is formed at a part of the surface of said epitaxial layer, and the fourth impurity diffused layer is formed at the surface of said epitaxial layer has a higher impurity concentration than that of said epitaxial layer, and extends over said epitaxial layer and the device further comprises: a bipolar device formed in another surface region of said semiconductor substrate. Another form of high withstand-voltage Bi-CMOS transistor device in accordance with the invention comprises: a semiconductor substrate of a second conductivity type, a buried layer of a first conductivity type with a high impurity concentration, which is formed as a deep well in said semiconductor substrate, an epitaxial layer of the first conductivity type formed as a well in said buried layer, and a lateral MOSFET as defined in the last but one paragraph, formed in the epitaxial layer rather than the substrate, wherein the third impurity diffused layer has a higher impurity concentration than that of said epitaxial layer, and is formed at the surface of said epitaxial layer so as to extend over said epitaxial layer and buried layer, while being in contact with part of the periphery of said first impurity diffused layer, and the fourth impurity diffused layer is formed to have a less depth from the surface of said epitaxial layer to the junction than that of said third impurity diffused layer and the device further comprises: a bipolar device formed in another surface region of said semiconductor substrate. According to the invention from another aspect there is provided a method of manufacturing a lateral MOSFET comprising the steps of: forming a drain region by injecting impurities of a second conductivity type into the drain forming region of a semiconductor substrate of a first conductivity type and then diffusing them, forming a gate insulating film in the back gate forming region, the drain electrode contact layer forming region, and the source forming region on said semiconductor substrate, forming a gate electrode by depositing a polysilicon film over the entire surface and then patterning the deposited film, forming a back gate region by injecting impurities of the first conductivity type into said back gate forming region with said gate electrode as a mask and then diffusing the impurities, such that the back gate region is in contact with a first part of the periphery of the drain region, a second part of the periphery of this layer being in contact with the substrate, forming a drain electrode connecting layer and a source region by injecting impurities of the second conductivity type into said drain electrode connecting layer forming region and source forming region and then diffusing the impurities, depositing an interlayer insulating film over the entire surface and then making openings for a source/back gate common electrode and a drain electrode, and forming a source/back gate common electrode and a drain electrode by evaporating a metal wiring layer on the entire surface and then patterning the evaporated layer. In a lateral MOSFET according to the present invention back gate region a part of whose surface is a channel region is formed to surround the drain region, while being in contact with a part of the periphery of the drain region. With this configuration, if a high voltage electrostatic surge invades the drain electrode, a surge current will disperse from the drain region toward the surrounding back gate region in every direction. As a result, a rise in the electric potential at the drain region is suppressed. Thus the electric potential at the drain region hardly exceeds the dielectric strength of the gate insulating film, thereby increasing resistibility to electrostatic surges. This increased resistibility to the surge suppresses a breakdown of the gate insulating film and thus electrostatic breakdown of the device. This invention can be more fully understood from the following detailed description, given by way of example, when taken in conjunction with the accompanying drawings, in which: Fig. 1A is a plan view showing a plan pattern of a conventional lateral MOSFET; Fig. 1B is a sectional view of the lateral MOSFET of Fig. 1A taken along a line B-B; Fig. 2 is a sectional view illustrating a surge current path when an electrostatic surge enters the lateral MOS FET of Fig. 1B; Fig. 3A is a plan view showing a plan pattern of a first embodiment of a lateral MOS FET according to the present invention; Fig. 3B is a sectional view taken along a line X-X of Fig. 3A; Figs. 4A through 4M are sectional views illustrating the manufacturing processes of the lateral MOS FET of Fig. 3B; Figs. 5A and 5B are sectional views showing a second embodiment as an integrated circuit according to the present invention; and Figs. 6A and 6B are sectional views showing a third embodiment as an integrated circuit according to the present invention. Embodiments of the lateral MOS FET of the present invention will be explained in detail with reference to the accompanying drawings. Fig. 3A is a plan view showing a plan pattern of a first embodiment of a lateral MOS FET according to of the present invention, and Fig. 3B is a sectional view taken along a line X-X of Fig. 3A. In Fig. 3A, reference character Ba denotes a back gate contact portion; Da, a drain contact portion; Sa, a source contact portion; and G, a gate electrode. The back gate contact portion Ba is provided around the drain contact portion Da. The source contact portion Sa is in contact with a part of the back gate contact portion Ba for common use. In Fig. 3B, a semiconductor substrate 10 of a first conductivity type, i.e., n-type in the present invention, is an n - -type semiconductor substrate with relatively low impurity concentration. The substrate 10 is made of, e.g., a silicon monocrystalline substrate. A drain region 11 is a first impurity diffused layer of a second conductivity type, i.e., p-type in the present invention, which is formed on the surface of the semiconductor substrate 10. A drain electrode connecting layer 12 is a second impurity diffused layer of a p + -type. The connecting layer 12 is located within the first impurity diffused layer 11 and has a less depth from the surface of the substrate 10 to the junction and has a higher impurity concentration than that of the diffused layer 11. A back gate region 13 is a third impurity diffused layer of an n-type with a higher impurity concentration than that of the semiconductor substrate 10. The back gate region 13 surrounds the first and second impurity diffused layers 11 and 12 on the surface of the semiconductor substrate 10, while being in contact with a part of the periphery of the first impurity diffused layer 11. A source region 14 is a fourth impurity diffused layer of a p + -type. The source region 14 is located in the third impurity diffused layer 13 in the area where the third impurity diffused layer 13 is in contact with the first impurity diffused layer 11. The source region 14 has a less depth from the surface of the substrate 10 to the junction than that of the third impurity diffused layer 13 and has a higher impurity concentration than that of the first impurity diffused layer 11. A gate electrode G is formed via a gate insulating film 15 on the channel region CH which is the surface region of the third impurity diffused layer 13 intervened between the fourth and first impurity diffused layers 14 and 11. The gate insulating film 15 is made of, for example, silicon dioxide (SiO 2 ) film. A drain electrode D is formed in contact with the second impurity diffused layer 12. A source/back gate common electrode SB is isolated from the drain contact portion Da while surrounding it, as shown in Fig. 3A, and is in contact with both the third and fourth impurity diffused layers 13 and 14, as shown in Fig. 3B. An interlayer insulating film 16 is formed of SiO 2 , for example. Now, referring to Figs. 4A through 4M, a manufacturing method of the lateral p-channel MOS transistor in Fig. 3 will be described in detail. As shown in Fig. 4A, an insulating film 21 is formed by dry oxidation at 1000°C on the surface of the n - -type silicon substrate 10. The insulating film 21 is made of SiO 2 film of 0.1 µm thickness, for example. As shown in Fig. 4B, a photoresist pattern 22 is formed on the surface by photoetching. Then p-type impurities are injected into the entire surface by ion implantation. Boron ion is used as the p-type impurity. As shown in Fig. 4C, borons are diffused by heat treatment at 1200°C to form the p-type impurity diffused layer 11. The diffused layer 11 is used as the drain region. As shown in Fig. 4D, an insulating film (SiO 2 ) 23 is then grown to a thickness of 1.0 µm on the surface by steam oxidation at 1000°C. After the growth of the insulating film 23, as shown in Fig. 4E, openings 23a are formed by removing predetermined areas of the insulating film 23 by means of photoetching. As shown in Fig. 4F, gate insulating films 15 are formed on the bottom of the openings 23a by dry oxidation at 1000°C. The gate insulating film 15 is made of SiO 2 film of 0.1 µm thickness, for example. As shown in Fig. 4G, a polysilicon film is deposited to a thickness of 0.5 µm on the entire surface of the substrate by chemical vapor deposition (CVD). Then, the polysilicon film is patterned by photoetching to thus form the gate electrode G. As shown in Fig. 4H, a photoresist pattern 24 is formed on the resultant surface by photoetching. N-type impurity ions are injected into the entire surface by ion implantation, using the photoresist pattern and the gate electrode G as a mask. Phosphorus ion P + is used as the n-type impurity ion, for example. As shown in Fig. 4I, phosphorous is diffused by heat treatment at 1200°C to form the n-type impurity diffused layer 13. The diffused layer 13 is used as the back gate region. As shown in Fig. 4J, a photoresist pattern 25 is formed by photoetching on the surface. Then, boron ions B + are implanted into the entire surface by ion implantation, using the photoresist pattern 25, the gate electrode G and the insulating film 23 as a mask. As shown in Fig. 4K, an interlayer insulating film (SiO 2 ) 16 is deposited to a thickness of 1.0 µm by CVD on the entire surface. Then, the interlayer insulating film 16 is annealed by heat treatment at 1000°C. Borons are diffused by the same heat treatment to form the p + -type impurity diffused layer 12 and the impurity diffused layer 14. The diffused layers 12 and 14 are used as the drain electrode connecting layer and the source region, respectively. As shown in Fig. 4L, contact holes are formed by removing predetermined areas of the interlayer insulating film 16 by means of photoetching. These contact holes correspond to the back gate contact portion Ba, the drain contact portion Da, and the source contact portion Sa. Finally, as shown in Fig. 4M, a metal wiring film such as Aℓ film is deposited to a thickness of 1.0 µm over the surface of the resultant structure. The metal wiring film is then patterned by photoetching to form the drain electrode D and the source/back gate common electrode SB. The drain electrode D is in contact with the impurity diffused layer 12 as the drain electrode connecting layer. The common electrode SB is in contact not only with the whole back gate region 13 but also with the source region 14 which is formed in the area of the back gate region 13. After this, sintering is executed to complete the lateral MOS FET of Fig. 3B. With the lateral p-channel MOS FET according to the first embodiment, the back gate region 13 is formed so as to surround the drain region 11 while being in contact with a part of the drain region 11. This arrangement allows a surge current to disperse from the drain region 11 to the surrounding back gate region 13. This suppresses a rise in the electric potential at the drain region 11. As a result, the electric potential value rarely exceeds the dielectric strength of the gate insulting film 15. Thus, a breakdown of the gate insulating film 15 and therefore an electrostatic breakdown of the device are suppressed . Fig. 5A is a sectional view showing a lateral p-channel MOS FET according to a second embodiment of the present invention. Fig. 5A shows a sectional structure of the MOS FET as an integrated circuit. In Fig. 5A, a lateral p-channel MOS transistor is formed on an island of an n - -type epitaxial layer 33 which is surrounded by a deep n + -type diffused layer 31 and an n + -type buried layer 32 formed in a p - -type substrate 30. More particulary, first the n + -type buried layer 32 is formed in the p - -type substrate 30 and the n - -type epitaxial layer 33 is formed on the substrate 30 and the layer 32. A p + -type semiconductor region 34 as an element isolation region is formed in outer part of the n - -type epitaxial layer 33. Further, in another part of the n - -type epitaxial layer 33, the deep n + -type diffused layer 31 reaching the n + -type buried layer 32 is formed. On the n - -type epitaxial layer 33 surrounded by both the deep n + -type diffused layer 31 and n + -type buried layer 32, the p-type diffused layer 11 is formed as the drain region. The n-type diffused layer 13 is then formed as the channel region/back gate region. The diffused layer 13 is in contact with part of the periphery of the p-type diffused layer 11 and be partially located in the deep n + -type diffused layer 31. An n-type diffused layer 13a, i.e. a part of the n-type diffused layer 13, is formed as the back gate region so as to be located in the deep n + -type diffused layer 31 in a manner to surround the p-type diffused layer 11. Here, numeral 12 denotes a p + -type diffused layer as the drain electrode connecting layer; 14, a p + -type diffused layer as the source region; 15, the gate insulating film; G, the gate electrode; D, the drain electrode; SB, the source/back gate common electrode; 16, the interlayer insulating film; and 35, an n + -type diffused layer as the back gate electrode connecting layer. Fig. 5B shows a sectional structure of a bipolar device as an integrated circuit which is formed on the same p - -type substrate 30 as shown in Fig. 5A. The p - -type substrate 30, a deep n + -type diffused layer 31 as a buried collector electrode connecting layer, an n + -type buried layer 32 as a collector buried electrode, an n - -type epitaxial layer 33, and a p + -type semiconductor region 34 as a device isolation region are formed by the same steps as those in Fig. 5A. Also an interlayer insulating film 16 is identical to that of Fig. 5A. A p-type diffused layer 11a as an external base region and a p + -type diffused layer 12a as a base electrode connecting layer are formed simultaneously with the drain region 11 and the drain electrode connecting layer 12 in Fig. 5A, respectively. An n + -type diffused layer 35a as a collector electrode connecting layer and n + -type diffused layer 35b as an emitter region are formed at the same time as the back gate electrode connecting layer 35 in Fig. 5A. A p-type diffused region 39 as a base region is formed between the steps for forming the external base region 11a and the emitter region 35b. More particularly, boron ions are injected as p-type impurity by ion implantation using another photoresist mask and then diffused simultaneously with the n-type diffused layer 13 in Fig. 5A. A base electrode B, an emitter electrode E, and a collector electrode C are formed simultaneously with the drain electrode D and the source/back gate common electrode SB in Fig. 5A. Fig. 6A is a sectional view showing a lateral p-channel MOS FET according to a third embodiment of the present invention. Fig. 6A also shows a sectional structure of the MOS FET as an integrated circuit. In Fig. 6A a lateral p-channel MOS transistor is formed on an island of a deep n - -type buried epitaxial layer 42 which is surrounded by an n + -type buried layer 41 on a p - -type substrate 40. More particulary, the convex n + -type buried layer 41 is first formed deeply in the p - -type substrate 40 and the n - -type buried epitaxial layer 42 is formed in the buried layer 41. A p-type diffused layer 11 is formed as the drain region in the epitaxial layer 42. An n-type diffused layer 13 is formed as the channel region/back gate region. The diffused layer 13 is in contact with part of the periphery of the p-type diffused layer 11 at the surface of the n - -type epitaxial layer 42, while being partially located in the n + -type buried layer 41. The n-type diffused layer 13a, i.e., a part of the n-type diffused layer 13, is formed as the back gate region at a part of the surface of the n - -type epitaxial layer 42 and at the surface of the n + -type buried layer 41 so as to surround the p-type diffused layer 11. Here, numeral 12 denotes a p + -type diffused layer as the drain electrode connecting layer; 14, a p + -type diffused layer as the source region; 15, the gate insulating film; G, the gate electrode; D, the drain electrode; SB, the source/back gate common electrode; 16, the interlayer insulting film,; and 35, an n + -type diffused layer as the back gate electrode connecting layer. Fig. 6B shows a sectional structure of a bipolar device as an integrated circuit which is also formed on the same p - -type substrate 40 as shown in Fig. 6A. The p - -type substrate 40, an n + -type buried layer 41 as a collector buried electrode, and a deep n - -type buried epitaxial layer 42 are formed by the same steps as those in Fig. 6A. An interlayer insulating film 16 is also identical to that of Fig. 6A. A p-type diffused layer 11a as an external base region, and an n-type diffused layer 13a are formed simultaneously with the drain region 11 and the channel region/back gate region 13 in Fig. 6A, respectively. A p + -type diffused layer 12a as a base electrode connecting layer is formed at the same time as the drain electrode connecting layer 12 in Fig. 6A. An n + -type diffused layer 35a as a collector electrode connecting layer and an n + -type diffused layer 35b as an emitter region are formed simultaneously with the back gate electrode connecting layer 35 in Fig. 6A. A p-type diffused region 45 as a base region is formed after the external base region 11a is formed. Born ions are implanted and diffused simultaneously with the layer 13a to thus form the base region 45. A base electrode B, an emitter electrode E and a collector electrode C are also formed simultaneously with the drain electrode D and the source/back gate common electrode SB in Fig. 6A. With lateral MOS FETs according to the present invention, it is possible to improve the resistibility to an electrostatic surge. However, a lateral MOS FET of the present invention can achieve the resistibility to an electrostatic surge of more than one thousand voltages, for example. A conventional lateral MOS FET that had the resistibility to an electrostatic surge as low as up to several hundred voltages when no capacitive load is applied.

Claims: A lateral MOSFET comprising: a first impurity diffused layer (11) of a second conductivity type formed at a part of the surface of a semiconductor region (10:33) of a first conductivity type; a second impurity diffused layer (12) of the second conductivity type located in said first impurity diffused layer (11) and formed so as to have a lesser depth from the surface of the semiconductor region (10:33) to the junction and a higher impurity concentration than those of said first impurity diffused layer (11); a third impurity diffused layer (13) of a first conductivity type with a higher impurity concentration than said semiconductor region (10:33), which is formed at a part of the surface of said semiconductor region (10:33) so as to surround said first impurity diffused layer (11) and said second impurity diffused layer (12), while being in contact with a first part of the periphery of said first impurity diffused layer (11), a second part of the periphery of the first impurity diffused layer being in contact with the semiconductor region (10:33); a fourth impurity diffused layer (14) of the second conductivity type located in said third impurity diffused layer (13) in the area where said third impurity diffused layer (13) contacts said first impurity diffused layer (11), and formed to have a lesser depth from the surface of the semiconductor region (10:33) to the junction than that of said third impurity diffused layer (13) and have a higher impurity concentration than that of said first impurity diffused layer (11); a gate electrode (G) formed via a gate insulating film (15) on the surface of said third impurity diffused layer (13) intervened between said fourth impurity diffused layer (14) and first impurity diffused layer (11); a drain electrode (D) formed in contact with said second impurity diffused layer (12); and a source/back gate common electrode (SB) formed in contact with both said third impurity diffused layer (13) and fourth impurity diffused layer (14). A lateral MOSFET according to claim 1, characterised in that said semiconductor region is a semiconductor substrate (10) of said first conductivity type. A lateral MOSFET according to claim 1, characterised in that said semiconductor region is an epitaxial layer (33,42) of said first conductivity type formed in a substrate (30,40). A lateral MOSFET according to claim 2, characterised in that said semiconductor substrate (10) is a silicon monocrystalline substrate and said gate insulating film (15) is a silicon dioxide film. A high withstand-voltage Bi-CMOS transistor device comprising: a semiconductor substrate (30) of a second conductivity type; a buried layer (32) of a first conductivity type with a high impurity concentration, which is formed to be buried in said semiconductor substrate (30); an epitaxial layer (33) of the first conductivity type formed in said semiconductor substrate (30) and above said buried layer (32); a connecting layer (31) of the first conductivity type, that is formed along the periphery of said epitaxial layer (33) to reach said buried layer (32) and has the impurity concentration equal to that of said buried layer (32) and higher than that of said epitaxial layer (33); and a lateral MOSFET as claimed in claim 3 formed in the epitaxial layer (33) wherein the first impurity diffused layer (11) is formed at a part of the surface of said epitaxial layer (33); and the fourth impurity diffused layer (13) is formed at the surface of said epitaxial layer (33), has a higher impurity concentration than that of said epitaxial layer (33), and extends over said epitaxial layer (33) and the device further comprises: a bipolar device formed in another surface region of said semiconductor substrate (30). A high withstand-voltage Bi-CMOS transistor device comprising: a semiconductor substrate (40) of a second conductivity type; a buried layer (41) of a first conductivity type with a high impurity concentration, which is formed as a deep well in said semiconductor substrate (40); an epitaxial layer (42) of the first conductivity type formed as a well in said buried layer (41); and a lateral MOSFET as claimed in claim 3 formed in the epitaxial layer (42); wherein the third impurity diffused layer (13) has a higher impurity concentration than that of said epitaxial layer (42), and is formed at the surface of said epitaxial layer (42) so as to extend over said epitaxial layer (42) and buried layer (41), while being in contact with part of the periphery of said first impurity diffused layer (11); and the fourth impurity diffused layer (14) is formed to have a less depth from the surface of said epitaxial layer (42) to the junction than that of said third impurity diffused layer (13); and the device further comprises: a bipolar device formed in another surface region of said semiconductor substrate (40). A method of manufacturing a lateral MOSFET comprising the steps of: forming a drain region (11) by injecting impurities of a second conductivity type into the drain forming region of a semiconductor substrate (10) of a first conductivity type and then diffusing them; forming a gate insulating film (15) in the back gate forming region, the drain electrode contact layer forming region, and the source forming region on said semiconductor substrate (15); forming a gate electrode (G) by depositing a polysilicon film over the entire surface and then patterning the deposited film; forming a back gate region (13) by injecting impurities of the first conductivity type into said back gate forming region with said gate electrode (G) as a mask and then diffusing the impurities, such that the back gate region is in contact with a first part of the periphery of the drain region 11, a second part of the periphery of this layer being in contact with the substrate; forming a drain electrode connecting layer (12) and a source region (14) by injecting impurities of the second conductivity type into said drain electrode connecting layer forming region and source forming region and then diffusing the impurities; depositing an interlayer insulating film (16) over the entire surface and then making openings for a source/back gate common electrode and a drain electrode; and forming a source/back gate common electrode (SB) and a drain electrode (D) by evaporating a metal wiring layer on the entire surface and then patterning the evaporated layer.

Inventors: SHIRAI KOJI, SHIRAI, KOJI, SHIRAI, KOJI, C/O INTELLECTUAL PROPERTY DIVISION
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: H01L29
IPC codes: H01L29, H01L21