Layer structure having contact hole for fin-shaped capacitors in DRAMS and method of producing the same

Abstract: A method of forming a structure having a contact hole (10) includes the steps of (a) forming an insulating layer (3) on a first conductive layer (2), (b) forming a second conductive layer (4) on the insulating layer, (c) forming an opening (6) in the second conductive layer, (d) forming a conductive sidewall (8) around an inner wall of the first conductive layer defining the opening, (e) selectively etching the insulating layer in a state where the second conductive layer and the conductive sidewall function as etching masks, so that the contact hole having a width smaller than that of the opening and defined by the conductive sidewall is formed, and the first conductive layer is exposed through the contact hole, and (f) removing the second conductive layer and the conductive sidewall by using a photoresist (11). This structure is employed to produce multi-finned stacked storage capacitor DRAMs.

Description: The present invention generally relates to a layer structure having a contact hole suitable for dynamic random access memories having fine contact holes, and a method of producing such a layer structure. More particularly, the present invention is concerned with a fin-shaped capacitor having such a layer structure, and a method of forming such a fin-shaped capacitor. Furthermore, the present invention is concerned with a dynamic random access memory having such a fin-shaped capacitor. Recently, there has been considerable activity as regards the development of 64Mbit dynamic random access memories (DRAM). There are known DRAMs having three-dimensional stacked capacitor cells capable of providing a storage capacity equal to or higher than 64Mbits (see Japanese Laid-Open Patent Application Nos. 1-137666, 1-147857 and 1-154549, USP 4,974,040 and T. Ema et al., "3-DIMENSIONAL STACKED CAPACITOR CELL FOR 16M AND 64M DRAMS", International Electron Devices Meetings, 592-IEDM 88, December 11-14, 1988). In order to increase the integration density, it is necessary to reduce the two-dimensional size of each memory cell without reducing the capacitance of each stacked capacitor. In order to fabricate 64Mbit DRAMs, a feature scale approximately equal to 0.3 [µm] is required. However, the conventional photolithography technique can realize a feature scale approximately equal to a maximum of 0.5 [µm]. 64Mbit DRAMs can be realized by reducing the size of each storage (stacked) capacitor. For this purpose, it is necessary to reduce the size of a contact window (opening) for a storage electrode which is a part of the stacked capacitor. As described above, since the feature scale realized by the conventional photolithography technique is approximately 0.5 [µm], it is impossible to form the contact window having a size approximately equal to 0.3 [µm]. It is also necessary to reduce the size of a window (contact hole) provided for connecting a word line formed of, for example, polysilicon, and a low-resistance wiring line (word-line shunt layer) formed of Al or Al alloy, directed to preventing the occurrence of a delay in signal transmission in the word line. Japanese Laid-Open Patent Application No. 63-119239 discloses a method for forming a fine pattern narrower than a feature scale limit of the conventional photolithography technique. The application teaches a process in which polysilicon, PSG or SiO 2 is grown on an SiO 2 mask having a window through which a substrate is partially exposed, and a grown film on the mask and the exposed substrate surface is anisotropically etched, so that a sidewall is formed on the substrate so that it is formed around the entire inner wall of the window in the mask. The distance between opposite surfaces of the sidewall in the window is less than the feature scale limit. Thus, a surface area of the substrate less than the feature scale limit is exposed through the sidewall in the window. Then, the substrate is etched in such a way that the combination of the sidewall and the mask function as an etching mask, so that a hole is formed in the substrate. The above-mentioned Patent Application discloses an arrangement in which the mask is formed of SiO 2 and a member to be processed is formed of Si. Thus, the removal of the mask material can be easily made. However, when a multilayer structure, such as DRAMS, is produced, it is necessary to consider three layers of a mask material, a material to be processed and a underlying material which is located under the processed material and which is exposed through a hole formed in the processed material. In this case, it is necessary to prevent the exposed portion of the underlaying material from be damaged during a process in which the mask material is removed. Further, if the mask material is left in the finalized products, it is necessary to have no problem arising from the existence of the left mask material. The above-mentioned Japanese Application does not suggest the above matters. Japanese Laid-Open Patent Application No. 60-224218 discloses the use of a sidewall directed to providing a window (contact hole) smaller than the feature scale limit of the conventional photolithography technique. The sidewall is formed of Al and formed on an SiO 2 layer and around an inner wall of a window formed in a silicon nitride (Si 3 N 4 ) layer also formed on the SiO 2 layer. The SiO 2 layer is selectively etched in such a way that the Al sidewall and the Si 3 N 4 layer function as mask layers. However, it is very difficult to form the Al sidewall in contact with the inner wall of the window in the Si 3 N 4 layer, since Al has a poor coverage characteristic. Further, it is necessary to form the Si 3 N 4 layer which is sufficiently thick, because the selective etching ratio of Si 3 N 4 to SiO 2 is small. Japanese Laid-Open Patent Application No. 63-116430 (which corresponds to U.S. patent application S.N. 924,223 filed on October 28, 1986) teaches the use of a sidewall for forming a hole smaller than the scale limit of the conventional photolithgraphy technique. The just above application shows a lift-off process for removing the mask material. However, the lift-off process has a problem in that some of the mask material separated from the substrate is re-adhered hereto. This frequently causes a pattern fault in a subsequent process. The Japanese application of concern does not disclose an effective step to process the mask material. Further, the Japanese application shows a sidewall formed on the side surface of a photosensitive material. It is necessary to form the sidewall at a low temperature due to the thermal stability of the photosensitive material. Thus, there is a great limitation regarding the selection of mask materials. In addition, the structure shown in the Japanese application of concern is limited to a special application. Further, the European Patent Application No. 0 010 596 discloses a method of forming a structure having a contact hole. The third embodiment of the EP 0 010 596 describes according to Figs. 3A-3D a method comprising the steps of: (a) forming an insulating layer (34, 35) on a silicon substrate (20); (b) forming a polysilicon layer (23) on said insulating layer (34, 35); (c) forming an opening (26, 27) in said polysilicon layer (23); (d) forming a sidewall (38) of silicon dioxide; and (e) selectively etching said insulating layer (34, 35). The insulating film sidewall remains by the final step rather than removing. When an underlying insulating layer is etched to form a contact therein in the case where the insulating sidewall is used, the insulating sidewall is concurrently etched with the underlying insulating layer. Hence it is very difficult to control the etching of the underlying insulating layer. DE 39 16 228 A1 discloses a layer structure according to the preamble of claim 22. IBM Technical Disclosure Bulletin, Vol. 30, No. 8, January 1988, pages 252 and 253 discloses a method of forming small contact holes in an insulator having dimensions smaller than can be resolved with the present lithography. To achieve a small hole in a first material, on a second material formed on the first material and having a lithography hole a thin layer is conformally deposited. If the material of the layer has a slower etch rate than the first material or the second material is much thicker, reactive ion etching is used to remove the thin layer from all but the vertical surfaces, and the reactive iron etching is continued to form a small hole in the first material. The object of the present invention is to provide a layer structure having a contact hole with an opening smaller than the minimum opening attainable by photolithography technique and a method of forming such a structure. The object is achieved by a method of forming a structure according to claim 1 and by a layer structure according to claim 22. According to the present invention, there is also provided a dynamic random access memory having any of the above-mentioned structures. According to the present invention, there is also provided a fin-shaped capacitor and a method for producing such a fin-shaped capacitor. Other objects, features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings, in which: FIG.1A through FIG.1H are cross-sectional views showing steps of an improved method for producing a layer structure having a contact hole according to a first preferred embodiment of the present invention; FIG.2 is a cross-sectional view showing a second preferred embodiment of the present invention; FIG.3 is a cross-sectional view showing a third preferred embodiment of the present invention; FIG.4 is a cross-sectional view showing a fourth preferred embodiment of the present invention; FIG.5A through 5N are cross-sectional views showing steps of a DRAM production method according to a fifth preferred embodiment of the present invention; FIG.6 is a plan view of a DRAM produced by the fifth preferred embodiment of the present invention; FIGS.7A through 7E are cross-sectional views showing a sixth preferred embodiment of the present invention; FIGS.8A and 8B are cross-sectional views showing a first variation of the fifth preferred embodiment of the present invention; FIG.9 is a cross-sectional view showing a second variation of the fifth preferred embodiment of the present invention; FIGS.10A through 10J are cross-sectional views showing an seventh preferred embodiment of the present invention; FIGS.11A through 11G are cross-sectional views showing a eighth preferred embodiment of the present invention; FIGS.12A through 12F are cross-sectional views showing a variation of the eighth preferred embodiment of the present invention; and FIGS.13A through 13G are cross-sectional views showing a modification of the variation shown in FIGS.12A through 12F. description will now be given of a first preferred embodiment of the present invention with reference to FIG.1A through FIG.1H. Referring to FIG.1A, a conductive layer 2 formed of, for example, polysilicon, is formed on a base 1 formed of an insulator, such as SiO 2 . The polysilicon layer 2 is a word line of a DRAM, for example. An insulating layer 3 formed of, for example, BPSG (boron-phosphosilicate glass), is grown to, for example, 0.5 µm on the entire surface by a CVD process. The BPSG layer 3 is heated in a wet atmosphere at 850°C for 10 minutes, and reflown, so that a substantially flat surface of the BPSG layer 3 can be formed. Then, a polysilicon layer 4 is grown to, for example, 1000 angstrom by the CVD process. After that, a photoresist film 5 is coated, and etched by the conventional photolithography technique, so that the photoresist film 5 functions as an etching resist having a hole pattern can be formed. Subsequently, the polysilicon layer 4 is selectively etched by an RIE (reactive ion etching) process in which a CCl 4 /O 2 gas is used and the photoresist film 5 functions as an etching mask. Thereby, a first opening 6 having a width (diameter) approximately equal to 0.5 µm is formed in the polysilicon layer 4. As shown in FIG.1B, a polysilicon layer 7 is grown to, for example, 1500 angstroms on the entire surface including the first opening 6 by CVD. Then, as shown in FIG.1C, the polysilicon layer 7 is selectively etched by the RIE process using a CCl 4 /O 2 gas, so that a sidewall 8 is formed on an inner wall (sidewall) of the first opening 6 formed in the polysilicon layer 4. The sidewall 8 defines a second opening 9 having a width approximately equal to 0.2 µm. As shown in FIG.1D, the BPSG layer 3 is selectively etched in an RIE process using a CHF 3 /He gas in which the polysilicon layer 4 and the sidewall 8 function as masks. Thereby, a contact hole 10 through which the polysilicon layer 2 is partially exposed is formed in the BPSG layer 3. As shown in FIG.1E, a photoresist film 11 is formed on the entire surface including the contact hole 10. Then, as shown in FIG.1F, the entire surface of the photoresist film 11 is exposed and developed. During this process, a small amount of light enters a bottom portion of the contact hole 10. Thus, a part of the photoresist film 11 is left in the contact hole 10. The polysilicon layer 4 and the sidewall 18 are dry-etched in a CF 4 /O 2 plasma atmosphere in a state where the polysilicon layer 2 is protected against dry etching due to the existence of the photoresist film 11 in the contact hole 10. During the dry etching process, the polysilicon layer 4 and the sidewall 8 are isotropically etched. After that, the photoresist film 11 is removed in an O 2 plasma. After that, an Al alloy (or Al) 12 is deposited on the upper surface including the contact hole 10 by a sputtering process. Then, the Al alloy layer 12 is etched, so that a desired Al (or Al alloy) pattern is formed. Thereby, the polysilicon word line 2 is connected to the Al alloy layer 12 via the contact hole 10. It will be noted that the contact hole 10 has a width smaller than the feature scale limit of the conventional photolithographic technique. It will also be noted that the above-mentioned production method is suitable for forming a contact hole for connecting the word line and the word-line shunt layer which is provided for preventing the occurrence of a delay in transmitting a signal via the word line. The BPSG layer 3 can be substituted for a stacked member in which a PSG layer and an SiO 2 layer are alternately stacked. It is also possible to employ an alternative step instead of the step shown in FIG.1H. In the alternative step, after the polysilicon layer 4 and the sidewall 8 are removed, the BPSG layer 3 is reflowed by heating the device in an N 2 atmosphere at 850°C for 20 minutes, so that an upper edge of the contact hole 10 is smoothly curved. The existence of such a smoothly curved upper edge of the contact hole 10 improves the coverage of the Al alloy layer 12. A description will now be given of a second preferred embodiment of the present invention with reference to FIG.2. A layer structure shown in FIG.2 is the same as that shown in FIG.1B except that an SiO 2 layer 13 is formed on the polysilicon layer 4. More specifically, the SiO 2 film 13 is grown to, for example, about 200 angstroms on the polysilicon layer 4 by CVD. Then, the photoresist film 5 shown in FIG.1A is formed on the entire surface. After that, the first opening 6 is formed in the SiO 2 layer 13 and the polysilicon layer 4. Then, the polysilicon layer 7 is formed on the photoresist film 5 and in the first opening 6 in the same way as shown in FIG.1B. Then, the polysilicon layer 7 is anisotropically etched in the vertical direction. The SiO 2 layer 13 functions as an etching stopper during the step shown in FIG.1C, so that it is possible to prevent a decrease in the thickness of the polysilicon layer 4. Further, it becomes easy to detect the end of etching since the SiO 2 layer 13 is exposed. It will be noted that the SiO 2 layer 13 is removed together with the BPSG layer 3 during the step shown in FIG.1E. Thus, it is not necessary to provide a special step to remove the SiO 2 layer 13. A description will now be given of a third preferred embodiment of the present invention with reference to FIG.3, in which those parts which are the same as those shown in the previous figures are given the same reference numerals. In the step shown in FIG.1G, the polysilicon layer 4 and the sidewall 8 are removed. On the other hand, according to the third embodiment of the present invention, as shown in FIG.3, the polysilicon layer 4 and the sidewall 8 are not removed, but left on the BPSG layer 3. After the layer structure shown in FIG.1D is obtained, the stacked layer 16 is formed on the entire surface including the polysilicon layer 4, the sidewall 8 and the exposed surface of the polysilicon layer 2 by CVD, for example. The stacked layer 16 consists of a Ti layer having a thickness of 200 angstroms and a TiN layer having a thickness of 1000 angstroms. Hereafter, the stacked layer 16 is referred to as a Ti/TiN layer 16. After the Ti/TiN layer 16 is formed, the Al alloy (or pure Al) 17 is deposited on the Ti/TiN layer 16 by sputtering. After that, the polysilicon layer 4, the Ti/TiN layer 16 and the Al alloy layer 17 are patterned by etching. It will be noted that if the Al alloy layer (or pure Al layer) 17 is deposited directly on the polysilicon layer 4 and the polysilicon sidewall 8, it will easily react to silicon in the layer 4 and the sidewall 8 during a subsequent annealing process in which a protection cover is formed, for example. The above reaction increases the resistance of the Al alloy layer 17. The Ti/TiN layer 16 functions as a barrier layer which prevents the above-mentioned reaction. The barrier layer 16 is not limited to the Ti/TiN layer. A description will now be given of a fourth preferred embodiment of the present invention with reference to FIG.4, in which those parts which are the same as those shown in the previous figures are given the same reference numerals. The fourth embodiment shown in FIG.4 has the left polysilicon layer 4 and the polysilicon sidewall 8, and uses a W (tungsten) layer functioning as a wiring line instead of the Al alloy (or pure Al) layer 17 shown in FIG.3. The use of the W layer 18 does not need the deposition of the Ti/TiN layer 16. After the layer structure shown in FIG.1D is obtained, the W layer 18 is gown to, for example, 5000 angstroms on the entire surface including the polysilicon layer 4, the polysilicon sidewall 8 and the exposed surface of the polysilicon layer 2 by CVD. The contact hole 10 is filled with tungsten, so that the coverage of the W layer 18 can be improved. It will be noted that it is easy to fill the contact hole 10 with tungsten by CVD. It will be noted that tungsten has a poor adhession to BPSG or SiO 2 . On the other hand, as shown in FIG.4, the W layer 18 is formed on the polysilicon layer 4 and the polysilicon sidewall 18. Thus, the adhession problem can be solved. A description will now be given of a fifth preferred embodiment of the present invention with reference to FIG.5A through FIG.5N. The fifth preferred embodiment of the present invention provides a DRAM having a contact hole defined by a sidewall. Referring to FIG.5A, an interlayer isolation insulating layer 22 is grown to, for example, 4000 angstroms on a p-type silicon substrate 21 by a selective thermal oxidation process (a local-oxidation-of-silicon process: LOCOS), in which a silicon nitride layer is used as an oxidation-resistant mask. Next, the silicon nitride layer serving as the oxidation-resistant mask is removed, so that active areas in the p-type silicon substrate 21 are exposed. Then, a gate insulating layer 23 having a thickness equal to, for example, 100 angstroms is formed on the exposed surfaces of the p-type silicon substrate 21 by a thermal oxidation process. After that, a polysilicon layer is grown to, for example, 1000 angstroms by CVD. Then, the polysilicon layer is patterned by a resist process and RIE process in the photolithography technique in which a CCl 4 /O 2 gas is used. Thereby, word lines WL are formed. After that, As ions are introduced into the p-type silicon substrate 21 by an ion implantation process in which the word lines WL and the interlayer isolation insulating layer 2 function as masks. Thereby, an n + -type source region 24 and an N + -type drain region 25 of a transfer transistor of a memory cell are formed in the p-type silicon substrate 21. The dose of As ions is equal to, for example, 1 x 10 15 atoms/cm 2 . During a subsequent thermal process, the source and drain regions 24 and 25 are heated. After that, an insulating layer 26 formed of SiO 2 is grown to, for example, 1000 angstroms by CVD. As shown in FIG.5B, the SiO 2 insulating film 26 is selectively etched in an RIE process in which a CHF 3 /H 2 gas is used, so that a bit line contact hole 24A is formed in the SiO 2 insulating film 26. It will be noted that if a positional error occurs in the bit line contact window 24A and thus the word line WL is partially exposed, an exposed portion of the word line WL can be compensated for, as will be described later. Thus, it is sufficient to provide an alignment margin approximately equal to 0.1 µm when the bit line contact window 24A is approximately 0.5 µm in diameter. As will be indicated later, it is preferable to remove a portion of the SiO 2 insulating layer 26 in a scribe area defined in a peripheral portion of a chip at the same time as then the bit line contact hole 24A is formed. As shown in FIG.5C, an SiO 2 insulating layer 41 is grown to, for example, 1000 angstroms on the entire surface by CVD. After that, as shown in FIG.5D, the SiO 2 insulating layer 41 is selectively etched by an anisotropic etching process, such as, an RIE process using a CHF 3 /H 2 gas. By this RIE process, a sidewall SW1 having an about 0.1 µm thickness is formed so that it surrounds a vertical inner wall of the bit line contact window 24A and a curved part of the SiO 2 insulating layer 26. The sidewall SW1 defines the width of the bit line contact hole 24A, which is approximately equal to 0.3 µm. It will be noted that this dimension, 0.3 µm, is considerably smaller than the scale limit by the conventional photolithography technique (approximately 0.5 µm). The formation of the sidewall SW1 contributes to reducing the alignment margin. Even if the word line WL is partially exposed due to the positional error of the bit line contact window 24A, the sidewall 24 will completely cover the exposed surface of the word line WL. The above-mentioned contact hole forming process is distinguished from a known self-alignment contact formation method. In the self-alignment contact formation method, an insulating layer corresponding to the SiO 2 insulating layer 26 and a polysilicon layer provided for the word lines WL are patterned into an identical shape. Then, sidewalls are formed around windows. Thus, the windows are automatically defined by the sidewalls, so that there is no need for any alignment margin. Normally, the insulating film corresponding to the SiO 2 insulating layer 26 is 2000 angstroms thick, and the underlying polysilicon layer provided for forming the word lines WL is 1000 angstroms thick. Thus, the sidewall is about 3000 angstrom high, and is a large step portion formed on the surface of the substrate. On the other hand, the process which has been described with reference to FIG.5D does not form such a great step surface portion. It should be noted that the sidewall SW1 is also formed on a step portion on the surface of the SiO 2 insulating film, so that the slope of the curved surface portion of the SiO 2 insulating layer 26 can be reduced. It is necessary to etch only the SiO 2 insulating layer 41. As has been described previously, the scribe area on the peripheral portion of the chip is exposed during the process shown in FIG.5B. Since the SiO 2 layer 41 is formed on the scribe area, etching is stopped when the scribe area which is a part of the p-type silicon substrate 21 appears. This judgment of whether or not the scribe area has appeared can be carried out by detecting a change of a plasma emitting state during the RIE process, or by detecting the film thickness of the scribe area by means of a laser interference instrument. Referring to FIG.5E, a polysilicon layer is grown to, for example, 500 angstroms on the entire surface by CVD. Then, As ions are introduced into the polysilicon layer by an ion implantation process in which the dose of As ions is equal to 1 x 10 15 atoms/cm 2 . After that, a WSi 2 film is formed to, for example, 500 angstroms on the impurity doped polysilicon layer by CVD. Then, the WSi 2 layer and the impurity doped polysilicon layer are patterned by an RIE process using a CCl 4 /O 2 gas, so that a bit line BL having a two-layer structure is formed. As shown in FIG.5F, an insulating layer 27 formed of Si 3 N 4 , a spacer layer 28 formed of SiO 2 and a polysilicon layer 29' which forms a part of a storage electrode (fin electrode) of a stacked capacitor are grown in this order by CVD. The Si 3 N 4 insulating layer 27, the SiO 2 spacer layer 28 and the polysilicon layer 29' are, for example, 1000, 500 and 1000 angstroms, respectively. It will be noted that the polysilicon layer 29' plays the important role, as will be described later. As shown in FIG.5G, the polysilicon layer 29' is selectively etched by the resist process and RIE process using a CCl 4 /O 2 gas in the conventional photolithography technique, so that an opening 29A having the same pattern as the storage electrode contact window is formed in the polysilicon layer 29'. During the selective etching process, it is preferable to remove a part of the polysilicon layer 29' on the scribe area in the chip peripheral region. The opening 29A has a width approximately equal to 0.5 µm, which is the scale limit attained by the conventional photolithography technique. As shown in FIG.5H, a polysilicon layer 32a is grown to, for example, 1000 angstroms by CVD. Then, as shown in FIG.5I, the polysilicon layer is anisotropically etched by an RIE process using a CCl 4 /O 2 gas. Thereby, a sidewall 32 formed of polysilicon around the inner surface of the opening 29A in the polysilicon layer is left on the SiO 2 spacer layer 28. The sidewall 32 is approximately 0.1 µm thick. As a result, the opening 29A is reshaped into an opening 32A having a width of about 0.3 µm. This dimension of the reshaped opening 29A is smaller than the scale limit by the conventional photolithography technique. The polysilicon layer 29' and the polysilicon sidewall 32 function as masks when the underlying insulating layers are etched to form the storage electrode contact window. It should be noted that there is no special limitation on the formation of the polysilicon layer 29' and the polysilicon sidewall 32, since they are formed of polysilicon. It should also be noted that the polysilicon layer 29' and the polysilicon sidewall 32 are not removed during a subsequent process, and are utilized as parts of the storage electrode of the stacked capacitor, as will be described in detail later. As shown in FIG.5J, the SiO 2 spacer layer 28, the Si 3 N 4 insulating layer 27, the SiO 2 insulating layer 26 and the SiO 2 gate insulating layer 23 are selectively etched by an RIE process in which a CHF 3 /H 2 is used and the polysilicon layer 29' and the polysilicon sidewall 32 function as the etching masks. By the RIE process, a storage electrode contact hole 25A is formed in the above-mentioned layers, so that the n + -type drain region 25 is partially exposed. As shown in FIG.5K, a polysilicon layer 29'' is grown to, for example, 500 angstroms by CVD. A part of the polysilicon layer 29'' completely covers the inner wall of the storage electrode contact window 25A and the exposed surface of the n + -type drain region 25. It is important to form the polysilicon layer 29'' in total contact with the Si 3 N 4 insulating layer 27. Then, As ions are introduced into the polysilicon layers 29'' and 29' by an ion implantation process in which the dose of the As ions is equal to, for example, 8 x 10 15 atoms/cm 2 . By this ion implantation process, each of the polysilicon layers 29'' and 29' has a reduced resistance. It will be noted toat the layers consisting of the polysilicon layers 29' and 29'' and the sidewall 32 is thicker than the vertically extending portion of the polysilicon layer 29 Referring to FIG.5L, a spacer layer 33 formed of SiO 2 is grown to, for example, 500 angstroms on the entire surface by CVD. After that, the SiO 2 spacer layer 33 is selectively etched by the resist process and RIE process using a CHF 3 /H 2 gas in the conventional photolithography technique. By the RIE process, an opening 33A having a belt shape is formed in the SiO 2 spacer layer 33. It is sufficient to form the opening 33A so that it is wider than the storage electrode contact window 25A, because the opening 33A is used for stacking a polysilicon layer (fin) on the integrated polysilicon layer consisting of the layers 29'' and 29' and the polisilicon sidewall 32. Referring to FIG.5M, a polysilicon layer is grown to, for example, 1000 angstroms by CVD. After that, As ions are introduced into the polysilicon layer by an ion implantation process in which the dose of As ions is equal to, for example, 1 x 10 15 atoms/cm 2 . Thereby, the resistance of the polysilicon layer is reduced. After that, the above polysilicon layer, the SiO 2 spacer layer 33, and the polysilicon layers 29'' and 29' are patterned into an electrode shape by the photoresist process and RIE process using a gas of CCl 4 +O 2 or CHF 3 +H 2 . Thereafter, the SiO 2 spacer layer 33 and the SiO 2 spacer layer 28 are completely removed by an etching process in which the device is placed in an HF etchant. Thereby, polysilicon fins 29 2 and 29 1 forming a storage electrode 25 of the stacked capacitor are formed. The fin 29 2 has a bottom contact area wider than the contact hole 25A shown in FIG.5J. As has been described previously, the wall of the Si 3 N 4 insulating layer 27 which is a part of the storage electrode contact window 25A completely makes contact with the polysilicon layer 29', so that there is no possibility that the SiO 2 insulating layer 26 and the SiO 2 interlayer isolation insulating layer 22 are damaged. After that, as shown in FIG.5N, a dielectric film 36 around an exposed surface of the storage electrode 29 is formed, and a cell plate 37 (opposed electrode) is formed so that it covers the entire surface. The dielectric film 36 is formed of, for example, Si 3 N 4 . The stacked capacitor is made up of the storage electrode 29, the dielectric film 36 and the cell plate 37. Then, a PSG layer 38 is formed on the entire surface, and word-line shunt layers 39 formed of, for example, an Al alloy, are formed on the PSG layer 38. FIG.6 is a plan view of the DRAM fabricated by the above-mentioned production process. In FIG.6, WL1 and WL2 indicate word lines, and BL1 and BL2 indicate bit lines. The word-line shunt layers 39 are connected to the corresponding word lines WL via contact holes (not shown for the sake of simplicity). It is preferable to form such contact holes by the aforementioned first through fifth embodiments of the present invention. It can be seen from FIG.5K that the lowermost polysilicon fin 29 1 has the sidewall 32, and the polysilicon layers 29' and 29". The polysilicon layer 29'' is thicker than the polysilicon layer 29', and the largest thickness of the sidewall 32 is approximately equal to the thickness of the polysilicon layer 29'. A description will now be given of a sixth embodiment of the present invention with reference to FIGS.7A through 7E, in which those parts which are the same as those shown in the previous figures are given the same reference numerals. The sixth embodiment of the present invention utilizes the steps which have been described with reference to FIGS.5A through 5L. After the step related to FIG.5L, a step shown in FIG.7A is carried out. A polysilicon layer is grown to, for example, 1000 angstroms on the entire surface. After that, as shown in FIG.7B, an insulating layer 34 formed of SiO 2 is grown to, for example, 2000 angstroms by CVD. Then, the SiO 2 insulating film 34 is patterned into the shape of the storage electrode by the resist process and RIE process using a CHF 3 /H 2 gas in the photolithography technique, so that openings are formed in the SiO 2 insulating film 34. Each of the openings is approximately 0.5 µm wide, which corresponds to the scale limit of the conventional photolithography technique. Then, an insulating layer 35 formed of SiO 2 is grown to, for example, 1000 angstroms on the entire surface by CVD. Thereafter, the SiO 2 insulating layer 35 is anisotropically etched by an RIE process using a CHF 3 and H 2 gas. Thereby, sidewalls 35 are formed around inner walls of the openings in the SiO 2 layer 34, and the rest thereof is removed. Each sidewall 35 defines an opening 35A having a width approximately equal to 0.3 µm, which is smaller than the scale limit of the conventional photolithography technique. Then, as shown in FIG.7C, the polysilicon layer 42, the SiO 2 spacer layer 33, and the polysilicon layers 29'' and 29' are patterned into the shape of the storage electrode by an RIE process in which a CHF 3 /H 2 gas is used and the SiO 2 insulating layer 34 and the SiO 2 sidewalls 15 function as etching masks. It should be noted that the distance between opposite portions of the polysilicon layer 42 is approximately 0.3 µm. Similarly, the distance between opposite portions of the polysilicon layer consisting of the polysilicon layer 29'' and 29' is also approximately 0.3 µm. This means that the adjacent storage electrodes are very close to each other, and thus the surface area of each storage electrode is increased, so that each stacked capacitor can have an increased capacitance. It will be noted that during etching of the SiO 2 spacer layer 33, the SiO 2 insulating layer 34 and the SiO 2 sidewalls 35 serving as etching masks are also etched. From this point of view, it is necessary for the layer 34 and the sidewalls 35 to have a sufficient thickness. Further, a special step to remove the SiO 2 insulating layer 34 and the SiO 2 sidewalls 35 is not needed because the SiO 2 insulating layer 34 and the sidewalls 35 are removed during a subsequent step in which the device is placed in an HF etchant, as shown in FIG.7D. After that, a process identical to that which has been described with reference to FIG.5N is carried out. FIG.7E shows a DRAM fabricated according to the sixth preferred embodiment of the present invention. A storage electrode 40 has two stacked polysilicon fins 40 1 and 40 2 . The polysilicon fin 40 1 corresponds to the patterned polysilicon layers 29'' and 29' and the polysilicon sidewall 32, and the polysilicon fin 40 2 corresponds to the patterned polysilicon layer 42. It can be seen from FIG.5N and FIG.7E that the adjacent stacked capacitors shown in FIG.7E are closer to each other than those shown in FIG.5N. A description will now be given of a first variation of the aforementioned fifth preferred embodiment of the present invention, with reference to FIGS.8A and 8B, in which those parts which are the same as those shown in the previous figures are given the same reference numerals. The first variation has a storage electrode having only the polysilicon fin 29 1 which consists of the polysilicon layers 29'' and 29' and the polysilicon sidewall 32. After the step which has been described with reference to FIG.5K, the polysilicon layer consisting of the polysilicon layers 29'' and 29' and the polysilicon sidewall 32 is patterned into the shape of the storage electrode. After that, the device is placed in an HF etchant, so that the insulating layer 28 is completely removed, as shown in FIG.8A. Then, the process which has been described previously with reference to FIG.5N is carried out, so that a DRAM shown in FIG.8B can be obtained. It is noted that the insulating layer 27 can be formed of SiO 2 or Si 3 N 4 . As shown in FIG.8B, the fin 29 1 is thicker than a vertically extending portion of the storage electrode. FIG.9 illustrates a second variation of the aforementioned fifth preferred embodiment of the present invention. In FIG.9, those parts which are the same as those shown in the previous figures are given the same reference numerals. The polysilicon fin 29 1 consisting of the polysilicon layers 29'' and 29' and the polysilioon sidewall 32 is formed directly on the insulating layer 27 formed of SiO 2 or Si 3 N 4 . The polysilicon layer 29' shown in FIG.5F is grown on the insulating layer 27 without forming the insulating layer 28. Then, the same steps as has been described with reference to FIGS.5G through 5K and FIG.5N are carried out. It is also possible to form the polysilicon fin 29 2 on the polysilicon fin 29 1 in the same way as has been described with reference to FIGS.5L and 5M. A description will now be given of an seventh preferred embodiment of the present invention with reference to FIGS.10A through 10J, in which those parts which are the same as shown shown in the previous figures are given the same reference numerals. A structure shown in FIG.10B is the same as that shown in FIG.5E. Steps to obtain the structure shown in FIG.10B are the same as those which have been described with reference to FIGS.5A through 5E. As shown in FIG.10C, the Si 3 N 4 insulating layer 27, the SiO 2 spacer layer 28, the impurity-doped polysilicon layer 29', a spacer layer 45 formed of SiO 2 and an impurity-doped polysilicon layer 46' are formed in this order by CVD. For example, each of these layers is 500 angstorms thick. Then, the polysilicon layer 46', the SiO 2 spacer layer 45 and the polysilicon layer 29' are selectively etched by the resist process and the RIE process, so that an opening 29A having a thickness equal to, for example, 0.6 µm is formed therein. During the above RIE process, a CCl 4 /O 2 gas is used for the polysilicon layers 46' and 29', and a CHF 3 /He gas is used for the SiO 2 spacer layer 45. As shown in FIG.10D, a polysilicon layer 47' is grown to, for example, 2000 angstorms on the entire surface by CVD. After that, as shown in FIG.10E, the polysilicon layer 47' is anisotropically etched by an RIE process in which a CCl 4 /O 2 gas or an HBr/He gas is used. Thereby, a polysilicon sidewall 47 is formed around an inner surface of the opening 29A, and the remaining portion of the polysilicon layer 47' is removed. The sidewall 47 defines a new opening 46A having a width approximately equal to 0.2 - 0.3 µm, which is smaller than the width of the opening 29A shown in FIG.10C. After that, as shown in FIG.10F, the SiO 2 spacer layer 28, the Si 3 N 4 insulating layer 27, the SiO 2 insulating layer 26 and the SiO 2 gate insulating layer 23 are partially removed by an RIE process in which a CHF 3 /He gas is used and the polysilicon layer 46' and the polysilicon sidewall 47 function as etching masks. By this RIE process, the surface of the n + -type drain region 25 is partially exposed through a contact hole 28A. It should be noted that the width of the opening 46A is very small and equal to about 0.2 - 0.3 µ m, and that the polysilicon layer 46' and the polysilicon layer 47 functioning as the etching masks form a part of the storage electrode without being removed. Thus, it is not necessary to provide a special step to remove the polysilicon layer 46' and the polysilicon sidewall 47 functioning the etching masks. As shown in FIG.10G, a polysilicon layer 46" is grown to, for example, 500 angstroms by CVD. During this step, the polysilicon layers 46'' and 46' as well as the polysilicon sidewall 47 are integrated. Then, as shown in FIG.10H, the polysilicon layers 46''and 46', the SiO 2 spacer layer 45, and the polysilicon layer 29' are patterned into the shape of the storage electrode in this order by the resist process using a single mask and the RIE process in the conventional photolithography process. After that, as shown in FIG.10I, the device shown in FIG.10H is placed in an HF etchant, so that the exposed SiO 2 insulating layers are isotropically etched, so that a storage electrode 50 having two polysilicon fins 50 1 and 50 2 is formed. The fin 50 1 is formed of the patterned polysilicon layer 29', and the fin 50 2 is formed of the patterned polysilicon layers 46'' and 46'. The fins 50 1 and 50 2 are connected by the polysilicon sidewall 47. The polysilicon layer 46'' which is a part of the fin 50 2 vertically extends from its portion on the polysilicon layer 46' and makes contact with the n + -type drain region 25. A vertical portion 50 3 of the storage electrode 50 consists of the polysilicon sidewall 47 and the polysilicon layer 46''. The vertical portion 50 3 , the polysilicon layer 46'', and the fin 50 2 have mutually different thicknesses t 1 , t 2 and t 3 , respectively. The vertical portion 50 3 is thicker than the polysilicon layer 46'' and the fin 50 2 . Finally, as shown in FIG.10J, the dielectric film 36, the cell plate 37, the PSG passivation layer 38 and the word-line shut layers 39 are formed in the same way as has been described with reference to FIG.5N. A description will now be given of a eighth preferred embodiment of the present invention with reference to FIGS.11A through 11G, in which those parts which are the same as those shown in the previous figures are given the same reference numerals. Production steps shown in FIGS.11A and 11B are carried out in the same way as those shown in FIGS.10A and 10B. After that, as shown in FIG.11C, the Si 3 N 4 insulating layer 27, the SiO 2 spacer layer 28, the impurity-doped polysilicon layer 29', the SiO 2 spacer layer 45 and the impurity-doped polysilicon layer 46' are formed in this order by CVD. Each of these layers is 500 angstroms thick, for example. Then, the polysilicon layer 46', the SiO 2 spacer layer 45, the polysilicon layer 29' and the SiO 2 spacer layer 28 are selectively etched by the resist process and RIE process, so that an opening 28A is formed therein. It will be noted that the SiO 2 layer 28 is etched as shown in FIG.11C, while the SiO 2 layer 28 shown in FIG.10C is not etched. After that, as shown in FIG.11D, a polysilicon layer 47' is grown to, for example, 2000 angstorms by CVD. After that, as shown in FIG.11E, the polysilicon layer 47' is selectively etched by an RIE process using a CCl 4 /O 2 gas, so that a polysilicon sidewall 47a is formed so that it surrounds the inner wall of the opening 28A. The remaining portion of the polysilicon layer 47' is completely removed. The polysilicon sidewall 47a defines a new opening 46A narrower than the opening 28A. Subsequently, as shown in FIG.11F, the Si 3 N 4 insulating layer 27, the SiO 2 insulating layer 26 and the SiO 2 gate insulating layer 23 are selectively etched by an RIE process in which a CHF 3 /He gas is used and the polysilicon layer 46' and the sidewall 47a function as etching masks. By this RIE process, the surface of the n + -type drain region 25 is partially exposed through a through hole 27A having the same width as the opening 46A. After that, the aforementioned production steps are carried out, so that a DRAM shown in FIG.11G can be obtained. The length of the sidewall 37a used in the eighth embodiment of the present invention is greater than that of the sidewall 37 used in the seventh embodiment of the present invention. Thus, the sidewall 47a functions as the mask more stably than the sidewall 47. On the other hand, the distance between the sidewall 37a and the word line WL is closer than the corresponding distance obtained in the seventh embodiment of the present invention. Thus, the breakdown voltage of the DRAM shown in FIG.11G is slightly smaller than that of the DRAM shown in FIG.10J. A description will now be given of a variation of the eigth preferred embodiment of the present invention with reference to FIGS.12A through 12F, in which those parts which are the same as those shown in the previous figures are given the same reference numerals. FIGS.12A and 12B are the same as FIGS.10A and 10B. Then, as shown in FIG.12C, the Si 3 N 4 insulating layer 27, the SiO 2 layer 28, the impurity-doped polysilicon layer 29', the SiO 2 spacer layer 45 and the impurity-doped polysilicon layer 46' are formed in this order by the aforementioned process. Then, an SiO 2 insulating layer 48 is grown to, for example, 200 angstroms by CVD. Then, by using the resist process and the RIE process in the photolithography process, the SiO 2 layer 48, the polysilicon layer 46', the SiO 2 spacer layer 45, the polysilicon layer 29' and the SiO 2 spacer layer 28 are selectively removed, so that the surface of the Si 3 N 4 layer 27 is partially exposed through the opening 28A. Then, as shown in FIG.12D, the polysilicon layer 47' is grown to, for example, 2000 angstorms by CVD. After that, as shown in FIG.13E, the polysilicon layer 47' is selectively etched by RIE, so that a widewall 42b is formed around an inner wall of the opening 28A. After that, as shown in FIG.12F, the Si 3 N 4 layer 27, the SiO 2 layer 26 and the SiO 2 gate insulating layer 23 are selectively etched via the opening defined by the sidewall 47b. The SiO 2 layer 48 is removed at the same time as the SiO 2 insulating layer 26 is removed. It will be noted that the SiO 2 layer 48 functions to protect the polysilicon layer 46' against the RIE process of forming the sidewall 47b. Further, the SiO 2 layer 48 functions as the mask more stably during the time when the Si 3 N 4 insulating layer 27 is being etched. A description will now be given of a modification of the variation shown in FIGS.12A through 12F, with reference to FIGS.13A through 13G, in which those parts which are the same as those shown in the previous figures are given the same reference numerals. FIGS.13A and 13B are the same as FIGS.10A and 10B, respectively. After forming the bit line BL, as shown in FIG.13C, an SOG (spin on glass) layer 49 is formed on the entire surface so that the surface of the SOG layer 49 is substantially flat enough to prevent the growth of residuum during a subsequent process. There is a possibility that residuum may be formed on a rough surface after the selective etching process. For example, in the variation which has been described with reference to FIGS.12A through 12F, the SiO 2 layer 48 may be partially left on a rough surface portion of the polysilicon layer 46'. For the sake of simplicity, FIG.13C shows that the SOG layer 49 is completely flat. It can be seen from FIG.13C, the SOG layer 49 absorbs a roughness of the surface shown in FIG.13B. It is also possible to form a PSG reflow layer instead of the SOG layer 49. After that, the layers 28, 29' 45, 46' and 48 are formed in the same way as has been described previously. Then, these layers are selectively etched so that the opening 28A is formed, as shown in FIG.13C. Then, as shown in FIG.13D, the polysilicon layer 47' is grown to, for example, 2000 angstroms by CVD, and selectively etched by the RIE process, so that a sidewall 47b is formed, as shown in FIG.13E. Thereafter, as shown in FIG.13F, the Si 3 N 4 insulating layer 27, the SOG layer 49, the SiO 2 layer 26 and the SiO 2 layer 23 are selectively etched, so that the n + -type drain region 25 is partially exposed through the opening 27A. Finally, a DRAM shown in FIG.13G is fabricated by the aforementioned process which has been described with reference to FIG.5N. The present invention is not limited to the specifically disclosed embodiments, and variations and modifications may be made without departing from the scope of the present invention.

Claims: A method of forming a structure having a contact hole (10, 25A, 28A, 27A), comprising the steps of: (a) forming an insulating layer (3, 27) on a first conductive region (2, 25); (b) forming a second conductive layer (4, 29', 46') over said insulating layer; (c) forming an opening (6, 29A, 28A) in said second conductive layer; (d) forming a conductive sidewall (8, 32, 47, 47a, 47b) around an inner wall of said second conductive layer defining said opening, wherein said sidewall (8, 32, 47, 47a, 47b) is formed by: (d1) forming an additional conductive layer (32a) on the surface including the opening (6, 29A, 28A) in said second conductive layer; and (d2) anisotropically etching said additional conductive layer (32a) to remove the horizontally extending areas of this layer (32a) and to leave behind vertically extending parts which form the sidewall (8, 32, 47, 47a, 47b); (e) selectively etching said insulating layer in a state in which said second conductive layer and said conductive sidewall function as etching masks, so that said contact hole (10, 25A, 28A, 27A) having a width smaller than that of said opening and defined by said conductive sidewall is formed in said insulating layer and said first conductive region is exposed through said contact hole; (f) forming a third conductive layer (17, 29'', 46'') on said second conductive layer, said conductive sidewall and said first conductive region being exposed through said contact hole; and (g) patterning said third conductive layer and second conductive layer simultaneously to form a given pattern. A method as claimed in claim 1, characterized in that said method comprises, between said step (e) and said step (f) the step of: (e-1) forming a barrier layer (16) on said second conductive layer (4), said conductive sidewall (8) and said first conductive region (2) exposed through said contact hole (10); and in said step (f) said third conductive layer (17) is formed on said barrier layer, said barrier layer preventing said third conductive layer from reacting with said second conductive layer and said conductive sidewall. A method as claimed in claim 2, characterized in that said barrier layer (16) comprises a bilayer structure having a titanium layer and a titanium nitride layer; and said third conductive layer (17) comprises aluminium. A method as claimed in claim 2, characterized in that said second conductive layer (4) comprises polysilicon; and said third conductive layer (17) comprises polysilicon. A method as claimed in claim 1, characterized in that said second conductive layer (4) comprises polysilicon; said conductive sidewall (8) comprises polysilicon; and said third conductive layer (18) comprises tungsten. A method as claimed in claim 5, characterized in that said contact hole (10) is filled with tungsten of said third conductive layer (18). A method as claimed in claim 1, characterized in that said method is a method of producing a fin-shaped capacitor in a dynamic random access memory; said first conductive region (25) is a diffusion region of a semiconductor substrate; in said step (d) said conductive sidewall (32) defines a second opening (32A) having a width smaller than that of said first opening (29A); in said step (e) said contact hole (25A) formed in said insulating layer (23, 26, 27, 28) has a width substantially identical to that of said second opening; in said step (g) said second conductive layer (29') and said third conductive layer (29'') are patterned into a shape of a storage electrode (29) of a fin-shaped capacitor; and said method further comprises, after said step (g), the steps of (h) forming a dielectric film (36) around an exposed surface of said storage electrode; and (i) forming a cell plate (37) around said storage electrode covered by said dielectric film. A method as claimed in claim 7, characterized in that said step (a) comprises the steps of: forming a first insulating layer (23, 26, 27) directly on said semiconductor substrate; and forming a second insulating layer (28) on said semiconductor substrate, said insulating layer (23, 26, 27, 28) having said first and second insulating layers; and said method further comprises the step of: isotropically etching said second insulating layer, so that said storage electrode is spaced apart from said first insulating layer. A method as claimed in claim 1, characterized in that said method is a method of producing a fin-shaped capacitor in a dynamic random access memory; said first conductive region (25) is a diffusion region of a semiconductor substrate; in said step (d) said conductive sidewall (32) defines a second opening (32A) having a width smaller than that of said first opening (29A); in said step (e) said contact hole (25A) formed in said insulating layer (23, 26, 27, 28) has a width substantially identical to that of said second opening; said method comprises, between said step (f) and said step (g), the steps of: (f-1) forming, on said third conductive layer (29''), a second insulating layer (33) having a third opening (33A) having a width substantially identical to that of said first opening; and (f-2) forming a fourth conductive layer (29 2 ) on said second insulating layer and said third conductive layer exposed through said third opening; in said step (g) said second and third conductive layers (29', 29") and said second insulating layer (33) are patterned into a shape of a storage electrode of a fin-shaped capacitor; and said method further comprises, after said step (g), the steps of (h) isotropically etching said second insulating layer so that said second insulating layer is removed; (i) forming a dielectric film (36) around an exposed surface of said storage electrode; and (j) forming a cell plate (37) around said storage electrode covered by said dielectric film. A method as claimed in claim 9, characterized in that said step (a) comprises the steps of: forming a third insulating layer (23, 26) directly on said semiconductor substrate; forming a fourth insulating layer (49) on said third insulating layer; and forming a fifth insulating layer (27) on said fourth insulating layer, said first insulating layer (23, 26, 27, 28) having said third and fourth insulating layers; said fifth insulating layer is formed of a material identical to that of said third insulating material; and said fifth insulating layer is removed during said step (h), so that said storage electrode is spaced apart from said fourth insulating layer. A method as claimed in claim 9, characterized in that said step (g) comprises the steps of: forming a third insulating layer (34) having a fourth opening (34A) on said fourth conductive layer (29 2 ), said fourth opening being located at a position different from that of said first opening (25A); forming an insulating sidewall (35) around an inner surface of said fourth insulating layer (49) defining said fourth opening, said insulating sidewall defining a fifth opening (35A) having a width smaller than that of said fourth opening; and etching said second, third and fourth conductive layers (29'; 29''; 29 2 ) and said second and third insulating layers (33; 34) in a state in which said fourth insulating layer and said insulating sidewall function as etching masks. A method as claimed in claim 1, characterized in that said method is a method of producing a fin-shaped capacitor in a dynamic random access memory; said first conductive region (25) is a diffusion region of a semiconductor substrate; in said step (b) a plurality of stacked-layer structures (28, 29'; 45, 46') is formed, a lowermost one (28, 29') of said stacked-layer structures being formed on said insulating layer (23, 26, 27), each of said stacked-layer structures having a spacer layer (28, 45) and said second conductive layer (29', 46'); in said step (c) said opening (29A) is formed in said stacked-layer structures except said spacer layer (28) of said lowermost one of said stacked-layer structures (29'); in said step (d) said conductive sidewall (47) is formed around an inner wall of said stacked-layer structures defining said opening, and defines a second opening (46A) having a width smaller than that of said first opening (29A); in said step (e) also said spacer layer (28) of the lowermost one of said stacked-layer structures is selectively etched in a state in which said second conductive layer (46') of an uppermost one of said stacked layer structures and said conductive sidewall (47) function as etching masks, and said contact hole (28A) is formed in said spacer layer of the lowermost one of said stacked-layer structures and said insulating layer; in said step (f) said third conductive layer (46") is formed on said second conductive layer (46') of the uppermost one of said stacked-layer structures, said conductive sidewall and said diffusion region; in said step (g) said third conductive layer (46'') and said stacked-layer structures except said spacer layer (28) of the lowermost one of said stacked-layer structures are patterned into a shape of a storage electrode (50) of a fin-shaped capacitor; and said method further comprises, after said step (g), the steps of (h) isotropically etching said spacer layer (28, 45) of each of said stacked-layer structures so that said spacer layer is removed; (i) forming a dielectric film (36) around said storage electrode; and (j) forming a cell plate (37) around said storage electrode covered by said dielectric film. A method as claimed in claim 1, characterized in that said method is a method of producing a fin-shaped capacitor in a dynamic random access memory; said first conductive region (25) is a diffusion region of a semiconductor substrate; in said step (b) a plurality of stacked-layer structures (28, 29'; 45, 46') is formed, a lowermost one (28, 29') of said stacked-layer structures being formed on said insulating layer (23, 26, 27), each of said stacked-layer structures having a spacer layer (28, 45) and said second conductive layer (29, 46'); in said step (c) said opening (29A) is formed in said stacked-layer structures; in said step (d) said conductive sidewall (47a, 47b) is formed around an inner wall of said stacked-layer structures defining said opening, and defines a second opening (46A) having a width smaller than that of said first opening (29A) ; in said step (e) said second conducive layer (46') of an uppermost one of said stacked-layer structures and said conductive sidewall function as etching masks; in said step (f) said third conductive layer (46") is formed on said second conductive layer (46') of the uppermost one of said stacked-layer structures, said conductive sidewall and said diffusion region; in said step (g) said third conductive layer (46'') and said stacked-layer structures are patterned into a shape of a storage electrode (50) of a fin-shaped capacitor; and said method further comprises, after said step (g), the steps of (h) isotropically etching said spacer layer (28, 45) of each of said stacked-layer structures so that said spacer layer is removed; (i) forming a dielectric film (36) around said storage electrode; and (j) forming a cell plate (37) around said storage electrode covered by said dielectric film: A method as claimed in claim 12 or 13; characterized in that said method further comprises, between said step (b) and said step (c) the step of: · forming a second insulating layer (48) on said second conductive layer (46') of the uppermost one of said stacked-layer structures; and said second insulating layer is removed during said step (e). A method as claimed in claim 12 or 13, characterized in that said step (a) comprises the steps of: forming a second insulating layer (23, 26) on said semiconductor substrate; forming a third insulating layer (49) on said second insulating layer; heating said third insulating layer so that said third insulating layer has a substantially flat surface; and forming a fourth insulating layer (27) on said substantially flat surface of said third insulating layer; and said second, third and fourth insulating layers form said insulating layer (23, 26, 27). A method as claimed in claim 12 or 13 characterized in that said second conductive layer (29', 46') comprises polysilicon; and said spacer layer (28, 45) comprises silicon oxide. A method as claimed in claim 15, characterized in that said second and fourth insulating layers (23, 26, 27) comprise silicon oxide; and said third insulating layer (49) comprises one of a spin-on-glass layer and a phosphosilicate glass layer. A method as claimed in claim 1, characterized in that said method is a method of producing a fin-shaped capacitor in a dynamic random access memory; said first conductive region (25) is a diffusion region of a semiconductor substrate; in said step (b) a plurality of stacked-layer structures (63-68) is formed, a lowermost one (63, 64) of said stacked-layer structures being formed on said insulating layer (23, 26, 62), each of said stacked-layer structures having a spacer layer (63, 65, 67) and said second conductive layer (64, 66, 68); in said steps (c), (d) and (e) said contact hole (62A) is formed in said stacked-layer structures and said insulating layer so that said diffusion region is exposed through said contact hole; in said step (f) said third conductive layer (75) is formed on said second conductive layer (68) of an uppermost one of said stacked-layer structures; in said step (g) said third conductive layer (75) and said stacked-layer structures are patterned into a shape of a storage electrode (90) of a fin-shaped capacitor; and said method further comprises, after said step (g), the steps of (h) isotropically etching said spacer layer (63, 65, 67) of each of said stacked-layer structures so that said spacer layer is removed; (i) forming a dielectric film (36) around said storage electrode; and (j) forming a cell plate (37) around said storage electrode covered by said dielectric film. A method as claimed in claim 18, characterized in that said step (a) comprises the steps of: forming a second insulating layer (23, 26) on said semiconductor substrate; forming a third insulating layer (62) on said second insulating layer; heating said third insulating layer so that said third insulating layer has a substantially flat surface; and forming a fourth insulating layer (64) on said substantially flat surface of said third insulating layer; and said fourth insulating layer is removed during said step (h). A method as claimed in claim 19, characterized in that said second and fourth insulating layers (26, 63) comprise silicon oxide; said third insulating layer (62) comprises silicon nitride; and said second and third conductive layers comprise polysilicon. A method as claimed in claim 18, characterized in that said steps (c) to (e) comprise the steps of: forming a fourth conductive layer (70) on a top of said stacked-layer structures; forming a second insulating layer (71) on said fourth conductive layer, forming a photoresist film (72) having a window pattern on said second insulating layer; etching said second insulating layer and said fourth conductive layer so that a first window is formed in said fourth conductive layer and said second insulating layer; and removing said photoresist film; and said conductive sidewall (74) is formed around an inner wall of said fourth conductive layer defining said window, wherein said contact hole formed by said steps (c) to (e) having a size defined by said conductive sidewall. A layer structure, comprising: a first conductive region (2, 25); an insulating layer (3, 27) formed on said first conductive region and having a contact hole (10, 25A, 28A, 27A), said first conductive region being exposed through said contact hole; a second conductive layer (4, 29', 46') formed over said insulating layer and having an opening (6, 29A, 28A) having a width of approximately 0.5 µm, which is the scale limit attained by the conventional photolithography technique and being large than that of said contact hole, wherein said opening (6, 29A, 28A) surrounds said contact hole (10, 25A, 28A, 27A); a conductive sidewall (8, 32, 47, 47a, 47b) formed over said insulating layer exposed through said opening and formed around an inner wall of said second conductive layer defining said opening, wherein the part of the conductive sidewall which is furthest from the second conductive layer defines the contour of said contact hole; and a third conductive layer (17, 29'', 46'') formed on said second conductive layer, said conductive sidewall and said first conductive region being exposed through said contact hole. A layer structure as claimed in claim 22, characterized in that the layer structure further comprises a barrier layer (16) formed on said second conductive layer (4), said conductive sidewall (8) and said first conductive region (2) exposed through said contact hole (10); and said third conductive layer (17) is formed on said barrier layer, said barrier layer preventing said third conductive layer from reacting with said second conductive layer and said conductive sidewall. A layer structure as claimed in claim 22, characterized in that said third conductive layer (17) comprises aluminium; said first conductive region (2) and said second conductive layer (4) comprise polysilicon; and said conductive sidewall (8) comprises polysilicon. A layer structure as claimed in claim 23, characterized in that said barrier layer (16) comprises a bilayer structure having a titanium layer and a titanium nitridyer. A layer structure as claimed in claim 22, characterized in that said third conductive layer (18) comprises a material which causes no reaction with said second conductive layer (4) and said conductive sidewall (8). A layer structure as claimed in claim 26, characterized in that said third conductive layer (18) comprises tungsten; said second conductive layer (4) comprises polysilicon; and said conductive sidewall (8) comprises polysilicon. A layer structure as claimed in claim 22, characterized in that said layer structure is a dynamic random access memory; said first conductive region (25) is a first diffusion region of a semiconductor substrate (21) having said first diffusion region (25) and a second diffusion region (24) of a transfer transistor; said insulating layer (23, 26, 27) further has a second contact hole (24A) exposing said second diffusion region; the layer structure further comprises a word line (WL) covered by said insulating layer; a stacked capacitor (29, 36, 37) which is in contact with said first diffusion region through said first contact hole; a bit line (BL) which is in contact with said second diffusion region through said second contact hole; and a second insulating layer (38) covering said stacked capacitor; and said stacked capacitor comprises a storage electrode (29, 40), a dielectric film (36) and a cell plate (37); said storage electrode which is in contact with said first diffusion region through said first contact hole has a first fin (29 1 , 40 1 ) having said second conductive layer (29'), said conductive sidewall (32) and said third conductive layer (29''); and a second opening (32A) is formed by said second portion having a width substantially identical to that of said first contact hole. A layer structure as claimed in claim 22, characterized in that said layer structure is a fin-shaped capacitor; said first conductive region (25) is a diffusion region of a semiconductor substrate (21); the layer structure further comprises a storage electrode (29, 40) having an exposed surface; a dielectric film (36) formed around said exposed surface of said storage electrode; and a cell plate (37) covering said storage electrode surrounded by said dielectric film; and said storage electrode is in contact with said diffusion region (25) through said contact hole (25A) formed in said insulating layer (23, 26, 27) formed on said semiconductor substrate; said storage electrode has a first fin (29 1 , 29 2 ) having said second conductive layer (29'), said conductive sidewall (32) and said third conductive layer (29''); and second opening (32A) is formed by said second portion having a width substantially identical to that of said contact hole (25A). A layer structure as claimed in claim 28 or 29, characterized in that said storage electrode comprises a second fin (29 2 , 40 2 ) having a contact area in which said second fin is in contact with said first fin (29 1 , 40 1 ); said contact area is wider than said contact hole (25A); and said first and second fins are spaced apart from each other. A layer structure as claimed in claim 28 or 29 characterized in that said first fin (29 1 , 40 1 ) is spaced apart from said insulating layer (27). A layer structure as claimed in claim 28 or 29, characterized in that said first fin (29 1 , 40 1 ) of said storage electrode is formed on said insulating layer (27). A layer structure as claimed in claim 30, characterized in that said first fin (29 1 , 40 1 ) of said storage electrode is thicker than said third conductive layer (29'') thereof. A layer structure as claimed in claim 28 or 29, characterized in that said storage electrode having said first fin (29 1 , 40 1 ) having said second conductive layer, said conductive sidewall and said third conductive layer comprises polysilicon. A layer structure as claimed in claim 22, characterized in that said layer structure is a dynamic random access memory; said first conductive region (25) is a first diffusion region of a semiconductor substrate (21) having said first diffusion region (25) and a second diffusion region (24) of a transfer transistor; said insulating layer (23, 26, 27) further has a second contact hole (24A) exposing said second diffusion region; the layer structure further comprises a word line (WL) covered by said insulating layer; a stacked capacitor (29, 36, 37) which is in contact with said first diffusion region through said first contact hole; a bit line (BL) which is in contact with said second diffusion region through said second contact hole; and a second insulating layer (38) covering said stacked capacitor; and said stacked capacitor comprises a storage electrode (50), a dielectric film (36) and a cell plate (37); and said storage electrode which is in contact with said first diffusion region through said first contact hole has a plurality of said second conductive layers (29', 46'), said conductive sidewall (47, 47a, 47b) connecting said second conductive layers to each other, and said third conductive layer (46'') extending on an uppermost one (46') of said second conductive layers and said conductive sidewall. A layer structure as claimed in claim 35, characterized in that said conductive sidewall (47) of said storage electrode is spaced apart from said first insulating layer (27); and a lowermost one (29') of said second conductive layers of said storage electrode is spaced apart from said first insulating layer. A layer structure as claimed in claim 35, characterized in that said conductive sidewall (47a, 47b) of said storage electrode is in contact with said first insulating layer (27) ; and a lowermost one (29') of said second conductive layers of said storage electrode is spaced apart from said first insulating layer. A layer structure as claimed in claim 37, characterized in that said storage electrode (50) has a substantially flat surface which extends above said word line (WL). A layer structure as claimed in claim 35, characterized in that said storage electrode (50, 36, 37) comprises polysilicon. A layer structure as claimed in claim 22, characterized in that said layer structure is a fin-shaped capacitor; said first conductive region (25) is a diffusion region of a semiconductor substrate (21); the layer structure further comprises a storage electrode (50) having an exposed surface; a dielectric film (36) formed around said exposed surface of said storage electrode; and a cell plate (37) covering said storage electrode surrounded by said dielectric film; and said storage electrode is in contact with said diffusion region (25) through said contact hole (25A) formed in said insulating layer (23, 26, 27) formed on said semiconductor substrate; said storage electrode has a plurality of said second conductive layers (29', 46'), said conductive sidewall (47, 47a, 47b) connecting said second conductive layers to each other, and said third conductive layer (46'') extending on an uppermost one (46') of said second conductive layers and said conductive sidewall. A layer structure as claimed. in claim 40, characterized in that said conductive sidewall (47) of said storage electrode is spaced apart from said insulating layer (27); and a lowermost one (29') of said second conductive layers of said storage electrode is spaced apart from said insulating layer. A layer structure as claimed in claim 40, characterized in that said conductive sidewall (47a, 47b) of said storage electrode is in contact with said insulating layer (27); and a lowermost one (29') of said second conductive layers of said storage electrode is spaced apart from said insulating layer. A layer structure as claimed in claim 42, characterized in that said insulating layer (27) has a substantially flat surface on which said conductive sidewall (47b) of said storage electrode is formed. A layer structure as claimed in claim 22, characterized in that said layer structure is a dynamic random access memory; said first conductive region (25) is a first diffusion region of a semiconductor substrate (21) having said first diffusion region (25) and a second diffusion region (24) of a transfer transistor; said insulating layer (23, 26, 62) further has a second contact hole (24A) exposing said second diffusion region; the layer structure further comprises a word line (WL) covered by said insulating layer; a stacked capacitor (90, 36, 37) which is in contact with said first diffusion region through said first contact hole (62A); a bit line (BL) which is in contact with said second diffusion region through said second contact hole; and a second insulating layer (38) covering said stacked capacitor; and said stacked capacitor comprises a storage electrode (90), a dielectric film (36) and a cell plate (37); and said storage electrode which is in contact with said first diffusion region through said first contact hole has a plurality of said second conductive layers (64 (90 1 ), 66 (90 2 ), 68), and said conductive sidewall (75) connecting said second conductive layers to each other and extending on an uppermost one (68) of said second conductive layers. A layer structure as claimed in claim 22, characterized in that said layer structure is a fin-shaped capacitor; said first conductive region (25) is a diffusion region of a semiconductor substrate (21); the layer structure further comprises a storage electrode (90, 36, 37) having an exposed surface; a dielectric film (36) formed around said exposed surface of said storage electrode; and a cell plate (37) covering said storage electrode surrounded by said dielectric film; and said storage electrode is in contact with said diffusion region (25) through said contact hole (62A) formed in said insulating layer (23, 26, 62) formed on said semiconductor substrate; said storage electrode has a plurality of said second conductive layers (64 (90 1 ), 66 (90 2 ), 68), and said conductive sidewall (75)connecting said second conductive layers to each other and extending on an uppermost one (68) of said second conductive layers. A layer structure as claimed in claim 44 or 45, characterized in that a lowermost one (64, 90 1 ) of said second conductive layers is spaced apart from said insulating layer (62). A layer structure as claimed in claim 44 or 45, characterized in that a lowermost one (64, 90 1 ) of said second conductive layers is in contact with said insulating layer (62). A layer structure as claimed in claim 40, 44 or 45, characterized in that said storage electrode (90) comprises polysilicon.

Inventors: EMA TAJI, EMA, TAJI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1991
Main classification: H01L27
IPC codes: H01L21, H01L27