Method and apparatus for driving a display device

Abstract: When performing gradation display by giving digital value as display data to each pixel arranged in a matrix on a display panel and emitting the pixels at a brightness corresponding to the magnitude of the digital value, plural display frame periods are set as one cycle, and digital value α is given as display data in certain display frames selectively determined in the cycle, and digital value β = α ± M (M being a positive integer) is given as display data in other display frames in the same cycle. Accordingly, a halftone gradation between the gradation corresponding to the digital value α and the gradation corresponding to the digital value β may be displayed in plural degrees depending on the rate of the number of display frames given the digital value α and the number of display frames given the digital value β.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for driving a display device such as liquid crystal display, plasma display, EL display and LED display. 2. Description of the Prior Art Hitherto, for example, for gradation display by a liquid crystal display device of active matrix driving system, analog signals are applied as the display data corresponding to each pixel disposed in matrix on a display panel, and the control voltage of the display panel is varied depending on the magnitude of the analog signal, thereby achieving gradation display. In another method, digital signals are given as the display data, and the analog voltage corresponding to input digital value is selected, and the selected analog voltage is used as the control voltage of the display panel for gradation display. In a liquid crystal display apparatus of simple matrix driving system, a frame thinning method is employed for gradation display. In this method, plural display frame periods are determined as one cycle, and depending on the gradation to be displayed, the number of display frames for ON driving of the pixels in the cycle and the number of display frames for OFF driving of the pixels are variably set. In the case of plural gradation displays by a large liquid crystal display device of 10 inches or larger size by using such conventional method, since the capacity of the electrode becomes large because of the large size of the display panel, when an analog signal is fed as display data, it becomes difficult to drive the electrode by transmitting the analog voltage at high speed. Also, when entering digital value as display data, it is necessary to generate the analog voltage by the number of the digital values, and prepare the changeover circuits for selecting the voltages by the number of pixels per line to be arranged on the display panel, which results in the increase of the circuit scale. Furthermore, in the case of plural gradation displays by the frame thinning method, in the liquid crystal display device of simple matrix driving system, there is no problem because the response speed is slow, but in the liquid crystal display device of active matrix driving system, the response speed is high, and the flicker is very obvious, and the display grade is extremely lowered. SUMMARY OF THE INVENTION It is hence a primary object of the invention to provide a method and apparatus for driving a display device which overcome the above problems. This invention is defined by independent claims 1 and 8. The dependent claims 2 to 7 and 9 to 15 are directed to embodiments of the invention. According to the invention, either a first digital value α or a second digital value β is supplied as display data in each display frame in one cycle, and the gradation of the mean of these digital values, that is, the halftone gradation of the gradation corresponding to the digital value α and the gradation corresponding to the digital value β is displayed. In each display frame however, each pixel is not set either in ON drive or in OFF drive alternately, but either one of two adjacent gradations is set in display state. As a result, plural gradations can be displayed with less obvious flicker. Also, no extra hardware is necessitated for the generation and selection of additional analogue voltages for driving the display. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing a basic structure of a driving circuit to which a driving method of one of the embodiments of the invention is applied, Fig. 2 is a timing chart for showing the relation between each synchronizing signal and display frame in the same driving method, and Fig. 3 is a block diagram for explaining another embodiment of the invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Now referring to the drawings, preferred embodiments of the invention are described below. Fig. 1 is a block diagram showing a composition of a driving circuit for 29 gradation display in a liquid crystal display device 1 of active matrix driving method. The liquid crystal display device 1 displays, on a display panel not shown in the drawing, by receiving three-bit digital signals at input terminals E2, E1, E0, as display data corresponding to pixels arranged in matrix. The input three-bit digital signal denotes a digital value of 0 to 7, and therefore the liquid crystal display device I is equipped with a function for selecting an analog voltage corresponding to each digital value, and operating the corresponding pixel at a brightness corresponding to that analog voltage. A computer 2 possesses functions for delivering fivebit digital signals (D4, D3, D2, D1, D0) as video signal corresponding to one of such pixels from output terminals d4, d3, d2, d1, d0, and delivering a vertical synchronizing signal Vsync synchronized with the display period of one screen portion of the display panel described above. A one-subtraction circuit 3 receives three upper bits (D4, D3, D2) of the video signal delivered from the computer 2, subtracts one from the digital value α expressed by the upper three bits, and delivers the calculated digital value β = α - 1 as three-bit digital signal (D4′, D3', D2′) to input terminals B2, B1, B0 of a data selector circuit 5 of the next stage, and this circuit is composed of read-only memory, logic circuitry and so on. The data selector circuit 5 possesses input terminals A2, A1, A0 for directly receiving the upper three bits (D4, D3, D2) of the video signal delivered from the computer 2. A counter 4 counts the vertical synchronizing signals Vsync delivered from the computer 2, and delivers a synchronizing signal V0 of twice the period of the vertical synchronizing signal Vsync, and a synchronizing signal V1 of four times the period to apply these synchronizing signals V0, V1 to a selection signal generating circuit 6 of the next stage, and it is practically realized, for example, by a commercial circuit such as 74LS163. The selection signal generating circuit 6 generates a selection signal Select on the basis of the digital signals of lower two bits (D1, DO) of the video signal given from the computer 2, and the synchronizing signals V0, V1 given from the counter 4, and delivers the selection signal to a data selector circuit 5. The data selector circuit 5 selects and takes in either the three-bit digital signal (D4, D3, D2) given from the computer 2, or the three-bit digital signal (D4', D3', D2') given from the one-subtraction circuit 3, depending on the selection signal Select given from the selection signal generating circuit 6, and delivers from the output terminals Y2, Y1, Y0 as display data to give to the liquid crystal device 1. The operation of 29-gradation display of the liquid crystal device 1 by the thus composed driving circuit is explained below. The upper three-bit digital signal (D4, D3, D2) of video signal delivered from the computer 2 is directly fed to the input terminals A2, A1, A0 of the data selector circuit 5, and is simultaneously subtracted by one from the digital value α as shown in Table 1 by the one-subtraction circuit 3 to be converted into three-bit digital signal (D4', D3′, D2') expressing the subtracted digital value β= α - 1 to be applied to input terminals B2, B1, B0 of the data selector circuit 5. On the other hand, the vertical synchronizing signal Vsync delivered from the computer 2 is counted by the counter 4, and according to the counting, the synchronizing signal V0 of twice the period of the vertical synchronizing signal Vsync, and the synchronizing signal V1 of four times the period of the vertical synchronizing signal Vsync are delivered from the counter 4, and these synchronizing signals V0, V1 are fed into the selection signal generating circuit 6. Fig. 2 is a timing chart showing the corresponding relation of the vertical synchronizing signal Vsync and synchronizing signals V0, V1. In the selection signal generating circuit 6, according to the synchronizing signals V0, V1 being fed, the period of the vertical synchronizing signal Vsync, that is, the display frame in the display period for one screen of the display panel is discriminated as shown in Table 2. V1 V0 Frame No. 0 0 0 0 1 1 1 0 2 1 1 3 More specifically, in the selection signal generating circuit 6, as shown in Fig. 2, the display frame in the period when both synchronizing signals V0 and V1 are "0" is number 0, the display frame in the period when the synchronizing signal V0 is "1" and the synchronizing signal V1 is "0" is number 1, the display frame in the period when the synchronizing signal V0 is "0" and the synchronizing signal V1 is "1" is number 2, and the display frame in the period when both synchronizing signals V0 and V1 are "1" is number 3, thereby discriminating the display frames. This discrimination is repeated in each cycle of four display frame periods. In the selection signal generating circuit 6, depending on the digital values of four types expressed by two-bit digital signal (D1, D0) given from the computer 2, either "1" or "0" is selected as the selection signal Select to be delivered in the period of each frame as shown in Table 3. Frame No. 0 1 2 3 0 0 1 0 0 0 0 1 1 0 1 0 D1 D0 1 0 1 1 0 1 1 1 1 1 1 1 That is, when the two-bit digital signal (D1, D0) is (0, 0), the selection signal Select delivered from the selection signal generating circuit 6 in the period of each display frame of number 0, 1, 2, 3 is respectively 1, 0, 0, 0, the selection signal Select delivered when the digital signal (D1, D0) is (0, 1) is respectively 1, 0, 1, 0, the selection signal Select delivered when the digital signal (D1, D0) is (1, 0) is respectively 1, 1, 0, 1, and the selection signal Select delivered when the digital signal (D1, D0) is (1, 1) is respectively 1, 1, 1, 1. In the data selector circuit 5, on the other hand, in the period of the display frame when the selection signal Select given from the selection signal generating circuit 6 is "1", the digital signal (D4, D3, D2) from the computer 2 expressing the digital value α is taken in, and it is given as the display data to the liquid crystal display device 1, and in the period of the display frame when the selection signal Select is "0", the digital signal (D4′, D3′, D2′) from the one-subtraction circuit 3 expressing the digital value β is taken in, and it is given as display data to the liquid crystal display device 1. That is, the liquid crystal display device 1 receives the display data of the digital value as shown in Table 4 in each display frame, depending on the digital value of the lower two-bit digital signal (D1, D0) delivered from the computer 2. Frame No. 0 1 2 3 Mean 0 0 α β β β α - 0.75 0 1 α β α β α - 0.5 D1 D0 1 0 α α β α α - 0.25 1 1 α α α α α For example, when the digital signal (D1, D0) is (1, 1) expressing the digital value 3 of the highest position, in one cycle of four display frame periods from frame number 0 to frame number 3, the digital value α is given in each display frame to the liquid crystal display device 1 as display data, and the mean of the display data in this one cycle is α . In other words, in the pixels of the display panel corresponding to this display data, the brightness corresponding to the digital value α is obtained in average in this one cycle. Or when the digital signal (D1, DO) is (1, 0) expressing the digital value 2, in the display frame of frame number 2 in the same one cycle, the digital value β is the display data, while the digital value α is the display data in all other three display frame periods, and the mean of the display data in this one cycle is (3α + β) / 4 = (3α + α - 1) / 4 = α - 0.25 To be more specific, in the pixels, the brightness corresponding to the digital value (α - 0.25 ) in average is obtained in this one cycle. This brightness shows the brightness one degree lower than the brightness of the digital value α when the interval from the brightness corresponding to the digital value α to the brightness corresponding to the digital value β one less than the digital value α is divided in four degrees. Similarly, when the digital signal (D1, D0) is (0, I) expressing the digital value 1, the same one cycle comprises two periods of the display frame having digital value α as display data, and two periods of the display frame having digital value β as display data, and therefore the mean of the display data in this one cycle is (2α + 2β ) / 4 = (2α + 2α - 2) / 4 = α - 0.5 That is, the brightness of pixels at this time is one degree lower than when the mean of the digital value is α - 0.25. Furthermore, when the digital signal (D1, DO) is (0, 0) expressing the digital value 0, in this one cycle, the display frame having the digital value α as the display data is in one period, while the digital value β is used as the display data in the other three display frame periods, so that the mean of the display data in this one cycle is (α + 3β) / 4 = (α + 3α - 3) / 4 = α - 0.75 That is, the brightness of pixels at this time is one degree lower than when the mean of the digital value is α - 0.5. Thus, the brightness of each degree of dividing into four degrees between the brightness corresponding to the digital value α and the brightness corresponding to the digital value β one smaller is displayed in a cycle of four display frame periods. The upper three-bit digital signal (D4, D3, D2) delivered from the computer 2 expresses eight kinds of digital values from 0 to 7 as shown in Table 1, and therefore the brightness that can be displayed in each display frame with pixels on the display panel correspondingly is available in (8-1) = 7 degrees, but as described above, on the basis of the lower two-bit digital signal (D1, D0) delivered also from the computer 2, by selecting the display data of each display frame in a cycle of four display frame periods at either the digital value a or the digital value β one smaller than this, each brightness of the seven degrees is further divided in four degrees and displayed, and supposing the state of complete absence of light emission to be a brightness of one degree, the number of gradations that can be displayed in this embodiment is {(8 - 1) x 4} + 1 = 29 Fig. 3 is a block diagram for explaining another embodiment of the invention. A main feature of this embodiment is that the gradation display is effected at the digital value β = α + 1. That is, in Fig. 3, instead of one-subtraction circuit 3 in Fig. 1, a one-addition circuit 7 is used. Therefore, the upper three-bit digital signal (D4, D3, D2) of the video signal delivered from the computer 2, and the digital output (D4′, D3′ D2′) delivered from the one-addition circuit 7 are as shown in Table 5. In the data selector circuit 5, on the other hand, same as in the foregoing embodiment, in the period of the display frame when the selection signal Select given from the selection signal generating circuit 6 is "1", the digital signal (D4, D3, D2) from the computer 2 expressing the digital value α is taken in, and it is given to the liquid crystal display device 1 as dislay data, and in the display frame period when the selection signal Select is "0", the digital signal (D4′, D3′, D2′) from the one-addition circuit 7 expressing digital value β is taken in, and it is given to the liquid crystal display device 1 as display data (see Table 3 and Table 5). That is, in the liquid crystal display device 1, depending on the digital value of the lower two-bit digital signal (D1, D0) delivered from the computer 2, the display data of the digital value as shown in Table 6 is fed in each display frame. Frame No. 0 1 2 3 Mean 0 0 α β β β α + 0. 0 1 α β α β α + 0.5 D1 D0 1 0 α α β α α + 0.25 1 1 α α α α α In the pixels of this embodiment, corresponding to the above embodiment, when the digital signal (D1, D0) expresses the digital value 2 of (1, 0), the brightness corresponding to the digital value (α + 0.25) is obtained in average in one cycle. This brightness expresses the brightness one degree higher than the brightness of the digital value α , when the interval between the brightness corresponding to the digital value α and the brightness corresponding to the digital value β one more than the digital value α is divided into four degrees. It is the same in other digital values. Besides, corresponding to the upper three-bit digital signal (D4, D3, D2) delivered from the computer 2, on the display panel, the brightness can be displayed in seven degrees, and this brightness may be further divided into four degrees on the basis of the lower two-bit digital signal (D1, D0), and supposing the state of complete light emission to be a brightness of one degree, this embodiment also realizes 29-gradation brightness display. In the foregoing embodiments, the value added or subtracted by only one is explained, but the invention may be also realized in the gradation display system by combining three values, that is, one-added value α + 1, one-subtracted value α - 1, and the original value α, or in the case of using the value added or subtracted by two, three, four or the like (a positive integer) as the β value. The invention may be embodied in other specific forms without departing from the scope thereof as defined by the claims.

Claims: A method of driving a display device having a matrix array of pixels, using a multi-bit digital signal which determines the brightness of each pixel, the method comprising dividing said digital signal into a display portion of a first digital value (α:D4D3D2) and a control portion (D1D0), generating at least one second digital value (β) by performing an arithmetic operation on said first digital value, and outputting to the display device a digital data signal having a cycle comprising a plurality of frames in each of which frames said first digital value or the or a said second digital value is selectively output in dependence upon the digital value of said control portion, characterised in that said control portion (D1D0) comprises more than one bit of said multi-bit digital signal. A method according to claim 1, wherein said arithmetic operation generates said second digital value (β) by adding or subtracting a positive integer (M) to or from said first digital value (α). A method according to claim 2, wherein said arithmetic operation generates said second digital value (β) by subtracting one from said first digital value (α). A method according to claim 2, wherein said arithmetic operation generates said second digital value (β) by adding one to said first digital value (α). A method according to any of claims 1 to 4, wherein said control portion comprises two bits of said multi-bit digital signal. A method according to any of claims 1 to 5, wherein said cycle of the digital data signal comprises four frames. A method according to any of claims 1 to 6, wherein said display portion comprises a set (D4D3D2) of higher order bits of said multi-bit digital signal and said control portion comprises a set (D1D0) of lower order bits of said multi-bit digital signal. Apparatus for driving a display device having a matrix array of pixels, using a multi-bit digital signal which determines the brightness of each pixel, the apparatus comprising first means (2) for generating said digital signal in a form having a display portion of a first digital value (α:D4D3D2) and a control portion (D1D0) comprising more than one bit, second means (3) for generating at least one second digital value (β) by performing an arithmetic operation on said first digital value, third means (4,6) for generating a selection signal, having a cycle comprising a plurality of frames, according to the digital value of said control portion, and fourth means (5) for selecting in each of said plurality of frames, in dependence upon said selection signal, either said first digital value or the or a said second digital value, and for outputting a signal of that selected value to the display device. Apparatus according to claim 8, wherein said third means (4,6) generates the frames of said selection signal from a vertical synchronizing signal output by said first means (2), the vertical synchronizing signal defining one display frame. Apparatus according to claim 8 or claim 9, wherein said second means (3) generates said second digital value (β) by adding or subtracting a positive integer (M) to or from said first digital value (α). Apparatus according to claim 10, wherein said second means (3) generates said second digital value (β) by subtracting one from said first digital value (α). Apparatus according to claim 10, wherein said second means (3) generates said second digital value (β) by adding one to said first digital value (α). Apparatus according to any of claims 8 to 12, wherein said control portion comprises two bits of said multi-bit digital signal. Apparatus according to any of claims 8 to 13, wherein said cycle of the selection signal comprises four said frames. Apparatus according to any of claims 8 to 14, wherein said display portion comprises a set (D4D3D2) of higher order bits of said multi-bit digital signal and said control portion comprises a set (D1D0) of lower order bits of said multi-bit digital signal.

Inventors: NAKANISHI KAORU, TANAKA HIROSHI, NAKANISHI, KAORU, TANAKA, HIROSHI
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1991
Main classification: H04N3
IPC codes: G09G3, G09G5, H04N3, G02F1