Single request arbitration scheme for common bus

Abstract: The invention discloses a single request arbitration code for determining if only one communication module (14) is contending for a common data bus (12) and gives that module (14) access within two bus clock cycles. An aggregate code is generated by using the true and complement of the module identification. A check code for each bit is determined by adding the aggregate code for the bit and its adjacent bit. If the check code contains any zeros, then more than one module (14) is contending for the bus (12). The 10-bit single arbitration scheme allows for error detection and correction on a 32-bit common data bus (12).

Description: Background of the Invention 1. Technical Field The invention disclosed broadly relates to bus communication systems and more particularly relates to the arbitration of control of the bus by contending devices desiring access to a common bus for the transfer of data. 2. Background Art In high speed communication systems having a common bus interconnected to multiple communicating modules, latency due to arbitration of contending modules and message transfer is a serious problem. When a plurality of communicating modules vie for a common data bus simultaneously, an arbitration code is necessary to prioritize the requesting modules to select the module to receive access to the bus. A bus acquisition system is disclosed in US-A-4736366 (Rickard) and a bus transceiver is disclosed in US-A-4756006 (Rickard), both patents owned by the common assignee of this invention. The teachings of these two patents are herein incorporated by reference. A typical communication system may have up to 32 communicating modules which compete for a common bus. One hundred twenty- eight logical priority levels can be ascribed to the 32 modules. The arbitration sequence, which takes place upon the data bus, requires eight bus cycles to resolve the winner's logical and physical ID. In the EP 0 220 536 A2 and the US-A- 4 402 040 methods are disclosed, wherein each requesting module places an arbitration code unto the bus, consisting of an element code and its complement. In particular according to the first of these documents, the arbitration code is modified by the bus, that contains a wired logic, so that the arbiter is able to check from the code presented on the bus, how many modules are requesting. The method still needs always 8 cycles for 2 8 modules to assign the correct priority. The problem of the invention is to reduce the arbitration cycle latency. The problem is solved by a method and a system according to the independent claims. Improvements of the invention are characterized in dependent claims. There are times when only one module is in contention for the bus. Even though in the state of the art it is common for only one module to be vying for the bus at any given time, that the module must suffer a full multiple, in the example above, equal to eight cycles, cycle arbitration sequence. According to the invention low latency arbitration is obtained in adding two cycles at the beginning of the arbitration sequence to determine if one or more modules are contending for control of the bus. If only one module is contending for the bus, it is not necessary to continue to the eight cycle arbitration sequence, but give that module immediate access to the bus. The invention and improvements advantageously meet the following objects: It is an object of the invention to provide an improved bus arbitration system which reduces the arbitration cycle latency. It is another object of the invention to provide a bus arbitration scheme having error detection. It is still another object of the invention to provide an improved bus arbitration code which can be duplicated or triplicated on a 32-bit data bus to allow error detection or correction, respectively. Summary of the Invention The present invention is a method for determining arbitration within a common bus communication system, wherein the module ID is written in true and complement form. All modules determine the number of contending modules by calculating a check code after receiving an aggregate (wire-OR) idle bus code from the bus. If the number of contenders is equal to one, then the winner of the vie has been determined and the arbitration is complete. If the number of contenders is greater than one, then the vie sequence continues to determine the eventual winner. Brief Description of the Drawings The present invention, together with other and further advantages and features thereof, will be readily understood from the following detailed description when taken with the accompanying drawings. Fig. 1 is a schematic representation of a common bus having 32 modules connected thereto. Fig. 2 is a timing diagram of the bus clock having a single competitor arbitration code resolution. Fig. 3 is a timing diagram for the bus having multiple module contenders. Fig. 4 is a block diagram showing an implementation of the idle bus arbitration having error correction. Detailed Description of the Invention Shown in Fig. 1, a communications unit 10 employs a common data bus 12 and has a plurality of communication modules 14. Each communication module 14 has a physical ID from zero to 31 and contains a bus interface unit (BIU) 16, a central processing unit (CPU) 18 and a memory unit 20. The BIU 16 does the interfacing between the bus 12 and the communication module 14. The central processor 18 controls the communication module, directing the storage of data in memory unit 20 and sending it out on the common bus through the BIU 16. When more than one module requests the bus 12, an arbitration code is employed to decide which contender vying for the bus 12 receives control of the bus 12. A standard method for achieving this would be to force each contending module 14 to output a code of zero through 31 corresponding to its unique 5-bit physical ID. Five bits are needed to represent a number from zero to 31. The codes for each module are wire-OR'ed on the bus (low active) resulting in an aggregate arbitration code. Then the 32-bit aggregate code could be checked for the number of bits that are active. If only one bit is active, bus tenure can be transferred to the corresponding module 14. If greater than one bit is active, then normal arbitration techniques would be employed. However, checking this code for the number of active bits requires a large amount of logic. The logic is usually open-collector bipolar having large drive and sink current requirements. A large number of comparators are needed. Since the entire 32-bit data bus is required to source the code, error detection is difficult, if not impossible. A better code for each contender would be as follows: for each logic 0 in the physical ID, output '01' on the bus, and for each logic 1 in the physical ID, output '10' on the bus. This forms a true and complement of the physical module ID. Non-contenders would activate no lines on the bus. The result for a five-bit physical ID is a 10-bit single competitor arbitration code. The arbitration code is as follows: The aggregate arbitration code is created by the wire-OR of the bus. For example, two modules 14 are contending, module 0 has a module ID of MID=00000 and module 1 has MID=00001. The resulting aggregate code is 0101010100 as shown in Table 2. A check code can be derived from the aggregate arbitration code satisfying the following equations: o Check Code (4) = Aggregate Code (9) + Aggregate Code (8) (+ = logical OR) o Check Code (3) = Aggregate Code (7) + Aggregate Code (6) o Check Code (2) = Aggregate Code (5) + Aggregate Code (4) o Check Code (1) = Aggregate Code (3) + Aggregate Code (2) o Check Code (0) = Aggregate Code (1) + Aggregate Code (0) If the check code contains any zeros, then more than one module 14 is contending for the bus. Normal arbitration sequences will be required to determine the bus control. If the check code contains all ones, then the bus control can be transferred to the single competing module 14. Table 3 shows the result of a two request arbitration. Table 4 shows the result of a single request arbitration. Note that the check code is equal to all ones in Table 4. This technique allows assignment of tenure in two cycles instead of eight cycles. The logic to check this code compared with the 1-of-32 code approach is significantly simpler and requires much less chip area and wiring bays. Shown in Fig. 2 is a clock step sequence for the two-cycle arbitration code. In step A, all contending modules assert their idle bus code of true and complement of their physical location ID. In step B, all modules determine the number of contending modules by calculating the check code after receiving the aggregate wire-OR idle bus code from the bus. If the number of contenders is equal to one, then the winner of the vie has been determined and the vie is complete. Therefore, the bus state in step C is HO which stands for heading zero of the first message. The winner begins to transfer its message. In Fig. 3 there is shown an arbitration vie resulting in more than one contender. In step C, a bus state is V1 (vie 1). The vie sequence continues to determine the eventual winner. Six more cycles are required. Another feature of the invention is that since the code is compact, it can be duplicated or triplicated on a 32-bit data bus to allow error detection or correction, respectively. That is, only 10 bits are required for the single request arbitration code. In a 32-bit data bus, the arbitration code can be replicated three times. This is not possible with the 1-of-32 code approach since all available data bus lines are used to source the code. An additional error detection can be achieved by the generation of an error code. The error code equations are: o Error Code (4) = Aggregate Code (9) & Aggregate Code (8) (& = logical AND) o Error Code (3) = Aggregate Code (7) & Aggregate Code (6) o Error Code (2) = Aggregate Code (5) & Aggregate Code (4) o Error Code (1) = Aggregate Code (3) & Aggregate Code (2) o Error Code (0) = Aggregate Code (1) & Aggregate Code (0) If the error code contains any ones, then it can be assumed that an error has occurred. This is true since each pair of aggregate code bits should never contain the '11' combination. The example shown in Table 5 shows the error code. Error code correction can be done by a voting of two out of three of the triplicated idle bus arbitration logical implementation. Shown in Fig. 4 are the 10-bit arbitration codes put in 10 bits 0-9. In Fig. 4, the three bits for bit 9 are first AND'ed together, then OR'ed together to form the triple modular redundant unit 22, which are AND'ed together to form the bit error correction code. These significant bits are OR'ed together to produce the error code which must equal zero if no error has occurred. The single request arbitration code has applications to many different bus protocols. It can be implemented to provide extensions and enhancements to the current common bus protocols.

Claims: Method of requesting arbitration between contending communication modules (14) connected to a common data bus (12) via a wired -OR logic, each of said modules (14) being identified by a module identification number, said method containing for each module (14) requesting the bus (12) the steps of generating an aggregate code by forming a digital data word comprising the bits of the module identification number and its complements; and asserting the aggregate code to the bus (12); wherein the method also contains the steps of checking the data word on the bus (12), modified by the wired -OR logic of the bus (12), whether it is an aggregate code, by comparing the corresponding bits of the identification number with the complement of the bits of the complemented identification number; and generating a check code signaling that there is only 1 module (14) accessing the bus (12), when the data word agrees with the structure of said aggregate code according to said comparison, characterized by giving the requesting module (14) access to the bus (12), if the check code signals that the number of contending modules (14) is one, otherwise performing a sequence to prioritize the contending modules (14). Method according to claim 1, characterized in, that the step of generating said aggregate code is performed during a first single cycle, and the step of comparing and generation of the check code is performed during a second single cycle. Method according to claim 1 or 2, characterized in, that the wired -OR logic of the modules in connection to the bus (12) is of the type open collector, and that an error signal is generated, when both, anyone of the bits and its corresponding complement bit on the bus (12), exhibit a logic level corresponding to open collector. Method according to anyone of claims 1 to 3, characterized in, that the aggregate code is generated in duplicate or triplicate to provide error detection. A communication system having a common data bus (12) and contending modules (14) requesting said bus (12) and being connected with the bus (12) via wired -OR logic, the communication system also comprising means for arbitration among contending communication modules (14) and means for generating an aggregate code by forming a digital data word comprising the bits of the module identification number and its complements; means for asserting the aggregate code to the bus (12); means for checking the data word on the bus (12), modified by the wired -OR logic of the bus (12), whether it is an aggregate code, by comparing the corresponding bits of the identification number with the complement of the bits of the complemented identification number; and means for generating a check code signaling that there is only 1 module (14) accessing the bus (12), when the data word agrees with the structure of said aggregate code according to said comparison. characterized by means for giving the requesting module (14) access to the bus (12), if the check code signals that the number of contending modules (14) is one, otherwise performing a sequence to prioritize the contending modules (14). System according to claim 5, characterized in, that said aggregate code is generated during a first single cycle of said system, and the check code is generated during a second single cycle of the system. System according to claim 5 or 6, characterized in, that the wired -OR logic of the modules (14) for connecting them to the bus (12) is of the type open collector, and that an error signal is generated, when both, anyone of the bits and its corresponding complement bit on the bus (12), exhibit a logic level corresponding to said open collector. System according to anyone of claims 5 to 7, characterized by means for generating the aggregate code in duplicate or triplicate to provide error detection.

Inventors: KALAJAINEN DENNIS M, KALAJAINEN, DENNIS M.
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1991
Main classification: G06F13
IPC codes: G06F11, G06F13