Programmable delay circuit

Abstract: A programmable delay circuit (6) of the present invention is comprised of an input terminal (5a,5b) to which an input signal to be delayed is supplied, N (N ≧ 2) delay circuits (G₁...G n ) of a plurality of stages connected in cascade, a plurality of differential amplifier (D₁...D n-1 ) connected to respective stages between the delay circuits of the plurality of stages and having a pair of differential amplifier transistors (Q₁₁,Q₁₂...Q n-11 ,Q n-12) and current switches (Q₁...Q n-1 )for supplying a drive current from a common current source (9) to the pair of differential amplifier transistors, a common output terminal (VOUT, VOUT B ) commonly connected to respective outputs of a pair of differential amplifier transistors of the plurality of differential amplifiers and a control circuit (10) for selectively controlling the current switches of the plurality of differential amplifiers, wherein even when any one of the current switches of the plurality of differential amplifiers is selected, delay amounts of the differential amplifiers become constant so that linearity of delay characteristic can be improved. Since a single common current source is employed, the power consumption is reduced. When a buffer stage (7) connected in cascade is provided between the outputs of the plurality of differential amplifiers and the common output terminal, the output capacitances of the differential amplifier transistors can be reduced and thus the programmable delay circuit of the present invention can be operated at high speed.

Description: FIELD OF THE INVENTION The present invention relates to a programmable delay circuit according to the precharacterizing part of claim 1. Such a programmable delay circuit is known from US-A-4,675,562, or from EP-A-0 317 758. "A Digitally Programmable Delay Chip with picosecond Resolution" described in IEEE Proceedings of the 1989 Bipolar Circuit and Technology Meetings, September 18-19, 1989, pp. 295 to 297 forms a further conventional programmable delay circuit. A block diagram forming Fig. 1 shows an example of such a conventional programmable delay circuit. As shown in Fig. 1, a main or coarse delay circuit 1 is composed of 32 delay gates G 0 to G 31 connected in cascade, a multiplexer 1a and a latch circuit 1b. The latch circuit 1b latches a digital signal of 5 bits (D 0 to D 4 ) input thereto from a control circuit (not shown) and the multiplexer 1a is controlled in response to the digital output of the latch circuit 1b, thereby pulse signals applied to input terminals IN and INB being delayed by an arbitrary delay time of 110 picoseconds per gate. a cascade circuit 2 is connected to an output of the multiplexer 1a to expand the delay time and composed of a multiplexer 2a and a latch circuit 2b which latches a digital signal D 5 . An output of the cascade circuit 2 is supplied through a buffer stage 3 to output terminals A1 and Q1B,respectively, and a sub or fine tune circuitry 4 is connected to the output of the cascade circuit 2. Fig. 2 is a schematic block diagram showing an example of a conventional multiplexer, and as shown in Fig. 2, the multiplexer 1a of Fig. 1 is generally comprised of 8 stages of delay gates G 1 to G 8 and seven multiplexers A through G which are supplied with control signals S 0 to S 6 delivered from the latch circuit 1b. However, in the conventional delay circuit of Fig. 2, the multiplexer 1a is composed of seven multiplexers A through G connected in a so-called tournament fashion, which needs 2 n -1 multiplexer stages if there are provided 2 n -1 delay circuits. Further, since the signal is passed through n multiplexers from each of the delay gates to the output terminal Q 1 , the fixed delay time is increased. In that case, if n is increased, the delay error caused by the multiplexer 1a from each of the delay gates to the output terminal Q 1 is increased, thus deteriorating linearity of delay characteristic more. Furthermore, since the pulse signals supplied to the input terminals IN and INB are passed through the n multiplexers (e.g., the multiplexers A, E and G), the power consumption is increased. U. Tietze & Ch. Schenk, "Halbleiter-Schaltungstechnik", 1983, Springer Verlag, Berlin, Heidelberg, New York, Tokyo; pages 728-731 discloses a broad band multiplexer including differential amplifier stages and current switches for selectively providing a drive current from a common current source to a selected pair to the transistors of a differential amplifier according to a logic selection signal. The programmable delay circuit disclosed in US-A-4,675,562 is composed of fine and coarse delay sections, each section comprising a plurality of delay stages, which are either serial-connected differential delay lines or cascaded gates. As is shown in Fig.3 of US-A-4 675 562, the first two delay sections include differential multiplexers, each multiplexer stage including a differential transistor amplifier, wherein each stage of the multiplexer is respectively coupled with an input or output of a corresponding delay line stage. The stages of the multiplexer are selected by a selection circuit comprising transistors, each of said transistors being respectively coupled to connected emitter terminals of the differental amplifiers of each multiplexer stage, said transistors selectively supplying current from a single current source to select each stage of the multiplexer. An ordinary emitter follower output amplifier supplies the output signals of the known delay circuit. Further the output signals of the programmable coarse delay circuit shown in Fig 5 of US-A-4,675,562 are derived from the output of a logical AND gate. SUMMARY OF THE INVENTION It is an object of the present invention to provide a programmable delay circuit in which linearity of delay characteristic can be improved, in which power consumption can be reduced, which can be operated at high speed and which can produce satisfactory delay characteristic. According to an essential aspect of the present invention, a programmable delay circuit solving the above object comprises: a) differential input terminals to which an input signal to be delayed is supplied; b) n delay circuits of a plurality of stages connected in cascade, where n ≥ 2; c) a differential multiplexer consisting of a plurality of first differential amplifiers respectively connected to said plurality of stages of delay circuits, each first differential amplifier having a pair of transistors, d) differential output terminals to which respective output terminals of said pair of transistors of said plurality of first differential amplifiers of said multiplexer are commonly connected; wherein e) each first differential amplifier of said multiplexer is further connected to a respective one of a plurality of current switches for selectively supplying a drive current from a common current source to a respective one of said first differential amplifiers of said multiplexer when the respective one of said current switches is selected by a control circuit for selectively ON-OFF controlling said current switches, and a buffer stage is connected in cascade between said differential output terminals and output terminals of said programmable delay circuit, characterized in that each of said delay circuits of said plurality of stages is formed of an emitter follower circuit and a second differential amplifier, said second differential amplifier being connected to emitter terminals of said emitter follower circuit, each of said plurality of first differential amplifiers of said multiplexer is respectively connected to respective said emitter terminals;and said buffer stage is configured so as to reduce the apparent output capacitances of the transistors of said first differential amplifiers. According to the programmable delay circuit of the present invention, even when any one of the current switches of the plurality of differential amplifiers is selected, delay amounts of the differential amplifiers become constant so that linearity of delay characteristic can be improved. Also, since the single common current source is employed, the power consumption can be reduced. Further, when the buffer stages connected in cascade are provided between the outputs of said plurality of differential amplifiers and said common output terminal, the output capacitances of the differential amplifier transistors can be apparently reduced and thus the programmable delay circuit of the present invention can be operated at high speed. The above, and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof to be taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing an example of a conventional programmable delay circuit; Fig. 2 is a block diagram showing an example of a multiplexer used in the conventional programmable delay circuit of Fig. 1; Fig. 3 is a block circuit diagram showing a fundamental arrangement of a programmable delay circuit; and Fig. 4 (formed of Fig. 4A and 4B) is a circuit diagram showing an embodiment of the programmable delay circuit according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described with reference to the drawings. Fig. 3 shows in block circuit form a fundamental arrangement of the programmable delay circuit which is in said block circuit form not subject matter of the claimed invention. Referring to Fig. 3, input signals (pulse signals such as clock signals or the like) to be delayed are supplied to input terminals 5a and 5b of a delay circuit 6 and, by way of example, these input signals are opposite in phase. The delay circuit 6 has N stages (N ≧ 2) and composed of a plurality of delay circuits (G 1 through G n ) which are connected in cascade. Input electrodes (bases) of a pair of differential amplifier transistors Q 11 and Q 12 are connected between the first and second delay circuits G 1 and G 2 of the delay circuit 6. Output electrodes (collectors) of the transistors Q 11 and Q 12 are connected through transistors Q b1 and Q b2 which constitute a buffer stage 7 and connected in cascade to common output terminals VOUT and VOUTB, respectively. Incidentally, load resistors R 1 and R 2 are connected between a reference voltage source V ref (by way of example, ground potential) and the common output terminals VOUT and VOUTB, respectively. A current switch 8 is composed of transistors Q 1 to Q n-1 , and a common current source 9 has a current value of, for example, I ref . The differential amplifier transistors Q 11 and Q 12 and the transistor Q 1 of the current switch 8 constitute a first differential amplifier D 1 ; differential amplifier transistors Q 21 and Q 22 connected between the second and third delay circuits G 2 and G 3 and a transistor Q 2 of the current switch 8 constitute a second differential amplifier D 2 ; and differential amplifier transistors Q n-11 and Q n-12 connected between the third delay circuit G 3 and an N'th delay circuit G n and a transistor Q n-1 of the current switch 8 constitute a (N-1)'th differential amplifier D n-1 . In Fig. 3, reference numeral 10 designates a control circuit which selectively controls the current switch 8. For example, the control circuit 10 controls the transistors Q 1 to Q n-1 of the current switch 8 in response to, for example, digital signals d 1 to d k of K bits. Operation of the thus constructed programmable delay circuit will be described below. Referring to Fig. 3, when, for example, the transistor Q 1 of the current switch 8 is selected by the digital signals d 1 to d k of the control circuit 10, the transistor Q 1 is turned on to permit the current I ref of the common current source 9 to be supplied to the differential amplifier transistors Q 11 and Q 12 of the first differential amplifier D 1 so that the input signals applied to the input terminals 5a and 5b are supplied to the first delay circuit G 1 . An output of the first delay circuit G 1 is amplified by the first differential amplifier D 1 and supplied through the buffer stage 7 to the common output terminals VOUT and VOUTB. Similarly, when the transistor Q 2 of the current switch 8 is selected, the transistor Q 2 is turned on to permit the current I ref of the common current source 9 to be supplied to the differential amplifier transistors Q 21 and Q 22 of the second differential amplifier D 2 so that the input signals applied to the input terminals 5a and 5b are supplied to the second delay circuit G 2 . An output of the second delay circuit G 2 is amplified by the second differential amplifier D 2 and supplied through the buffer stage 7 to the common output terminals VOUT and VOUTB. That is, the current switch 8 of the plurality of differential amplifiers D 1 to D n-1 is controlled by the control signals C 1 to C n-1 of the control circuit 10, whereby the outputs of the 2 n-1 (N-1)'th delay circuits G 1 to G n-1 can be selectively output. Even when any of the transistors Q 1 to Q n-1 of the current switch 8 of the plurality of differential amplifiers D 1 to D n-1 is selected, the delay times of the differential amplifiers D 1 to D n-1 are constant and the fixed delay times are reduced so that linearity of delay characteristic can be improved. Also, since the single common current source 9 is used, the power consumption can be reduced. Further, when the cascade-connected buffer stage 7 is connected between the outputs of the plurality of differential amplifiers D 1 to D n-1 and the common output terminals VOUT and VOUTB, the output capacitances of the differential amplifier transistors Q 11 to Q n-12 are apparently reduced, thereby the programmable delay circuit of the invention being operated at high speed. Incidentally, the delay time can be further increased by providing other differential amplifiers (not shown) in the output of the N'th delay circuit G n . Alternatively, though not shown, it is possible to provide a differential amplifier which supplies the input signals applied to the input terminals 5a and 5b directly to the common output terminals VOUT and VOUTB (the first delay circuit G 1 is bypassed). A specific circuit arrangement of the embodiment of the programmable delay circuit according to the present invention will be described with reference to Fig. 4. Fig. 4 is formed of Fig. 4A and 4B drawn on two sheets of drawings so as to permit the use of a suitably large scale. Some of the principles explained above with reference to Fig. 3 are valid also for the circuit shown in Fig. 4. In Fig. 4, like parts corresponding to those of Fig. 3 are marked with the same references and therefore need not be described in detail. As shown in Fig. 4, the delay circuit 6 of Fig. 3 is composed of eight stages of first delay circuit G 1 to eighth delay circuit G 8 and each of the first to eighth delay circuits G 1 to G 8 is formed of an emitter-follower circuit and a differential amplifier. The transistors Q 1 to Q 8 constructing the current switch 8 of the first to eighth differential amplifiers D 1 to D 8 are controlled by control signals C 1 to C 8 from a control circuit (not shown). In the embodiment of Fig. 4, if the delay time of each delay circuit is selected to be, for example, 100 psec, the delay time can be varied in a range of from 100 psec to 800 psec (e.g., 10 nsec in the case of 2 n = 128), thus achieving similar effects to those of Fig. 3. Further, in this embodiment, since the input pulse signal is transmitted in a push-pull fashion, there is then the advantage that the duty ratio of the input pulse signal can be maintained constant until it is output. As will be clear from the above explanation, according to the programmable delay circuit of the present invention, even when any one of the current switches of the plurality of differential amplifiers is selected, the delay amounts of the differential amplifiers become constant so that the linearity of the delay characteristic can be improved. Also, since the single common current source is employed, the power consumption can be reduced. When the cascade-connected buffer stage is provided between the outputs of the plurality of differential amplifiers and the common output terminal, the output capacitances of the differential amplifier transistors can be apparently reduced so that the programmable delay circuit of the present invention can be operated at higher speed. Furthermore, according to the programmable delay circuit of the present invention, even when the number of stages of the delay circuit is increased, delay errors of the multiplexer can be prevented from being accumulated unlike the example of the prior art, thus making it possible to obtain satisfactory delay characteristic.

Claims: A programmable delay circuit comprising: a) differential input terminals (5a, 5b) to which an input signal to be delayed is supplied; b) n delay circuits (G 1 -G n ) of a plurality of stages connected in cascade, where n ≥ 2; c) a differential multiplexer consisting of a plurality of first differential amplifiers (D1-D n-1 ) respectively connected to said plurality of stages of delay circuits, each first differential amplifier having a pair of transistors (Q 11 , Q 12 ; Q n-11 , Q n-12 ), d) differential output terminals to which respective output terminals of said pair of transistors of said plurality of first differential amplifiers of said multiplexer are commonly connected; wherein e) each first differential amplifier (D 1 -D n-1 ) of said multiplexer is further connected to a respective one of a plurality of current switches (Q 1 -Q n-1 ) for selectively supplying a drive current from a common current source (9) to a respective one of said first differential amplifiers (D 1 -D n-1 ) of said multiplexer when the respective one of said current switches (Q 1 -Q n-1 ) is selected by a control circuit (10) for selectively ON-OFF controlling said current switches (Q 1 -Q n-1 ), and a buffer stage is connected in cascade between said differential output terminals and output terminals (V out , V outB ) of said programmable delay circuit, characterized in that each of said delay circuits (G1-Gn) of said plurality of stages is formed of an emitter follower circuit and a second differential amplifier, said second differential amplifier being connected to emitter terminals of said emitter follower circuit, each of said plurality of first differential amplifiers (D 1 -D n-1 ) of said multiplexer is respectively connected to respective said emitter terminals;and said buffer stage (7) is configured so as to reduce the apparent output capacitances of the transistors of said first differential amplifiers. The programmable delay circuit according to claim 1, wherein a complementary signal is supplied to said input terminals to which the input signal to be delayed is supplied and a complementary signal delayed by a delay time determined by the selection of one of the current switches is derived from said output terminals.

Inventors: MURAKAMI DAISUKE C O SONY CORP, MURAKAMI, DAISUKE, Murakami, Daisuke, c/o SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1991
Main classification: H03K5
IPC codes: H03K17, H03K5