Logarithmic amplifying circuit

Abstract: The circuit comprises a plurality of stages of cascaded differential amplifiers (11, 12, ..., 1m); a plurality of logarithmic full wave rectifiers (21, 22, ..., 2(m + 1) which produce output currents I RSJ (J = 1 to m + 1) having logarithmic full-wave characteristics; and an adder (3) for adding the output currents and producing a signal corresponding to the sum current. The logarithmic full-wave rectifier (21) comprises n squaring full-wave rectifiers ((21-1), (21-2) ..., (21-n)), and a pair of current mirror circuits (40A) and (40B) constituting an addition means for adding output currents from these squaring full wave rectifiers. Each squaring full-wave comprises a set of two differential pairs (30A₁, 30B₁,; 30A₂, 30B₂).

Description: The present invention relates to a logarithmic amplifying circuit and, more particularly, to a logarithmic amplifying circuit suited for a MOS integrated circuit. A conventional logarithmic amplifying circuit of this type is generally realized in a bipolar integrated circuit. Such a circuit is disclosed in. eg. EP-A-0.248.428. A logarithmic amplifying circuit realized in a MOS integrated circuit is disclosed in eg. Japanese Patent Laid-Open No. 62-292010. The logarithmic amplifying circuit in these integrated circuits are designed in such a manner that multistage differential amplifiers are connected in cascade, and squaring full-wave rectifiers are respectively connected to an input of the first stage and output terminals of the subsequent stages. With this arrangement, signals at these input and output terminals are subjected to squaring full-wave rectification, and the outputs from the squaring full-wave rectifiers are added together. For this reason, these outputs are affected by the characteristics of the respective squaring full-wave rectifiers, which include dynamic range characteristics, and hence excellent logarithmic characteristics cannot be obtained. It is an object of the present invention to provide a logarithmic amplifying circuit which has a wide dynamic range and can obtain excellent logarithmic characteristics. In one aspect the invention provides a logarithmic amplifier comprising: a) a plurality of differential amplifier stages each having first and second input nodes and first and second output nodes, said amplifier stages being connected to each other in cascaded arrangement such that said first and second output nodes of a preceding amplifier stage are connected respectively to said first and second input nodes of a succeeding amplifier stage, an input signal being supplied between said first and second input nodes of a first stage of said cascaded arrangement; b) a plurality of logarithmic full wave rectifier blocks, each rectifier block having first and second input terminals one rectifier block having its input terminals respectively connected to the first and second input nodes of the first amplifier stage, the other rectifier blocks having their input terminals respectively connected to said first and second output nodes of an associated one of said amplifier stages to receive an output signal appearing between said first and second output nodes of the associated amplifier stage, each rectifier block rectifying its respective input signal to produce an output current at first and second output terminals thereof and having logarithmic full-wave rectification with respect to an input voltage; c) an adder to add output currents from said rectifier blocks to each other and output a signal corresponding to the sum current; characterised in that d) each rectifier block includes a first current source, first and second MOS transistors connected in a differential manner, said first MOS transistor having a gate connected to said first input terminal, a drain connected to said first output terminal, a source directly connected to said first current source and a first ratio of a gate width to a gate length, said second MOS transistor having a gate connected to said second input terminal, a drain connected to said second output terminal, a source directly connected to said first current source and a second ratio of a gate width to a gate length, said first ratio being different from said second ratio, a second current source, third and fourth MOS transistors connected in a differential manner, said third MOS transistor having a gate connected to said second input terminal, a drain connected to said first output terminai, a source directly connected to said second current source and a third ratio of a gate width to a gate length, said fourth MOS transistor (M14) having a gate connected to said first input terminal, a drain connected to said second output terminal, a source directly connected to said second current source and a fourth ratio of a gate width to a gate length, said third ratio being different from said fourth ratio, a third current source, fifth and sixth MOS transistors connected in a differential manner, said fifth MOS transistor having a gate connected to said first input terminal, a drain connected to said first output terminal, a source directly connected to said third current source and a fifth ratio of a gate width to a gate length, said sixth MOS transistor having a gate connected to said second input terminal, a drain connected to said second output terminal, a source directly connected to said third current source and a sixth ratio of a gate width to a gate length, said fifth ratio being different from said sixth ratio, a fourth current source, seventh and eighth MOS transistors connected in a differential manner, said seventh MOS transistor having a gate connected to said second input terminal, a drain connected to said first output terminal, a source directly connected to said fourth current source and a seventh ratio of a gate width to a gate length, said eighth MOS transistor having a gate connected to said first input terminal, a drain connected to said second output terminal, a source directly connected to said fourth current source and an eighth ratio of a gate width to a gate length, said seventh ratio being different from said eighth ratio, and an output circuit connected to said first and second output terminals for adding the currents output from said rectifier blocks. Furthermore, said output circuit of said each rectifier block includes a first current mirror circuit having a current input terminal connected to said first output terminal of each rectifier block and thereby supplied commonly with drain currents of said first, third, fifth and seventh MOS transistors and a current output terminal connected to the drains of the second, fourth, sixth and eighth MOS transistors, and a second current mirror circuit having a current input terminal connected to said second output terminal of said each rectifier block and thereby supplied commonly with drain currents of said second, fourth, sixth and eighth MOS transistors and to the current output terminal of said first current circuit, said second current mirror circuit providing via its output terminal a sub total current representing said output signal of said each rectifier block. Reference will now be made, by way of example, to the accompanying drawings, in which:- Fig. 1 is a block diagram showing a logarithmic amplifying circuit according to an embodiment of the present invention; Fig. 2 is a circuit diagram showing a logarithmic full-wave rectifier in the logarithmic amplifying circuit of the present invention; Fig. 3 is a circuit diagram showing a squaring full-wave rectifier, as a basic unit, constituting the logarithmic full-wave rectifier shown in Fig. 2; and Figs. 4 and 5 are graphs showing the characteristics of a squaring full-wave rectifier, in which ratio W 1 (gate width)/L 1 (gate length) is used as a parameter. The present invention will be described below with reference to accompanying drawings. Fig. 1 is a block diagram showing a logarithmic amplifying circuit according to an embodiment of the present invention. The logarithmic amplifying circuit comprises a plurality of (m) stages of cascaded differential amplifiers 11, 12, ..., and 1m, a plurality of logarithmic full-wave rectifiers 21, 22, ..., and 2(m+1) respectively connected to the input and output terminals of the first-stage differential amplifier 11 and the output terminals of the differential amplifiers 12 to 1m of the subsequent stages and designed to respectively output currents I RSJ (J = 1 to m+1) having logarithmic full-wave characteristics with respect to an input voltage V 1 , and an adder 3 for adding the output currents I RSJ from the logarithmic full-wave rectifiers 21, 22, ..., and 2(m+1) and outputting a signal V 0 corresponding to the sum current. Since the logarithmic full-wave rectifiers 21, 22, ..., and 2(m+1) of the logarithmic amplifying circuit are all the same in circuitry arrangement, only the logarithmic full-wave rectifier 21 is shown in Fig. 2. Referring to Fig. 2, the logarithmic full-wave rectifier 21 comprises n squaring full-wave rectifiers (21-1), (21-2), ..., and (21-n), and a pair of current mirror circuits 40A and 40B constituting an addition means for adding output currents from these squaring full-wave rectifiers. Each squaring full-wave rectifier is constituted by a set of two differential pairs. For example, in the squaring full-wave rectifier (21-1), a set of two differential pairs is constituted by differential pairs 30A 1 and 30B 1 . In the squaring full-wave rectifier (21-2), a set of two differential pairs is constituted by differential pairs 30A 2 and 30B 2 . Since the squaring full-wave rectifiers are all the same in circuitry arrangement, only one of them is shown in Fig. 3, and its circuit arrangement and operation will be described below. Referring to Fig. 3, each squaring full-wave rectifier comprises a set of two differential pairs 30A and 30B, and a pair of current mirror circuits 40A and 40B serving as an addition means. The differential pair 30A is constituted by first and second transistors M1 and M2. The gate of the first transistor M1 is connected to a first input terminal T 1 , one of a pair of first and second input terminals T 1 and T 2 for receiving an input voltage V 1 . The source of the transistor M1 is connected to a first current source I 01 . The ratio of the gate width to the gate length of the transistor M1 is set to be a predetermined value. The gate and source of the second transistor M2 are respectively connected to the input terminal T 2 and the first current source I 01 . The ratio of the gate width to the gate length of the second transistor M2 is set to be different from that of the first transistor M1. The other differential pair 30B is constituted by third and fourth transistors M3 and M4. The gate and source of the third transistor M3 are respectively connected to the second input terminal T 2 and a second current source I 02 . The ratio of the gate width to the gate length of the third transistor M3 is set to be a predetermined value. The gate and source of the fourth transistor M4 are respectively connected to the first input terminal T 1 and the second current source I 02 . The ratio (W/L) of the gate width to the gate length of the fourth transistor M4 is set such that the ratios (W/L) of the gate-width/gate-length of the third and fourth transistors M3 and M4 are equal to those of the first and second transistors M1 and M2. The first current mirror circuits 40A comprises transistors M5 and M6. The current input terminals of the current mirror circuit 40A is connected to the drains of the first and third transistors M1 and M3, whereas the current output terminal is connected to the drains of the second and fourth transistors M2 and M4. The second current mirror circuit 40B comprises transistors M7 and M8. The current input terminal of the current mirror circuit 40B is connected to the drains of the second and fourth transistors M2 and M4 and to the current output terminal of the first current mirror circuit 40A. The squaring full-wave rectifier shown in Fig. 3 requires the pair of current mirror circuits 40A and 40B. However, in the squaring full-wave rectifier shown in Fig. 2 which is constituted by a plurality of differential pairs, the pair of current mirror circuits 40A and 40B is commonly used for all the differential pairs (21-1), (21-2), ..., and (21-n) An operation of this embodiment and the characteristics of the respective components will be described below. The squaring full-wave rectifier will be described first. Drain currents I d1 , I d2 , I d3 , and I d4 of the transistors M1, M2, M3, and M4 are obtained as follows. If ratios W/L of gate widths W to gate lengths L of the respective transistors are represented by W 1 /L 1 , W 2 /L 2 , W 3 /L 3 , and W 4 /L 4 , then (W 2 /L 2 )/(W 1 /L 1 ) = (W 4 /L 4 )/(W 3 /L 3 ) = K > 1 In this case if β = µ N C ox 2 · W 1 L 1 where µ N is the mobility of the transistor, and C ox is the gate capacitance of the gate oxide film per unit area, then I d1 = β (V gs1 - V t ) 2 I d2 = Kβ (V gs2 - V t ) 2 I d3 = β (V gs3 - V t ) 2 I d4 = Kβ (V gs4 - V t ) 2 for I d1 + I d2 = I d3 + I d4 = I 0 V I = V gs1 - V gs2 = V gs4 - V gs3 where V t is the threshold voltage of the transistor. The transistors M5, M6, M7, and M8 constitute the first and second current mirror circuits 40A and 40B, and an output current I RS from this squaring full-wave rectifier is given by I RS = (I d2 + I d4 ) - (I d1 + I d3 ) = 2 K-1 K+1 I o -4β K(K-1) (K+1) 2 V I 2 Fig. 4 shows this output current I RS with K and W 1 /L 1 used as parameters. Fig. 5 shows the output current I RS as a function of V I (dB). The current I RSO in equation (9) in the absence of a signal is given by I RSO = I RS (V l = 0) = 2 K-1 K+1 I o The current I RSO monotonously increases with respect to K. According to equation (9), if I RS = 0, an operating maximum input voltage V I0 is given by V l0 = 1 + 1 K · I o 2β Even if the value K changes, the range of change is sufficiently compressed. Therefore, the voltage V I0 is substantially constant, if K has a large value. Similarly, an input voltage V I0.5 for I RS = I RSO /2 is given by V I0.5 = 1 2 1 + 1 K · I o β = 1 2 V I0 Therefore, the input voltage v I0.5 remains substantially constant with respect to a change in K. The inclination of the current I RS is obtained by differentiating equation (9) as follows: dI RS dV I = -8β K(K-1) V I (K + 1) 2 For example, when I RS becomes I RSO /2, the corresponding inclination is represented by dI RS dV I (V I = V I0.5 ) = -4 (K-1) (K+1) K K+1 βI 0 That is, the current I RS monotonously decreases with respect to K. The caracteristics of the logarithmic full-wave rectifier 2J (J= 1 to m+1) will be described below. The operating dynamic range of the Xth (X= 1 to n) squaring full-wave rectifier constituting the logarithmic full-wave rectifier is represented as the following equations by superposing the product by P X on I RSX , provided that the range of charge in output current I RSX is set to be (1 - 2P X ) times the current I RSXO (0 <P X < 0.5): V I1 (1 - P 1 ) = V I2 (P 2 ) v I2 (1 - P 2 ) = V I3 (P 3 ) V I(n-1) {1-P (n-1) } = V In (P n ) In this case, V IX (P X ) and V IX (1 - P X ) respectively represent input voltages at which the current I RSX is P X and (1 - P X ) times I RSXO (= I RSX (V IX = 0)). In this case, an operating dynamic range d of a logarithmic full-wave rectifier 2J is given by d = V I1 (P 1 )/V In (1 - P n ) If this value is expressed logarithmically, D(dB) = V I1 (P 1 ) (dB) - V In (1 - P n ) (dB) According to equations (9) and (10), V IX (1 - P X ) = P X 2 · K X + 1 β X K X I OX V IX (P X ) = 1 - P X 2 · K X + 1 β X K X I OX Hence, Therefore, the dynamic range d is obtained by d = 1-P 1 P n · K n (K+1) K 1 (K n + 1) · I O1 I On · β n β 1 For example, if K 1 = K 2 = .... = K n I 01 = I 02 = ... = I On then, d = 1-P 1 P n β n β 1 = 1-P 1 P n β n β 1 According to equations (15) to (17), P (X-1) β (X-1) = 1-P X β X ∴ β X β (X-1) = 1-P X P (X-1) ∴ β n β 1 = β n β (n-1) · β (n-1) β (n-2) · ··· · β 2 β 1 = 1-P n P (n-1) · 1-P (n-1) P (n-2) · ··· · 1-P 2 P 1 ∴ d = 1-P n P n · 1-P (n-1) P (n-1) · ··· · 1-P 2 P 2 1-P 1 P 1 The magnitude of a logarithmic characteristic error of the logarithmic full-wave rectifier 2J is determined by P X . In order to reduce the error, the value P X needs to be increased. If, for example, P 1 = P 2 = ···= P n = 0.1 then, ∴ d = 3 n If this value is expressed in terms of dB, D(dB) = 9.54 x n(dB) As a result, an operating dynamic range of 9.54 dB is obtained per squaring full-wave rectifier. In addition, if P 1 = P 2 = ··· = P n = 0.2 then, d = 2 n If this value is expressed in terms of dB, d(dB) = 6.02 x n(dB) As a result, an operating dynamic range of 6.02 dB is obtained per squaring full-wave rectifier. If the value P X is increases, the operating dynamic range is reduced. However, since the operating dynamic range is increased n times at the output terminal of the logarithmic full-wave rectifier 2J, an operating dynamic range much wider than that of the conventional circuit can be obtained. Since output currents I RSJ from the logarithmic full-wave rectifiers 2J having such characteristics are added together by the adder 3, and the sum current is converted into an output voltage V 0 , the output voltage V 0 has a dynamic range of d (m+1) . With this operation, excellent logarithmic characteristics with a wide dynamic range and a small error can be obtained. As has been described above, according to the present invention, logarithmic full-wave rectifiers are respectively connected to the input and output terminals of a plurality of stages full-wave of cascaded differential amplifiers. Each logarithmic full-wave rectifier has a plurality of squaring full-wave rectifiers which perform squaring full-wave rectification of corresponding signals at these input and output terminals. The logarithmic full-wave rectifier adds the outputs from the squaring full-wave rectifiers, and output the sum. The outputs from the respective logarithmic full-wave rectifiers are added together. With this operation, excellent logarithmic characteristics with a wide dynamic range and a small error can be obtained.

Claims: A logarithmic amplifier comprising: a) a plurality of differential amplifier stages (11,12) each having first and second input nodes and first and second output nodes, said amplifier stages being connected to each other in cascaded arrangement such that said first and second output nodes of a preceding amplifier stage are connected respectively to said first and second input nodes of a succeeding amplifier stage, an input signal being supplied between said first and second input nodes of a first stage (11) of said cascaded arrangement; b) a plurality of logarithmic full wave rectifier blocks (21,22), each rectifier block having first and second input terminals (T1,T2) one rectifier block having its input terminals respectively connected to the first and second input nodes of the first amplifier stage, the other rectifier blocks having their input terminals respectively connected to said first and second output nodes of an associated one of said amplifier stages (11,12) to receive an output signal appearing between said first and second output nodes of the associated amplifier stage, each rectifier block rectifying its respective input signal to produce an output current at first and second output terminals thereof and having logarithmic full-wave rectification with respect to an input voltage; c) an adder (3) to add output currents from said rectifier blocks (21,22) to each other and output a signal corresponding to the sum current; characterised in that d) each rectifier block (21,22) includes a first current source (111), first and second MOS transistors (M11,M12) connected in a differential manner, said first MOS transistor (M11) having a gate connected to said first input terminal (T1), a drain connected to said first output terminal, a source directly connected to said first current source and a first ratio (W1/L1) of a gate width to a gate length, said second MOS transistor (M12) having a gate connected to said second input terminal (T2), a drain connected to said second output terminal, a source directly connected to said first current source and a second ratio of a gate width to a gate length, said first ratio being different from said second ratio, a second current source (I12), third and fourth MOS transistors (M13,M14) connected in a differential manner, said third MOS transistor (M13) having a gate connected to said second input terminal (T2), a drain connected to said first output terminal, a source directly connected to said second current source and a third ratio of a gate width to a gate length, said fourth MOS transistor (M14) having a gate connected to said first input terminal, a drain connected to said second output terminal, a source directly connected to said second current source and a fourth ratio of a gate width to a gate length, said third ratio being different from said fourth ratio, a third current source (I21), fifth and sixth MOS transistors (M21,M22) connected in a differential manner, said fifth MOS transistor (M21) having a gate connected to said first input terminal, a drain connected to said first output terminal, a source directly connected to said third current source and a fifth ratio of a gate width to a gate length, said sixth MOS transistor (M22) having a gate connected to said second input terminal, a drain connected to said second output terminal, a source directly connected to said third current source and a sixth ratio of a gate width to a gate length, said fifth ratio being different from said sixth ratio, a fourth current source (I22), seventh and eighth MOS transistors (M23,M24) connected in a differential manner, said seventh MOS transistor (M23) having a gate connected to said second input terminal, a drain connected to said first output terminal, a source directly connected to said fourth current source and a seventh ratio of a gate width to a gate length, said eighth MOS transistor (M24) having a gate connected to said first input terminal, a drain connected to said second output terminal, a source directly connected to said fourth current source and an eighth ratio of a gate width to a gate length, said seventh ratio being different from said eighth ratio, and an output circuit (30Bn, 40A, 40B) connected to said first and second output terminals for adding the currents output from said rectifier blocks. An amplifier according to Claim 1, wherein said output circuit of said each rectifier block includes a first current mirror circuit (40A) having a current input terminal connected to said first output terminal of each rectifier block and thereby supplied commonly with drain currents of said first, third, fifth and seventh MOS transistors and a current output terminal connected to the drains of the second, fourth, sixth and eighth MOS transistors, and a second current mirror circuit (40B) having a current input terminal connected to said second output terminal of said each rectifier block and thereby supplied commonly with drain currents of said second, fourth, sixth and eighth MOS transistors and to the current output terminal of said first current circuit, said second current mirror circuit providing via its output terminal a sub total current (IRS1) representing said output signal of said each rectifier block.

Inventors: KIMURA KATSUJI, KIMURA, KATSUJI, KIMURA, KATSUJI, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: H03G7
IPC codes: H03G11, H03G7, G06G7