Data shuffling apparatus

Abstract: A data rearranging device in block unit used in an apparatus for recording and reproducing video signal after high efficiency coding, possessing address generating means (11) for controlling the addresses to the data memory, in which the input address (8) to the input data is assigned to the address of the already delivered data.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data shuffling apparatus used in recording or transmission of video information after high efficiency encoding. 2. Description of the Prior Art Video information is tremendous in the data quantity, and it is often transmitted or recorded after high efficiency encoding in order to curtail the data quantity. High efficiency encoding is means for compressing the data quantity by removing the redundant portions of the video information. As the method of high efficiency encoding, it is known, for example, to divide the input sample values first into blocks composed of adjacent plural pixels, and orthogonally transform in every block, and encode in every orthogonal transformation. In the case of such block unit coding, first the input video data must be shuffled, or rearranged into the sequence of blocks suited to encoding. In particular, to enhance the efficiency of high efficiency encoding or disperse the effects of an error, it is important to shuffle the blocks (see the Japanese Patent Application No. 63-271178). Here is explained an example of gathering two fields (= 1 frame) of TV signals to make up one page, and composing one block in the unit of two fields. Fig. 10 is an explanatory diagram of a block of this prior art. As shown in Fig. 10, this block is composed of a total of 64 pixels consisting of horizontal 8 pixels adjacent on the screen, vertical 4 lines, and two fields in the time axis direction. A conventional shuffling apparatus is shown in Fig. 11. In Fig. 11, numeral 1 is a video input unit, 2 is an input switch, 3 is a first page memory, 4 is a second page memory, 5 is an output switch, 6 is a video output unit, and 7 is an address control unit. A TV signal is first entered from the top line of the first field sequentially line after line, and after all lines of the first field are filled up, the input into the second field is started. Accordingly, in Fig. 11, the video data entered from the video input unit 1 is put into the first page memory 3 by the input switch 2. At the same time, the video data of the previous page recorded in the second page memory 4 is shuffled, and delivered into the video output unit 6 through the output switch 5. Meanwhile, the input and output addresses of these two page memories are controlled in the address control unit 7, and are rearranged into the blocks as shown in Fig. 10. In this way, when input and output of the image data for one page is over, the input switch 2 and output switch 5 are changed over, and the same processing as the previous page is conducted, using the first page memory as the output memory and the second page memory as the input memory. Thereafter, in every page, while changing over the input and output memories, by rearranging, the continuously entered moving picture can be shuffled. In the prior art, however, shuffling of data in two fields (one page) requires video memories for four fields (two pages). Since the video information is very large in data quantity, a large memory is required for shuffling, which resulted in increase of memory cost and power consumption. JP-A-1,114,277 discloses a data shuffling apparatus of this type, provided with two memories for storing two pages of data, and a memory changeover switch for alternately selecting one of the two memories to be the input memory, and one to be the output memory. EP-A-0,125,840 discloses a data shuffling apparatus which is designed to shuffle data in a field before storage to distribute proximal parts of the picture over distal regions of the storage medium, so that errors occurring on the storage medium are distributed evenly and less obviously across the reproduced image. The apparatus disclosed suffers from the same disadvantage as the apparatus disclosed in Fig. 11, in that either enough memory for two frames must be supplied, or the reading in and reading out from the memory cannot occur simultaneously. It is hence a primary object of the invention to present a data shuffling apparatus capable of realizing shuffling of data of one page by a memory of about one page, by controlling the addresses to the page memory. To achieve the above object, the invention presents a data shuffling apparatus for shuffling data in each of a plurality of pages of data, each of the plurality of pages being composed of a plurality of blocks of data, said apparatus comprising: a data memory having a storage capacity to hold a page of data for temporarily storing data; and data address generating means coupled to the data memory for generating a sequence of addresses of the data memory so that the data in the current page are written into the data memory in a first sequence and the written data are read out from the data memory in a second sequence which is different from the first sequence to thereby shuffle the data in the current page, characterized in that the data memory operates such that data in a block in the current page is read from a portion of the data memory indicated by a current address generated by the address generating means, and data in a block in a next page is thereafter written into the same portion of the data memory during a time said portion is addressed by the current address generating means, and that the data address generating means changes the sequence of the addresses of the data memory on a page by page basis. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a first embodiment of the invention; Fig. 2 is an execution diagram for data an address generating unit of the first embodiment of the invention when generating addresses for input of page n to data memory; Fig. 3 is an execution diagram of the data address generating unit of Fig. 2 when generating addresses for input of page n+1 to data memory; Fig. 4 is a block diagram of a second embodiment of the invention; Fig.5 is a block diagram of a third embodiment of the invention; Fig. 6 is a block diagram of a fourth embodiment of the invention; Fig. 7 is a diagram illustrating the constitution of an input address generating unit of the fourth embodiment; Fig. 8 is a block diagram of a fifth embodiment of the invention; Fig. 9 is an explanatory diagram of division of one page of video information according to the fifth embodiment of the invention; Fig. 10 is an explanatory diagram of block forming in the prior art; and Fig. 11 is a block diagram of a shuffling apparatus of the prior art. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings, some of the preferred embodiments of the invention are described below. Fig. 1 is a block diagram of a first embodiment of the invention. In Fig. 1, numeral 7 is a data input unit, 8 is an input address unit, 9 is an output address unit, 10 is a data memory, 11 is a data addressing generating unit, and 12 is a data output unit. This embodiment is a data shuffling apparatus for shuffling video signals in which one page is composed of two fields. The input and output addresses obtained from the input address unit 8 and output address unit 9 are fed into the data address generating unit 11, and are converted into an address for the data memory. The data recorded in the recording portion indicated by the address delivered from the data address generating unit 11 is delivered to the output unit 12. At the same time, the data in block unit entered from the input unit 7 is recorded in the recording portion indicated by the address delivered from the data address generating unit 11. Fig. 2 is an execution diagram of the data address generating unit 11 in Fig. 1. In Fig. 2, numeral 13 is an input address unit, same as 10 in Fig. 1, 14 is an output address unit, same as 11 in Fig. 1, 15 is a first address memory, 16 is a second address memory, 17 to 20 and 22 are switches, and 21 is a data address output unit. Suppose, in the first place, the address corresponding to the data memory at the time of input of the data of page n-1 into the data memory is recorded in the first address memory. The input address unit 13 is connected to the address of the second address memory by the switch 17, the output address unit 14 to the address of the first address memory by the switch 18, and the data address output unit 21 to the output of the first address memory and the input of the second address memory by the switches 19 and 20. The data address thus recorded in the first address memory is read out according to the output address entered from the output address unit 14, and is delivered to the address output unit 21 as the address corresponding to the data memory for entering page n. The address delivered from the address output unit 21 becomes the input address corresponding to the data of page n, and simultaneously becomes the output address of the data of page n-1. At the same time, the address of the data memory corresponding to the input of page n is recorded in the second address memory 16 according to the input address entered from the input address unit 13. In this way, all addresses of the data memory corresponding to page n are delivered, and then the switches are inverted, and the addresses corresponding to page n+1 are similarly delivered from the second address memory. Fig. 3 shows a connection example of the switches 17 to 20 corresponding to page n+1. In the data address generating unit of the invention, by repeating such operation in every frame, the input and output addresses of the data memory corresponding to each page can be generated. Incidentally, the switch 22 in Fig. 2 and Fig. 3 is used when the input address 13 is employed as the initial value of the content of the address memory, at the time of reset such as turning on the power. By utilizing the invention in this way, the data addresses of the output data and input data may be equalized, so that the size of the data memory may be reduced to 1/2 of the conventional memory. A second embodiment is explained, in which a part of the input data is not utilized. Generally, the video information contains horizontal blanking and vertical blanking in every field, and such portions are not usually transmitted in high efficiency encoding. Therefore, the capacity of the memory may be saved by not recording such redundant portions in the data memory. In the first embodiment, however, since the data input timing and output timing are identical, it is necessary to synchronize the timing of the redundant portion of the input side and the timing of the redundant portion of the output side. Fig. 4 is a block diagram of the embodiment for matching the timings of redundant parts of input and output. In Fig. 4, numeral 23 is an input unit, 24 is an input address unit, 25 is an output address unit, 26 is a buffer, 27 is a data memory, 28 is a data address generating unit, and 29 is an output unit. The difference between this embodiment and the embodiment explained in Fig. 1 is that the buffer 26 is placed between the input unit 23 and the data memory 27. The data entered from the input unit 23 is first recorded in the buffer 26, and is fed into the data memory 27 by matching with the timing of the data delivered to the output unit 29. Thus, by matching the input and output timings by using the buffer 26, this invention may be applied even if the input and output are different in timing. In the embodiment in Fig. 4, meanwhile, the buffer is disposed at the input side of the data memory, but it is also possible to install the buffer at the output side of the data memory. A third embodiment is explained by referring to the block diagram in Fig. 5. In Fig. 5, numeral 30 is a data input unit, 31 is a data memory for one page portion, 32 is a data output unit, 33 is an address memory, and 34 is an address converting unit. The video data of page n-1 recorded in the data memory 31 delivers the data recorded in the position shown by the address generated by the address converting unit 34 from the data output unit 32. After the output of the data at this address, the video data of page n entered from the data input unit 30 is entered in the same address. At the same time, the input and output addresses of the data memory 31 delivered from the address converting unit 34 are recorded in the address memory 33. The operation of the apparatus in Fig. 5 is described below. To simplify the explanation, it is supposed that the video data entering this shuffling apparatus is composed of horizontal 8 pixels and vertical 4 lines in one field, and is rearranged into a block of 64 pixels by gathering together the video data in two fields as shown in Fig. 10. Therefore, the line numbers of the input video data and the line numbers of the output video data are expressed in the sequence as shown in Table 1. The input line numbers 0 to 3 in Table 1 denote the first field, and 4 to 7, the second field. When the input and output sequences are controlled in this sequence shown in the table, a block of 64 pixels composed of two fields is made up. More specifically, when the input address of a certain page corresponding to the data memory is equal to the input line number of Table 1, the output address of that page may be generated by matching with the sequence of the output line numbers in Table 1. In Table 1, supposing the i-th input address of a certain page is Ai, the output address Bi to be delivered by the i-th time of that page is expressed in the following function f ( ): Bi = f (Ai) = 4 x Ai - p x 7 where p is a maximum integer as far as Bi is not a negative number. Input, output sequence Input line number Output line number 0 0 0 1 1 4 2 2 1 3 3 5 4 4 2 5 5 6 6 6 3 7 7 7 The address converting unit 34 in Fig. 5 generates, by using this function f ( ), the output address of page n-1 (that is, the input address of page n) from the input address of page n-1. In this embodiment, therefore, the output address of page n-1 of the data memory and the input address of page n are equal to each other. This input, output address is delayed for the portion of one page, and the input, output address of the next page is led out in the address converting unit 34. As a result, the input, output address for each page may be easily generated. Besides, the data memory necessary for this embodiment is enough with a memory for one page portion, and the video memory capacity may be reduced to 1/2 of the prior art in Fig. 11. Incidentally, the number of lines and number of pixels used in the explanation of this embodiment may be freely variable, and the address control in other than line unit is also possible. At the same time, the above function may be variously applied, and the address converting unit may be realized, for example, by a ROM table or the like. A fourth embodiment is shown in Fig. 6. In Fig. 6, numeral 35 is a data input unit, 36 is a data memory for one page, 37 is a data output unit, 38 is an address memory, 39 is an address converting unit, 40 is a delay circuit for delaying the address for a specific time, 41 is an input address generating unit, and 42 is an output address generating unit. The video data entered from the data input unit 35 is recorded in the data memory according to the input address generated by the input address generating unit 41. The output of the data memory 36 is delivered to the data output unit 37 according to the output address generated by the output address generating unit 42. Fig. 7 shows the constitution of the input address generating unit 41 and output address generating unit 42. In Fig. 7, numeral 43 denotes an upper position address input unit from the delay circuit 40 or address converting unit 39 in Fig. 6, 44 is a lower position address generating unit, and 45 is an address output unit. The upper position address entered from the input unit 43 is delivered from the output unit 45 together with the lower position address generated in the lower position address generating unit 44. The upper position address in this embodiment represents the address in block unit, while the lower position address is the address for rearranging the data in the block. Accordingly, when the address in the block unit (upper position address) differs, the lower position addresses in the input address generating unit 41 and output address generating unit 42 in Fig. 6 may be generated quite independently. The upper position address of the input and output address is generated by using the address memory 38 and address converting unit 39 same as in the embodiment in Fig. 5. The upper position address of the input address of page n-1 delivered from the address memory 38 is converted into the upper position address of the input address corresponding to page n (that is, the upper position address of the output address corresponding to page n-1) in the address converting unit 39. The upper position address obtained here is entered into the delay circuit 40 and output address generating unit 42. The upper position address entered in the delay circuit 40 is delayed for a specific time, and is entered into the input address generating unit 41. By this time delay, different addresses are entered in the upper position address to be entered in the input address generating unit 41 and the upper position address entered into the output address generating unit 42, and always the upper position address entered in the output address generating unit 42 is ahead. Therefore, the input address delivered from the input address generating unit 41 is always different from the output address delivered from the output address generating unit 42. In this embodiment, thus, the data in the page unit can be shuffled by the data memory for one page only. In this embodiment, different from the embodiment in Fig. 5, since the input and output addresses can be generated independently, a freer rearranging manner is possible. For example, the lower position address of the input address can generate addresses in every line by matching with the data input, while the lower position address of the output address can generate addresses in every horizontal 8 pixels, vertical 4 lines by matching with the data output. Furthermore, in this embodiment, since only the upper portion of the input and output address is generated by using the address memory, the capacity of the address memory may be saved. In this embodiment, moreover, the timing of the data output is ahead of the timing of the data input for the portion of delay time by the delay circuit 40. In actual TV signal, however, a specific blanking period is present at the end of one page. Accordingly, by advancing the data output by making use of this blanking period, it is possible to start output after the input of the previous page is all over. Referring now to Fig. 8, a fifth embodiment is explained below. In Fig. 8, numeral 46 is a data input unit, 47 is a data memory for one page, 48 is a data output unit, 49 is an address memory, 50 is a first address converting unit, 51 is a second address converting unit, 52 is a third address converting unit, 53 is a fourth address converting unit, 54 is a fifth address converting unit, 55 is a delay circuit for delaying the address for a specific time, 56 is an input address generating unit, and 57 is an output address generating unit. The video data entered from the data input unit 46 is recorded in the data memory according to the input address generated by the input address generating unit 56. The output of the data memory 47 is delivered to the data output unit 48 according to the output address generated by the output address generating unit 57. Of these input and output addresses, the lower position addresses are generated inside the input address generating unit 56 and output address generating unit 57 as shown in Fig. 7. By contrast, the upper position addresses of the input, and output addresses are generated, same as in the embodiment in Fig. 6, in a total of five (k = 5) address converting units of the first address converting unit 50 to fifth address converting unit 54, as well as in the address memory 49. In this embodiment, the video information of one page is divided into five parts in the horizontal direction as shown in Fig. 9, and is rearranged differently in block unit in each part. Therefore, the upper position address of the input address of the previous page delivered from the address memory 49 is a first classified into five groups, and depending on which region in Fig. 9 each group belongs to, the address converting means is selected out of the first address converting unit 50 to the fifth address converting unit 54. The upper position address converted by the selected address converting means is entered into the delay circuit 55 and output address generating unit 57. The upper position address entered into the delay circuit 55 is delayed for a specific time, and is fed into the input address generating unit 56. As a result, the input address delivered from the input address generating unit 56 is always different from the output address delivered from the output address generating unit 57, it is moreover possible to generate the position already after the output by the output address. By contrast to the embodiment in Fig. 6, the embodiment in Fig. 8 is advanced in the degree of freedom of shuffling the data. In this embodiment, as shown in Fig. 9, since one page is divided into five parts and reassembled, it is suited to improvement of efficiency of high efficiency encoding, and shuffling process for dispersing the effect of transmission route error. Meanwhile, the method of dividing one page and the number of divisions (k) are arbitrary. The invention is explained herein by referring to five embodiments, but the constitution of the invention may be realized also in other various manners. In the fourth and fifth embodiments, the input and output addresses to the data memory are independently. By making use of this property, in the input signal having jitter in the household VTR or the like, the input clock of the data memory can be synchronized with the input signal, and the output clock may be synchronized with the subsequent signal processing clock, so that the input jitter can be removed. Or by controlling the data address generating unit of the invention, it is also possible to realize special reproduction such as still picture, slow and strobe display. Incidentally, in the foregoing embodiments of the invention, the use in encoding is explained, but the invention may be similarly applied to decoding. Or, one page issupposed to be composed of two fields, but one page may be composed in the unit of various data quantities, and it may be also applied to shuffling of other data than video signal. In thus constituted invention, the addresses to the input video data are assigned to the addresses of the already delivered video data. Accordingly, shuffling of one page can be realized by the data memory for the portion of one page, so that the moving picture may be shuffled in the memory capacity of 1/2 of the prior art. Besides, the input and output addresses of each page may be easily generated by using the addresses of the previous page recorded in the address memory. As a result, by a relatively simple control, the circuit scale and power consumption may be greatly reduced. Furthermore, the invention may be also applied in removal of jitter from the input signal.

Claims: A data shuffling apparatus for shuffling data in each of a plurality of pages of data, each of the plurality of pages being composed of a plurality of blocks of data, said apparatus comprising: a data memory (10; 27; 31; 35; 47) having a storage capacity to hold a page of data for temporarily storing data; and data address generating means (11; 28) coupled to the data memory for generating a sequence of addresses of the data memory so that the data in the current page are written into the data memory in a first sequence and the written data are read out from the data memory in a second sequence which is different from the first sequence to thereby shuffle the data in the current page, characterized in that the data memory (10; 27; 31; 35; 47) operates such that data in a block in the current page is read from a portion of the data memory indicated by a current address generated by the address generating means, and data in a block in a next page is thereafter written into the same portion of the data memory during a time said portion is addressed by the current address generated by the data address generating means, and that the data address generating means (11; 28) changes the sequence of the addresses of the data memory on a page by page basis. An apparatus according to claim 1, wherein the data address generating means (11; 28) includes an address memory (33; 38; 49) for recording therein the addresses of the data memory corresponding to the current page, and an address converting means (34; 39) coupled to the address memory for converting an address read from a portion of the address memory by a predetermined conversion function and applying the converted address to the data memory and the address memory, wherein the address memory stores the converted address to the same portion of the address memory from which the address is read. An apparatus according to claim 1, further comprising buffer means (26; 40; 55) for matching timings of data inputted to the data memory and data outputted from the data memory. An apparatus according to claim 1, wherein the data address generating means comprises: an address memory (33;38;49) for recording therein addresses of the data memory such that an address Bi indicating an area of the data memory from which a block of data written therein has been read out is recorded into an address i of the address memory, the address Bi recorded in the address i of the address memory being applied to the data memory for writing an i-th input block of data in the current page into the area of the data memory indicated by the address Bi; and address converting means (34;39) coupled to the address memory for converting the address Bi outputted from the address memory to an address Ai which is expressed by Ai=f(Bi), where f( ) denotes a predetermined conversion function of Bi, the address Ai being applied to the data memory (31;36) for reading out a block of data written into an area of the data memory indicated by the address Ai as an i-th output block of data in the current page. An apparatus according to claim 1, wherein the address is composed of an upper position address indicating an area for one block of data and a lower position address indicating a portion for each data in the block within the area, and wherein the data address generating means comprises: lower position address generating means (44) for generating the lower position address; an address memory (38) for recording therein upper position addresses of the data memory such that an address Bi indicating an area of the data memory (36) from which a block of data written therein has been read out is recorded into an address i of the address memory being applied together with the lower position address generated by the lower position address generating means (44) to the data memory for writing an i-th input block of data in the current page into the area of the data memory indicated by the address Bi; and address converting means coupled to the address memory (38) for converting the address Bi outputted from the address memory to an address Ai which is expressed by Ai=f(Bi), where f( ) denotes a predetermined conversion function of Bi, the address Ai being applied together with the lower position address generated by the lower position address generating means (44) to the data memory (56) for reading out a block of data written into a portion of the data memory indicated by the address Ai as an i-th output block of data in the current page. An apparatus according to claim 1, wherein the plurality of blocks in the current page are classified into a plurality of groups of blocks, wherein the data address generating means generates an address of the data memory (47) so that the data in each of the plurality of groups of blocks in the current page are written into the data memory in a first sequence and the written data are read out from the data memory in a second sequence which is different from the first sequence to thereby shuffle the data in each of the plurality of groups of blocks in the current page, wherein the data address generating means comprises: an address memory (49) for recording therein addresses of the data memory such that an address Bi indicating an area of the data memory from which a block of data written therein has been read out is recorded into an address i of the address memory, the address Bi recorded in the address i of the address memory being applied to the data memory (47) for writing an i-th input block of data in the current page into the area of the data memory indicated by the address Bi; and a plurality of address converting means (50-54) each being coupled to the address memory for converting the address Bi outputted from the address memory, wherein, when the i-th input block of the data in the current page belongs to a j-th group of blocks among the plurality of groups of blocks of data, a j-th address converting means converts the address Ai which is expressed by Ai=fj(Bi), where fj( ) denotes a predetermined conversion function of Bi which is dependent on the j-th group of blocks, the address Ai being applied to the data memory (47) for reading out a block of data written into an area of the data memory indicated by the address Ai as an i-th output block of data in the current page. An apparatus according to claim 1, wherein the plurality of blocks in the current page are classified into a plurality of groups of blocks, wherein the data address generating means generates an address of the data memory (47) so that the data in each of the plurality of groups of blocks in the current page are written into the data memory (47) in a first sequence and the written data are read out from the data memory in a second sequence which is different from the first sequence to thereby shuffle the data in each of the plurality of groups of blocks in the current page, wherein the address is composed of an upper position address indicating an area for one block of data and a lower position address indicating a portion of each data in the block within the area, and wherein the data address generating means comprises: lower position address generating means (44) for generating the lower position address; an address memory (49) for recording therein upper position addresses of the data memory (47) such that an address Bi indicating an area of the data memory from which a block of data written therein has been read out is recorded into an address i of the address memory, the address Bi recorded in the address i of the address memory being applied together with the lower position address generated by the lower position address generating means (44) to the data memory for writing an i-th input block of data in the current page into the area of the data memory indicated by the address Bi; and a plurality of address converting means (50-54) each being coupled to the address memory (49) for converting the address Bi outputted from the address memory, wherein, when the i-th input block of data in the current page belongs to a j-th group of blocks among the plurality of groups of blocks of data, a j-th address converting means converts the address Bi outputted from the address memory to an address Ai which is expressed by Ai=fj(Bi), where fj( ) denotes a predetermined conversion function of Bi which is dependent on the j-th group of blocks, the address Ai being applied to the data memory (47) for reading out a block of data written into an area of the data memory indicated by the address Ai as an i-th output block of data in the current page. An apparatus according to claim 1, wherein the data address generating means comprises: a first address memory (15) for recording therein addresses of the data memory (10) for reading out the data in the current page stored in the data memory, the first address memory being responsive to an externally given read address (13;14) for outputting an address (21) recorded in an area of the first address memory indicated by the externally given read address to the data memory for reading a block of data stored in an area of the data memory indicated by the address memory and then writing a block of data in a next page into the area of the data memory indicated by the address outputted from the first address memory; and a second address memory (16) for recording therein addresses of the data memory (10) for shuffling the data in the next page, the second address memory being responsive to an externally given write address (13;14) for recording the address outputted from the first address memory into an area of the second address memory (16) indicated by the externally given write address, and wherein operations of the first and second address memories (15;16) being alternately changed over to each other on page by page basis. An apparatus according to any of claims 1 to 8, wherein each page of the plurality of pages being inputted to the apparatus is preceded by a blanking period, and wherein the data in the current page written in the data memory (10;27,31;36;47) being read out during the blanking period of the next page. An apparatus according to any of claims 1 to 8, wherein the data to be shuffled are data of a video signal, and wherein a timing for writing the data into the data memory (10;27;31;36;47) is synchronized with a clock which is synchronized with the horizontal synchronizing signal of the video signal, and a timing for reading out the written data from the data memory is synchronized with a clock signal of a data processor coupled to the apparatus. An apparatus according to any of claims 1 to 8, wherein the data to be shuffled are data of a video signal, and wherein a timing for writing the data into the data memory (10;27;31;36;47) is synchronized with a clock signal of a data processor coupled to the apparatus, and a timing for reading out the written data from the data memory is synchronized with a clock which is synchronized with the horizontal synchronizing signal of the video signal.

Inventors: JURI TATSURO, KASHIRO TAKAO, MATSUMI CHIYOKO, JURI, TATSURO, KASHIRO, TAKAO, MATSUMI, CHIYOKO
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1991
Main classification: H04N5
IPC codes: H04N7, H04N5