Driver circuit

Abstract: The driver circuit comprises drive means (Q2) for drawing an output current from a bus line (13) in a first state of the circuit. An output diode (S1) in the path of the output current is reverse biased in a second state of the circuit to isolate the drive means from the bus line. The driver circuit comprises means (26, S3, P1) for biasing the output during connection of the circuit to a live bus line, so as to reduce noise for other circuits connected to the bus line. Further a control current (I Q2B ) for the drive transistor is drawn from the bus line (13), beyond the output diode (S1). By this means, power dissipation (heat) within the driver circuit due to the control current is eliminated.

Description: The invention relates to a bus system according to the precharacterizing part of Claim 1. The invention also relates to a circuit module and a logic bus driver circuit for use in such a bus system. Such a bus system is known from European patent application EP. 0 352 965. This publication discloses a bus system with two busses connected via a data transfer circuit which transfers data between the two busses. This circuit is intended for use inside an integrated circuit. The use of two busses with a connecting data transfer circuit reduces the required magnitude of the output current that has to be provided by the driver circuits in each of the circuits connected to one of the busses. A conventional driver circuit causes a desired voltage swing on the bus line in a time period determined by the capacitance of the bus line, the magnitude of the voltage swing and the magnitude of the output current. Three measures that can be used to increase the speed of communication are (i) to increase the current capability of the drive means, (ii) to reduce the bus line capacitance and (iii) to reduce the voltage swing required. An example of a standard bus system which seeks higher operating speeds by a combination of these three measures is the Futurebus+ system, defined by IEEE Standard 896.1. Many other standard and proprietary bus systems have sought to provide high-speed communication by one or more of these means, and will continue to do so into the future. In such systems, ever higher output currents are specified. The power dissipation (heat) which inevitably results from these high currents becomes a constraint when it is desired to include one or more driver circuits in a single integrated circuit (chip). Additional power dissipation arises from control circuitry and can make this constraint more severe. For example, bipolar transistors make compact, high-current drive means, but demand substantial control currents to keep them turned on. The power dissipation involved in supplying these control currents can amount to a significant portion of the total power dissipation of the chip. When an individual driver circuit is not active, it becomes part of the load for the other driver circuits connected to the bus line. Unfortunately, high-current drive means, and bipolar transistors especially, tend to have large output capacitances. Coupling these capacitances to the bus line negates the speed advantage gained from the higher output current. Ideally, output capacitances of individual circuits should make only a minor contribution to the overall capacitance of the bus line, so that bus line performance is independent of the number of modules connected. A further consequence of the output capacitance of a driver circuit is that the driver cannot be connected to a "live" bus line (that is, one on which other drivers and receivers are communicating) without introducing some noise on the bus line. A new circuit module suddenly connected to a live bus line can therefore result in loss of data for other modules, or even total system failure. Since many modular data processing systems are used in critical, real-time applications such as process control and telephone switching, live insertion of new modules is desirable, while the consequences of data loss or systems failure can be very serious. Note that reducing the voltage swing between the logic levels on the bus line increases speed only at the expense of reducing the inherent noise immunity of the receiving modules. United States Patent US 4 415 817 describes a logic circuit including a bipolar drive transistor, a bipolar control transistor, and a plurality of output diodes. Each output diode carries an output current to the input of a respective further logic circuit. The output diodes are provided to isolate these further circuits from one another, and to provide a high "fan-out" of the logic circuit (the number of inputs that can be driven by the logic circuit). Japanese patent publication No. 58/084342 describes a circuit with a number sample and hold circuits collectively connected to an A/D converter via a multiplexer. The node between the multiplexer and the A/B converter is discharged completely each time the selection of the multiplexer changes. It is an object of the invention to address one or more of the above problems and to enable the provision of an improved bus system, circuit module and driver circuit for bus lines. The invention provides for a bus system according to the characterizing part of Claim 1. The noise generated during live insertion of such a driver circuit is reduced because of the reduced voltage swing between the voltage at the output terminal and the voltage actually present on the bus line (which is in the range between 0.75V and 2.0V in the case of the Futurebus+ bus system, whereas the power supply terminals in the Futurebus+ system are at 0V and 5V respectively). The pre-biassing means may comprise a bias supply terminal for connection to a bias voltage source, which bias voltage source is connected and active before connection to the bus line. The bias voltage source may for example comprise a battery, or a connector pin designed to make contact before other connector pins make contact during connection of a circuit module to a live bus system. Such a driver circuit may further comprise means for isolating the bias supply terminal from the remainder of the circuit once conduction of a main supply current is established, and/or means for isolating the bias supply terminal from the remainder of the circuit when no bias voltage source suitable for pre-biassing is connected to the bias supply terminal. The pre-biassing means may include an output diode having a cathode connected to the drive means and having an anode connected to the output terminal. The output diode isolates the drive means from the output terminal when the voltage at the output terminal is lower than the voltage at the output of the drive means. In this case the output diode becomes reverse biased and thereby acts as a small capacitance in series with a large capacitance in series with the large capacitance of the drive means reducing the overall capacitance at the output terminal. Active further drive means can bring the voltage at the output of the drive means at a level above the voltage of the output terminal more quickly than a mere resistor, for example. The output diode may be a Schottky diode. The capacitance of a Schottky diode is lower than that of a p-n diode, and thus provides better isolation. The lower forward voltage drop of a Schottky diode also relieves some design constraints and assists in reducing on-chip power dissipation. In an embodiment, the pre-biasing means are arranged to apply a reverse bias to the output diode before connection of the output terminal to the bus line. In this way, the pre-biasing means enables the output diode to isolate the larger capacitance of the drive means from the bus during live insertion. In an embodiment the circuit module comprises a further transistor whose main current path is connected between the anode and the control electrode of the first mentioned transistor and whose control electrode is controlled through the input signal. The drawing of control current from the output terminal by the further transistor from the output terminal beyond the output diode means that some or all of the power dissipation due to the control current will occur outside the driver circuit, relieving somewhat the constraint on the packaging of driver circuits in an integrated circuit. In contrast, the control transistor in the logic circuit of US 4,415,817 draws the control current for the drive transistor via a resistor from an internal supply terminal of the logic circuit, and not from an output terminal. Thus the control current in the known logic circuit makes a full contribution to power dissipation within the logic package. The known logic circuit is not described as being suitable for driving a high-speed bus via a single output diode. The high frequency (capacitive) properties of output diodes are not discussed in US 4,415,817. Brief Description of the Drawings Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawing, in which: Figure 1 shows a driver circuit in accordance with the present invention; Figure 2 shows various voltage levels for a specific embodiment of the driver circuit of Figure 1; Figure 3 shows parasitic capacitances in the driver circuit of Figure 1; and Figure 4 shows a circuit module including the driver circuit of Figure 1. Detailed Description of the Embodiments Figure 1 shows a driver circuit which is connected between an input terminal 10 (V I ) and an output terminal 12 (V O ). The output terminal is shown connected to an intermediate point on a bus line 13 which is modelled in Figure 1 by transmission lines 14 and 16, terminated by respective resistors 18 and 20. The transmission lines 14 and 16 have a characteristic impedance Z 0 , while the terminating resistors 18 and 20 connect the bus line to a terminating voltage V t with a resistance R t each. The output terminal 12 (V O ) may be an output pin of an integrated circuit package including the driver circuit, and also a connector for making the connection to the bus line 13. The driver circuit has two main supply terminals 22 (V CC ) and 24 (V GND ) and a bias supply terminal 26 (V BIAS ). The supply terminals 22, 24 and 26 may be the supply pins of the integrated circuit package, which may include several similar driver circuits. Between the supply terminal 22 (V CC ) and the supply terminal 24 V( GND ), there are connected in series: a first resistor R1, an upper NPN transistor Q1, two p-n didoes D1 and D2 and a lower NPN transistor Q2. The NPN transistors Q1 and Q2 have their emitters towards terminal 24 (V GND ) and the diodes D1 and D2 have their cathodes towards terminal 24 (V GND ). The collector of the lower NPN transistor Q2 is connected to the cathode of a first Schottky diode S1, whose anode is connected to the output terminal 12 (V O ). The inverter terminal 10 (V I ) is connected to the input of a CMOS inverter 28 and also to the gate of an N-channel insulated gate field-effect transistor N1. The term "CMOS" is used in a broad sense herein, and includes in particular insulated gate transistor technology wherein the transistor gates are made of polysilicon rather than metal. The drain of transistor N1 is connected to the output terminal 12 (V O ), while the source of transistor N1 is connected to the base of the lower NPN transistor Q2. The devices N1, Q2 and S1 together form a lower drive arrangement 30 of the driver circuit. The output of the inverter 28 is connected to the base of the upper NPN transistor Q1 and also to the gate of a further N-channel insulated gate transistor N2. The drain of transistor N2 is connected to the base of the lower NPN transistor Q2 via a second resistor R2 and a second Schottky diode S2 (cathode to R2). The source of transistor N2 is connected to the supply terminal 24 (V GND ). The devices N2, R2 and S2 form a base pull-off arrangement 32 for the lower NPN transistor Q2. A P-channel insulated gate transistor P1 has its source and gate connected to the emitter and collector respectively of the upper NPN transistor Q1. The collector of transistor Q1 is connected to the bias supply terminal 26 (V BIAS ) via a third Schottky diode S3. Figure 2 shows the voltage levels V CC , V GDN and so forth that are present in normal operation in a version of the Figure 1 circuit suitable for use as a backplane driver in a Futurebus+ system. This version of the circuit is presented by way of example only. The invention is in no way limited to application in Futurebus+ or any other standard bus system. In normal operation, a positive supply voltage V CC =5.0V is applied to the terminal 22, while a ground supply voltage V GND =0.0V is applied to terminal 24. A positive bias voltage V BIAS , equal to V CC , is applied to the terminal 26. Thus, in normal operation, the P-channel transistor is turned off (non-conducting), so that the elements P1 and S3 may be ignored. The elements P1 and S3 play a role in the "live insertion" of the driver circuit, to be described below with reference to Figure 3. The driver circuit receives at its input 10 a logic signal V I at conventional CMOS levels, and produces at its output 12 a corresponding inverted output signal V O at the logic levels of the Futurebus+ system. In that system, a low logic level is represented by V O =V OL =1.0V when V I is high, while a high level is represented by V O =V OH =2.0V when V I is low. A threshold voltage V TH = 1.55V is used by receiver circuits connected to the bus line 13 to distinguish between logic levels. The standard in fact specifies the following tolerance ranges (min,max): V OL (0.75,1.1V); V OH (1.9V,2.0V); V TH (1.47V, 1.62V); V CC (4.5V, 5.5V). When V I is low (indicating the V OH state), the output of the inverter 28 is high (V CC ). Then the transistor N1 is turned off, while the transistor N2 and the upper NPN transistor Q1 are both turned on (conducting). In this state, therefore, the pull-off arrangement 32 actively turns off the lower NPN transistor Q2. The Schottky diode S2 has a characteristic forward voltage drop V S2 which is slightly less than the characteristic base-emitter forward voltage V BE of the NPN transistor Q2. This will improve switching speed in a subsequent transition to the V OL state, since the capacitance inherent in the base of transistor Q2 need only be changed from V S2 to VBE before the NPN transistor Q2 will turn on. At the same time, the transistor Q1 is conducting and the diodes D1 and D2 are forward biased. The voltage drop from V CC across the transistor Q1 and the diodes D1 and D2 means that the cathode of the output Schottky diode S1 is pulled up to a voltage around 3V, that is, somewhere between V OH and V CC . The output Schottky diode S1 is therefore reverse biased and, since the transistor Q2 is turned off, no static current flows in the driver circuit in the V OH state. In the V OH state, the circuit is essentially passive, the bus line 13 being held at V OH by the terminating voltage V t acting via the terminating resistors 18 and 20. In a transition from the V OL state to the V OH state, the capacitance C S1 of the output pin 12, to assist a rapid transition on the bus line 13. Figure 3 shows C S1 and other capacitances present in the driver circuit of Figure 1. The transistor Q2 has a large effective collector emitter capacitance C Q2 due to its large size and the Miller effect which multiplies the actual collector-base capacitance by the current gain β (beta) of the transistor. This large capacitance C Q2 is decoupled from the output pin 12 in the V OH state by the smaller capacitance C C1 of the reverse biased output Schottky diode S1. Also connected to the output pin 12 is an electrostatic discharge (ESD) protection device E1, represented as a further NPN transistor with its base and emitter both connected to V GND . The ESD device E1 has a parasitic capacitance C E1 , which is not enhanced by the Miller effect because of the base-emitter connection. Also present is the capacitance C P inherent in the output pin 12, and the connections from it to the bus line 13. The total output capacitance C O of the driver circuit is approximately C S1 +C E1 +C P , and in particular does not include the large capacitance C Q2 of the lower NPN transistor Q2. The circuit can therefore be designed to have low output capacitance C O . A maximum of C O =5 picofarads (5pF) is specified for the Futurebus+ system. Subsequently, when V I goes high (to V CC ), a transition to the V OL state is initiated. The output of the inverter 28 goes low (to V GDN ). Transistors Q1 and N2 are thus turned off, while the N-channel base control transistor N1 turns on. Since V O is still equal to V O H at this point, transistor N1 can supply base current I Q2B to the lower NPN transistor Q2. This base current turns on transistor Q2 which draws an output current I O through the now forward biased Schottky diode S1, pulling the output pin 12 and the bus line 13 towards V GND . The output voltage V O does nor reach V GND , however. The transistor N1 is designed to have a certain on-resistance R DSN1 which causes V O to limited at the desired level V OL (1.0V for Futurebus+), while I O settles to a static value IOL. The value R DSN1 required to give a desired combination of V OL and I OL can be determined from a knowledge of VBE and β for the NPN transistor Q2 through the relation: R DSN1 = β ( V OL - V BE ) I OL The desired setting of V OL holds over a wide range of temperature, since the gain of the N-channel transistor N1 decreases as VBE of the NPN transistor Q2 decreases with increasing temperature. In the V OL state, the driver circuit has active control of the level on the bus line 13. This allows control to be taken by any one of many such circuits connected to the bus line 13 in a wired-AND configuration. The non-controlling circuits simply remain in the V OH state. For the Futurebus+ system, the static output current I OL is nominally 80 milliamps (mA). With I OL =80mA, a bus line having a total capacitance of 150pF can be driven through a swing of one volt (that is, from V OH to V OL ) in just under two nanoseconds (ns). If 2ns is a desired switching speed for the bus system, it becomes apparent why a limit such as 5pF must be imposed on the output capacitance of each passive driver attached to the bus line, even with such a high current drive capability. The 150pF may for example comprise 100pF due to the bus line itself and 50pF due to ten other drivers being connected to the same bus line. The lower NPN transistor Q2 has to be large enough to supply the large current I OL for the duration of the V OL state, which results inevitably in a high power dissipation (V OL ×I OL =1.0×0.08=0.08watts) within the driver chip in the V OL state. The pins 12 (V O ) and 24 (V GND ) and the corresponding internal interconnections must be constructed to carry the large current. In an integrated circuit with nine such driver circuits, the static ground supply current through pin 24 (V GND ) might reach 700-800mA accompanied by 7-8 watts of on-chip power dissipation. A circuit designed to cope with worst-case conditions might expect to supply I OL as high as 100mA. In this context, any additional on-chip power dissipation or current supply requirement for the circuit is very undesirable. The particular lower drive arrangement 30 in the circuit of Figure 1 contributes to a lower on-chip power dissipation. In particular, the connection of the drain of the N-channel transistor N1 to the output pin 12, beyond the output Schottky diode S1, results in the base current I Q2B (equal to I OL /β) being drawn from the bus line 13, rather than from the chip's own positive supply terminal 22 (V CC ). Assuming a value of 100 for β, and assuming I OL =80mA, an on-chip power dissipation of (V CC -VBE)xI Q2B , at least 3.4 milliwatts (mW), is avoided per driver circuit. In fact, a more conventional control arrangement would have to generate several times the nominal value of I Q2B , because of the need to compensate V OL against worst-case variations of operating temperature and supply voltage. The gain β of the bipolar transistor Q2 might for example vary from 60 to 200 over a typical range of operating temperature. Assuming again that nine driver circuits are integrated on a single chip, a potential 150-200mW of on-chip power dissipation has been avoided. There is moreover no corresponding increase in the power dissipation in the backplane or anywhere else off-chip, since I OL is the same whether or not it includes the control current I Q2B . A further benefit of drawing the base current for the transistor Q2 from the output terminal is that the positive supply terminal 22 (V CC ) needs to pass no significant static current, in either state. Only a transient current is drawn during the transition from the V OL state to the V OH state. Those skilled in the art will appreciate that many variations of driver circuit are possible around the basic driving arrangement 30. Such variations will inevitably result when such a driving arrangement is adapted to different applications other than the Futurebus+ backplane. The polarities of the various transistors and diodes may be reversed, different voltage levels and current requirements may arise, and so forth. A complementary pair of such driving arrangements may be desirable in another application. The circuit need not be constructed in BiCMOS technology. The N-channel base control transistor N1 could be replaced by bipolar transistor, although this might require a very small base current to be drawn from V CC or from the input terminal 10. Figure 4 shows the driver circuit of Figure 1 (referenced 40 in Figure 4) as part of a larger circuit module 42, which makes use of the driver circuit's features for so-called live insertion. The terminals and signals of the driver circuit 40 are identified by the same reference signs as in Figure 1. The module 42 may for example comprise a single integrated circuit, a multi-chip package or a printed circuit board. The module 42 is connected in operation to other modules via bus system in the form of a backplane 44, and is removably connected to the backplane 44 by a connector 46 having mating pairs of contacts suffixed "a" and "b". The backplane 44 includes the bus line 13 of Figure 1, and supply lines 48 (V CC ') and 50 (V GND '). The bus line 13 may be unique in the backplane, carrying only serial data, or it may be just one of tens or hundreds of bus lines, carrying parallel data. Within the connector 46, a group of mating contact pairs 52a/52b is provided for connecting the module 42 to the V CC ' supply line 48 of the backplane. Another group of mating contact pairs 54a/54b is provided for connecting the module 42 to the V GND ' supply line 50. A single contact pair 56a/5b connects the module 42 to the bus line 13. An additional contact pair 58a/58b, distinct from the group 52a/52b, also connects the module to the V CC '. The contact pair 58a/58b and at least one of the contact pairs in the group 54a/54b are constructed so as to make contact before the contact pairs 52a/52b and 56a/56b during mating of the connector 46. The connector 46 is shown in Figure 4 in an intermediate state of insertion in which only the contact pairs 58a/58b and at least one of the group 54a/54b are mated. Within the circuit module 42 the driver circuit 40, a receiver circuit 60 and a data processing (DP) circuit 62 are all connected for operation to module supply lines 64 (V CC ) and 66 (V GND ). The V GND supply line 66 s connected directly to the contacts 54a of the connector 46, while the V CC supply line 64 is connected to the contacts 52a through a switch 68. The bias supply terminal 26 (V BIAS ) of the driver circuit 40 is connected to the contact 58a. The DP circuit 62 is connected to receive data from the contact 56a (bus line 13) via the receiver circuit 60. The DP circuit is connected for transmission of data to the input terminal 10 of the driver circuit 40, whose output 12 (V O ) is also connected to the contact 56a. Live insertion is the action of connecting the circuit module 42 to the backplane 44 while the backplane is active, and other modules (not shown) are communicating via the bus line 13. The main voltage supply lines 64 and 66 for the module 42 are connected via groups of contact pairs because of the supply currents for the module are too great for a single contact pair. The switch 68 is used to block the main supply currents during live insertion, since one contact pair in each group will inevitably mate first, and would otherwise be damaged or destroyed by the large current. The switch may be closed manually or automatically to activate the circuit module 42 once all contact pairs are fully mated. During live insertion, the sudden connection of the inactive driver circuit output 12 to the bus line 13 imposes a transient load on the bus line 13, while the output capacitance of the driver circuit charges to the unknown level present on the bus line 13. If this output capacitance were to include the large Miller capacitance C Q2 of the bipolar transistor Q2 (Figures 1 and 3), the resulting noise on the bus line could easily cause loss of data or perhaps a total system failure. Since the switch 68 is not yet closed, the main positive supply V CC is not available to reverse bias the output Schottky diode S1 and so isolate C Q2 from the output terminal. In the circuit module 42, however, the bias supply terminal 26 (V BIAS ) of the driver circuit 40 is arranged to receive the bias voltage V BIAS independently of the main voltage supply V CC , and before contact is made with the bus line 13. This bias supply is used in the driver circuit 40 to pre-bias the output 12 of the driver circuit as follows. Before power is applied to the circuit, all points can be assumed to be discharged to a common level, V GND . In particular, the V CC supply pin 22 is assumed to be at V GND . Leakage through insulation or atmosphere will generally ensure this state. If necessary, additional Schottky diodes S4 and S5 can be added as shown by broken lines in Figure 1, where they will discharge respective nodes in the circuit almost to V GND without affecting normal operation. When V BIAS is applied before V CC , as shown in Figure 4, the P-channel transistor P1 gets turned on by the connection of its gate to the V CC pin 22 via the resistor R1. This completes a current path from the V BIAS pin 26 to the junction of the collector of the lower NPN transistor Q2 and the cathode of the Schottky diode S1. This current path is represented in Figure 3 and included the diodes D1, D2 and S3. The current through this path therefore draws the collector of transistor Q2 to a voltage VC which is fixed below V BIAS by an amount equal to the sum of the forward voltage drops across those diodes. Assuming V BIAS =5.0V, V C will be a little over 3 volts. With the collector of transistor Q2 at or above V OH in this manner, no transient current needs to be drawn from the bus line 13 to charge the Miller capacitance C Q2 of the transistor Q2 when contact is made between the output pin 12 (V O ) and the bus line. Moreover, the Schottky diode S1 is reverse biased (V C is greater than V OH and V t ). The low operating output capacitance C O of the driver circuit (approximately C S1 +C E1 +C P ) is therefore in place as a barrier to large transients before the output terminal 12 is connected to the bus line 13. The total output capacitance will be seen to comprise a first component (chiefly C S1 ) in series with a second component. In addition to charging the transistor Q2 and isolating the capacitance C Q2 from the output pin 12, the current from the V BIAS pin 26 also charges the capacitive voltage divider formed by these two components of the output capacitance C O . If C S1 is designed to be approximately equal to C E1 +C P , then the output pin 12 (V O ) will be charged to voltage midway between V GND and V C . Since V C is a little over 3 volts in the example, the output pin 12 becomes charged to a voltage between the Futurebus+ logic levels V OH and V OL , somewhere close to the threshold voltage V TH =1.55V. Consequently, transient current from the bus line 13 will only be required to charge C O the short distance from V TH to the level V OH or V OL prevailing on the bus line 13 when contact is made. By this means, the noise resulting from mating of the contact pair 56a/56b is further reduced, to a level at which it is very unlikely to cause data loss for the other modules connected to the bus line 13. When the switch 68 is eventually closed, and the terminal 22 of the driver circuit 40 is connected to the backplane supply line 48, the P-channel transistor P1 turns off, allowing normal operation of the driver circuit to commence. Since the collector of the lower transistor Q2 is pre-charged to the voltage V C , above V OH , the circuit is essentially already in the passive, V OH state. Thus the module 42 can commence receiving data from the bus line 13 without introducing any further noise to the system. The Schottky diode S3 serves a further purpose in addition to its role in setting V C . If the live insertion facility is not in use, or if the V BIAS supply fails, either the Schottky diode S3 or the transistor P1 will isolate the V BIAS terminal 26 from the rest of the circuit whether that terminal is tied to V CC , tied to V GND , or left floating. Those skilled in the art will readily appreciate that many variations of the pre-biasing arrangement described are possible. For example, the bias supply voltage V BIAS could be provided by a battery supply within the circuit module 42, rather than by a special arrangement of contacts in the backplane connector 46. Those skilled in the art will further appreciate how the pre-charging of the various capacitances can be adjusted to allow low-noise live insertion in a given application. The voltage drops in the pre-charging current path can be altered as required, and also the capacitances if necessary, subject of course to other constraints. In particular, the capacitance of a diode such as the Schottky diode S1 can be altered by varying the size or nature of the device itself and/or by varying the size of the reverse bias voltage applied to the diode during the pre-charging. It will apparent that the provision and efficacy of the particular lower driving arrangement 30 is in no way dependent on the provision of a pre-biasing mechanism for live insertion,and vice versa .

Claims: A bus system comprising at least one data bus line and a circuit module removably connected to the data bus line, the circuit module comprising a logic bus driver circuit (40) having an output terminal (12) removably connected to the data bus line (13); a supply terminal for connection to a supply voltage (GND); drive means (Q2, N1) for connecting the output terminal to the supply terminal for passage of an output current under control of an input signal; characterized, in that the circuit module comprises connector means for applying a bias voltage to a supply terminal and for connecting the circuit module to the bus, the connector means being arranged for ensuring that during live insertion the bias voltage is contacted to the bias supply terminal of the driver circuit before the output terminal makes contact to the bus line, live insertion being physical connection of the circuit module to the data bus line while that data bus line is active, and in that the logic bus driver circuit contains pre-biasing means (26, S3, P1, S1) connected to the bias supply terminal and operative to establish at the output terminal a voltage substantially in a range of voltage levels that are assumed by the bus line during operational use, before the output terminal makes contact to the bus line during live insertion. A circuit module for use in a bus system, which bus system has a data bus line (13), the circuit module comprising a logic bus driver circuit having an output terminal (12) for connection to the data bus line (13); a supply terminal for connection to a supply voltage (GND); drive means (Q2, N1) for connecting the output terminal to the supply terminal for passage of an output current under control of the input signal; characterized, in that the circuit module comprises connector means for applying a bias voltage to a supply terminal and for connecting the circuit module to the bus, the connector means being arranged for ensuring that during live insertion the bias voltage is contacted to the bias supply terminal of the driver circuit before the output terminal makes contact to the bus line, live insertion being physical connection of the circuit module to the data bus line while that data bus line is active, and in that the logic bus driver circuit contains pre-biasing means (26, S3, P1, S1) connected to the bias supply terminal and operative to establish at the output terminal a voltage substantially in a range of voltage levels that are assumed by the bus line during operational use, prior to connection of the output terminal to the bus line during live insertion. A circuit module according to Claim 2, arranged to disable the pre-biasing means upon completion of live insertion. A circuit module according to Claim 2, comprising a further supply terminal (22) for connection to a further supply voltage (Vcc); further drive means (Q1) connected between the further supply terminal and the drive means and operative to supply a further current to a node between the drive means and the further drive means; and wherein: the pre-biasing means is operative to establish said voltage at the output terminal prior to connection of the further supply terminal to the further supply voltage during live insertion. A circuit module according to claim 2, wherein the pre-biasing means comprises an output diode (S1) having a cathode connected to the drive means and having an anode connected to the output terminal. A circuit module according to Claim 5, wherein the pre-biasing means are arranged for applying a reverse bias to the output diode (S1) before physical connection of the output terminal. A circuit module according to claim 3, wherein the pre-biasing means comprises a transistor (P1) having a main current channel coupled between the bias terminal and the drive means and having a control electrode for receiving a turn-off voltage upon completion of the live insertion. A circuit module according to claim 7, comprising: a further supply terminal (22) for connection to a further supply voltage (V cc ); further drive means (Q1) connected between the further supply terminal and the drive means and operative to supply a further current to a node between the drive means and the further drive means; and wherein the transistor (P1) has its main current channel connected in parallel to the further drive means (Q1); the transistor (P1) has its control electrode connected to the further supply terminal.

Inventors: FLETCHER THOMAS DALE, HAHN EMIL NORMAN, FLETCHER, THOMAS DALE, HAHN, EMIL NORMAN
Applicants: KONINKL PHILIPS ELECTRONICS NV, KONINKLIJKE PHILIPS ELECTRONICS N.V.
Application year: 1991
Main classification: H03K19
IPC codes: H03K17, H03K19, H04L25