Thyristor switch gate pulse generator

Abstract: A gate pulse generator for a reactive power compensation device in which a capacitor (2) is connected in series with antiparallel connected thyristors (3U,3X) and which is so constructed that triggering pulses (GP(U), GP(X)) are produced and current (Ic) is passed into said capacitor (2) when both a signal of forward voltage (FV(X), FV(U)) imposed on said thyristors (3U, 3X) and a thyristor conduction period signal that is reset by a phase control signal (PHS(U),PHS(X)) are present. The gate pulse generator (6) includes a means by which conduction period signals associated with thyristors of one polarity are reset during conduction if both a triggering pulse (GP(U), GP(X)) of thyristors of the opposite polarity and a delayed (12U,12X) phase control signal (PHS(U),PHS(V)) associated with the opposite polarity thyristor is present.

Description: The present invention relates to a reactive power compensation device, and more particularly to a thyristor switch gate pulse generator for capacitor load switching in a reactive power compensation device. In the past, the main demand for reactive power compensation devices has been for flicker control of arc furnaces and rolling mills, but in recent years there has also been interest in their applications for changing power system voltages and power surge control, etc. and they are also coming into increased use in transformer substation filter phase advancing equipment. Such equipment uses a combination of TCRs (thyristor controlled reactors) for which normally reactor current is controlled by thyristors or thyristor switches (thyristor switched capacitors; referred to below as TSCs) which have thyristor converters connected in series to capacitors and reactors. Increases in the voltage and capacity of such equipment have involved the use of TCRs constituted by series connections of large numbers of thyristors. Since the load of a TSC is a capacitor, it functions as an on-off switch and a gate pulse generator that switches the thyristors on and off must be able to switch a large number of thyristors on and off all together at high speed. The prior art will now be described with reference to Figs. 3, 4, 5, 6A and 6B. Fig. 3 is a block diagram of a typical TSC. A capacitor 2, a reactor 4 and a thyristor converter 8 constituted by a gate pulse generator 6 which produces gate pulse signals for thyristors 3U and 3X in response to on-off commands from a control unit 7 are connected in series to a TSC transformer 1. Reference numeral 5 designates a circuit for detection of thyristor switch 3U and 3X voltage. Fig. 4 shows the waveforms during normal operation of the various sections of the TSC shown in Fig. 3. VS is the primary voltage of the TSC transformer and IC and VC are the current and voltage of the capacitor constituting the load of the thyristor converter. PHS indicates phase control signals (referred to below as PHS) which are output by control unit 7 and are produced at the peak phase of power supply voltage VS to make the TSC converter excitation rush current minimum. Mostly in recent years, a narrow gate pulse system has been employed for thyristor gate pulse generation. A narrow gate pulse system is one in which triggering signals in the form of one-shot pulses are supplied to thyristors at thyristor triggering times and compared to a conventional broad pulse system. It has the advantage that it is possible to make the power supply circuit of the gate pulse generator smaller and cheaper, etc. Fig. 5 shows a gate pulse generator in a narrow gate pulse system. Reference numerals 8U and 8X designate flip-flop circuits, 9U and 9X AND gates, 10U and 10X one-shot circuits that output set pulse widths, 11U and 11X OR gates, 12 a one-shot circuit, 13 an AND gate, 14 a time delay circuit that outputs a signal after a set delay, 15 an AND gate and 16 a time delay circuit. Flip-flop circuit 8U is set by a PHS(U) pulse output by the control circuit 7. A gate pulse signal GP(U) (referred to as GP below) of set width is output by one-shot circuit 10U and supplied to a gate of a thyristor switch only when the logical product of the forward voltage signal FV(U) of thyristor 3U and the Q output of flip flop 8U at AND gate 9U is "1". Flip-flop circuit 8U that has been set by a PHS(U) pulse is reset by the logical sum output of OR gate 11U. For one input of OR gate 11U, while one-shot circuit 12 is outputting a set pulse width after output of a gate pulse signal GP(X) of opposite-phase thyristor 3X, the logical product taken by AND gate 13 shows that both the forward voltage signal FV(U) of thyristor switch 3U and the F signal FV(X) of thyristor switch 3X (a reverse voltage signal with respect to reactor 4 of thyristor switch 3U) are "0" and this logical product becomes "1" only when time delay circuit 14 causes continuation for more than a set time. In other words, the output of time delay circuit 14 becomes "1" only if a state in which both the forward voltage signal FV(U) and the reverse voltage signal FV(X) are not present in a set time after supply of a gate pulse signal GP(X) to opposite-phase thyristor switch 3X has continued for more than the thyristor turn-off time. Output signals of time delay circuit 16 are supplied to the other input of OR gate 11U. The logical product of GB signals (system stop signals) and reverse voltage signals FV(X) is taken at AND gate 15 and the output of this logical product becomes "1" only after time delay circuit 16 has caused continuation for more than a set time. In other words, the output of time delay circuit 16 becomes "1" when a reverse voltage is imposed for more than the turn-off time after stopping. Gate pulses GP(U) are output while setting of flip-flop circuit 8U by PHS(U) pulses and resetting of 8U by the two types of signals described above are alternately repeated. Generally speaking, there are no problems with the above-described gate pulse generator resetting method as long as there is no need to consider external factors such as system voltage surges, etc. but since in actual fact external factors too must be taken into consideration, a problem as explained in relation to Figs. 6A, 6B and 6C occurs. Fig. 6A is a waveform timing diagram showing waveforms during the TSC operation, and particularly illustrates the TSC converter 1 secondary side voltage VS, capacitor current and voltage IC and VC, the voltage V A-K across opposite electrodes of thyristor switch 3U and the forward side and reverse side gate pulse signals GP(U) and GP(X). The waveforms of Fig. 6A are representative of normal operation of the circuit shown in Fig. 5. Fig. 6B illustrates operation of the circuit shown in Fig. 5 in the case where an intermittence of current occurs. In particular, the particular waveforms shown in Fig. 6B illustrate the case where the capacitor current IC is made intermittent by a system voltage surge. When the capacitor current is intermittent, the AND condition of 9U (or 9X) is established and GPs of both phases are output out of synchronism with the PHS signals and protection against partial commutation failure of thyristor switches 3U and 3X is effected. If, subsequently, the intermittency of the current comes to an end and there is a move to normal conduction, the conditions for the resetting circuits of flip-flops 8U and 8X are established and so the flip-flops of both phases are reset. In Fig. 6B, when U phase conduction ends and there is a move to X phase conduction, the current is intermittent and after a set time both the flip-flops are reset. Action by the resetting circuit of flip-flop 8U is a correct action but since flip-flop 8X is reset soon after own-phase conduction starts, GP output becomes impossible even if the current is intermittent when X phase conduction ends and therefore partial commutation failure is caused and one can anticipate breakdown of thyristor elements. Next described in more detail in relation to the waveform shown in Fig. 6B is a mechanism by which partial commutation failure occurs. In Fig. 6B, two intermittences occur at t2 and t7. Flip-flop 8X is reset at time t5, which is delayed from t2 by the delay time Td. The prior art circuit shown in Fig. 5 has the problem that if a second intermittence occurs at t7 and terminates at t8, GP(X) cannot be generated. GP(X) can be generated when the state of F.F.(U) is "1". As the state of F.F.(U) is "0" at t8 (see Fig. 6B), GP(X) cannot be generated at t8. The thyristor 3X is turned off at t7 because the reverse voltage is applied to the thyristor 3X. The forward voltage is applied to the thyristor 3X at t8, and some elements of the thyristor 3X may turn on and other elements may not turn on. A partial commutation failure may occur due to differences in the characteristics of the thyristor elements when the forward voltage is applied to the thyristor before the turn-off time. Partial commutation failure occurs in the absence of GP(X) due to the characteristics of thyristors connected in series. In series connection, there is a dispersion in turn-off time of the series connected thyristors. Each thyristor has its own turn-off time. In general, if a positive voltage is applied to a thyristor in a short time after turn-off, the thyristor turns on in the absence of a gate pulse. If the positive voltage is applied at the point after- "turn-off time", the thyristors do not turn on in the absence of a gate pulse. For example, if the time of applying a negative voltage T has the value as defined by the following relationship, partial commutation failure occurs: Tmin < T < Tmax, where Tmin refers to the minimum turn-off time of the thyristors and Tmax refers to the maximum turn-off time of the thyristors. In this case, some elements are turned on and the other elements are maintained in the off condition, which results in a partial commutation failure condition. If a small number of thyristors, such as, only one thyristor is in the off condition, the total voltage is then applied to that one thyristor thereby destroying that thyristor. In the circuit of Fig. 5, the delay time Td of the delay timer 14 is set so that Td is greater than the turn-off time of the thyristor. F.F. (U) is reset at t6 by GP(U) after a time delay Td after t2. The possibility of partial commutation failure in the conventional circuit of Fig. 5 is a very great drawback from the point of view of providing a highly reliable reactive power compensation device. SUMMARY OF THE INVENTION Accordingly, one object of this invention is to provide a novel gate generator for a reactive power compensation device which during TSC operation confirms that a satisfactory turn-off time has been ensured and makes it possible to reset only the flip-flop circuits of phases which it is all right to reset and which, by outputting GPs prior to this, forcibly retriggers thyristor elements and so prevents partial commutation failure and breakdown of the thyristor elements. Another object of this invention is to provide a new and improved gate pulse generator as above described, which distinguishes between correctly timed gate pulses and phase voltages (versus intermittences) and gate pulses that are out of synchronism, and which avoids resetting the GP flip-flop of Fig. 5 if the gate pulses are not correctly timed. These and other objects are achieved according to the present invention defined in Claim 1, in particular by providing a new and improved gate pulse generator in a reactive power compensation device in which a capacitor is connected in series with thyristors that are connected in antiparallel and which is so devised that triggering pulses are produced and current is passed into the capacitor when both a signal of forward voltage imposed on the thyristors and a thyristor conduction period signal that is reset by a phase control signal are present, including means for resetting conduction period signals during conduction if both an inverted pair phase phase-control signal and a triggering pulse are present after a set time. Thus, the gate pulse generator of the present invention includes a circuit which, on condition that there is present an own-phase gate pulse that has been emitted within a set time after input of a voltage (PHS) signal from a control unit, resets the flip-flop of the opposite phase. Due to the addition of this circuit, upon the following output of an opposite-phase gate pulse (GP), even if the conventional resetting condition occurs wherein there is an absence both of a GV(U) signal and of an FV(X) signal for more than a set time, flip-flop resetting is effected only if the opposite-phase GP is correctly timed. Thus, since resetting in response to GPs that are out of synchronism with PHSs is eliminated, there is no resetting during own-phase conduction and it is possible to output gate pulses even if intermittent current flows at the end of own-phase conduction and so to prevent partial commutation failure and breakdown of thyristor elements. BRIEF DESCFRIPTION OF THE DRAWINGS A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein: Fig. 1 is a block diagram of one embodiment of the gate pulse generation circuit of the present invention; Figs. 2A, 2B and 2C are waveform diagrams illustrating waveforms produced at various sections of a TSC by a gate pulse generation circuit of the present invention under various operating conditions; Fig. 3 is a circuit diagram of a typical TSC; Fig. 4 is a waveform diagram of waveform at different sections of the TSC for giving an understanding the operation of the TSC; Fig. 5 is a block diagram of a conventional narrow gate pulse type gate pulse generation circuit; and Figs. 6A and 6B are waveform diagrams illustrating waveforms at various sections during various conditions of operation of the TSC driven by gate pulses produced by the circuit of Fig. 5. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings, wherein like reference numerals designate identical or corresponding parts throughout the several views, and more particularly to Figs. 1, 2A, 2B and 2C thereof, the gate pulse generator of the present invention includes essentially identical circuits for generating the U-phase gate pulses GP(U) and X-phase gate pulses GP(X). As is evident from Fig. 2A, during normal operation, signals PHS(U), FV(U), PHS(X), FV(X), and GB are applied to the gate pulse generator circuit. As with the conventional circuit shown in Fig. 5, signals PHS(U) and PHS(X) are produced by control circuit 7 at the maximum forward and reverse voltages of VS, respectively. The signal FV(X) is at a logic level "1" when the signal V A-K shown in Figs. 2A-2C and 6A-6B is negative and a logic level "0" when the signal V A-K is positive. Signal FV(U) is positive when the signal V A-K is positive, and vice versa. The signal V A-K is the voltage across the anode and cathode of the thyristor 3U shown in Figure 3. In Figures 2A-2C, the signal F.F.(U) is the Q output of the flip-flop 8U, whereas the signal F.F.(X) is the Q output of the flip-flop 8X. The signal GB is a system stop signal. In Fig. 1, reference numeral designations 8U and 8X designate flip-flops, 9U, 9X designate AND gates, 10U, 10X designate one-shot circuits, 11U, 11X designate OR gates, 12U, 12X designate one-shot circuits, 13U, 13X designate AND gates, 14U, 14X designate time delay circuits, 15U, 15X designate AND gates, 16U, 16X designate time delay circuits, 17U, 17X designate one-shot circuits, and 18U, 18X designate AND gates. In relation to the conventional circuits shown in Fig. 5, the gate pulse generator of the present invention further includes the provision of one-shot circuit 17U and AND gate 18U for controlling generation of the reset pulse fed back to the flip-flop circuit 8X, and corresponding circuits 17X and 18X for controlling generation of a resetting pulse applied to the flip-flop 8U. During operation, a PHS(X) signal causes the one-shot circuit 17X to output a one-shot pulse of set width and the logical product of this pulse and GP(X) is taken at the output of AND gate 18X. The output signal of AND gate 18X is applied to one-shot circuit 12X which produces a pulse applied to the AND gate 13U, which, if FV(U) and FV(X) are "0", after a time delay produced by time delay circuit 14U is applied via OR gate 11U to the reset terminal of flip-flop 8U. This chain of circuit elements forms a U phase flip-flop resetting circuit, whereas corresponding circuits for the X phase flip-flop 8X, above-identified, comprise an X phase flip-flop resetting circuit. In the gate pulse generator circuit constituted as above-described and shown in Fig. 1, even if an intermittent current occurs because of a system voltage surge, etc., and gate pulses which are out of synchronism with the PHS(U) and PHS(X) signals of the two phases are output, flip-flop resetting of flip-flops 8U and 8X is effected only when correctly timed gate pulses GP(X) and GP(U) are output. It is therefore, according to the invention, possible to prevent the flip-flop resetting during own-phase conduction. Consequently, even if there is an intermittent current at the end of an own-phase conduction, gate pulses that are out of synchronism with the PHS(U) and PHS(X) signals can be output, and partial commutation failure and breakdown of thyristor elements can be prevented. The effect of the present invention is illustrated with respect to the timing waveform shown in Fig. 2A-2C. Fig. 2A shows a normal operation of the circuit shown in Fig. 1. Fig. 2B shows the case where a current intermittence occurs. Fig. 2C is an enlarged view of a portion of Fig. 2B where a current intermittence occurs. In Fig. 2C, current intermittences occur at t2 and t7. GP(U) is generated at t2, and GP(X) is generated at t3 due to the first intermittence. GP(U) cannot be generated at t7 because the flip-flop F.F.(U) (i.e., flip-flop 8U) is reset at t6. This presents no problem because none of the thyristor elements in the thyristor U may turn on. In this instance, the reverse voltage has been applied over enough time. GP(X) can be generated at t8 because F.F.(U) has not yet reset at t8. Consequently, even if there is an intermittent current at the end of own-phase conduction, gate pulses that are out of synchronism with the PHS signals can be output and partial commutation failure and breakdown of thyristor elements can be prevented. Advantageously, the present invention causes no drawbacks, since the additional circuits which prevent partial commutation failure do not disturb the conventional reset circuits and functions typically performed. According to the present invention, own-phase flip-flop resetting is effected if a correctly timed opposite-phase gate pulse is output. Thus, in the present invention, even if a current is intermittent and gate pulses that are out of synchronism with the PHS signals in the two phases are output, since flip-flop resetting is effected only if gate pulses are correctly timed and even if the current is subsequently intermittent, it is possible to output gate pulses that are out of synchronism with the PHS signals. The present invention therefore makes it possible to provide a highly reliable static type reactive power compensation device in which thyristor elements are protected from partial commutation failure and breakdown. Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention by be practiced otherwise than as specifically described herein.

Claims: A gate pulse generator for applying gate pulse signals to a pair of anti-parallel connected first (3U) and second (3X) thyristors, comprising: logic circuit means including respective first and second S-R flip-flops (8U, 8X) which receive the phase control signals PHS(U), PHS(X) to produce first and second gate pulse signals (GP(U), GP(X) which are applied respectively to said thyristors, when a forward voltage is applied across the anode and cathode of said first and second thyristors, respectively; characterised by: means (17X, 18X) for resetting the first flip-flop 8(U) only if a gate pulse signal GP(X) applied to said second thyristor (3X) is present a predetermined time after a forward voltage FV(X) is present across the anode-cathode of said second thyristor; and means (17U, 18U) for resetting the second flip-flop 8(X) only if a gate pulse signal GP(U) applied to said first thyristor is present a predetermined time after a forward voltage FV(U) is present across the anode-cathode of said first thyristor. A reactive power device in which a capacitor is connected in series with a pair of anti-parallel connected thyristors, having a gate pulse generator for said thyristors as claimed in claim 1.

Inventors: OGIWARA HIDESHI, OGIWARA, HIDESHI, OGIWARA, HIDESHI, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: H03K17
IPC codes: H03K17, G05F1, H02J3