Switching apparatus with cascaded switch sections

Abstract: A diode (14) is connected at a first electrode (16) thereof to a source of input signal (Si) to be switched via a capacitor (20) and is connected at a second electrode (18) thereof via an output circuit (30,40) to an output terminal (12). A bias control circuit (62,64,60), coupled to the diode (14), provides a first operating mode in which the diode (14) is forward biased for coupling the input signal (Si) to the output terminal (12) via the output circuit (30,40) and provides a second operating mode in which the first electrode (16) of the diode (14) is DC isolated so that the diode (14) rectifies the AC component of the input signal (Si) and in so doing generates a reverse bias for self-biasing the diode (14) to a non-conductive condition.

Description: Field of the Invention This invention relates to signal switching apparatus and particularly to apparatus of the kind employing cascaded switch sections for enhancing the off-state attenuation of high frequency signal components being switched. An attenuation circuit comprising a diode having a first electrode connected by a DC blocking capacitor to a source of input signal and having a second electrode coupled via an output circuit to an output terminal for providing an attenuated output signal and comprising a bias control circuit for controlling conduction of said diode is disclosed in J. Markus: "Modern electronic circuits reference manual", 1980, Mc Graw Hill, New York, US; page 30. In DE-A-3412 863, Fig. 5, a nonadditive mixer for combining the outputs of two switching circuits is disclosed. Background of the invention The attenuation provided by a switch when the switch is turned off ("off-state" attenuation) is an important figure of merit for a switching circuit and particularly so in applications where the signal to be switched contains significant amounts of high frequency energy. As an example, when switching between a number of video input signals for television apparatus (e.g., recorders, receivers,, monitors, effects generators, etc.) it is important that the video input signal that is not selected be attenuated below a minimum level to avoid interference with the selected video input signal. Generally speaking, it would be desirable to attenuate the unselected video signal by at least 60 dB and preferably more. Such levels of attenuation at video frequencies are not easily achieved with conventional integrated circuit switches due, for example, to the presence of parasitic capacitances. For this reason various methods have been proposed for improving the off-state attenuation of integrated circuit switches. One such technique, described in the following two examples, is to connect switches in cascade so that their off-state attenuations are additive. A first example of switch cascading for improved off-state attenuation is described by Nigborowicz et al. in U.S. Pat. No. 4,521,810 entitled VIDEO SOURCE SELECTOR which issued 4 June, 1985. In a specific embodiment of this switching circuit, an emitter follower is connected in cascade with an integrated circuit switch of the CMOS type and a clamping transistor is connected to the base of the emitter follower transistor and controlled to disable the emitter follower when the CMOS switch is opened. By this means the video signal being switched is attenuated both by the disabled emitter follower circuit and by the CMOS switch when the switch is turned off. A second example of cascaded switching circuits is described by Deiss in U.S. Pat. No. 4,638, 181 entitled SIGNAL SOURCE SELECTOR which issued 20 January 1987. In a specific embodiment disclosed in the Deiss patent a diode switch is connected in series with a CMOS integrated circuit switch. The circuit includes a bias circuit that sends turn-on current through the CMOS switch to the diode switch when the CMOS switch is closed. Another bias circuit applies reverse bias to the diode switch when the CMOS switch is opened. For maximum off-state attenuation Deiss recommends the use of a diode of the p-i-n type as such diodes exhibit a very low junction capacitance and thus minimize parasitic coupling when the diode is off. An example of PIN diode switch is described by M. Goldstein in an article entitled "Improved Receiver Selectivity and Gain Control" published November 1977 in Ham Radio magazine at pages 71-73. In this arrangement PIN diodes provide RF signal attenuation. However, this system is relatively complex requiring multiple diodes (3) and also requires a dual-polarity bias signal source for applying a positive voltage (+12V) to a diode network for opening an RF signal path and for applying a negative voltage (-12V) to the network for closing the RF signal path. An example of a diode bridge switching network used as a UHF mixer is described by Vander Vorst and Laloux in "Ultrahigh Frequencies (UHF) Theory, Practice and Measurement" published in 1982 by Catholic University of Louvain, UHF and Telecommunications Laboratory. This arrangement provides high speed switching of an RF signal but it is relatively complex requiring four diodes and bias for the diodes requires a "floating" AC generator with one output thereof connected to the diode anodes and the other output thereof connected to the diode cathodes. It is one object of the present invention to simplify biasing of a diode switch. In principle, in the present invention, simplification is achieved by biasing the diode in such a manner that the diode generates its own turn-off bias. A switching circuit embodying the invention comprises a diode (14) having a first electrode (16) connected by a DC blocking capacitor (20) to a source of an input signal (Si) to be switched and having a second electrode (18) coupled via an output circuit (30, 40) to an output terminal (12) for providing a switched output signal. A bias control circuit (62, 64, 60), coupled to the first (16) and second (18) electrodes of the diode (14) controls conduction of the diode, the bias control circuit comprising a first resistor (62) coupled between the second electrode (18) of the diode (14) and a first source (25) of DC potential (+Vs) and a second resistor in series with a switch (60) coupled between the first electrode (16) of the diode (14) and a second source of DC potential (66). The bias control circuit has a first operating mode when the switch is closed for forward biasing the diode (14) and the transistor via the first resistor (62) and the switch (60) thereby enabling the diode and the transistor to couple the input signal (Si) to the output terminal (12). The bias control circuit has a second operating mode, when the switch is open, for providing DC isolation of the first electrode (16) of the diode so that the diode (14) rectifies the input signal (Si) applied thereto via the capacitor (20) for producing a reverse bias voltage for the diode (14) and the transistor to thereby decouple the input signal (Si) from the output terminal (12). The output circuit (30, 40) includes a transistor (Q1) having an input electrode (base) connected to the second electrode (18) of the diode (14) for receiving DC bias therefrom. In accordance with a further aspect of the invention the output circuit comprises a non-additive mixer. In accordance with yet another aspect of the invention the output circuit includes an amplifier and a non-additive mixer. Brief Description of the Drawing The invention is illustrated in the accompanying drawing wherein like elements are denoted by like reference designators and in which: FIGURE 1 is a circuit diagram of a switch embodying the invention; and FIGURE 2 is a block diagram, partially in schematic form, of a color television receiver embodying the invention including exemplary element values for the elements of the switch of FIGURE 1 and including further features of the switch for the specific application shown and described. Detailed Description The switching circuit of FIGURE 1 includes an input terminal 10 for receiving an input signal Si to be switched and an output terminal 12 for providing a switched output signal. A diode 14 is provided having a first electrode 16 (cathode) coupled via a DC blocking capacitor 20 to the signal input terminal 10 and having a second electrode 18 (anode) coupled via an output circuit (30 and 40) to the output terminal 12. The output circuit comprises a cascade connection of an amplifier 30 and a non-additive mixer 40. Amplifier 30 comprises an NPN transistor Q1 having a base electrode connected to the second electrode (anode) 18 of diode 14, having an emitter electrode coupled to a source of reference potential (ground) via an emitter resistor 32 and having a collector electrode coupled to a supply voltage input terminal 25 via a collector load resistor 34. A positive supply voltage Vs is applied to supply terminal 25. The non-additive mixer 40 comprises a pair of NPN transistors Q2 and Q3 having the collector electrodes thereof connected to the supply terminal 25 and having the emitter electrodes thereof connected to the output terminal 12 and coupled to ground via a current source 42. The current source may be implemented as a resistor or it may be a transistor biased to operate as a current source. The base electrode 44 of transistor Q2 serves as one input of the non-additive mixer 40 and is connected to the output of amplifier 30 at the collector of transistor Q1. The base electrode 46 of transistor Q3 serves as a second input of the non-additive mixer 40 and is connected to an input terminal 50. In this example of the invention a DC bias voltage Vb is applied to terminal 50. In a further example discussed later a second input signal to be switched is applied to input terminal 50. The remaining elements of FIGURE 1 comprise a bias control circuit for diode 14 for providing a first operating mode in which diode 14 is forward biased for coupling the input signal Si to output terminal 12 via amplifier 30 and non-additive mixer 40 and for providing a second operating mode in which the first electrode (cathode) 16 of diode 14 is DC isolated so that the diode rectifies the AC component of the input signal Si supplied via DC blocking capacitor 20 and in so doing generates a reverse bias voltage which "self-biases" diode 14 to an OFF (non-conductive) state. As will be explained, amplifier 30 and non-additive mixer 40 provide further attenuation of the input signal in response to the self-biasing conditions of diode 14. The bias control circuit comprises a first resistor 62 coupled between the supply terminal 25 and the second electrode (anode) 18 of diode 14 and a second resistor 64 coupled in series with a switch 60 between the first electrode (cathode) 16 and a source of reference potential shown here as being a ground point 66. Operation of the switching circuit of FIGURE 1 will first be described for the case where the control switch 60 is closed. For this condition a DC path exists between supply terminal 25 and ground 66 through resistors 62, diode 14, resistor 64 and switch 60. Current flow in this path has two effects. Firstly, it forward biases diode 14 and so diode 14 couples the AC component of the input signal Si to the base of transistor Q1 of amplifier 30. Secondly, resistors 62 and 64 and diode 14 form a potential divider which provides temperature compensated DC bias to the base of transistor Q1 which biases the transistor for linear operation. The temperature compensation effect results because voltage changes of the base-emitter junctions voltage Vbe of transistor Q1 are accompanied by similar changes of voltage across the P-N junction of diode 14. Accordingly, in this mode of operation diode 14 serves the dual functions of (1) providing coupling of the AC component of input signal Si and (2) providing Vbe temperature compensation of transistor Q1 in amplifier 30. Amplifier 30 amplifies the AC component of the input signal coupled via diode 14. The gain of amplifier 30 is given, to a good approximation, by the ratio of the collector and emitter load resistors 34 and 32, respectively. The resistors, in conjunction with the DC bias applied to the base of transistor Q1 also determine the quiescent collector voltage which is a factor to be considered in the operation of the following non-additive mixer stage 40. A preferred bias condition for amplifier 30 is one which provides an output signal voltage that is within a range defined by the supply voltage Vs applied to terminal 25 and the bias voltage Vb applied to terminal 50. Illustratively, one may select DC bias for amplifier 30 such that the output voltage is about three quarters of the supply voltage Vs and the bias voltage Vb may be selected to be about one-half of the supply voltage Vs. Of importance to the present invention is that the bias voltage Vb for the non-additive mixer 40 is less than the supply voltage Vs for amplifier 30 and that amplifier 30 is biased to a quiescent level between Vs and Vb. As an example, for a 12 volt supply amplifier 30 may be biased to provide a quiescent output voltage of 9 volts and the bias Vb applied to non-additive mixer 40 may be 6 volts. The amplified signal at the output (collector Q1) of amplifier 30 is applied to transistor Q2 of non-additive mixer 40. Transistor Q3, being DC biased at a lower voltage than transistor Q2 as previously explained, is therefore turned off and transistor Q2 and current source 42 function as an emitter follower to couple the amplified output signal to output terminal 12. Briefly summarizing the foregoing, closure of switch 60 forward biases diode 14 which then provides the dual functions of (1) coupling the AC component of signal Si to amplifier 30 and (2) generating a temperature compensated DC bias voltage for amplifier 30. Amplifier 30 amplifies the coupled signal and provides an output voltage at a DC level which reverse biases transistor Q3 of the non-additive mixer 40 and is coupled to the output terminal 12 via transistor Q2 operating as an emitter follower. Operation of the switching current of FIGURE 1 will now be discussed for the case where control switch 60 is OPEN. For this condition there is no DC path from the first electrode (cathode) 16 of diode 14 to any point in the switching circuit. The DC isolation of the first electrode (cathode) 16 of diode 14 has a number of significant effects on the circuit operation previously described. A first effect is that his condition enables diode 14 to rectify the AC component of input signal Si and store the rectified voltage on capacitor 20. The capacitor 20 is charged by current flow through resistors 62 and diode 14 when input signal excursions are lower than the anode voltage of diode 14 but there is no discharge path and so the accumulated charge reverse biases diode 14 thereby attenuating the input signal. A second effect of opening switch 60 is that resistors 62 and 64 no longer bias transistor Q1 of amplifier 30 for linear operation. Instead current flow through resistor 62 is completely diverted to the base of transistor Q1 and this current effectively overdrives transistor Q1 in to a non-linear mode in which the transistor is at or at least near saturation. Full saturation is not essential. What is important to the present invention is that the DC bias for transistor Q1 be changed only enough to decrease the collector voltage to a level sufficient to reverse bias transistor Q2 in non-additive mixer 40. This level is any voltage less than the DC bias voltage Vb applied to terminal 50. When this occurs transistor Q2 is reverse biased and transistor Q3 operates in conjunction with current source 42 as an emitter follower to couple the bias signal Vb to output terminal 12. Accordingly, in this mode (switch 60 open) the input signal Si is attenuated by diode 14 (which generates its on turn-off voltage by rectifying the input signal) and by amplifier 30 and by non-additive mixer 40. FIGURE 2 illustrates an application of the switching circuit of FIGURE 1 for selectively switching two chrominance input signals in a color television receiver. This FIGURE also shows exemplary element values and voltages. The color television receiver of FIGURE 2 includes a tuner and IF processing unit 200 of conventional design having an input terminal 210 for receiving an RF modulated video input signal and an output for providing a baseband demodulated video output signal. Other baseband composite video input signals are provided by auxiliary input connectors 212 and 214. An SVHS (super VHS) input connector 216 is provided for receiving a baseband video input signal of a separated luminance (SVHS-Y) and chrominance (SVHS-C) format. A four position selector switch 220 is provided for selectively coupling the signals S1, AUX-1, AUX-2 and SVHS-Y to the input 222 of a comb filter 230. Channel selection for tuner 200 and signal selection by switch 220 is controlled by a control unit 240. The comb filter 230 has luminance (Y) and chrominance (C) outputs coupled to a video processing and display unit 250 of conventional design for processing and displaying color video images. The comb filter 230 is of a type having an emitter follower output stage for the chrominance signal. This stage is represented in comb filter 230 by transistor Q3 and current source 42 with the base of transistor Q3 biased at about 6 volts. It will be noted that these elements are identical to those used in non-additive mixer 40. Advantageously, the presence of an emitter follower in comb filter 230 eliminates the need for this element in the SVHS chrominance switch 280 as will now be described. The SVHS chrominance switch 280 corresponds to the switch of FIGURE 1 with the following modifications. Firstly, an input signal terminating resistor 282 is provided between input terminal 10 and ground. This resistor terminates the SVHS chrominance signal provided by SVHS connector 216 in a standard characteristic impedance (75 Ohms). Electro-static discharge (ESD) protection is provided by an ESD protection resistor 284 connected in series with capacitor 20. The resistor 64 of FIGURES 1 is implemented by a series connection of a pair of 2.7K-Ohm resistors having the common connection thereof by-passed to ground by a capacitor (470 pico-Farads). This network functions as a low pass filter which provides the dual functions of (1) suppressing noise from switch 60 from entering the chrominance signal processing channel and (2) suppressing chrominance signals from entering switch 60 and thus interfering with other signals which may be switched by switch 60. Another change in this embodiment is the inclusion of a bare isolation resistor of 470 Ohms between the base of transistor Q1 and the anode of diode 14 for isolating parasitic capacitances associated with transistor Q1. Switch 60 is controlled by controller 240. In operation control unit 240 selects signals for display by controlling switches 220 and 60. For example, when selecting video signals S1, AUX-1 or AUX-2 control unit 240 sends corresponding selection signals to switch 220 and simultaneously sends an inhibit signal to switch 60 which opens switch 60. This disables signal flow in the SVHS chrominance signal path as previously explained. Briefly reviewed, in this mode diode self-biases itself to an off state by rectifying the SVHS chrominance signal (if any is present), amplifier 30 is driven to saturation (or near saturation) and the non-additive mixer 40 selects the comb filter output signal. When the SVHS signal source 216 is selected by control unit 240 the switch 220 couples the SVHS luminance signal to processor 250 and the SVHS chrominance signal is coupled to processor 250 via diode 14, amplifier 30 and non-additive mixer 40 as previously explained in the description of FIGURE 1.

Claims: A switching circuit, comprising: a diode (14) having a first electrode (16) connected by a DC blocking capacitor (20) to a source of an input signal (Si) to be switched and having a second electrode (18) coupled via an output circuit (30, 40) to an output terminal (12) for providing a switched output signal; a bias control circuit (62, 64, 60) coupled to the first (16) and second (18) electrodes of said diode (14) for controlling conduction of said diode, characterized by said output circuit (30, 40) including a transistor (Q1) having an input base electrode connected to said second electrode (18) of said diode (14) for receiving DC bias therefrom; said bias control circuit comprising a first resistor (62) coupled between said second electrode (18) of said diode (14) and a first source (25) of DC potential (+Vs) and a second resistor (64) in series with a switch (60) coupled between said first electrode (16) of said diode (14) and a second source of DC potential (66); said bias control circuit having a first operating mode when said switch is closed for forward biasing said diode (14) and said transistor (Q1) via said first resistor (62) and said switch (60) thereby enabling said diode and said transistor to couple said input signal (Si) to said output terminal (12); said bias control circuit having a second operating mode when said switch is open for providing DC isolation of said first electrode (16) of said diode (14) so that said diode (14) rectifies said input signal (Si) applied thereto via said capacitor (20) for producing a reverse bias voltage for said diode (14) and said transistor (Q1) to thereby decouple said input signal (Si) from said output terminal (12). A switching circuit as recited in Claim 1 characterized in that said output circuit (30, 40) includes a non-additive mixer (40) connected to an output electrode of said transistor (Q1). A switching circuit as recited in Claim 1 characterized in that said output circuit (30, 40) includes a cascade connection, in the order named, of said transistor (Q1) and a non-additive mixer (40). A switching circuit as recited in Claim 3 characterized in that said non-additive mixer (40) includes an input (44) connected to an output electrode of said transistor (Q1) and a further input (46) to which a bias voltage (Vb) is applied that is less than a supply voltage (Vs) applied to said transistor (Q1) and said transistor is biased to provide a quiescent output voltage intermediate the values of said supply voltage (Vs) and said bias voltage (Vb). A switching circuit as recited in Claim 1 characterized in that said diode (14) in said first operating mode provides temperature compensated DC bias for said transistor in said output circuit (30, 40).

Inventors: SENDELWECK GENE KARL, SENDELWECK, GENE KARL
Applicants: THOMSON CONSUMER ELECTRONICS, THOMSON CONSUMER ELECTRONICS, INC.
Application year: 1991
Main classification: H03K17
IPC codes: H03K17, H04N5