Method of manufacturing a semiconductor memory device

Abstract: A method of producing a highly reliable mask ROM and the product produced by the method are disclosed. The method is characterized by comprising the steps of forming low doped source-drains to relax the electric field between the gate electrode and drain, thereby suppressing the creation of hot carriers, and of depositing dielectrics of a predetermined thickness between neighbouring gates to control the projection range of impurities implanted into the source-drain region of the bit into which data is to be written, the thickness of the dielectrics being determined such that the projection range does not exceed the junction depth of the source-drain in order to preclude the formation of parasitically doped layers which cause punch-through across an unwritten transistor.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates in general to a method of manufacturing a semiconductor memory and in particular to a method of manufacturing a large-capacity NAND-type mask ROM with submicrometer gates. Description of the Related Art A method of producing a NAND-type mask ROM is presented in Japanese Patent Laid-open No. 62-92362, in which data programming is performed through ion implantation. The method as a representative case of the prior art will be explained with reference to Figs. 1 through 3 of the accompanying drawings. As shown in Fig. 1, a field oxide 2 is first formed on a P-type silicon substrate 1 by the LOCOS method, and then a gate oxide 3 is formed on the substrate. Next, a polysilicon is deposited over the entire surface of the layers formed by the preceding steps and selectively etched to form polysilicon gate electrodes 4a through 4e, using a photoresist as a mask. N + -type diffusion layers 9a through 9g are then formed in the P-type silicon substrate 1 by ion implantation using gate electrodes 4a through 4e as masks. Next, photoresist 10 is formed in the manner shown in Fig. 2, in which openings 11 are provided above only each transistor or bit to which the data "ON" is to be written. These bits are hereafter referred to as data bits. Using photoresist 10 as a mask, phosphorus ions with an incident energy high enough to penetrate gate electrodes 4b and 4d are implanted into the silicon substrate, thereby forming N - doped channel layers 12b and 12e under the gate electrodes 4b and 4d, respectively. In this way, depletion-type MOSFETs are formed in the data bits which correspond to data-storing bits. Next, as illustrated in Fig. 3, an interlayer dielectric 13 of PSG (Phospho-Silicate Glass) is formed over the existing surface, and a digit line contact 14 is opened above the N + -type diffusion layer 9a through interlayer dielectric 13. Finally, a digit line 15 of aluminum is deposited both on the interlayer dielectric 13 and in the digit line contact 14, and a NAND-type mask ROM device provided with N + -type single-drain MOSFETs in its memory cells and its peripheral circuits is obtained. In the prior art above, when "ON" data is written by implanting the phosphorus ions through the gate electrodes to form the N - doped channel layers 12b, 12e N - doped layers 12a, 12c, 12d and 12f are also formed parasitically in the silicon substrate 1 underneath the source-drain diffusion layers, as shown in Fig. 2. These parasitically doped layers (hereafter, referred to as parasitic layers) allow junction depth X j of the sources and drains to be larger. As is well-known in the art, a MOSFET normally operates in response to a gate voltage, provided that the channel length L is sufficiently longer than the sum of the widths of the depletion layers in the source and drain junctions. However, when the scale of the device is reduced to the order of submicrometers, making the channel length L a critical value L min or less, punch-through tends to take place. According to an empirical law in the field of semiconductor devices, the critical channel length L min increases in proportion to (X j ) 1/3 . Accordingly, punch-through tends to occur as the junction depth X j increases, even if the actual channel length L remains unchanged. As a result, punch-through takes place between parasitic layers 12c and 12d, i.e. across the channel region of the unwritten bit or "OFF" bit (9c, 9d, 4c), thereby generating a current path irresponsive to a control signal applied to gate electrode 4c. This leads to the problem that "OFF" data in the unwritten bit (9c, 9d, 4c) cannot be read. Another problem arises from the fact that the foregoing semiconductor memory consists of N + -type single drain transistors. As is well-known, when the channel length L is not sufficiently long in comparison with critical length L min , as is the case in a so-called submicrometer-scale device, hot carriers caused by a strong electric field between the drain and gate tend to be created between the gate electrode and drain. This creation of hot carrier brings about detrimental unstable behavior of the transistor which results in unreliable performance of the semiconductor device. This is the case in the peripheral circuit composed of an N + -type single drain transistor (9f, 9g, 4e) shown in Fig. 3. This tendency becomes more prominent, with higher doping levels in the N + diffusion layers of the source and drain. Accordingly, when an N + -type single-drain MOSFET is employed, the reliability of the device is a problem unless the power supply voltage is lowered according to pattern scaling. Japanese patent application No. 60-241259, as set out in Patent Abstracts of Japan, vol. 10, No. 99, (E-396) [2156], describes a method for manufacturing a ROM which reduces the formation of parasitically-doped layers. In this method, once the gate electrode of a MOSFET has been formed on a gate oxide film deposited on a P-type silicon substrate, and source and drain regions have been formed by ion implantation, the thickness of the gate oxide film to the sides of the gate is increased by exposure to an oxidising atmosphere. A photo-resist film is then formed over the surface of the device, covering both the gate and the gate oxide film, and is formed into a mask by removal of the portion of the photo-resist film over the gate area. Ions are then implanted through the gate oxide film to form an N-type layer of low concentration in the substrate. Japanese patent application JP 61-218165, as set out in Patent Abstracts of Japan, vol. 11 No. 59, (E-482) [2506], describes a method for manufacturing a semiconductor memory in which a memory cell is formed as a single-drain cell and a peripheral circuit adjacent to it is formed as a double-drain structure. In order to prevent damage due to ion-implantation, the source and drain regions of the single-drain cell are doped at a lower density than those of the adjacent double-drain structure. SUMMARY OF THE INVENTION The invention provides a method for manufacturing a semiconductor memory device as defined in the appendant independent claim. Preferred features of the invention are defined in dependent sub-claims. In a preferred embodiment, the invention may provide a method for manufacturing a semiconductor memory in which no parasitic doped layer is formed when data is written. Advantageously, the invention may provide a method for manufacturing a semiconductor memory comprising a single-drain MOSFET with a submicrometre gate in which hot carriers are less likely to be created than in conventional single-drain MOSFETS. The invention may also advantageously provide a method for manufacturing a semiconductor memory including a memory region and a highly reliable peripheral circuit composed of submicrometre-gate MOSFETs through common manufacturing steps in parallel. In a further preferred embodiment, the invention may provide a highly reliable semiconductor memory composed of single drain MOSFETs with submicrometre gates, in which hot carrier creation is substantially minimised and punch-through is substantially eliminated. The method of the invention comprises the steps of: (a) forming a field oxide on a major surface of a semiconductor substrate of a first conductivity type; (b) forming a first dielectric as a gate dielectric; (c) forming gate electrodes on the first dielectric wherein in the memory region a plurality of the gate electrodes are formed so that the ratio of the height of the gate electrodes to the distance between neighbouring gate electrodes equals or exceeds 1, and in the peripheral circuit region at least one gate electrode is formed; (d) implanting low-concentration impurity ions of a second conductivity type into the semiconductor substrate using the gate electrodes as masks to form lightly-doped source-drain diffusion regions of the memory transistors, and lightly-doped source-drain regions of the LDD transistor in the peripheral circuit region; (e) forming on the first dielectric between the gate electrodes in the memory region a second dielectric of a thickness 1/2 or more of the distance between the neighbouring gate electrodes and, at the same time, forming the second dielectric on the sides of each gate electrode in the peripheral circuit region, and etching back the second dielectric to leave a predetermined thickness of the second dielectric unetched on the first dielectric between the gate electrodes in the memory region and to leave at least a portion of the second dielectric on the sides of each gate electrode in the peripheral circuit region; (f) implanting high-concentration impurity ions of the second conductivity type into the semiconductor substrate using the gate electrodes and the second dielectric as masks to form highly-doped source-drain regions of the second conductivity type of the LDD transistor in the peripheral circuit region; (g) coating a photoresist over the existing surface, the photoresist having an opening above selected memory transistors; and (h) implanting impurity ions of the second conductivity type through the gate electrodes and the first and second dielectric into the semiconductor substrate using the photoresist as a mask so as to form a lightly doped channel region of the second conductivity type in each of the selected memory transistors. According to this method, the projection range of the impurity ions implanted into the source-drain region through the second dielectric in step (f) can be varied depending on the predetermined thickness of the second dielectric. The larger the predetermined thickness of the second dielectric the smaller the projection range into the substrate of ions of a given type and energy implanted during step (h). Thus, for implantation with ions of a given type and energy the dimensions of any parasitically-doped layers can be reduced by the method of the invention and so punch-through in the manufactured memory device can be advantageously reduced. Accordingly, in order to eliminate the parasitically-doped layers and minimise punch-through, it is preferable to select the predetermined thickness so that the projection range does not exceed the junction depth of the source-drain. The reasons why the ratio of the height of the gate electrode to the distance between the neighbouring gate electrodes (hereafter the ratio is referred to as an aspect ratio) is selected to be equal to or more than 1 and why the second dielectric is deposited to a thickness 1/2 or more the distance between the two gate electrodes are as follows: As the dielectric is deposited, the thickness of the deposited dielectric on the confronting sides of neighbouring gate electrodes increases, reducing the distance between dielectrics on the gate electrodes. When the thickness of the deposited dielectric on the confronting sides of the neighbouring gate electrodes reaches 1/2 of the distance between the gate electrodes, the dielectrics come into contact with each other, thereby completely filling the gap between the two gate electrodes. Generally, if the aspect ratio is sufficiently larger than 1, then the top surface of the dielectric at the time when the gap is completely filled becomes substantially parallel to the surface of the semiconductor substrate. The surface of the dielectric subsequently advances in a direction normal to the surface of the semiconductor substrate, i.e., upwardly. When the dielectric is etched back after the preceding deposition step, its surface is uniformly etched back downwardly. As a result, a uniform thickness of the dielectric can be left on the gate dielectric. In contrast, as the aspect ratio decreases from 1, the top surface of the deposit of the dielectric in an intermediate region between the neighbouring gate electrodes tends to be lower than the top surface of the deposit of the dielectric on the gate electrodes when the gap between the gate electrodes is completely filled. If such an uneven surface of the dielectric is then uniformly etched back, the thicknesses of the dielectrics in the intermediate region between the gate electrodes and in the end region near the confronting sides of the gate electrodes will be different. Consequently, when an implanting ion beam bombards the semiconductor substrate through the dielectric to write data, the projection range in the source-drain region immediately beneath the intermediate region between the gate electrodes will differ from the projection range in the source-drain regions immediately beneath the end region. As a result, the doped layers in the source-drain regions will not be of uniform depth. To avoid this drawback, an aspect ratio of 1 or more is selected. In order to reduce the formation of hot-carriers, particularly in a single-drain MOSFET, it is preferable to perform ion implantation in step (c) so as to form N - type diffusion layers of source-drains. By using a low-doped drain of this type, the electric field between the gate and drain can be relaxed, and consequently, the creation of hot carriers suppressed and high reliability of the semiconductor memory attained even if the gate length of the memory is of the order of submicrometres. In the resulting single-drain MOSFET this provides the advantage that even if circuit components are reduced in size according to device scaling, it is not necessary to vary the power supply voltage for the semiconductor memory in relation to the scaling. In addition, it should be noted that an N-type transistor is preferable to a P-type transistor on account of its high-speed operation. Advantageously, the method of the invention allows the memory region and the peripheral circuit region to be fabricated during the same steps. The source-drains in the memory and the lightly doped layers for an LDD transistor for relaxing the strong electric field near the drain junction are formed in step (d) in parallel and the second dielectric for reducing or preventing formation of parasitically doped layers in the memory region, i.e. filling layers, and the second dielectrics for defining doping regions of the highly doped source-drains through self-alignment in the peripheral circuit region i.e. side wall dielectrics, are both formed in step (e). In this way an LDD transistor which is free from hot carrier creation even when the gate length is of the order of submicrometres may advantageously be produced together with the semiconductor memory. The above and other objects, features, and advantages of the present invention will become apparent from the following description referring to the accompanying drawings which illustrate an example of a preferred embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1 through 3 are cross-sectional views showing the conventional successive steps of manufacturing a semiconductor memory device; and Figs. 4 through 7 are cross-sectional views showing the successive steps of manufacturing a semiconductor memory device according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A method of manufacturing a semiconductor memory according to the present invention will be described below with reference to Figs. 4 through 7. As shown in Fig. 4, a field oxide 2 having a thickness ranging from 600 to 800 nm is first formed on a P-type silicon substrate 1 by the LOCOS method and then a gate oxide 3 having a thickness ranging from 15 to 30 nm is formed thereon. Next, a polysilicon layer is deposited on the entire existing surface, and selectively etched to form gate electrodes 4a through 4g, using a photoresist as a mask. In this step, the gate length i.e., the length of each gate electrode, is selected to be of submicrometer size in the range from 0.4 to 0.8 µm, and an aspect ratio, i.e., the ratio of the thickness of the polysilicon, or the height of the gate electrodes to the distance between neighbouring gate electrodes, is selected to be 1 or more for the reasons described above. Using the gate electrodes 4a through 4g as masks, phosphorus ions are then implanted into the P-type silicon substrate 1 at a dose ranging from 1 to 3 x 10 13 cm -2 at an acceleration voltage ranging from 30 to 50 KeV. In this manner, N - -type single-drain MOSFETs having N - -type diffusion layers 5a through 5g are formed in the memory region, and N - -type diffusion layers 5h, 5i for relaxing the electric field between the gate and drain are formed in the peripheral circuit. Next, a dielectric 6 having a thickness 1/2 or more the distance between neighbouring gate electrodes is deposited on the existing surface, and heat-treated, thus filing the spaces between the gate electrodes in the memory region with the dielectric. As shown in Fig. 5, the dielectric 6 is then etched back to leave filling layers 8a through 8e at a predetermined thickness along with side wall dielectrics 7a through 7d. The thickness D 0 of the filling layers 8a through 8e is selected so that the projection range R pl of the implanting ion beam incident for writing data, as measured from the substrate surface, which is scattered forward through the filling layers 8a through 8d into the source-drain regions (the source-drain of the data bits) underneath the filling layers is equal to the source-drain junction depth X j . After the filling layers 8a through 8e and the side wall dielectrics 7a through 7d have been formed, arsenic ions are implanted into the silicon substrate using the gate electrode, the filling layers and the side wall dielectrics as masks, thereby forming N + -type doped layers 19a through 19d which are self-aligned with the side wall dielectrics. In this way, an LDD transistor is formed in the peripheral circuit region. A photoresist 10 having openings 11a and 11b above only the transistors in which data "ON" are to be written is then formed, as shown in Fig. 6. Using the photoresist 10 as as mask, phosphorus ions are implanted into the silicon substrate 1 at an incident energy high enough to penetrate the gate electrodes 4b and 4d, thereby forming N - type channel doped layers 12a and 12b underneath the gate electrodes 4b and 4d, in which the data "ON" is written. The incident energy of the phosphorus ion beam is determined so that projection range R p2 , the projection range of the phorphus ion beam incident for writing data which is scattered forward through the gate electrodes into the channel region underneath the gate electrodes 4b and 4d, is also equal to the source-drain junction depth X j . In this way, a channel doped layer and drain-source diffusion layers of the same profile are formed without forming any parasitic layer, thereby preventing the generation of punch-through across an "OFF" bit between the "ON" bits. Next, as shown in Fig. 7, an interlayer dielectric 13 of PSG is formed and a digit line contact 14 is opened in the interlayer dielectric 13 on the N + -type diffusion layer 9a or the N - -type diffusion layer 5a. Subsequently, a digit line 15 of aluminum is deposited on the interlayer dielectric 13 and in the digit line contact 14. In this way, formation of the NAND-type mask ROM and the peripheral circuit of the LDD transition is achieved. The above embodiment is a typical example of the method for producing a NAND-type mask ROM and the product provided by the method. However, the present invention is not be limited to the illustrated embodiment and should be understood to have various modifications. For example, while the first and second conductivity types are P and N respectively in the above embodiment, they can also be N and P respectively, although high-speed operation cannot be expected in the latter option. Further, in the embodiment above, the thickness D 0 of the filling layers 8a through 8e is so prescribed that the projection range R pl is equal to the source-drain junction depth X j . However, since the requirement for the projection range R p1 is that R p1 should not exceed the junction depth X j in order to preclude the formation of parasitic layers, the thickness of the filling layers can also be larger than D 0 . Although the variations of the embodiment described above are possible, the scope of the present invention is defined in the appended claims.

Claims: A method of manufacturing a semiconductor memory device which includes a peripheral circuit region comprising an LDD transistor as well as a memory region comprising a plurality of memory transistors, comprising the steps of: (a) forming a field oxide (2) on a major surface of a semiconductor substrate (1) of a first conductivity type; (b) forming a first dielectric as a gate dielectric (3); (c) forming gate electrodes (4a - 4f) on the first dielectric wherein in the memory region a plurality of the gate electrodes are formed so that the ratio of the height of the gate electrodes to the distance between neighbouring gate electrodes equals or exceeds 1, and in the peripheral circuit region at least one gate electrode (4g)is formed; (d) implanting low-concentration impurity ions of a second conductivity type into the semiconductor substrate using the gate electrodes as masks to form lightly-doped source-drain diffusion regions (5b - 5f) of the memory transistors, and lightly-doped source-drain regions (5h,5i) of the LDD transistor in the peripheral circuit region; (e) forming on the first dielectric between the gate electrodes in the memory region a second dielectric (6) of a thickness 1/2 or more of the distance between the neighbouring gate electrodes and, at the same time, forming the second dielectric on the sides of each gate electrode in the peripheral circuit region, and etching back the second dielectric to leave a predetermined thickness of the second dielectric unetched (8a-8e) on the first dielectric between the gate electrodes in the memory region and to leave at least a portion of the second dielectric (7c,7d) on the sides of each gate electrode in the peripheral circuit regional; (f) implanting high-concentration impurity ions of the second conductivity type into the semiconductor substrate using the gate electrodes and the second dielectric as masks to form highly-doped source-drain regions (19a - 19d) of the second conductivity type of the LDD transistor in the peripheral circuit region; (g) coating a photoresist (10)over the existing surface, the photoresist having an opening (11a,11b) above selected memory transistors; and (h) implanting impurity ions of the second conductivity type through the gate electrodes and the first and second dielectric into the semiconductor substrate using the photoresist as a mask so as to form a lightly-doped channel region (12a, 12b) of the second conductivity type in each of the selected memory transistors. A method according to claim 1, wherein the predetermined thickness of the second dielectric after etching is determined so that the projection range of the ions implanted in step(h) scattered forward through the second dielectric into the source-drain regions (5b - 5f) of the memory transistors does not exceed the junction depth of the source-drain regions of the memory transistors A method according to claim 1 or 2, wherein the first and second conductivity types are P and N types respectively, and the length of each gate electrode is designed to be between 0.4 micrometres and 0.8 micrometres.

Inventors: TASAKA KAZUHIRO, TASAKA, KAZUHIRO
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: H01L21
IPC codes: H01L27, H01L21