Tape carrier semiconducteur device

Abstract: A tape carrier semiconductor device has a resin sealed area not so larger than the size of the semiconductor chip, e.g. substantially not exceeding 2 mm to the outside. A device hole is not larger than an area formed by extending the outer periphery of the semiconductor chip to the outside by 0.3 mm and an epoxy resin of 500 - 1200 ps in viscosity is used for sealing the chip.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a tape carrier semiconductor device, and, more particularly, to a tape carrier semiconductor device of a small external size capable of high density mounting. Description of the Related Art Heretofore, sealing resins for tape carrier semiconductor devices have been selected giving priority to thinning the thickness of the resin applied to the semiconductor devices. With respect to the viscosity of the resin, liquid resins having a viscosity ranging from 100 to 150 cps are widely used and the device hole size is usually equal to the chip size plus 0.6 - 1.0 mm, and the size of the resulting resin sealed area is about the chip size plus 4 - 5 mm. A technique capable of controlling the size of the resin sealed area to a range of the chip size plus 1 - 2 mm has not yet been available. The size of a resin sealed area is mostly left to a natural phenomenon, and after pouring a sealing resin, the natural extension of the sealing resin is allowed until the natural extension stops. Viscosity of liquid resins used heretofore is so low that the size of area covered by the sealing resin extends too widely and it is difficult to control the size of resin sealed area. On the contrary, even if the resin viscosity is raised, the sealed area can not be controlled to a desired size of area, and conversely, LSI chips can not be fully covered so that there is a problem in terms of reliability. For the purpose of controlling the size of a resin sealed area, there is a method of printing a paste sealing resin on the device. Although this method can control the resin sealed area at the side of the chip on which the paste sealing resin is printed, it is difficult to control the extending area of the sealing resin flowing to the opposite side of the chip through a gap between the LSI chip and the device hole. MICROELECTRONICS PACKAGING HANDBOOK, R. TUMMALA et al., Van Nostrand Reinhold, New York, 1989, pages 410-411 and 443-445, describes TAB (tape automated bonding) packaging and in particular inner lead bonding between inner leads formed on the tape substrate and bump electrodes formed on the chip and the improvement in the density of connections offered by TAB over alternative packaging techniques. SUMMARY OF THE INVENTION An object of the present invention is to provide a tape carrier semiconductor device which is more compact than hitherto achieved using the aforedescribed techniques. In one aspect, the present invention provides a method of manufacturing a tape carrier semiconductor device comprising a semiconductor chip set at a device hole provided in a substrate and sealed by an epoxy resin, wherein the epoxy resin is applied to one side of the semiconductor chip and caused to flow to the other side thereof through the gap between the outer edge of the semiconductor chip and the edge of the device hole so that the epoxy resin covers inner leads connecting the semiconductor chip to a lead pattern on the substrate, the epoxy resin has a viscosity in the range 500 to 1200 ps, and said gap between the outer edge of the semiconductor chip and the edge of the device hole is not greater than 0.3 mm wide. The method of the present invention enables a tape carrier semiconductor device to be realised having a resin-sealed area which extends laterally beyond the outer edge of the semiconductor chip by a distance of not greater than 2 mm. In another aspect, the present invention provides a tape carrier semiconductor device comprising a semiconductor chip set at a device hole provided in a substrate and sealed by an epoxy resin, wherein the gap between the outer edge of the semiconductor chip and the edge of the device hole is not greater than 0.3 mm wide, said epoxy resin extends laterally beyond the outer edge of the semiconductor chip by a distance not greater than 2 mm, and said epoxy resin covers inner leads connecting the semiconductor chip to a lead pattern on the substrate. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of a tape carrier semiconductor device sealed with an epoxy resin, according to an embodiment of the present invention; FIG. 2 is a plan view of the tape carrier semiconductor device of FIG. 1 before being sealed with an epoxy resin; FIG. 3 is a plan view of a conventional tape carrier semiconductor device sealed with a liquid resin; and FIG. 4 is a graph showing the relationship between resin viscosity and resin-sealed area. DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 illustrates a tape carrier semiconductor device sealed with an epoxy resin, according to an embodiment of the present invention. A lead pattern 6 is provided on a substrate 5 by using an adhesive such as an epoxy resin, and further a solder resist 7, for example, composed of an epoxy resin, is furnished for protecting minute patterns and decreasing connection resistances. LSI chip 2 set at a device hole (not shown in FIG. 1, but corresponding to 4 in FIG. 2) is sealed with an epoxy resin 1 (crosshatched) having a viscosity of 500 to 1200 ps applied thereto. LSI chip 2 is covered with the epoxy resin on the opposite side of the device to that seen in FIG. 1. The side of the LSI chip 2 visible in FIG. 1 is covered at its periphery with the epoxy resin. In FIG. 1, A′ and B′ represent the transverse and the longitudinal lengths of LSI chip 2, respectively and A and B represent the transverse and the longitudinal lengths of the resin sealed region, respectively. Each of (A - A′)/2, (B - B′)/2 and the distance between a vertex of LSI chip 2 and that of the resin sealed area corresponding to said vertex of LSI chip 2 is 2 mm or less. FIG. 2 shows a tape carrier semiconductor device of FIG. 1 which has not yet been sealed with the epoxy resin. In FIG. 1 and FIG. 2, like reference numerals show like parts. LSI chip 2 is set at device hole 4 and inner leads 3 are connected with LSI chip 2. C and D represent the transverse and the longitudinal lengths of device hole 4, respectively, and A′ and B′ represent the transverse and the longitudinal lengths of LSI chip 2. Each of (C - A′)/2, (D - B′)/2 and the distance between a vertex of LSI chip 2 and a vertex of device hole 4 corresponding to the vertex of LSI chip 2 is 0.3 mm or less. FIG. 3 shows the tape carrier semiconductor device of FIG. 2 LSI chip 2 of which has been sealed with a liquid resin having a viscosity of 100 - 150 cps applied thereto. In FIG. 1 and FIG. 3, like reference numerals indicate like parts. In FIG. 3, A and B represent the transverse and the longitudinal lengths of the resin sealed region, respectively. A′ and B′ represent the transverse and the longitudinal lengths of LSI chip 2, respectively. Each of (A - A′)/2 and (B - B′)/2 exceeds 2mm. A feature of the present invention is that a particular range of viscosity of the sealing resin is used and the relation between the size of the device hole and the size of LSI chip is defined so as to control the resin sealed region. FIG. 4 illustrates a relationship between the viscosity of an epoxy resin and the resin sealed region in the case where the device hole size is equal to (chip size + 0.2 mm) (i.e. the distance between the inner pheriphery of the device hole and the outer periphery of the LSI chip being 0.2 mm). The "α" in FIG. 4 stands for the distance between the outer periphery of the LSI chip and the outer periphery of the resin sealed region. In FIG. 4, the resin viscosity giving the resin sealed region which is equal to (chip size + 1 to 2 mm) (i.e. α = 1 to 2 mm) is 500 - 1200 ps. The lower limit of the resin sealed region is selected to be (chip size + 1 mm) (i.e. α = 1 mm) here since defective sealing is liable to occur when the resin sealed region is less than (chip size + 1 mm). The curve in the graph of FIG. 4 is obtained when the device hole size is equal to (chip size + 0.2 mm). However, a curve similar to the curve in FIG. 4 is obtained until the device hole size increases to (chip size + 0.3 mm) (i.e. the distance between the inner periphery of the device hole and the outer periphery of the LSI chip). When the epoxy resin viscosity is higher than the above-mentioned upper limit or the device hole size is larger than the above-mentioned upper limit, the epoxy sealing resin can not completely cover the inner leads connecting with an LSI chip or with an LSI chip and a tape carrier pattern, and therefore, the reliability and the mechanical strength are problematic. On the contrary, when the epoxy resin viscosity is lower than the lower limit, i.e. 500 ps, the resin sealed region extends too much. When the gap between the LSI chip and the device hole is too small, the epoxy resin for sealing can not flow through the gap and thereby, can not reach the back surface of the LSI chip. Therefore, the reliability is problematic. As a sealing resin, an epoxy resin having a viscosity of 500 - 1200 ps is used. Representative epoxy resins are glycidyl ether type epoxy resins. Exemplary suitable epoxy resins are bisphenol A type epoxy resins, bisphenol F type epoxy resins, phenol novolaks type epoxy resins and the like. Materials which are in contact with the epoxy sealing resin are, for example, substrates of the tape carrier. As the substrates, various materials may be used, and are usually resin materials. Exemplary suitable resin materials include polyimide resin films, glass epoxy substrates and polyester resin substrates. In addition, as other materials in contact with the epoxy sealing resin, there may be mentioned a solder resist 7 as shown in FIG. 1. According to the present invention, the degree of extension of the epoxy sealing resin having a viscosity of 500 - 1200 ps varies somewhat depending upon the kind of the material, but is not so largely affected by the kind of the material. The method of sealing the LSI chip with the epoxy sealing resin is not particularly critical. For example, the epoxy resin having a viscosity of 500 - 1200 ps may be dropped onto the LSI chip. The procedure for sealing the chip may be carried out following prior art procedures, for example, applying the epoxy resin to the chip from one side thereof and allowing it to flow to the opposite side of the chip and extend naturally until its flow stops. For example, an LSI chip of 1.3 mm x 14 mm in size was put on a film carrier at a device hole such that the gap between the inner periphery of the device hole and the outer periphery of the chip was about 0.1 mm. Then about 13 mg of an epoxy resin having a viscosity of about 800 ps was dropped on the chip. The resulting resin sealed region was about 3.3 mm x 16 mm in size. It is not always necessary that the gap between the inner periphery of a device hole and the outer periphery of a semiconductor chip is the same at every position of the periphery, as far as the gap size is within the range as defined in the present invention. For example, the gap size at a portion where the number of inner leads is smaller is made narrower than the gap size at a portion where the number of inner leads is larger. Such difference in gap size is desired so as to avoid non-uniform flows to the back surface of the chip due to the difference in the number of inner leads overhanging the device hole. As described above in detail, according to the present invention, the problem of the resin sealed region affecting the determination of the outer size of a tape carrier semiconductor device can be solved. As a result, there is produced a subminiature tape carrier semiconductor device of which resin sealed region is within an area formed by extending the periphery of the semiconductor chip to the outside by 2 mm. For example, the present invention is particularly effective to decrease a resin sealed area in a liquid crystal driver so as to lessen the outer periphery of a portion other than the display portion. The invention being thus described, it will be obvious that the same may be varied in many ways. There are described above novel features which the skilled man will appreciate give rise to advantages.

Claims: A method of manufacturing a tape carrier semiconductor device comprising a semiconductor chip (2) set at a device hole (4) provided in a substrate (5) and sealed by an epoxy resin (1), wherein the epoxy resin (1) is applied to one side of the semiconductor chip (2) and caused to flow to the other side thereof through the gap between the outer edge of the semiconductor chip (2) and the edge of the device hole (4) so that the epoxy resin (1) covers inner leads (3) connecting the semiconductor chip (2) to a lead pattern (6) on the substrate (5), the epoxy resin (1) has a viscosity in the range 500 to 1200 ps, and said gap between the outer edge of the semiconductor chip (2) and the edge of the device hole (4) is not greater than 0.3 mm wide. A method of manufacturing a tape carrier semiconductor device according to claim 1, wherein said gap between the outer edge of the semiconductor chip (2) and the edge of the device hole (4) is narrower at a portion where the number of inner leads (3) is smaller than at a portion where the number of inner leads (3) is greater. A tape carrier semiconductor device comprising a semiconductor chip (2) set at a device hole (4) provided in a substrate (5) and sealed by an epoxy resin (1), wherein the gap between the outer edge of the semiconductor chip (2) and the edge of the device hole (4) is not greater than 0.3 mm wide, said epoxy resin (1) extends laterally beyond the outer edge of the semiconductor chip (2) by a distance not greater than 2 mm, and said epoxy resin (1) covers inner leads (3) connecting the semiconductor chip (2) to a lead pattern (6) on the substrate (5). A tape carrier semiconductor device according to claim 3, wherein said gap between the outer edge of the semiconductor chip (2) and the edge of the device hole (4) is narrower at a portion where the number of inner leads (3) is smaller than at a portion where the number of inner leads (3) is greater.

Inventors: CHIKAWA YASUNORI, HONDA YOSHIAKI, MAEDA TAKAMICHI, MORI KATSUNOBU, TAJIMA NAOYUKI, TSUDA TAKAAKI, CHIKAWA, YASUNORI, HONDA, YOSHIAKI, MAEDA, TAKAMICHI, MORI, KATSUNOBU, TAJIMA, NAOYUKI, TSUDA, TAKAAKI
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1991
Main classification: H01L23
IPC codes: H01L21, H01L23