A data output stage of the buffer type, having reduced noise to ground, for logic circuits of the CMOS type

Abstract: A data output stage (1) of the buffer type for CMOS logic circuits, being of the type having at least one pair of MOS transistors (M1,M2) associated to drive an output node (3) of said stage (1), comprises first (8) and second (9) feedback loops which are structurally independent and respectively connected between said node (3) and a corresponding gate electrode (G1,G2) of each transistor (M1,M2) to pre-charge said output node (3) at a predetermined voltage value and reduce the noise to ground during the switching phase.

Description: This invention relates to a data output stage of the buffer type, as defined in the preamble of the claim. As is known, circuit devices of the above-outlined kind are useful to prevent undesired electric interactions between a driver circuit and a driven circuit. A first prior approach to the problem of providing such a buffer is disclosed, for example, in European Patent No. EP 0 284 357 to Toshiba. That patent describes the construction of a driver circuit incorporating a large-size CMOS inverter. The use of that inverter as a buffer involves problems from the high sensitivity of the circuit to switching noise. A second prior approach is disclosed in European Patent No. EP 0 251 910 to Fujitzu, whereby the switching noise of a data output buffer is reduced by driving the gates of the driver through a suitable RC circuit. A major drawback of the last-mentioned approach is the reduced speed of the entire circuit. Also known are other types of driver circuits which provide for a pre-discharge step of the output, which is brought to a logic high consistent with logics of the TTL type. This pre-discharge step is clocked by an internal clock of the circuit, which is caused to operate prior to enabling the buffer stage. The latter circuit arrangement does afford a reduction in noise on the output being switched from a logic high to a logic low, but has proved ineffective as it is switched the other way. EP-A-0 384 673, which has priority dates earlier than the priority date of this application and was published after that date, discloses an output circuit with a precharging circuit for sensing and precharging the level of an output terminal to an intermediate level. This known precharging circuit comprises two output transistors with structurally independent feedback networks which include NOR and NAND gates to provide respective threshold voltages above and below the intermediate level. Patents Abstracts of Japan, vol 12, no. 124 (E-601) (2971) & JP-A-62 248 306 discloses an output buffer having two feedback networks to precharge its output to a level intermediate to a high and a low logic level, according to the preamble portion of the claim. Patents Abstracts of Japan, vol. 11, no. 162 (P-579) (2609) & JP-A-61 294 682 discloses an output buffer with two feedback networks having a common inverter. The underlying technical problem of this invention is to provide a data output stage of the buffer type, having such structural and functional characteristics as to reduce the noise to ground during the switching step and overcome the above-mentioned drawbacks with which the prior art is beset. This technical problem is solved by an output stage as defined and characterized in the claim. The features and advantages of an output circuit stage according to the invention will become apparent from the following detailed description of an exemplary embodiment thereof, given by way of illustration and not of limitation with reference to the accompanying drawings. In the drawings: Figure 1 is a circuit diagram showing schematically the output stage of this invention; and Figures 2 and 3 are respective comparative graphs of the current values which appear in the stage of Figure 1 and in circuits according to the prior art. With reference to the drawing figures, generally shown at 1 is a data output stage of the buffer type embodying this invention and being intended for high switching rate, CMOS-type logic circuits. The stage 1 comprises a pair of MOS transistors M1 and M2 which are associated to drive an output node 3. More particularly, the source electrode S1 of transistor M1 is connected to the drain electrode D2 of transistor M2, and these electrodes are both connected to the output node 3. The source S2 of transistor M2 is connected to ground, whilst the drain D1 of transistor M1 is connected to a power supply pole, not shown because conventional. Each transistor, M1 and M2, is provided with a conventional gate electrode G1 and G2 being connected electrically each to the output of respective circuit portions 4 and 5. Such portions 4 and 5 are each comprised basically of a pair of MOS transistors, M3 and M4, having their respective source and drain electrodes connected in parallel with each other. The drains D3 and D4 of each pair of transistors M3 and M4 are connected directly to each corresponding gate electrode G1 and G2. The source electrodes of the first circuit portion 4 are connected to the output of an inverter 6, whilst the corresponding souce electrodes of the other portion 5 are connected to the input of said inverter 6. Provided upstream of said inverter 6 is an additional inverter 7 which has its input connected to the drain electrodes of a pair of MOS transistors M5 and M6, connected in parallel, of which the source electrodes constitute a signal input 2 for the stage 1. Advantageously, according to this invention, the stage comprises first 8 and second 9 feedback networks which are structurally independent and respectively connected between the output node 3 and a corresponding gate electrode, G1 and G2, of each transistor M1 and M2. The first network 8 comprises an inverter 10 having its input connected to the node 3 and its output connected to the gate G1. The second loop 9 comprises a pair of inverters 11 and 12 connected serially to each other, with the input of the inverter 11 being connected to the node 3 and the output of the inverter 12 to the gate G2. The circuit structure of this invention allows the output node 3 to be pre-charged irrespective of the type of stage 1 switching. In essence, the circuit structure of this invention allows the capacitive load on the node 3 to be brought to an intermediate voltage to a logic low and a logic high consistent with logics of the TTL type. The transistor M1 operates as a pull-up for the output stage 1, whereas the other transistor, M2, operates as a pull-down. In the preferred embodiment being discussed, the threshold voltage of each feedback loop formed by networks 8 and 9 is selected to bring the output node 3 to an intermediate voltage value to the potential difference between the switching levels which, with logics of the TTL type is of 1.4 Volts. With the inventive circuit, this will occur independently of the voltage value appearing at the load connected to the node 3. The threshold voltage of the loop with network 8 is set at 1.3 Volts, and that of the loop with the lower network 9 is set at a value of 1.6 Volts. In this way, the loop with networks 8 and 9 are made operatively independent so as to avoid undesired oscillations. As an example, assuming a starting state whereby a logic high is present on the output node 3, the pull-down transistor M2 will be enabled because of the threshold of the loop with network 9 being set at 1.6 Volts. Under this condition, the node 3 will commence to discharge down to the threshold voltage value Vs. Due to the propagation delay of the inverters, 11 and 12, the transistor M2 is turned off on the node 3 reaching a voltage value of 1.4 Volts. Assuming, on the other hand, that in a starting condition, the output 3 is at a logic low, the pull-up transistor M1 will be enabled, and the node 3 charged up to the threshold voltage value present at the upper loop 8. The turn-off delay of the transistor M1 is less than that of the transistor M2, and accordingly, even under this operating condition, the voltage value present at the node 3 will be of 1.4 Volts. The feedback loops with networks 8 and 9 will be simultaneously operational in neither of these examples of operation. The output stage of this invention allows the current peak which appears during-the switching step to be lowered, thereby providing a reduction in the noise on the power supplies. Actual tests carried out by the Applicant have permitted the circuit performance to be analysed both in terms of gain and phase edge in comparison with circuits according to the prior art. For demonstrative purposes, plotted in Figures 2 and 3 are the behaviors of the switching current value versus time, for conventional circuits and the circuit of this invention. It may be appreciated from these graphs that, in the inventive circuit, the charge Q = Q1 + Q2 stored on the output capacitor C is scattered over a longer time period (Figure 3) than in circuits of conventional design. This effectively lowers the current peak during the switching phase.

Claims: A data output stage (1) of the buffer type, having low noise to ground and for use in CMOS logic circuits, which comprises at least one pair of MOS output transistors (M1 and M2) associated in a push-pull arrangement to drive an output node (3) of said stage (1), and first (8) and second (9) structurally independent feedback networks which are respectively connected between said node (3) and a gate electrode (G1, G2) of a corresponding one of said MOS output transistors (M1 and M2) to form a first and second feedback loops and pre-charge said output node (3) to approximately a predetermined voltage level, said first feedback network (8) being arranged to raise the voltage at said output node (3) toward said predetermined voltage level when the voltage at said output node (3) is below a first threshold voltage lower than said predetermined voltage level, and said second feedback network (9) being arranged to lower the voltage at said output node (3) toward said predetermined voltage level when said voltage at said output node (3) is above a second threshold voltage higher than said predetermined voltage level, said data output stage comprising a first circuit portion (4) for coupling a signal input to the gate (G1) of one (M1) of said MOS output transistors and a second circuit portion (5) for coupling said signal input to the gate (G2) of the other (M2) of said MOS output transistors, each of said first and second circuit portions (4, 5) consisting of a pair of MOS transistors (M3, M4) the respective source and drain electrodes of which are connected to each other, characterized in that said first network (8) comprises a first inverter (10) having its input connected to said output node (3) and its output directly connected to the gate electrode (G1) of said one (M1) of said MOS output transistors, and said second network (9) comprises a second inverter (11) and a third inverter (12) connected in series with each other, the input of the second inverter (11) being connected to the said output node (3) and the output of the third inverter (12) being directly connected to the gate (G2) of said other (M2) of said MOS output transistors; and in that said first circuit portion (4) is coupled to said signal input through a fourth inverter (6) whereas said second circuit portion (5) is directly connected to said signal input.

Inventors: DALLABORA MARCO, MACCALLI MARCO, ROLANDI PAOLO, DALLABORA, MARCO, MACCALLI, MARCO, ROLANDI, PAOLO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1991
Main classification: H03K19
IPC codes: H03K19