Endurance management for solid state files

Abstract: A nonvolatile storage system including several data storage arrays; a counter storage array for storing values indicating the remaining useful life of each of the data storage arrays; and a device for controlling access to each of the data storage arrays as a function of the values stored in each counter array. The counter array has an appreciably longer useful life than any of the data storage arrays.

Description: The present invention relates to an apparatus and method for counting the number of erase/write cycles that have occurred in nonvolatile files, and for reallocating a file when the counted number of erase/write cycles of the file approaches its endurance limit. The cost per bit of magnetic memory, such as magnetic disks, is decreasing. However, the cost per bit of nonvolatile memory, such as EEPROMs, is decreasing at an even faster rate. Presently, most systems do not employ nonvolatile devices due to their limited endurance, which in the best EEPROM technologies is at most approximately 10 7 erase/write cycles. This is due to the breakdown of tunneling dielectrics. When nonvolatile devices are employed, severe limitations are placed on the circuit design. Specifically, such a system must be configured to limit the number of erase/write cycles experienced by the nonvolatile devices. The following are examples of such systems. U.S. Patent 4,803,707 to Cordan Jr. discloses a vehicle odometer system for counting pulses representing vehicle mileage, and for storing the signal count during periods when the vehicle power is disabled. In this system, a group of nonvolatile memory cells is used to store binary values for odometer readings up to 10,000 miles. For odometer readings greater than 10,000, a new set of memory cells is accessed. Thus, each group of memory cells is cycled up to only 10,000 times which is below the endurance limit. The higher order bits of each memory block, which are not cycled as often as the lower-order bits, serve as a pointer for the new set of memory cells. In order to ensure the integrity of the stored data, this system requires that each group of nonvolatile memory cells be reallocated well below the maximum endurance limit of the cells. However, such a reallocation scheme is not practical in a system containing a large number memory blocks because the memory blocks would be reallocated too often. U.S. Patent No. 4,528,683 to Henry discloses an odometer system which employs a highly particularized five-bit word per decimal position counting scheme, along with a multi-level multiplexer to move the decimal ones, tens, hundreds and thousands position through a nonvolatile memory array. This system allows erase/cycle "wear" effects of the cells to be spread throughout the memory array, thereby preventing any one group of cells from wearing out too quickly. U.S. 4,663,770 to Murray et al discloses a system including nonvolatile counter devices. In order to distribute the erase/write cycle wear effects among the various counter devices, counter usage is successively shifted. While the scheme of this system allows for distribution of the erase/write wear effects among the nonvolatile devices within the system, the coding and decoding for this distribution requires a complex hardware configuration. EP-A-0398654 discloses an apparatus for writing data to an EEPROM. In order to prolong the life of the EEPROM, the number of rewrite cycles is counted and stored in a count portion of the data structure. When the count portion reaches a certain number, the CPU stores further data in an auxiliary region during the next updating cycle. The teaching of EP-A-0398654 forms the preamble to claim 1. EP-A-0392895 discloses a system of Flash EEprom memory chips with controlling circuits serving as non-volatile memory with the ability to remap and replace defective cells with substitute cells. The remapping is performed automatically as soon as a defective cell is detected. When the number of defects in a Flash sector becomes large, the whole sector is remapped. EP-A-0 349 775 discloses flash EEPROMs in which kind of memories entire groups of cells are erased at one go. The number of erase cycles experienced by each block is recorded and incremented by one for each cycle. This stored number is read out at the beginning of an erase/write cycle. Once it reaches a predetermined limit, the block can be replaced automatically with a new redundant block. It is an object of the invention to provide a nonvolatile memory system containing a large number of primary large memory blocks, and a minimum number of identical "substitutional" or reallocation memory blocks. It is another object of the invention to provide a system which utilizes nonvolatile devices and which is relatively simple in design. It is still another object of the invention to provide a system which ensures the integrity of data stored in nonvolatile memory even though the memory is subjected to a large number of erase/write cycles. The present invention as laid down in the claims accomplishes these and other objects in advantageous manner. The invention provides this by counting the number of erase/write cycles that a nonvolatile data block experiences, and reallocating the data block when the counted number of erase/write cycles approaches a predetermined number representing the endurance limit of the nonvolatile data block. In the following the invention will be described in more detail in connection with the embodiments shown in the drawing, in which Fig. 1 is a block diagram showing a memory system according to the invention; Fig. 2 is a block diagram of a counter utilized in the system shown in Fig. 1; Fig. 3 is a circuit block diagram for illustrating a counting operation according to the invention, and Fig. 4 is a flowchart showing the operation according to the invention. PREFERRED EMBODIMENTS OF THE INVENTION As shown in Fig. 1, the memory system according to the invention includes several primary counter/data registers 1, 2, 3, 4,...N, several substitutional counter/data registers 5, 6,....M; and a directory processor 10. Each of the primary and substitutional counter/data registers includes a large nonvolatile memory block, e.g., which contains 2 x 10 3 bytes, and a counter for counting each erase/write cycle that the associated memory block experiences. During an erase/write cycle for a particular memory block, the counter associated with that particular memory block is first read. If the read count is below a predetermined number, such as 1.0 x 10 7 which is the erase/write cycle endurance limit for a nonvolatile memory block, then the counter is incremented by one. However, if the read count is above the erase/write cycle endurance limit, then the counter outputs a reallocation signal, via signal line 20, to the directory processor 10 indicating that the memory block should be reallocated. Upon receiving the reallocation signal from a counter, the directory processor 10 downloads the data in the memory block, whose erase/write cycle endurance limit has been reached, into one of the substitutional counter/data registers 5, 6,...M which has not yet been accessed, i.e., subjected to any erase/write cycles. Since the substitutional counter/data register has not yet been previously accessed, the reallocated data can now be safely subjected to another 1.0 x 10 7 erase/write cycles. The directory processor 10 functions to keep track of which primary and substitutional counter/data registers contain data. For example, if primary counter/data register 1 sends a reallocation signal to the directory processor 10, the directory processor 10 will determine which of the substitutional counter/data registers 5,6...M do not contain data, i.e., have not been accessed. If, for example, substitutional counter/data register 6 has not been accessed, then the directory processor 10 will reallocate the data from primary counter/data register 1 to the substitutional counter/data register 6. The address of counter/data register 6 will now serve as the address for the data previously stored in primary counter/data register 1. Fig. 2 shows the counter of the counter/data registers in greater detail. As shown in Fig. 2, the counter includes a twenty- eight bit binary register 30 which stores the high-order bits of the counted data, a pair of nonvolatile linear registers 40 and 50 which store the lower-order bits of the counted data, and a comparator 60 for comparing the data stored in the linear registers 40 and 50. The binary register includes twenty-two bits for storing data, and six-bits for an ECC (Error Correction Code). Each of the linear registers stores twelve-bits of counted data. The following Table exemplifies the count sequence of the counter shown in Fig. 2 between erase/write cycles N and N+4. E/W Cycle Binary Register Linear Registers N 10010 000111 N+1 10010 001111 N+2 10010 011111 N+3 10010 111111 N+4 10011 000000 In this example, the nonvolatile counter bits experience 1/12 as many erase/write cycles as do the data bits, and therefore the counter bits do not deteriorate as quickly as do the data bits of the associated memory block, thereby ensuring an accurate count of the number of erase/write cycles of the associated data block. In Fig. 2 the comparator 60 compares the data contained in the linear registers 40 and 50. Since the linear registers 40, 50 are identical and count the same erase/write cycles, the counted data contained therein should always be the same. However, in the event of an error in either of the two linear registers, the higher count is assumed correct. In the event of an error in the binary register, the error is corrected by the ECC. This technique could be extended to higher orders of redundancy, if desired. Fig. 3 shows the operation of counting the linear registers. The data bits are directly connected to a driver 70, and the linear counter bits are connected to the driver 70 via the data bits and a switch 80. During all accesses, the counter bits are read first. During the erase portion of the erase/write cycle, If the linear counters are not full, the linear counter bits will be disconnected from the driver 70 by operating switch 80 to the "UP" position, as shown in Fig. 3. During the write portion of the cycle, only the next linear bit will be written. If the linear counter bits are full, then the counter bits will remain connected to the driver for the entire erase/write cycle by operating switch 80 to the "DOWN" position. During the erase/write cycle, the linear register will be reset to all zeros, and the binary counter counted-up by one. Fig. 4 shows the operation of the memory system. As shown in Fig. 4, it is first determined in step S1 whether or not an erase/write cycle has been requested for a particular data block. If an erase/write cycle has been requested, then the counter associated with that particular memory block is read at step S2. The linear registers 40 and 50 are then compared at step S3 to determine if they are equal to each other. As indicated above, the linear registers 40 and 50 are identical, and should always contain the same data. If it is determined in step S3 that the linear registers 40 and 50 are equal to each other, then the process proceeds to step S4 where it is determined whether the counter is full, i.e., whether the counter has reached the predetermined endurance limit of the memory block. If it is determined that the counter is not full at step S4, then the process proceeds to step S5 where it is determined whether or not any error has occurred by examining the ECC of the binary register. If it is determined that no errors have occurred, then the counter is incremented by 1, and the process proceeds back to step S1. If in step S3 it is determined that the linear registers 40 and 50 are not equal to each other, then it is assumed that an error has occurred, and the process proceeds to step S7 where the higher data count of the two registers is taken as the correct count. The process then proceeds to step S8 where it is determined whether or not the counter is full. If the counter is not full, then the process proceeds to step S9 where the counter is incremented by a value X which is some significant fraction of the counter's full capacity, because it was determined in step S3 that an error occurred, i.e., the linear registers were not equal to each other in step S3. Such an error may mean that the nonvolatile memory cells are beginning to wear out. By incrementing the counter by the value X, the count is significantly increased. As a result, the memory block associated with the counter will be reallocated sooner. If in steps S4 or S8 it is determined that the counter is full, then the data contained in the memory block is reallocated to a empty or spare substitutional data/counter memory block, as discussed above. If in step S5 it is determined from the ECC that an error has occurred, then the count is incremented by the value X. Again, since an error has occurred, this may mean that the nonvolatile memory cells are beginning to wear out. By incrementing the counter with the value X which is some significant fraction of the total count, the data contained in the associated data block will be reallocated sooner. In another embodiment of the invention, the linear registers are replaced with a random number generator programmed to generate an output having a one-in-twelve chance of being a "1" or HIGH output in any erase/write cycle. Upon generation of a "1" output, the binary register would be counted-up. While in this embodiment the exact count of the write/erase cycles would no longer be absolutely correct, the count would be statistically accurate enough. Alternatively, the random number generator may be a pseudo-random number generator such a linear feedback shift register of long prime number length, properly weighted. In another embodiment of the invention, the nonvolatile memory blocks are tested by subjecting the memory blocks to relatively short erase/write cycles to determine which memory blocks are likely to fail first, and which memory blocks have a better than average endurance to erase/write cycles. Those memory blocks which are likely to fail first could be loaded with a pre-count so that if these blocks are subjected to substantially more than average usage, the blocks would be reallocated early, i.e., earlier than if the counter was not loaded with a pre-count. On the other hand, those memory blocks determined to have a better than average endurance to erase/write cycles could be used as substitutional blocks. These high endurance memory blocks would later be substituted for high usage addresses. Thus, the strongest storage cells would subsequently be used for the highest usage addresses. Further, the counters of the system could be combined with a redundancy bad-block scheme wherein those memory blocks determined to have extremely poor endurance to erase/write cycles are preloaded with a full count. This could be done when the memory is first manufactured, or later on a periodic basis during use. In another embodiment of the invention, the counters store count values corresponding to endurance-limiting phenomena other than numbers of erase/write cycles. For example, a sensor could be used to indicate that the memory is being stressed by the application of high power surges or voltages, or other temporary endurance-detracting environmental conditions such as high temperatures. A count could be generated that varies as a function of the amount of time the stress conditions are experienced, the absolute value of such stress conditions, and the count already stored in the counter (i.e., as the counter value increases, the above stress conditions will have a greater effect upon endurance). Another alternative is to generate counts that reflect other more permanent environmental endurance detractors, such as high humidity, low pressure, ambients having high particulate counts, etc. Another alternative is to monitor the validity of the data from the memory using error correction codes (ECC) to increment the counter for memory blocks experiencing soft errors. Again, the count could be weighed such that the count is higher as the number of soft errors increases, or as the soft errors occur later in time. Yet another alternative is to identify "key" memory blocks that will be used most often and/or will store critical information. The counters associated with these blocks could be incremented prior to or during memory usage, without the occurrence of endurance-limiting phenomena. As such, the accesses would be diverted from such blocks earlier than the remaining blocks, further insuring the integrity of the stored data. In another embodiment of the invention, the functions of the directory processor 10 are combined in the counters. It is noted that the number stored in the counter is useless once a full count is obtained. The functions of the directory processor 10 can be combined in the counters by including, for example, three additional bits for each counter. These bits could indicate when the count is full, and by implication when other counter bits are to be used for other purposes. When the counter is full, as indicated by the stored code in these three bits, then the other bits in the counter can serve as a pointer for indicating which substitutional block is to be addressed.

Claims: A nonvolatile storage means comprising: a plurality of data storage registers (1, 2, ..., N; 5,6, ..., M); at least one counter means (Fig. 2) for counting a number of erase/write cycles that each of the plurality of data storage registers (1, 2, ..., N; 5, 6, ..., M) experience; controlling means (10) for controlling access to each of said plurality of data storage registers (1, 2, ..., N; 5, 6, ..., M) as a function of the values stored in said counter means (Fig. 2); characterized by the plurality of data storage registers (1, 2, ..., N; 5, 6, ..., M) comprising a plurality of nonvolatile memory blocks (1, 2, ..., N; 5, 6, ..., M), each having a plurality of memory cells, at least one of said plurality of nonvolatile memory blocks (5, 6, ..., M) containing no data and not having been previously accessed; the counter means (Fig. 2) storing values indicating the remaining useful life of each of said plurality of data storage registers (1, 2, ..., N; 5, 6, ..., M); the counter means (Fig. 2) having an appreciably longer useful life than any of said plurality of data storage registers (1, 2, ..., N; 5, 6, ..., M); wherein the controlling means (10) is coupled to said counter means (Fig. 2) and reallocates data contained in a first memory block (1, 2, ..., N) to said at least one memory block when the counter means (Fig. 2), for said first memory block, reaches a predetermined value. The system according to claim 1, wherein said predetermined value represents a predetermined endurance limit of each of said nonvolatile memory cell blocks (1, 2, ..., N; 5, 6, ..., M). The system according to claim 1 or 2, wherein there are a plurality of counter means (Fig. 2), and wherein each of said plurality of counter means (Fig. 2) comprises a first nonvolatile counter (30) and a second nonvolatile counter (40). The system according to claim 3, wherein each of said plurality of counter means (Fig. 2) further comprises a third nonvolatile counter (50). The system according to claim 3 or 4, wherein each of said plurality of counter means (Fig. 2) further comprises an associated comparator (60) means for comparing the data contained in said second (40) and third (50) nonvolatile counters with each other. The system according to any one of claims 3 to 5, further comprising means for incrementing one of said plurality of counters means by one when its associated comparator means determines that the second (40) and third (50) nonvolatile counters are equal to each other, and for incrementing said one counter means (Fig. 2) by a predetermined value which is substantially greater than one when said associated comparator means (60) determines that said second (40) and third (50) nonvolatile counters are not equal to each other. The system according to any one of claims 3 to 5, wherein each of said plurality of counter means (Fig. 2) comprises a binary counter and a random number generator. A method for counting a number of erase/write cycles of a nonvolatile memory system including a plurality of nonvolatile memory blocks (1, 2, ..., N; 5, 6, ..., M), at least one (5, 6, ..., M) of said plurality of nonvolatile memory blocks (1, 2, ..., N; 5, 6, ..., M) containing no data and not having been previously accessed, the method comprising: counting (S1 - S6) a number of erase/write cycles that the plurality of nonvolatile memory blocks (1, 2, ..., N; 5, 6, ..., M) experience, respectively; and reallocating (S11) data contained in a first memory block (1, 2, ..., N) to said at least one memory block (5, 6, ..., M) when the counted number of erase/write cycles of said first memory block (1, 2, ..., N) is equal to a predetermined value, and further comprising the steps of determining (S5) any errors in the nonvolatile memory system, and incrementing (S12) the counted number of erase/write cycles by a number substantially greater than one if any errors are determined (S5). The method according to claim 8, further comprising the step of determining (S7) which nonvolatile memory blocks (1, 2, ..., N; 5, 6, ..., M) have a high endurance to erase/write cycles and which nonvolatile memory blocks (1, 2, ..., N; 5, 6, ..., M) have a low endurance to erase/write cycles. The method according to claim 9, further comprising the step of preloading (S9) the counter associated with low endurance memory blocks (1, 2, ..., N; 5, 6, ..., M) with a count which is substantially greater than one. The method according to claim 9 or 10, further comprising the step of designating at least one of the determined high endurance memory blocks as said at least one memory block (5, 6, ..., M) which contains no data.

Inventors: PRICER WILBUR DAVIS, PRICER, WILBUR DAVIS
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1991
Main classification: G01C22
IPC codes: G11C29, G11C17, G06F12, G11C16, G01C22