MOS output circuit

Abstract: An output circuit for a memory device has four MOS transistors. A first MOS transistor (M1) and a second MOS transistor (M2) comprise an output stage of the output circuit, and a control circuit controls the voltages of the gates of the first and the second MOS transistors (M1, M2). A third MOS transistor (M3) has its source connected to the gate of the second MOS transistor (M2), and a fourth MOS transistor (M4) has its source connected to the gate of the first MOS transistor (M1). When the data which are supplied to the control circuit are changed, the third or the fourth MOS transistor (M3, M4) assists the level shift of the gate of the second and the first MOS transistor (M2, M1) at the beginning of the level shift. By continuing the level shift, the third or the fourth MOS transistor (M3, M4) is turned off. As a result the source-gate voltage of the third or the fourth MOS transistor (M3, M4) becomes lower than its threshold voltage, so that the switching noise or ground noise is reduced.

Description: Field of the Invention This invention relates to an output circuit for a memory constituted by MOS transistors. Description of the Prior Art In general, a demand for a higher speed is raised for an output circuit adapted for outputting data of a memory device constituted by MOS transistors. However, with increase in the operating speed, of the memory device constituted by MOS transistors, problems are raised in connection with the noise produced during switching of the output circuit. This switching noise is caused by the high inrush current flowing at the instant when the output stage MOS transistor is turned on and the parasitic capacitance which inevitably exists on the source voltage line or the ground potential line. Such noise or fluctuations in the voltage level in the source voltage line or the ground potential line affect seriously the memory device itself or peripheral devices. In order to reduce the noise, it is effective to swing the levels of the gates of the output stage MOS transistor gradually, but high-speed access is not achieved. US-A-4 604 731 discloses an output circuit comprising : an output stage including a first MOS transistor having its source and drain respectively connected to a power voltage line and an output terminal and a second MOS transistor having its source and drain respectively connected to a ground potential line and said output terminal, and a control circuit connected to the gates of said first and second MOS transistors and responsive to output data to control the voltage at said gates. According to the present invention, the circuit further comprises : a third MOS transistor having its source connected to the gate of said second MOS transistor and having its drain supplied with a predetermined voltage, said third MOS transistor being controlled in accordance with the gate voltage of said first MOS transistor, and a fourth MOS transistor having its source connected to the gate of said first MOS transistor and having its drain supplied with a predetermined voltage, said fourth MOS transistor being controlled in accordance with the gate voltage of said second MOS transistor, and in which the control circuit comprises means for controlling the gates of the third and fourth MOS transistors by the logically inverted gate voltages of the first and second MOS transistors, respectively, at least during an output enable period. The circuit of the invention enables outputting at a higher speed, and switching noises may be reduced. The channels of the first and the fourth MOS transistors may be of the same conductivity type, and the channels of the second and the third MOS transistors may also be of the same conductivity type. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram showing an output circuit according to an embodiment of the present invention. Fig. 2 is a waveform diagram for illustrating the operation of the output circuit shown in Fig. 1. Fig. 3 is a waveform diagram in which changes in the MOS transistor gate voltages at the output stage of the conventional output circuit are compared to those at the output stage of the output circuit shown in Fig. 1. Fig. 4 is a waveform diagram in which changes in the GND noise in the output circuit of Fig. 1 are compared to those in the conventional output circuit. Fig. 5 is a waveform diagram in which changes in the voltage at the output terminal of the output circuit shown in Fig. 1 are compared to those at the output terminal of the conventional output circuit. Description of the Preferred Embodiment By referring to the drawings, a preferred embodiment of the present invention will be explained in detail. The present embodiment is an example of an output circuit for a MOS memory constituted by, for example, an SRAM or a DRAM, in which the gates of MOS transistors constituting an output stage are charged electrically. Fig. 1 shows a circuit arrangement of the output circuit 21. The output stage of the output circuit 21 is constituted by an nMOS transistor M 1 as a first MOS transistor and an nMOS transistor M 2 as a second MOS transistor. The nMOS transistor M 1 has its drain and source connected to a source voltage line and to an output terminal 22, respectively. The nMOS transistor M 1 has its gate connected to an output terminal of a NOR circuit 27 so as to be controlled by the NOR circuit 27. An nMOS transistor M 4 , a fourth MOS transistor, has its source connected to the gate of the nMOS transistor M 1 , to which the input terminal of an invertor 23 in also connected. The nMOS transistor M 2 has its drain and source connected to the output terminal 22 and to the ground potential line, respectively. The nMOS transistor M 2 has its gate connected to an output terminal of a NOR circuit 28 so as to be controlled by the NOR circuit 28. An nMOS transistor M 3 , a third MOS transistor, has its source connected to the gate of the nMOS transistor M 2 , to which one input terminal of a NOR circuit 25 is also connected. A pMOS transistor 24 is controlled by the invertor 23, the input terminal of which is connected to the gate of the nMOS transistor M 1 . The function of this pMOS transistor 24 is to raise the voltage level at the output terminal 22. The voltage source Vcc is supplied to the source of the pMOS transistor 24. Hence, when the gate voltage V GH of the nMOS transistor M 1 is at the high level or "H" level, the output level of the invertor 23 is at the low level or "L" level to turn on the pMOS transistor 24 to raise the voltage at the output terminal 22. The abovementioned NOR circuits 27 and 28 constitute a control circuit which is responsive to signals from a sense amplifier for driving the nMOS transistors M 1 and M 2 of the output stage, respectively. The NOR circuit 27 has two input terminals, one of which is connected to the drain of an nMOS transistor 34 constituting the sense amplifier and the other of which is supplied with an output enable signal OE . The output terminal of the NOR circuit 27 is connected to the gate of the nMOS transistor M 1 . Similarly to the NOR circuit 27, the NOR circuit 28 has two input terminals, one of which is connected to the drain of an nMOS transistor 33 constituting the sense amplifier and the other of which is supplied with the output enable signal OE . The output terminal of the NOR circuit 28 is connected to the gate of the nMOS transistor M 2 . The NOR circuits 25, 26 function to drive nMOS transistors M 3 and M 4 adapted for electrically charging the gates of the output stage nMOS transistors M 2 and M 1 . The NOR circuit 25 has two input terminals, one of which is connected to the gate of the nMOS transistor M 2 and the other of which is supplied with the output enable signal OE . The output terminal of the NOR circuit 25 is connected to the gate of the nMOS transistor M 4 for driving the nMOS transistor M 4 . Similarly to the NOR circuit 25, the NOR circuit 26 has two input terminals, one of which is connected to the gate of the nMOS transistor M 1 and the other of which is supplied with the output enable signal OE . The output terminal of the NOR circuit 26 is connected to the gate of the nMOS transistor M 3 for driving the nMOS transistor M 3 . The nMOS transistors M 3 and M 4 constitute a circuit for electrically charging the output stage nMOS transistors M 2 and M 1 . When the output data are inverted, these nMOS transistors M 3 and M 4 are turned on to permit high speed electrical charging of the gates. The nMOS transistor M 3 has its gate and source connected to the output terminal of the NOR circuit 26 and to the gate of the nMOS transistor M 2 , respectively. The source voltage Vcc is supplied to the drain of the nMOS transistor M 3 . The nMOS transistor M 4 has its gate and source connected to the output of the NOR circuit 25 and to the gate of the nMOS transistor M 1 , respectively. The source voltage Vcc is similarly supplied to the drain of the nMOS transistor M 4 . Since the nMOS transistors M 3 and M 4 have their sources connected to the gates of the output stage nMOS transistors M 2 and M 1 which are subject to changes in the potential level, the nMOS transistors M 3 and M 4 are turned off when the source to gate voltage is below the threshold voltage Vth. The result is that the noise is reduced during the turn-off period. The data transferred to such output circuit 21 are supplied from the sense amplifier which is made up of a pair of pMOS transistors 31 and 32, the above mentioned nMOS transistors 33 and 34, a constant current source, and an nMOS transistor 35 functioning as a switch. This sense amplifier amplifies a signal from a memory cell. The source voltage Vcc is supplied to the sources of the pMOS transistors 31 and 32. The drains and the gates of the pMOS transistors 31 and 32 are cross-coupled to each other. The nMOS transistor 34 has its drain connected to the drain of the pMOS transistor 32 and has its gate supplied with a signal D from the memory cell. The nMOS transistor 33 has its drain connected to the drain of the pMOS transistor 31, while having its gate supplied with a signal D from the memory cell. The signal D has a level which is an inversion of the signal D. The ground voltage GND is applied to the source of the nMOS transistor 35, while an equalizing signal EQ is supplied to the gate of the transistor 35. Hence, when the equalizing signal EQ is at the "H" level, the sense amplifier is in operation and, when the signal EQ is at the "L" level, the sense amplifier is not in operation. pMOS transistors 36, 37 and 38 are pull-up and equalizing MOS transistors controlled by the equalizing signal EQ . The source voltage Vcc is supplied to the source of the pMOS transistors 36 and 37. The drain of the pMOS transistor 36 is connected to the drain of the pMOS transistor 32 and the drain of the pMOS transistor 37 is connected to the drain of the pMOS transistor 31. The equalizing signal EQ is supplied to the gates of the pMOS transistors 36 and 37, such that, with the equalizing signal EQ at the "L" level, the drain potential of each of the pMOS transistor 36 and 37 is pulled up. The pMOS transistor 38 is an equalizing transistor. The source and the drain of the pMOS transistor 38 are connected to the drains of the pMOS transistors 31 and 32, respectively. With the equalizing signal EQ at the "L" level, these drains are shorted for equalization. Referring to Fig. 2, the operation of the output circuit 21 is explained. If the signal D is initially at the "H" level, the "L" level signal is supplied from the sense amplifier to the NOR circuit 27, while the "H" level signal is supplied from the sense amplifier to the NOR circuit 28, by the sense amplifier operation. It is assumed that the output of the NOR gate 27, that is the gate voltage V GH of the nMOS transistor M 1 , is at the "H" level, and the output of the NOR gate 28, that is the gate voltage V GL of the nMOS transistor M 2 , is at the "L" level, as shown at (a) in Fig. 2. At this time, the equalizing signal EQ is at the "H" level, as shown at (b) in Fig. 2, while the output enable signal OE is at the "L" level. At time t 1 , the equalizing signal EQ is changed from "H" level to "L" level. The nMOS transistor 35 is thereby turned off to stop the operation of the sense amplifier, at the same time that the pMOS transistors 36, 37 and 38 are turned on. The result is the equalization and voltage pullup are performed, therefore, the voltage level at the sense amplifier side input terminal of the NOR circuit 27 being raised. When the voltage level at the sense amplifier side input terminal of the NOR circuit 27 exceeds the threshold voltage Vth of the NOR circuit 27, the output level of the NOR circuit 27 is changed from "H" level to "L" level, so that the gate voltage V GH of the nMOS transistor M 1 is lowered. At time t 2 , the gate voltage V GH reaches an intermediate level suited to the driving capability of each of the nMOS transistor M 4 which has been in the turned-on state and the driving MOS transistor of the NOR circuit 27 operating to pull down to the low level side. At time t 3 , a little later than time t 2 , the nMOS transistor M 3 is turned on by means of the NOR circuit 26, so that the gate voltage V GH similarly reaches an intermediate level suited to the driving capability of each of the nMOS transistor M 3 and the driving MOS transistor of the NOR circuit 28 operating to pull down to the low level side. Then, at time t 4 , the equalizing signal EQ is again changed from "L" level to "H" level to activate the sense amplifier. When the signal D is changed to the "L" level, the sense amplifier output, that is the voltage level of the sense amplifier side input terminal of the NOR circuit 27, is at the "H" level, while the voltage level at the sense amplifier side input terminal of the NOR circuit 28, is at the "L" level. As a result of these changes in the input voltage levels, the output of the NOR circuit 27 is changed from the above mentioned intermediate level to a lower "L" level, whereas the output of the NOR circuit 28 is chanyed from the above mentioned intermediate level to the "H" level. In keeping with these changes in the output voltage levels, the gate voltage V GL of the nMOS transistor M 2 is quickly raised in level due to high speed electrical charging caused by the driving of the nMOS transistor M 3 which has already been turned on and of the NOR circuit 28. With the output of the NOR circuit 28 at the "H" level, the output of the NOR circuit 25 is at the "L" level, so that the nMOS transistor M 4 is turned off. Thus the gate voltage V GH of the nMOS transistor M 1 is at "L" level, equal to the output level of the NOR circuit 27, without being affected by the nMOS transistor M 4 . At this stage, the voltage level D out at the output terminal 22 starts to be lowered, as shown at (c) in Fig. 2, with the noise level being slightly increased, as shown at (d) in Fig. 2. The gate voltage V GL of the nMOS transistor M 2 is then increased and, at time t 5 , the gate to source voltage of the nMOS transistor M 3 falls below the threshold voltage Vth. This causes the nMOS transistor M 3 to be turned off, so that the gate of the nMOS transistor M 2 is changed solely by the NOR gate 28 and hence the rate of increase of the gate voltage V GL is lowered. Thus, after time t 5 , the noise level is lowered to eliminate the inconvenience brought about by the switching noise. The favorable effects shown in Figs. 3 to 5 become apparent from the comparison of the above described output circuit of the present embodiment and the conventional output circuit in which the gate of the output stage MOS transistor is not charged or discharged electrically. Fig. 3 shows the results of comparison of the gate voltage V GL , wherein a curve F 1 depicts the characteristics of the output circuit of the present embodiment and a curve F 2 those of the conventional output circuit. It will be seen that, with the output circuit of the present embodiment, the voltage level transition proceeds at a higher speed because of the above described electrical charging at the higher rate by the nMOS transistor M 3 and, after the nMOS transistor M 3 is turned off, the voltage level rises gradually, however, the voltage level transition proceeds at a higher rate on the whole than with the conventional output circuit. Fig. 4 shows the results of comparison of the GND noise as the switching noise, wherein a curve F 3 depicts characteristics of the output circuit of the present embodiment and a curve F 4 those of the conventional output circuit. It will be seen from the comparison of the curves F 3 and F 4 that the present embodiment is capable of high speed outputting without the level of the noise. Fig. 5 shows the results of comparison of the voltages at the output terminals, wherein a curve F 5 depicts characteristics of the output circuit of the present embodiment and a curve F 6 those of the conventional output circuit. It is apparent from Fig. 5 that data outputting may occur at a higher speed with the output circuit of the present embodiment than with the conventional output circuit. It will be seen from the foregoing that a high speed outputting becomes possible with the output circuit of the present embodiment because the nMOS transistors M 3 and M 4 operate simultaneously with the NOR circuits 27 and 28 at the time of outputting with the voltage level being changed. On the other hand, when the gate voltage falls below the threshold voltage Vth of the nMOS transistors M 3 and M 4 , after the end of the high speed transition in the voltage level, these nMOS transistors M 3 and M 4 are turned off. Thus the switching noise may be reduced as compared with the case in which the nMOS transistors M 3 and M 4 are maintained at all times in the operating state. Since the MOS transistors M 3 and M 4 provided for realizing high speed level transition are of the same conductivity type, stable operation may be assured even on occurrence of dispersions in manufacture. Thus, with the output circuit of the present invention, the third and the fourth MOS transistors have their sources connected to the gates of the second and first output stage MOS transistors and, by the cooperation of these third and fourth MOS transistors and the control circuit, the gates of the second and first MOS transistors are charged or discharged electrically with changes in data. In other words, data outputting may occur at a higher rate because the third and the fourth MOS transistors contribute to electrical charging. In addition, by the turning on of the third and the fourth MOS transistors prior to the timing of the data output, as a result of saving the switching time, the present embodiment is capable of higher speed access time. It will be noted that the sources of these third and fourth MOS transistors are connected to the gates of the first and second MOS transistors which are changed in the voltage level. Thus, when the gate to source voltages of the third and the fourth MOS transistors fall below the threshold voltage Vth of these third and fourth MOS transistors, these MOS transistors are turned off and hence no longer contribute to changes in the gate voltages of the second and first MOS transistors. Therefore, there is little increase of the switching noise by additon of the third and the fourth MOS transistors. With the above described output circuit of the present invention, high speed output level transition becomes possible since the third and the fourth transistors contribute to gate voltage transitions of the output stage MOS transistors. These third and fourth MOS transistors have their sources connected to the gates of the output stage MOS transistors, so that the level transition rate is retarded when the gate voltages of the output stage MOS transistors are raised to values lower than the threshold voltage of the third and the fourth MOS transistors, thereby reducing the switching noise.

Claims: An output circuit (21) comprising : an output stage including a first MOS transistor (M1) having its source and drain respectively connected to a power voltage line and an output terminal and a second MOS transistor (M2) having its source and drain respectively connected to a ground potential line and said output terminal, and a control circuit (27,28) connected to the gates of said first and second MOS transistors (M1, M2) and responsive to output data (D, D ) to control the voltage at said gates, characterized in that the circuit further comprises : a third MOS transistor (M3) having its source connected to the gate of said second MOS transistor (M2) and having its drain supplied with a predetermined voltage, said third MOS transistor (M3) being controlled in accordance with the gate voltage of said first MOS transistor (M1), and a fourth MOS transistor (M4) having its source connected to the gate of said first MOS transistor (M1) and having its drain supplied with a predetermined voltage, said fourth MOS transistor (M4) being controlled in accordance with the gate voltage of said second MOS transistor (M2), and in that the control circuit comprises means (25, 26) for controlling the gates of the third and fourth MOS transistors (M3, M4) by the logically inverted gate voltages of the first and second MOS transistors (M1, M2), respectively, at least during an output enable period. The output circuit according to claim 1, wherein the channels of said first and fourth MOS transistors (M1, M4) are of the same conductivity type, and the channels of said second and third MOS transistors (M2, M3) are of the same conductivity type. The output circuit according to claim 2, wherein said third and fourth MOS transistors (M3, M4) are nMOS transistors having their drain supplied with a source voltage. The output circuit according to claim 1, wherein during an equalization phase, the gate controlling means (25, 26) is operated, by an equalization circuit, to turn on said third and fourth MOS transistors (M3, M4), which equalization phase precedes a data output phase. The output circuit according to claim 1, wherein said control circuit is operated in accordance with data from a sense amplifier. The output circuit according to claim 5, wherein the signal from said sense amplifier is amplified by the output circuit after equalization of the sense amplifier outputs. The output circuit according to claim 1, wherein the control circuit comprises a plurality of logic elements, the gate of each of the first to fourth MOS transistors (M1 - M4) being connected to the output of one such element, the control circuit being responsive to the output data (D, D ) to control the voltages at said gates. The output circuit according to claim 7, wherein the control circuit comprises first to fourth NOR logic elements (27, 28, 26, 25), the outputs of which are connected to the first to fourth MOS transistors (M1, M2, M3, M4) respectively, each NOR clement (27, 28, 26, 25) having an input connected to an output enable signal ( OE ), the third and fourth NOR logic elements (26, 25) having a second input connected to the gate of the first and second MOS transistors (M1, M2) respectively, the third and fourth NOR logic elements (26, 25) thereby controlling the gates of the third and fourth MOS transistors (M3, M4) by the logically inverted gate voltages of the first and second MOS transistors (M1, M2), respectively, during an output enable period. The output circuit according to claim 8, wherein the first and second NOR logic elements (27, 28) each have a second input connected to an equalization circuit (36, 37, 38) such that during an equalization period the third and fourth MOS transistors (M3, M4) are both turned on, and the first and second MOS transistors (M1, M2) have their gates at an intermediate voltage level between logic high and logic low voltage values.

Inventors: YUMOTO AKIRA, YUMOTO, AKIRA
Applicants: SONY CORP, SONY CORPORATION
Application year: 1991
Main classification: G11C7
IPC codes: H03K19, G11C11, G11C7