Semiconductor device and semiconductor device packaging system

Abstract: A package (1) comprising a first semiconductor chip (100) with pads for wire bonding and contacts for chip-to-chip interconnection, and a second semiconductor chip (200) also with contacts for chip-to-chip interconnection is mounted on a substrate (4) with a printed circuit (6). The first and second chips are coupled together via respective contacts. Chip-to-chip interconnections can be made by heat hardened silver pastel by anisotropic conductive material (9) or by a tape carrier having printed wires (9') supported by flexible film (8a). The two chips together are tightly-coupled pair having low interconnect capacitances and resistances. The first chip comprises an arithmetic logic unit (ALU), at least one register, a stack pointer, a program counter, and an index register. The second chip comprises a command register, a command decoder, and a timing generator, the command decoder in communication with the first semiconductor chip, the command register responsive to a program memory located outside the device.

Description: Background of the present invention Industrial Field of Use The present invention relates to a semiconductor device and a semiconductor packaging system of computer systems and more particularly to structures that allow some flexibility in computer architectures so that program and command word-lengths can be easily adjusted. Description of the Prior A rt Central processing units (CPUs) are conventionally comprised of a basic control unit, an arithmetic logic unit (ALU), and several general/special purpose registers. All of which elements are now routinely integrated on a single monolithic semiconductor substrate as a direct result of advancements in semiconductor processing technology. The control unit, ALU, and registers are usually interconnected by various proprietary kinds of intra-chip buses (sometimes called micro-buses). Program commands and I/O data flow over these buses. The internal connections between the elements dramatically reduce the number of external connections that would otherwise be necessary. Quality and reliability experts have a rule-of-thumb that says a reduction in the number of external pins and their PC board connections will be directly reflected in an improvement in a system's reliability. Individual device reliability is often computed on the basis of how many pins the IC's in a system have. But high levels of integration reduce the flexibility a system designer has with customizing the architecture for particular applications. Since the interconnects are on-chip, they are not accessible to board and systems designers. So these engineers are stuck with whatever the chip designer decided to offer as a general compromise between conflicting applications that were envisioned at the time the chip was specified. Each section and interconnect of a monolithic semiconductor CPU, quite naturally, has a fixed composition. Each CPU must therefore have a standardized fixed command (instruction) set. But non-monolithic implementations, even though they allow relatively mixing and matching each of the elements of a central processing unit, have serious disadvantages. For example, the required complex interconnections invite high failure rates. Being able to select a system optimal to its application is very compelling and can tip the scales in that direction. A major advantage of semiconductor integrated circuit technology is that many electronic elements are microminiaturized at the same time in a single array. However, central processing units rarely have flat, non-hierarchical structures. For example, a command register receives program commands from program memory and then sends these commands to a command decoder. The command decoder deciphers the program commands and sends out micro-commands (also called microcode). More complex and larger instructions can make use of wider microcodes, and do more in parallel. Fewer instructions are needed to implement each step in a program. A reduction in power consumption is possible if the number of elements in a command that must be fetched can be reduced. Conversely, if the length of a command word is made shorter, the processing of the command can be reduced, because the decoding is less complicated, and timing generators can be simplified. High-speed processing is possible because faster clocks can be used. The document JP-A-1-138725 discloses a process of manufacturing chip packages in which hybride integrated circuit substrates are mounted on a tape carrier after which the carrier is cut so that individual packages each including one semiconductor chip are obtained. The document JP-A-2-113543 discloses a semiconductor device having two LSI chips arranged side by side and interconnected by means of two wiring layers formed on a film tape. The document GB-A-2 053 566 discloses an integrated circuit package provided with a socket arrangement into which a second integrated circuit package may be plugged. The document US-A-3,984,813 discloses a microprocessor system having at least two separate LSI chips one including a central processing unit which requires an external program counter, and the other one including a memory for storing the instruction codes and a program counter for addressing the memory. The document JP-A-61-287133 discloses a semiconductor device including within one package three separate chips stacked one upon the other and interconnected by means of wire bonding. One chip includes a large scale memory element, another one a central processing control element and a third one a programming memory. It is an object the present invention to provide a central processing unit allowing it to easily change the command and instruction sets to allow for flexibility of a system designer to customize the architecture for particular applications. This object is achieved with a central processing unit as claimed in claims 1, 4 and 7, respectively. Preferred embodiments of the invention are subject-matter in the dependent claims. An advantage of the present invention is that various program command word lengths can be accommodated by swapping in different first chips. Another advantage of the present invention is that if the word lengths of commands in a program memory are long enough, arithmetic operations can be executed in one command fetch. This reduces the overall program fetch time used. Another advantage of the present. invention is that there can be a significant reduction in power consumption and consequently a longer battery life. Another advantage of the present invention is that if the command word lengths in program memory are short, high speed processing is possible because of a simpler timing generator can be implemented. Another advantage of the present invention is that the word lengths in program memory can be easily increased. Another advantage of the present invention is that a variety of second chips can be produced each in small lots, and the first chip can be produced in one version and in quantity. Depending on how they are combined, a low cost and diversified computer can be offered by tailoring the product to the application in which it will be used. Another advantage of the present invention is that the two-chip construction solves the heat generation problem, and higher speeds, compared to single-chip devices; are possible. Other objects and attainments together with a fuller understanding of the present invention will become apparent and appreciated by referring to the following description and claims taken in conjunction with the accompanying drawings. Brief Description of the Drawings Fig. 1 is a functional block diagram of a variable word length computer system, according to a first embodiment of the present invention; Fig. 2 is a block diagram of a program counter block in the computer system of Fig. 1; Fig. 3 is a timing chart of various system clocks generated by the timing generator of the ALU/register chip of the computer system of Fig. 1; Fig. 4A is a cross section of a wire-bonded chip-on-board type of package for the computer system of Fig. 1; Fig. 4B is a view of the active surface of chip 100 showing pads (contacts) arranged in two concentric squares about the periphery. The clockwise arrow represents the direction of increasing pin numbers; Fig. 4C is a view of the active surface of chip 200 showing pads (contacts) arranged in a square about the periphery. The counter-clockwise arrow represents the direction of increasing pin numbers and matches that of Fig. 4B when chips 100 and 200 are assembled face-to-face as in Fig. 4A ; Fig. 5 is a cross section of a package similar to that of Fig. 4A, but with an anistropic layer connecting chip 100 to chip 200; Fig. 6A is a top view of a tape automated bonded (TAB) type chip-on-board type of package for the computer system of Fig. 1; Fig. 6B is a cross sectional diagram of the package of Fig. 6A taken along the line 6B-6B. This cross-section intersects certain printed wires connecting chip 100 to chip 200; Fig. 6C is a cross sectional diagram of the package of Fig. 6A taken along the line 6C-6C. This cross-section intersects certain printed wires connecting the substrate and chip 100; Fig. 7 is a cross sectional diagram of a pair of stackable PGA packages for the computer system of Fig. 1; Fig. 8 is three dimensional perspective view of the packages of Fig. 7; Fig. 9 is a cross section of a surface mount type of QFP package mounted on a PGA type package, the pair containing chips 100 and 200 for the computer system of Fig. 1; and Fig. 10 is three dimensional perspective view of the packages of Fig. 9. Description of the Preferred Embodiments In Fig. 1, a first embodiment of the present invention is a variable word length computer system, comprised of two major parts, a 4-bit "general purpose" chip 100 and an ALU/register chip 200. Preferably, chips 100 and 200 are sealed together in the same device package. General purpose chip 100 has an arithmetic logic unit (ALU) 102; registers 104, 106, 110, and 112; a program counter 114; index registers 116 and 118; a stack pointer 120; a register pointer 122; and an interrupt controller 124. ALU 102 performs arithmetic operations between (4-bit) data stored in temporary registers 104 and 106. ALU 102 can do addition with carry (ADD), addition without carry (ADC), subtraction with borrow (SUB), subtraction without borrow (SBC), logical AND (AND), logical OR (OR), exclusive logical OR (XOR) comparison (CP), bit test (FAN), right rotation with carry (RRC), left rotation with carry (RLC), inversion (NOT), and more. When the arithmetic operation results of ALU 102 are all zero, a "Z" flag 108b (zero flag) will be set. When an addition carry result is generated and when a subtraction borrow is generated, a "C" flag 108a (carry flag) will be set. By setting a "D" flag 108c (digital flag), for decimal arithmetic operations mode, addition and subtraction will be BCD. Registers 110 and 112 are each 4-bit general purpose registers and function as accumulators. Chip 200 is comprised of a command register 202, a command decoder 204, and a timing generator 206. A program memory 302 supplies macrocode to command register 202. An oscillator 306 clocks timing generator 206. In Fig. 2, program counter 114 comprises two registers and three counters that address for command register 202 the various memory areas of program memory 302, described below. A program counter bank (PCB) 114a is a 1-bit counter that designates a program memory bank area. A program counter page (PCP) 114b is a 4-bit counter of the program memory page area. A program counter step (PCS) 114c is an 8-bit counter that designates the memory word step area. The program memory address therefore comprises 13 bits. A new bank pointer (NBP) 114d is a 1-bit register used for a branch destination bank address. When a branch command has been executed, the value of new bank pointer (NBP) 114e is loaded into program counter bank 114a. New page pointer (NPP) 114e is used for a page section register. When a branch command is executed, a value for the new page pointer 114e is loaded into program counter page 114b. Index register 116 is comprised of a 4-bit page section register and an 8-bit pre-settable counter. A maximum of 4,096 words can be specified. Index registers 118 and 116 are similar, and each has a 4-bit page section register and an 8-bit presettable counter. A maximum of 4,096 words can be specified. Stack pointer 120 is an 8-bit register that designates data memory stack address. Register pointer 122 is a 4-bit register for the data memory register address. Interrupt controller 124 can generate a maximum of 15 interrupt vectors for various interrupt requests from peripherals and internal elements. An interrupt enable/disable is specified by means of interrupt flag "I" 108d. When the "I" flag 108d is set, interrupts are enabled. When it is reset, interrupts are disabled. A bus 126 is a 4-bit data bus and a bus 128 is an 8-bit address bus. Command register 202 receives fetches of commands from program memory 302. Command decoder 204 then decodes the (macro) command codes and generates corresponding microcode comprised of many different basic control signals Among the control signals are a program counter control signal, a system control signal, an arithmetic operation control signal, a register control signal, a memory control signal, a flag control signal, a stack pointer control signal, a RAM expansion index register control signal, et cetera. Timing generator 206 produces a number of different system clocks that respond to commands that have different numbers of command cycles. For example, in Fig. 3, the first through fourth system clocks depend on particular system control signals that are then in effect. The program instruction set (command repertory) influence: the makeup of control signals from command decoder 204, the bit length of command register 202, and the bit length of the system clock of timing generator 206, all of which are on the ALU/register chip 200. The internal composition of general purpose chip 100 does not change, even if different instruction sets are being used. If the word length of the commands in the program memory is long, a savings in battery power consumption can be realized. ALU/register chip 200 is combined with general purpose chip 100. As such, it is possible to execute several arithmetic logic operations with one command fetch. In reducing the number of command fetches, a reduction in power consumption and a longer battery life results. Conversely, when a high speed system is formed that requires only a limited amount of processing, the command words can be shortened, and ALU/register chip 200, which corresponds to the, is combined with general purpose chip 100. Higher speed processing can be accomplished by means of the simplification of timing generator 206 and the simplification of command decoder 204 in terms of ALU/register chip 200 in the case. In a 4-bit CPU, there are typically 70 control signals that must be output from command decoder 204, and 40 system clock lines output from timing generator 206. Fig. 4A shows a cross section of a package 1 comprising general purpose chip 100, which is mounted to a substrate 4. Chip 200 is stacked on top of general purpose chip 100. In Fig. 4B, pads on the surface of chip 100 make external connections to pads 130a through 130x. In Fig. 4C, pads 232a through 232p are located on one surface of chip 200. Pads 232a to 232p are laid out such that they line up with inter-chip connecting pads 132a to 132p. Pads 130a to 130x are connected to a plurality of printed circuits 6 through a plurality of bonding wires 5. Within printed circuit 6 are the data bus 126 and an address bus 128. Chip 200 has its active surface facing the active surface of chip 100. Pads 232a to 232p of chip 200 and the inter-chip connection pads 132a to 132p are coupled by a silver paste 2 that can have sufficient bonding strength, if a heat hardened silver paste is used. Control signals from chip 200 that are not used by chip 100 (e.g., memory control signals) simply pass through to the bonding wires and the printed circuits. A clock from oscillator 306 (Fig. 1) passes through the printed circuits, bonding wires, the pads, the wiring within chip 100, the inter-chip connecting pads and chip 200. In order to protect chips 100 and 200 and to protect bonding wires 5, they are covered with a resin molding material 3. Fig. 5 shows an anisotropic conductive material 9 being used in place of silver paste 2 in the gap between chip 100 and Chip 200. Material 9 conducts only across the film thickness in one direction, and only corresponding pads will be interconnected connected. Operating speed will be reduced if the signal connection length between chip 100 and chip 200 is too long, because the line resistance and line capacitance will increase. But in the present invention, the two chips have their active surfaces facing toward each other and the corresponding pads are connected. This makes for an extremely short connection length. So, line resistance and line capacitance will be insignificant. With the above construction, a quick response to new applications is possible. The is possible by starting with a uncompleted product, having only chip 100 on substrate 4, and choosing a new ALU/register chip from among a series of chips. Figs. 6A-6C show a second way to package parts of the computer system of Fig. 1. A flexible circuit 8 having flex wires 9' makes the necessary connections between the outside and chips 100 and 200 (instead of bonding wires). Fig. 6B is a cross-section that shows how wires 9' interconnect chips 100 and 200 and are carried by a film portion 8a attached to substrate 4 via circuit 6. Fig. 6C is a cross-section that shows how wires 9' interconnect chip 100 with the outside. A plurality of pads 140 1 through 140 28 are positioned in a square pattern at a predetermined pitch (lead spacing) along the perimeter of chip 100. Pads 240 1 to 240 10 are also grouped in a square on chip 200, which is smaller than its counterpart on chip 100. The latter are set at a second predetermined pitch, which may or may not be the same as the first pitch. In Fig. 6C, a connection is made between the pads on chip 100 and printed circuit 6 by flexible circuit 8. The one end of each of wires 9' connect to the pads via bumps 10. In Fig. 6B, bumps 11 connect the pads of chip 200 to printed circuit wires 9' which then connect with bumps 12. Printed wires 9' are supported by flexible film 8a. Chip 200 is initially supported in its mid-air position above chip 100 during the packaging process by wires 9'. Then, in order to add strength and protection from the environment, chips 100 and 200 are encapsulated in a resin molding material 3 (e.g., epoxy). In the packaging process, chip 100 has flexible circuit 8 aligned on top. Inner edges of printed wires 9' are gang bonded to the pads on chip 100. Prior to soldering, bumps 11 are formed on the pads of chip 200. Chip 200 is then aligned with flexible circuit 8, and the pads of chip 200 are reflow soldered to wires 9'. The outer edges of printed wires 9' and printed circuit 6 are connected. Then resin 3 is molded to cover and fortify the delicate chips and their connections. Figs. 7 and 8 show a third embodiment of the present invention that can be used to package part of the computer system of Fig. 1. A pin grid array package (PGA) 20 is stacked onto a PGA 13, which has three ceramic layers 16a, 16b and 16c. A plurality of pins 18a to 18x are assembled into layer 16c. A cavity 14a allows chip 100 to be fixed in the middle. Center ceramic layer 16b and upper ceramic layer 16 have wiring patterns 14b and 14c formed in gold, and are connected to with bonding wires 15a and 15b. One end of gold wire pattern 14b connects to a through-hole plated wire 17a and to the base of pin 18b. Pin 18b is therefore electrically connected to chip 100. A lid 19 covers chip 100. PGA 20 also has three ceramic layers, these are layers 22, 24 and 26. Pins 28a to 28n are assembled into lower ceramic layer 22. Chip 200 is mounted in chip cavity 24a near the middle of ceramic layer 24. Gold wiring patterns 24b and 24c are routed between layers 24 and 26. Bonding wires 25a and 25b connect the pads on chip 200 with gold wiring patterns 24b and 24c. Gold wiring pattern 24b connects to pin 28a by a through-hole plated wire 27a. And, gold wiring pattern 24c is connected to pin 28n by a through-hole plated wire 27b. A plurality of sockets 30a to 30n are assembled in upper ceramic layer 16a. Pins 28a to 28n are such that they will fit into sockets 30a to 30n. For example, chip 200 connects to pin 18a via wire 27a, pin 28a, socket 30a and through-hole plated wire 17b. Chip 100 can be interconnected with chip 200, for example, by bonding wire 25b, plated wire 24c, through-hole wire 27b, pin 28n, socket 30n, through-hole wire 17c, plated wire 14c and bonding wire 15b. Chip 200 is covered by lid 29. Figs. 9 and 10 represent an example not forming part of the present invention of a package that can house part of the computer system of Fig. 1. Fig. 10 show a diagonal exploded view of the number of the same structure. A quad flat package (QFP) 50 is soldered to the top of a PGA package 40. PGA 40 has three stacked ceramic layers 42, 44 and 46, similar to PGA 13. Pins 48a to 48x are assembled in lower layer 42. Chip 100 is mounted face down in chip cavity 44a, near the middle of ceramic layer 44. A predetermined wiring pattern is placed between the ceramic layers for interconnect. Gold wiring patterns 44b and 44c are positioned between lower and middle layers. The pads and the gold wiring patterns are connected by bonding wires 45a and 45b. For example, gold wiring pattern 44b is connected to pin 48c by through-hole plated wire 47a. Gold wiring pattern 44c is connected to gold wiring pattern 49a of upper layer through though hole plated wire 47b. Gold wiring pattern 49b is connected to pin 48a by through-hole plated wire 47c. QFP package 50 houses ALU/register chip 200. A plurality of outer leads 50a match up with respective wiring patterns (e.g., patterns 49a and 49b) on the top of ceramic layer 46. Bonding of QFP 50 to PGA 40 can be done with a conventional solder reflow method. Chip 100 is mounted upside down in cavity 44a and is covered by lid 43. The length of the outer leads 50a are shorter than those of PGA 20 (Fig. 7). So the interconnect of chips 100 and 200 is shorter. As a result, even though there are two discrete packages, the wiring capacitance and resistance between chips 100 and 200 are significantly reduced from what would otherwise exist. Thus, the present invention described herein is intended to embrace all such alternatives, modifications, applications and variations as may fall within the spirit and scope of the appended claims.

Claims: A central processing unit device, comprising: a substrate (4, 4a); a printed circuit (6) on the substrate; a first semiconductor chip (100) of a general purpose type including an arithmetic logic unit (102), at least one register (110, 112), a stack pointer (120), a program counter (114), and an index register (116, 118) and having pads (130a-130x) for wire bonding to make external connections and contacts (132a-132p) for chip-to-chip interconnection on its active surface; and a second semiconductor chip (200) configured for a particular application, including a command register (202), a command decoder (204), and a timing generator (206) and having contacts (232a-232p) for chip-to-chip interconnection on its active surface, wherein the first and second chips are stacked one upon the other on said substrate with their active surfaces facing each other and with the respective contacts for chip-to-chip interconnection connected via a connector means. The device of claim 1, wherein: said connection of the first and second semiconductor chips is accomplished by coupling said contacts with a heat-hardened silver paste (2). The device of claim 1, wherein: respective contacts (132a-132p, 232a-232p) on the first and second semiconductor chips (100, 200) are coupled together via an anisotropic conductive material (9). A central processing unit device, comprising: a substrate (4); a printed circuit (6) on the substrate; a first semiconductor chip (100) of a general purpose type including an arithmetic logic unit (102), at least one register (110, 112), a stack pointer (120), a program counter (114), and an index register (116, 118) and having pads (140 1 -140 28 ) for bonding; a second semiconductor chip (200) configured for a particular application, including a command register (202), a command decoder (204), and a timing generator (206) and having pads (240 1 -240 10 ) for bonding; and a flexible circuit (8) having a first plurality of printed wires (9') that electrically couple pads on the first semiconductor chip with pads on the second semiconductor chip, the flexible circuit having a second plurality of printed wires (9') that electrically couple pads on the first semiconductor chip with the printed circuit on the substrate; wherein the first and second chips are stacked one upon the other on said substrate. The device of any of the preceding claims, wherein the first and second semiconductor chips (100, 200) are encapsulated in an epoxy resin. The device of any of the preceding claims, wherein the first and second semiconductor chips (100, 200) each have active surfaces facing one another. A central processing unit device, comprising: a first package (13) having; first, second, and third ceramic layers (16a, 16b, 16c); a plurality of connector pins (18a-18x) in the first ceramic layer (16c); a plurality of sockets (30a-30n) in the third ceramic layer (16a); a first semiconductor chip (100) of a general purpose type including an arithmetic logic unit (102), at least one register (110, 112), a stack pointer (120), a program counter (114), and an index register (116, 118), said first semiconductor chip being mounted in a cavity in the second and third ceramic layers; a first lid (19) that covers the first semiconductor chip; a first connection means for electrically connecting the first semiconductor chip to respective sockets, the connection means comprising bonding wires, plated through-holes in the third ceramic layer, and printed circuits; a second connection means for electrically connecting the first semiconductor chip to respective connector pins, the connection means comprising bonding wires, plated through-holes in the first ceramic layer, and printed circuits; a second package (20) having; fourth, fifth, and sixth ceramic layers (22, 24, 26); a plurality of connector pins (28a-28n) in the fourth ceramic layer (22) such that they mate with the plurality of sockets in the third ceramic layer of the first package; a second semiconductor chip (200) configured for a particular application and including a command register (202), a command decoder (204), and a timing generator (206), said second semiconductor chip being mounted in a cavity in the fifth and sixth ceramic layers; a second lid (29) that covers the second semiconductor chip; a third connection means for electrically connecting the second semiconductor chip to respective connector pins in the fourth ceramic layer, the connection means comprising bonding wires, plated through-holes in the fourth ceramic layer, and printed circuits; wherein the second package is stacked upon the first package with said plurality of connector pins of the second package received in said plurality of sockets of the first package. The device of claim 7 wherein said second connection means includes plated through-holes (17a, 17b) in the first and second ceramic layers (16c, 16b), and said third connection means includes plated through-holes (27a, 27b) in the fourth and fifth ceramic layers (24, 26) The device of any of the preceding claims, wherein: said program counter (114) comprises a program counter bank (114a), a program counter page (114b), a program counter step (114c), a new bank pointer (114d), and a new page pointer (114e).

Inventors: ABE SACHIYUKI, HAYASHI YOSHIMITSU, TSUKAMOTO TAKASHI, YABUSHITA TETSUO, ABE, SACHIYUKI, HAYASHI, YOSHIMITSU, TSUKAMOTO, TAKASHI, YABUSHITA, TETSUO, Abe, Sachiyuki, c/o Seiko Epson Corporation, HAYASHI, YOSHIMITSU,C/O SEIKO EPSON CORPORATION, Tsukamoto, Takashi, c/o Seiko Epson Corporation, Yabushita, Tetsuo, c/o Seiko Epson Corporation
Applicants: SEIKO EPSON CORP, SEIKO EPSON CORPORATION
Application year: 1991
Main classification: H01L25
IPC codes: H01L25, H01L23, H01L21, G06F15