TRANSISTOR SATURATION-PREVENTING CIRCUIT

Abstract: The invention is to prevent saturation of transistors in a current amplifier. The transistor saturation-preventing circuit is comprised of a second transistor (Q₂) which forms a current mirror circuit with respect to a first transistor (Q₁) in a current amplifier, saturation detecting means (R₁) that is connected to the second transistor (Q₂) to detect saturation in the first transistor (Q₁), and a current feedback means (D₁) which feeds part of the output current of the first transistor (Q₁) back to the preceding stage through the saturation detecting means (R₁), when it is saturated, in order to decrease the base current of the first transistor (Q₁).

Description: TECHNICAL FIELD The present invention relates to an amplifier formed by a transistor. More particularly, the invention pertains to a circuit for preventing oversaturation of a transistor which forms a current amplifier. BACKGROUND ART Known current amplifiers employing transistors, generally, have such circuit constructions as shown in Figs. 9 and 10. The current amplifier depicted in Fig. 9 uses PNP type transistor Q 1 , which has an emitter connected to a power supply Vcc. A load L is connected between a collector of that transistor Q 1 and a ground. A base of the transistor Q 1 is connected to an input terminal T, so that a base current Ib 1 flows from the base of the transistor Q 1 to the input terminal T. Thus, the transistor Q 1 supplies the load L with a collector current Ic obtained by multiplying the base current Ib 1 by a current amplification factor β. The current amplifier shown in Fig. 10 is of a type employing an NPN type transistor Q 11 , which has its emitter grounded, and the load L is connected between a collector of the transistor Q 11 and the power supply Vcc. A base of the transistor Q 11 is connected to the input terminal T, from which a base current Ib 11 flows to the base of the transistor Q 11 . The transistor Q 11 supplies the load L with the collector current Ic obtained by multiplying the base current Ib 11 by the current amplification factor β. Fig. 11 illustrates relationships among the collector current Ic the base current Ib and a collector-emitter voltage Vce, which are supplied by the transistor Q 1 or Q 11 forming the current amplifier. In the Fig. 11, the abscissa and ordinate are drawn to represent the collector-emitter voltage Vce and collector current Ic, respectively, and a particular relation is shown between those voltage Vce and current Ic in each of the transistors Q 1 and Q 11 , in accordance with the variation of base current Ib flowed in the transistor. Further as evident from Fig. 11, if the collector-emitter voltage Vce is somewhat higher, the collector current Ic is substantially proportional to the base current Ib, but if the collector-emitter voltage Vce becomes lower, then the same voltage Vce is proportional to the collector current Ic in the region where a certain amount of the base current Ib is flowed. At this point, the voltage Vce is a saturation voltage Vces. In the case where the transistor Q 1 or Q 11 is saturated by supplying thereto a sufficient amount of base current Ib, the collector current Ic, the saturation voltage Vces and ambient temperature Ta bear such relationships as shown in Fig. 12. In Fig. 12, there are depicted the relationships between the collector current Ic and the saturation voltage Vces, with ambient temperature Ta varied, wherein the abscissa represents the collector current Ic and the ordinate the saturation voltage Vces. As is apparent from Fig. 12, the saturation voltage Vces is in direct proportion to the collector current Ic and has a positive temperature characteristic, and hence the resistance between the collector and emitter of the transistor in the saturated state is equivalent to a resistor Rces which has a positive temperature coefficient. In the current amplifiers shown in Figs. 9 and 10, when the transistors Q 1 and Q 11 are in the saturated state, a further increase of the base current Ib will make the transistors Q 1 and Q 11 oversaturated, rendering unstable their operations of current amplifiers. Also, the current amplifiers will similarly become unstable in operation when the internal impedance of the load L increases abruptly or a voltage is induced in the load L by an external factor. Therefore, oversaturation of transistors must be prevented. This could be achieved by detecting the moment when the transistor is saturated, through utilization of its saturated voltage and then keeping the base current Ib from leaving or entering the base of the transistor in excess of the base current Ib which left (in the case of the PNP type transistor Q 1 ) or entered (in the case of the NPN type transistor Q 11 ) the base of the transistor at the moment of its saturation. It is not easy, however, to detect the saturated state of the transistor by the saturation voltage Vces. The reason for this is that the saturation voltage Vces is influenced by the collector current Ic and ambient temperature Ta as will be seen from Fig. 12 and undergoes substantial changes according to various conditions. GB-2014814 A discloses a first transistor saturation control circuit of a similar structure as in the present invention which uses a transistor of opposite conductivity type to the first transistor and connected as a follower to the collector and to a bias source which is coupled to the base of the first transistor. DISCLOSURE OF THE INVENTION The present invention has for its object the provision of a transistor saturation preventing circuit for preventing the saturation of a transistor under any circumstances, which merely requires adding a simple circuit to a current amplifier. To attain the above object, the transistor saturation preventing circuit according to the present invention is provided with: a current amplifier including a first transistor, a second transistor forming a current mirror circuit with respect to the first transistor, and a saturation detecting means connected to the second transistor to detect a saturation of the first transistor; and a current feedback means characterized in that: upon detection of the saturation of said first transistor by said saturation detecting means which generates a voltage substantially equal to the saturation voltage of the first transistor, the current feedback means becomes electrically conductive and generates a decrease of voltage down to a level substantially equal to a base-emitter voltage of said second transistor, and feeds a current portion from or to the collector of the first transistor to or from an input such that the input current in said current mirror circuit provided to said second transistor via the saturation detection means is reduced by this current portion resulting in a reduction of base current of said first transistor. Accordingly, in such arrangement, there flows a current proportional to a collector current flowed in the first transistor, and the current flows in the second transistor which forms the current mirror circuit and saturation detecting means. Thus, detecting such current by the saturation detecting means permits for detection of saturation in the first transistor. If the saturation of first transistor is detected by the saturation detecting means, the feedback means becomes electrically conductive, with decrease of voltage down to a level substantially equal to the base-emitter voltage of the second transistor, thereby feeding back one portion of the output current of first transistor to a circuit preceding the saturation detecting means of the current amplifier, whereby the base current of the first transistor is decreased. It is therefore possible to prevent oversaturation of the first transistor. Furthermore, the present invention ensures to prevent oversaturation of transistors in any cases, and hence offers a transistor circuit which is stable regardless of input and load conditions. According to the invention, the circuit to be added therein is relatively simple and economical. In another aspect of the invention, there is employed a current mirror circuit, which serves to keep constant a current ratio between the current flowed in the first transistor and the current flowed in the saturation detecting means. Accordingly, the precision in detecting the saturation is far improved, thus preventing, more positively, the transistor against saturation. Even an excessive operation for such saturation block will not lower the efficiency of power supply in the circuit. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram illustrating an embodiment of the transistor saturation preventing circuit according to the present invention; Fig. 2 is a circuit diagram illustrating a second embodiment of the present invention; Fig. 3 is a circuit diagram illustrating a third embodiment of the present invention; Fig. 4 is a circuit diagram illustrating a fourth embodiment of the present invention; Fig. 5 is a circuit diagram illustrating a fifth embodiment of the present invention; Fig. 6 is a circuit diagram illustrating a sixth embodiment of the present invention; Fig. 7 is a circuit diagram illustrating a seventh embodiment of the present invention; Fig. 8 is a circuit diagram illustrating a eighth embodiment of the present invention; Fig. 9 is a circuit diagram showing a conventional current amplifier; Fig. 10 is a circuit diagram showing another conventional current amplifier; Fig. 11 is a graph showing the relationship between the collector-emitter voltage and collector current of an ordinary transistor; and Fig. 12 is a graph showing the temperature dependence of the collector current and the collector-emitter saturation voltage of the ordinary transistor. BEST MODE FOR CARRYING OUT THE INVENTION The construction of a transistor saturation preventing circuit according to the present invention will hereinafter be described in detail with reference to its embodiments shown in the drawings. Fig. 1 illustrates a first embodiment of the transistor saturation preventing circuit according to the present invention. The illustrated transistor saturation preventing circuit constitutes a current amplifier, wherein a transistor Q 2 is added to the conventional circuit shown in Fig. 9 which includes the transistor Q 1 , forming a current mirror circuit to keep constant the input-output current ratio Ic 1 /Ir 1 . In other words, in such circuit, a current flows in the second transistor Q 2 of PNP type in the same way as the collector current Ic flows in the first transistor Q 1 of the same PNP type, just as if it was reflected in a mirror, whereupon the PNP-type second transistor Q 2 constitutes a current mirror circuit of the PNP-type first transistor Q 1 . The transistors Q 1 and Q 2 have their emitters connected to the power supply Vcc and have their bases connected to each other. The transistor Q 1 has its base further connected to the collector of the transistor Q 2 . The load L is connected between the collector of transistor Q 1 and the ground GND. The transistor Q 2 , which forms the foregoing current mirror circuit, is connected at its collector to an input terminal Ti via a resistor R 1 . The resistor R 1 is set to have a minimum value of the collector-emitter voltage Vce of transistor Q 1 , thus forming a saturation detecting means. The collector of transistor Q 1 is further connected to the anode of a diode D 1 ,which has a cathode connected to the circuit of the input terminal Ti side. With such arrangement, when the collector-emitter voltage Vce of the transistor Q 1 becomes nearly equal to the value defined by the resistor R 1 , the diode D 1 is energized, thereby feeding back a portion of the collector current Ic 1 to the input-terminal-Ti-side circuit disposed at the circuit preceding the resistor R 1 . The transistors Q 1 and Q 2 form a current mirror circuit and also form a current amplifier. The resistor R 1 constitutes a saturation detecting means for detecting saturation of the transistor Q 1 . The diode D 1 serves as a current feedback means. Therefore, when the transistor Q 1 gets saturated, the transistor Q 2 equivalently acts as a mirror of the transistor Q 1 , and consequently, a voltage equal to the saturation voltage Vces of the transistor Q 1 is induced in the resistor R 1 , conducting the diode D 1 . Such conduction of diode D 1 feeds back a portion of the output current Ici of the transistor Q 1 to the input-terminal-Ti-side circuit at the circuit preceding the resistor R 1 , so as to decrease the base current Ib which flows out of the transistor Q 1 . At this point, between both terminals of diode D 1 , there is developed a voltage drop substantially equal to the base-emitter voltage Vbe of the transistor Q 2 . In Fig. 1, an input current via the input terminal Ti is indicated by Iin; a current flowing through the resistor R 1 is indicated by Ir 1 ; the collector current of transistor Q 1 is indicated by Ic 1 ; and a current flowing through the load L is indicated by I L . Now, if the input current Iin is gradually increased from zero, a potential at the side of cathode of diode D 1 , which is initially equal to the supply voltage value of power supply Vcc when the input current Iin is zero, starts to drop toward the ground level by the reason that the base-emitter voltage Vbe of transistor Q 2 is induced with such increase of input current Iin and a voltage drops at the resistor R 1 . At the same time, a potential at the side of anode of the diode D 1 (i.e. a potential applied to the load L), which is initially equal to the ground level when the input current Iin is zero, goes up toward the voltage of power supply Vcc in accordance with the increase of load current I L . Thus, the cathode-side potential of diode D 1 starts to drop from the supply voltage of power supply Vcc toward the ground level, while the anode-side potential of same D 1 is being increased, and subsequently both cathode-and anode-side potentials of diode D 1 becomes equal to each other. Thereafter, if the anode-side potential of diode D 1 becomes higher than its cathode-side potential, with a forward voltage applied to the diode D 1 , then the diode D 1 is energized to feed back a portion of the colector current Ic 1 of transistor Q 1 to the input-terminal-Ti-side circuit, whereby the thus fed-back collector current portion is added to the input current Iin. By virtue of such fed-back current, the current Ir 1 will not increase any longer even if the input current Iin goes up further, and consequently, the load current I L does not increase, so that the collector-emitter voltage Vce of transistor Q 1 is fixed to a certain value. Letting, now, the collector-emitter voltage of the transistor Q 1 at this point of time (when the collector-emitter voltage Vce of the transistor Q 1 is fixed to a certain value) be represented by Vce 1 , and letting the base-emitter voltage of transistor Q 2 and the voltage across the diode D 1 at that time be represented by Vbe 2 and Vf 1 , respectively, we can express the relation among those voltages by the following equation: Vce 1 = Vbe 2 + R 1 · Ir 1 - Vf 1 The transistors Q 1 and Q 2 and the diode D 1 , insofar as they have the same semiconductor structure, are substantially identical in terms of forward voltage drop, including the temperature characteristic thereof, and thus, setting Vbe 2 =Vf 1 , then the Eq. (1) becomes as follows: Vce 1 = R 1 · Ir 1 Here, if it is desired to operate the transistor Q 1 until it verges very closely to saturation, let the saturation voltage of transistor Q 1 be taken to be Vces 1 , then it follows from the Eq. (2) that; Vces 1 = R 1 · Ir 1 Furthermore, the resistance between the collector and emitter of the transistor Q 1 in the saturated state is equivalent to a resistor as referred to previously in Fig. 12; hence, let us give Rces 1 to the equivalent resistance between the collector and emitter of transistor Q 1 , and the following equation can be obtained: Vces 1 = Rces 1 · Ic 1 Substitution of the Eq. (4) into the Eq. (3) gives: R 1 · Ir 1 = Rces 1 · Ic 1 R 1 = (Ic 1 / Ir 1 ) · Rces 1 The ratio (Ic 1 /Ir 1 ) in the Eq. (5) is the input-output current ratio of the current mirror circuit formed by the transistors Q 1 and Q 2 , and this ratio can be regarded as a fixed constant which is determined by the performance of the transistors Q 1 , Q 2 and values of them set in the circuit. Hence, if the value and temperature coefficient of the equivalent resistance Rces 1 are known, the set value of resistor R 1 can be determined. That is, the resistance value of resistor R 1 as the saturation detecting means corresponds to a product obtained by multiplying the proportional constant Rces 1 between the output current Ic 1 and saturation voltage Vces 1 of first transistor Q 1 by the input-output current ratio (Ic 1 /Ir 1 : current gain) of current mirror circuit composed of the transistors Q 1 and Q 2 . This is expressed by the foregoing Eq. (5). By setting the value and temperature coefficient of the resistor R 1 as described above, it is possible to prevent the transistor Q 1 from oversaturation, irrespective of the collector current Ic 1 and ambient temperature Ta. Moreover, adjusting the resistor R 1 enables desired choice of the saturation degree, including the non-saturated state. Further, should the collector potential of transistor Q 1 go up abruptly owing to a sudden increase in the internal impedance of load L or owing to an abnormal voltage being generated by an external factor, the current flow through diode D 1 to thereby immediately cut off the base current of transistor Q 1 , thus assuring to prevent the oversaturation of transistor Q 1 . Fig. 2 illustrates a second embodiment of the present invention, in which first and second transistors Q 11 and Q 12 are both NPN-type transistors. Both emitters of the transistors Q 11 and Q 12 are grounded. The transistors Q 11 and Q 12 have their bases connected to each other, with the base of the transistor Q 11 being connected to the collector of the transistor Q 12 . The collector of the transistor Q 12 is connected to the input terminal Ti via a resistor R 11 . The anode of a diode D 11 is connected to the input terminal Ti, while the cathode of the same D 11 is connected to the collector of the transistor Q 11 . The load L is disposed between and connected with the power supply Vcc and the collector of transistor Q 11 . The second embodiment as constructed above is exactly identical to the embodiment in Fig. 1, except that the transistors Q 11 , Q 12 and diode D 11 in the former are opposite in polarity to those in the latter, and that the application of power source voltage in this particular second embodiment differs from that in the first embodiment, which makes reversed the current direction between the two embodiments. The principle of operation and operational effect of the second embodiment are the same as those of the Fig. 1 embodiment, and a specific explanation is deleted thereon. It should be noted, however, that the resistor R 11 is a saturation detecting means and the diode D 11 is a current feedback means. Fig. 3 illustrates a third embodiment of the present invention, which employs a PNP-type transistor Q 3 and a current mirror circuit M 1 , instead of using the diode D 1 as the feedback means in the Fig. 1 embodiment. In the present embodiment of Fig. 3 the current mirror circuit M 1 is disposed between and connected with the collector of transistor Q 3 and the ground GND, with a current mirror circuit M 2 being connected to the input side (the preceding side) of the resistor R 1 which serves as saturation detecting means. Namely, the current mirror circuit M 1 is composed of NPN-type transistors Q M11 and Q M12 , which have their emitters grounded. Both bases of the transistors Q M11 and Q M12 are connected to each other. The base of transistor Q M12 is connected to the collector of the transistor Q M11 . Those transistors are connected to the collector of transistor Q 3 . The transistor Q M12 has its collector connected to the input terminal Ti. The current mirror circuit M 2 is comprised of NPN-type transistors Q M21 and Q M22 , which have their emitter grounded. The bases of those transistors Q M21 and Q M22 are connected to each other. The base of the transistor Q M21 is connected to the collector of the transistor Q M22 . Those transistors are connected to the input terminal Ti. The transistor Q M21 is connected at its collector to the resistor R 1 and the base of transistor Q 3 . Now let it be assumed that the input current to the current mirror circuit M 2 via the input terminal Ti is increased gradually from zero. Then, the collector current of the transistor Q M21 in the current mirror circuit M 2 , which is initially zero when the input current is zero, will go up with increase of that input current to the current mirror circuit M 2 . Here, since the collector current of the transistor Q M21 is the input current Iin, it is seen that the latter Iin increases, which induces the base-emitter voltage Vbe 2 of transistor Q 2 and also increases the voltage drop across the resistor R 1 . Consequently, the base potential of the transistor Q 3 , which is initially equal to the voltage of power supply Vcc when the input current to the current mirror circuit M 2 is zero, begins to drop toward the ground level, with increase of that input current to the current mirror circuit M 2 . At the same time, the emitter potential of the transistor Q 3 , which is initially equal to the ground level when the input current to the current mirror circuit M 2 is zero, rises toward the voltage of power supply Vcc from the ground level with an increase of the load current I L as the input current to the current mirror circuit M 2 increases. Subsequently, the base potential of transistor Q 3 becomes equal to the emitter potential of the same. Thereafter, when the base potential of transistor Q 3 becomes lower than the emitter potential and the base-emitter voltage Vbe of the transistor Q 3 becomes a forward voltage, the transistor Q 3 becomes conductive. Upon the transistor Q 3 being conductive, a portion of the collector current Ic 1 is fed back to the input current of current mirror circuit M 2 via the collectors of transistors Q M11 and Q M12 in the current mirror circuit M 1 . This decreases the input current to the current mirror circuit M 2 . In this respect, however, any further increase of such input current, which flows from the input terminal Ti to the circuit M 2 , will keep the forward volage to be applied to the transistor Q 3 and thus will not raise the input current Iin and not raise the load current I L neither. In this way, the collector-emitter voltage Vce of the transistor Q 1 is fixed to a certain value. At this point, letting now the collector-emitter voltage of transistor Q 1 and the base-emitter voltage of transistor Q 3 be represented by Vce 1 and Vbe 3 , respectively, we can express the relation between those two voltages as follows: Vce 1 = Vbe 2 + R 1 · Ir 1 - Vbe 3 Also, in this embodiment, insofar as the transistors Q 2 and Q 3 have the same semiconductor structure, their respective base-emitter voltages Vbe 2 and Vbe 3 , including their temperature characteristics, are substantially equal to each other (on the understanding that the transistor Q 1 is also of the same semiconductor structure as those of the foregoing two transistors). Hence, given the condition: Vbe 2 =Vbe 3 , we can transform the Eq. (6) to : Vce 1 =R 1 · Ir 1 , whereupon all the other Eqs. (2) to (5) hold as similar to the embodiment in Fig. 1. Accordingly, oversaturation of the transistor Q 1 can be prevented in any cases. Further, the degree of saturation of the transistor Q 1 can be chosen arbitrarily by setting the value of the resistor R 1 Fig.4 illustrates a fourth embodiment of the present invention. This embodiment greatly differs from the Fig. 3 embodiment in that the first and second transistors Q 11 , Q 12 and the transistor Q 3 used as feedback means are all formed by NPN-type transistors and that current mirror circuits M 11 and M 12 are both formed by PNP-type transistors. Specifically, the transistors Q 11 and Q 12 have their emitters grounded, and have their bases connected to each other, wherein the base of transistor Q 11 is connected to the collector of transistor Q 12 . The collector of the transistor Q 12 is connected via a resistor R 12 to the current mirror circuit M 12 . The load L is disposed between and connected with the power supply Vcc and collector of the transistor Q 11 . The base of transistor Q 13 is connected to the point where the resistor R 12 and current mirror circuit M 12 are connected together, whereas the collector of the transistor Q 13 is connected to the current circuit of M 11 and the emitter of the same Q 13 is connected to the collector of transistor Q 11 . The current mirror circuit M 11 is comprised of PNP-type transistors Q M111 and Q M112 , which have their emitters connected to the power supply Vcc. The bases of the transistors Q M111 and Q M112 are connected to each other, wherein the base of the transistor Q M112 is connected to the collector of the transistor Q M111 , and those transistors are connected to the collector of the transistor Q 13 . The transistor Q M112 has its collector connected to the input terminal Ti. The current mirror circuit M 12 is comprised of PNP-type transistors Q M121 and Q M112 , the emitters of which are connected to the power supply Vcc. The bases of the transistors Q M121 and Q M122 are connected to each other, wherein the base of transistor Q M121 is connected to the collector of transistor Q M122 , and hence the both transistors are connected to the input terminal Ti. The collector of transistor Q M112 is connected to the base of the transistor Q 13 and to the collector of the transistor Q 12 via the resistor R 12 . The present embodiment in Fig. 4 is exactly identical in construction to the Fig. 3 embodiment above, except that the transistors Q 11 , Q 12 , Q 13 and current mirror circuits M 11 and M 12 in the former embodiment are opposite in polarity to those in the latter embodiment, and except that the application of power source voltage in this particular fourth embodiment differs from that in the third embodiment, which makes reversed the current direction between the two embodiments. The principle of operation and operational effect of this embodiment are the same as those of the Fig. 3 embodiment, and hence will not be described in detail. It is noted here that the resistor R 12 constitutes a saturation detecting means and designations M 11 and M 12 denote the current mirror circuits. Fig. 5 illustrates a fifth embodiment of the present invention. This embodiment is constructed, using the Fig. 1 embodiment, such that the load L is connected via a power transistor Q ⊘ to the first embodiment, so as to increase the output current capacity, forming thus an emitter-follower current amplifier. The transistor Q 1 is connected at its collector to the base of the power transistor Q ⊘ . The collector of this power transistor Q ⊘ is connected to the power supply Vcc. The load L is disposed between and connected with the emitter of power transistor Q ⊘ and the ground GND. The principle of operation and operational effect of this fifth embodiment are exactly identical with those of the Fig. 1 embodiment, except that a large current can be applied to the load L by the power transistor Q ⊘ . Fig. 6 illustrates a sixth embodiment of the present invention. This embodiment is constructed, using the second embodiment in Fig. 2, such that the load L is connected to that second embodiment via an PNP-type power transistor Q ⊘1 , which thus forms an emitter-follower current amplifier. specifically, according to this Fig. 6 embodiment, the collector of the transistor Q 11 is connected to the base of the power transistor Q ⊘1 . The collector of that power transistor Q ⊘1 is grounded, and the emitter of the same Q ⊘1 is connected via the load L to the power supply Vcc. The principle of operation and operational effect in the present embodiment are the same as those of the Fig. 5 embodiment, and hence no detailed description thereof will be repeated. Fig.7 illustrates a seventh embodiment of the present invention. In this embodiment, a transistor Q 4 is employed as a saturation detecting means, in place of the resistor R1 which is used as the saturation detecting means in the Fig. 3 embodiment, and further there is employed a current mirror circuit M 3 comprising three transistors Q M31 , Q M32 and Q M33 , in place of the current mirror circuit M 2 including the two transistors Q M21 and Q M22 in the Fig. 3 embodiment. The collector of the transistor Q M33 in the current mirror circuit M 3 is connected to the input terminal Ti of the current circuit of this embodiment. The collector of another transistor Q M32 in the current mirror circuit M 3 is connected to the base of the transistor Q 4 . The collector of still another transistor Q M33 in the current mirror circuit M 3 is connected to the collector of transistor Q 4 as well as to the base of transistor Q 3 . Now, let it be assumed that the input current to the current mirror circuit M 3 from the input terminal Ti is increased gradually from zero. The collector current of the transistor Q M12 , is still zero, and thus, with regard to the collector current (equal to the current Iin) of the transistor Q M31 in the current mirror circuit M 3 , the initial zero level of the collector current, when the input current thereto is zero, becomes increased with an increse of the collector current (equal to the input current) of the other transistor Q M33 in the same circuit M 3 . At the same time, is increased likewise the collector current (equal to the base current Ib 4 of the transistor Q 4 ) of the transistor Q M32 in the same circuit M 3 . Suppose that the current ratio, Ib 4 /Iin, in that current mirror circuit M 3 is set at such a value that renders the transistor Q 4 completely saturated. Then, the collector-emitter voltage Vce of transistor Q 4 becomes a saturation voltage Vces 4 that increases in proportion to a collector current Ic 4 of the transistor Q 4 . When the current Iin increases from zero as mentioned above, the base potential of the transistor Q 3 starts to drop toward the ground level from the supply voltage Vcc, owing to the saturation voltage Vces 4 and the base-emitter voltage Vbe 2 of the transistor Q 2 . At the same time, the emitter potential of the transistor Q 3 rises toward the supply voltage Vcc from the ground level with an increase of the load current I L . Then, when the base potential of transistor Q 3 drops lower than the emitter potential thereof, the base-emitter voltage Vbe 3 in the same transistor Q 3 becomes a forward voltage. Thus, the transistor Q 3 conducts, feeding back a portion of the collector current Ic 1 to the collector of transistor Q M33 of the current mirror circuit M 3 , via the base of the transistor Q M11 and collector of the transistor Q M12 of the current mirror circuit M 1 . With such feedback of current, any further increase of the input current, which flows from the input terminal Ti to the current mirror circuit M 3 , will not lead to the increase of current Iin, as explained in the foregoing embodiment in Fig. 3. Accordingly, the load current I L will not increase either. In this way, the collector-emitter voltage Vce of the transistor Q 1 is fixed to a certain value. The collector-emitter voltage Vce 1 of the transistor Q 1 at this moment can be obtained by the following equation: Vce 1 = Vbe 2 + Vces 4 - Vbe 3 Also in this embodiment, insofar as the transistors Q 2 and Q 3 have the same semiconductor structure, their respective base-emitter voltages Vbe 2 and Vbe 3 , including their temperature characteristics, are substantially equal to each other (on the understanding that the transistor Q 1 is also of the same semiconductor structure as those of the foregoing two transistors). Hence, given the condition: Vbe 2 =Vbe 3 , we can transform the Eq. (7) above to: Vce 1 = Vces 4 Here, let us give Rces 4 to the equivalent resistance between the collector and emitter of transistor Q 4 in saturated state. Then, the Eq. (8) becomes as follows: Vce 1 = Rces 4 · Ic 4 As similar to the embodiments in Figs. 1 through 4, the following equations may be established: Vces 1 = Rces 4 · Ic 4 = Rces 1 · Ic 1 Rces 4 = (Ic 1 /Ic 4 ) · Rces 1 The ratio (Ic 1 /Ic 4 ) in the Eq. (11) is the input-output current ratio of the current amplifier composed of the transistors Q 1 and Q 2 ; namely, a current gain. Therefore, the resistance Rces 4 may be multiplied by the current gain (Ic 1 /Ic 4 ) of the resistance Rces 1 . If the transistors Q 1 , Q 2 , Q 3 and Q 4 have the same semiconductor structure, there is no difference in temperature coefficient between the resistances Rces 1 and Rces 4 , which eliminate the need for temperature compensation in this embodiment. The equivalent resistance between the collector and emitter of each of the transistors Q 1 and Q 4 in their saturated state can be controlled by the size of the transistor as well. Thus, this embodiment also insures to prevent oversaturation of the transistor Q 1 in any cases. Besides, the degree of saturation of the transistor Q 1 may be set selectively, depending on the size of the transistor Q 4 . Fig. 8 illustrates an eighth embodiment of the present invention. This embodiment greatly differs from the one in Fig. 7, in that the first and second transistors Q 11 , Q 12 and a transistor Q 13 used as feedback means are all NPN-type transistors, and that there is employed current mirror circuits M 11 and M 13 which comprise PNP-type transistors. The transistors Q 11 and Q 12 have their emitters grounded. Both bases of those transistors Q 11 , Q 12 are connected to each other, with the base of transistor Q 11 being connected to the collector of transistor Q 12 . The collector of the transistor Q 12 is, in turn, connected via a transistor Q 14 to the current mirror circuit M 13 . The load L is disposed between and connected with the power supply Vcc and the collector of the transistor Q 11 . The transistor Q 13 is connected at its base to the point where the collector of transistor Q 4 and the current mirror circuit M 13 are connected together. The collector of transistor Q 13 is connected to the current mirror circuit M 11 . The emitter of same Q 13 is connected to the collector of transistor Q 11 . The current mirror circuit M 11 is comprised of PNP-type transistors Q M111 and Q M112 . Both emitters of transistors Q M111 and Q M112 are connected to the power supply Vcc. the bases of those transistors Q M111 , Q M112 are connected to each other, and connected to the collector of transistor Q M111 ; hence, the transistors are connected to the collector of transistor Q 13 . The transistor Q M112 has its collector connected to the input terminal Ti. The current mirror circuit M 13 is comprised of PNP-type transistors Q M113 , Q M132 and Q M133 , wherein the emitters respectively of the transistors Q M131 , Q M132 , Q M133 are connected to the power supply Vcc. All bases of the transistors Q M131 , Q M132 , Q M133 are connected with each other, and connected to the collector of the transistor M 133 ; hence the transistors are connected to the input terminal Ti. The transistor Q M131 has its collector connected to the base of the transistor Q 13 and the collector of the transistor Q 14 . The transistor Q M132 has its collector connected to the base of the transistor Q 14 . The emitter of transistor Q 14 is connected to the collector and base of the transistor Q 12 . The above-described embodiment in Fig. 8 is identical with the one in Fig. 7, except that the transistors Q 11 , Q 12 , Q 13 and the current mirror circuits M 11 , M 13 in the former embodiment are opposite in polarity to those in the latter, and that the application of power source voltage in this particular eighth embodiment differs from that in the seventh embodiment, which makes reversed the current direction between the two embodiments. The principle of operation and operational effect of the present embodiment are the same as those of the Fig. 7 embodiment, and no detailed description thereon will be given. It is noted here that the transistor Q 14 forms a saturation detecting means. The above-described embodiments are illustrative of preferred embodiments of the present invention, but the invention is not limited specifically thereto and various modifications and variations may be effected without departing from the scope and gist of the invention. For instance, the addition of power transistor, as in the embodiments of Figs. 5 and 6, may be done in the other embodiments as well. If the power transistor is added to the transistor Q 1 in the embodiments other than the ones shown in Figs. 5 and 6, it is possible to enlarge the capacity of current sufficient to be supplied to the load L. It may also be possible to combine the embodiment(s) in Fig(s). 1 and/or 4 with the ones in Figs. 7 and 8. According to the embodiments in Figs. 1,2,3,4,5 and 6 the degree of saturation of the transistors Q 1 and Q 11 is not sensitive to and not influenced by a change in the set value of the resistors R 1 , R 11 , so that the resistors R 1 , R 11 need not necessarily be set at a value equal to a calculated value, but may be set close thereto. Accordingly, the value of the resistors R 1 , R 11 can be roughly set, with ease. In the case where the circuit of the present invention is fabricated as an integrated circuit (IC), the resistor R 1 normally has a positive temperature co-efficient close to the saturation voltage of the transistor. This saves the necessity of temperature compensation and allows ease in the design of the circuit. INDUSTRIAL APPLICABILITY The transistor saturation preventing circuit according to the present invention is applicable to electronic circuits, integrated circuits and similar circuits which amplify and supply the current. Moreover, the circuit in the invention operates stably, irrespective of an input condition and a load condition, and therefore may be applied to a measuring circuit which requires intricate connection with the other pertinent circuits, a protective circuit for a circuit whose load condition is changeable extremely.

Claims: A transistor saturation preventing circuit comprising a current amplifier which includes a first transistor (Q 1 ), a second transistor (Q 2 ) which forms a current mirror circuit with respect to said first transistor, and a saturation detecting means (R 1 ) for detecting a saturation of said first transistor, said saturation detecting means being connected to said second transistor, and also there is provided a current feedback means (D 1 ), characterized in that: upon detection of the saturation of said first transistor by said saturation detecting means (R 1 ), which generates a voltage substantially equal to the saturation voltage of the first transistor, the current feedback means (D 1 ) becomes electrically conductive and generates a decrease of voltage down to a level substantially equal to a base-emitter voltage of said second transistor, and feeds a current portion (Ic 1 -I L ) from or to the collector of the first transistor (Q 1 , Q 11 ) to or from an input (Ti) such that the input current (Ir 1 ) in said current mirror circuit provided to said second transistor via the saturation detection means is reduced by this current portion resulting in a reduction of base current of said first transistor. The transistor saturation preventing circuit according to claim 1, which employs a resistor (R 1 ) as said saturation detecting means. The transistor saturation preventing circuit according to claim 1, which employs a transistor (Q 4 ) as said saturation detecting means. The transistor saturation preventing circuit according to claim 1, which employs a diode (D 1 ) as said current feedback means. The transistor saturation preventing circuit according to claim 1, which employs a transistor (Q 3 ) as said current feedback means.

Inventors: NAITO HAYATO, NAITO, HAYATO, NAITO, HAYATO, K.K. SANKYO SEIKI SEISAKUSHO
Applicants: SANKYO SEIKI SEISAKUSHO KK, KABUSHIKI KAISHA SANKYO SEIKI SEISAKUSHO
Application year: 1991
Main classification: H03F1
IPC codes: H03K19, H03K17, H03F3, H03F1