Method for producing semiconductor device having alignment mark

Abstract: An alignment method for a semiconductor device having a conductive thin film (9) on a conductive substrate surface across an insulation film (4), comprises steps of: forming in the insulation film, at least two apertures (5,6) exposing the substrate surface therein; selectively depositing a conductive material (7,8) in the apertures thereby forming a stepped portion in at least one of said apertures; and forming the conductive thin film (9) at least on said insulation film. The alignment is conducted utilizing the stepped portion.

Description: The present invention relates to a method for producing a semiconductor device such as a memory, a photoelectric converting device, a signal processing device or the like adapted for use in various electronic appliances, and more particularly to a method for producing a semiconductor device using an alignment mark for patterning wiring. It also concerns a method of producing an alignment mark. In the formation of wiring layers by patterning in conventional semiconductor device production, the precision of said patterning is improved by automatic alignment utilising a recess, formed in a predetermined position in advance, as a mark. For example, in producing a conventional semiconductor device including a CMOS transistor, as shown in Fig. 1, oxide films 2, 4 on the principal surface of a silicon substrate 1 are partially removed at a predetermined position by selective etching to expose the silicon surface, thus forming a mother mark 6. Then the entire substrate surface, including said mother mark 6, is covered by a metal film 9, and as a result a recess 10 is formed in said metal film 9, corresponding to the form of said mother mark 6. A wiring layer of desired pattern is obtained by patterning said metal film 9, utilising auto-alignment achieved by irradiating said recess 10 with a laser beam and detecting the reflected light, or by utilising data obtained by image processing such as TV-AA (television auto-alignment). However, in such conventional semiconductor device production, if a contact 7 is formed by a selective metal depositing method such as tungsten CVD to a thickness required for the wiring layer, the mother mark area and the metal film therearound become flat so that the recess 10 corresponding to said mother mark 6 is no longer formed, because of the selective growth characteristic of said depositing method. Consequently the detection of the mother mark 6, essential for auto alignment, becomes difficult and the precision of alignment becomes significantly deteriorated. Fig. 2 shows a contact 7 and an aperture filling 8 formed by selective deposition utilising the tungsten CVD mentioned above. On the mother mark 6, a metal film composed of tungsten is deposited to the level of the insulation film 4, and when the wiring layer 9 is deposited thereafter, the portion 10, which is intended to serve later as the alignment mark, becomes flat instead of recessed, making mark detection difficult. An alternative approach is described in European Patent Application EP-A-0199030. As there described there is provided a semiconductor substrate having at its surface an insulating layer with a mother mark aperture defined therein. Conductive material such as aluminium or aluminium silicide is deposited to fill the aperture and a surplus of this material also is deposited covering the surface of the insulating layer. As a further step, etching is then performed to remove the surplus conductive material to produce a depression in the conductive material filling the aperture. A similar depression is formed when further conductive material is deposited over the depression in the aperture filling. This similar depression is then used as alignment mark for pattern alignment. The present invention provides an alternative to the approach just described and is intended as a solution to the problem aforesaid. In common with EP-A-0 199 030, in the present invention there is provided a method of producing an alignment mark which method comprises: providing a semiconductor substrate having at its surface an insulating layer with a contact hole and a further aperture formed therein: depositing a conductive material selectively to fill said contact hole; and depositing wiring material on said insulating layer and on said conductive material filling said contact hole. The present invention is characterised in that: said further aperture exposes an area of the substrate larger than the area of the substrate exposed by said contact hole; and said depositing of conductive material is performed by selective chemical vapour deposition using an alkylaluminium hydride and hydrogen, so that although said contact hole is filled, said aperture is only partially filled; whereby an alignment mark is produced over the partially filled aperture as said wiring material is deposited. In selective chemical deposition using alkyl aluminium hydride and hydrogen it has been discovered that the rate of deposition is dependant on the localised surface area of substrate exposed. By producing an aperture exposing a larger area of substrate than a contact hole, it is thus possible to only partially fill the aperture at the same time as filling the contact hole. An alignment mark recess can therefore be produced without difficulty. In the accompanying drawings: Figs. 1 and 2 are schematic views showing conventional methods for forming an alignment mark; Fig. 3 is a schematic cross-section view of a device, at a stage in production, having an alignment mark formed according to a preferred embodiment of the present invention; Figs. 4A to 4C are schematic cross-section views of a device in earlier stages of production showing a method for producing a semiconductor device according to said preferred embodiment; Figs. 5 to 8 are views showing examples of manufacturing apparatus adapted for use in the method of the present invention; and Figs. 9A to 9D are schematic perspective views showing steps of wiring layer formation using the method of the present invention. Now the present invention will be clarified in detail by an embodiment shown in the attached drawings. The following description is given by way of example only. Fig. 3 illustrates a semiconductor device at a stage in production following the forming of an alignment mark by the method described hereinafter, embodying the present invention. A semiconductor substrate 1, composed for example of silicon, is provided having functional elements such as MOS transistors, bipolar transistors or the like (not shown). On the principal surface of said substrate 1 there are formed, in succession, a thermal oxide film 2 and an interlayer insulation film 4, in which are opened a contact hole 5 and a mother alignment mark 6 constituting a stepped portion. A diffusion layer 3 extends from the bottom of said contact hole 5 to the interior of the semiconductor substrate 1. In said contact hole 5 and mother mark 6, there is selectively deposited a conductive material such as aluminium by a special CVD method to be explained later, thereby forming a wiring contact 7 and a filling 8 of conductive film. Also a wiring layer 9 composed of a non-selectively deposited conductive layer, is formed on said contact 7 and filling 8 of conductive film, and on the interlayer insulation film 4. In the semiconductor device of such structure, a recess 10 is formed in the wiring layer 9 above the mother mark 6, as a stepped portion corresponding to the form of the step in the mother mark 6, and is used as an alignment mark for auto-alignment in the patterning of the wiring layer 9. In said semiconductor device, since the recess 10 can be formed precisely at the position of the mother mark 6 mentioned above, wiring can be obtained precisely according to design, by a patterning operation utilising said recess 10 as the alignment mark. Since the patterning is not positionally aberrated, high-density wiring is possible. The material to be employed for electrode leads and wiring can be Al, an alloy principally composed of aluminium such as Al-Si, Al-Cu, Al-Si-Ti or Al-Si-Cu; Cu, Mo or W or alloys thereof. For filling the contact hole for electrode extraction, there is employed the Al-CVD method to be explained later. The insulation film is preferably composed of an inorganic material such as silicon oxide or silicon nitride formed by CVD or sputtering, PSG (phosphosilicate glass) or PBSG (borophosphosilicate glass), or an organic material such as polyimide. The wiring layer 9 on the insulation film 4 can be formed for example by forming a metal layer 9 by CVD or sputtering on the entire insulation film 4 followed by patterning of said metal layer 9 into the form of desired wiring by a photolithographic process. The stepped portion 10 for alignment has a step preferably of 40 nm (400 Å) or larger, and more preferably of 50 nm (500 Å) or larger. In the following there will be explained the preferred method for producing the semiconductor device shown in Fig. 3, with reference to Figs. 4A to 4C. The planar area of the stepped mother mark 6 is made sufficiently larger than that of the contact hole 5, in order to utilise the size dependence of film growth rate in the selective deposition in the CVD method to be explained later. More specifically, in selective metal deposition into holes of different sizes, the film growth rate in a smaller hole is higher than that in a larger hole. Consequently the film growth rate in this case is lower in the mother mark 6 than in the contact hole 5. The producing method for the semiconductor device shown in Fig. 3 will be explained in the following with reference to Figs. 4A to 4C. At first a thermal oxide film 2 is formed on the principal surface of a semiconductor substrate 1, and ion implantation with patterned photoresist and thermal treatment are conducted to form a diffusion layer 3 (Fig. 4A). Then an interlayer insulation film 4 is deposited on the thermal oxide film 2 and thermally treated, and a contact hole 5 and a stepped mother mark 6 are formed by contact patterning and etching in such a manner that said mother mark 6 is larger in planar area than the contact hole (Fig. 4B). Subsequently Al-Si is deposited by selective deposition in the contact hole 5 and the mother mark 6. Said deposition is terminated when the upper surface of the contact 7 in the contact hole 5 reaches the level of the upper surface of the interlayer insulation film 4. At this point, because of the above-mentioned size dependence of the selective deposition, the film 8 deposited in the mother mark 6 does not reach the upper surface of the interlayer insulation film 4, so that said film 8 is recessed in the surrounding insulation film 4 (Fig. 4C). Thus, at the contact hole 5, the upper surface of the contact 7 can be made planar with that of the interlayer insulation film 4, while the recessed form of the mother mark 6 can still be utilised for mask alignment in the patterning of the wiring layer 9. Subsequently the entire surface of the semiconductor substrate 1 shown in Fig. 4C is modified by RF plasma treatment, and is subjected to non-selective deposition of Al-Si by CVD, thereby forming a second wiring layer 9, whereby the recessed form of the mother mark 6 is repeated as a stepped recess 10 in the upper surface of said wiring layer 9 (Fig. 3). In such semiconductor device, desired wiring patterns can be formed precisely on the semiconductor substrate 1 by a patterning operation of the wiring layer utilising auto-mask alignment based on irradiation of the recess 10 with a laser beam and detection of the reflected light. As explained in the foregoing, the present invention is capable, based on selective metal deposition by a particular CVD method, of forming a portion faithfully corresponding to the shape of a stepped portion on the upper face of a conductive thin film as a mask alignment mark, whereby a photoresist pattern can be faithfully formed on the substrate surface by auto-alignment in wiring layer patterning. In the following there will be explained the film forming method which is adapted for use in the foregoing embodiment. Said film forming method is suitable for filling an aperture with a conductive material for the purpose of forming an electrode or alignment mark of the above-explained structure, and its depositing speed is dependent on the area of substrate exposed by said aperture. More specifically, the film forming method used in the present invention forms a deposition film on an electron-donating substrate by a surface reaction, utilising alkylaluminium hydride gas and hydrogen gas (said method being hereinafter called Al-CVD method). An aluminium film of particularly satisfactory quality can be obtained by employing monomethylaluminium hydride (MMAH) or dimethylaluminium hydride (DMAH) as the raw material gas and hydrogen gas as the reaction gas, and heating the substrate surface in the presence of a mixture of these gases. In the selective aluminium deposition, the substrate surface is preferably maintained, by direct or indirect heating, at a temperature at least equal to the decomposition temperature of alkylaluminium hydride but not exceeding 450°C, more preferably from 260 to 440°C. The substrate can be heated to the above-mentioned temperature range by direct or indirect heating, but an aluminium film of satisfactory quality can be obtained by maintaining the substrate in said temperature range by direct heating. For example, when the substrate surface temperature is maintained in the more preferred range of 260-440°C, a satisfactory aluminium film can be obtained at a deposition speed of 300-500 nm/min (3000-5000 Å/min), which is higher than that obtainable with resistance heating. Such direct heating, in which the substrate itself is heated by direct energy transfer from heating means, can be achieved by heating with a lamp, such as a halogen lamp or a xenon lamp. Also indirect heating can be achieved by resistance heating, for example by a heating resistor provided in a support member for supporting the substrate in a film forming chamber. The above-mentioned method, when applied to a substrate having both an electron-donating surface area and an electron non-donating surface area, forms aluminium single crystal with satisfactory selectivity, solely on the electron-donating surface area. Said aluminium is excellent in all the properties required for an electrode/wiring material, including a reduced frequency of hillocks and a reduced frequency of formation of alloy spikes. This is presumably because of facts that aluminium of satisfactory quality can be selectively formed on a conductive or semiconductive surface constituting an electron-donating surface and that said aluminium excellent in crystalline character, scarcely shows formation of alloy spikes resulting from eutectic reactions with the underlying material such as silicon. Said aluminium when employed as an electrode in the semiconductor device, shows advantages not anticipated in the prior technology and beyond the concept of the conventional aluminium electrode. As explained in the foregoing, this method provides monocrystalline structure in the aluminium deposited in an aperture formed for example in an insulation film and exposing therein an electron-donating surface such as a semiconductive substrate surface, but this Al-CVD method can also deposit selectively metal films principally composed of aluminium with satisfactory film quality, as will be explained in the following. For example, a conductive material such as Al-Si, Al-Ti, Al-Cu, Al-Si-Ti or Al-Si-Cu can be deposited by introducing, in addition to alkylaluminium hydride gas and hydrogen: Si-containing gas such as SiH₄, Si₂H₆, Si₃H₈, Si(CH₃)₄, SiCl₄, SiH₂Cl₃ or SiHCl₃; Ti-containing gas such as TiCl₄, TiBr₄ or Ti(CH₃)₄; and Cu-containing gas such as copper bisacetylacetonate (Cu(C₅H₇0₂)), copper bisdipivaloylmethanite (Cu(C₁₁H₁₉O₂)₂) or copper bishexafluoroacetylacetonate (Cu(C₅HF₆O₂)₂); in suitable combination, as a gaseous mixture. Also since said Al-CVD method is capable of selective film formation and providing satisfactory surface characteristics in the deposited film, there may be employed a non-selective film forming method in a next step to form an aluminium film or a metal film principally composed of aluminium on the selectively deposited aluminium film and on a insulation film composed for example of SiO₂, thereby obtaining a metal film widely usable for wirings of the semiconductor device. Examples of such metal film include combinations of selectively deposited Al, Al-Si, Al-Ti, Al-Cu, Al-Si-Ti or Al-Si-Cu and non-selectively deposited Al, Al-Si, Al-Ti, Al-Cu, Al-Si-Ti or Al-Si-Cu. The non-selective film deposition can be achieved, for example, by a CVD method other than said Al-CVD method or by sputtering. Film forming apparatus In the following there will be described a film forming apparatus adapted for use in electrode formation according to the present invention. Figs. 5 to 7 illustrate a continuous metal film forming apparatus adapted for use in the film forming method explained above. Said continuous film forming apparatus consists, as shown in Fig. 5 of a loading chamber 311, a CVD reaction chamber 312 serving as a first film forming chamber, an Rf etching chamber 313, a sputtering chamber 314 serving as a second film forming chamber, and an unloading chamber 315, which can mutually communicate by gate valves 310a - 310f in a sealed state from the external atmosphere and can be evacuated independently by vacuum systems 316a - 316e. The loading chamber 311 is provided to replace the atmosphere of the substrate prior to deposition with hydrogen gas, in order to increase the throughput. The next CVD reaction chamber 312 is to conduct the selective deposition by the aforementioned Al-CVD method onto the substrate under an ordinary or low pressure, is provided therein with a substrate holder 318 equipped with a heating resistor 317 for heating the substrate surface to be subjected to said film deposition at least within a temperature range of 200 - 450°C, and is further provided with a raw material gas line 319 for introducing raw material gas such as the alkylaluminium hydride gasified by bubbling with hydrogen gas in a bubbler 319-1 and another gas line 319' for introducing hydrogen gas as the reaction gas. The Rf etching chamber 313, for cleaning (etching) the substrate surface after selective deposition in argon atmosphere, is provided therein with a substrate holder 320 capable of heating the substrate at least within a temperature range of 100 - 250°C and an Rf etching electrode line 321, and is further provided with an argon gas supply line 322. The sputtering chamber 314, for non-selective deposition of a metal film by sputtering onto the substrate surface in argon atmosphere, is equipped therein with a substrate holder 323 for heating the substrate at least within a range of 200 - 250°C and a target electrode 324 for supporting a sputtering target 324a, and is also provided with an argon gas supply line 325. The final unloading chamber 315, for adjustment of the substrate after metal film deposition before the transfer of said substrate to the exterior, is capable of replacing the atmosphere with nitrogen. Fig. 6 shows another structure of the continuous metal film forming apparatus suitable for use in the above-explained film forming method, wherein the same components as those in Fig. 5 are represented by same numbers. The apparatus in Fig. 6 is different from that in Fig. 5 in that the substrate surface can be directly heated by halogen lamps 330 constituting direct heating means, and in that the substrate holder 312 is provided with projections 331 for supporting the substrate in a floating state for such direct heating. The direct heating of the substrate surface with such structure allows an increase in deposition speed, as explained already in the foregoing. The continuous metal film forming apparatus of the above-explained structure is in practice equivalent to a structure shown in Fig. 7 in which the loading chamber 311, CVD reaction chamber 312, Rf etching chamber 313, sputtering chamber 314 and unloading chamber 315 are mutually linked through a transfer chamber 326, wherein the loading chamber 311 also serves as the unloading chamber 315. Said transfer chamber 326 is provided, as shown in Fig. 7 with an arm 327 which can rotate in both directions AA and telescope in directions BB and can transfer the substrate in succession from the loading chamber 311 through the CVD reaction chamber 312, Rf etching chamber 313, sputtering chamber 314 to the unloading chamber-315 without exposure to the external atmosphere. Film forming procedure In the following there will be described the film forming procedure for forming electrodes and wirings according to the present invention. Figs. 9A to 9D are schematic perspective views showing the steps of said film forming procedure. At first described is the outline of said procedure. A semiconductor substrate 401 bearing an insulation film 402 with apertures 403, 404 in said film 402 is maintained at a surface temperature for example of 260-450°C in the film forming chamber, and aluminium is selectively deposited on the semiconductor exposed by said aperture by a thermal CVD method in a mixed atmosphere of alkylaluminium hydride gas such as DMAH and hydrogen gas. Naturally there may be deposited selectively a metal film principally composed of aluminium, such as Al-Si, by introduction of Si-containing gas, as explained before. Then, on the selectively deposited aluminium film and on the insulation film, a metal film composed solely or principally of aluminium is non-selectively deposited by sputtering. Subsequently the non-selectively deposited metal film is patterned into a desired shape to obtain the electrodes and wiring. In the following, said procedure will be explained in greater detail with reference to Figs. 6 and 9A - 9D. The substrate employed is for example a monocrystalline silicon wafer with an insulation film thereon, having apertures of different sizes therein. Fig. 9A schematically illustrates a part of said substrate, wherein shown are a monocrystalline silicon substrate 401 constituting a conductive substrate; a thermal silicon oxide film 402 constituting an insulation film; and apertures 403, 404 of different sizes. The aluminium film formation, for forming an electrode in the first wiring layer, is conducted in the following manner, with the apparatus shown in Fig. 6. At first the above-mentioned substrate is placed in the loading chamber 311, in which hydrogen is introduced to establish a hydrogen atmosphere, as explained before. The CVD reaction chamber 312 is evacuated by the vacuum system 316b to a pressure of ca. 1 x 10⁻⁶ Pa [1 x 10⁻⁸ Torr]. However the aluminium film formation is possible at a pressure higher than 1 x 10⁻⁶ Pa [1 x 10⁻⁸ Torr]. Then DMAH gas obtained by bubbling is supplied from the gas line 319, utilising H₂ as carrier gas. Also H₂ as the reaction gas is supplied from the second gas line 319', and the reaction chamber 312 is maintained at a predetermined pressure, by regulating the aperture of an unrepresented slow-leak valve. A typical total pressure is about 2.0 x 10² Pa [1.5 Torr], with a DMAH partial pressure of ca. 2.0 x 10² Pa [5.0 x 10⁻³ Torr]. Then the halogen lamps 330 are turned on to directly heat the wafer, and selective deposition of aluminium is thus conducted. The DMAH supply is terminated after the lapse of a predetermined deposition time. Said deposition time is a time required by the aluminium film on Si (silicon substrate 1) to reach the thickness of SiO₂ (thermal oxide film 2) and can be experimentally determined in advance. The substrate surface temperature is maintained at about 270°C by direct heating. By the above-explained steps, an Al film 405 is selectively deposited in the apertures as shown in Fig. 16B. The above-mentioned steps are called a first film forming step for electrode formation in the contact hole. Subsequently the CVD reaction chamber 312 is evacuated by the vacuum system 316b to a pressure of 7 x 10⁻¹ Pa [5x10⁻³ Torr] or lower, and the Rf etching chamber 313 is simultaneously evacuated to a pressure of 7x10⁻⁴Pa [5 x 10⁻⁶ Torr] or lower. After the chambers reach the above-mentioned pressures, the substrate is transferred from the CVD reaction chamber 312 to the Rf etching chamber 313 by the transfer means, by opening the gate valve 310c, and said gate valve 310c is subsequently closed. The Rf etching chamber 313 is evacuated by the vacuum system 316c to a Pressure of 10⁻⁴Pa [10⁻⁶ Torr] or lower, and is then maintained in argon atmosphere of 10-10⁻¹Pa [10⁻¹-10⁻³ Torr] by argon supply from the argon supply line 322. The substrate holder 320 for Rf etching is maintained at ca. 200°C, and an Rf power of 100 W is supplied for about 60 seconds to the Rf etching electrode 321, thereby inducing an argon discharge in the Rf etching chamber 313 and eliminating an unnecessary surface layer of the CVD deposition film by etching with argon ions. The etch depth in this case is about 10 nm (100 Å) calculated by oxide. Said Rf etching of the surface of the CVD film in the Rf etching chamber may however be dispensed with, since the surfacial layer of the CVD film, being transported in the vacuum, is free from oxygen etc. from the air. In such case, the Rf etching chamber 313 serves for a rapid temperature change if there is a large temperature difference between the CVD reaction chamber 312 and the sputtering chamber 314. After the completion of Rf etching, the argon supply is terminated, and the Rf etching chamber 313 is evacuated to 7x10⁻⁴Pa [5x10⁻⁶ Torr]. Then, after the sputtering chamber 314 is evacuated to 7x10⁻⁴Pa [5 x 10⁻⁶ Torr] or lower, the gate valve 310d is opened, then the substrate is transferred from the Rf etching chamber 313 to said sputtering chamber 314 by the transfer means, and said gate valve 310d is closed. Subsequently the sputtering chamber 314 is maintained in argon atmosphere of 10-10⁻¹Pa [10⁻¹-10⁻³ Torr] as in the Rf etching chamber 313, and the substrate holder 323 is maintained at 200 - 250°C. An argon discharge is inducted with a DC power of 5 - 10 KW to scrape the target of Al or Al-Si (Si: 0.5 %) with argon ions, thereby depositing Al or Al-Si non-selectively onto the substrate with a deposition speed of ca. 1 µm/min [10000 Å/min]. This step is called a second film forming step for forming a wiring to be connected with the electrode. After the formation of a metal film of about 500 nm [5000 Å] on the substrate, the supply of argon and DC power is terminated. The unloading chamber is evacuated to 7x10⁻¹ Pa [5x10⁻³ Torr] or lower, the substrate is transferred thereto by opening the gate valve 310e. After said gate valve is closed, nitrogen gas is introduced into the unloading chamber 311 to the atmospheric pressure, and the substrate is taken out by opening the gate valve 310f. The above-explained second film forming step forms an Al film 406 on the SiO₂ film 402 as shown in Fig. 16C. Wirings of a desired form can be obtained by patterning said Al film 406 as shown in Fig. 16D. [Experimental results] In the following there will be given experimental results showing the superiority of said Al-CVD process and of the quality of the aluminium film deposited in the aperture. There were employed plural substrates (sample 1-1) consisting of monocrystalline n-silicon wafers, bearing a thermally oxidized surfacial SiO₂ layer of a thickness of 800 nm [8000 Å] in in which apertures of different sizes from 0.25 x 0.25 to 100 x 100 µm² were patterned to expose the underlying monocrystalline silicon therein. These samples were subjected to aluminium film formation by the Al-CVD method, employing DMAH as the raw material gas and H₂ as the reaction gas with a total pressure of 2x10² Pa [1.5 Torr] and a DMAH partial pressure of 6.7x10⁻¹ Pa [5.0x10⁻³ Torr], and with a regulated power to the halogen lamps to obtain the substrate surface temperature within a range of 200 - 490°C by direct heating. The obtained results are summarized in Table. 1. As will be apparent from Tab. 1, aluminium could be deposited selectively with a deposition speed as high as 300-500 nm/min [3000-5000 Å/min.] at a substrate surface temperature of 260°C or higher, obtained by direct heating. The aluminium film obtained in the aperture within a substrate surface temperature range of 260-440°C showed satisfactory characteristics with no carbon content, a resistivity of 2.8 - 3.4 µΩcm, a reflectance of 90 - 95 %, a density of hillocks at least equal to 1.0 µm within a range of 0 - 10, and almost no spike formation (represented by frequency of destruction of junctions of 0.15 µm). On the other hand, within a substrate surface temperature-range of 200 - 250°C, the film quality is considerably superior to that in the prior technology though it is somewhat inferior to that in the temperature range of 260-440°C, but the deposition speed could not exceed 100-150 nm/min [1000-1500 Å/min.] and the throughput was in a relatively low range of 7 - 10 wafers/hr. Also at a substrate surface temperature equal to or higher than 450°C, the quality of the aluminium film in the aperture became deteriorated, with a reflectance of 60% or lower, a density of hillocks of at least 1 µm within a range of 10 - 10⁴ cm⁻² and a frequency of alloy spike formation of 0 - 30 %. In the following there will be explained how the above-explained method can be favorably applied to an aperture such as a contact hole. The following samples were subjected to aluminium film formation under the same conditions as those employed for the sample 1-1. A sample 1-2 was prepared by forming, on monocrystalline silicon constituting a first substrate surface material, a silicon oxide film of a thickness of 800 nm [8000Å] by CVD as a second substrate surface material, and patterning said silicon oxide film by a photolithographic process to form apertures of different sizes from 0.25 x 0.25 to 100 x 100 µm²,thereby localling exposing the monocrystalline silicon surface therein (said sample being hereinafter represented as "CVD SiO₂ (or simply SiO₂)/monocrystalline silicon"). Also there were prepared: a sample 1-3 of a boron-doped oxide film obtained by normal pressure CVD (hereinafter BSG)/monocrystalline silicon; a sample 1-4 of a phosphor-doped oxide film obtained by normal pressure CVD (hereinafter PSG)/ monocrystalline silicon; a sample 1-5 of phosphor- and boron-doped oxide film obtained by normal pressure CVD (hereinafter BSPG)/ monocrystalline silicon; a sample 1-6 of a nitride film obtained by plasma CVD (hereinafter P-SiN)/monocrystalline silicon; a sample 1-7 of a thermal nitride film (T-SiN)/ monocrystalline silicon; a sample 1-8 of a nitride film obtained by low pressure CVD (LP-SiN)/monocrystalline silicon; and a sample 1-9 of a nitride film obtained by ECR (ECR-SiN)/monocrystalline silicon. Furthermore there were prepared samples 1-11 to 1-179 (sample numbers 1-10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110, 120, 130, 140, 150, 160 and 170 are lacking) by taking all the combinations of following first substrate surface materials of 18 kinds and second substrate surface materials of 9 kinds. The first substrate surface materials employed were monocrystalline silicon (mono-Si), polycrystalline silicon (poly-Si), amorphous silicon (a-Si), tungsten (W), molybdenum (Mo), tantalum (Ta), tungsten silicide (WSi), titanium silicide (TiSi), aluminium (Al), aluminium silicon (Al-Si), titanium-aluminium (Al-Ti), titanium nitride (Ti-N), copper (Cu), aluminum-silicon-copper-(Al-Si-Cu), aluminium -palladium (Al-Pd), titanium (Ti), molybedenum silicide (Mo-Si), and tantalum silicide (Ta-Si). Also the second substrate surface materials employed were T-SiO₂, SiO₂, BSG, PSG, BPSG, P-SiN, T-SiN, LP-SiN, and ECR-SiN. In all these samples, there could be obtained aluminium films comparable in quality to that of the aforementioned sample 1-1. Then an aluminium film was non-selectively deposited by sputtering on the substrates subjected to selective aluminium deposition as explained above and was patterned. The aluminium film obtained by said sputtering and the selectively deposited aluminium film in the aperture showed satisfactory contact with high electrical and mechanical durability, because of the excellent surface state of the latter aluminium film in the aperture.

Claims: A method of producing an alignment mark which method comprises: providing a semiconductor substrate (1) having at its surface an insulating layer (4) with a contact hole (5) and a further aperture (6) formed therein: depositing a conductive material (7) selectively to fill said contact hole (5); and depositing wiring material (9) on said insulating layer (4) and on said conductive material (7) filling said contact hole (5); which method is characterised in that: said further aperture (6) exposes an area of the substrate (1) larger than the area of the substrate (1) exposed by said contact hole (5); and said depositing of conductive material is performed by selective chemical vapour deposition using an alkylaluminium hydride and hydrogen, so that although said contact hole (5) is filled, said aperture (6) is only partially filled; whereby an alignment mark (10) is produced over the partially filled aperture (6,8) as said wiring material (9) is deposited. A method according to claim 1, wherein said alkylaluminium hydride is dimethylaluminium hydride. A method as claimed in either preceding claim wherein at least one of a Si-, Ti-,or Cu-containing gas is mixed with said alkylaluminium hydride and hydrogen to deposit selectively Al-Si, Al-Ti, Al-Cu, Al-Si-Ti, or Al-Si-Cu as the selectively deposited conductive material. A method of producing a wired semiconductor device using an alignment mark for wiring pattern alignment, which method includes: performing a method of producing an alignment mark (10) as claimed in any one of the preceding claims; and patterning said wiring material (9) using said alignment mark (10) for pattern alignment. A method as claimed in claim 4 wherein automatic pattern alignment is performed using laser light reflected from said alignment mark.

Inventors: MONMA GENZO, OKABE TAKAHIKO, YUZURIHARA HIROSHI, MONMA, GENZO, OKABE, TAKAHIKO, YUZURIHARA, HIROSHI, Monma, Genzo, c/o Canon Kabushiki Kaisha, Okabe, Takahiko, c/o Canon Kabushiki Kaisha, YUZURIHARA, HIROSHI, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1991
Main classification: H01L23
IPC codes: H01L23