Power semiconductor device

Abstract: A p-type emitter layer (22) has the main surface and the opposite surface. An n⁺-type buffer layer (20) formed on the main surface of the emitter layer (22). An anode electrode (24) formed on the opposite surface of the emitter layer (22). An n-type base layer (10) formed on the buffer layer (20). The n-type base layer (10) has an impurity concentration lower than that of the buffer layer (20), and permits the tip of a depletion layer reaches the buffer layer (20), in the vicinity of the maximum value of the rated voltage. A p-type base layer (12) formed on the n-type base layer (10). An n-type emitter layer (14) formed on the p-type base layer (12). An cathode electrode (16) formed on the n-type emitter layer (14).

Description: This invention relates to a semiconductor device, and more particularly to a high-power bipolar composite element. Bipolar composite elements, such as GTOs or IGBTs, are generally used for large current-carrying semiconductor devices. Such large current-carrying semiconductor devices using bipolar composite elements are employed in inverters, converters, or the like, where those composite elements consume an extremely large amount of power. Therefore, to obtain a semiconductor device with higher efficiency and better performance, it is necessary to minimize the power consumption of elements used. The amount of power consumed by elements is given by the following equation: P = V TM ·I TM ·D + f(E on + E off ) where P is the amount of power consumed, V TM the forward voltage drop, I TM the on-current, D the duty, f the frequency, E on the turn-on loss, and E off the turn-off loss. In equation (1), the term V TM ·I TM ·D is known as the steady state loss, and the term f(E on + E off ) the switching loss. High withstand-voltage elements (e.g., GTOs), which are used in devices whose rated blocking voltage exceeds 4500V, are composed of four layers: the n-type cathode layer, p-base layer, n-type base layer, and p-type anode layer. With this arrangement, to reduce the steady state loss, it is desirable to make the n-type base layer thinner. Just thinning the layer, however, permits the depletion layer extending within the n-type base layer to reach the p-type emitter layer, causing punch-through. To overcome this problem, devices that have an n⁺-type buffer layer of a relatively high concentration between the n-type base and p-type anode layers are widely used (see, for example, PESC '88 RECORD, Proceedings of the 19th Annual IEEE Power Electronics Specialists Conference, Kyoto, JP, vol. 2, pages 903-907). The formation of the n⁺-type layer buffer between the n-type base and p-type anode layers enables the n-type base layer to be thinned without creating a punch-through problem. For example, in the case of a GTO whose rated blocking voltage is 6000V, the presence and absence of the n⁺-type buffer layer makes the following difference: [Absence of the n⁺-type buffer layer] With the base-layer specific resistance ranging from 300 Ω·cm to 360 Ω·cm, the thickness of the n-type base layer must be approximately 970 µm. [Presence of the n⁺-type buffer layer] With the n-type base-layer specific resistance of 600 Ω·cm, the required thickness of the n-type base layer reduces to approximately 550 µm. With the 550-µm-thick n-type base layer of a specific resistance of 600 Ω·cm, however, the depletion layer will reach the n⁺-type buffer layer at voltages on the order of 1200 to 1700 V. This causes a high electric field to be applied to the n⁺-type buffer layer in practical use (at voltages on the order of 3900 to 4800 V). When the GTO is turned off in this state, a large quantity of holes from the p-type anode layer are injected into the n-type base layer, slowing the decay of the tail current. With a high voltage during turning off, the large tail current creates a large amount of switching loss. That is, as the n-type base layer becomes thinner, the steady state loss decreases, while the switching loss increases. The object of the present invention is to provide a semiconductor device that overcomes the problem that the thinning of the n-type base layer by formation of the n⁺-type buffer layer increases the switching loss. The foregoing object is accomplished by a semiconductor device, comprising: an emitter layer of a first conductivity type having a main surface and an opposite surface; a buffer layer of a second conductivity type formed on the main surface of the emitter layer of the first conductivity type; an anode electrode formed on the opposite surface of the emitter of the first conductivity type; a first base layer of the second conductivity type which is formed on the buffer layer of the second conductivity type with the impurity concentration of the first base layer being lower than that of the buffer layer, a second base layer of the first conductivity type formed on the first base layer; an emitter layer of the second conductivity type formed on the base layer of the first conductivity type; and a cathode electrode formed on the emitter layer of the second conductivity type, characterized in that and in which said first base layer has thickness and impurity concentration chosen so that the tip of the depletion layer reaches the buffer layer at a reverse bias voltage across the junction between said first and second base layers having a value in the vicinity of the maximum value of the rated voltage; This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a sectional view for a semiconductor device according to an embodiment of the present invention; Fig. 2 shows an impurity concentration profile for a cross section taken along line 2-2 of Fig. 1; Figs. 3 and 4 each show impurity concentration profiles for conventional semiconductor devices; Fig. 5 illustrates the relationship between the steady state loss and switching loss of a GTO with a rated blocking voltage of 6000 V; Fig. 6 is a sectional view for a shorted-anode GTO according to a second embodiment of the present invention; and Fig. 7 illustrates the relationship between the specific resistance and thickness of the n-type base layer for achieving the present invention. Referring to the accompanying drawings, embodiments of the present invention will be explained. Fig. 1 is a sectional view for a GTO according to a first embodiment of the present invention. As illustrated, on one surface of an n-type base layer 10 whose specific resistance is on the order of 300 to 360 Ω·cm, a p-type base layer 12 is formed. Formed on the p-type base layer 12 are n-type cathode layers 14, on which cathode electrodes 16 are formed. Each of the cathode electrodes 16 is connected to a cathode terminal K. Also formed on the p-type base layer 12 is a gate electrode 18, which is connected to a gate terminal G. On the other surface of the n-type base layer 10, an n⁺-type buffer layer 20 of a high impurity concentration is formed. Formed on the n⁺-type buffer layer 20 is a p-type anode layer 22, on which an anode electrode 24 is formed. The anode electrode 24 is connected to an anode terminal A. With such an arrangement, to obtain, for example, a rated blocking voltage of 6000 V, the n-type base layer 10 in this invention has a specific resistance of on the order of 300 to 360 Ω·cm and a thickness of approximately 650 µm. With the n-type base layer 10, when the voltage applied across the anode and cathode is raised to the range from 3900 to 4800 V, 65 to 80% of the rated blocking voltage, the tip of the depletion layer extending within the n-type base layer 10 is beginning to reach the n⁺-type buffer layer 20. Fig. 2, illustrating this situation, shows an impurity concentration profile for a cross section taken along line 2-2 of Fig. 1, in which the growth of the depletion layer is depicted. Line I in Fig. 2 indicates the growth of the depletion layer at the rated voltage or at 6000 V, whereas line II shows the depletion layer growth at the turn-off voltage in practical use or in the voltage range of 3900 to 4800 V. Fig. 3 shows an impurity concentration profile for a conventional GTO with an n⁺-type buffer layer. In Fig. 3, numeral 110 indicates the n-type base layer, 112 the p-type base layer, 114 the n-type cathode layer, 120 the n⁺-type buffer layer, and 122 the p-type anode layer. As with Fig. 2, line I in Fig. 3 indicates the growth of the depletion layer at the rated voltage or at 6000 V, whereas line II shows the depletion layer growth at the turn-off voltage in practical use or in the voltage range of 3900 to 4800 V. As illustrated, in the conventional GTO with the n⁺-typebuffer layer, the depletion layer shown by line II is controlled by the n⁺-type buffer layer 114 so as not to come into contact with the p-type anode layer. During turning off, an extremely high electric field is applied to the n⁺-buffer 114, which permits a large quantity of holes from the p-type anode layer 112 to be injected into the n-base layer 110, thereby increasing the switching loss. Fig. 4 shows an impurity profile for a conventional GTO without an n⁺-type buffer layer. The same parts in Fig. 4 and Fig. 3 are indicated by the same reference characters. As illustrated, a conventional GTO without an n⁺-type buffer layer has the very thick n-type base layer 110, so that the depletion layer distribution shown by line II prevents a high electric field from being applied to and around the interface between the n-type base layer and p-type anode layer. The thick n-type base layer 110, however, increases the steady state loss. With a GTO according to this invention, as shown by line II in Fig. 2, the depletion layer is beginning to reach the n⁺-type buffer layer 20 at the turn-off voltage in practical use, or in the range of 65 to 80% of the rated blocking voltage. This prevents the injection of holes from the p-type anode layer into the n-type base layer, which raised a problem in conventional devices as explained in Fig. 3. Accordingly, the switching loss can be reduced. In the range larger than approximately 80% of the rated blocking voltage, as shown by line I in Fig. 2, the growth of the depletion layer is suppressed by the n⁺-type buffer layer 20, which causes no punch-through. Therefore, it is unnecessary to form a thick n-type base layer unlike the conventional device as described in Fig. 4, which reduces the steady state loss. As described above, by causing the tip of the depletion layer to reach the n-type base layer 10 in the voltage range of 65 to 80% of the rated blocking voltage or near the maximum voltage during turn-off, both the steady state loss and switching loss can be reduced sufficiently, which decreases the power consumption, the sum of both losses. Fig. 5 shows the relationship between the steady state loss and switching loss of a GTO with a rated blocking voltage of 6000 V. In Fig. 5, line III indicates the results of a conventional GTO with a buffer layer, whereas line IV represents the results of a conventional GTO without a buffer layer. Line V shows the results of a GTO according to this invention. As seen from Fig. 5, with the GTO according to this invention, the sum of the switching loss and the steady state loss can be minimized, which reduces the power consumption. Fig. 6 is a sectional view for a shorted-anode GTO according to a second embodiment of this invention. The same parts in Fig. 6 and Fig. 1 are indicated by the same reference characters and the explanation will be only focused on the different parts. The GTO shown in Fig. 6 is obtained by forming an additional n-type shorted-anode layer 26 between the n⁺-type buffer layer 20 and anode electrode 24 in the GTO of Fig. 1. With the shorted-anode GTO, the tip of the depletion layer extending within the n-type base layer 10 is also caused to reach the n⁺-type buffer layer 20 in the range of 65 to 80% of the rated blocking voltage. For example, to obtain a rated blocking voltage of 6000 V, the thickness of the n-type base layer 10 is set for approximately 650 µm and its specific resistance for on the order of 300 to 360 Ω·cm. The impurity profile for the cross section taken along line 2-2 of Fig. 6 is the same as the first embodiment or the profile as shown in Fig. 2. As described, this invention is also applicable to shorted-anode GTOs. Fig. 7 illustrates the relationship between the specific resistance and thickness of the n-type base layer which enables the tip of the depletion layer to reach the n⁺-type buffer layer in the range of 65 to 80% of the rated blocking voltage in a GTO according to the present invention. As shown in Fig. 7, for a rated blocking voltage of 4500 V, it is desirable to set the specific resistance for on the order of 200 to 250 Ω·cm and the thickness for on the order of 450 to 550 µm. Similarly, for a rated blocking voltage of 6000 V, it is desirable to set the specific resistance for on the order of 300 to 380 Ω·cm and the thickness for on the order of 620 to 750 µm; and for a rated blocking voltage of 9000 V, it is favorable to set the specific resistance for on the order of 450 to 550 Ω·cm and the thickness for on the order of 940 to 1100 µm. Although not shown in Fig. 7, for a rated blocking voltage of 5000 V, it is preferable to set the thickness of the n-type base layer for approximately 520 µm and its specific resistance for on the order of 220 to 260 Ω·cm; for a rated blocking voltage of 7000 V, it is preferred to set the thickness for approximately 700 µm and the specific resistance for on the order of 340 to 400 Ω·cm. While in the above embodiments, this invention is applied to a GTO with a rated blocking voltage of 6000 V, it is not restricted to this and may be applied to other bipolar composite elements including IGBTs.

Claims: A semiconductor device comprising an emitter layer (22) of a first conductivity type having a main surface and an opposite surface, a buffer layer (20) of a second conductivity type formed on the main surface of said emitter layer (22) of the first conductivity type, an anode electrode (24) formed on the opposite surface of said emitter (22) of the first conductivity type, a first base layer (10) of the second conductivity type formed on said buffer layer (20) of the second conductivity type, said base layer (10) of the second conductivity type having an impurity concentration lower than that of said buffer layer (20), a second base layer (12) of the first conductivity type formed on said first base layer (10), an emitter layer (14) of the second conductivity type formed on said second base layer (12), and a cathode electrode (16) formed on said emitter layer (14) of the second conductivity type, characterized in that: said first base layer (10) has thickness and impurity concentration chosen so that the tip of the depletion layer reaches said buffer layer (20) at a reverse bias voltage across the junction between said first and second base layers having a value in the vicinity of the maximum value of the rated blocking voltage. The semiconductor device according to claim 1, characterized in that said vicinity of the maximum value of the rated blocking voltage is in the range of 65% to 80% of the rated voltage. The semiconductor device according to claim 1, characterized by further comprising a gate electrode (18) formed on said base second layer (12). The semiconductor device according to claim 1, characterized by further comprising a shorted-anode region (24) of the second conductivity type formed in said emitter layer (22) of the first conductivity type between said buffer layer (20) and said anode electrode (24). The semiconductor device according to claim 1, characterized in that said first base layer (10) of the second conductivity type has a resistivity ranging from 200 to 250 Ω·cm and a thickness ranging from 450 to 550 µm, when said rated blocking voltage is 4500 V. The semiconductor device according to claim 1, characterized in that said first base layer (10) of the second conductivity type has a resistivity ranging from 300 to 380 Ω·cm and a thickness ranging from 620 to 750 µm, when said rated blocking voltage is 6000 V. The semiconductor device according to claim 1, characterized in that said first base layer of the second conductivity has a resistivity ranging from 450 to 550 Ω·cm and a thickness ranging from 940 to 1100 µm, when said rated blocking voltage is 9000 V.

Inventors: FUJIWARA TAKASHI C O INTELLECT, HIYOSHI MICHIAKI C O INTELLECT, MATSUDA HIDEO C O INTELLECTUAL, SUZUKI HISASHI C O INTELLECTUA, FUJIWARA, TAKASHI, C/O INTELLECTUAL PROPERTY DIV., HIYOSHI, MICHIAKI, C/O INTELLECTUAL PROPERTY DIV., MATSUDA, HIDEO, C/O INTELLECTUAL PROPERTY DIV., SUZUKI, HISASHI, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: H01L29
IPC codes: H01L29