Cache memory system and operating method

Abstract: In a method for cleaning data elements in a memory system (10) accessible by a bus master, a first data element is transferred between the bus master and a fast memory (20) while writing the first element to a dirty element register (526) within the memory system (10). The first element is then cleaned by writing it from the register (526) to a slow memory (12) within the system (10) without delaying memory access requests for the fast memory (20).

Description: This invention relates to computer memory systems. The performance of a computer system can be enhanced by the use of a memory hierarchy. For example, a three tiered memory can be constructed from low, medium, and fast memories. A low speed memory may be a magnetic disk for low cost, bulk storage of data. A medium speed memory may be constructed from DRAMs for use as the computer system's main memory. A fast memory may employ SRAMs for use as a processor cache memory. The theory behind memory hierarchy is to group code (instructions) and other data to be executed by the system processor in the highest speed memory. Since fast memory is typically the most expensive memory available, economics dictate that it be relatively small. Main memory consisting of DRAMs is denser and less expensive than a cache memory with SRAMs, and can therefore be significantly larger than the cache memory. During operation, instructions and other data are transferred from system memory to the cache memory in order to have quick access to the variables of the currently executing program. As additional data, not in the cache, is required, such data is transferred from the main memory by replacing selected data in the cache. Various replacement algorithms are utilized to determine which data is replaced. An efficiently operating cache architecture exhibits a high ratio of "hits" to accesses. A "hit" occurs when data requested is in the cache. A number of factors influence the hit ratio. The dominant factor is the locality of reference of the code being executed. In other words, if the code is located in proximate physical locations in memory, the hit ratio will be higher than if the code is widely distributed throughout memory. Another factor influencing the hit ratio of a cache is the number of devices having access to the memory. If only a single bus master, such as the system processor, has access to the memory, the data stored in the cache can be controlled to achieve a reasonably high hit ratio. However, when more than a single bus master has access to the memory through the same cache, the cache can bounce back and forth between requests from the bus masters, greatly reducing the hit ratio. In other words, the cache is non-discriminatory, with the demands of the system processor and other bus masters affecting the cache equally. One operation can significantly impact the data make-up of the cache. For example, data cached in response to memory accesses from a non-host CPU bus master will overwrite data needed by the host processor. Another factor affecting the hit ratio relates to the fact that both code and non-code data are cached. Blocks of data in the system memory are mapped into different physical locations in the cache. If each block of data in system memory may be mapped to only a single location, the cache is known as a direct mapped cache. Set associative mapping involves each block of data being mapped to more than a single location. For example, if each block of data may be mapped to either of two locations, the cache is known as two-way set associative. Irrespective of the number of locations available for a system memory block, when both code and non-code data are being cached, there will be overlap in their respective mappings. Thus, when both code and non-code data are cached, there can be significant thrashing which takes place as data is replaced in response to memory accesses. An issue related to cache hits is whether or not a data element in a cache is valid and/or dirty. A data element is valid as long as no corresponding element in the system memory is more current. If the data element in the cache contains multiple data bytes, the concept of validity may extend down to the byte level. In other words, it is possible for certain selected bytes of a data element to be valid while other bytes in the same element are invalid. A data element may become wholly or partially invalid if all or some of its data bytes, respectively, are written to -the system memory from a bus master while the data element resides in the cache. A data element in a cache is dirty if it is more current than a corresponding element in the system memory. A data element becomes dirty when a bus master writes the element to a cache and not to system memory. A cache "overflow" is the condition created when a dirty and valid data element in a cache is overwritten by a bus master. To prevent the dirty and valid element from becoming lost when overwritten, the element must be written immediately into the system memory from the cache. An overflow write can force several individual writes, depending on the line size of the cache. The paper "Intel Advanced Information 82385 High Performance 32-Bit Cache Controller" October 1987, Intel Santa Clara order number 290143-002 discloses a cache controller which is a peripheral for the Intel 80386 microprocessor. It stores a copy of frequently accessed code and data from main memory in a local cache memory. A dual bus architecture allows other masters to access system resources while the 80386 microprocessor operates mainly out of its cache. Cache coherency is preserved by monitoring the system bus address lines by means of a bus watching mechanism at no cost to system or local throughput. Further, in IBM Technical Disclosure Bulletin volume 23, numbered 12, May 1981, pages 5426-5427, there is described a cache system implementing preventive cast out operations in cache hierarchies, wherein a change bit of a block written back to main memory is reset. It is an object of the present invention to provide a computer memory system and a method for operating same, wherein data elements may be cleared in an efficient manner. Therefore, according to one aspect of the present invention, there is provided a method for cleaning data elements in a memory system including a system memory accessible by a bus master through a system bus connected therebetween, a cache accessible by the bus master through the system bus connected therebetween, and a register connected to said bus, said method comprising the steps of: writing a dirty data element to said register while transferring said dirty data element between said bus master and said cache; directly routing address information and control bits corresponding to a memory access request from said bus master to said cache over a second bus while isolating said system bus, said register and said system memory from said cache and said bus master such that said system bus is open during a first period and is available for a transfer of a dirty data element from said register to said system memory, without delaying said memory access request from said bus master; and providing a signal to reset a dirty bit in response to said transfer of a dirty data element from said register to said system memory. According to another aspect of the present invention, there is provided a memory system comprising: a system memory for storing data elements accessible by a bus master; a system bus connecting said system memory with said bus master for transferring data elements; a cache connected to said system bus; a register connected to said system bus for holding a dirty data element transferred between said cache and said bus master; a second bus connected to said bus master and to said cache for directly routing to said cache address information and control bits corresponding to a memory access request from said bus master to said cache; and means for providing a signal to reset a dirty bit in response to a transfer of a dirty data element from said register to said system memory; wherein said system bus, said register, and said bus master are isolated from said cache and said bus master such that said system bus is open during a first period and is available for said transfer of a dirty data element from said register to said system memory, without delaying a memory access request from said bus master. A memory system and method according to the present invention has the advantage that the need to locate and retrieve all valid and dirty elements in the cache is avoided, hence resulting in a reduction in wait states for bus masters. A further advantage is the avoidance of the need for additional logic to prioritize and efficiently locate and retrieve all such valid and dirty elements residing in the cache. One embodiment of the present invention will now be described by way of example, with reference to the accompanying drawings, in which:- Figure 1 is a block diagram of a high performance computer memory system according to one form of the present invention; and Figures 2A and 2B are a diagram of a cache and dirty element register according to one form of the present invention. Figure 1 shows a block diagram of a computer memory system 10. System 10 includes a system memory 12 which in a preferred embodiment consists of dynamic random access memory (DRAM) chips. The data stored in memory 12 can be generally divided into code data (instructions) and non-code data. As used herein, the term "data" refers to information and includes both code data (instructions) and non-code data. Memory 12 is connected to other parts of a computer system (not shown) by bus means 14. Memory system 10 is designed for use with two or more bus masters, although it is operable with a single master. More particularly, it is designed for use with a host processor such as an Intel processor 386, 386sx or 486 in combination with other bus masters or devices which will compete with the host processor for access to memory system 10. Access to DRAM 12 is controlled by DRAM controller 22 which is located within bus means 14. Memory system 10 also includes an internal cache 16, a pre-fetch cache 18 and a write buffer cache 20, each connected to bus 14. In a preferred form, internal cache 16 is a 4K byte, four-way set associative cache, pre-fetch cache 18 is a 128 byte, direct-mapped cache, and write buffer cache 20 is a 128 byte, two-way set associative cache. A feature of the caches is that their functionality may be varied depending upon the host processor type (386, 386sx or 486) utilized. However, certain features of the caches do not vary. For example, internal cache 16 holds data which is selected solely on the basis of memory accesses by the host processor. In other words, internal cache 16 is dedicated to the host processor and will not be affected by memory accesses by other bus masters. It will be appreciated that each of the caches is readable by any of the bus masters. Thus, even though cache 16 will not allow data writes therein based on memory accesses by other than the system processor, it will be read by another bus master if requested data happens to reside therein. It will further be appreciated that each of the caches snoops (observes) any data writes not intended for it in order to invalidate its contents upon snoop hits, thereby ensuring coherency. Another immutable feature of the caches is that pre-fetch cache 18 contains solely code data pre-fetched from DRAM 12. Furthermore, it only prefetches code based on a memory access by the host processor. In operation, whenever the system processor requests code data not already in the pre-fetch cache, the next sequential 128 bytes of code are pre-fetched into cache 18 as a queue in anticipation of subsequent requests for code. Write buffer cache 20 only buffers data to be written into DRAM 12. It is not merely a write buffer, but is a cache which, as mentioned above, can be read by any bus master. However, it will not cache data from DRAM 12. The present invention, including its operation with respect to cache 20, will be discussed more fully in reference to Figure 2 below. An important feature of the caches is the separation of the functionality of each of the caches such that the selective definition of those functions based on the processor type is readily effected. By this insight, the present system is able to achieve or exceed the performance of a system utilizing a single cache many times larger than the cumulative size of the subject caches. With respect to the selective definition of function based on processor type, for a system employing a 486 system processor, write buffer cache 20 buffers data writes by any bus master other than the system processor. For a system employing a 386 or 386sx system processor, internal cache 16 holds only code data and is a read only cache for the system processor, and write buffer cache 20 buffers data writes by any bus master including the system processor. The operational characteristics of the caches are defined through self configuration at power-on time based on information relating to the type of host processor present. DRAM controller 22 supports fast page mode for accesses to DRAM 12. Fast page mode is a well known technique for speeding up accesses to DRAM by activating a row line in a memory page and then strobing sequential column lines to transfer data into or out of DRAM. DRAM 12 is divided into pages which contain either code or non-code data. A register associated with DRAM 12 is located either in DRAM 12 or DRAM controller 22 and holds the page address of a most recently accessed page. In effect, the system provides a bias towards code pages or non-code pages depending upon the type of processor connected to the system. For example, if the system processor is a 486, the address of the most recently accessed code address page is held in the register. In operation, both code and non-code data pages in DRAM 12 can be randomly accessed. If a code page is accessed on one cycle and a non-code page is accessed on the next cycle, the address of the code page is held in a register while the non-code page is accessed. Immediately after the non-code page access, the address in the register is used to reopen the code page. In contrast, if the system processor is a 386 or 386sx, the address of the most recently accessed non-code address page is held in the register. The combination of selective open page bias, fast page mode accesses and multiple caches provides increased system performance. Write buffer cache 20 is a two-way set associative cache. The non-code data region of memory may be divided into three areas known as list, heap and stack. Data blocks in memory are reserved for the list, heap and stack, each of which has its own organization and purpose. For example, a stack is a set of data elements, only one of which can be accessed at a time. The list data is primarily read and generally not written to. In structured programs, a high percentage of writes occur to the stack with the second most data writes occurring to the heap. By proper assignment of the heap and stack data blocks in DRAM and mapping respective blocks to opposing sets in the two-way set associative cache, increased operational efficiency can be realized. Furthermore, an open page bias in the DRAM for non-code data will effectively be an open page bias for list data. In this manner, operational efficiency is further enhanced. Figures 2A and 2B show more detail of write buffer cache 20 connected to bus 14. As noted previously, cache 20 is a two-way set associative cache, in a preferred embodiment. Cache 20 includes two cache ways 500 and 502. Each way has a data storage region 504 and 506, respectively, and a tag RAM 508 and 510, respectively. Data storage regions 504 and 506 store data elements and tag RAMs 508 and 510 store the tag portion of the address for the data element in corresponding locations in regions 504 and 506, respectively. A dual port register file 512 is associated with cache ways 500 and 502 and contains status information for each data element stored in cache 20. For example, it stores a dirty flag bit for each data element. A valid flag bit for each data byte is stored together with each data byte in regions 504 and 506. Cache 20 is also connected to an address/control bus 514 which receives selected address and control signals directly from accessing bus masters prior to the information being provided over bus 14. Tristate devices 520 and 524 are provided between cache 20 and bus 14 to isolate cache 20 from bus 14 and other devices connected to bus 14 at certain times, as will be discussed more fully below. An important feature of the present invention is dirty element register 526 which is connected directly to bus 14. Register 526 holds a single data element, its address, its "way" in write buffer cache 20, valid bits for each byte of the data element, and a dirty/valid bit (DV) which indicates if a dirty and valid data element exists in register 526. The operation of register 526 will next be described with respect to cache 20. However, it will be clear to those skilled in the art that register 526 can be effectively utilized with any cache. In operation, any dirty data element being transferred into or out of cache 20 is written to register 526. For example, any data element written to cache 20 from a bus master is by definition considered "dirty", and a dirty element flag in dual port register file 512 is set. Thus, each data element written to cache 20 from a bus master is also written to register 526. A data element being read from cache 20 may or may not be dirty, depending upon whether or not it was previously cleaned. If it is dirty, then the corresponding dirty flag in dual port register file 512 will be set which will signal register 526 to store the subject data element. If it is not dirty, it will not be written to register 526. The transfer of the data element from or to cache 20 occurs at the same time as the data element is written to register 526. Once the data element is in register 526, an attempt is made to clean it by writing it to DRAM 12. The write to DRAM 12 will not delay memory access requests for cache 20 or any of the other caches or system memory. One technique that can be employed involves the monitoring of bus 14 and transmitting the data element on a free or open cycle. In a preferred embodiment, the memory system is synchronized to a clock cycle. The fastest data reads take two cycles (when there is a cache hit). When a request comes into the bus interface, predetermined address and control bits get routed directly to the cache 20 over bus 514 to start a memory access. This occurs in the first period during which period the bus 14 is idle or inactive. If there is a cache hit, the data element is placed on bus 14 during the second cycle. Since, bus 14 is open (not used) during the first period, tristate devices 520 and 524 and the bus interface (Figure 1) isolate bus 14, register 526 and DRAM 12 from cache 20 and the bus master, and the dirty data element in register 526 is transferred to DRAM 12 during this first period. By transferring the dirty data element to DRAM 12 during open cycles, a memory access request from a bus master is not delayed. The valid bits in register 526 are used by DRAM controller 22 to transfer only valid bytes of the subject data element to DRAM 12. If the data element is written to DRAM 12 during the open period, a signal is provided to dual port register file 512 to remove or reset the dirty flag bit. If there are no open cycles on bus 14 prior to the next access of cache 20, the next data element (if dirty) transferred to or from cache 20 overwrites the element in register 526. Thus, it is possible that a dirty data element will not be cleaned when it is transferred to register 526. However, the present invention provides the opportunity to clean the element each time it so transferred. Moreover, since the write buffer cache 20 is filled only by data writes from a bus master, the type of data tends to be accessed more than once. This provides many opportunities to clean each data element. By keeping the data elements in cache 20 generally clean, the present invention avoids significant cache overflow problems which occur when dirty data in the cache must be overwritten.

Claims: A method for cleaning data elements in a memory system (10) including a system memory (12) accessible by a bus master through a system bus (14) connected therebetween, a cache (20) accessible by the bus master through the system bus (14) connected therebetween, and a register (526) connected to said bus (14), said method comprising the steps of: writing a dirty data element to said register (526) while transferring said dirty data element between said bus master and said cache (20) directly routing address information, and control bits corresponding to a memory access request from said bus master to said cache 20 over a second bus (514) while isolating said system bus (14), said register (526) and said system memory (12) from said cache (20) and said bus master such that said system bus (14) is open during a first period and is available for a transfer of a dirty data element from said register (526) to said system memory (12), without delaying said memory access request from said bus master; and providing a signal to reset a dirty bit in response to said transfer of a dirty data element from said register (526) to said system memory (12). A memory system (10) comprising: a system memory (12) for storing data elements accessible by a bus master; a system bus (14) connecting said system memory with said bus master for transferring data elements; a cache (20) connected to said system bus (14); a register (526) connected to said system bus (14) for holding a dirty data element transferred between said cache (20) and said bus master; a second bus (514) connected to said bus master and to said cache (20) for directly routing to said cache (20) address information and control bits corresponding to a memory access request from said bus master to said cache (20); and means for providing a signal to reset a dirty bit in response to a transfer of a dirty data element from said register (526) to said system memory (12); wherein said system bus (14), said register (526), and said bus master are isolated from said cache (20) and said bus master such that said system bus (14) is open during a first period and is available for said transfer of a dirty data element from said register (526) to said system memory (12), without delaying a memory access request from said bus master.

Inventors: ELLIS JACKSON L, ELLIS, JACKSON L.
Applicants: INTEL CORP, INTEL CORPORATION
Application year: 1991
Main classification: G06F12
IPC codes: G06F12