Logic circuit including a fault detection circuit

Abstract: A circuit for detecting when a fault condition has occurred includes an input stage (12, 18, 14, 24, 20) responsive to a logic signal supplied to an input of the circuit for providing an output logic signal at an output thereof. An output stage (26), including a pulldown circuit (30, 32), responsive to the output logic signal of the input stage, for providing an output logic signal at an output of the circuit. A fault detection circuit (34, 36) coupled to the output of the input stage and to the output stage for forcing the output of the circuit to a predetermined logic state when the pulldown circuit of the output stage is defective.

Description: Background of the Invention This invention relates to detection circuits and, in particular, to a fault detection circuit which senses pull down current from an ECL logic circuit thereby pulling an output of the ECL logic circuit to a known logic state when a fault has occurred. Most, if not all, ECL circuits utilize a pull down circuit to provide the proper logic high and low voltage levels at an output. Further, ECL circuits are susceptible to a type of AC related failure that typically remains undetected under traditional stuck at fault coverage testing. An AC failure can occur when random process defects cause an open pull down circuit within the ECL circuit. Such defects can be related to contacts, vias, metal interconnect, resistor and transistor structures that have been isolated. For current state of the art VLSI ECL circuits, the probability of occurrence for this type of AC defect can reach 10,000 ppm. Therefore, if these defects are not detected, they can pose serious problems to the operation of any integrated circuit which includes the ECL circuit therein. European Patent Application No. EP-A-0063407 provides examples of fault detection circuitry that can detect internal as well as interconnect faults of various types between integrated circuit chips. Hence, a need exists for a circuit that detects when an AC failure occurs in a logic circuit. EP-A-0 055 571 discloses circuits according to the preambles of Claims 1 and 2. Summary of the Invention Accordingly, the present invention seeks to provide an improved logic circuit for detecting when a failure occurs. In accordance with a first aspect of the present invention there is provided a circuit as defined in Claim 1. In accordance with a second aspect of the present invention there is provided a circuit as defined in Claim 2. An exemplary embodiment of the present invention will be better described with reference to the accompanying drawings. Brief Description of the Drawings FIG. 1 is a detailed schematic diagram illustrating an ECL logic circuit incorporating a fault detection circuit in accordance with the present invention. FIG. 2 is a detailed schematic diagram illustrating an ECL logic circuit incorporating an alternate embodiment of a fault detection circuit in accordance with the present invention. Detailed Description of the Present Invention Referring to FIG. 1, a detailed schematic diagram illustrating an ECL logic circuit incorporating an AC fault detection circuit is shown comprising transistor 12 having a collector coupled by resistor 14 to a first supply voltage terminal at which the operating potential V CC is applied. The base of transistor 12 is coupled to terminal 16 at which voltage potential V IN is applied, while the emitter of transistor 12 is coupled to the emitter of transistor 18. Further, the emitters of transistors 12 and 18 are coupled by current source 20 to a second supply voltage terminal at which the operating potential V EE is applied. The base of transistor 18 is coupled to terminal 22 at which voltage potential V BB is applied, while the collector of transistor 22 is coupled by resistor 24 to operating potential V CC . Transistor 26 has a collector coupled to operating potential V CC ; a base coupled to the collector of transistor 18, and an emitter coupled to output terminal 28 for providing voltage potential V out . The emitter of transistor 26 is further coupled to the collector of transistor 30, the latter having an emitter coupled by resistor 32 to operating potential V EE . The fault detection circuit of FIG. 1 is comprised of transistor 34 and resistor 36. Resistor 36 is coupled between the base of transistor 30 and terminal 38 where voltage potential V CS is applied. The collector of transistor 34 is coupled to the collector of transistor 18, while the base of transistor 34 is coupled to terminal 40 at which voltage potential V 2 is applied. Finally, the emitter of transistor 34 is coupled to the emitter of transistor 30. In operation, the input stage comprised of transistors 12 and 18, resistors 14 and 24 and current source 20 function in a well known manner to provide a voltage at the collector of transistor 18 which is a function of the voltage level appearing at terminal 16. The voltage at the collector of transistor 18 subsequentially provides output voltage V out at output terminal 28, via output transistor 26. To more clearly illustrate, assume that voltage V IN exceeds voltage V BB such that substantially all the current provided by current source 20 flows through transistor 12 and resistor 14, and substantially zero current flows through transistor 18 and resistor 24. Therefore, the voltage at the base of output transistor 26 is substantially equal to operating potential V CC and correspondingly the voltage V out is substantially equal to V CC - V be(tran. 26) . Or more succinctly, a logic high voltage level applied at the base of transistor 12 results in a logic high voltage level provided at the emitter of transistor 26 and output terminal 28. On the other hand, assume that voltage V BB exceeds voltage V IN such that substantially all the current provided by current source 20 flows through transistor 18 and resistor 24, and substantially zero current flows through transistor 12 and resistor 14. Therefore, the voltage at the base of output transistor 26 is substantially equal to V CC - (I 20 x R 24 ). Further, voltage V out can be calculated in equation 1; V out = V CC - (I 20 x R 24 ) - V be(tran. 26) where V out is the voltage at output terminal 28; I 20 is the current provided by current source 20; R 24 is the resistance of resistor 24; and V be(tran. 26) is the base-emitter voltage of transistor 26. More succinctly, a logic low voltage level applied at the base of transistor 12 results in a logic low voltage level provided at the emitter of transistor 26 and output terminal 28. The active pull down circuit comprised of transistor 30 and resistor 32 is necessary to bias transistor 26 with predetermined current 12 and to achieve the proper output logic voltage levels at output terminal 28. Under normal operation, the fault detection circuit comprised of transistor 34 and resistor 36 is transparent to the ECL logic circuit and provides virtually no increase in power and a negligible impact on size and performance. This is so because voltage V 1 will be sufficiently large enough to render transistor 34 non-operative during normal operation. Further, the voltage drop across resistor 36 is negligible since the base current of transistor 30 is typically small under proper operation. However, if a fault condition occurs that causes abnormal operation of the active pull down circuit comprised of transistor 30 and resistor 32, transistor 34 will be rendered operative, current I 1 will flow through transistor 34, and output voltage V out will be forced to a known logic state. The fault condition could occur as a result of at least two types of defects as will described below. First assume a first type of defect is present which causes an open base, an open emitter or shorted base to emitter condition such that I B(tran. 30) or I E(tran. 30) substantially equals zero. This will allow transistor 34 to be rendered operative since transistor 30 is essentially rendered non-operative and voltage V 2 will be greater than voltage V 1 . Transistor 34 will then function to draw a predetermined current (I 1 ) from operating potential V CC thereby pulling the base of transistor 26 to a predetermined voltage, via the voltage drop across resistor 24, such that a known logic state will be provided at output terminal 28, for example a logic low. Secondly, assume a second type of defect is present which causes an open collector condition for transistor 30 where I C(tran. 30) substantially equals zero and, therefore, I B(tran. 30) = I E(tran. 30) . This condition may result from a break in the metal contact connecting the emitter of transistor 26 to the collector of transistor 30. For this condition, the base current of transistor 30 is typically beta times the base current of transistor 30 for normal operating conditions. Therefore, the value of resistor 36 should be selected such that the voltage at the emitters of transistors 30 and 34 (V 1 ) will be sufficiently negative to forward bias transistor 34. Similar to the first type of defect, transistor 34 will then function to draw a predetermined current from operating potential V CC thereby pulling the base of transistor 26 to a predetermined voltage, via the voltage drop across resistor 24, such that a known logic state will be provided at output terminal 28, for example a logic low. It should be noted that the value of resistor 36 is chosen such that under normal operation, I B(tran. 30) causes a negligible voltage drop across resistor 36. However, for the second defect where I B(tran. 30) = I E(tran. 30) , the increased I B(tran. 30) causes a sufficient voltage drop across resistor 36 to make the voltage at the emitter of transistor 30 (V 1 ) such that the differential voltage (V 2 - V 1 ) is greater than the base emitter turn on voltage of transistor 34 in order to render transistor 34 operative. Referring to FIG. 2, a detailed schematic diagram illustrating an ECL logic circuit incorporating an alternate embodiment of a fault detection circuit is shown. It is understood that components similar to those of FIG. 1 are indicated by the same reference numbers. The circuit of FIG. 2 further comprises a passive pull down circuit comprised of resistor 44 which is coupled between the emitters of transistors 26 and 34 and operating potential V EE . Also, the fault detection circuit of FIG. 2 comprises transistor 34 whereby the fault detection circuit of FIG. 1 comprises transistor 34 and resistor 36. In operation, voltage V 2 is selected to insure that transistor 34 is rendered non-operative during normal operation. Therefore, the current through transistor 26 and resistor 44 will provide a sufficient voltage drop across resistor 44 such that the differential voltage (V 2 - V 1 ) is less than the base emitter turn on voltage of transistor 34 in order to render transistor 34 non-operative. However, if an open circuit condition exists between the emitter of transistor 26 and resistor 44, voltage V 2 is also selected to allow transistor 34 to become operative. Therefore, the differential voltage (V 2 - V 1 ) will be greater than the base emitter turn on voltage of transistor 34 in order to render transistor 34 operative. Further, as afore aforedescribed, transistor 34 will then function to draw a predetermined current (I 1 ) from operating potential V CC thereby pulling the base of transistor 26 to a predetermined voltage, via the voltage drop across resistor 24, such that a known logic state will be provided at output terminal 28, for example a logic low. By now it should be apparent from the foregoing discussion that a novel fault detection circuit has been provided for forcing the output of a logic circuit to a known logic state when a fault condition occurs.

Claims: A logic circuit having an input and an output, comprising: an input stage responsive to a logic signal supplied to the input of the circuit for providing an output logic signal at an output thereof; an output stage having a first input, the output stage responsive to said output logic signal of said input stage at the first input, for providing an output logic signal at the output of the circuit wherein said output stage includes a resistor (32) and a first transistor (26) having a collector, a base and an emitter, said collector being coupled to a second supply voltage terminal, said base being coupled to said output of said input stage, and said emitter being coupled to the output of the circuit; characterized by detection means coupled both to said input stage and said output stage for forcing the output of the circuit to a predetermined logic state responsive to a fault condition occurring in said output stage, the detection means comprising: a transistor (34) having a collector, a base and an emitter, said collector being coupled to said output of said input stage, said base being coupled to a first terminal at which a first reference potential is applied, and said emitter being coupled to a first supply voltage terminal via said resistor (32) and to the output of the circuit; and a resistor (36) coupled between a second input of said output stage and a second terminal at which a second reference voltage is applied; wherein said output stage further includes a second transistor (30) having a collector, a base and an emitter, said collector being coupled to said emitter of said first transistor of said output stage, said base being coupled to said second terminal by said resistor (36) of said detection means, and said emitter being coupled to said first supply voltage terminal and to said emitter of said transistor (34) of said detection means, said resistor (32) of said output stage being coupled between said emitter of said second transistor of said output stage and said first supply voltage terminal. A logic circuit having an input and an output, comprising: an input stage responsive to a logic signal supplied to the input of the circuit for providing an output logic signal at an output thereof; an output stage responsive to said output logic signal of said input stage, for providing an output logic signal at the output of the circuit wherein said output stage includes: a transistor (26) having a collector, a base and an emitter, said collector being coupled to a second supply voltage terminal, said base being coupled to said output of said input stage, and said emitter being coupled to the output of the circuit and to said emitter of said transistor of said detection means; and a resistor (44) coupled between said emitter of said transistor of said output stage and said first supply voltage terminal characterized by detection means coupled both to said input stage and said output stage for forcing the output of the circuit to a predetermined logic state responsive to a fault condition occurring in said output stage, the detection means comprising: a transistor (34) having a collector, a base and an emitter, said collector being coupled to said output of said input stage, said base being coupled to a first terminal at which a first reference potential is applied, and said emitter being coupled to a first supply voltage terminal via a resistor (44) and to the output of the circuit. A circuit according to any preceding claim wherein said input stage includes: a first transistor (12) having a collector, a base and an emitter, said collector being coupled to said second supply voltage terminal, said base being coupled to the input of the circuit; a second transistor (18) having a collector, a base and an emitter, said collector being coupled to said second supply voltage terminal and to said output of said input stage, said base being coupled to a third terminal at which a bias voltage is supplied, and said emitter being coupled to said emitter of said first transistor of said input stage; a first resistor (14) coupled between said collector of said first transistor of said input stage and said second supply voltage terminal; a second resistor (24) coupled between said collector of said second transistor of said input stage and said second supply voltage terminal; and a current source (20) coupled between said emitters of said first and second transistors of said input stage and said first supply voltage terminal.

Inventors: DOMER STEVEN M, HOLLSTEIN ROGER L, SHAPIRO FREDERICK B, DOMER, STEVEN M., HOLLSTEIN, ROGER L., SHAPIRO, FREDERICK B.
Applicants: MOTOROLA INC, MOTOROLA, INC.
Application year: 1991
Main classification: H03K19
IPC codes: H03K19