IC Tester

Abstract: In an IC tester for testing a memory built in a logic IC, a memory test pattern generator (20) includes a waveform control pattern memory (20B) and a logical comparison pattern memory (20C), and waveform control pattern data (PB) and logical comparison control pattern data (PC) from these waveform control pattern memories are supplied to a waveform controller (32) and a logical comparator (33) via a pattern selector (25) capable of selectively switchable to respective pins of the IC under test (36).

Description: BACKGROUND OF THE INVENTION The present invention relates to an IC tester which is capable of testing a logical IC device having one or more memories built therein. Some of logical IC's have mainly logical circuits formed therein but there are also logical IC's having a memory or memories built therein in addition to logical circuits. In this type of IC terminals leading to the memory can all be connected to external pins by switching the mode of operation from a logical circuit test mode to a memory test mode. Accordingly, the incorporated memory can be tested independently of the logical circuits by setting the memory test mode. An IC tester according to the pre-characterizing portion of claim 1 is disclosed in the document GB-A-2 108 277. Fig. 1 shows the construction of a conventional IC tester for testing IC's of this kind. The IC tester is provided with a logic test pattern generator 10 for generating logic test patterns for testing a logical circuit of an IC 36 under test and a memory test pattern generator 20 for generating memory test patterns for testing a memory or memories built therein. The IC tester is adapted to be switched between the logical circuit test mode and the memory test mode so as to be able to test the logical circuit and the memory independent of each other. The logic test pattern generator 10 comprises a logic test pattern memory 10A, a waveform control pattern memory 10B and a logical comparison control pattern memory 10C. The logic test pattern memory 10A has logic test pattern data stored therein for performing a logic test on the IC 36 under test and the pattern data is read out therefrom as logic test pattern data PLA of plural channels which are supplied through OR circuits 61 to a waveform formatter 31. Generally, the number of channels is set to be equal to the number of pins of an IC under test which is deemed to have the largest number of pins among IC's to be tested. The waveform control pattern memory 10B has waveform control pattern data for logic test stored therein and the logic test waveform control pattern data is read out therefrom as logic test waveform control pattern data PB of plural channels which are supplied to a waveform controller 32. The logical comparison control pattern memory 10C has logical comparison control pattern data for logic test stored therein and the logic test logical comparison control pattern data is read out therefrom as logic test logical comparison control pattern data PC of plural channels which are supplied to a logical comparison part 33. The waveform formatter 31 generates a logical waveform for testing the logical circuit of an IC 36 under test, based on the logic test pattern data PLA read out of the logic test pattern memory 10A and provided via OR circuits 61 and a timing signal TS provided from a timing generator 40. The logical waveform is supplied as a logic test pattern signal to the IC 36 via a group of drivers 35. The waveform control pattern data PB read out of the waveform control pattern memory 10B is input into the waveform controller 32 to effect ON-OFF control of each driver of the driver group 35. That is, when a logic test pattern signal is applied to terminal pins of the IC under test 36, the corresponding drivers are controlled to assume the ON state (i.e. the activated state) and when a response signal is taken out of the IC 36, the driver is controlled to enter the OFF state (i.e. the state of a high output impedance). The comparison control pattern data PC read out of the logical comparison control pattern memory 10C is input into the logical comparison part 33, wherein it is controlled on a bitwise basis (i.e. for each pin) whether or not to make a comparison between the logic of the response output signal from the IC under test 36, decided by a logic decision comparator group 37, and expected value pattern PD derived from the logic test pattern data PLA. Reference numeral 38 denotes a failure analysis memory for storing the results of logical comparison from the logical comparison part 33. The timing generator 40 applies the timing signal TS to the waveform formatter 31, the waveform controller 32 and the logical comparison part 33 to time their operations. The timing generator 40 also applies an operating clock CK to a sequence controller 50. Based on the operating clock CK supplied from the timing generator 40, the sequence controller 50 generates a control signal such as a pattern address, which is applied to the test pattern memory 10A, the waveform control pattern memory 10B and the logical comparison control pattern memory 10C to control their readout sequences to read out therefrom the respective pieces of pattern data PLA, PB and PC. Also in the case of testing a memory in the IC 36, the control signal such as a pattern address, provided from the sequence controller 50, is used to read out the waveform control pattern data PB and the comparison control pattern data PC from the logic test pattern generator 10 and, in this instance, the logic test pattern data PLA is not read out, but instead memory test pattern data PMA is read out of the memory test pattern generator 20 by the same control signal. The memory test pattern data PMA is composed of address pattern data which is applied to the address input pins of the IC under test 36, input data pattern data which is provided to the data input pins of the IC 36 and control pattern data which controls whether to effect a write or read in each test cycle. These pieces of data are respectively provided at predetermined ones of output terminals Q 0 to Q i of the memory test pattern generator 20 irrespective of the pin array of the IC under test 36. The memory test pattern data PMA is selected by a pattern selector 25, for each pin, in accordance with terminal select addresses set in a pattern select register 26 and is provided via the OR circuit 61 to the waveform formatter 31. The pattern selector 25 is made up of multiplexers MP 1 to MP n provided corresponding to pins T 1 to T n of the IC under test 36 and each having connected thereto all the output terminals Q 0 to Q i of the memory test pattern generator 20. The pattern select register 26 is made up of terminal address registers R 1 to R n connected to control terminals C of the multiplexers MP 1 to MP n , respectively. Prior to the test of the IC 36 an address is set in each of the terminal address registers R 1 to R n for specifying any one of the output terminals Q 1 to Q i which is to be selected by each of the multiplexers MP 1 to MP n in accordance with the pin array of the IC 36. Thus, selected pieces of the address pattern data and the input data pattern data are provided to the address and input pins of the IC under test 36 according to the setting of the pattern select register 26. The sequence controller 50 provides to an inhibit terminal INH of the pattern selector 25 a control signal GS which represents whether the test currently under way is a logic test or memory test. When the control signal GS is, for example, a "1" representing a logic test, the pattern selector 25 inhibits its all outputs, preventing erroneous outputting of signals from the memory test pattern generator 20. Conventionally, during the memory test the memory test pattern data PMA selected by the pattern selector 25 for each pin is provided to the waveform formatter 31, and at the same time, the waveform control pattern data PB and the comparison control pattern data PC are provided to the waveform controller 32 and the logical comparison part 33 from the logic test pattern generator 10, effecting waveform control and control of the logical comparison. The waveform control and the logical comparison must be conducted for each pin, and consequently, when the positions of pins for testing a memory differ with the types of IC's to be tested, it is necessary that programs for generating the waveform control pattern data PB and the comparison control pattern data PC be prepared for each type. In practice, some memory built-in type logic IC devices have such arrangements of terminals as shown in Figs. 2 through 4. In the IC 36 depicted in Fig. 2 there are arranged memory test address input pins 361 on a side A containing a first pin T 1 , memory test data output pins 362 on a side B, and memory test data input pins 363 and a read/write control signal input pin 364 on a side D containing a last pin T n . These pins 361 through 364 are connected to a memory 36M incorporated in the IC 36. The other remaining pins are those for a logic circuit 36L shown as an area except the memory 36M in the IC 36. The IC depicted in Fig. 3 has memory test data I/O pins 365 arranged on the side A containing the first pin T 1 , the read/write control signal input pin 364 on the side B and the memory test address input pins 361 on the side D. The IC 36 shown in Fig. 4 has built therein two memories 36M1 and 36M2. In this instance, there are arranged the address input pins 361 of the memory 36M1 and the data I/O pins 365 of the memory 36M2 on the side A, the data output pins 362 of the memory 36M1 and the read/write control signal input pin 364 of the memory 36M2 on the side B and the data input pins 363 and the read/write control signal input pin 364 of the memory 36M1 and the address input pins 361 of the memory 36M2 on the side D. In the case where the arrangement of pins differs with the types of IC's as mentioned above, it is necessary in the prior art to change the setting of the pattern select register 26 for each type and to prepare pattern generation programs of the waveform control pattern memory 10B and the logical comparison control pattern memory 10C for each type. This inevitably calls for increased storage capacities of the test pattern memory 10B and the logical comparison control pattern memory 10C. Besides, it is troublesome to manage the pattern generation programs prepared for each type of the IC to be tested. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an IC tester which permits reduction of the overall storage capacity of the logic test pattern generator and allows ease in the management of pattern generation programs. This object is achieved with an IC tester as claimed in claim 1. Specific embodiments of the invention are subject-matter of the dependent claims. With the arrangement of the present invention, since the waveform control pattern data and the logical comparison control pattern data can be selected by the pattern selectors for each pin and then output, programs in the memory test pattern generator for the generation of the memory test pattern data, the waveform control pattern data and the logical comparison control pattern data can be produced independently of the arrangement of pins of the IC under test. Consequently, programs for the generation of pattern data in the memory test pattern generator need not be prepared for each type of the IC to be tested. This affords reduction of the capacities of the memories forming the logic test pattern generator. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram for explaining the prior art; Fig. 2 is a block diagram for explaining the internal construction of a memory built-in type logic IC; Fig. 3 is a block diagram for explaining the internal construction of another memory built-in type logic IC; Fig. 4 is a block diagram for explaining the internal construction of still another memory built-in type logic IC; Fig. 5 is a block diagram illustrating an embodiment of the present invention; Fig. 6 is a block diagram illustrating a modified form of the present invention; Fig. 7 is a block diagram showing a pattern selector and a pattern select memory in an h-th channel in the embodiment of Fig. 6; Fig. 8 is a block diagram illustrating another embodiment of the present invention; and Fig. 9 is a block diagram illustrating still another modification of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig. 5 illustrates in block form an embodiment of the present invention. As is the case with the prior art example of Fig. 1, this embodiment includes the logic test pattern generator 10, the memory test pattern generator 20, the pattern selector 25, the pattern select register 26, the waveform formatter 31, the waveform controller 32, the logical comparison part 33, the driver group 35, the IC under test 36, the logic decision comparator group 37, the timing generator 40 and the sequence controller 50. These pieces of data PMA, PB, PC and PLA are each output over n channels in anticipation of an IC which is assumed to have the largest number n of pins among IC's to be tested. For example, the driver group 35 includes n drivers accordingly and the logic decision comparator group 37 is also made up of n comparators. All the other constituent elements 25, 26, 31, 32, 33, 61, 62 and 63 are also provided in units of n channels. The constituent elements are interconnected via n channel lines. In the present invention the memory test pattern generator 20 comprises a memory test pattern generation part 20A, a waveform control pattern memory 20B and a logical comparison control pattern memory 20C. As in the prior art example of Fig. 1, the memory test pattern generation part 20A generates the memory test pattern data PMA composed of address and data patterns to be provided to the IC under test, and the waveform control pattern data PB and the comparison control pattern data PC are read out of the waveform control pattern memory 20B and the logical comparison control pattern memory 20C, respectively. These pieces of data PMA, PB and PC are provided at output terminals Q 0 to Q i , Q i+1 to Q j and Q j+1 to Q k , respectively. The pattern selector 25 is formed by a multiplexer group including three multiplexers MA h , MB h and MC h (where h = 1, 2, ..., n) for each channel. The multiplexer MA h has connected to its input all the output terminals Q 0 to Q i of the memory test pattern generation part 20A, the multiplexer MB h has connected to its input all the output terminals Q i+1 to Q j of the waveform control pattern memory 20B and the multiplexer MC h has connected to its input all the output terminals Q j+1 to Q k of the logical comparison control pattern memory 20C. The pattern select register 26 is formed by a register group including three registers RA h , RB h and RC h for each channel. These three registers RAh, RBh and RCh have terminal select addresses SAah, SAbh and SAch set therein respectively. These terminal select addresses SAah, SAbh and SAch serve to cause the multiplexers MAh, MBh and MCh to select and connect one of the terminals Qo to Qi to its output, one of the terminals Qi+1 to Qj to its output, and one of the terminals Qj+1 to Qk to its output, respectively. The terminal select addresses are provided as terminal select control signals to the multiplexers MA h , MB h and MC h . When the control signal GS applied from the sequence controller 50 to the inhibit terminal INH of the pattern selector 25 is a "1" representing that the logic test is under way, the pattern selector 25 inhibits its all outputs. During the memory test the memory test pattern data PMA, the waveform control pattern data PB and the comparison control pattern data PC are output from the memory test pattern generation part 20A, the waveform control pattern memory 20B and the logical comparison pattern memory 20C, respectively. These pieces of data PMA, PB and PC are selected by the pattern selector 25 for each channel in accordance with the terminal select addresses SAah, SAbh and SAch set in the pattern select register 26, and the memory test pattern data PMA thus selected for each channel is input into the waveform formatter 31 via the OR circuit 61. In the waveform formatter 31 the memory test pattern data PMA and the timing signal TS from the timing generator 40 are used to produce a memory test pattern signal in an actual waveform as in the prior art, and the memory test pattern signal is applied via the driver group 35 to the corresponding channel of the IC under test 36. At the same time, the waveform control pattern data PB and the comparison control pattern data PC are sorted by the pattern selector 25 for each pin and are supplied to the waveform controller 32 and the logical comparison part 33 in the channel corresponding to the desired pin. As described above, according to the present invention, it is possible to determine, by the setting of the pattern select register 26, which signal is applied to which pin of the IC under test 36; so that pattern data for the memory test to be conducted alone, irrespective of the pin arrangement of the IC 36, needs only to be stored in each of the waveform control pattern memory 20B and the logical comparison control pattern memory 20C of the memory test pattern generator 20 and different test pattern data need not be used for each type of the IC under test. Accordingly, the waveform control pattern memory 20B and the logical comparison control pattern memory 20C of the memory test pattern generator 20 may be small in capacity. On the other hand, since the waveform control pattern data PB and the logical comparison control pattern data PC for executing the memory test need not be stored in the logic test pattern generator 10, the capacities of the waveform control pattern memory 10B and the logical comparison control pattern memory 10C can be reduced substantially. Fig. 6 illustrates a modified form of the present invention. In this embodiment the pattern select register 26 in the Fig. 5 embodiment is substituted with a pattern select memory 261 and an address AD is produced by the sequence controller 50 and is used to access the pattern select memory 261 to read out therefrom three terminal select addresses for each channel, by which the selective connections of the multiplexers MA h , MB h and MC h of the pattern selector 25 are controlled. The pattern select memory 261 has n memory planes MP 1 to MP n which are accessed by the common address AD. As seen from Fig. 7 which shows the multiplexers MA h , MB h and MC h and the memory plane MP h corresponding to the h-th channel, there are stored in the memory planes MP 1 to MP n of each channel at addresses AD1, AD2, ..., corresponding to the type of the IC the terminal select addresses SAah, SAbh and SAch for setting the selective connections of the three multiplexers MA h , MB h and MC h for each channel in accordance with the pin arrangement of the IC. With such a construction, by providing the address AD corresponding to the type of the IC 36 from the sequence controller 50 to the pattern select memory 261, it is possible to set therein the selective connections of the multiplexers MA h , MB h and MC h corresponding to the pin arrangement of the IC 36. By storing different pieces of terminal select address data in the pattern select memory 261 at a plurality of addresses, it is possible to change the address AD from the sequence controller 50 to thereby change the terminal select address data which is read out of the pattern select memory 261. Accordingly, the terminal select state of the pattern selector 25 can be switched in a desired step in the test sequence. Thus, the two memories 36M1 and 36M2 of different pin arrangements, built in the IC as shown in Fig. 4, can be tested successively at high speed. The IC 36 may sometimes have a construction in which the address and data are alternately input into the memory 36M via a common input pins and are latched in a memory address latch and a memory data data latch alternately with each other. Also in such a case, according to the Fig. 6 embodiment, the pin connection can be switched as required during the generation of a test pattern. In some cases, the IC 36 may have a construction in which only one input pin is provided for each of the address and the data to be supplied to the memory 36M and the address and data are input serially into an address register and a data register, respectively. In the memory test of such an IC, parallel addresses and parallel data are respectively converted into serial form by sequentially changing the selective terminal connection in the pattern selector 25 and are each provided to one channel lines corresponding to each of the address input pin and the data input pin. This can be done by sequentially switching those of the inputs to the multiplexers of the two channels which correspond to the parallel addresses and the parallel data. In the embodiment of Fig. 6 the pieces of pattern data PLA, PB and PC from the logic test pattern generator 10 and the pieces of pattern data PMA, PB and PC from the memory test pattern generator 20 are switched by switching circuits 601, 602 and 603 for each channel in response to a switching control signal SC and then provided to the waveform formatter 31, the waveform controller 32 and the logical comparison part 33. The control signal GS from the sequence controller 50 is applied to all of n gates G 1 to G n provided in the pattern selector 25 to enable and disable them during the memory test and during the logic test. As is evident placed under control of the sequence controller. In this embodiment the main sequence control part 50A applies a start signal SS to the memory test pattern sequence control part 50B upon completion of the test of the logical circuit part (not shown) of the IC by a series of patterns. The memory test pattern sequence control part 50B responds to the start signal SS to execute a program portion for generating a series of memory test patterns, by which the memory test pattern generator 20 is controlled to make the memory test by the series of patterns. Upon completion of the execution of the program portion for generating the series of patterns, the memory test pattern sequence control part 50B applies an end signal ES to the main sequence control part 50A and stops the execution of the memory test pattern generation program. When supplied with the end signal ES, the main sequence control part 50A executes again the program portion for generating a series of logic test patterns for the logic test. Thereafter, the logic test and the memory test are repeated using the same procedure until all the necessary tests of the IC are completed. In the embodiment of Fig. 8 the logic test pattern generation program for the main sequence control part 50A may be created taking into account only the step in which to conduct the logic test and the contents of the memory test to be conducted in the step need not be taken into consideration. The memory test pattern generation program for the memory test pattern sequence control part 50B may be created taking into account only the contents of the memory test to be conducted. This allows ease in the production of the pattern generation programs for the IC test. Moreover, since during the memory test the logic test pattern generator 10 can be from Fig. 7 in which the memory plane MP h corresponding to the h-th channel is shown, there are stored in the pattern select memory 261 the switching control data SC for switching control of the switching circuits 601, 602 and 603 for each channel as well as the terminal select addresses SAah, SAbh and SAch. The switching data SC read out of the pattern select memory 261 is provided to the switching circuits 601, 602 and 603 via the gates G 1 to G n which are enabled only during the memory test. During the logic test the outputs SC of the gates G 1 to G n are, for example, all "0's," by which all the channels of the switching circuits 601, 602 and 603 are connected to the side of the logic test pattern generator 10. During the memory test the channels corresponding to the switching circuits 601, 602 and 603 are connected to the logic test pattern generator 10 or memory test pattern generator 20, depending on whether the switching control data SC set in each of the memory planes MP 1 to MP n is a "0" or "1." Fig. 8 illustrates a modified form of the Fig. 5 embodiment. The sequence controller 50 in Fig. 5 is made up of a main sequence control part 50A which operates in accordance with the common operating clock CK from the timing generator 40 and a memory test pattern sequence control part 50B. In the case of an IC having a memory built therein, the logic part and the memory part are each tested after completion of the test of either one of them. Alternatively, the memory test is conducted for each area of the memory and consequently for each sequence of patterns and the logic test is also conducted for each sequence of patterns; in this case, the memory test and the logic test for each sequence of patterns are made alternately with each other. The test sequence is operated by a different sequence, it is possible to operate the logical circuit of the IC under test simultaneously with its memory to test the influence of the former on the latter and to test an IC of a construction in which no memory test can be conducted unless a signal is applied to the pin for logical circuit use in a certain sequence. In the embodiment of Fig. 8 the sequence controller 50 in the embodiment of Fig. 5 is modified, and it is apparent that the sequence controller 50 in the embodiment of Fig. 6 can similarly be modified. Fig. 9 illustrates another embodiment of the present invention in which a further modification of the main sequence control part 50A in Fig. 8 is applied to the embodiment of Fig. 6. In this embodiment the main sequence control part 50A comprises a logic test pattern sequence control part 50AA and a link control part 50C connected thereto. The link control part 50C is also connected to the memory test pattern sequence control part 50B. The link control part 50C applies the pattern generation start signal SS to the sequence control parts 50AA and 50B in a predetermined order and, at the same time, supplies the pattern selector 25 with the control signal GS which represents whether the memory test or logic test is to be conducted. When supplied with the pattern generation start signal SS, the sequence control parts 50AA and 50B each execute a program portion for generating a series of patterns and, upon completion of the pattern generation, apply the end signal ES to the link control part 50C. Thus, the pattern generation program for the logic test pattern sequence control part 50AA can be produced without regard to the memory test. A sequence control program for the link control part 50C defines only the order of steps for conducting the memory test and the logic test in a series of test sequence, and hence the program can be created with more ease. In the above, when the IC under test 36 is a high-speed IC, its input and output pins are often provided for the exclusive use therefor, and in this instance, the ON/OFF state of the driver 35 is not changed for each test cycle in a series of tests. That is, there is no need of generating waveform control pattern data by use of the logic test pattern generator 10 and the memory test pattern generator 20 but instead fixed n-bit data for specifying the ON/OFF state of each driver 35 corresponding to the type of the IC 36 is set in a register (not shown) provided in the waveform controller 32, and during the test of the IC 36 the n-bit data is provided to a control terminal of the driver 35 to fixedly control its ON/OFF state. In test equipment for testing such high-speed IC's, it is possible to omit the waveform control pattern memories 10B and 20B, the multiplexers MB 1 to MB n , the OR circuit 62 and the switching circuit 602 used in the embodiments of Figs. 5, 6, 8 and 9. As described above, according to the present invention, since the waveform control pattern and the logical comparison pattern for the memory test are obtained by reading them out of the test pattern generator 20, the waveform control pattern memory 10B and the logical comparison pattern memory 10C in the logic test pattern generator 10 are required to store only the pattern generation program for the logic test and a program for generating patterns which are provided to pins for exclusive use of the logic circuit during the memory test -- this affords reduction of the capacities of memories forming the waveform control pattern memory 10B and the logical comparison control pattern memory 10C. Besides, since the present invention employs the construction in which the selection of pins is controlled by the pattern selector 25, a set of test patterns needs only to be stored in the waveform control pattern memory 20B and the logical comparison control pattern memory 20C of the memory test pattern generator 20 independently of the pin arrangement of the IC under test. Hence, the waveform control pattern memory 20B and the logical comparison control pattern memory 20C can be formed by small-capacity memories.

Claims: An IC tester for testing an IC (36) having a logical circuit part, a memory part, and n pins (T 1 - T n ) to which a logic test pattern data (PLA) is applied, where n is an integer greater than or equal to 2, said IC tester comprising: logic test pattern generating means (10) for generating said logic test pattern data (PLA) of n channels for performing a test on said logical part of said IC (36), said logic test pattern generating means (10) further including a waveform control pattern memory (10B) which stores waveform control pattern data (PB) for use in testing the logical circuit part of said IC (36) and which outputs said waveform control pattern data (PB) of n channels, and a logical comparison control pattern memory (10C) which stores logic test logical comparison control pattern data (PC) for use in testing said logical circuit part of said IC and which outputs said logic test logical comparison control pattern data (PC) of n channels; memory test pattern generating means (20) having a plurality of output terminals (Q 0 -Q i ) and for generating a memory test pattern data (PMA) for performing a test on said memory part of said IC (36); pattern selector means (25) of n channels connected to said output terminals (Q 0 - Q i ) of said memory test pattern generating means (20); and pattern selection setting means (26) of n channels for setting the selection of said memory test pattern data, said IC tester being characterized in that: said memory test pattern generating means (20) includes a memory test pattern generator (20A) having a plurality of output terminals (Q 0 - Q i ) and for generating on said output terminals said memory test pattern data for performing said test on said memory part of said IC, and further includes a logical comparison control pattern memory (20C) for storing logical comparison control pattern data (PC) for use in testing said memory part of said IC, said stored logical comparison control pattern data (PC) being read out on output terminals (Q j+1 - Q k ) of said logical comparison control pattern memory (20C), and a waveform control pattern memory (20B) for storing waveform control pattern data (PB) for use in testing said memory part of said IC, said stored waveform control pattern data (PB) being read out on output terminals (Q i + 1 - Q j ) of said waveform control pattern memory (20B); said pattern selector means (25) of n channels, connected to said output terminals (Q 0 - Q i ) of said memory test pattern generator (20A), to at least one output terminal (Q j + 1 - Q k ) of said logical comparison control pattern memory (20C), and to said output terminals (Q i + 1 -Q j ) of said waveform control pattern memory (20B) of said memory test pattern generating means (20), respectively, for selectively outputting said memory test pattern data supplied thereto to corresponding channels connected to said pattern selector means as memory test pattern data (PMA), said logical comparison control pattern data supplied thereto to corresponding channels connected to said pattern selector means as logical comparison control pattern data (PC), and said waveform control pattern data supplied thereto to corresponding channels connected to said pattern selector means as waveform control pattern data (PB), respectively, in accordance with a pin arrangement of said IC; pattern selection setting means (26) of n channels for setting the selection of said memory test pattern data, the selection of said logical comparison control pattern data, and the selection of said waveform control pattern data with respect to n channels by said pattern selector means (25); waveform formatter means (31) of n channels for generating logical waveforms at a predetermined time period and phase or timing, based on one of said logic test pattern data (PLA) and said memory test pattern data (PMA) supplied thereto, and correspondingly outputting said logical waveforms to n channels connected to said waveform formatter means (31) as a test waveform signal; driver means (35) of n channels for controlling said test waveform signal supplied thereto whether or not said test waveform signal is outputted therefrom for each channel, based on said waveform control pattern data supplied thereto from a corresponding one of said logic test pattern generating means (10) and said memory test pattern generating means (20), said driver means (35) applying said test waveform signal controlled thereby to corresponding pins of said IC; and logical comparison means (33) of n channels for logically comparing a response signal outputted from said IC in response to said applied test waveform signal with said test pattern data supplied from said corresponding one of said logic test pattern generating means and said memory test pattern generating means for respective channels specified by said logic comparison control pattern data (PC) supplied thereto from said corresponding one of said logic test pattern generating means and said memory test pattern generating means. The IC tester according to claim 1 wherein said logic test pattern generating means (10) further includes a logic test pattern memory (10A) for storing said logic test pattern data (PLA) and outputting said logic test pattern data of n channels therefrom, and said IC tester further comprises: first gate means (61) for selectively outputting one of said memory test pattern data (PMA) and said logic test pattern data (PLA) supplied thereto from said memory test pattern generator (20A) and said logic test pattern memory (10A), respectively, to said waveform formatter means (31) and said logical comparison means (33) through a first set of n channels; second gate means (62) for selectively outputting one of said memory test waveform control pattern data (PB) and said logic test waveform control pattern data (PB) supplied thereto from said memory test waveform control pattern memory (20B) and said logic test waveform control pattern memory (10B), respectively, to control said driver means (35) through a second set of n channels; and third gate means (63) for selectively outputting one of said memory test logical comparison control pattern data (PC) and said logic test logical comparison control pattern data (PC) supplied thereto from said memory test logical comparison control pattern memory (20C) and said logic test logical comparison control pattern memory (10C), respectively, to control the logical comparison operation of said logical comparison means (33) through a third set of n channels. The IC tester according to claim 2, wherein said pattern selector means (25) includes: a first multiplexer group (MA 1 - MA n ) consisting of multiplexers each having all of its input terminals correspondingly supplied with outputs of said memory test pattern generator (20A) and selectively outputting a desired one of these outputs to its output terminal, a second multiplexer group (MB 1 - MB n ) consisting of multiplexers each having all of its input terminals correspondingly supplied with outputs of said memory test waveform control pattern memory (20B) and selectively outputting a desired one of these outputs to its output terminal, and a third multiplexer group (MC 1 - MC n ) consisting of multiplexers each having all of its input terminals correspondingly supplied with outputs of said memory test logical comparison control pattern memory (20C) and selectively outputting a desired one of these outputs to its output terminal; and wherein said pattern selection setting means (26) includes pattern select memory means (261) having prestored three selective connection address data for each channel, said three selective connection address data of each channel specifying which one of the outputs supplied to the input terminals of each of the multiplexers of the same corresponding channels of said first, second and third multiplexer groups is to be selected in accordance with the pin arrangement of said IC. The IC tester according to claim 3, wherein said pattern select memory means (261) includes memory planes (MP 1 - MP n ) which have said selective connection address data corresponding to IC's of the same type stored at at least one common address thereof, and have said selective connection address data corresponding to IC's of another type stored at at least another common address thereof. The IC tester according to claim 4 further comprising sequence control means (50) for controlling the sequence of generating said logic test pattern data (PLA) in said logic test pattern generating means (10) and the sequence of generating said memory test pattern data (PMA) in said memory test pattern generating means (20), and for providing a common read address to said memory planes during the memory test. The IC tester according to any one of claims 2 to 5, wherein said first, second and third gate means (61, 62, 63) are each formed by a group of OR circuits of n channels. The IC tester according to any one of claims 2 to 5 wherein said first, second and third gate means (61, 62, 63) are each formed by a group of switching circuits (601, 602, 603) of n channels, said switching circuits of each group selectively outputting data inputted thereto for each channel in accordance with control signals (SC) of n channels. The IC tester according to claim 7 as dependent on claim 5 further comprising a control signal gate group including gates (G 1 - G n ) each enabled and disabled by a control signal (GS) representing whether the memory test or logic test is being performed, said control signal being provided from said sequence control means (50), and wherein said memory planes have switching control data for said switching circuits of corresponding channels prestored at said common addresses in accordance with the type of said IC, and said switching control data being provided to said switching circuits of the corresponding channels of each of said first, second and third gate means (61, 62, 63) through the gates of the corresponding channels of said control signal gate group. The IC tester according to claim 1 further comprising sequence control means (50) for controlling the sequence of generating the logic test pattern data (PLA) in said logic test pattern generating means (10) and the sequence of generating the memory test pattern data (PMA) in said memory test pattern generating means (20), said sequence control means including a main sequence controller (50A) and a memory test pattern sequence controller (50B), and wherein said main sequence controller controls the logic test pattern generating sequence of said logic test pattern generating means in accordance with a program and applies a start signal (SS) to said memory test pattern sequence controller, and said memory test pattern sequence controller responds to said start signal to control the memory test pattern generating sequence of said memory test pattern generating means in accordance with another program and, upon completion of said pattern generating sequence, applies an end signal (ES) to said main sequence controller. The IC tester according to claim 9 wherein said main sequence controller (50A) includes a link controller (50C) and a logic test pattern sequence controller (50AA), said link controller applying a start signal (SS) to each of said memory test pattern sequence controller (50B) and said logic test pattern sequence controller, said memory test pattern sequence controller and said logic test pattern sequence controller responding to said start signals to start said memory test pattern generating sequence and said logic test pattern generating sequence in accordance with respective programs, and upon completion of said pattern generating sequences, applying end signals (ES) to said link controller. The IC tester according to claim 9 or 10 wherein said pattern selection setting means (26) is a pattern select memory which stores at different addresses a plurality of different selective connection address data each specifying the setting of selection of said memory test pattern data (PMA) and said logical comparison control pattern data (PC), and said sequence control means (50) generates an address (AD) for accessing said pattern select memory.

Inventors: TAKANO KAZUO, TAKANO, KAZUO
Applicants: ADVANTEST CORP, ADVANTEST CORPORATION
Application year: 1991
Main classification: G06F11
IPC codes: G11C29, G01R31