Electrical circuit for generating pulse strings

Abstract: An electrical circuit is described for generating clock pulses for a multi-chip computersystem which contains a clock generation chip and various logic circuit chips. The clock pulses used on the logic circuit chips are generated on the clock generation chip and are transferred to the logic circuit chips. For the generation of the clock pulses a so-called clocksplitter circuit is provided on the clock generation circuit. This clocksplitter generates two pulse strings out of a third pulse string which is derived from an oscillator. The clocksplitter contains a number of gates and latches which have an impact on the throughput time of a pulse to run through the clocksplitter, as well as on the skew of the two generated pulse strings. The invention provides an electrical circuit which has an improved throughput time and skew of the generated pulse strings.

Description: The invention relates to an electrical circuit for generating a first and a second pulse string with a first pulse duration out of a third pulse string with a second pulse duration, the second pulse duration being half of the first pulse duration and the second pulse string being shifted by the value of the second pulse duration with regard to the first pulse string. Especially, the invention relates to an electrical circuit for generating clock pulses for use in a computersystem. Such an electrical circuit is known for example from multichip computersystems which contain a clock generation chip and various logic circuit chips. The clock pulses used on the logic circuit chips are generated on the clock generation chip and are transferred to the logic circuit chips. For the generation of the clock pulses a so-called clocksplitter circuit is provided on the clock generation circuit. This clocksplitter generates two pulse strings out of a third pulse string which is derived from an oscillator. The clocksplitter contains a number of gates and latches which have an impact on the throughput time of a pulse to run through the clocksplitter, as well as on the skew of the two generated pulse strings. An electronic circuit for providing two alternating pulse strings is disclosed in DE 36 05 722 A1. Shift register latches are known in general from P.H. Bardell et al, Built-In Test for VLSI: Pseudorandom Techniques, John Wiley & Sons, 1987, pp. 26 to 33. It is an object of the invention to provide an electrical circuit which has an improved throughput time and skew of the generated pulse strings. According to the invention this object is solved by an electrical circuit as claimed in claim 1. As latching is avoided in the two shift register latches and due to the respective feedback paths between the two shift register latches, the first and the second pulse string mainly depend on the third pulse string. As the third pulse string only has to run through a minor number of gates, the throughput time and especially the skew of the two generated pulse strings is improved. The delaying means provided in the respective feedback paths of the two shift register latches improve the proper function of the circuit. In an embodiment of the invention inverting means are provided for generating the inversion of the third pulse string. This is the only gate which the third pulse string has to run through in one of two paths to the two shift register latches. Further advantages of the invention will be apparent from the following description of an embodiment of the invention in connection with the accompanying drawings. Fig. 1 shows a block diagram of an electrical circuit for generating pulse strings according to the invention. Fig. 2 shows a timing diagram of three electrical signals of the circuit of Fig. 1. The electrical circuit shown in Fig. 1 provides two shift register latches (10, 11) with two pulse inputs (101, 102; 111, 112), one data input (104, 114) and two data outputs (106, 107; 116, 117), respectively. The first pulse input (101, 111) of each shift register latch (10, 11) is connected with the output of an AND gate (13, 16). One of the two inputs of the AND gates (13, 16) are supplied with a first test signal (TS1). The other input of the AND gate (16) is supplied with a third pulse string (OSC) whereas the other input of the AND gate (13) is supplied via an INVERT gate (19) with the inversion of the third pulse string (OSC). The second pulse input (102, 112) of each shift register latch is supplied with a second signal (TS2). The data input (104) of the first shift register latch (10) is connected via an INVERT gate (24) and a DELAY gate (23) with the data output (116) of the second shift register latch (11). The data input (114) of the second shift register latch (11) is connected via a DELAY gate (21) with the data output (106) of the first shift register latch (10). The delay time of the DELAY gates (21, 23) is less than half of the second pulse duration (T2). At the data outputs (106, 107) of the first shift register latch (10) a first pulse string (PH1) is available whereas at the data outputs (116, 117) of the second shift register latch (11) a second pulse string (PH2) is available. The first, second and third pulse string (PH1, PH2, OSC) are shown in Fig. 2. The first and the second pulse string (PH1, PH2) have a first pulse duration (T1) and the third pulse string (OSC) has a second pulse duration (T2). As can be seen from Fig. 2, the second pulse duration (T2) is half of the first pulse duration (T1) and the second pulse string (PH2) is shifted by the value of the second pulse duration (T2) with regard to the first pulse string (PH1). The first test signal (TS1) can be used for test purposes, e.g. for testing the function of the circuit by supplying only one pulse of the third pulse string (OSC). This can be achieved by ANDing an appropriate test signal (TS1) with the third pulse string (OSC). In operation, the first test signal (TS1) has the binary value "1". With the first test signal (TS1) having the binary value "1" the inversion of the third pulse string (OSC) is supplied to the pulse input (101) of the first shift register latch (10) and therefore determines the moment of the taking over of data into the data input (104) of the first shift register latch (10). Under the same condition, the third pulse string (OSC) is supplied to the pulse input (111) of the second shift register latch (11) and therefore determines the moment of the taking over of data into the data input (114) of the second shift register latch (11). For both shift register latches (10, 11) the moment of the taking over of data into their data input (104, 114) is determined by the transition of the respective signal at the pulse input (101, 111) from the binary value "0" to the binary value "1". As the first shift register latch (10) is supplied with the inversion of the third pulse string (OSC) the moment of the taking over of data into the data input (104) of the first shift register latch (10) is shifted by the value of half of the second pulse duration (T2) with regard to the moment of the taking over of data into the data input (114) of the second shift register latch (11). The second signal (TS2) could be used for taking over the data from the first data output (107, 117) to the second data output (106, 116) of the shift register latches (10, 11). However, in the current electrical circuit shown in Fig. 2, the second signal (TS2) is not used in that manner but it has a binary value such that the first data output (107, 117) and the second data output (106, 116) of the shift register latches (10, 11) are internally connected all the time. In other words, the second signal (TS2) has a binary value such that the first data output (107, 117) and the second data output (106, 116) of the shift register latches (10, 11) always carry the same binary value. In operation, the second signal (TS2) has the binary value "1". If, for example, the second pulse string (PH2) has just become the binary value "1", the first pulse string (PH1) has also the binary value "1". The binary value "1" of the second pulse string (PH2) is delayed by the DELAY gate (23). This situation is depicted with reference number 30 in Fig. 2. Prior to the next 1-0 transition of the third pulse string (OSC) the binary value "1" of the second pulse string (PH2) is inverted into the binary value "0" by the INVERT gate (24) and reaches the data input (104) of the first shift register latch (10). With this next 0-1 transition of the third pulse string (OSC) the binary value "0" is taken over to the data output (106) of the first shift register latch (10) and therefore the first pulse string (PH1) has now the binary value "0". The binary value "0" of the first pulse string (PH1) is delayed by the DELAY gate (21). This situation is depicted with reference number 31 in Fig. 2. Prior to the next 0-1 transition of the third pulse string (OSC) the binary value "0" of the first pulse string (PH1) reaches the data input (114) of the second shift register latch (11). With this next 0-1 transition of the third pulse string (OSC) the binary value "0" is taken over to the data output (116) of the second shift register latch (11) and therefore the second pulse string (PH2) has now the binary value "0". This situation is depicted with reference number 32 in Fig. 2. The binary value "0" of the second pulse string (PH2) is delayed and inverted again and with the next 1-0 transition of the third pulse string (OSC) the first pulse string (PH1) becomes the binary value "1" again; etc. The transitions of the first and the second pulse strings (PH1, PH2) only depend on the transitions of the third pulse string (OSC). The number of gates which the third pulse string (OSC) has to run through is is very low. Without the first test signal (TS1) and therefore without the AND gates (13, 16) there would remain only the INVERT gate (19) in the path of the third pulse string (OSC). As a consequence, the throughput time as well as the skew of the electrical circuit shown in Fig. 2 is very good.

Claims: Electrical circuit for generating a first and a second pulse string (PH1, PH2) with a first pulse duration (T1) out of a third pulse string (OSC) with a second pulse duration (T2), the second pulse duration (T2) being half of the first pulse duration (T1) and the second pulse string (PH2) being shifted by the value of the second pulse duration (T2) with regard to the first pulse string (PH1), comprising: first and second shift register latches (10, 11), each of the first and second shift register latches (10, 11) having two pulse inputs (101, 102, 111, 112), one data input (104, 114) and one data output (106), whereby one of the two pulse inputs (101, 111) of each of the first and second shift register latches (10, 11) is provided for determining the moment of the taking over of data into the data input (104, 114) and the other one of the two pulse inputs (102, 112) of each of the first and second shift register latches (10, 11) is provided for determining the moment of the taking over of data from the data input (104, 114) to the data output (106, 116), the third pulse string (OSC) and the inversion of the third pulse string (OSC) being applied to the one of the two pulse inputs (101, 111) of the first and the second shift register latches (10, 11), respectively, and the other one of the two pulse inputs (102, 112) of each of the first and second shift register latches (10, 11) being supplied with a signal (TS2) such that the data is taken over to the data output (106, 116) at once without latching, and the data output (106, 116) of each one of the first and second shift register latches (10, 11) being coupled to the data input (114, 104) of the other one of the first and second shift register latches (11, 10), and further comprising: inverting means (24) being provided within the feedback path from the data output (116) of one of the first and second shift register latches (11) to the data input (104) of the other one of the first and second shift register latches (10), the two data outputs (106, 116) of the two shift register latches (10, 11) carrying the first and the second pulse string (PH1, PH2), delaying means (21, 23) being provided within each of the two feedback paths from the data outputs (106, 116) to the data inputs (114, 104) of the first and second shift register latches (10, 11). Electrical circuit according to claim 1 further comprising: inverting means (19) for generating the inversion of the third pulse string (OSC). Electrical circuit according to claim 1 or 2 further comprising: AND gates (13, 16) for supplying a signal (TS1) for test purposes. Electrical circuit according to one of claims 1 to 3 for use in a computer system.

Inventors: KNAUFT GUENTER, LEPPLA BERND DIPL-ING, SCHMUNKAMP DIETMAR DIPL-ING, WEISS ULRICH, KNAUFT, GUENTER,, LEPPLA, BERND, DIPL.-ING., SCHMUNKAMP, DIETMAR, DIPL.-ING., WEISS, ULRICH, Knauft, Günter,
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1991
Main classification: H03K5
IPC codes: H03K5