Method of forming a microelectronic device with a first and a second element

Abstract: The present invention is directed to a method for forming planar microelectronic devices, with the devices including elements made from the same or from different materials, and with the devices capable of being fabricated with gaps between elements of sub-submicron dimensions with an exceptional control. On a substrate (10) there is a deposited conductive layer (14) and a second material (16). The second material is patterned, and it and the conductive material are etched to form the first element and the first element cap, respectively. Next, a layer of sacrificial material of predetermined thickness is deposited on top of the structure. It is the thickness of this sacrificial layer, rather than any patterning or etching, that determines how big the gap will be between elements. More particularly, the sacrificial material is deposited using a conformal deposition. In this manner, there are formed vertical walls of sacrificial material alongside the vertical walls of the first element and its cap, with the sacrificial material walls having a lateral thickness equal to the thickness of the deposited sacrificial material. Next, a second conductive layer is deposited using a conformal deposition. In this manner, there are formed vertical walls of second conductive material alongside the vertical walls of the sacrificial material, on the opposite side of these walls from the vertical walls of the first element and its cap. Similar to the sacrificial material walls, the second conductive material walls have a vertical thickness that depends on the height of the first element an its cap. The cap thickness is chosen such that the second conductive material walls have a height greater than the deposition thickness of the second conductive material. In this manner, when next the second element material is anisotropically etched to an extent sufficient to remove the second conductive material from most of the structure, some portion of the second conductive material walls will remain to form the second element. Finally, the sacrificial material is anisotropically etched, thereby removing the sacrificial material walls between the first element and the second element.

Description: This invention relates to microelectronic devices, and more particularly to a method of forming a vacuum microelectronic device with a first and a second element, in particular self aligned, closely spaced elements. A promising technology for use in high speed electronic systems is the vacuum microelectronic device, which in essence is a miniature vacuum tube that uses a cold emitter. One type of vacuum microelectronic device uses a field effect emitter in which electrons tunnel through the vacuum energy barrier whose width is determined by the electric field. For significant electron tunneling to take place at the tip of the emitter, the electric field at the tip much reach a relatively high strength (e.g., 1x10 7 V/cm). To achieve such a high electric field, the emitters are provided with a relatively sharp tip (e.g., the point of a wedge, cone or pyramid shape). Moreover, the emitter is placed relatively close to the extraction electrode. The closer the gap between emitter and extraction electrode, the lower the voltage needed to produce the requisite electric field strength. Moreover, the closer the spacing, the less stringent the requirement for a vacuum. These considerations are discussed in detail in a journal article entitled, "Physical Considerations in Vacuum Microelectronics Devices," Electron Devices, IEEE, Nov. 1989, Vol. 36, No. 11, p. 2641. One practical method of fabricating vacuum microelectronic devices is micromachining a substrate (e.g., silicon or ceramic). For example, a journal article, "Lateral Miniaturized Vacuum Devices," IEDM 89-533, describes a process for fabricating a vacuum triode on a silicon substrate. In particular, the emitter is placed relatively close to the extraction electrode by fabricating the electrode above a portion of the emitter, separated from the emitter by a sacrificial layer that is later removed. The collector and emitter are positioned by patterning (e.g., photolithography) and etching techniques. At present, very advanced patterning and etching techniques, such as those used in VLSI fabrication, have a resolution no lower than about 0.5 micron, with patterning and alignment tolerances of about 0.2 micron. However, practical vacuum microelectronic devices require a closer spacing and better control of it. Thus, it is the object of the present invention to provide a method for forming on a substrate a microelectronic device having a first and a second element enabling closer spacing of these elements while keeping a better control. According to the invention, this object is solved with a method according to claim 1. The present invention is directed to a method for forming planar microelectronic devices, with the devices including elements made from the same or from different materials, and with the devices capable of being fabricated with gaps between elements of extremely small dimensions, down to tens of nm (hundreds of angstroms). In a preferred embodiment, a layer of the first sacrificial material is deposited and patterned (to suspend the tip of the cathode). A thin conductive layer (cathode) is deposited and capped by another sacrificial layer of the same material as the first sacrificial layer. These two sandwiched layers are now patterned with two sequencial masks to form the cathode and its tip. A layer of another sacrificial materialof predetermined thickness is deposited on the top of the structure using a method of conformal deposition. The thickness of this material defines the gap between the cathode's tip and the self aligned anode. In this manner, there are formed vertical walls of sacrificial material alongside the vertical walls of the first element and its cap, with the sacrificial material walls having a lateral thickness equal to the thickness of the deposited sacrificial material. Next, a second conductive layer is deposited using a conformal deposition. In this manner, there are formed vertical walls of second conductive material alongside the vertical walls of the sacrificial material, on the opposite side of these walls from the vertical walls of the first element and its cap. The second conductive layer is then etched anisotropically to form a so called spacer or stinger along the second sacrificial layer across the cathode's tip. The second sacrificial material is anisotropically etched, thereby removing the sacrificial material walls between the first element and the second element. An oxide layer is deposited and patterned to anchor interconnect metal to the substrate. The interconnect metal is deposited and patterned. Finally the first sacrificial layer (oxide) is removed (e.g., etched or washed out). Other aspects of the invention will become apparent from the following description with reference to the drawings, wherein: Figures 1A-4A are cross-sectional views of various stages in forming a vacuum diode according to the method of the present invention; and Figures 1B-4B are top views of various stages in forming a vacuum diode according to the method of the current invention. Referring now to Figures 1A and 1B, there are shown cross-sectional and top views, respectively, of a substrate 10 on which a ramp 12 has been formed by depositing about 200 nm (2000 angstroms) of silicon dioxide, then patterning and etching the oxide. Substrate 10 can be made of ceramic, or be a silicon substrate preferably covered by an insulating layer, such as silicon nitride. Next, a conductive layer (e.g., a layer of about 50 nm (500 angstrom) thick tungsten) that will form cathode 14 is deposited, followed by deposition of a layer of material (e.g., a layer of about 200 nm (2000 angstrom) thick silicon dioxide) that will form cathode cap 16. The cathode cap 16 material is patterned and then etched together with underlying portions of the cathode 14 material and the ramp 12 material to form cathode cap 16, cathode 14, and ramp 12, respectively. Ramp 12 elevates the portion 18 of cathode 14 which overlies ramp 12. Elevating cathode portion 18 aids in the ballistic transport of electrons. It is important that one corner 20 of cathode portion 18 be relatively sharp in order to concentrate the electric field lines. To obtain a sharp corner 20, it is well known to one skilled in the art to perform the above step of patterning the cathode cap 16 material using a two masking process. Referring now to Figures 2A and 2B, a sacrificial layer 22 of silicon nitride, 200 nm (2000 angstroms) thick, is next deposited using a conformal deposition technique, such as CVD (Chemical Vapour Deposition). In this manner, in effect a vertical wall 24 of silicon nitride is formed along the sides of the raised structures on substrate 10, with the portion 26 of the nitride wall 24 having greatest height being found alongside cathode portion 18. Moreover, since the deposition was conformal, the nitride wall 24 will have a thickness substantially equal to the thickness of the nitride deposition. Note that the height of nitride wall portion 26 is a function of not only the nitride thickness but of the thicknesses of the ramp 12, cathode 14, and cathode cap 16, with the thickness of cathode cap 16 being the likely candidate for adjusting the height of nitride wall portion 26. Referring now to Figures 3A and 3B, anode 28 is formed by a technique similar to the side wall spacer technique employed in the fabrication of certain MOS transistors. A conductive layer, such as 500 nm (5000 angstroms) thick layer of polycide, that will form anode 28 is deposited using a conformal deposition technique (e.g., CVD , chemical vapor deposition). Here, as with the conformal deposition of the sacrificial material, in effect there is formed a vertical wall of the anode 28 material along the sides of the raised structures on substrate 10. The polycide is then anisotropically etched to an extent sufficient to remove the polycide from all areas except near the highest portion 26 of the nitride wall 24. In this manner, node 28 is formed. In the course of the anisotropic etch, the side 30 of anode 28 exterior to nitride wall portion 26 will become rounded since it is not shielded by nitride wall portion 26. Referring now to figures 4A and 48, sacrificial layer 22 is etched using a technique that only removes the portion of the layer that is not covered by anode 28. For example, the silicon nitride sacrificial layer 22 is removed using a plasma etch. In this manner, the nitride wall portion 26 between the anode 28 and the cathode portion 16 is removed, while a portion 32 of nitride remains to support and elevate anode 28 to a position substantially level with raised cathode portion 18. Next, a passivation layer of silicon dioxide is deposited, patterned and etched to form contact and anchor widows, and a layer of interconnect metal (e.g., aluminum) is deposited, patterned and etched to form interconnects to the anode 28 and to cathode 14, with the interconnects contacting the anode 28 and cathode 14 through the contact windows. Finally, an isotropic etch, such as a wet oxide etch, is used to remove ramp 12 and cathode cap 16. With the above invention, the gap between elements is defined by the thickness of the deposition of a sacrificial material, rather than by patterning and etching. Consequently, the method of the invention allows much smaller gaps between elements. While the invention has been described with reference to the structures disclosed, it is not confined to the specific details set forth, but is defined by the following claims.

Claims: A method for forming on a substrate (10) a microelectronic device having a first and a second element (14,28) comprising the steps of: depositing a first layer (14) of electrically conductive material on said substrate (10); depositing a cap material (16) on said first layer (14); forming said first element and the first element cap from said first layer and said cap material, respectively, such that a vertical step (20) is formed at an edge of said first element (14); conformally depositing a sacrificial material (22) forming vertical wall of sacrificial material at said step (20); conformally depositing a second layer (28) of electrically conductive material forming a second vertical wall opposing said edge of said first element (14); anistropically etching said second layer (28) to form said second element; and anistropically etching said sacrificial material (22) to remove said vertical wall of sacrificial material between said first and second element, to thereby generate the first and second element made of electrically conductive material in self aligned relation. A method as claimed in claim 1, comprising the additional steps of: before said first conductive layer (14) is deposited on said substrate (10), depositing a primary layer (12) of sacrificial material on said substrate (10); and forming a ramp structure from said primary layer (12). The method according to claim 2, including the step of removing said primary layer (12) of sacrificial material.

Inventors: BOL IGOR I, BOL, IGOR I.
Applicants: XEROX CORP, XEROX CORPORATION
Application year: 1991
Main classification: H01J9
IPC codes: H01J9, H01J21, H01L49