Bi-CMOS low-noise output buffer circuit

Abstract: A low-noise output buffer circuit of this invention comprises a P-channel MOSFET (102) having a source connected to a power source potential, for outputting the power source potential according to a first input signal, an N-channel MOSFET (103) having a source connected to a ground potential, for outputting the ground potential according to a second input signal, a bipolar transistor (105) having a collector connected to the power source potential, an emitter connected to an output terminal (106) and a base connected to the drain of the P-channel MOSFET, and a diode (107) having a cathode connected to the drain of the N-channel MOSFET and an anode connected to the base of the NPN bipolar transistor.

Description: This invention relates to the improvement of a Bi-CMOS output buffer circuit which is particularly required to have a large current driving ability and high operation speed. Conventionally, a circuit shown in Fig. 1, for example, is known as a Bi-CMOS output buffer circuit which is required to have a large current driving ability and high operation speed. The operation of the above circuit is described below. First, assume that an input signal is applied to an input terminal 901. In this case, a P-channel MOSFET 902 is set in the OFF state and an N-channel MOSFET 903 is set in the ON state. Therefore, the base potential of an NPN bipolar transistor 904 is substantially set to an "L (GND)" level, thereby turning off the transistor 904. The voltage V IN of "H" level applied to the input terminal 901 is applied to an inverter 905. That is, a non-inverted signal (in this case, a voltage of "H" level) of the input signal V IN is applied to the base of a transistor 907. As a result, the transistor 907 is turned on, thus causing an output voltage V OUT of "H" level to be output from an output terminal 908. Next, assume that a voltage V IN of "L (low)" level is applied to the input terminal 901. In this case, a voltage of "L" level is applied to the base of the transistor 907 to turn off the transistor 907. At this time, the P-channel MOSFET 902 is set in the ON state and the N-channel MOSFET 903 is set in the OFF state. Therefore, the base potential of the transistor 904 rises to turn on the transistor 904, thereby causing an output potential V OUT of "L" level to be output from the output terminal 908. In the above output buffer circuit, an N-channel MOSFET 909 of the inverter 906 is turned on when the input signal V IN is changed from the "H" level (for example, 5 V) to the "L" level (for example, 0 V). As a result, the base potential of the transistor 907 is set to substantially 0 V and the transistor 907 is turned off. At this time, since the P-channel MOSFET 902 is set into the ON state, the base potential of the transistor 904 rises and a current flows into the base thereof. Therefore, the transistor 904 is turned on so that the output potential V OUT of the output terminal 908 may be changed from the "H" level to the "L" level. However, as shown in Fig. 2, a phenomenon called "undershoot" is caused by the flow of a transition current i and the presence of parasitic inductance Lp of a bonding wire or the like in the above output buffer circuit. The phenomenon is a well-known phenomenon that the output potential V OUT is temporarily set to be negative (below the GND level) and can be expressed by an equation of Lp × di/dt. The undershoot causes the value of the output potential V OUT to be lower than -V F . As a result, the base potential of the transistor 907 is set to a value obtained by adding the peak value (-V USP ) of the undershoot to the threshold voltage V F of the transistor 907, that is, a value equal to or lower than 0 V. Therefore, as shown in Fig. 1, a potential difference occurs between the source and drain of the N-channel MOSFET 909 of the inverter 906 and a current i 1 flows into the base of the transistor 907 from V SS (GND level). As a result, the transistor 907 which must be kept in the OFF state will be set into the ON state, thereby causing a large collector current to flow in the transistor 907. Therefore, as shown in Fig. 3, the power source voltage V DD becomes unstable or fluctuates because of the flow of a collector current and the presence of the inductance (L P ) component of the power source V DD line. In this case, a plurality of logic circuits such as the above output buffer circuit are contained in the LSI, and in general, the logic circuits are commonly connected to the power source V DD . Therefore, the output voltage V' OUT of a logic circuit 911 which is arranged near the above output buffer circuit 910 may fluctuate. The degree of fluctuation in the output voltage V' OUT may exceed the circuit threshold voltage of the next-stage logic circuit connected to the logic circuit 911, and in this case, the next-stage logic circuit may be erroneously operated. The circuit of Figure 1 is reflected in the preamble of claim 1. EP-A-0 344 614 and JP-A-1-57821 show circuits relating to TTL totem pole circuits, arranged so as to avoid simultaneous conduction of the elements. Bipolar transistors are used for controlling the pull-up transistor, and in EP-A-0 344 614 diodes are arranged to block current flow back to the base of the pullup transistor. This invention has been made to solve the above problem, and an object of this invention is to provide an output buffer circuit which can be made highly reliable by preventing a large current (through current) caused by the undershoot from flowing from the power source so as to prevent fluctuation in the power source potential. According to the invention from one aspect, there is provided a circuit as set out in claim 1. According to the invention from another aspect, there is provided a circuit as set out in claim 8. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram showing a conventional output buffer circuit; Fig. 2 is a diagram showing the relation between the power source voltage V DD waveform and output V OUT waveform of a conventional output buffer circuit; Fig. 3 is a circuit diagram showing the relation between variation in a logic output V' OUT waveform and variation in the power source potential caused by the conventional undershoot phenomenon; Fig. 4 is a circuit diagram showing the basic construction of a pull-up section of a Bi-CMOS buffer according to a first embodiment of this invention; Fig. 5 is a circuit diagram showing the output buffer circuit of Fig. 4 more in detail; Fig. 6 is a diagram showing the relation between the power source voltage V DD waveform and output V OUT waveform of an output buffer circuit of this invention; Fig. 7 is a diagram showing the diode characteristic; Figs. 8 to 10 are circuit diagrams showing modifications of the output buffer circuit of Fig. 5; Fig. 11 is a circuit diagram showing the basic construction of a pull-up section of a Bi-CMOS buffer according to a second embodiment of this invention; Fig. 12 is a circuit diagram showing the output buffer circuit of Fig. 11 more in detail; and Fig. 13 is a circuit diagram showing an output buffer circuit according to a third embodiment of this invention. There will now be described an embodiment of this invention with reference to the accompanying drawings. In this description, common portions in all of the drawings are denoted by the same reference numerals so as to omit the redundant explanation thereof. Fig. 4 is a circuit diagram showing the basic construction of a pull-up section of a Bi-CMOS buffer according to a first embodiment of this invention. In this case, 101 denotes an input terminal, 102' an element such as a P-channel MOSFET for outputting an "H" level potential (power source V DD potential), 103' an element such as an N-channel MOSFET for outputting an "L" level potential (ground V SS potential), 104 a logic circuit, for example, an inverter, 105 an NPN bipolar transistor connected to receive an output potential of the logic circuit 104 at the base thereof, 106 an output terminal, and 107 a diode. In the output buffer circuit of this invention, the diode 107 is connected between the bipolar transistor 105 and the element 103 for outputting an "L" level potential (ground V SS potential). The cathode and anode of the diode 107 are respectively connected to the element 103' and the base of the bipolar transistor 105. With this connection, a phenomenon that the bipolar transistor 105 is turned on by the undershoot can be prevented. Fig. 5 is a circuit diagram more concretely showing the above output buffer circuit according to the first embodiment. In this case, 102 and 108 denote P-channel MOSFETs, 103 and 109 denote N-channel MOSFETs, 110 denotes an NPN bipolar transistor, and 111 denotes an inverter. The operation of the above circuit is concretely explained below. First, assume that the potential V OUT of the output terminal 106 is changed from the "H" level to the "L" level. In this case, the undershoot as is shown in Fig. 6 occurs in the output potential V OUT by a transition current flowing in the bipolar transistor 110 and the inductance component (L P ) of the wiring and the like. As a result, if the threshold voltage of the bipolar transistor 105 is set to -V F the output potential V OUT may be sometimes set equal to or less than -V F . When the output potential V OUT becomes equal to or less than -V F , the base potential of the bipolar transistor 105 becomes negative so that a potential difference occurs between the base of the bipolar transistor 105 and the source (ground potential) of the N-channel MOSFET 103. The operation explained so far is the same as that of the conventional case. However, in this invention, the diode 107 is connected between the drain of the N-channel MOSFET 103 and the base of the bipolar transistor 105. In order to utilize the reverse current characteristic shown in Fig. 7, the cathode of the diode 107 is connected to the drain of the N-channel MOSFET 103 and the anode thereof is connected to the base of the bipolar transistor 105. With this connection, a current i 1 caused by the undershoot can be interrupted. With the above construction, the current i 1 caused by the undershoot can be interrupted by the presence of the diode 107. Therefore, a current required for turning on the bipolar transistor 105 will not be supplied to the base of the bipolar transistor 105. That is, the bipolar transistor 105 can be prevented from being unwantedly turned on. As shown in Fig. 6, since fluctuation in the power source voltage V DD can be suppressed and fluctuation in the logic output potential at a portion near the output buffer circuit can be suppressed, a highly reliable logic operation can be attained. In this case, a potential difference occurring between the ground potential V SS and the base of the bipolar transistor 105 is as small as negligible when compared with the breakdown voltage in the reverse direction of the diode 107. Figs. 8 to 10 respectively show the modifications of the first embodiment. In the modification shown in Fig. 8, a resistor is used instead of the P-channel MOSFET of the inverter 105 of Fig. 5. Further, in the modification shown in Fig. 9, a resistor is used instead of the N-channel MOSFET of the inverter 105 of Fig. 5. Further, in the modification shown in Fig. 10, an NPN bipolar transistor is used instead of the N-channel MOSFET of the inverter 105 of Fig. 5. Also, in the above modifications, the same effect as that of the first embodiment can be obtained. Fig. 11 is a circuit diagram showing the basic construction of a pull-up section of a Bi-CMOS buffer according to a second embodiment of this invention. In the output buffer circuit of this embodiment, a diode 107 is connected between a logic circuit 104 and a ground V SS potential. The cathode of the diode 107 is connected to the ground V SS potential and the anode thereof is connected to the logic circuit 104. With the above construction, a current caused by the undershoot can be interrupted and the bipolar transistor 105 can be prevented from being turned on. The logic circuit 104 outputs an output signal (power source V DD potential) of "H" level or an output signal (ground V SS potential) of "L" level according to an input signal. Fig. 12 is a circuit diagram concretely showing the output buffer circuit of Fig. 11. The operation of the above circuit is the same as that of the output buffer circuit of Fig. 5. Thus, even when a diode is provided outside the logic circuit, the same effect as that obtained in the first embodiment can be attained. Further, the logic circuit 104 may be formed of the inverter with the construction shown in Figs. 8 to 10 as well as the inverter with the construction shown in Fig. 5. Fig. 13 shows an output buffer circuit according to a third embodiment of this invention. In this embodiment, an N-channel MOSFET 112 is used as an element for outputting an "L" level voltage. In this case, the base of the N-channel MOSFET 112 is connected to the output terminal of an inverter 111 and therefore the circuit construction can be made extremely simple. In the above first to third embodiments, the diode 107 having a PN junction is used as an element for interrupting a current path i 1 caused by the undershoot phenomenon, but a Schottky diode may be used instead of the above diode, for example. Further, the source of the N-channel MOSFET 103 in the logic circuit 104 is preferably set at the ground potential, and it is not preferable to set the source of the N-channel MOSFET higher than the ground potential. The logic circuit 104 is not limited to an inverter; it can be a NAND gate or a NOR gate.

Claims: A Bi-CMOS output buffer circuit comprising: a switch element (110, 112) connected between a first reference ground potential (VSS) and an output terminal (106); a first bipolar transistor (105), an emitter of which is connected to said output terminal (106) and a collector of which is connected to a power source (VDD) ; a first logic circuit (108, 109) having at least one MOS transistor, said circuit being arranged to turn on said switch element (110, 112) when an input signal is at a first level, and to turn off said switch element (110, 112) when said input signal is at a second level; and a second logic circuit (104, 111) having at least one transistor (103), said circuit being arranged to turn on said first bipolar transistor (105) by supplying a current to a base of said first bipolar transistor (105) when said input signal is at the second level, and to turn off said first bipolar transistor (105) when said input signal is at the first level; said buffer circuit being characterised in that said second logic circuit has a diode (107) connected in series with said at least one transistor (103) of the second logic circuit, said diode (107) and said at least one transistor (103) being coupled in series with and between said reference ground potential (VSS) and a base of said first bipolar transistor (105) in such a manner that the cathode of the diode is connected to the reference potential side and the anode is connected to the first bipolar transistor side, said at least one transistor (103) of the second logic circuit being arranged to be controlled by said input signal, said diode (107) being so arranged that when an output potential (VOUT) of said buffer circuit lowers to or below -VF due to an undershoot of the output potential (VOUT), where VF is a threshold voltage of said first bipolar transistor (105), said diode prevents a reverse current from flowing into the base of said first bipolar transistor (105) from said at least one transistor (103). A Bi-CMOS output buffer circuit according to claim 1, characterized in that: said second logic circuit includes a first inverter (111) arranged to receive said input signal, and a second inverter (104) arranged to receive an output signal of said first inverter (111); said at least one transistor of the second logic circuit is an N-channel MOS transistor (103), said second inverter circuit including said N-channel MOS transistor (103) having a source connected to said first reference ground potential (VSS) and a gate to which the output signal of said first inverter (111) is input, and a P-channel MOS transistor (102) having a source connected to said power source (VDD), a gate arranged to receive the output signal of said first inverter (111), and a drain connected to the base of said first bipolar transistor (105); and said diode (107) having an anode connected to the base of said bipolar transistor (105) and a cathode connected to a drain of said N-channel MOS transistor (103). A Bi-CMOS output buffer circuit according to claim 1, characterized in that: said second logic circuit includes a first inverter (111) arranged to receive said input signal, and a second inverter (104) arranged to receive an output signal of said first inverter (111); said at least one transistor of the second logic circuit is an N-channel MOS transistor (103), said second inverter circuit including said N-channel MOS transistor (103) having a source connected to said first reference ground potential (VSS) and a gate arranged to receive the output signal of said first inverter (111), and a resistance connected between said power source (VDD) and the base of said first bipolar transistor; and said diode (107) having an anode connected to the base of said bipolar transistor (105) and a cathode connected to a drain of said N-channel MOS transistor (103). A Bi-CMOS output buffer circuit according to claim 1, characterized in that: said second logic circuit includes a first inverter (111) arranged to receive said input signal and to output an output signal for controlling said at least one transistor (103) of the second logic circuit (104, 111); said at least one transistor (103) of the second logic circuit (104, 111) is a bipolar transistor having an emitter connected to said first reference ground potential (VSS) and a base connected to receive the output signal of said first inverter (111); and a resistance is connected between said power source (VDD) and said base of said first bipolar transistor (105); said diode (107) having its anode connected to the base of said first bipolar transistor (105) and its cathode connected to a collector of said bipolar transistor. A Bi-CMOS output buffer circuit according to claim 1, characterized in that: said second logic circuit includes a first inverter (111) arranged to receive said input signal, and a second inverter (104) arranged to receive an output signal of said first inverter (111); and said diode (107) having an anode connected to said second inverter (104) and a cathode connected to said first reference ground potential (VSS). A Bi-CMOS output buffer circuit according to claim 1, characterized in that: said switch element includes a third bipolar transistor (110) having an emitter connected to said first reference ground potential (VSS), a collector connected to said output terminal (106) and a base connected to said first logic circuit (108, 109). A Bi-CMOS output buffer circuit according to claim 1, characterized in that: said switch element includes a MOS transistor (112) having a source connected to said first reference ground potential (VSS), a drain connected to said output terminal (106) and a gate connected to said first logic circuit (111). A Bi-CMOS output buffer circuit comprising: a switch element (110, 112) connected between a first reference ground potential (VSS) and an output terminal (106); a first bipular transistor (105), an emitter of which is connected to said output terminal (106) and a collector of which is connected to a power source (VDD); a first logic circuit (108, 109) having at least one MOS transistor, said circuit being arranged to turn on said switch element (110, 112) when an input signal is at a first level, and to turn off said switch element (110, 112) when said input signal is at a second level; and a second logic circuit (104, 111) having at leas one transistor (102), said circuit being arranged to turn on said first bipolar transistor (105) by supplying a current to a base of said first bipolar transistor (105) when said input signal is at the second level, and to turn off said first bipolar transistor (105) when said input signal is at the first level; said buffer circuit being characterized in that said second logic circuit has a diode (107) connected in series with a resistor of the second logic circuit, and said diode (107) and said resistor being coupled in series with and between said reference ground potential (VSS) and a base of said first bipolar transistor (105) in such a manner that the cathode of the diode is connected to the first reference ground potential side and the anode is connected to the first bipolar transistor side, said diode (107) being so arranged that when an output potential (VOUT) of said buffer circuit lowers to or below -VF due to an undershoot of the output potential (VOUT), where VF is a threshold voltage of said first bipolar transistor (105), said diode prevents a reverse current from flowing into the base of said first bipolar transistor (105) via said resistor. A Bi-CMOS output buffer circuit according to claim 8, characterized in that: said second logic circuit includes a first inverter (111) arranged to receive said input signal, and a second inverter (104) arranged to receive an output signal of said first inverter (111); said at least one transistor of the second logic circuit is a P-channel MOS transistor (102), said second inverter circuit including said resistor having one end connected to said first reference ground potential (VSS) and said P-channel MOS transistor (102) having a source connected to said power source (VDD), a gate arranged to receive the output signal of said first inverter (111), and a drain connected to the base of said first bipolar transistor (102); and said diode (107) having an anode connected to tho base of said bipolar transistor (105) and a cathode connected to another end of said resistor.

Inventors: FUKUDA MASAYO, KIMURA MASAHIRO, MATSUO KENJI, TSUCHIYA IKUO, FUKUDA, MASAYO, KIMURA, MASAHIRO, MATSUO, KENJI, TSUCHIYA, IKUO, FUKUDA, MASAYO, C/O INTELLECTUAL PROPERTY DIV., KIMURA, MASAHIRO, C/O INTELLECTUAL PROPERTY DIV., MATSUO, KENJI, C/O INTELLECTUAL PROPERTY DIV., TSUCHIYA, IKUO, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1991
Main classification: H03K19
IPC codes: H01L27, H01L21, H03K19, H01L29