Method of fabricating a field effect device with polycrystaline silicon channel

Abstract: A CMOS SRAM cell has a polycrystalline silicon signal line between a common node, which is the data storage node, and the power supply. A field effect device is fabricated within this polycrystalline silicon signal line. The channel of the field effect device is separated from an active area in the substrate by a thin gate dielectric, and the active region within the substrate functions as the control gate for the field effect device. Such a device can be used to provide polycrystalline silicon P-channel transistors for use in CMOS SRAM cells.

Description: The present invention relates generally to integrated circuit devices, and more specifically to a field effect device having a polycrystalline silicon channel. CMOS static random access memories (SRAM) are increasingly used in the electronics industry due to their combination of speed, low power, and no requirement for refresh. A CMOS SRAM cell is built around a cross-coupled latch and accessed by, typically, 2 control gates for a standard SRAM cell. Four control gates are used to access the cell for 2-port memory devices. The basic SRAM cell can be formed using cross-coupled CMOS inverters, having 2 each n-channel and p-channel transistors. To conserve physical layout space, the p-channel transistors are often replaced with resistive loads. Typical loads include a polycrystalline silicon resistor, and 2 back-to-back polycrystalline silicon diodes. An example of the latter is described in co-pending US Patent Application Serial Number 298,530, filed January 18, 1989, which issued as US 5,196,233 on March 23, 1993. This patent discloses a method for fabricating a resistive load element for a semiconductor device using standard semiconductor processes. The resistive load element is formed in a layer of second level polysilicon, by creating back-to-back PN diodes therein. Resistive loads of either type are formed to have a very high resistance in order to reduce power comsumption by the cell. Use of a p-channel transistor as the load for the SRAM cell results in a cell having better electrical characteristics. Such cells are faster than those using resistive loads, since the p-channel transistors can provide a higher drive current than high resistance devices. Also, use of p-channel transistors gives higher immunity to soft errors, such as those caused by alpha particle impacts and noise. The primary disadvantage of SRAM cells incorporating p-channel load transistors is that the layout area for each cell is significantly larger than those using resistive loads. This reduces device density and increases chip costs. The use of p-channel transistors in highly integrated circuits is disclosed in DE-A-2,503,864. This document discloses the creation of an "upside-down" p-type field effect device where the source, drain and channel regions are formed in a layer of polysilicon which overlies a layer of gate oxide deposited over an active area in a substrate, where the active area operates as a control gate for the transistor. Another prior art doucment EP-A-0104616 discloses an integrated SRAM cell in which: the source, drain and channel regions of the n-channel selection transistors are formed in the substrate with a first strip of polysilicon forming their control gates; the source, drain and channel regions of the "upside-down" p-channel load transistors are formed in a second strip of polycrystalline silicon, with active regions in the substrate forming their control gates; and the source, drain and channel regions of the n-channel switching transistors are formed in the substrate with the second polycrystalline silicon strip forming their control gates. A reference, qualifying as prior art under EPC Article 54(3), EP-A-0392540, discloses an integrated SRAM cell in which the source, drain and channel regions of the n-channel switching transistors are formed in the substrate with their control gates formed in a first polysilicon layer; the source, drain and channel regions of the "upside-down" p-channel load transistors are formed in a second polysilicon layer with their control gates formed in the substrate; and the source, drain and channel regions of the n-channel selection transistors are formed in the substrate with their control gates formed in a first polycrystalline silicon layer. In the prior art discussed above, the gate oxides of the n and p-channel transistors are formed in a common layer of oxide formed in a single step. Therefore, the characteristics of the transistors are to some extent linked together. It would be desirable to provide an SRAM cell which combined the advances of p-channel loads with the cell layout area requirements of resistive load cells. It would be further desirable to provide a field effect device load, suitable for use with an SRAM cell, which provides increased current drive over resistive loads, and which provides a high OFF resistance. It is therefore an object of the present invention to provide an integrated circuit with a so-called "upside down transistor" which can be individually characterised. According to one aspect of the present invention there is provided a method for fabricating field effect devices in an integrated circuit comprising the steps of: forming an active region in a semiconductor substrate; forming a first field effect device in the semiconductor substrate, said first field effect device having source/drain regions opposite a gate electrode formed from a first layer of polysilicon and a channel under the gate electrode within the substrate said channel being separated from the gate electrode by a first oxide layer; forming a second oxide layer over the substrate; forming an opening through the second oxide layer to expose an underlying conductive region; forming a second layer of polycrystalline silicon over the second oxide layer and the exposed underlying conductive region; forming, for a second field effect device, source/drain regions in the second layer of polycrystalline silicon; forming a region to constitute a channel element in the second layer of polycrystalline silicon between the source/drain regions over the active region; and etching portions of the second layer of polycrystalline silicon to define said channel element as an elongate element connecting the source/drain regions of the second field effect device, wherein the second field effect device has a gate formed by the active region; wherein: the step of forming the first field effect device comprises carrying out a process step to form the first oxide layer over the substrate prior to definition of the gate electrode of the first field effect device, said process step being distinct from the process step used to form the second oxide layer of the second field effect device; and wherein the step of forming the second layer of polycrystalline silicon is carried out in a separate process step to the one in which the first layer of polysilicon is formed. Therefore, according to the present invention, a CMOS SRAM cell has a polycrystalline silicon signal line between a common node, which is the data storage node, and the power supply. A field effect device is fabricated within this polycrystalline silicon signal line. The channel of the field effect device is separated from an active area in the substrate by a thin gate dielectric, and the active region within the substrate functions as the control gate for the field effect device. Such a device can be used to provide polycrystalline silicon p-channel transistors for use in CMOS SRAM cells. The invention, which is defined in the appended claims, as well as a preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: Figures 1-4 illustrate fabrication of a polycrystalline silicon field effect device according to the present invention; Figure 5 is a plan view showing the layout of a CMOS SRAM cell utilizing a polycrystalline silicon field effect device according to the present invention: Figure 6 is a schematic diagram of the SRAM cell of Figure 5 . The process steps and structures described below do not form a complete process flow for manufacturing integrated circuits. The present invention can be practiced in conjunction with integrated circuit fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention. The figures representing cross-sections of portions of an integrated circuit during fabrication are not drawn to scale, but instead are drawn so as to illustrate the important features of the invention. Referring to Figure 1 , a cross-section of a portion of a CMOS SRAM cell is shown as being fabricated in a P-type substrate 10 . Field oxide regions 12, 14 separate active regions of the device. Active region 16 is located between field oxide regions 12, 14 , and forms a common source/drain region for 2 field effect transistors (not shown). Active region 18, although shown as separated into 2 parts, is actually a single active region as will be shown in connection with Figure 5 . Polycrystalline silicon gate line 20 is formed over a thin gate oxide layer 22 as known in the art. Sidewall spacers 24 are formed using an anisotropic etch as known in the art, causing the formation of lightly doped drain (LDD) regions 26 . Although polycrystalline silicon line 20 appears to function as the gate of a field effect device in the cross sectional view of Figure 1 , it will actually become the location of a shared contact region to be described below. The impurity doping profiles in the region of the polycrystalline silicon line 20 are the same as those for an actual transistor, but this is merely an artifact of the fabrication process as known in the art. Active regions 18 are connected other than in the plane of the cross section of Figure 1 , and direct electrical contact will be made between the polycrystalline silicon signal line 20 and the underlying active region 18 as will be further described below. To this point, standard fabrication techniques for a CMOS SRAM are used. Variations from the standard process flows will now be performed in order to fabricate a polycrystalline silicon field effect device according to the present invention. A thin oxide layer 28 is deposited over the surface of the device, preferably using Plasma Enhanced Chemical Vapor Deposition (PECVD). This allows formation of a good quality oxide layer at relatively low temperatures, between 400°C and 700°C. Layer 28 is preferably deposited to a thickness of approximately 500 angstroms, followed by a densification step performed by heating the device to a temperature of preferably above 850°C. This densification step, in addition to improving the quality of the oxide layer 28 , is also preferably used to anneal and activate the N + and P + implants in the active areas of the device. The oxide layer 28 will be used as a dielectric for a field effect device, so the quality of oxide layer 28 is important. Referring to Figure 2 , a shared contact region 30 is formed in the oxide layer 28 with a mask and etch step, followed by the deposition of an undoped polycrystalline silicon layer 32 to a depth of approximately 2000 angstroms. A mask is then used to define the shared contact region and an N + implant is made to form region 34 . This N + region within the polycrystalline silicon layer 32 makes good electrical contact with both the active region 18 and the polycrystalline silicon signal line 20 . The N + implant area is larger than the actual shared contact region 30 and preferably extends part way onto the field oxide region 12 . Referring to Figure 3 , a P + implant mask is then made, followed by a P + step to form region 36 and 38. Region 38 forms one source/drain region of the polycrystalline silicon transistor, and the V cc interconnect lines. P + region 36 forms the other source/drain region of the polycrystalline silicon transistor, and also forms a diode at its interface 40 with N + region 34 . Preferably, the layout of the photomasks causes the implanted N + and P + region 34 , 36 , to overlap slightly, to insure diode formation at the resulting interface 40 . N - channel region 42 is then formed by means of a blanket N - implant over the surface of the device. This implant need not be masked, since its doping level is relatively light compared to that of the N + and P + regions 34 , 38 , 40 . Region 42 forms the conductive channel of the polycrystalline silicon P-channel transistor for which the P + regions 36, 38 are the source and drain. After all implants have been made into the second polycrystalline silicon layer 32 , a masking and etch step is performed to define the polycrystalline silicon transistors, the shared contact region, and the V cc interconnect lines. It is preferable to make all implants into the second layer of polycrystalline silicon before patterning such layer so that the polycrystalline silicon layer can be used to protect underlying areas of the device. The order in which the N + , P + , and N - implants are made is not important. Although these implants have been described above as being performed in the order N + , P + , N - , they could just as easily have been made in the order N - , N + , P + , or any other desired order. As described above, it is not necessary to use a mask for the N - implant. Referring to Figure 4 , once the second layer of polycrystalline silicon has been patterned, a thick oxide layer 44 is then formed over the surface of the ship. Oxide layer 44 is preferably formed from a deposited undoped oxide layer to a thickness of approximately 2000 angstroms, and a PSG or BPSG layer to a tickness of approximately 6000 angstroms. Insulating layer 44 may then be subjected to reflow in order to smooth its contours prior to metal deposition. After formation of insulating layer 44 is complete, a metal layer is deposited in patterned to form signal lines 46 . The remainder of the processing steps for the device are conventional. Figure 5 shows a preferred layout for a CMOS SRAM cell which utilizes the P-channel polycrystalline silicon transistors fabricated as designed above for use as load devices. Further details of such SRAM cell layout are described in the co-pending, related reference as described above. In addition to the first level polycrystalline silicon lines 20 , word lies 48 are also formed from the first level polycrystalline silicon layer. Contact region 50 are opened through the overlying insulating layer 44 to make contact with the various metal data signal lines. A metal device ground line makes contact with the SRAM cell through contact region 52 . The cell layout shown in Figure 5 is an 8-T, dual-port SRAM cell. Each of the polycrystalline silicon lines 48 forms the gate for two N-channel transistors. Each of the signal lines 20 form the gate for a signal N-channel transistor, and the active region 16 act as gates for the two P-channel polycrystalline silicon devices having channels in regions 42 . The P-channel devices are used as load devices between the shared contacts 30 and the V cc signal lines 38 . A schematic diagram corresponding to the cell layout of Figure 5 is shown in Figure 6 . N-channel transistors 60 , 62 combine with polycrystalline silicon P-channel transistors 64 , 66 to form the cross-coupled latch of the cell. N-channel transistors 68 and 70 are connected to the true and complement data write lines (DW) and (DWB) respectively. N-channel transistors 72 and 74 are connected to the true and complement data write signal lines (DR) and (DRB) respectively. Diodes 76 , 78 are those formed by the P-N interfaces 40 , and connect to common nodes 80 , 82 , respectively. The common nodes 80 and 82 correspond to the active region 16 shown in Figures 1-4 and act as the gate region for the P-channel transistors 66 , 64 . Transistors 68 , 70 are gated by the word write signal line WW, and read transistors 72 , 74 are controlled by the word read signal line WR. Lines WW and WR correspond to the polycrystalline word lines 48 shown in Figure 5. The lines DW, DR, DWB, DRB, and the ground connection are the metal signal lines which make contact to contact regions 50 and 52 of Figure 5 . Operation of the 8-T SRAM cell of Figure 6 is conventional, and is readily apparent to those skilled in the art. It will apparent to those skilled in the art that the techniques described above can be used in many different situations. For example, the polycrystalline silicon P-channel loads can be used in single port 6-T cells as well as the dual-port 8-T cells described. Cell layouts other than that shown in Figure 5 may also be used, and some layouts may make formation of the diodes 76 , 78 undesirable or unnecessary. If desired, the gate oxide layer 28 can be grown instead of deposited, although this relatively high temperature step may not be desirable in some process flows. In addition, circuit designs other than SRAM cells may be able to make use of N-channel polycrystalline silicon transistors, and these can be fabricated using the described techniques simply by forming N + source/drain regions and a P - channel. The CMOS SRAM cell described above has several important advantages over prior art cells. The high value polycrystalline silicon resistor and back-to-back diode load devices limited current flow therethrough to approximately a few picoamps, limiting the overall speed of the device. The use of the polycrystalline silicon P-channel devices allows a load of a few hundred nanoamps to drive switching of the SRAM cell. The quality of the polycrystalline silicon transistors is not high compared to those formed in a monocrystalline silicon substrate, but their performance in an SRAM cell is significantly better than that of the previous high resistance load devices. Since the P-channel devices provide a high resistance when turned off, and a relatively low resistance when turned on, giving a lower impedance path to the power supply, the SRAM cell is more stable to noise and soft errors such as alpha particle impacts. The cell is faster due to the higher switching current, and works well with lower supply voltages. The particular layout described in connection with Figure 5 has the advantage that a relatively long, narrow P-channel device is formed. This gives a high OFF resistance desired for the reasons described above, while also providing a significantly lower ON resistance compared to resistive load devices. While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the invention as defined by the appended claims.

Claims: A method for fabricating field effect devices in an integrated circuit comprising the steps of: forming an active region (16) in a semiconductor substrate; forming a first field effect device (60) in the semiconductor substrate (10) , said first field effect device having source/drain regions opposite a gate electrode (20) formed from a first layer of polysilicon (20) and a channel under the gate electrode within the substrate (10) said channel being separated from the gate electrode by a first oxide layer (22); forming a second oxide layer (28) over the substrate (10); forming an opening through the second oxide layer (28) to expose an underlying conductive region (18,20); forming a second layer of polycrystalline silicon (32) over the second oxide layer (28) and the exposed underlying conductive region (18,20); forming, for a second field effect device (64), source/drain regions (36,38) in the second layer of polycrystalline silicon (32); forming a region (42) to constitute a channel element in the second layer of polycrystalline silicon (32) between the source/drain regions (36,38) over the active region (16); and etching portions of the second layer of polycrystalline silicon (32) to define said channel element (42) as an elongate element connecting the source/drain regions (36,38) of the second field effect device (64), wherein the second field effect device has a gate formed by the active region (16); wherein: the step of forming the first field effect device (60) comprises carrying out a process step to form the first oxide layer (22) over the substrate prior to definition of the gate electrode (20) of the first field effect device (60), said process step being distinct from the process step used to form the second oxide layer (28) of the second field effect device (64); and wherein the step of forming the second layer of polycrystalline silicon (32) is carried out in a separate process step to the one in which the first layer of polysilicon (20) is formed. The method of claim 1, wherein said second oxide layer forming step comprises the step of depositing an oxide layer. The method of claim 2, wherein the depositing step uses plasma enhanced chemical vapour deposition. The method of claim 2 or 3, wherein said second oxide layer is deposited at temperatures between 400°C and 700°C. The method of any one of claims 2 to 4, wherein said second oxide is layer is 500Å thick. The method of any one of claims 2 to 5, wherein said second oxide layer is subjected to a densification step, involving heating. The method of claim 1, wherein said second oxide layer forming step comprises the step of growing an oxide layer. The method of any preceding claim, wherein said first field effect device (60) is an n-channel field effect device, with n-type source/drain regions. The method of any preceding claim wherein said second field effect device (64) is a p-channel field effect device, with p-type source/drain regions. The method of claim 9, further comprising the step of: before said etching step, forming an n-type conductive region in the second polycrystalline silicon layer adjacent one of the p-type source/drain regions of the second field effect device and covering the opening formed in the second oxide layer (28), wherein a P-N junction is formed between the n-type conductive region and said p-type source/drain region. The method of any preceding claim further comprising the step of: forming a further n-channel field effect device (68) wherein the exposed underlying conductive region (18) is a source/drain region of the second n-channel transistor. The method of claim 9 when dependent upon claim 8, wherein said first polysilicon layer (20) makes electrical contact with the active area (18,16) in the substrate and the underlying conductive region comprises a first source/drain region of the first field effect device, whereby the first and second field effect devices are serially connected and their gate electrodes are interconnected, to form an inverter structure. The method of claim 1, wherein said steps of forming the source/drain and channel regions in the second layer of polycrystalline silicon comprise the steps of: lightly implanting an n-type impurity in a region which will become a p-channel region; and heavily implanting a p-type impurity in regions adjacent to the p-channel region to define source/drain regions for the p-channel transistor. The method of claim 13, further comprising the step of heavily implanting an n-type impurity over the opening in the second oxide layer, wherein a p-n junction is formed between the region containing the heavy p-type implant and the region containing the heavy n-type implant. The method of claim 14, wherein said light implant step is performed after said heavy implant steps. The method of claim 14, wherein said light implant step is performed between said heavy implant steps. The method of claim 14, wherein said heavy n-type implant step is performed before said heavy p-type implant step. The method of claim 9 when dependent on claim 8 further comprising the steps of: before the step of forming said second oxide layer (28) forming a second n-channel field effect device (62) having source/drain regions opposite a gate electrode formed from the first layer of polysilicon (20) , wherein a first source/drain region of the second n-channel field effect device (62) is common with a first source/drain region of the first field effect device (60); forming openings in the second oxide layer (28) to expose portions of the gate electrodes and second source/drain regions of the n-channel field effect devices (60,62); forming the second polycrystalline layer (32) over said openings; forming a second p-channel field effect device (66) in the second polycrystalline layer (32) wherein the second source/drain regions of the n-channel field effect devices (60,62) act as the gate electrodes (16) for the p-channel field effect devices (66,64), the first source/drain regions (38) of the p-channel field effect devices each connect to a power line and the second source/drain regions (36) of the p-channel field effect devices each connect to both a gate (20) of one of the n-channel field effect devices (62,60) and the second source/drain region (18) of the other n-channel field effect device transistor, to form a cross-coupled latch. The method of claim 18, wherein the process step to form the first oxide layer (22) over the substrate prior to definition of the gate electrode (20) of the first field effect device also forms the gate oxide of the second n-channel field effect device and the process step to form the second oxide layer (28) of the second field effect device also forms the gate oxide layer of the second p-channel field effect device. The method of claims 18 or 19 further comprising the step of forming separate n-type conductive regions (34) in each of the second source/drain regions (36) of the p-channel field effect devices wherein each of the n-type regions (34) connects to the second source/drain regions (18) of one of the n-channel field effect devices.

Inventors: CHAN TSIU C, GURITZ ELMER H, HAN YU-PIN, CHAN, TSIU C., GURITZ, ELMER H., HAN, YU-PIN
Applicants: ST MICROELECTRONICS INC, STMICROELECTRONICS, INC.
Application year: 1991
Main classification: H01L27
IPC codes: H01L27, H01L21