Superconducting field-effect transistor with inverted MISFET structure and method for making the same

Abstract: This field-effect transistor comprises a conductive substrate (2) serving as the gate electrode, an insulating barrier layer (3), and a superconducting channel layer (1) on top of the barrier layer (3). The superconductor layer (1) carries a pair of mutually spaced electrodes (4, 5) forming source and drain, respectively. The substrate is provided with an appropriate gate contact (6). The substrate (2) consists of a material belonging to the same crystallographic family as the barrier layer (3). In a preferred embodiment, the substrate (2) is niobium-doped strontium titanate, the barrier layer (3) is undoped strontium titanate, and the superconductor (1) is a thin film of a material having a lattice constant at least approximately similar to the one of the materials of the substrate (2) and barrier (3) layers. A preferred material of this type is YBa₂Cu₃O 7-δ , where 0 ≦ δ ≦ 0,5.

Description: This invention relates to field-effect transistors having a current channel consisting of high-T c superconducting material the conductivity of which can be reproducibly influenced by an electrical field, and whose structure is that of an inverted MISFET (Metal-Insulator-Superconductor) in the sense that the substrate is used as the gate electrode. The invention further relates to a method for making superconducting field-effect transistors with inverted MISFET structure. For several decades, the electronics industry has made enormous efforts to shrink the size of electronic components and circuits with the aim of increasing the speed of operation and of reducing the power consumption/dissipation. These efforts have led to the development of integrated circuits and multi-layer ceramic devices which, in a volume of a few cubic millimeters, contain many thousands of transistors and other circuit components. These devices have very high operating speeds owing to the shortened distances the electrons need to travel inside of them. All of the modern circuits use advanced semiconductor materials, such as silicon and gallium arsenide, for example. The discovery by Bednorz and Muller (Z. Phys., B64 (1986) p. 189) of a new class of superconductor materials has of course opened another avenue to even lower power consumption and caused a worldwide search for possible applications of these materials in electronic circuitry. A number of studies on the electric field-effect in copper oxide compounds have been reported (for example by U. Kabasawa et al. in Japanese Journ. of Appl. Phys. 29 L86, 1990), but so far only minor field-effects in high-T c superconductors have been found. However, EP-A-0 324 044 already describes a three-terminal field-effect device with a superconducting channel in which electric fields are used to control the transport properties of channel layers consisting of high-T c superconductor materials. While this seemed to be a promising approach, growth studies of such devices have shown that in the suggested configuration the ultrathin superconducting layers readily degrade during deposition of insulator layer and top electrode. EP-A-354804 discloses a superconductive transistor with a semiconductive substrate on which two insulating films are arranged. On the upper insulating film a drain electrode and a source electrode are arranged as well as an upper gate electrode on a gate insulator. In the substrate a lower gate electrode is arranged. For the use of this device the upper gate electrode is indispensable whereas the lower gate electrode is only used as a subsidiary electrode. JP-A-1101676 & Abstract of Japanese Patent Application discloses a superconducting transistor which controls a superconducting current flowing to a direction where the critical supercurrent is large by a superconducting current flowing to a direction where the current density is small. An oxide superconductor is provided on a crystal substrate so that the c axis of the oxide superconductor is aligned with that of the crystal substrate, wherein two electrodes distantly connected to the oxide superconductor perpendicular to the c axis, and a third electrode is provided in a place other than diagonal lines connecting the two electrodes. Current control is implemented by changing a superconducting current perpendicularly flowing relative to the c axis of the oxide superconductor to a normal conductive current by a current which is smaller than that flowing along the c axis. According to the constitution, large superconducting currents can be controlled by small currents, and superconducting transistors which are easy to be fabricated can be obtained. JP-A-64000779 & Abstract of Japanese Patent Patent Application discloses a superconducting transistor overcoming the limits of the high density and the high speed of a semiconductor device by a method wherein an oxide film having a channel layer in which phase transition of superconductor-semiconductor-insulator is created is employed and source and drain electrodes and a gate electrode which controls the carrier concentration in the channel layer are provided. A silicon oxide film is formed on the surface of a p-type Si substrate doped with boron. An oxide superconducting film is formed by sputtering and patterned to form sorce and drain main electrodes. Terminal electrodes composed of Au films are formed and a gate electrode composed of an Au film is formed on the rear surface of the substrate. In this device, the surface part of the oxide semiconductor film is used as a channel layer and phase transition between a high resistance semiconductor and a superconductor is created in the channel layer by controlling the carrier concentration in the channel layer by the gate electrode. JP-A-63283178 & Abstract of Japanese Patent Patent Application discloses a superconducting FET which operates at a high temperature with stable characteristics by employing a laminated layer structure of an oxide superconductor and nonmagnetic transition metal compound exhibiting superconductor-semiconductor phase transfer by applying a voltage thereto. A nonmagnetic transition metal oxide, an oxide having a channel for causing a superconductor-semiconductor phase transfer are laminated by a sputtering method through an SiO2 film on a p-type Si substrate, and electrodes of source, drain and gate are attached thereto. When the gate electrode is biased to zero or negative, a laminated layer film exhibits superconductive, while when it is biased to positive, hole concentration in the film near a gate is reduced, normal magnetic ions are generated in the film to become normal conductive, and the FET is turned OFF. EP 0324220 discloses a method of preparing superconducting thin films with controlled crystallite orientation onto a variety of substrates. A thin buffer layer of oriented polycrystalline SrTiO3 is deposited onto the desired substrate to form simultaneously a diffusion barrier and a lattice-matched, preferred orientation layer for the polycrystalline epitaxy of the superconducting thin film. In accordance with the present invention, this drawback is avoided through deposition of the superconducting film after the insulating layer, and locating the gate electrode underneath the insulator and the high-T c film. Still in accordance with the present invention, a conducting substrate is used as the gate electrode, and to facilitate the growth of preferably perfect crystals, substrate and insulator are chosen from the same crystallographic family of materials, that is, the lattice constants of the materials chosen to at least approximately match. For example, electrically conducting Nb-doped SrTiO 3 is used for the substrate, and undoped SrTiO 3 is used for the insulator layer. The use of niobium-doped strontium titanate Nb:SrTiO 3 in a high-T c superconductor structure was described by H. Hasegawa et al. in their paper "Contact between High-T c Superconductor and Semiconducting Niobium-Doped SrTiO 3 ", Japanese Journ. of Appl. Phys., Vol. 28, No. 12, Dec. 1988, pp. L 2210-L 2212, and in their EP-A-0 371 462. These references describe a diode structure where a superconducting film is deposited onto an Nb-doped SrTiO 3 substrate. The authors of these references are only interested in measuring the rectifying properties and the resistance in forward and reverse directions. They "demonstrated that there are unknown interfacial layers between the two materials", a problem that the present invention elegantly overcomes. This invention is based on experimental evidence for a significant electric field-effect recently discovered to exist in thin superconducting films. These experiments were performed with materials of the copper oxide class of superconductors, in particular YBa 2 Cu 3 O 7-δ . Thin films of superconducting YBa 2 Cu 3 O 7-δ are already known from EP-A-0 293 836. Eptiaxial growth of YBa 2 Cu 3 O 7-δ is described in EP-A-0 329 103. For the purposes of the present invention, the value of "δ" shall be considered to be close to zero (preferred), but it can be as large as 0,5. Those skilled in the art of high-T c superconductor materials will appreciate that many other materials in that class will be equally suited for the field-effect transistor structures of the MISFET type, as herein suggested. Also, other methods for depositing films of high-T c materials and of SrTiO 3 are known in the art, such as laser evaporation, electron beam evaporation and molecular beam epitaxy. While the acronym "MISFET" is usually employed to characterize Metal-Insulator-Semiconductor Field-Effect Transistor structures, this term will in the following description be maintained for describing an analogous structure, although the embodiments of the present invention to be described will use different materials, viz. electrically conducting Nb-doped SrTiO 3 in place of the Metal, and a superconductor instead of the Semiconductor. MISFET-type structures have been developed in accordance with the present invention which allow the application of electric fields larger than 10 7 V/cm across insulating SrTiO 3 barriers on ultrathin epitaxially grown YBa 2 Cu 3 O 7-δ channel layers. Epitaxial growth of YBa 2 Cu 3 O 7-δ by rf-magnetron sputtering is described in EP-A-0 343 649. In these structures, the normal-state resistivity and the density of free carriers in the YBa 2 Cu 3 O 7-δ films can be modified substantially with gate voltages of on the order of 50 V. Shortly after the discovery of the high-T c superconductor materials, Bednorz et al. in their above-cited EP-A-0 324 044 predicted on theoretical grounds that high-T c superconductor materials may bear an electric field-effect which is much larger than that in low-T c superconductor materials: The length scale by which electrostatic fields are screened in conducting materials is given by the sum L D + L DZ of the Debye length L D = (ε o ε r kT/q 2 n) 1/2 and the width of eventual depletion zones L DZ = N/n. Here, ε o and ε r are the dielectric constants of the vacuum and of the conducting material, respectively, k is the Boltzmann constant, T is the absolute temperature, q is the elementary charge, n is the density of mobile carriers, and N the induced areal carrier density. Because of their high carrier density, low-T c superconductors usually screen electric fields so well that the fields only have a minor influence on materials properties. To attenuate the screening, recent experiments on the electric field-effect in low-T c superconductors have focused on compounds with exceptionally low carrier density, like doped SrTiO 3 , with niobium as the dopant, for example. In high-T c superconductor compounds, larger field-effects are expected owing to their intrinsically low carrier concentration and because of their small coherence length. The low carrier concentration of about 3 ... 5 × 10 21 /cm 3 leads to screening lengths in the range of tenths of nanometers, and the small coherence lengths allow the fabrication of ultrathin layers with respectable critical temperatures. Superconducting films as thin as 1...2 nm have already been grown; electric fields can penetrate such films to a considerable extent. It is an object of the present invention as claimed to propose superconducting field-effect transistors with an inverted MISFET structure where the superconducting channel layer is deposited on top of the insulating barrier layer so as to avoid degradation effects that have been found to impair the functioning of prior art devices. It is a further object of the invention as claimed to teach a method of making superconducting field-effect transistors whose inverted MISFET structure permits the deposition of the superconducting channel layer after the deposition of the insulating barrier layer. It is still another object of the invention as claimed to propose the use of materials for the substrate and insulator layer which have at least approximately the same lattice constants so as to facilitate crystal perfection. The problem to be solved by the invention as claimed is to provide a superconducting field-effect transistor which due to a better lattice match between the substrate and the insulator provides a smaller defect concentration in the superconducting layer. The lattice match is achieved by exploiting the fact that the electrically conductive substrate as well as the insulating layer can be made from the same base material, namely SrTiO 3 , which being undoped is an insulator and which being Nb-doped is conductive. Furthermore, SrTiO 3 has nearly the same lattice constant as has the high-Tc superconductor YBa 2 Cu 3 O 7-δ . Hence a lattice match is rendered possible also for this configuration of materials. Details of two embodiments of the transistor and of the inventive method will hereafter be explained by way of example, with reference to the attached drawings in which: Fig. 1 is a schematic diagram of a first embodiment of a field-effect transistor in accordance with the invention; Fig. 2 is a schematic diagram of a second embodiment of an inventive field-effect transistor; Fig. 3 shows the I G /V G characteristics of the field-effect transistor of Fig. 1; Fig. 4 is a diagram showing the dependence of the changes of the channel resistivity as a function of the gate voltage V G ; Fig. 5 shows the dependence of the channel resistivity as a function of the absolute temperature. To apply large electric fields on thin films of superconducting YBa 2 Cu 3 O 7 , in accordance with the invention, an inverted MISFET-structure as shown in Fig.1 is used. In this structure, a superconducting film 1 of the thickness s is separated from a gate electrode 2 by an insulating layer 3 of the thickness t. Besides the thickness of the superconductor, the resistivity p i and the breakthrough field strength E BD of the insulator are crucial parameters. The required values for E BD and for ρ i can be simply estimated, if space charge effects are neglected: To induce a surface charge density in superconducting film 1 which corresponds to the unperturbed density n of mobile charge carriers, the capacitor consisting of gate electrode 2 and superconductor film 1 has to be biased with a voltage V G = qnst ε 0 ε i where ε i is the dielectric constant of the insulator 3. Equation (1) implies that to modulate the carrier density in high-T c superconductors substantially, the product ε i × E BD of the dielectric constant ε i and the breakdown field strength E BD has to be of the order of 10 8 V/cm. (For comparison, SiO 2 has an ε i × E BD product of 4 × 10 7 V/cm at room temperature). In addition, the normal-state resistivity of the insulator has to be sufficiently high to avoid leakage currents which result in an input loss V G × I G . For a typical case of I G < I DS /100 and I DS = 10µA, and an area of the gate electrode 2 of 1mm 2 , the resistivity must be higher than 10 14 Ωcm/ε i at operating temperature. In view of these requirements, insulating layers with high dielectric constants are recommended. Therefore, and for its good compatibility with the growth of YBa 2 Cu 3 O 7 , SrTiO 3 is selected as barrier material for insulating layer 3. The compatibility of YBa 2 Cu 3 O 7 with SrTiO 3 has already been pointed out in EP-A-0 299 870 and EP-A-0 301 646, and the use of a buffer layer of oriented polycrystalline SrTiO 3 has been described in EP-A-0 324 220 and EP-A-0 341 788. The method recommended for fabricating the MISFET structure of Fig. 1 with a SrTiO 3 barrier layer 3 involves the following steps: 1. A gate electrode 2 is provided in the form of a (conductive) n-type {100} -oriented Nb-doped SrTiO 3 single crystal grown by a conventional zone melting technique. The doping factor is between 10 -3 and 5% niobium, preferably at 0,05% Nb. This gate electrode 2 is used as the substrate for all further depositions. It should be pointed out that, while a single-crystal substrate is preferred, a polycrystalline or amorphous substrate may be used as well. Also, dopants other than niobium may be used to render the SrTiO 3 conducting. One example is an oxygen deficit. 2. On top of the substrate 2, a {100}-oriented insulating layer 3 of SrTiO 3 is epitaxially grown by reactive rf-magnetron sputtering at 6,7 Pa in an O 2 /Ar atmosphere at 650°C (temperature of the sample holder). The thickness of this layer can be in the range of 1 to 1000 nm. 3. Without breaking vacuum, a superconducting film 1 of YBa 2 Cu 3 O 7-δ is epitaxially grown on top of the insulating SrTiO 3 layer 3 by hollow cathode magnetron sputtering, wherein the value of "δ" is preferably equal to zero, but can be as large as 0,5. The thickness of the superconductor layer can be in the range of 1 to 1000 nm. 4. Metal pads, for example gold pads 4 and 5, are then sputtered onto the YBa 2 Cu 3 O 7-δ top layer 1 to form source and drain contacts, respectively. 5. Finally, a gate contact 6 is provided by diffusing silver into the Nb-doped SrTiO 3 gate/substrate 2. Fig. 2 shows a slightly different (but more truly MISFET) structure. The preferred way to manufacture this structure involves the following steps: 1. A {100}-oriented SrTiO 3 layer 7 is provided as an insulator which is polished down to a thickness of 20...30 µm. 2. On top of the thinned insulator 7, a YBa 2 Cu 3 O 7-δ film 8 is sputtered, wherein the value of "δ" is preferably equal to zero, but can be up to 0,5. 3. Gold pads 9 and 10 are provided on top of the superconductor layer 8 to form source and drain contacts, respectively. 4. On the back side of the thinned insulator, a conducting gate electrode 11 in the form of a metal layer, a gold layer, for example, is deposited. It bears an appropriate contact 12. 5. Optionally, gate electrode 11 may be supported on an insulating substrate 13, be it for stability, as indicated in Fig. 2. Fig. 3 shows a typical characteristic of the gate current I G through the insulating layer 3 as a function of the applied gate voltage V G for a device in accordance with Fig. 1. The measured characteristic is the one expected for a pin-junction, the superconductor and the substrate being the p and n electrodes, respectively. In one sample studied, the insulating barrier had a resistivity of 4 × 10 13 Ω cm at a forward bias of 3 V, and of 4 × 10 14 Ω cm at a reverse bias of 20 V. Breakdown field strengths at room temperature of 5 × 10 5 V/cm and of 1.5 × 10 7 V/cm were obtained in the forward and reverse directions, respectively. The capacitance of this sample was 2 × 10 -7 F/cm 2 at room temperature. This value corresponds to a relatively low ε i = 8 (t=40 nm). This low dielectric constant may be caused by an insulating surface layer on the Nb-doped SrTiO 3 substrate, which was observed in agreement with a report by Hasegawa et al. in Japan. Journ. of Appl. Phys., 28 L2210 (1989). The layer has a breakdown voltage of about 2 V. Nevertheless, the ε i E BD products of the SrTiO 3 barrier layers under reverse bias were about 10 8 V/cm, which is the limit of the values required by Eq. (1). The influence of the gate voltage V G on the channel resistance R DS of a sample that consists of 10 nm thick YBa 2 Cu 3 O 7-δ film on a 40 nm thick SrTiO 3 barrier layer is shown in Fig. 4. Obvious from the diagram is an approximately linear dependence of the measured normal-state resistivity on the gate voltage, and that the effect on resistivity changes sign when the gate voltage is reversed. The measured polarity of the voltage induced resistance change agrees with the theoretical expectation: YBa 2 Cu 3 O 7-δ is a p-type conductor, hence a positive voltage V G at the gate electrode depletes the free carrier concentration in the channel and, therefore, increases the channel resistance R DS , whereas a negative voltage V G at the gate electrode enhances the free carrier concentration in the channel and, therefore, decreases the channel resistance R DS . The value of the measured channel resistance R DS (V G ) agrees well with the theoretical prediction: Applying 30 V to the sample that was used to generate Fig. 4 and which has a capacitance of 2 × 10 -7 F/cm 2 , induces a change in the electron density on the electrodes of 2 × 10 13 /cm 2 . On the other hand, YBa 2 Cu 3 O 7-δ has a carrier density of about 3 - 5 × 10 21 /cm 3 , and this corresponds to an areal density of mobile holes in the 10 nm thick channel layer of 3 - 5 × 10 15 /cm 2 . This means that, within experimental error, at any temperature a change of the free carrier density in the channel results in a corresponding change in R DS . The temperature dependence of the resistivity R DS (T) of the YBa 2 Cu 3 O 7-δ film is shown in Fig. 5. The sample is typical for all devices of the type shown in Fig. 1. The temperature dependence of the voltage-induced variation of the channel resistance change ΔR DS /R DS (V G , T) for this sample is depicted in Fig. 4. As shown by this figure, within experimental scatter, the fractional change of the channel resistance ΔR DS /R DS is almost constant as a function of temperature. A temperature-independent ΔR DS /R DS (V G ) ratio is observed down to T c (R DS = 0). The change of the channel resistance induced by the gate voltage V G corresponds to a change of the R DS (T) characteristic at midpoint T c of 50 mK for V G = 18 V. From the measurements taken with several sample embodiments of the field-effect transistor in accordance with the invention, it has been determined that the operating gate voltage V G should be in the range between 0,1 and 50 V, the thickness s of the superconducting film should be in the range between 1 and 30 nm, and the thickness of the insulating layer should be in the range between 0,3 and 100 nm. To make sure that the structures prepared in accordance with the present invention indeed perform as expected, i.e. that the current flow in the channel can actually be controlled by the electrical field-effect, spot-checking measurements have been made as follows: 1. Measurement of R DS (V G ) on samples that had barrier layer resistances which were lower by a factor of 500 (at 20 V) than the sample yielding the curves in Fig. 4. This measurement showed the same R DS (V G ) characteristics, demonstrating that the observed effect is not caused by the finite gate current I G . 2. To elucidate whether V G primarily affects the channel resistance R DS or whether the effect is based on a change of V DS , R DS was measured for different channel currents I DS . Even if I DS is varied by four orders of magnitude, an applied gate voltage results in a change of the channel resistance R DS and does not induce significant voltages in the channel layer. MISFET-type heterostructures consisting of YBa 2 Cu 3 O 7-δ /SrTiO 3 multilayers have been developed which allow the application of electric fields larger than 10 7 V/cm to superconducting films of YBa 2 Cu 3 O 7-δ . In these devices, electric field-effects generate changes in the channel resistance. The YBa 2 Cu 3 O 7-δ films have a preferred thickness on the order of 10 nm and are operated with gate voltages of about 30 Volts. The channel resistivity changes can be attributed to equally strong changes of the carrier density in the high-T c superconductor.

Claims: Field-effect transistor comprising an electrical-field-controlled current channel, a gate electrode, a source electrode and a drain electrode, whereby an insulating barrier layer (3, 7) is arranged on top of an electrically conductive, mono- or polycrystalline substrate (2, 11), and a superconductive layer (1, 8) is arranged on top of said insulating barrier layer (3, 7) and serves as said current channel, and pads (4, 5, 9, 10) are arranged on top of said superconductive layer (1, 8) at a mutual distance from one another and serve as said source and drain electrodes, respectively, characterized in that said substrate (2, 11) is provided with a contact (6, 12); whereby the lattice constants of said substrate (2, 11) and said insulating barrier layer (3, 7) at least approximately match, said substrate forming said gate electrode, and consisting of Nb-doped SrTiO 3 with a doping factor of between 10 -3 % and 10 % niobium, preferably 0,05 % Nb. Field-effect transistor in accordance with claim 1, characterized in that the lattice constants of said superconductive layer (1, 8) and said insulating barrier layer (3, 7) at least approximately match. Field-effect transistor in accordance with claim 1 or 2, characterized in that the crystallographic orientation of said substrate (2, 11) is {100}. Field-effect transistor in accordance with one of claims 1 to 3, characterized in that said insulating barrier layer (3, 7) consists of SrTiO 3 having a {100} crystallographic orientation, with a thickness in the range of 0,3 to 100 nm. Field-effect transistor in accordance with one of claims 1 to 4, characterized in that said superconductive layer (1, 8) consists of YBa 2 Cu 3 O 7-δ , wherein 0 ≤ δ ≤ 0.5, and has a thickness in the range of 1 to 30 nm. Field-effect transistor in accordance with one of claims 1 to 5, characterized in that said contact (6, 12) consists of silver diffused into said substrate (2, 11). Method of making a field-effect transistor having an electrical-field-controlled current channel and gate, source and drain electrodes, characterized by the following steps: providing a conductive substrate (2, 11) comprising at least one electrically conductive Nb-doped SrTiO 3 -crystal having a doping factor between 10 -3 % and 10 % niobium, preferably of 0,05% Nb; with an insulating barrier layer (3, 7) comprising SrTiO 3 on it; depositing a superconductive layer (1, 8) on the insulating barrier layer (3, 7); depositing pads (4, 5, 9, 10) on the superconductive layer (1, 8) at a predetermined mutual distance as source and drain electrodes, respectively; and providing a contact (6, 12) at said substrate (2, 11). Method in accordance with claim 7, characterized in that said substrate (2, 11) is provided comprising at least one conductive n-type {100}-oriented Nb-doped SrTiO 3 -crystal; on top of said substrate (2, 11) a {100}-oriented insulating barrier layer (3, 7) is deposited; on top of said insulating barrier layer (3, 7), a superconductive layer (1, 8) consisting of YBa 2 Cu 3 O 7-δ is deposited, wherein 0 ≤ δ ≤ 0.5; on said superconductive layer (1, 8) the pads (4, 5, 9, 10) are deposited to form the source and drain electrodes, respectively; the contact (6, 12) is provided at said substrate (2, 11). Method in accordance with claim 7 or 8, characterized in that said insulating barrier layer (3, 7) comprising SrTiO 3 is epitaxially grown by reactive rf-magnetron sputtering at 6.7 Pa in an O 2 /Ar atmosphere at 400 to 900°C. Method in accordance with one of claims 7 to 9, characterized in that said superconductive layer (1, 8) is epitaxially grown on top of the insulating barrier layer (3, 7). Method in accordance with one of claims 7 to 10, characterized in that said gate contact (6, 12) is provided by diffusing silver into the substrate (2, 11). Method in accordance with claim 7, characterized by the following steps: providing on the conductive substrate (2, 11) a {100}-oriented SrTiO 3 layer as the insulating barrier layer (3, 7) and thinning it down to a thickness of 20...30 µm; sputtering on top of the thinned insulating layer (3, 7), a YBa 2 Cu 3 O 7-δ layer as the superconductive layer (8), wherein 0 ≤ δ ≤ 0.5, with a thickness in the range of 1 to 10 nm; providing the pads (4, 5, 9, 10) on top of the superconductive layer (1, 8) to form the source and drain contacts, respectively; depositing a metallic layer on the backside of the thinned insulating layer (3, 7) to form the substrate (2, 11); applying the contact (6, 12) at the underside of said substrate (2, 11). Method in accordance with claim one of claims 7 to12, characterized in that the substrate (2, 11) comprises an insulating layer which is provided underneath said contact (6, 12).

Inventors: BEDNORZ JOHANNES GEORG DR, MANNHART JOCHEN DIETER DR, MUELLER CARL ALEXANDER PROF DR, BEDNORZ, JOHANNES GEORG, DR., MANNHART, JOCHEN DIETER, DR., MUELLER, CARL ALEXANDER, PROF. DR., Müller, Carl Alexander, Prof. Dr.
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1991
Main classification: H01L39
IPC codes: H01L39, H01L21, B05D5, H01B12