Frame synchronization dependent type bit synchronization extraction circuit

Abstract: A frame synchronization dependent type bit synchronization extraction circuit in an ISDN terminal equipment (TE) connected to a reference point S/T of an ISDN basic user network interface, for establishing bit synchronization between an internally produced signal and received data. To make the timing extraction jitter small and make the bit timing stable, it comprises a counter preset mode synchronization unit (21, 23, 26), a digital phase-lock loop mode synchronization unit (21,22,23,24,25), frame synchronization detection unit (30), and an inhibiting unit (27,28) for inhibiting the operation of the counter preset mode synchronization unit, and the bit synchronization is effected by only the digital phase locked loop mode synchronization unit after the frame synchronization is detected by the frame synchronization detection unit.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit synchronization extraction circuit used for bit synchronization in an integrated service digital network (ISDN) line interface connected to a reference point S/T of an ISDN basic user network interface, and more particularly relates to a bit synchronization extraction circuit which is dependent on frame synchronization. The bit synchronization extraction is included in an ISDN line interface which is included in an ISDN terminal equipment (TE) connected through the reference point S/T to a network termination (NT). In the ISDN terminal equipment (TE), to enable smooth bidirectional communication, the transmitting signal must be synchronized with the received signal. To this end, the bit synchronization extraction circuit generates a bit timing signal which is synchronized with the received signal. The bit timing signal is used as a clock signal for the transmitting signal. In the bit synchronization extraction circuit, it is desirable that the timing extraction jitter be as small as possible, and that the bit timing be stable in the presence of line noise. According to the recommendation of CCITT, the bit timing extraction jitter in the transmitting signal with respect to the received signal must be within ±7 percent of the bit period. 2. Description of the Related Art Conventionally, there are two types of bit synchronization extraction circuits, i.e., a counter preset mode circuit and a digital phase locked loop (DPLL) mode circuit. The conventional counter preset mode circuit has an advantage of a short time for extraction of the bit synchronization, but had the disadvantage of being sensitive against line noise and having a large timing extraction jitter. conventional DPLL mode has the advantage of also being resistant to line noise and having small timing extraction jitter, but has the disadvantage of taking a long time for bit synchronization extraction. That is, the amount of correction until establishment of bit synchronization could be 2.6 µs (5.2 µs/2) in the worst case. There is the disadvantage of the long time taken for establishment of bit synchronization due to the correction of this in steps of less than 0.36 µs (5.2 µs × 0.07). For example, if correction is made in steps of 0.16 µs, 16 steps of correction (2.6 µs ÷ 0.16 µs) is required until establishment of bit synchronization. Therefore, if there were eight protection stages, points of change of data of 128 bits (16 steps × 8 stages) would be required. Since there are of four points of change of data in the 48 bits of one frame (250 µs) in the minimum case, the maximum time for establishment of synchronisation would be 8 ms (128 bits/4 × 250 µs). The ISDN terminal equipment uses the bit timing extracted by the bit synchronization extraction circuit for transmiting data to the line. To ensure the restriction in transmitting data, i.e., to ensure a bit timing jitter within ±7 percent (0.36 µs), the latter DPLL mode has been used, since the restriction cannot be met by the former. IEEE International Conference on Communications 1987, Vol. 1, p. 596-600 shows a special frame format for achieving stable timing extraction. A digital phase lock loop is used but there is no suggestion of an inhibit means for inhibiting a counter pre-set mode synchronization means in accordance with a frame synchronization detection means. SUMMARY OF THE INVENTION An object of the present invention is to provide a frame synchronization dependent type bit synchronization extraction circuit in which the timing extraction jitter is as small as possible, and the bit timing is stable in the presence of line noise. The restriction on the bit timing jitter is a restriction for data transmission from the ISDN terminal equipment. Therefore, the operation of the DPLL for bit synchronization is made dependent on the frame synchronization in operation. Therefore, use is made of the fact that data is transmitted to the ISDN line from the ISDN terminal equipment connected to the ISDN user network interface only when synchronization of the received data has been established and when out of synchronization, data is not transmitted. According to one aspect of the present invention, there is provided a frame dependent bit synchronization extraction circuit as set out in claim 1. It is made possible to shorten the bit synchronization extraction time and, after frame synchronization has been established, due to the resistance to line noise and the small timing extraction jitter, ensure a bit timing extraction jitter, a restriction in data transmission, of within ±7 percent (0.36 µs). Another aspect of the present invention provides a bit synchronization extraction circuit as set out in claim 13. It is made possible to shorten the bit synchronization extraction time and, when frame synchronization has been established, due to the resistance to line noise and the small timing extraction jitter, ensure a bit timing extraction jitter, a restriction in data transmission, of within ±7 percent (0.36 µs). According to the present invention, by switching the bit synchronization extraction system depending on the frame synchronization, it is possible to shorten the bit synchronization extraction time and, after establishment of frame synchronization, due to the resistance to line noise and small timing extraction jitter, ensure a bit timing extraction jitter, a restriction when transmitting data, of within ±7 percent (0.36 µs). The restriction on the bit timing jitter is a restriction for data transmission. Therefore, the operation of the DPLL for bit synchronization is made dependent on the frame synchronization in operation. Therefore, using the fact that data is transmitted to the ISDN line from the ISDN terminal connected to the ISDN user network interface only when synchronization of the received data has been established and when out of synchronization, data is, not transmitted, One preferred embodiment of the present invention presets the counter unit and extracts bit synchronization at the point of change of the received signal by a change point detection unit when frame synchronization is not detected (that is, until reception of three consective normal frames). The operation at that time is the same as the counter preset mode. Further, when frame synchronization is detected, it compares the phases of the 192 kHz bit timing produced by division from the internally free-running oscillation circuit and the signal received from the NT and corrects the bit timing by the phase difference when frame synchronization is detected. This operation is the same as the DPLL mode. Another preferred embodiment of the present invention has a pseudo frame synchronization unit with P as the number of consecutive normal frames for establishment of frame synchronization (P ≤ 2) and Q ≥ 2 as the number of consecutive error frames for loss of frame synchronization, and presets the counter unit and detects bit synchronization at the point of change of the received signal by a change point detection unit when pseudo frame synchronization is not detected (that is, until reception of P number of normal frames). The operation at this time is the same as the counter preset mode. Further, it compares the phases of the 192 kHz bit timing produced by division from the internally free-running oscillation circuit and the signal received from NT and corrects the bit timing by the phase difference when pseudo frame synchronization is detected. The operation at this time is the same as the DPLL mode. At least one frame of time is ensured between the establishment of pseudo frame synchronization and establishment of frame synchronization. BRIEF DESCRIPTION OF THE DRAWINGS The above object and features of the present invention will be more apparent from the following description of the preferred embodiments in comparison with the prior arts with reference to the accompanying drawings, wherein: Figure 1 is a block diagram showing the system construction in the field of utilization in industry of the present invention; Fig. 2 is a view of the frame construction of data in an ISDN network in the field of utilization in industry of the present invention; Fig. 3 is a block diagram showing the ISDN line interface as background of the present invention; Fig. 4 is an explanatory view of the operation of the apparatus of Fig. 3; Fig. 5 is a block diagram showing an example of the conventional bit synchronization extraction unit; Fig. 6A to 6E are explanatory views of the operation of the apparatus of Fig. 5; Fig. 7 is a block diagram showing another example of a conventional bit synchronization extraction unit; Fig. 8 is an explanatory view of the operation of the apparatus of Fig. 7 in the case of an advance; Fig. 9 is an explanatory view of the operation of the apparatus of Fig. 7 in the case of a delay; Fig. 10 is a block diagram showing the principle of the present invention; Fig. 11 is a block diagram of a bit synchronization extraction circuit according to an embodiment of the present invention; Fig. 12 is an explanatory view of the operation of the circuit of Fig. 11; Fig. 13A is a circuit diagram of an oscillating unit 21 in the unit of Fig. 11; Fig. 13B shows the output waveform of the oscillating unit 21 shown in Fig. 13A; Fig. 14 is a circuit diagram of a phase comparison unit 24 in the unit of Fig. 11; Fig. 15 is an explanatory view of the operation of the unit 24 in the case of an advance; Fig. 16 is an explanatory view of the operation of the unit 24 in the case of a delay; Fig. 17 is a circuit diagram of a stage protection unit 25 in Fig. 11; Fig. 18 is an explanatory view of the operation of the unit 25 in the case of an advance; Fig. 19 is an explanatory view of the operation of the unit 25 in the case of a delay; Fig. 20 is a circuit diagram of a pulse adjustment unit 22 in Fig. 11; Fig. 21 is an explanatory view of the operation of the unit 22 in the case of an advance; Fig 22 is an explanatory view of the operation of the unit 22 in the case of a delay; Fig. 23 is a circuit diagram of a counter unit 23 in Fig. 11; Fig. 24 is an explanatory view of the operation of the unit 23 in Fig. 23; Fig. 25A is a circuit diagram of a change point detecting unit 26 in Fig. 11; Fig. 25B is an explanatory view of the operation of the unit 26 in Fig. 25A; Fig. 26 is a circuit diagram of a frame synchronization detection unit 30 in Fig. 11; Fig. 27 is an explanatory view of the operation of the unit 30 in Fig. 26; Fig. 28 is a block diagram of a bit synchronization extraction circuit according to another embodiment of the present invention; Fig. 29 is a circuit diagram of a pseudo frame synchronization detection unit 40 in Fig. 28; and Fig. 30 is an explanatory view of the operation of the unit 40 in Fig. 29. DESCRIPTION OF THE PREFERRED EMBODIMENTS For better understanding of the present invention, the technical field of the present invention and the conventional arts are first described with reference to Fig. 1 to Fig. 9. The construction of a system including a reference point S/T of an ISDN basic user network interface is shown in Fig. 1. In the figure, a network termination (NT) 61 connected to a network 60 is connected with an ISDN terminal equipment (TE) 62 through the S/T point. The frame construction of a signal sent between the network termination (NT) 61 and the ISDN terminal equipment (TE) 62 is shown in Fig. 2. As shown in the figure, in the ISDN basic user network interface, data is transmitted in both directions at a speed of 192 kbit/s (bit period is 5.2 µs) with 48 bits used as one frame (250 µs). To enable communication between the ISDN terminal equipment (TE) 62 and network termination (NT) 61, the ISDN terminal equipment (TE) 62 and the network termination (NT) 61 must operate at the same timing. However, the 192 kHz clock, as it is, produced by frequency division by the oscillator at the ISDN terminal equipment (TE) 62, is usually off in phase from the timing of the signal received from the network termination (NT) 61, so mutual communication is not possible. Therefore, the terminal equipment (TE) 62 must have the function of bit synchronization for making the 192 kHz clock produced by frequency division by the oscillator match with the timing of the received signal in both frequency and phase. Figure 3 is a block diagram showing the construction of a conventional ISDN line interface in the ISDN terminal equipment (TE) 62. In the figure, 81 is a receiver, 82 is a bit synchronization extraction unit, 83 is a frame synchronization detection unit, 84 is a frame disassembly unit, 85 is a frame assembly unit, 86 is a flipflop, and 87 is a driver. The receiver 61 receives data from the network termination (NT) 61 through the ISDN line. The bit synchronisation extraction unit 82 extracts the 192 kHz bit timing from the signal received from the network terminal (NT) 61 for the bit synchronization. The frame synchronization detection unit 83 deems that frame synchronization has been established when a normal 48 bit frame is successively received three times from the received signal for frame synchronization. The ISDN terminal equipment (TE) 62, when deeming that frame synchronization has been established, produces a 4 kHz frame timing from the frame construction and starts the disassembly of the received data, the assembly of the transmitting data, and the transmission of the signal. Further, when a normal 48 bit frame cannot be received two times in a row, it deems that loss of frame synchronization is produced and must immediately stop signal transmission. Subsequent to this, it starts the detection of frame synchronization again. The ISDN terminal equipment (TE) 62 must synchronize the transmitting signal to the bit timing extracted by the bit synchronization extraction unit 82. The bit timing extraction jitter when observed by the transmitting signal is regulated to within ±7 percent (0.36 µs) of the bit period, so the 192 kHz bit timing extracted with establishment of bit synchronization must be within ±7 percent (0.36 µs) of the received signal. The operation of the ISDN line interface of Fig. 3 will be explained by Fig. 4. The signal (a) received by the receiver 81 enters the bit synchronization extraction unit 82, the frame synchronization detection unit 83, and the frame disassembly unit 84. At the bit synchronization extraction unit 83, a 192 kHz bit timing signal (b) synchronized with and having the same phase as the received signal is prepared. The frame synchronization detection unit 83, when receiving three normal frames in a row, outputs "1" as the frame synchronization signal (c) to show that frame synchronization has been established and, when not able to receive two normal frames in a row, outputs "0" as the frame synchronization signal (c) to show that it has been loss of frame synchronization. At the frame disassembly unit 84, the received signal is disassembled into B1, B2 and D when frame synchronization is established. At the frame assembly unit 85, when frame synchronization has been established, B1, B2, and D are assembled into frames and the flipflop 86 is used to match the phase to the bit timing signal (b) from the bit synchronization extraction unit 82, produce the transmitting data, and send it out through the driver 87. The present invention relates to the bit synchronization extraction unit 82 in the above ISDN user network interface. In the bit synchronization extraction unit 82, it is desirable that the bit synchronization extraction time be as short as possible, that the timing extraction jitter be as small as possible, and that the bit timing be stable with respect to line noise. Conventional bit synchronization extraction units came in a counter preset mode and a DPLL mode. The counter preset mode is explained using Fig. 5 and Fig. 6A-6E. In the figures, the change point detection unit 101 detects the point of change of the data a4 received from the line and generates a pulse a9. On the other hand, the clock signal a1 from the free-running oscillation unit 102 is divided by the counter unit 103 to make a2, and the counter unit 104 generating the bit timing is preset by the pulse from the change point detection unit 101. More specifically, to generate the bit timing signal a3 (Fig. 6E) of αHz (α = 192 × 10 3 ) synchronized with the received signal, the free-running signal a1 (Fig. 6A) of βHz (β = α × M × N, where M and N are integers, for example, M = 2 and N = 16 for β = 6.144 × 10 6 ) is prepared by the oscillation unit 102. This signal a1 is divided to 1/M by the counter unit 103 to make the signal a2 (Fig. 6B), while the signal a2 is divided to 1/N by the counter unit 104. The change point detection unit 101 detects the point of change p1 of the received signal and generates the pulse a9 (Fig. 6D) from the clock timings C1 and C2 by the signal a1. This pulse a9 is used to preset the counter unit 104. The counter unit 104 starts to count the 5.2 µs of bit period from the rising edge of the pulse a9. In this way, a bit timing signal of αHz synchronized with the received data is obtained. This counter preset system establishes bit synchronization immediately at the point of change of the received signal, but has the defects that the bit timing is immediately affected by line noise included in the received data and there is a large timing extraction jitter due to the presetting of the counter 2. The DPLL (digital phase locked loop) system will be explained using Fig. 7, Fig. 8, and Fig. 9. This system compares the phases of the bit timing signal a3 produced by frequency division from the internally free-running oscillator 121 and the data received from the line and uses the phase difference to correct the bit timing. More specifically, the bit synchronization extraction unit of the DPLL system, to produce the bit timing signal a3 of αHz (α = 192 × 10 3 ) synchronized with the received data a4, is comprised of an oscillation unit 121 which prepares a free-running signal a1 of βHz (β = α x M × N, where M and N are integers, for example, when M = 2 and N = 16, β = 6.144 × 10 6 ), a pulse adjustment unit 122 which divides the signal a1 to 1/M and further adjusts the increase or decrease of the pulse, a counter unit 123 which divides to 1/N the output a2 of the pulse adjustment unit 122 and prepares a bit timing signal a3 synchronized by bit with the received data a4, a phase comparison unit 124 which compares the phases of the received data a4 and the bit timing signal a3 of the output of the counter unit 123 and, when the bit timing is advanced, outputs an advance pulse a5 and when the bit timing is delayed, outputs a delay pulse a6, and a stage number protection unit 125 which outputs to the pulse adjustment unit 122 a decrease command signal a7 when the advance pulse a5 is continuously generated L number of times (for example, L = 8) without occurrence of a delay pulse a6 during that time and outputs an increase command signal a8 to the pulse adjustment unit 122 when the delay pulse a6 is continuously generated L number of times (for example, L = 8) without an advance pulse a5 occurring during that time. When the phases of the received data a4 and the bit timing signal a3 output from the counter unit 123 are compared and the bit timing is ahead, an advance pulse a5 is generated from the phase comparison unit 124. When the advance pulse a5 is continuously generated L number of times (for example, L = 8), a decrease command signal a7 is output to the pulse adjustment unit 122, which pulse adjustment unit 122 reduces the pulses. Therefore, when divided to 1/N by the counter unit 123, the bit timing becomes delayed by exactly 1/β (0.16 µs when β = 6.144 MHz) second of one step and the received data a4 is approached. By repeating this, gradually the phase of the bit timing signal a3 matches the received data a4. When comparing the phases of the received data a4 and the bit timing signal a3 of the output of the counter unit 123 and the bit timing is delayed, a delay pulse a6 is generated from the phase comparison unit 124. If the delay pulse a6 is continuously generated L times (for example, L = 8), an increase command signal a8 is output to the pulse adjustment unit 122 and the pulses are increased by the pulse adjustment unit 122. Therefore, when the output signal a2 of the pulse adjustment unit 122 is divided to 1/N by the counter unit 123, the bit timing signal a3 advances by exactly 1/β (0.16 µs when β = 6.144 MHz) of one step and the phase of the received data is approached. By repeating this, gradually the phase of the bit timing signal a3 matches the phase of the received data a4. In this method, if bit synchronization is obtained and the phases are made to match, the bit timing becomes stable with respect to line noise and, further, corrections are made in step amounts, so the timing extraction jitter is 1/β second (in this example, 0.16 µs). In this way, the conventional counter preset mode had the advantage of a short time for extraction of the bit synchronization, but had the disadvantage of being sensitive against line noise and having a large timing extraction jitter. Further, the conventional DPLL mode had the advantage of also being resistant to line noise and having small timing extraction jitter, but had the disadvantage of a lone bit synchronization extraction time. That is, the amount of correction until establishment of bit synchronization could be 2.6 µs (5.2 µs/2) in the worst case. There was the disadvantage of the long time taken for establishment of bit synchronization due to the correction of this in steps of less than 0.36 µs (5.2 × 0.07). For example, if correction is made in steps of 0.16 µs, 16 steps of correction (2.6 µs ÷ 0.16 µs) would be required until establishment of bit synchronization. Therefore, if there were eight protection stages, points of change of data of 128 bits (16 steps × 8 stages) would be required. Since there are four points of change of data in the 48 bits of one frame (250 µs) in the minimum case, the maximum time for establishment of synchronization would be 8 ms (128 bits/4 × 250 µs). The ISDN terminal equipment uses the bit timing extracted by the bit synchronization extraction circuit 82 for transmiting data to the line. To ensure the restriction in transmitting data, i.e., to ensure a bit timing jitter within ±7 percent (0.36 µs), the latter DPLL mode has been used, since the restriction cannot be met by the former. Now, embodiments of the present invention will be described in the following. Figure 10 is a block diagram of the principle of the present invention. In the figure, there is shown a bit synchronization extraction in an ISDN terminal equipment connected to a reference point S/T of an ISDN basic user network interface, for establishing bit synchronization between an internally produced signal and a received signal, wherein 1 is an oscillation unit which generates a free-running signal; 2 is a counter unit which divides the free-running signal and produces a bit synchronization signal of a desired frequency; 3 is a phase comparison unit which compares the phases of the output signal of the counter unit and the received data; 4 is a pulse adjustment unit which adjusts the number of pulses of the free-running signal in accordance with the phase difference obtained at the output of the phase comparison unit; 5 is a change point detection unit which detects a point of change of the received data; and 6 is a frame synchronization detection unit which detects the frame synchronization from the received data. When the frame synchronization detection unit 6 does not detect frame synchronization, the counter unit 2 is preset at the point of change of the received data by the change point detection unit 5 and the bit synchronization is extracted and, when the frame synchronization detection unit 6 detects frame synchronization, the number of pulses of the free-running signal is changed in accordance with the phase difference obtained at the output of the phase comparison unit 3. In place of the frame synchronization detection unit 6, use may be made of a pseudo frame synchronization detection unit 7 of no more than two as the number of concecutive normal frames for establishment of frame synchronization and at least two as the number of consecutive error frames for loss of frame synchronization. In this case, when the pseudo frame synchronization detection unit 7 does not detect pseudo frame synchronization, the counter unit 2 is preset at the point of change of the received data by the change point detection unit 5 and the bit synchronization is extracted and, when the pseudo frame synchronization detection unit 7 detects pseudo frame synchronization, the number of pulses of the free-running signal is changed in accordance with the phase difference obtained at the output of the phase comparison unit 3. Figure 11 is a block diagram showing the construction of a frame synchronization dependent type bit synchronization extraction circuit according to an embodiment of the present invention, while Fig. 12 is an explanatory view of the operation of the circuit of Fig. 11. In Fig. 11, the frame synchronization dependent type bit synchronization circuit is included in an ISDN line interface in an ISDN terminal equipment (TE). To produce a bit timing signal a3 of αHz (α = 192 × 10 3 ) synchronized with the received data a4, provision is made of an oscillation unit 21 which prepares a free-running signal of βHz (β = α × M × N, wherein M and N are integers, for example, when M = 2 and N = 16, β = 6.144 x 10 6 ); a pulse adjustment unit 22 which divides the signal a1 to 1/M and adjusts the increase or decrease of pulses; a counter unit 23 which divides the output a2 of the pulse adjustment unit 22 to 1/N and prepares a bit synchronized bit timing signal a3, a phase comparison unit 24 which compares the phases of the received data a4 and the bit timing signal a3 of the output of the counter unit 23 and, when the bit timing is advanced, outputs an advance pulse a5 and when the bit timing is delayed, outputs a delay pulse a6, and a stage protection unit 25 which, when L number of advance pulses a5 (for example, L = 8) are generated in a row without occurrence of a delay pulse a6 during that time, outputs a decrease command signal a7 to the pulse adjustment unit 22 and, when L number of delay pulses (for example, L = 8) are generated in a row without occurrence of an advance pulse a5 during that time, outputs an increase command signal a8 to the pulse adjustment unit 22. Further, it is provided with a change point detection unit 26 which detects a point of change of the received data a4 and outputs a change point detection pulse a9, a frame synchronization detection unit 30 which detects the frame synchronization from the received data and outputs a frame synchronization signal a10, an inverter 27 which inverts the frame synchronization signal a10, and an AND gate which obtains the logical AND of the change point detection pulse a9 from the change point detection unit 26 and the output of the inverter 27. The connection between the output of the counter unit 23 and an input of the phase comparison unit 24 is a PLL feedback route. As shown in Fig. 12, the circuit of Fig. 11 operates in the counter preset mode before frame synchronization is established and in the DPLL mode after the same. In the counter preset mode, where the frame synchronization signal a10 is a low level, the bit timing signal a3 of αHz (α = 192 × 10 3 ) synchronized with the received data a4 is produced by preparing a free-running signal a1 of βHz (β = α × M × N, where M and N are a integers, for example, when M = and N = 16, β = 6.144 × 10 3 ), dividing the signal a1 to 1/M by the pulse adjustment unit 22, and dividing the signal a2 to 1/N by the counter unit 23. The change point detection unit 26 detects a point of change of the received signal and generates a pulse a9 by the clock signal in the same way as in the past. The pulse a9 passes through the AND gate 28 and presets the counter unit 23. The counter unit 23 starts to count a bit period of 5.2 µs from the rising edge of the pulse a9. In this way, a bit timing signal of αHz bit synchronized with the received data is obtained. Therefore, the bit synchronization is established immediately at a point of change of the received data a4. When normal frames are received three times and the frame synchronization signal a10 becomes high level, the output of the invertor 27 becomes low level, the change point detection pulse a9 no longer passes through the AND gate 28, and the DPLL (digital phase locked loop) mode is entered. In this case, the phases of the bit timing signal a3 produced by division from the internally free-running oscillation unit 21 and the data a4 received from the line are compared by the phase comparison unit 24 and the phase difference is used to correct the bit timing. More specifically, the phases of the received data a4 and the output of the counter unit 23, i.e., the bit timing signal a3, are compared and, when the bit timing is advanced, an advance pulse a5 is generated from the phase comparison unit 24. If the advance pulses a5 continue to be generated for L number of times (for example, L = 8), a decrease command signal a7 is output to the pulse adjustment unit 22, which pulse adjustment unit 22 reduces the pulses. Therefore, when divided to 1/N by the counter unit 23, the bit timing is delayed by exactly 1/β of one step (0.16 µs when β = 6.144 MHz) and the received data a4 is approached. By repeating this, gradually the phase of the bit timing signal a3 matches the received data a4. Further, when the phases of the received data a4 and the output of the counter unit 23, i.e., the bit timing signal a3, are compared and the bit timing is delayed, a delay pulse a6 is generated from the phase comparison unit 24. When L number of delay pulses a6 (for example, L = 8) are generated in a row, an increase command signal a5 is output to the pulse adjustment unit 22, which pulse adjustment unit 22 increases the pulses. Therefore, when dividing to 1/N the signal a2 output adjustment unit 22 by the counter unit 23, the bit timing signal a3 advances by exactly 1/β of one step (0.16 µs when β = 6.144 MHz) and the phase of the received data is approached. By repeating this, the phase of the bit timing signal a3 gradually matches the phase of the received data. In this method, if bit synchronization is established and the phases match, the bit timing becomes stable with respect to line noise and since corrections are made in single steps, the timing extraction jitter is 1/β second (for example, 0.16 µs). If two error frames are received in a row, the frame synchronization signal a10 becomes low level and the process returns to the counter preset mode once again. According to the above-mentioned embodiment explained by Fig. 11 and Fig. 12, by switching the bit synchronization extraction system depending on frame synchronization, it is possible to shorten the bit synchronization extraction time and, at establishment of frame synchronization, due to the resistance to line noise and small timing extraction jitter, ensure a bit timing extraction jitter, a restriction when transmitting data, of within ±7 percent (0.36 µs). Fig. 13A is a circuit diagram of the oscillating unit 21 in the circuit shown in Fig. 11, and Fig. 13B shows waveform of the oscillating signal a1 of 6.144 MHz. As shown in Fig. 13A, the oscillating unit 21 is a well known crystal oscillator consisting of a crystal 131, a resistor 132, capacitors 133 and 134, and drivers 135 and 136. Fig. 14 is a circuit diagram of the phase comparison unit 24 in the circuit shown in Fig. 11, Fig. 15 is an explanatory view of the operation of the unit 24 in the case of an advance, and Fig. 16 is an explanatory view of the operation of the unit 24 in the case of a delay. As shown in Figs. 14 to 16, a change of the received signal a4 is lached in a D-type flipflop 141 in response to a rise of the clock signal a1 from the oscillating unit 21. The clock signal a1 has a frequency of 6.144 MHz or has a period ΔT of 0.16 µs. The lached output of the flipflop 141 is input to the D-input of a D-type flipflop 143 in response to a clock signal which is obtained by inverting the clock signal a1 by an inventer 142. The output of the flipflop 141 is inverted by an inverter 144. The output of the inverter 144 and the output of the flipflop 143 are applied to the inputs of a NOR gate 145. The output of the NOR gate 145 and the bit timing signal a3 are applied to the inputs of an AND gate 146. The output of the NOR gate 145 and the output of an inverter 147, the input thereof is connected to the bit timing signal a3, are applied to the inputs of an AND gate 148. By this construction, a pulse is generated after a change of the received data a4. If the bit timing signal a3 output from the counter unit 23 is at a high level when the pulse from the NOR gate 145 is generated, namely, if the bit timing signal is advanced before the change of the received data, the advance signal a5 is output from the AND gate 146, as shown in Fig. 15. On the contrary, if the bit timing signal a3 is at a low level when the pulse from the NOR gate 145 is generated, namely, if the bit timing signal a3 is delayed with respect to the change of the received signal, the delay signal a6 is output from the AND gate 148. Fig. 17 is a circuit diagram of the stage protection unit 25, Fig. 18 is an explanatory view of the operation of the unit 25 in the case of an advance, and Fig. 19 is an explanatory view of the operation of the unit 25 in the case of a delay. As shown in Fig. 17, the stage protection unit 25 includes two 1/8 counters 171 and 172, two inverters 173 and 174, and two AND gates 175 and 176. In the case where the bit timing signal a3 is in advance of the received signal a5, namely, when the advance signal a5 is generated, the 1/8 counter 171 counts the advance pulses a5 L times, for example, 8 times in a row, and then generates an advance protection signal b1. The advance pulse a5 at the generation of the advance protection signal b1 is gated through the AND gate 175. Thus, a decrease signal a7 is obtained at the output of the AND gate 175. In this case, the delay signal a6 is always at the low level which is inverted by the inverter 173 and is applied to the inverted reset terminal XRST of the counter 171. In the case where the bit timing signal a3 is delayed with respect to the received signal a4, namely when the delay pulse a6 is generated, the 1/8 counter 172 counts the delay pulses a6 L times, for example, 8 times in a row, and then generates a delay protection signal b2. The delay pulse a6 at the generation of the delay protection signal b2 is gated through the AND gate 176. Thus, an increase signal a8 is obtained at the output of the AND gate 176. In this case, the advance signal a5 is always at the low level which is inverted by the inverter 174 and is applied to the inverted reset terminal XRST of the counter 172. Fig. 20 is a circuit diagram of a pulse adjustment unit 22 in the circuit shown in Fig. 11, Fig. 21 is an explanatory view of the operation of the unit 22 in the case of an advance, and Fig. 23 is an explanatory view of the operation of the unit 22 in the case of a delay. The clock signal a1 from the oscillating unit 21 is applied to an input or an inverter 201, and the output of the inventer 201 is applied to a clock terminal CK of a flipflop 202 which has a D-input connected to an inverted output XQ and has a noninverted output Q. When the output Q of the flipflop 202 is at a high level, the clock signal a1 is passed through an AND gate 203, while when the inverted output XQ is at a high level, the clock signal a1 is passed through an AND gate 204. The decrease signal a7 from the stage protection unit 25 is applied to a clock terminal of a flipflop 213 which has a D-input pulled up to a power source. The Q output of the flipflop 213 is connected to a D-input of a flipflop 215 which has a clock terminal CK connected through an inverter 214 to the output of an OR gate 208. The inverted output XQ of the flipflop 215 is connected to the inverting reset terminal XRST. The Q output of the flipflop 215 reset terminal an input of an OR gate 216. The output of the OR gate 216 is connected to a clock terminal CK of a flipflop 217 which has a D-input connected to its inverted output XQ. The Q output of the flipflop 217 is connected to an input of an AND gate 205 and through an inverter 206 to an input of an AND gate 207. through an input of the to gate 205 is connected to the output of the AND gate 203. Also, another input of the AND gate 207 is connected to the output of the AND gate 204. The outputs of the AND gates 205 of 207 are connected to the inputs of the OR gate 208. The inverted output XQ of the flipflop 217 is connected to an input of an AND gate 209 and through an inverter 210 to an input of an AND gate 211. Another input of the AND gate 207 is connected to the output of the AND gate 203. Also, another input of the AND gate 211 is connected to the output of the AND gate 204. The outputs of the to gates 209 and 211 are connected to the inputs of the OR gate 212. The increase signal aβ from the stage protection unit 25 is applied to a clock terminal of a flipflop 218 which has a D-input pulled up to a power source. The Q output of the flipflop 218 is connected to a D-input of a output of the 220 which has a clock terminal CK connected through an invertor 219 to the output of the OR gate 212. The inverted output XQ of the flipflop 220 is connected to the inverting reset terminal XRST of the flipflop 218. The Q output of the flipflop 220 is connected to another input of the OR gate 216. When neither the decrease signal a7 nor the increase signal a8 is applied to the circuit 22, the clock signal a1 having a period ΔT is alternately passed through the AND gates 203 and 204. Therefore, every other pulse of the clock signal passes throng the AND gates 204 and 211 and the OR gate 212 so that the period T1 of the output signal a2 is ΔT × M (M=2). When the decrease signal a7 is applied to a clock terminal CK of the flipflop 213, namely, when the bit timing signal a3 is in advance of the received signal a4 by a time t as shown in Fig. 21, the clock signal a1 is modified at each time when the decrease signal a7 is supplied to a clock signal a2 which has a period longer than the period T1. Thus, the period of the clock signal a2 in this case is T1 + ΔT. This modification is carried out by the flipflops 213, 215 and 217. Accordingly, the bit timing signal a3 has a period T2 + ΔT. As a result, the difference between the change point of the received signal a3 and the rise time of the bit timing signal a3 is shortened to ΔT. When the increase signal a8 is applied to a clock terminal CK of the flipflop 218, namely, when the bit timing signal a3 is delayed with respect to the received signal a4 by a time t as shown in Fig. 22, the clock signal a2 is modified to have a shortened period T1 - ΔT so that the bit timing signal is modified, at each time when the increase signal a8 is applied, to have a shortened period T2 - ΔT, as shown in Fig. 22. This modification is carried out by the flipflops 218, 220, and 217. Figure 23 is a circuit diagram of the counter unit 23. As shown in the figure, the counter unit 23 comprises a 1/16 counter 230 having a clock terminal CK, a preset terminal PRST, and a noninverted output Q. Fig. 24 is an explanatory view of the operation of the counter unit 23 in Fig. 23. The counter 230 counts the period of 5.2 µs from the preset timing. After the 5.2 µs period, the bit timing signal a3 is raised. Fig. 25A is a circuit diagram of the change point detecting unit 26, and Fig. 25B is an explanatory view of the operation of the unit 26. As shown in the figures, after a rise of the received signal a4, a change point detection pulse a9 is generated in response to a rise of the clock signal a1. Fig. 26 is a circuit diagram of the frame synchronization detection unit 30, and Fig. 27 is an explanatory view of the operation of the circuit 30 in Fig. 26. As shown in the figures, the frame synchronization detection unit 30 comprises a D-type flipflop 261 having a D-input for receiving the received signal a4. The bit timing signal a3 is applied through an invertor 262 to a clock terminal CK of the flipflop 261. The received data latched by the flipflop 261 is output to a frame detection unit 263. If the received data is normal, a normal indicating signal b3 is output; while if the received data is an error, an error signal b4 is output. The normal signal b3 is applied as a clock signal to a clock terminal CK of a 1/3 counter. The normal signal b3 is also applied through an invertor 268 to an inverted reset terminal XRST of a 1/2 counter 267. The error signal b4 is applied as a clock signal to a clock terminal CK of the 1/2 counter 267, and is applied through an invertor 265 to an inverting reset terminal XRST of the 1/3 counter 264. When the 1/3 counter counts the normal signal b3 three times in a row, a pulse b5 is generated form the 1/3 counter 264. The pulse b5 is applied to a clock terminal CK of a flipflop 266 which has a D-input pulled up to a power supply. When the 1/2 counter counts the error signal b4 two times in a row, a pulse b6 is generated from the 1/2 counter 267. The pulse b6 is applied through an invertor 269 to an inverting reset terminal XRST of the flipflop 266. By this construction, a frame synchronization signal a10 is output when the normal signal b3 is received three times in a row. The frame synchronization signal a10 continues its high level until the error signal b4 is generated two times in a row. Figure 28 is a block diagram showing the construction of a system of a frame synchronization dependent type bit synchronization detection and extraction circuit according to another embodiment of the present invention. In Fig. 28, the difference from Fig. 11 is that while, in Fig. 11, use was made of a frame synchronization signal a10 to switch between the counter preset mode and DPLL mode, in Fig. 28, use is made of a pseudo frame synchronization detection unit 40. The other parts of the construction are the same as in Fig. 11 and the elements are shown by the same reference numerals. Figure 29 is a circuit diagram of a pseudo synchronization detection unit 40 in Fig. 28, and Fig. 30 is an explanatory view of the operation of the unit 40 in Fig. 29. In Fig. 29, the difference from Fig. 26 is that while, in Fig. 26, there is a 1/3 counter 264, in Fig. 30, the 1/3 counter 264 is not provided. The D-type flipflop 266 directly receives at its clock terminal CK the normal signal b3 from the frame detection unit 263. The other parts of the construction are the same as in Fig. 26 and the elements are shown with the same reference numerals. As can be seen from Fig. 29 and Fig. 30, the pseudo frame synchronization detection unit 40 detects pseudo frames with no more than two as the number P of consecutive frames for establishment of frame synchronization and at least two as the number Q of consecutive error frames for loss of frame synchronization. That is, if one or two normal frames are detected in the received data, pseudo frame synchronization is detected. When two or more error frames are detected during establishment of a pseudo frame, the pseudo frame synchronization is off. In this embodiment, P = 1 and Q = 2. Therefore, the frame synchronization signal a10 in the embodiment of Fig. 11 becomes a high level when three normal frames are received, but the pseudo frame synchronization signal all in the embodiment is immediately generated when one normal frame is received. Even if one normal frame is received, frame synchronization is not deemed established until three in a row have been received, so no disassembly of frames, assembly of frames, or transmission of data can be performed, but when the pseudo frame synchronization signal all becomes high level, there is a shift from the counter preset mode to the DPLL mode. Then if two error frames in a row are received, the counter preset mode is returned to from the DPLL mode. Since there is a quick shift to the DPLL mode, compared with the first embodiment, the time of the DPLL mode is long and therefore stable transmission of data is made. As clear from the above explanation, according to the present invention, by switching between the counter present mode and the DPLL mode depending on frame synchronization, it is possible to shorten the bit synchronization extraction time and, at establishment of frame synchronization, due to the resistance to line noise and small timing extraction jitter, ensure a bit timing extraction jitter, restriction when transmitting data, of within ±7 percent (0.36 µs). The present invention is not restricted to the above described embodiments, but various modifications are possible. For example, the present invention may be applied not only to the bit synchronization extraction circuit in an ISDN terminal, but also to other synchronization establishing circuits. Further, even when the frame synchronization detection unit 30 is not provided, the combination itself of the counter preset mode unit and the DPLL mode unit without the frame synchronization detection unit is also effective for quick synchronization establishment. This is because, since the counter 23 is forced to be preset in response to a change in received data, and the output of the counter unit 23 is synchronized with the received data quickly when there is no line noise. Therefore, the synchronization by the DPLL mode is usually realized within a short time. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A frame synchronization dependent type bit synchronization extraction circuit in an ISDN terminal equipment (TE) connected to a reference point S/T of an ISDN basic user network interface, for establishing bit synchronization between an internally produced signal and received data, comprising: counter preset mode synchronization means (21, 23, 26) for generating a first bit timing signal synchronized with received data by detecting a change point of said received data; digital phase locked loop mode synchronization means (21, 22, 23, 24, 25) for generating a second bit timing signal synchronized with said received data by the use of digital phase locked loop between said second bit timing signal and said received data; frame synchronization detection means (30) for detecting a frame synchronization of said received data; and inhibiting means (27, 28), operatively connected to said counter preset mode synchronization means and said frame synchronization detection means, for inhibiting the operation of said counter preset mode synchronization means after said frame synchronization is detected by said frame synchronization detection means. A frame synchronization dependent type bit synchronization extraction circuit as claimed in claim 1, wherein said digital phase locked loop mode synchronization means comprises a PLL circuit having a PLL feedback route, and after said frame synchronization is detected, the signal on the PLL feedback route is synchronized with said received data by phase comparison. A frame synchronization dependent type bit synchronization extraction circuit as claimed in claim 1, wherein said counter preset mode synchronization means comprises: oscillation mean (21) for generating a free-running signal; counter means (23), operatively connected to said oscillation means, for dividing said free-running signal to produce said internally produced signal; and change point detection means (26), operatively receiving said received data and operatively connected to said counter means (23), for detecting a point of change of said received data to generate a change-point signal (a9); said inhibiting means (27, 28) passes said change point signal (a9) to be supplied to said counter means (23) to preset said counter means (23) before said frame synchronization is detected. A frame synchronization dependent type bit synchronization extraction circuit as claimed in claim 1, wherein said digital phase locked loop mode synchronization means comprises: oscillation means (21) for generating a free-running signal; counter means (23), operatively connected to said oscillation means, for dividing said free-running signal to produce said internally produced signal; and phase comparison means (24), operatively receiving said received data and operatively connected to said counter means (23), for comparing the phase of said internally produced signal and the phase of said received data; and pulse adjustment means (22), operatively connected between said oscillating means (21) and said counter means (23) and operatively connected to said phase comparison mean (24), for adjusting the number of pulses of said free-running signal in accordance with the phase difference obtained at the output of said phase comparison means (24). A frame synchronization dependent type bit synchronization extraction circuit as claimed in claim 1, wherein said counter preset mode synchronization means and said digital phase locked loop mode synchronization means comprises: oscillation means (21) for generating a free-running signal; counter means (23), operatively connected to said oscillation means, for dividing said free-running signal to produce said internally produced signal; and change point detection means (26), operatively receiving said received data and operatively connected to said counter mean (23), for detecting a point of change of said received data to generate a change-point signal (a9); phase comparison means (24), operatively receiving said received data and operatively connected to said counter mean (23), for comparing the phase of said internally produced signal and the phase of said received data; and pulse adjustment means (22, 25), operatively connected between said oscillating means (21) and said counter means (23) and operatively connected to said phase comparison means (24), for adjusting the number of pulses of said free-running signal in accordance with the phase difference obtained at the output of said phase comparison means (24); said inhibiting means (27, 28) passes said change point signal (a9) to be supplied to said counter means (23) to reset said counter means (23) before said frame synchronization is detected. A frame synchronization dependent type bit synchronization extraction circuit as claimed in claim 5, wherein said inhibiting means (27, 28) comprises: an inverter (27) having an input connected to the output of said frame synchronization detection means (30); and an AND gate (28) having a first input connected to the output of said change point detection means (26) and having a second input connected to the output of said inverter (27), the output of said AND gate (28) being connected to a preset terminal (PRST) of said counter means (23). A frame synchronization dependent type bit synchronization extraction circuit as claimed in claim 6, wherein said frame synchronization detection means (30) comprises normal frame counting means (261, 263, 264) for counting a predetermined number of normal frames in a row to generate a frame synchronization signal, and error frame counting means (261, 263, 267) for counting errors a predetermined number of frames in a row to generate an loss of frame synchronization signal, said frame synchronization signal or said loss of frame synchronization signal being supplied to said input of said invertor (27). A frame synchronization dependent type bit synchronization extraction circuit as claimed in claim 7, wherein, to generate said frame synchronization signal, said normal frame counting means (261, 263, 264) has means to count normal frames three times in a row. A frame synchronization dependent type bit synchronization extraction circuit as claimed in claim 7, wherein, to generate said pseudo frame synchronization signal, said normal frame counting means (261, 263, 264) has means to count normal frames no more than two times in a row. A frame synchronization dependent type bit synchronization extraction circuit as claimed in claim 5, wherein, said phase comparison means (24) comprises advance signal generating means for generating an advance signal (a5) when said internally produced signal (a3) is in advance of said received data (a4), and delay signal generating means for generating a delay signal (a6) when said internally produced signal (a3) is delayed by said received data (a4). A frame synchronization dependent type bit synchronization extraction circuit as claimed in claim 10, wherein said pulse adjustment means (22, 25) comprises: a pulse adjustment unit (22), operatively connected between said oscillation means (21) and said counter means (23), and a stage number protection unit (25), operatively connected between said phase comparison means (24) and said pulse adjustment unit (22), for generating a decrease signal (a7) when said advance signal (a5) is generated a predetermined number of times in a row, and for generating an increase signal (a8) when said delay signal (a6) is generated a predetermined number of times in a row. A frame synchronization dependent type bit synchronization extraction circuit as claimed in claim 5, wherein said counter means (23) comprises an 1/N dividing counter (230) for counting N bits, where N is a positive integer, after said change point signal (a9) is applied from said change point detection means (26) through said inhibiting means to said counter means (23). A frame synchronization dependent type bit synchronization extraction circuit in an ISDN terminal equipment (TE) connected to a reference point S/T of an ISDN basic user network interface, for establishing bit synchronization between an internally produced signal and received data, comprising: oscillation means (21) for generating free-running signal; counter means (23) for dividing said free-running signal to produced said internally produced signal of a desired frequency; phase comparison means (24) for comparing the phases of said internally produced signal output from said counter means (23) and said received data; pulse adjustment means (22) for adjusting the number of pulses of said free-running signal in accordance with the phase difference obtained at the output of said phase comparison means (24); change point detection means (26) for detecting a point of change of said received data; frame synchronization detection means (30) for detecting the frame synchronization from the received data; and switching means (27, 28) for forcing said counter means (6) to be preset at the point of change of said received data by said change point detection means (5) to establish the bit synchronization before said frame synchronization detection means (6) detects frame synchronization and, for forcing the number of pulses of said free-running signal to be change in accordance with the phase difference obtained at the output of said phase comparison means (3) after said frame synchronization detection means (6) detects frame synchronization. A frame synchronization dependent type bit synchronization extraction circuit as claimed in claim 13, wherein said switching means (27, 28) comprises: an inverter (27) having an input connected to the output of said frame synchronization detection means (30); and an AND gate (28) having a first input connected to the output of said change point detection means (26) and having a second input connected to the output of said invertor (27), the output of said AND gate (28) being connected to a preset terminal (PRST) of said counter means (23). A frame synchronization dependent type bit synchronization extraction circuit as claimed in claim 14, wherein said frame synchronization detection means (30) comprises normal frame counting means (261, 263, 264) for counting a predetermined number of normal frames in a row to generate a frame synchronization signal, and error frame counting means (261, 263, 267) for counting errors in a predetermined number of frames in a row to generate loss of frame synchronization signal, said frame synchronization signal or said out of frame synchronization signal being supplied to said input of said inverter (27). A frame synchronization dependent type bit synchronization extraction circuit as claimed in claim 15, wherein, to generate said frame synchronization signal, said normal frame counting means (261, 263, 264) has means to count normal frames three times in a row. A frame synchronization dependent type bit synchronization extraction circuit as claimed in claim 15, wherein, to generate said pseudo frame synchronization signal, said normal frame counting means (261, 263, 264) has means to count normal frames no more than two times in a row. A frame synchronization dependent type bit synchronization extraction circuit as claimed in claim 13, wherein, said phase comparison means (24) comprises advance signal generating means for generating an advance signal (a5) when said internally produced signal (a3) is in advance of said received data (a4), and delay signal generating means for generating a delay signal (a6) when said internally produced signal (a3) is delayed by said received data (a4). A frame synchronization dependent type bit synchronization extraction circuit as claimed in claim 18, wherein, said pulse adjustment means (22, 25) comprises: pulse adjustment unit (22), operatively connected between said oscillation means (21), and said counter means (23), and stage number protection unit (25), operatively connected between said phase comparison means (24) and said pulse adjustment unit (22), for generating a decrease signal (a7) when said advance signal is generated a predetermined number of times in a row, and for generating an increase signal (a8) when said delay signal is generated a predetermined number of times in a row. A frame synchronization dependent type bit synchronization extraction circuit as claimed in claim 13, wherein said counter means (23) comprises a 1/N dividing counter (230) for counting N bits, where N is a positive integer, after said change point signal (a9) is applied from said change point detection means (26) through said inhibiting means to said counter means (23). A frame synchronization dependent type bit synchronization extraction circuit as claimed in claim 13, wherein said frame synchronization detection means (30) has three as the number of consecutive normal frames for establishment of frame synchronization for said received data. A frame synchronization dependent type bit synchronization extraction circuit as claimed in claim 13, wherein said pseudo frame synchronization detection means (40) has no more than two as the number of consecutive normal frames for establishment of frame synchronization for said received data. A frame synchronization dependent type bit synchronization extraction circuit as claimed in claim 13, wherein said frame synchronization detection means (30) has two as the number of consecutive error frames for loss of frame synchronization for said received data. A frame synchronization dependent type bit synchronization extraction circuit as claimed in claim 13, wherein said pseudo frame synchronization detection means (40) has at least two as the number consecutive error frames for loss of frame synchronization for said received data.

Inventors: NAKAYAMA MIKIO, NAKAYAMA, MIKIO
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1991
Main classification: H04L7
IPC codes: H04L7, H03L7