Pattern shift measuring method

Abstract: A method of measuring pattern shift on a diffused semiconductor wafer after an epitaxial process comprising: measuring a ratio between the line width of a linear pattern vertical to an orientation flat and line width of a linear pattern parallel to the orientation flat to determine the shift between these patterns.

Description: The invention relates to a method of estimating a shift between a diffusion pattern on a semiconductor wafer and a pattern on an epitaxial layer thereof after an epitaxial process, and more particularly to a method of estimating the pattern shift without destroying the semiconductor wafer and in a short period of time. It is essential to control the shift of a buried diffusion pattern after growth of an epitaxial layer in a bipolar transistor in an IC. For this purpose, the growth conditions (such as reaction temperature and reaction speed) should be always controlled to assure constant pattern shift. However, it is very difficult to strictly control the growth conditions since frequent measurement of the pattern shift is inevitable. Conventionally, the angular lapping stain method is used for this purpose. This method comprises: (1) slicing chips having a buried layer in parallel to and perpendicular to the orientation flat by using a dicing saw; (2) angular polishing of optional surfaces of the sliced tips ( ϑ=11° 32'); (3) etching the polished surfaces (Sirtl, 2 to 3 seconds); and (4) measuring the shift of the patterns of the buried layers by using differential, interference micrographs (x 150). The pattern shift factor is obtained by the following equation: the pattern shift factor = the amount of shift (micrometer)/the thickness of the epitaxial layer (micrometer). However, since it takes approximately 2 hours to measure the pattern shift and requires destruction of specimens, this conventional method cannot be used so frequently and is rather expensive. To solve the problem of the conventional method, some proposals were made to perform the pattern shift measurement through non destructive tests as disclosed in such publications as Japanese Patent Laid Open Publications 64-31 413 and 64-31 414. In the method described in the first mentioned document, a substrate disposed in a vacuum epitaxial device is charged with a dummy substrate on it and when epitaxial growth is performed, a part with an epitaxial layer as well as a part without the epitaxial layer are formed on the substrate. A positive type resist is coated on the semiconductor substrate where epitaxial growth is performed on the other side surface and mask alignment is carried out with a mask which is used in the case of formation of buried layer at the part where epitaxial growth is not performed and the above part is exposed and also it is developed. Patterns of the resist remain on the buried layer and they are formed at a position which has been held prior to epitaxial growth even in the part where epitaxial growth has been performed. Thus the relation of positions between the pattern of the buried layer located at the part where epitaxial growth has been performed and the pattern of the resist are measured. In a method known from second document 64-31 414 fine patterns are put in a semiconductor substrate and epitaxial growth is performed. Observing forms including the directions of the patterns where growth has been performed, the presence of any abnormality of the shift of the patterns is judged from the presence of abnormality regarding their formation. Thus, inspection of the shift of the patterns during epitaxial growth which is performed towards the semiconductor substrate can be carried out only by observing the surfaces without destroying the semiconductor substrate. Under the present circumstances, there is a great demand for a more simplified and reliable method of measuring the pattern shift. It is therefore an object of this invention to provide a method of reliably measuring the pattern shift of a semiconductor wafer in a short period of time without destroying the semiconductor wafer. This object is achieved by the features as set forth in the independent claim 1. According to this invention, the pattern shift can be determined only by measuring the line width of a linear pattern vertical to the orientation flat and/or by measuring the line width of a linear pattern parallel to the orientation flat. According to this invention, the pattern shift can be reliably and inexpensively measured in about five minutes without destroying the semiconductor wafers. Many other objects, advantages and features of the present invention will be better understood from the following description taken in conjunction with the accompanying drawings. FIG. 1 shows a correlation between a ratio W V /W H obtained by the method of this invention and a pattern shift ratio obtained by the conventional method; FIG. 2 shows a correlation between W V of this invention and the pattern shift ratio determined by the conventional method; and FIG. 3 shows a correlation between W H of this invention and the pattern shift ratio determined by the conventional method. One embodiment of this invention will now be described with reference to the accompanying drawings. Measurement was performed under the following conditions: Specimens; CZ p-type semiconductor wafer 〈111〉 off-angle 3° 30' in 〈112〉 100, 10-20Ω-cm, OF〈110〉 Buried diffusion layer; Sb, 15Ω/□, depth 8mm Width of the buried diffusion layer; 60 µm Epitaxial layer growth; 10 µm, 1Ω-cm Reaction furnaces used; Cylindrical and vertical furnaces Reaction temperatures; 1150, 1100 and 1050°C Reaction speeds; 0.30 and 0.60 µm /min Reaction pressure; 760 Torr Measurement; A Nomarski differential microscopic interferometer (magnification factor, x200) was used to measure the line width (W V ) of a pattern vertical to the OF(orientation flat), and the line width (W H ) of a pattern parallel to the OF. The measured values and the ratio W V /W H are shown in Table 1. Furnace type Reaction temperature (°C) Reaclion speed µm/min pattern shift ratio W V (µm) W H (µm) W V /W H Vertical furnace 1150 0.30 0.594 61.9 63.2 0.98 do. 0.54 0.900 61.9 63.9 0.97 1100 0.30 0.986 61.3 65.2 0.94 do. 0.53 1.11 60.6 66.5 0.91 1050 0.30 1.32 58.7 69.1 0.85 do. 0.53 1.32 56.7 68.5 0.83 Cylindrical furnace 1150 0.25 0.98 61.9 63.9 0.97 do. 0.56 1.23 60.6 65.9 0.92 1100 0.28 1.35 60.6 67.8 0.89 do. 0.57 1.48 58.7 69.8 0.84 1050 0.30 2.11 54.8 70.4 0.78 do. 0.58 2.01 56.7 70.4 0.81 W V /W H = Line width (W V ) vertical to OF〈110〉/Line width (W H ) parallel to OF〈110〉 FIGS. 1 to 3 are graphs showing the correlation between the pattern shift ratios determined by the conventional method (angular lapping stain method), and the values W V /W H , W V and W H determined by the method of this invention. Any of W V /W H , W V and W H have correlations to the pattern shift ratio of the conventional method (W V /W H and W V have negative correlations and W H has a positive correlation to the conventional pattern shift ratio). It was confirmed that the pattern shift can be determined by measuring W V /W H , and W V or W H . In this embodiment, the buried diffusion layer is antimony (Sb). The method of this invention is also applicable to buried diffusion layers of impurities such as boron (B), phosphorous (P) and arsenic (As). According to this invention, it is possible to measure the pattern shift of the epitaxial semiconductor wafer in a short period of time without destroying the wafer. Therefore, measurement can be performed very frequently so that the growth conditions can be always kept optimum.

Claims: A method of estimating a shift between a diffusion pattern on a semiconductor wafer and a pattern on an epitaxial layer thereof after an epitaxial process, said method comprising the steps of: measuring a line width of a linear pattern on the epitaxial layer vertical to an orientation flat; and/or measuring a line width of a linear pattern on the epitaxial layer parallel to the orientation flat; and estimating the shift based on the line width of the linear pattern or the line widths of the linear patterns. A method of estimating a shift between a diffusion pattern on a semiconductor wafer and a pattern on an epitaxial layer thereof after an epitaxial process according to claim 1, wherein said method comprises the steps of: predetermining the correlation between the pattern shift ratio and a line width of a linear pattern on the epitaxial layer vertical to an orientation flat; measuring a line width of a linear pattern on the epitaxial layer vertical to the orientation; and estimating the shift based on the predetermined correlation and the measured line width. A method of estimating a shift between a diffusion pattern on a semiconductor wafer and a pattern on an epitaxial layer thereof after an epitaxial process according to claim 1, wherein said method comprises the steps of: predetermining the correlation between the pattern shift ratio and a line width of a linear pattern on the epitaxial layer parallel to an orientation flat; measuring a line width of a linear pattern on the epitaxial layer parallel to an orientation flat; and estimating the shift based on the predetermined correlation and the measured line width. A method of estimating a shift between a diffusion pattern on a semiconductor wafer and a pattern on an epitaxial layer thereof after an epitaxial process according to claim 1, wherein said method comprises the steps of: predetermining the correlation between the pattern shift ratio and a ratio between the line width of a linear pattern on the epitaxial layer vertical to an orientation flat and the line width of a linear pattern on the epitaxial layer parallel to the orientation flat; measuring a line width of a linear pattern on the epitaxial layer vertical to the orientation flat; measuring a line width of a linear pattern on the epitaxial layer parallel to an orientation flat; calculating the ratio between the measured line widths; and estimating the shift based on the predetermined correlation and the ratio between the measured line widths. A method of estimating a shift between a diffusion pattern on a semiconductor wafer and a pattern on an epitaxial layer thereof after an epitaxial process according to claim 1, wherein a microscopic interferometer is used to measure a line width of a linear pattern on the epitaxial layer.

Inventors: MIKI KATSUHIKO SHIN-ETSU HANDO, MIKI, KATSUHIKO, SHIN-ETSU HANDOTAI, C. H. NO. 207
Applicants: SHINETSU HANDOTAI KK, SHIN-ETSU HANDOTAI COMPANY LIMITED
Application year: 1991
Main classification: G01B9
IPC codes: G03F9, G01N21, G01B21, G06T7, G06T1, G01B11, H01L21