Semiconductor integrated circuit

Abstract: Disclosed is a semiconductor integrated circuit of a bipolar CMOS gate array type having a plurality of basic cells (8, 9, 10, and11)arranged in a matrix, each of which comprising MOS transistors (P1 to P4 and N1 to N4) as memory cells, a bipolar transistor (NPN1), and a resistance (R1) and bit lines for transferring data stored in the memory cells to the outside, and the semiconductor integrated circuit is characterized by that the basic cells (8, 9, 10, and 11) are grouped into a plurality of blocks (BLOCK A and BLOCK B), the bipolar NPN transistor (NPN1 or NPN4) in each block is used as a driver for reading operations of the data stored in the memory cells (P1 to P8 or N1 to N8) in each block (BLOCK A or BLOCK B), and the output line (OUTPUT LINE B or OUTPUT LINE D) is kept at a logic state "0" before reading operations for the memory cells (P1 to P8 or N1 to N8).

Description: BACKGROUND OF THE INVENTION 1.Field of the Invention This invention relates to a semiconductor integrated circuit, and more particularly to a construction of a semiconductor integrated circuit comprising a plurality of bipolar CMOS (Bi-CMOS) gate arrays. 2.Description of the Prior Art All memory cores in a conventional ROM formed by using bipolar CMOS gate arrays are made up of MOS transistors. Fig. 1 is part of circuit diagram of a ROM which is made up of the conventional Bi-CMOS gate array. In the same diagram, each of a plurality of memory cells 4 is connected to a word line 5 and an output line 1 (a bit line 1). The source terminal 4S of the memory cell 4 is connected to a power source V DD (not shown) or a ground for programming. The drain terminal 4D of the memory cell 4 is connected to the output line 1. When the memory cell 4 is addressed by a Bi-CMOS decoder 3 through a word line 5, data stored therein are read out on the output line 1. The memory cells 4 corresponding one word for word processing are connected to the output line 1. In the conventional ROM having the construction described above, a Bi-CMOS are used as the decoder 3 or the sense amplifier 2 for high speed operation. Moreover, because all of the drains of memory cells corresponding to the word for word processing are connected to the output line 1, the loads of the output line 1 becomes so heavy that there is a problem in the prior art that it takes much times to execute a reading operation for the memory cells 4. Namely, the operation speed in reading become lower. Fig. 2 shows reading forms for access time for the reading operation of the conventional ROM comprising the Bi-CMOS gate arrays. The number of the memory cells connected to the output line 1 is the same number of the memory cells corresponding to one word for word processing, as shown in Fig. 1. In the same diagram, when an output level L o of the output line 1 exceeds a threshold level Ls of the sense amplifier 2, a reading operation of the data stored in the ROM is started (TO). A total of the access time of the reading operation for the ROM is given as following: T CMOS = T B - T S where the end time of the reading operation is T E and the time that an address signal is given to the Bi-CMOS decoder 3 is Ts. In the ROM having the construction described above. As the memory cells belonging to the word line are connected to the output line 1 as the loads, there is the problem that the rise-time (Ts - T o ) of the reading operation of the memory cell 4 requires much time. Fig. 3 shows a construction of a basic cell as an unit cell of the Bi-CMOS gate array. In the same diagram, reference characters N1 to N4 designate N-type MOS transistors, P1 to P4 are P-type MOS transistors, NPN is a bipolar transistor, and R is a resistance. The Bi-CMOS gate array widely used is made up of a plurality of the basic cells arranged on a Large-scale integrated (LSI) device, which are connected to one another by wirings. However, the bipolar transistor in the basic cell is not used in the conventional ROM so that the utilizable efficiency of the basic cell has been lower. To summarize the problem of the conventional ROM implementing the Bi-CMOS gate arrays, a plurality of memory cells are connected to one output line so that the access time of the memory cell in the ROM is slowed and the degree of integration of the ROM becomes low because the Bi-transistor NPN in the basic cell has not been used. EP-A-0 258 715 shows a Bi-CMOS static RAM with a plurality of cell blocks and a bipolar transistor for discharging an associated main bit line quickly, to give a faster READ operation. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a ROM with Bi-CMOS gate arrays capable of having a shorter access time and high integration degree. According to the present invention, there is provided a semiconductor integrated circuit of a gate array type as set out in claim 1. Another aspect of the invention is set out in claim 3. Preferred features are set out in the dependent claims. In the semiconductor integrated circuit according to the present invention, the memory cells of the predetermined numbers are grouped into one block. The Bi-transistor provided in the basic cell as the memory cell in the block is used as a driver for driving the memory cells in the block. The number of memory cells driven by one driver is optimized so that a high speed operation for reading the data stored in the memory cells can be carried out. Moreover the bipolar transistor in the Bi-CMOS gate array, which is not used in the conventional ROM, is utilized as the driver so that the high degree of integration for a ROM can be achieved. The object, features and advantages of the present invention will be more apparent from the following description of a preferred embodiment, taken in conjunction with the accompanying drawing. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows part of construction of a semiconductor integrated circuit (ROM) conventionally used; Fig. 2 show wave forms of reading operations in the semiconductor integrated circuit (ROM), as shown in Fig. 1; Fig. 3 shows a construction of a basic cell provided in a semiconductor integrated circuit (ROM); Fig. 4 shows a construction of a semiconductor integrated circuit (ROM) of an embodiment according to the present invention, in which the basic cells, as shown in Fig. 3, are used ; Fig. 5 is wave forms for reading operations of the semiconductor integrated circuit (ROM) as shown in Fig. 4; Fig. 6 shows a construction of a semiconductor integrated circuit (ROM) of another embodiment according to the present invention, in which the basic cells, as shown in Fig. 3, are used; and Fig. 7 is timing charts for reading operations, in which the upper timing chart is for a ROM of the first embodiment, and the lower timing chart is for a ROM of a second embodiment, according to the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS Hereinafter, embodiments of the present invention will be explained with reference to the attached drawings. In a first embodiment, the construction of a ROM implemented in a Bi-CMOS gate array is explained, similar to the conventional ROM described in the description of the prior art. Fig. 4 shows a construction of the semiconductor integrated circuit or a ROM. In the same diagram, reference numbers 8, 9, 10, and 11 designate the basic cells, as shown in Fig. 3. Reference numbers 6 and 7 denote sense amplifiers connected to a bipolar transistor NPN1 through an output line B (or a bit line) and data stored in memory cells P1 to P8 and N1 to N8 are read out to outside thereof through the sense amplifiers 6 and 7. The memory cells P1 to P8 and N1 to N8 comprise PMOS transistors and NMOS transistors, respectively, and the drains of the PMOS transistors P1 to P8 are connected to the output line A. The output line A is also connected to the base of the bipolar transistor NPN1. The emitter of the bipolar transistor NPN1 is connected to the output line B and the resister R1 in the basic cell 8. Similarly, the drains of the NMOS transistors N1 to N8 in the basic cells 8 and 9 as the memory cell are connected to an output line C which is connected to the base of a bipolar transistor NPN4 in a basic cell 11. In addition, the output line C is also connected to the base of the bipolar transistor NPN 4 through a resister R5. Each source of the PMOS transistors P1 to P8 is connected to the earth or a power source V DD for programming. In the ROM of the first embodiment having the construction described above, a plurality of the basic cells are arranged in a matrix so as to obtain a Bi-CMOS gate array. Moreover, eight MOS transistors, for example the PMOS transistors P1 to P8 in the two basic cells 8 and 9, are grouped into one block A, because it is preferable to separate the PMOS transistors P1 to P8 and NMOS transistors N1 to N8 for optimizing the operations of the sense amplifiers 6 and 7. The PMOS transistors P1 to P4 in the basic cell 8 and the PMOS transistors P1 to P8 in the basic cell 9 are grouped into the block A. Similarly, the NMOS transistors N1 to N4 in the basic cell 8 and the NMOS transistors N5 to N6 in the basic cell 9 are grouped into a block B in the embodiment. Although the operating speed of the bipolar transistor NPN1 as a driver used for reading operations of the memory cells P1 to P8 in the block A is very high, the bipolar transistor NPN1 controls only the eight PMOS transistors P1 to P8 belonging to the block A so that a high speed operation of the semiconductor integrated circuit can be achieved. Fig. 5 shows wave forms of the reading operation of the semiconductor circuit according to the present embodiment. When compared to the access time (T CMOS ) of the conventional semiconductor integrated circuit, as shown in Fig. 2, the access time T BICMOS for the reading operation of the ROM according to the first embodiment is shorter than the access time T CMOS of the ROM as shown in Fig. 2 (T CMOS > T BICMOS ). In the present embodiment, the bipolar transistor NPN1 is used as the driver so as to handle the memory cells P1 to P8 in the block A. The output line B or the bit line is usually grounded (pulled down) through the resistance R3. In the ROM of the present embodiment described above, for example, when the PMOS transistor P1 whose data is "1" (high level) is selected by the word line 20, the level of the base of the driver NPN1 becomes a logic state "1". Consequently the level of the output line B becomes also "1". Thus, the data stored in the PMOS transistor P1 is transferred to the sense amplifier 6 through the driver NPN1. Next, the level of the output line B is pulled down to a logic state "0" (low level) by a pull-down resistance as a precharge operation for next reading operation. Conversely, when the PMOS transistor P1 whose data is "0" is selected, the driver NPN1 is not operated or in OFF state so that the level of the output line B is kept in the low state "0". Then, the output line B is also pulled down to the low level "0" by the pull down resistance R3 before next reading operation is started. In the embodiment, the precharge operation for setting the output line B at the low level "0" for the next reading operation is required between two reading operations. In such a case, the reading operation should be carried out in synchronization with the precharge operation. Fig. 7 shows two timing charts of reading operations, in which the upper timing chart (SYNCHRONOUS) is for the Bi-CMOS ROM of the first embodiment and the lower timing chart (ASYNCHRONOUS) is for a Bi-CMOS ROM according to a second embodiment, as described below in detail. Next, we will now be explained the second embodiment according to the present invention. Fig. 6 shows a construction of a semiconductor integrated circuit of the second embodiment, in which the plural basic cells 80, 90, 100, and 110 are used. In the same diagram, NPN10, PNP20, NPN30, and PNP40 are drivers for reading operations of memory cells P1 to P8 and of memory cells N1 to N8. Namely, the memory cells P1 to P8 are grouped into the block C, whose data are read out by the combination of the drivers NPN10 and PNP20 to the sense amplifier 6 through an output line 12. In addition, The memory cells N1 to N8 are grouped into the block D whose data are read out by the combination of the drivers NPN30 and PNP40 to the sense amplifier 7 through an output line 18. When data stored in the PMOS transistor P1 is in a logic state "1", the driver NPN10 is switched on so that the level of the output line 12 becomes "1". At the same time, the driver PNP20 is switched off. While, when the data stored in the PMOS transistor P1 is "0", the driver PNP20 is switched on so that the level of the output line 12 becomes "0". Simultaneously, the driver NPN10 is switched off. The drivers such as the bipolar transistor NPN 30 or PNP 40 in the block D shown in Fig. 6 can be similarly operated for the data stored in the memory cells N1 to N8. In the second embodiment described above, the two bipolar transistors NPN10 and PNP20 in the block C are used instead of the bipolar transistor NPN1 in the block A in the first embodiment as the drivers for the reading operations of the memory cells P1 to P8. The output level of the block C has two logical levels, "1" (high) and "0" (low), provided by the drivers NPN10 and PNP 20. Accordingly, as shown by the lower timing chart in Fig. 7, the semiconductor integrated circuit (ROM) of the second embodiment requires no precharge operation so that the higher reading cycle time can be achieved. Moreover, the resistances R3 and R6 used in the ROM of the first embodiment (shown in Fig. 4) is not necessary because the precharge operation for the output line 12 is not required. The scope of this invention is not limited to the embodiments described above, but includes many variations that will be obvious to one skilled in the art. For example, the number of the memory cells per block may be another number other than eight. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A semiconductor integrated circuit of the gate array type, comprising: a plurality of basic cells (8, 9, 10 and 11) arranged in a matrix, each of the basic cells comprising a plurality of MOS transistors (P1 - P4 and N1 - N4, P5 - P8 and N5 - N8) as memory cells, a bipolar transistor (NPN1, NPN4), and a resistor (R1, R2, R4, R5), said bipolar transistor having a base, emitter and collector; a plurality of bit lines (B, D) each for reading out data from the memory cells in a row; and a plurality of word lines (20) for selecting the memory cells in a column, characterised in that parts of a predetermined number of the basic cells are grouped into one memory block (A, B), each memory block containing a plurality of MOS transistors (P1 - P8, N1 - N8) of the same conductivity type, and not containing any MOS transistors of any other conductivity type, the bipolar transistor (NPN1 - NPN4) and the resistor (R1, R2, R4, R5) in one of the basic cells in each memory block being used for the same memory block as a driver for reading out data from the memory cells in the same memory block, the memory cells in the same memory block being connected to the base of the bipolar transistor and one side of the resistor which are used as said driver, and the emitter of the bipolar transistor used as said driver being connected to the other side of the resistor used as said driver and the bit line through which data from the memory cells are transferred to outside of the semiconductor integrated circuit. A semiconductor integrated circuit of a gate array type as claimed in claim 1, having means (R3, R6) for bringing the electrical level of the bit lines at a logic state "0" before the reading operation. A semiconductor integrated circuit of the gate array type, comprising: a plurality of basic cells (80, 90, 100, 110) arranged in matrix, each of the basic cells comprising: a plurality of MOS transistors (P1 - P4, N1 - N4, P5 - P8, N5 - N8) as memory cells; a bipolar transistor (NPN 10, PNP 20, NPN 30, PNP 40) of the NPN type or the PNP type; and a resistor (R1, R2, R4, R5); the semiconductor integrated circuit further comprising: a plurality of bit lines (12, 18) for reading out data from the memory cells in a row; and a plurality of word lines (22) for selecting the memory cells in a column; characterised in that a predetermined number of the basic cells are grouped into one memory block (C, D), the bipolar transistors of the NPN type and the PNP type and one of the resistors in adjacent basic cells in each memory block are used for the same memory block as a driver for reading out data from the memory cells in the same memory block, the memory cells in the memory block are connected to the base side of the bipolar transistors of NPN type and PNP type which are used as a driver and one side of said one of the resistors, and the emitter of the bipolar transistor of NPN type used as a driver is connected to the emitter of the bipolar transistor of PNP type used as a driver and the other side of said one of the resistors and the bit line (12, 18) through which data from the memory cells in the same memory block are transferred to outside of the semiconductor integrated circuit. A semiconductor integrated circuit according to claim 3, wherein a higher electrical level "1" is transferred to the bit line by the emitter of the bipolar transistor of the NPN type when the memory cell stores the higher electrical level "1" . A semiconductor integrated circuit of the gate array type, as claimed in claim 1, wherein each of the basic cells comprises a plurality of N-type MOS transistors (N1 - N4, N5 - N8) and a plurality of P-type transistors (P1 - P4, P5 - P8) as memory cells, and said semiconductor integrated circuit is formed of a plurality of memory blocks (A, B).

Inventors: HARA HIROYUKI, WATANABE YOSHINORI, HARA, HIROYUKI, WATANABE, YOSHINORI
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1991
Main classification: G11C7
IPC codes: H01L21, G11C7, G11C17, H01L27