Photoelectric converting device

Abstract: A photoelectric converting device comprises; a photoelectric converting section in which a plurality of photoelectric conversion elements, switching elements, matrix signal wirings, and gate drive wires are arranged on a same substrate and which generates parallel signals; a drive switching section for applying drive signals to the gate drive wirings; and a read switching section for converting the parallel signals which are transferred from the matrix signals wirings into a serial signal and reading out to an outside. The read switching section is constructed by transfer switches connected to the matrix signal wirings, read capacitors, and read switches for reading out the parallel signals as a serial signal from the read capacitors by being sequentially switched.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a photoelectric conversion device and, more particularly, to a photoelectric conversion device for use in an input section of an image processing apparatus, such as a facsimile apparatus, an image reader, a copier, an electronic blackboard, or the like. Related Background Art In recent years, a long line sensor having an equal or unity magnification optical system has been developed as a photoelectric converting device in order to realize a miniaturization and a high performance of the facsimile apparatus, image reader, and the like. Hitherto, such a kind of line sensor is constructed by connecting an integrated circuit (hereinafter, abbreviated to IC) for signal processing in which switching elements and the like are respectively constructed for photoelectric conversion elements arranged like an array of one line. However, as the number of photoelectric conversion elements, 1728 elements are needed in the case of the A4 size according to the G3 standard of the facsimile apparatus. Therefore, the number of installing steps also increases and a line sensor which sufficiently satisfies requirements regarding the manufacturing costs and the reliability is not obtained yet. On the other hand, hitherto, a construction by matrix wirings has been used as a construction to reduce the number of signal processing ICs and to reduce the number of installing steps. There has also been tried to cheaply provide an image reading apparatus of the long contact type in which thin film transistors (hereinafter, abbreviated to TFT) are used as switching elements and an integrated structure comprising photoelectric conversion elements, thin film transistors, matrix wirings, and the like is used, thereby reducing the function of a signal processing IC and realizing a high reading speed. Further, to provide an image reading apparatus of the long contact type of low manufacturing costs and a high reliability, there has also been developed a method whereby the photoconductive converting layer of the photoelectric conversion element and the semiconductor layer of the TFT are formed by the same material such as amorphous silicon and the photoelectric conversion elements, TFT, matrix wirings, and the like are integratedly formed on the same substrate by using the same manufacturing steps. Further, to realize miniaturization and low costs, there has also been proposed a photoelectric conversion device in which the photoelectric conversion element directly detects the reflected light from an original through a transparent spacer such as a glass or the like without using an equal magnification fiber lens array. Fig. 1 shows an equivalent circuit diagram of a conventional photoelectric converting device which has already been proposed by us. Light information which enters photoelectric conversion elements S 1-1 to S 36-48 is transmitted from the photoelectric conversion elements S 1-1 to S 36-48 through accumulation capacitors C s1-1 to C s36-48 , transfer TFTs T 1-1 to T 36-48 , resetting TFTs R 1-1 to R 36-48 , and matrix signal wirings L 1 to L 48 and become parallel voltage outputs. Further, the parallel voltage outputs are supplied to a read switch IC and become a serial signal. The serial signal is taken out to the outside. In an example of a construction of the above conventional photoelectric conversion device, the photoelectric conversion elements of 1728 bits corresponding to the total number of pixels are divided into 36 blocks every 48 bits. The operations of the 36 blocks are sequentially executed on a block unit basis. Fig. 2 shows a timing chart when an original of a uniform image concentration is read by the conventional photoelectric converting device. The light information which entered the photoelectric conversion elements S 1-1 to S 1-48 of the first block are converted into photo currents and are accumulated as charges into the accumulation capacitors C s1-1 to C s1-48 . After the elapse of a predetermined time, a first voltage pulse to transfer is applied to a gate drive line G 1 for a time t 1 , thereby switching the transfer TFTs T 1-1 to T 1-48 to the on state. The charges in the accumulation capacitors C s1-1 to C s1-48 are transmitted through the matrix signal wirings L 1 to L 48 and are transferred to load capacitors C L1 to C L48 , so that potentials V L1 to V L48 of the load capacitors rise (transfer operation). Subsequently, a voltage pulse is sequentially supplied from a shift register SR 2 to gate drive lines g 1 to g 48 and read switches T sw1 to T sw48 are sequentially switched to the on state, thereby converting the signals of the first block which were transferred to the load capacitors C L1 to C L48 into the serial signal. After completion of the impedance conversion, the serial signal is read out to the outside of the photoelectric converting apparatus. After that, a voltage pulse C res to reset is supplied to reset switches R sw1 to R sw48 for a time t 2 , thereby resetting the load capacitors C L1 to C L48 . Then, a voltage pulse is suppled to a gate drive line G 2 and the transfer operation of the second block is started. At the same time, the reset TFTs R 1-1 to R 1-48 are turned on, the charges in the accumulation capacitors C S1-1 to C S1-48 of the first block are reset, thereby preparing for the next read-out operation. In a manner similar to the above, by sequentially driving gate drive lines G 3 , G 4 , ..., the data of one line is generated. In the conventional photoelectric conversion device, the transfer operation, reading operation, and resetting operation are sequentially executed on a block unit basis as mentioned above. Therefore, the image signal from the photoelectric conversion device is intermittently generated as shown by V out in Fig. 2. JP-A-63-214084 discloses a photoelectric conversion device having a photoelectric conversion section with a plurality of photoelectric conversion elements, each photoelectric conversion element being associated with a respective switching element having a gate coupled to a gate drive conductor and matrix signal conductors for receiving signal from respective photoelectric conversion elements. A drive section is arranged to apply drive signals to the gate drive conductors for enabling signals from associated photoelectric conversion elements to be supplied in parallel to respective matrix signal conductors and stored by storage means. A read section has read capacitors, transfer switches for transferring charge from the storage means to the said capacitors, read switches for reading out charge stored by the read capacitors in sequence to provide a serial output signal. In operation of the photoelectric conversion device described in JP-A-63-214084, a transfer pulse is applied to the transfer switches, a pre-charge pulse is then applied to the matrix signal conductors and a drive signal subsequently applied to a gate drive conductor causing charge representing light incident on photoelectric conversion elements coupled to the gate drive conductor via the switching elements to be supplied by the matrix signal conductors and the transfer switches to respective read capacitors. After the end of the transfer pulse and the gate drive signal, the read switches are operated to read out charge from the read capacitors to provide a serial output signal. The supply of signals from the photoelectric conversion elements and the reading of charge from the read capacitors are thus carried out in sequence as in the photoelectric conversion device shown in Fig. 1 resulting in an intermittent generation of the image signal. To use the conventional photoelectric conversion device as an image input section of a system such as a facsimile apparatus or the like, there are cases where problems occur such that a processing circuit is needed to convert the intermittent signals which are generated by the photoelectric conversion device into a continuous signal and a correction circuit to execute a shading correction and the like becomes complicated. For instance, processes for temporarily storing the signal output of the photoelectric conversion device in a line memory before it is image processed and, thereafter, for converting the intermittent signals into the continuous signal are necessary. Or, it is necessary to non-continuously execute the image process. Consequently, in the conventional photoelectric conversion device, there are cases where problems occur such that the costs of the whole system rise and the like. According to one aspect of the present invention, there is provided a photoelectric conversion device comprising a photoelectric conversion section comprising a plurality of photoelectric conversion elements, each photoelectric conversion element being associated with a respective switching element having a gate coupled to a gate drive conductor and matrix signal conductors coupled to the switching elements for receiving signals from respective photoelectric conversion elements; a drive section for applying drive signals to the gate drive conductors for enabling signals from associated photoelectric conversion elements to be supplied in parallel to respective matrix signal conductors and stored by capacitive charge storage means coupled to the matrix signal conductors; and a read section comprising read capacitors, transfer switches for transferring charge from the charge storage means to the said read capacitors and read switches for reading out charge stored by the read capacitors in sequence to provide a serial output signal, characterised by control means for controlling operation of the read switches so that read out of charge from a read capacitor occurs after transfer of charge from the charge storage means by a transfer switch has been completed and overlaps with the supply of subsequent signals from the photoelectric conversion elements to the matrix signal conductors. In another aspect, the present invention provides a method of reading out signals from a photoelectric conversion device comprising a plurality of photoelectric conversion elements, each photoelectric conversion element being associated with a respective switching element having a gate coupled to a gate drive conductor and matrix signal conductors coupled to the switching elements for receiving signals from respective photoelectric conversion elements, which method comprises causing signals to be supplied in parallel from photoelectric conversion elements to matrix signal conductors for storage as parallel signals by capacitive charge storage means coupled to the matrix signal conductors by supplying gate drive signals to the gate drive conductors, transferring charge stored by the capacitive charge storage means to read capacitors, and reading charge stored by the read capacitors in sequence to provide a serial output signal, characterised by reading the charges stored by the read capacitors after completion of charge transfer from the capacitive charge storage means to the read capacitors and causing further signals to be supplied in parallel from the photoelectric conversion elements to the matrix signal conductors for storage as parallel signals by the capacitive charge storage means by supplying gate drive signals to the gate drive conductors while charge is being read out from a read capacitor. In a photoelectric conversion device or method embodying the invention, an intermittent output which causes a problem in the conventional photoelectric conversion devices which is matrix driven every block is avoided and the period of time when the signal between blocks is not generated is eliminated, so that a reading speed of the photoelectric converting apparatus can be made substantially high. In addition, there is no need to store a signal output of the photoelectric converting apparatus temporarily in a line memory before it is image processed or to convert the intermittent signals into a continuous signal on the side of a system such as a facsimile apparatus or the like or to non-continuously execute image processes. Further, using a photoelectric conversion device embodying the invention, since image processes on the side of a system such as a facsimile apparatus or the like can be executed by simple means, has the advantage of not causing an increase in costs of the whole system or a reduction in image quality. An embodiment of the invention provides a photoelectric conversion apparatus of low cost and a high image quality. An embodiment of the invention provides a photoelectric conversion device which can fully or substantially eliminate a period of time when a signal between blocks is not generated in a signal output of the photoelectric conversion device which is driven in a matrix manner and which can substantially raise reading speed. Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which: Fig. 1 is an equivalent circuit diagram of a conventional photoelectric conversion device; Fig. 2 is a timing chart for explaining the operation of the conventional photoelectric conversion device; Fig. 3 is an equivalent circuit diagram of a photoelectric conversion device according to the first embodiment of the invention; Fig. 4 is a timing chart for explaining the operation of the photoelectric conversion device of Fig. 3; Figs. 5A and 5B are schematic cross sectional view and plan view of a photoelectric conversion section according to the photoelectric conversion device of Fig. 3; Fig. 6 is an equivalent circuit diagram of a parallel/serial conversion section of the second embodiment of the invention; Fig. 7 is an equivalent circuit diagram of a parallel serial conversion section in the third embodiment of the invention; and Fig. 8 is a schematic constructional diagram of a facsimile apparatus to which a photoelectric conversion device of the invention is applied. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail hereinbelow with reference to the drawings. Fig. 3 shows an equivalent circuit diagram of a photoelectric conversion device as a preferred first embodiment according to the invention. In the embodiment, a construction of a photoelectric conversion section comprising a photoelectric conversion element section, an accumulation capacitor section, a TFT section, a matrix signal wiring section, a gate drive wiring section, and the like which are formed on the same substrate is fundamentally similar to the equivalent circuit diagram of the conventional photoelectric conversion device shown in Fig. 1. The photoelectric conversion device of the embodiment differs from the photoelectric conversion device shown in Figure 1 when it is seen as an equivalent circuit with respect to a read switch section in which transfer switches U sw1 to U sw48 and read capacitors C T1 to C T48 are provided between the load capacitors C L1 to C L48 and the read switches T sw1 to T sw48 in the matrix signal wiring section and a reset switch V sw to reset the read capacitors C T1 to C T48 is further provided. Transfer switches U sw1 to U sw48 are connected to the matrix signal wirings L 1 to L 48 , respectively, and are used to transfer the charges accumulated in the load capacitors C L1 to C L48 formed on the matrix signal wirings L 1 to L 48 to the read capacitors C T1 to C T48 . The transfer switches U sw1 to U sw48 are simultaneously driven by a transfer pulse G t . The read switches T sw1 to T sw48 are connected to the read capacitors, respectively, and are used to sequentially read out potentials of the read capacitors C T1 to C T48 to the outside of the photoelectric converting apparatus through an amplifier Amp by sequentially switching the read switches. The read switches are sequentially driven by the shift register SR 2 . R sw1 to R sw48 denote the reset switches which are arranged between the load capacitors C L1 to C L48 and the transfer switches U sw1 to U sw48 which are formed in the matrix signal wiring section and are used to reset the potentials of the load capacitors C L1 to C L48 to a reset potential V R . The reset switches are driven by the reset pulse C res . V sw denotes the reset switch to reset the potentials of the read capacitors C T1 to C T48 to the reset potential V R . The reset switch V sw is driven by a reset pulse g res . Fig. 4 is a timing chart showing the reading operation of the photoelectric converting device of the first embodiment. It is now assumed that an original has a uniform image concentration. The light information which entered the photoelectric conversion elements S 1-1 to S 1-48 of the first block are accumulated as charges into the accumulation capacitors C s1-1 to C s1-48 . After the elapse of a predetermined time, a voltage pulse is applied to the first gate drive line G 1 from a shift register SR 1 , so that the transfer TFTs T 1-1 to T 1-48 are turned on. Thus, the charges of the accumulation capacitors C s1-1 to C s1-48 are transmitted through the matrix signal wirings L 1 to L 48 and are transferred to the load capacitors C L1 to C L48 . A gate pulse width t 1 which is necessary for such a transfer of the charges depends on a time constant which is determined by smaller one of the capacitance values of the accumulation capacitor C s and the load capacitor C L and an ON resistance R t of the transfer TFT T. The accumulation capacitor C s is properly set to a value within a range from 10 to 20 pF. The load capacitor C L is properly set to a value within a range from 100 to 300 pF. Since the ON resistance R t of the TFT using a-Si:H is so large to be a few MΩ, the time constant is set to a value within a range from 10 to 40 µs. Subsequently, by applying a gate drive signal G t , the transfer switches U sw1 to U sw48 are simultaneously turned on and the signal charges accumulated in the load capacitors C L1 to C L48 are simultaneously transferred to the read capacitors C T1 to C T48 . A length t 3 of the gate pulse G t which is necessary for such a transfer of the charges depends on a time constant which is determined by an ON resistance R u of the transfer switch U sw and smaller one of the capacitance values of the load capacitor C L and the read capacitor C T . The load capacitor C L is properly set to a value within a range from 100 to 300 pF. The read capacitor C T is properly set to a value within a range from 10 to 20 pF. Since the ON resistance R u can be selected to a value within a range from 50 to 300 Ω if a general analog switch is used, the time constant can be set to a short value of 100 ns or less. Subsequently, by sequentially applying a voltage pulse to gate drive lines g 1 to g 48 from the shift register SR 2 , the signal charges of the first block which were transferred to the read capacitors C T1 to C T48 are converted into the serial signal by the read switches T sw1 to T sw48 . The serial signal is amplified by the amplifier Amp and is taken out as an output voltage V out to the outside of the photoelectric converting apparatus. A period of time t 4 when the signal output of one block is generated depends on the ON resistance R t of the read switch T sw , the input capacitance containing the wiring capacitance of the amplifier Amp, and the response speed of the amplifier. However, since the period t 4 can be selected to a value within a range from 1 to 2 µs per bit, it is set to a value within a range from about 50 to 100 µs per 48 bits. In the reading operation, the reset pulse g res is successively applied to the reset switch V sw for a latter part of the period of time t 6 when the voltage pulse which is applied to the gate drive lines g 1 to g 48 is set to a high voltage. Therefore, in the latter part of the period t 6, both of the read switch T sw and the reset switch V sw are simultaneously turned on and the read capacitors C T1 to C T48 are sequentially reset to the reset potential V R . A length t 5 of the gate pulse g res which is necessary to reset depends on a time constant which is determined by the ON resistance R v of the reset switch V sw , the ON resistance R t of the read switch T sw , and the capacitance value of the read capacitor C T . However, the value of the read capacitor C T is properly set to a value within a range from 10 to 20 pF. Since the ON resistances R v and R t can be selected to values within a range from 50 to 300 Ω if general analog switches are used, the time constant can be set to a short value of 100 ns or less. On the other hand, the load capacitors C L1 to C L48 are simultaneously reset by applying the reset pulse C res to the reset switches R sw1 to R sw48 in parallel with the above signal reading operation. A length t 2 of the gate pulse C res which is needed to reset the load capacitors depends on a time constant which is determined by an ON resistance R r of the reset switch R sw , the resistance of the matrix signal wirings, and the capacitance values of the load capacitor C L . The length t 2 is set to a value of about a few µs. After completion of the resetting operation, a voltage pulse is applied to the gate drive wiring G 2 from the shift register SR 1 and the transfer operation of the second block is started. Simultaneously with the transfer operation, the reset TFTs R 1-1 to R 1-48 of the first block are turned on. The charges of the accumulation capacitors C s1-1 to C s1-48 of the first block are reset to the reset potential V R , thereby preparing for the next accumulating operation. As will be obviously understood from the above description of the operations, in a photoelectric conversion device in accordance with the invention, a period of time when the signal between blocks is not generated in the signal output V out can be eliminated and the reading speed can be substantially made fast. That is, by transferring the signal charges in the load capacitors C L1 to C L48 to the read capacitors C T1 to C T48 , the resetting operation of the load capacitors C L1 to C L48 and the transfer operation of the next block can be executed in parallel with the reading operation by the read switches T sw1 to T sw48 . Thus, a time which is required for the reading and resetting operations of one block is determined by either longer one of the sum (t 1 + t 2 + t 3 ) of the period t 1 when the transfer TFTs are in the ON state, the period t 3 to transfer the charges to the read capacitors, and the period t 2 to reset the load capacitors and the period t 4 when the read switches T sw1 to T sw48 operate. Since the period t 3 is substantially so short to be 100 ns or less as mentioned above, such a time is decided by either longer period of the period (t 1 + t 2 ) and the period t 4 . In the photoelectric conversion device shown in Fig. 1 since the signal charges of the load capacitors C L1 to C L48 are not transferred to the read capacitors C T1 to C T48 , the resetting operation of the load capacitors C L1 to C L48 and the transfer operation of the next block cannot be executed in parallel with the operations of the read switches T sw1 to T sw48 . Therefore, a time which is required to execute the reading and resetting operations of one block is determined by the sum (t 1 + t 2 + t 4 ) of the period t 1 when the transfer TFTs are in the ON state, the period t 2 to reset the load capacitors, and the period t 4 when the read switches T sw1 to T sw48 operate. For instance, assuming that the periods t 1 , t 2 , and t 4 are respectively set to 40 µs, 5 µs, and 50µs, the reading time per block is equal to 95 µs in the case of the conventional apparatus. In the embodiment, the period t 4 is determined to be rate-determining step and is equal to 50 µs, so that the speed can be raised by about 50%. In the embodiment, if the reading time per block is set to a value which is equal to that in the conventional apparatus, that is, if it is set to 95 µs in the above example, the period t 4 when the read switches T sw1 to T sw48 operate can be changed from 50 µs to 95 µs and the sum (t 1 + t 2 ) of the period t 1 when the transfer TFTs are in the ON state and the period t 2 to reset the load capacitors can be set to a long time of 95 µs. Therefore, the ON resistances of the switches (TFTs and general analog switches) which restrict the respective periods can be set to large values, namely, the sizes of switches can be reduced. If there is no need to raise the read speed as mentioned above, there are advantages such that the chip size can be reduced and the switching noises can be reduced. Further, in the embodiment, since the period of time when the signal between blocks is not generated in the signal output V out is eliminated, there is no need to execute the processes for temporarily storing the signal output of the photoelectric converting apparatus into the line memory before it is image processed and for converting the intermittent signals into the continuous signal. Or, there is no need to non-continuously perform the image process. Thus, there are also advantages such that the costs of the whole system are not increased and the image quality doesn't deteriorate. Figs. 5A and 5B are a schematic cross sectional view and a schematic plan view of a photoelectric conversion section according to the photoelectric converting apparatus of the embodiment. In the embodiment, a photoelectric conversion element section 1, an accumulation capacitor section 2, TFT sections 3 and 4, a matrix signal wiring section 5, a gate drive wiring section 6, and the like are integratedly formed on a translucent insulative substrate 10 by using a-Si:H by the same process. A first conductor layer 24 made of Al, Cr, or the like, a first insulative layer 25 made of SiN or the like, a photoconductive semiconductor layer 26 made of a-Si:H, an ohmic contact layer 27 made of n+ type a-Si:H, and a second conductor layer 28 made of Al, Cr, or the like are formed on the insulative substrate 10. In the photoelectric conversion element section 1, reference numerals 30 and 31 denote upper layer electrode wirings. A signal light L' which was reflected by an original P changes a conductivity of the photoconductive semiconductor layer 26 made of a-Si:H and changes a current flowing between the upper layer electrode wirings 30 and 31 which face like a comb. Reference numeral 32 denotes a light shielding layer made of a metal. The light shielding layer 32 can be also constructed in a manner such that it is connected to a proper driving source and serves as a control electrode (gate electrode) which faces the main electrodes 30 (source electrode or drain electrode) and 31 (drain electrode or source electrode). The accumulation capacitor section 2 comprises: a lower layer electrode wiring 33; the first insulative layer 25 and the photoconductive semiconductor layer 26 which are formed on the lower layer electrode wiring 33; and a wiring which is formed on the photoconductive semiconductor layer 26 and is continuous with the upper layer electrode wiring 31 of the photoelectric conversion section 1. The accumulation capacitor section 2 has a structure of what is called an MIS capacitor. Any one of a positive bias and a negative bias can be used as a bias condition. However, by setting the bias condition so that the lower layer electrode wiring 33 is always set to a negative bias, a stable capacitance and stable frequency characteristics can be obtained. The TFT sections 3 and 4 comprise: a lower layer electrode wiring 34 serving as a gate electrode; the second insulative layer 25 serving as a gate insulative layer; the semiconductor layer 26; an upper layer electrode wiring 35 serving as a source electrode; an upper layer electrode wiring 36 serving as a drain electrode; and the like. In the matrix signal wiring section 5, an individual signal wiring 22 made of a first conductive layer, the insulative layer 25 which covers the individual signal wiring, the semiconductor layer 26, the ohmic contact layer 27, and a common signal wiring 37 which crosses the individual signal wiring and is made of a second conductor layer are sequentially laminated onto the substrate 10. Reference numeral 38 denotes a contact hole to obtain an ohmic contact between the individual signal wiring 22 and the common signal wiring 37. Reference numeral 39 denotes a line to line shield wiring provided between the common signal wirings. In the wiring section 6 of the gate lines to drive the TFTs, an individual gate wiring 40 made of the first conductor layer 24, the insulative layer 25 which covers the individual gate wiring, the semiconductor layer 26, the ohmic contact layer 27, and the common gate wiring 41 which crosses the individual gate wiring 40 and is made of the second conductor layer 28 are sequentially laminated onto the substrate 10. Reference numeral 42 denotes a contact hole to obtain an ohmic contact between the individual gate wiring 40 and the common gate wiring 41. As mentioned above, in the photoelectric converting apparatus of the embodiment, since all of the photoelectric conversion element section, accumulation capacitor section, TFT setion, matrix signal wiring section, and gate drive wiring section have the laminate structure of the photoconductive semiconductor layer, insulative layer, conductor layer, and the like, those sections are simultaneously formed by the same process. Further, a passivation layer 11 made of SiN or the like to mainly protect and stabilize the semiconductor layer surfaces of the photoelectric conversion element section 1 and TFT sections 3 and 4 and a friction resistance layer 8 made of a microsheet glass or the like to protect the photoelectric conversion elements and the like from the friction with the original P are formed on the second conductor layer 28. A static electricity countermeasure layer 15 made of a translucent conductor layer is formed between the passivation layer 11 and the friction resistance layer 8. The static electricity countermeasure layer 15 is arranged to prevent that the static electricity which is generated by the friction between the original P and the friction resistance layer 8 exerts an adverse influence on the photoelectric conversion elements and the like. A transparent conductive film of an oxide semiconductor such as ITO or the like is used as a material of the static electricity countermeasure layer 15 because it is necessary to transmit an illumination light L and the signal light L'. In the embodiment, the friction resistance layer 8 formed with the static electricity countermeasure layer 15 is adhered onto the passivation layer 11 by an adhesive layer. The embodiment uses a structure of the photoelectric converting apparatus of what is called a complete contact type in which the reflected light from an original is directly detected without using an equal magnification fiber lens array or the like. Thus, a system such as a facsimile apparatus or the like can be constructed as a fairly compact size and a degree of freedom in designing of the mechanism when a system is constructed increases. The invention can be also used in an image reading apparatus of the contact reading type using an equal magnification fiber lens and the like. Fig. 6 shows a preferred second embodiment according to the invention and shows an equivalent circuit diagram of only a parallel/serial converting section 12 because a photoelectric converting section is similar to that in the first embodiment shown in Fig. 1. It is a feature of the second embodiment that a dummy load capacitor C L0 , a transfer switch U sw0 to transfer charges of the dummy load capacitor C L0 , a read capacitor C T0 , a read switch T sw0 , a reset switch V sw0 to reset the read capacitor C T0 , and a reset switch R sw0 to reset the dummy load capacitor C L0 are added to the parallel/serial conversion section in the first embodiment. Further, a timing control circuit OR to drive the above additional circuits and buffer amplifiers Amp 1 and Amp 2 and a differential amplifier for obtaining a differential output between an output of the dummy load capacitor and an ordinary signal output are added. The reading operation of the second embodiment is executed as follows. By applying the reset pulse C res , the reset switch R sw0 operates simultaneously with the reset switches R sw1 to R sw48 and the dummy load capacitor C L0 is reset to the reset potential V R . By applying the transfer pulse G t , the transfer switch U sw0 operates simultaneously with the transfer switches U sw1 to U sw48 . The charges in the dummy load capacitor C L0 are transferred to the read capacitor C T0 . Then, by sequentially applying voltage pulses to the second gate drive lines g 1 to g 48 by the shift register SR 2 , the read switches T sw1 to T sw48 are sequentially turned on, thereby generating a signal output from the buffer amplifier Amp 1 . In parallel with the above operations, the read switch T sw0 is switched at timings when the OR of the gate pulses of the second gate drive lines g 1 to g 48 is calculated and a potential of the read capacitor C T0 is generated through the buffer amplifier Amp 2 . On the other hand, the read capacitor C T0 is reset to the reset potential V R by the reset switch V sw0 at the same timing as the timing when the read capacitor C T48 is reset. By the above operations, a dummy signal which is generated from the buffer amplifier Amp 2 is ideally set to the reset potential V R . However, actually, the switching noises of the switches are multiplexed. Similarly, in the signal which is generated from the buffer amplifier Amp 1 , the switching noises of the switches are also multiplexed to the light information obtained by the photoelectric conversion section. The switching noises multiplexed to the dummy signal and the switching noises multiplexed to the light information can be substantially equalized by making the shapes and the like of the switches which are used coincident. Therefore, the switching noises can be cancelled by obtaining a difference between the dummy signal which is generated from the amplifier Amp 2 and the signal which is generated from the amplifier Amp 1 . As mentioned above, in the second embodiment, by adding the operation to read out the charges of the dummy load capacitor C T0 , the switching noises which can cause a problem when the signal is read out can be cancelled. Thus, the photoelectric conversion device of the present invention can be also applied to a system such as facsimile apparatus, image reader, or the like to execute image processes of a high quality. Fig. 7 shows a preferred third embodiment according to the invention and shows another example of a construction of the parallel/serial conversion section in which a dummy signal is read out and a difference between the dummy signal and the inherent signal output is obtained, thereby cancelling the switching noises in a manner similar to the second embodiment. In the third embodiment, a power source for the reset potential V R is directly connected to the transfer switch U sw0 in place of the dummy load capacitor C L0 in the second embodiment. Since the transfer switch U SW0 is driven by the gate pulse G t ' at the timing synchronized with the reading timing of each bit, the potential of the read capacitor C T0 is set to the reset potential V R . The read switch T SW0 is switched and the potential of the read capacitor C T0 is read out to the buffer amplifier Amp 2 in a manner similar to the second embodiment. After that, the read capacitor C T0 is reset by the reset switch V SW0 at a timing of g res . Since the construction shown in Fig. 7 doesn't need the dummy load capacitor C L0 of a large capacitance value within a range from 100 to 300 pF, the switching noises can be easily cancelled as compared with the method whereby the dummy load capacitor C L0 is used as shown in the second embodiment. Further, since the read capacitor C L0 is reset at a timing of each bit, there are advantages such that a fluctuation of the potential of the read capacitor C L0 due to a leakage current or the like can be reduced and an error in association with the noise cancellation can be extremely reduced. By applying the photoelectric converting apparatus constructed as mentioned above, other various kinds of image processing apparatuses such as facsimile apparatus, image reader, copier, an electronic blackboad, and the like can be constructed. Fig. 8 shows a preferred example of a facsimile apparatus which is constructed by using a photoelectric conversion device 100 of the invention. Reference numeral 102 denotes a feed roller to feed the original P toward the reading position; 104 indicates a separating member to certainly separate and feed the originals P one by one; and 106 a conveying roller which is arranged at the reading position for the photoelectric conversion device 100 and restricts a surface of the original P to be read and conveys the original P. In the example shown in the diagram, W denotes a recording medium having a form of a roll paper. Image information which was read by the photoelectric conversion device 100 or image information which was transmitted from the outside is formed on the recording medium W. Reference numeral 110 denotes a recording head to form the image. Any one of various types of recording heads such as thermal head, ink jet recording head, and the like can be used as a recording head 110. As an ink jet recording head, for instance, there is preferably used a recording head of the type such that a film boiling phenomenon is caused in an ink by using a heat energy and a bubble is generated and the ink is emitted from an emission opening by the growth and contraction of the bubble. The recording head of either the serial type or the full-line type can be used. Reference numeral 112 denotes a platen roller for conveying the recording medium W toward the recording position by the recording head 110 and restricting the surface of the recording medium to be recorded. Reference numeral 120 denotes an operation panel in which switches to execute operation inputs, a display section to display messages and an operating state of the apparatus, and the like are arranged. Reference numeral 130 denotes a system control board. A control section to control each section, a processing circuit section of the image information, a transmitting and receiving section, and the like are provided on the board 130. Reference numeral 140 denotes a power source of the apparatus. By using the photoelectric conversion device of the invention as an image input section of the system such as a facsimile apparatus or the like, the image processes on the system side can be executed by simple means. Thus, the costs of the whole system can be remarkably reduced. As described above, according to the embodiment, the period of time when the signal between blocks is not generated in the signal output of the photoelectric conversion device which is matrix driven can be eliminated and the reading speed can be substantially made fast. Further, since the period of time when the signal between blocks is not generated in the signal output is eliminated, the processes for temporarily storing the signal output of the photoelectric converting apparatus into the line memory before the signal output is image processed and for converting the intermittent signals into the continuous signal do not need to be executed on the side of the system such as a facsimile apparatus or the like or there is no need to non-continuously perform the image processes, so that there are advantages such that the costs of the whole system are not increased and the image quality is not deteriorated.

Claims: A photoelectric conversion device comprising a photoelectric conversion section comprising a plurality of photoelectric conversion elements (S 1-1 to S 36-48 ), each photoelectric conversion element being associated with a respective switching element (T 1-1 to T 36-48 ) having a gate coupled to a gate drive conductor (G 1 to G 38 ) and matrix signal conductors (L 1 to L 48 ) coupled to the switching elements for receiving signals from respective photoelectric conversion elements (S 1-1 to S 36-48 ); a drive section for applying drive signals to the gate drive conductors (G 1 to G 38 ) for enabling signals from associated photoelectric conversion elements (S 1-1 to S 36-48 ) to be supplied in parallel to respective matrix signal conductors (L 1 to L 48 ) and stored by capacitive charge storage means (C L1 to C L48 ) coupled to the matrix signal conductors; and a read section comprising read capacitors (C T1 to C T48 ), transfer switches (U SW1 to U SW48 ) for transferring charge from the charge storage means (C L1 to C L48 ) to the said read capacitors (C T1 to C T48 ) and read switches (T SW1 to T SW48 ) for reading out charge stored by the read capacitors (C T1 to C T48 ) in sequence to provide a serial output signal, characterised by control means for controlling operation of the read switches (T SW1 to T SW48 ) so that read out of charge from a read capacitor (C T1 to C T48 ) occurs after transfer of charge from the charge storage means (C L1 to C L48 ) by a transfer switch (U SW1 to U SW48 ) has been completed and overlaps with the supply of subsequent signals from the photoelectric conversion elements (S 1-1 to S 36-48 ) to the matrix signal conductors (L 1 to L 48 ). A photoelectric conversion device according to claim 1, wherein resetting means are provided for supplying a resetting signal to reset the potential of a read capacitor (C T1 to C T48 ) during a latter part of the period during which the associated read switch (T SW1 to T SW48 ) is reading out charge from the read capacitor. A photoelectric conversion device according to claim 1 or 2, wherein resetting means (R SW1 to R SW48 ) are provided for resetting the potential of the capacitive charge storage means (C L1 to C L48 ) after transfer of charge from the capacitive charge storage means to the associated read capacitor (C T1 to C T48 ). A photoelectric conversion device according to any one of the preceding claims, wherein a number of blocks of photoelectric conversion elements (S 1-1 to S 1-48 , S 2-1 to S 2-48 ...) are provided with the gates of the switching elements (T 1-1 to T 1-48 , T 2-1 to T 2-48 ...) associated with photoelectric conversion elements in different blocks being coupled to different gate drive conductors (G 1 to G 48 ) for enabling parallel signals to be supplied to the matrix signal conductors (L 1 to L 48 ) from each block in sequence and wherein resetting means (R 1-1 to R 1-48 , R 2-1 to R 2-48 ...) are provided for resetting a block of photoelectric conversion elements while signals are being supplied to the matrix signal conductors by another block of photoelectric conversion elements. A photoelectric conversion device according to any one of the preceding claims, further comprising dummy signal capacitive charge storage means (C L0 ) and means (U SW0 , C T0 , T SW0 , C T0 , Amp1 and Amp2) for subtracting charge stored by the dummy signal storage means from the charge read out by the read switches. An image processing apparatus using as an image input section, a photoelectric converting device according to any one of the preceding claims. An image processing apparatus according to claim 6, wherein said image processing apparatus is a facsimile machine. An image processing apparatus according to claim 6, wherein said image processing apparatus is an image reader. An image processing apparatus according to claim 6, wherein said image processing apparatus is a copier. An image processing apparatus according to claim 6, wherein said image processing apparatus is an electronic blackboard. An image processing apparatus according to any one of claims 6 to 10, further comprising a recording section for recording according to an image information input by said image input section. An image processing apparatus according to claim 11, wherein said recording section is an ink jet recording device. An image processing apparatus according to claim 12, wherein said ink jet recording device emits an ink by using heat to form the ink jet. A method of reading out signals from a photoelectric conversion device comprising a plurality of photoelectric conversion elements (S 1-1 to S 36-48 ), each photoelectric conversion element being associated with a respective switching element (T 1-1 to T 36-48 ) having a gate coupled to a gate drive conductor (G 1 to G 48 ) and matrix signal conductors (L 1 to L 48 ) coupled to the switching elements for receiving signals from respective photoelectric conversion elements (S 1-1 to S 36-48 ), which method comprises causing signals to be supplied in parallel from photoelectric conversion elements (S 1-1 to S 36-48 ) to matrix signal conductors (L 1 to L 48 ) for storage as parallel signals by capacitive charge storage means (C L1 to C L48 ) coupled to the matrix signal conductors by supplying gate drive signals to the gate drive conductors (G 1 to G 48 ), transferring charge stored by the capacitive charge storage means to read capacitors (C T1 to C T48 ) and reading charge stored by the read capacitors in sequence to provide a serial output signal, characterised by reading the charges stored by the read capacitors (C T1 to C T48 ) after completion of charge transfer from the capacitive charge storage means (C L1 to C L48 ) to the read capacitors and causing further signals to be supplied in parallel from the photoelectric conversion elements to the matrix signal conductors (L 1 to L 48 ) for storage as parallel signals by the capacitive charge storage means (C L1 to C L48 ) by supplying gate drive signals to the gate drive conductors (G 1 to G 48 ) while charge is being read out from a read capacitor (C T1 to C T48 ). A method according to claim 14, further comprising resetting the potential of a read capacitor (C T1 to C T48 ) during a latter part of the period during which charge is being read out from the read capacitor. A method according to claim 14 or 15, further comprising resetting the capacitive charge storage means (C L1 to C L48 ) after transfer of charge to the read capacitors (C T1 to C T48 ). A method according to claim 14, 15 or 16, further comprising supplying gate drive signals in sequence to different blocks of photoelectric conversion elements (S 1-1 to S 1-48 , S 2-1 to S 2-48 ...) of the device for enabling parallel signals to be supplied to the matrix signal conductors (L 1 to L 48 ) from each block in sequence and resetting the photoelectric conversion elements of a block while signals are being supplied by another block to the matrix signal conductors. A method according to any one of claims 14 to 17, further comprising subtracting charge stored by dummy signal capacitive charge storage means (C L0 ) from charge read out from the read capacitors.

Inventors: ENDO TADAO, KAIFU NORIYUKI, SAIKA TOSHIHIRO, SHIMADA TETSUYA, ENDO, TADAO, KAIFU, NORIYUKI, SAIKA, TOSHIHIRO, SHIMADA, TETSUYA, ENDO, TADAO, C/O CANON KABUSHIKI KAISHA, KAIFU, NORIYUKI, C/O CANON KABUSHIKI KAISHA, SAIKA, TOSHIHIRO, C/O CANON KABUSHIKI KAISHA, SHIMADA, TETSUYA,C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1991
Main classification: H04N5
IPC codes: H04N5, H04N1, H04N3