Ultraviolet-erasable type nonvolatile semiconductor memory device having asymmetrical field oxide structure

Abstract: For obtaining improved writing characteristics, a reduced source resistance and an increased cell current of an ultraviolet-erasable type nonvolatile semiconductor memory device, a plurality of field oxide films (2) with an asymmetrical pattern are provided which are arranged in rows and columns to define memory cells with a stacked gate structure having floating and control gates (5, 1). Each of the field oxide films (2) has an extended portion (202, 203) at both sides in a row direction. The floating and control gates (5, 1) include a portion (101, 102) extending on each of the field oxide films in a column direction. A cell slit (6) is located at the extended portion (202, 203) of the field oxide film to electrically insulate the floating gates (5) for every rows from one another. A common control gate layer (1) is provided for every rows as the control gates of memory cells.

Description: This invention relates to an ultraviolet-erasable type nonvolatile semiconductor memory device comprising: a semiconductor substrate; a plurality of field oxide regions arranged in rows and columns on said semiconductor substrate, each field oxide region having in plan view a middle portion between two enlarged end portions; an array of memory cells defined by said field oxide regions, each of said memory cells including a stacked gate transistor having a floating gate, a control gate and a channel formed between adjacent end portions of said field oxide regions in the row direction, said floating gate being provided above said semiconductor substrate so as to overlap adjacent end portions of said field oxide regions in the row direction; cell slits electrically isolating floating gates of said memory cells from one another in the row direction; and common control gates connecting adjacent control gates of said memory cells in the row direction. Such an ultraviolet-erasable type nonvolatile semiconductor memory device (hereinafter called "EPROM") includes memory cells each comprised of a MOS transistor having floating and control gates. In this device, an electric charge, for example, electrons, is selectively stored in the floating gates of the memory cells to perform programming of data, and ultraviolet light is applied thereto to erase the stored data. Figs. 2A through 2D show such a conventional EPROM memory cell array. Specifically, Fig. 2A is a plan view of the array, Fig. 2B a sectional view taken along line A - A′ in Fig. 2A, Fig. 2C a sectional view taken along line B - B′ in Fig. 2A, and Fig. 2D a sectional view taken along line C - C′ in Fig. 2A, respectively. An EPROM having rectangular field oxide islands is known from EP-A-0 236 676. An EPROM having octagonal field oxide regions is described in Electronics, Vol. 62, (1989) March, No. 3. p.84. In the accompany drawings, reference numeral 21 denotes control gates disposed on an upper portion of a stacked gate structure. These control gates 21 are arranged parallel to one another, and extend in a row direction on a semiconductor substrate surface. Reference numeral 22 denotes field oxide films for isolation, each having a dumb-bell-shaped pattern having a semielliptical portion at both ends. The field oxide films 22 are arranged in row and column directions on the semiconductor substrate surface. Reference numeral 23 denotes drain regions, each of which is defined by two field oxide films 22 adjacent in the row direction and two control gates 21 crossing the semielliptical portions of the field oxide films 22 in the row direction. A source region 24 is provided by a region facing each drain region 23 through one control gate 21 in the column direction. A region enclosed by a dotted line in Fig. 2A is a cell slit 26, which shows a boundary region between floating gates 25 provided at the lower portion of the stacked gate structure, that is, which includes no floating gate 25 disposed under the control gates 21 and crosses each source region 24 in the column direction as shown in Fig. 2B. In Fig. 2B, reference numeral 31 denotes a P-type silicon substrate, 32 a gate insulating film provided between the substrate 31 and the floating gate 25, 33 an insulating film formed between the floating gate 25 and the control gate 21, respectively. As described above, memory cells are arranged in the row and column directions, thereby providing a memory cell array. Further, in each memory cell as shown in Fig. 2C, the floating gate 25 is formed on the gate insulating film 32 located between the drain and source regions 23 and 24, and the control gate 21 is provided above the floating gate 25 through an insulating film 33. In general, to increase the operating speed of the memory device, the current driving ability of each memory cell must be improved. Therefor, if a capacitance between the substrate 31 and the floating gate 25 is given by C1 and a capacitance between the floating gate 25 and the control gate 21 is given by C2 (referring to Fig. 2C), it is necessary to increase the equivalent capacitance rendered by C1·C2/(C1+C2). For increasing the equivalent capacitance, respective values of C1 and C2 may be high. Further, writing characteristics are improved as an electric field applied between the substrate 31 and the floating gate 25 is increased during data writing. Consequently, considering writing characteristics, it may be desirable that the capacitance C2 is higher than the capacitance C1. For these reasons, the floating gate 25 is extended on the field oxide film 22 to increase the capacitance C2 between the floating gate 25 and the control gate 21 as shown in Fig. 2B. For more increasing the capacitance C2, it has been proposed to partially enlarge widths of the floating gate 25 and control gate 21 on the field oxide film 22 as shown in Fig. 3. However, in such a structure, since the cell slit 26 is provided on an approximately central portion of the field oxide film 22, the enlarged gate portion is removed by the cell slit 26 to leave only a part thereof. Accordingly, the structure fails to provide a remarkable advantage even if a part of the gate width is increased. A method of forming the conventional memory cell structure will be explained with reference to Figs. 2A - 2C. At first, the dumbbell-shaped field oxide films 22 each having the semielliptical portion at both ends are formed in the P-type semiconductor substrate 31 in the row and column directions of the substrate surface, thereby isolating memory cells from one another. Then, conductive layers for providing the floating gates 25 are formed in the row direction of the substrate surface in such a manner that they extend onto both the gate insulating films 32 formed on the semiconductor substrate 31 and both ends of the semielliptical portions of the field oxide film 22. Thereafter, the conductive layers extending to both ends of the semielliptical portions in the row direction are selectively removed by a desired width. The cell slits 26 are then formed to provide the floating gates 25 of respective memory cells. At this time, the semiconductor substrate 31, which is exposed among the semielliptical portions of two field oxide films 22 that are adjacent to each other in the column direction, is selectively removed. However, as described above, since the cell slits 26 are formed in the semiconductor substrate 31, unwanted thickness steps are provided in the source region 24. As shown in Fig. 2D, the source region 24 is formed by ion-implanting N-type impurity into the P-type semiconductor substrate 31, and diffusing the implanted impurity thereinto. Narrow portions may be provided by the thickness steps in the N⁺-type layer serving as the source region 24, thereby increasing the resistance between the source region and a source contact (not shown). It is an object of this invention to provide an ultraviolet-erasable type nonvolatile semiconductor memory device having an improved field oxide structure. It is another object of the invention to provide an ultraviolet-erasable type nonvolatile semiconductor memory device having improved cell slits. According to one aspect of the present invention, the ultraviolet-erasable type nonvolatile semiconductor memory device intially defined is characterized in that each of said field oxide regions has an extended portion in a row direction at both ends thereof to provide an asymmetric pattern about both row and column directions; said floating gate includes a portion extending in a column direction on each of said field oxide regions, while said control gate has a corresponding portion extending in a column direction above each of said field oxide regions so as to face said portion of said floating gate; and each of said cell slits is located at said extended portion of each of said field oxide regions. The novel and distinctive features of the invention are set forth in the claims appended to the present application. The invention itself, however, together with further objects and advantages thereof may best be understood by reference to the following description and accompanying drawings in which: Fig. 1A is a plan view showing a memory cell structure of an EPROM according to an embodiment of the invention; Fig. 1B is a sectional view taken along line A - A′ in Fig. 1A; Fig. 1C is a sectional view taken along line B - B′ in Fig. 1A; Fig. 2A is a plan view showing a memory cell structure of a conventional EPROM; Fig. 2B is a sectional view taken along line A - A′ in Fig. 2A; Fig. 2C is a sectional view taken along line B - B′ in Fig. 2A; Fig. 2D is a sectional view taken along line C - C′ in Fig. 2A, and Fig. 3 is a plan view showing a part of the memory cell structure of the conventional EPROM. The ultraviolet-erasable type nonvolatile semiconductor memory device (EPROM) of the invention will now be explained with reference to the drawings. In Figs. 1A through 1C, reference numerals 1 and 1′ denote control gates of the stacked gate structure, each of which is provided on the upper portion of the stacked gate structure. The control gates 1 and 1′ include extended portion 101 and 102 facing each other in the column direction, and are arranged parallel with one another in the row direction. Reference numeral 2 denotes field oxide films for isolating memory cells, which are arranged at the intersections of the row and column directions of the substrate surface. Each film has a pattern which includes a base portion 201 extending in the column direction, a first semielliptically extended portion 202 extending to the left, and a second semielliptically extended portion 203 extending to the right. The extended portions 202 and 203 are asymmetrical with respect to a line extending along the base portion 201. The extended portion 202, for example, has a size substantially identical to a portion which is provided by removing the right half portion of one semielliptical portion of the field oxide film 22 (in Fig. 2A), and adding the removed right portion to the left half portion of the same. These field oxide films 2 isolate the memory cells from one another. Reference numeral 3 denotes drain regions 3 each defined by two field oxide films 2 arranged adjacent in the row direction and two control gates 1 and 1′ crossing the semielliptically extended portions 202 and 203 of the two films 2 adjacent to each other. A source region 4 is provided by a region facing each drain region 3 through one control gate 1 or 1′ in the column direction. A region enclosed by a dotted line Fig. 1A is a cell slit 6, which shows a boundary region between the floating gates 5 provided at the lower portion of the stacked gate structure, that is, which includes no floating gate 5 located under the control gate 1 and reaches the source region 4 in the column direction. In order to obtain a high equivalent capacitance, the floating gates 5 are provided with extended portions (not shown) opposed to the extended portions 101 and 102 of the control gates 1 and 1′. In Fig. 1B, reference numeral 11 denotes a P-type silicon substrate, 12 a gate insulating film formed between the substrate 11 and the floating gate 5, and 13 an insulating film formed between the floating gate 5 and control gate 1, respectively. Further, as shown in Fig. 1A, in each of the field oxide films 2 arranged in the column direction, the cell slits 6 do not overlap the extended portions 101 and 102 of the control gates 1 and 1′, and are located above the semielliptically extended portions 202 and 203 in the column direction so as to electrically isolate the floating gates 5. That is, the cell slits 6 are arranged in a staggered fashion in the field oxide films 2 which are adjacent to one another in the column direction. Consequently, the cell slits 6 do not cross the source regions 4. Thus, as shown in Fig. 1C, the unwanted thickness steps are not formed in the substrate 11, thereby reducing each source resistance and increasing the area of each floating gate. Accordingly, since the stacked gate structure including the control gates 1 and 1′ and the floating gates 5 can be made large, the capacitance C2 between the floating gate 5 and control gate 1 will be increased though the capacitance C1 between the semiconductor substrate 11 and floating gate 5 is approximately equal to the capacitance of the conventional structure. In addition, since each field oxide film 2 has a straight edge at both sides, the size thereof will be also reduced. Moreover, a variation in the patterns of the field oxide films after making the memory cells may be eliminated as compared to the conventional field oxide films having the semielliptical portion at both ends. According to the embodiment described above, even if the area S1 between the semiconductor substrate 11 and floating gate 5, which determines the capacitance C1, is same as that of the conventional one, the area S2 between the floating gate 5 and control gate 1, which determines the capacitance C2, is 1.4 times higher than that of the conventional one. In general, in consideration of dielectric breakdown voltage, the insulating film 13 provided between the floating gate 5 and the control gate 1 is made about 1.5 times thicker than the insulting film 12 provided between the semiconductor substrate 11 and floating gate 5. Thus, if the capacitance C1 is given by 1, the capacitance C2 becomes 2.9 in the embodiment, while it is 2.1 in the conventional structure. Accordingly, the equivalent capacitance C given by C1·C2/(C1+C2) becomes 0.74 in the embodiment, while it is 0.68 in the conventional structure. Therefore, the cell current can be increased by 10%, as compared to the conventional structure, thereby achieving the high speed operation. Further, a voltage to be applied to the gate insulating film 12, which determines an injection efficiency for injecting electrons into the floating gate 5 by applying a voltage V to the control gate 1, becomes 0.74 V, while it is 0.68 V in the conventional structure. This means that more electrons can be injected into the floating gate in the embodiment than in the conventional case. As described above, the present invention provides ultraviolet-erasable type nonvolatile semiconductor memory devices which have the increased cell current, the improved writing characteristics, and the reduced source resistance.

Claims: An ultraviolet-erasable type nonvolatile semiconductor memory device comprising: a semiconductor substrate (11); a plurality of field oxide regions (2) arranged in rows and columns on said semiconductor substrate, each field oxide region having in plan view a middle portion between two enlarged end portions; an array of memory cells defined by said field oxide regions (2), each of said memory cells including a stacked gate transistor having a floating gate (5), a control gate (1) and a channel formed between adjacent end portions of said field oxide regions (2) in the row direction, said floating gate (5) being provided above said semiconductor substrate (11) so as to overlap adjacent end portions of said field oxide regions (2) in the row direction; cell slits (6) electrically isolating floating gates (5) of said memory cells from one another in the row direction; and common control gates connecting adjacent control gates of said memory cells in the row direction; characterised in that: each of said field oxide regions (2) has an extended portion (202,203) in a row direction at both ends thereof to provide an asymmetric pattern about both row and column directions; said floating gate (5) includes a portion extending in a column direction on each of said field oxide regions (2), while said control gate (1) has a corresponding portion (101,102) extending in a column direction above each of said field oxide regions so as to face said portion of said floating gate; and each of said cell slits (6) is located at said extended portion (202,203) of each of said field oxide regions. A semiconductor memory device according to claim 1, characterised in that each of said field oxide films (2) has a base portion (201) arranged in said column direction, a first semielliptically extended portion (202) extending to a left side at an upper portion of said base portion (201), and a second semielliptically extended portion (203) extending to a right side at a lower portion of said base portion. A semiconductor memory device according to claim 2, characterized in that said first and second extended portions (202, 203) are arranged in said row direction. A semiconductor memory device according to claim 2, characterized in that said first and second extended portions (202, 203) are asymmetric with respect to a central line of said base portion (201). A semiconductor memory device according to claim 2, characterized in that said portion of said floating gate is provided on said base portion (201) of each of said field oxide films (2) so as to face the other portion thereof adjacent to one of said memory cells formed on the same field oxide film in said column direction. A semiconductor memory device according to claim 2, characterized in that said portion (101, 102) of said control state (1) is provided above said portion of said floating gate (5). A semiconductor memory device according to claim 1, characterized in that each of said memory cells is comprised of a MOS transistor having source and drain regions (4, 3) and a gate. A semiconductor memory device according to claim 7, characterized in that a gate insulating film (12) is provided between said semiconductor substrate (11) and said floating gate (5). A semiconductor memory device according to claim 7, characterized in that said drain region (3) is provided by a region surrounded by two field oxide films (2) adjacent to each other in said row direction and two control gates (1) passing through each of said extended portions (202, 203) thereof. A semiconductor memory device according to claim 7, characterized in that said source region (4) is provided by a region facing said drain region (3) through said control gate (1) in said column direction. A semiconductor memory device according to claim 1 characterized in that said cell slits (6) cross said floating gates (5) in said column direction. A semiconductor memory device according to claim 1, characterized in that said cell slits (6) are located in a staggered fashion on said field oxide films (2) adjacent in said column direction. A semiconductor memory device according to claim 10, characterized in that source regions (4) of said MOS transistors are provided in common for each row.

Inventors: SAKAI KATSUYA C O INTELL PROPE, SAKAI, KATSUYA, C/O INTELL.PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: H01L27
IPC codes: H01L21, H01L29, H01L27