Data processing device with test circuit

Abstract: A data processing device with a test circuit, comprises, a plurality of macro blocks (1a and 1b), a common bus (4) for transferring the output of one of the macro blocks (1a and 1b) to the macro blocks (1a and 1b), a tri-state buffer (30a and 30b) incorporated into each macro block (1a and 1b), a bus control circuit (2) for selecting the tri-state buffer (30a and 30b) in a normal operation mode in which the device performs its normal functions, then for transferring the information stored in the macro block (1a and 1b) corresponding to the tri-state buffer (30a and 30b) selected by the bus control circuit (2) to the common bus (4), a selecting control circuit, which comprises a selector (7a and 7b), an AND gate (9a and 9b), and F/F (6a and 6b), for selecting the tri-state buffer (30a and 30b) in a test operation mode which the device has entered, then for transferring the information stored in the macro block (1a and 1b) corresponding to the tri-state buffer (30a and 30b) selected by the selecting control circuit (2) to the common bus (4), and a F/F (8) for setting the device in either the normal operation mode or the test operation mode. In the data processing device according to the present invention, in addition to the bus control circuit (2) which is used in the normal operation mode, the selecting control circuit which is used in the test operation mode is provided, so that the efficiency of the test vector generation can be greatly improved.

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention relates to a data processing device with which the test vectors of a scan test for functional elements such as a plurality of macro blocks connected to a common bus can be generated very efficiently. Description of the Prior Art Functional elements (hereinafter referred to as macro blocks) each comprising an adder, an arithmetic and logic calculation unit, a random access memory (RAM), and a read only memory (ROM), and others which are combinational circuits or sequential circuits are connected to an address bus or a data bus to transfer data stored in the macro blocks in a data processing device such as a microprocessor. In general, a data transfer control method for the microprocessor is basically divided into two kinds of methods. The first method, for example, is executed by using a microprogram. In the method, an input/output operation for data is performed through a common bus under the control of one control block. In the second method, the data input-output operation is controlled through the common bus under the control of plural control blocks. Both the first and second methods are commonly used in conventional microprocessor devices including large scale, complicated and integrated circuits. In these conventional microprocessor devices, only one macro block is selected for the data output operation through the common bus to prohibit the data output operation by other macro blocks. The control operation for the data input/output operation, as described above, is used in a conventional microprocessor device to avoid conflict between data provided by the two or more macro blocks on the common bus (bus data conflict). It is almost impossible, in particular, to test thoroughly conventional microprocessor device using the second method in the normal operation mode by only using test instructions and data provided from outside the microprocessor device, since the microprocessor device include a great number of functional elements and the control operations among the functional elements are much more complicated than that using the first method. Normal operation mode means that in which a microprocessor device operates to execute its normal functions. As a good solution for the above problem, in general, a scan design method used to be adopted to test the dominant part of the microprocessor device. The main point of that method is that, the flip-flop (F/Fs) of the functional elements, the macro blocks and the like, and an input terminal and an output terminal of the microprocessor device, are connected in series and operate as if each of them are a part of a shift register directly connected to the outside the device in a 'scan' operation mode. In more detail, a scan test (operation) with a test vector in the scan design method is carried out as follows: (1) a test vector is set in series from the outside of the device through the chain of F/Fs in the scan operation mode, (2) one cycle of the test operations of the functional elements, the macro blocks and the like, is carried out in the normal operation mode, and (3) a resultant test data stored in the F/Fs is read out to the outside of the device again in the scan operation mode. As explained above, in the scan operation mode based on the scan design method, the test vectors and the resultant test data are transferred in series into the F/Fs and out of the F/Fs, respectively. As a result, though test operations for the sequential circuits incorporated in the microprocessor device are correctly executed by using the scan design method, the test operations take much time. In the prior art, a special test method other than the scan design method is therefore utilized for the test operations of the macro blocks such as ROM, RAM and other memory devices to reduce the test time required for the test operation of the devices in the conventional microprocessors. The scan design method is used for a macro block such as a control logic unit and other kinds of the macro blocks which are mainly composed of random logic circuits and F/Fs. In the following, the data output control operation for the data processing device in which a scan test (in which a test vector is set in the device by the scan operation based on the scan design method, the test operation for the device is carried out, and then a resultant test data is read out to the outside of the device) can be carried out by using the scan design method, will be explained with reference to Fig. 1. The scan test for the functional blocks can be executed by the data output operation based on the scan design method. Fig. 1 is a block diagram showing the configuration of the main part of the data processing device in which the scan test operation can be executed. In the same diagram, outputs of the macro blocks 1a and 1b are transferred alternately into a common bus 4 through a pair of bus buffers 3a and 3b under the control of a bus control circuit 2. The bus control circuit 2 comprises mainly a random logic circuit and in some cases a micro instruction control circuit and the like. One of the bus buffers 3a and 3b is selected by the bus control circuit 2. The functional blocks 1a and 1b may have data input paths from the common bus 4, which are depicted as paths 50a and 50b, respectively. In the scan test, for example, the test vectors, which are generated automatically by a Computer Aided Testing (CAT) system based on the D-algorithm, are provided to the macro blocks 1a and 1b, and the bus control circuit 2 in the scan operation mode. Next, only one cycle of the normal operation of the data processing device is executed, then the resultant test data of the execution are stored temporarily in a register 5, which is connected to the common bus 4, or registers in the macro blocks 1a and 1b (not shown). The resultant test data are read out in series through the register 5 or the registers in the macro blocks 1a and 1b, and through an output terminal to the outside of the device in the scan operation mode. There are four cases for controlling the output operations from the macro blocks 1a and 1b to the common bus 4 through the bus buffers 3a and 3b by the bus control circuit 2 in the scan test operation, as follows: (1) the output from the macro block 1a is transferred to the common bus 4 through the bus buffer 3a which is only in the active state under the control of the bus control circuit 2, (2) the output from the macro block 1b is transferred to the common bus 4 through the bus buffer 3b which is only in the active state under the control of the bus control circuit 2, (3) the outputs from the macro blocks 1a and 1b cannot be transferred to the common bus 4 through the bus buffers 3a and 3b, both of which are in the inactive state under the control of the bus control circuit 2, and (4) the outputs from the macro blocks 1a and 1b are transferred to the common bus 4 through the bus buffers 3a and 3b, both of which are in the active state under the control of the bus control circuit 2. In general, the frequency that each of the four states described above is generated by an automatic test vector generator is approximately equal in the scan test operation in the conventional data processing device. There is no advantage in executing the scan test operations under the two states (3) and (4), because no outputs obtained from the macro blocks 1a and 1b are transferred to the common bus 4 in the state (3). In the state (4), the outputs from the macro blocks 1a and 1b will conflict on the common bus 4. Accordingly, test vectors with the states (3) and (4) have to be excluded from a set of test vectors giving useful information on the faults of the device. As shown in Fig. 1, in the case where there are two macro blocks which output to the common bus 4, there are the four states for transferring the outputs of the macro blocks under the control of the bus control circuit 2. The frequency that each state (1), (2), (3), or (4) is generated in automatic test vector generation is nearly the same so that test vectors giving resultant test data can be obtained only twice in the meaningful generation of the four test vectors with the four states (1), (2), (3), or (4). In general, test vectors giving meaningful results in the scan test operation can be obtained at a rate of N times in 2 N time scan test vector generation, when the N (N is an integer) macro blocks are connected to the common bus. Therefore the occurrence probability of useful test vectors obtained in the automatic scan test vector generation for the conventional data processing device in which the N of 2 N is two or more is lower than 1. The greater the number of the macro blocks, the more time it takes to generate useful scan test vectors applicable to the device. In the prior art, checking operation for detecting whether generated test vectors cause data conflict or hi-impedance on a common bus or not is necessary to obtain useful test vectors after test vectors are generated by the CAT. When these undesirable states occur, the corresponding test vectors are excluded from a set of test vectors applied to the device. Thus, in the prior art, the test vectors by which only one buffer becomes in the active state are selected after all possible test vectors are generated. However, as described above, it takes much time to generate all possible test vectors for the conventional data processing device. Namely, the rate of the useful test vectors in all generated test vectors made by the CAT becomes lower. In other words, the efficiency of the test vector generation becomes lower. SUMMARY OF THE INVENTION An object of the present invention is to solve this problem of the prior art by providing a data processing device with a test circuit by which test vectors for test operations are generated in a short time and the efficiency of the test generation can be increased. A data processing device according to the present invention is described in claim 1. Advantageous embodiments are described in the subclaims. In addition to the first selection control means which is used in the normal operation mode, the second selection control means which is used in the test operation mode is incorporated in the data processing device according to the present invention, so that the efficiency of generating useful test vectors for the data processing device can be greatly improved. These and other objects, feature and advantages of the present invention will be more apparent from the following description of a preferred embodiment, taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic block diagram illustrating a conventional data processing device. Fig. 2 is a schematic block diagram of a data processing device with a test circuit according to the present invention. Fig. 3 is a timing chart for the data processing device as shown in Fig. 2. DETAILED DESCRIPTION OF THE EMBODIMENT A preferred embodiment according to the present invention will now be explained. Fig. 2 is a schematic block diagram of parts of a data processing device with a test circuit according to the present invention. The same diagram mainly shows macro blocks 1a and 1b and other constructional elements which are used for a scan test operation for the data processing device according to the present invention. As compared with the normal operation mode used in the conventional data processing device, the data processing device, as shown in Fig. 2, further comprises a test operation mode which differs from the normal operation mode and in which the bus buffers 3a and 3b, as shown in Fig. 2, are not controlled by the bus control circuit 2. Namely, in the data processing device shown in Fig. 2, output data transferred from the bus buffers 3a and 3b to the common bus 4 are controlled in the two operation modes - the normal operation mode and the test operation mode. The test operation mode will now be explained in more detail. The data processing device with a test circuit according to the present invention operates in three operation modes - the normal operation mode, the scan operation mode (which are also used in the conventional data processing device), and the test operation mode. An instruction from an external device is executed in the normal operation mode for the data processing device. In the scan operation mode, the F/Fs incorporated in the device can operate to set test vectors or read out the resultant test data. In the test operation mode, the action of the bus buffers is controlled by control data from the external device set in the scan operation mode by the scan-path method. The test operation mode handles more test vectors than the normal operation mode. Namely, test vectors which are never used in the normal operation mode are generated for the test operation mode for detecting troubled nodes in the macro blocks and others by the Computer Aided Testing (CAT) system. As compared with the data processing device shown in Fig. 1, the data processing device shown in Fig. 2 further comprises flip-flops (hereinafter called F/Fs) 6a and 6b, selectors 7a and 7b, a F/F 8, and a few logic gates. The F/Fs 6a and 6b can control the bus buffers 3a and 3b in the scan test. The control operations of the F/Fs 6a and 6b, and the bus buffers 3a and 3b which are controlled by the bus control circuit 2, are selected by the selectors 7a and 7b in the test operation mode. The selectors 7a and 7b are controlled by the F/F 8. The F/F 6a latches either a scanned test control input provided to its input terminal S or an activation signal A provided to its input terminal D as one of outputs of the bus control circuit 2 under the control of the test signal TEST in synchronization with a clock signal. The F/F 6a latches the scanned test control data through the input terminal S in the scan operation mode when the test signal TEST is at a high level (H). The F/F 6a latches the activation signal A through the input terminal D in the normal operation mode and the test operation mode when the test signal TEST is at a low level (L). The F/F 6b latches either an output provided from the F/F 6a to its input terminal S or an activation signal B provided to its input terminal D as another output from the bus control circuit 2 under the control of the test signal TEST in synchronization with the clock signal. The F/F 6b latches the output from the output terminal Q of F/F 6a through the input terminal S in the scan operation mode when the test signal TEST is at a high level (H). The F/F 6b latches the activation signal B through the input terminal D in the normal operation mode and in the test operation mode when the test signal TEST is at a low level (L). The F/F 6b outputs the activation signal B or the output from the F/F 6a as a scanning output from the output terminal Q in the F/F 6b in synchronization with the clock signal in the scan operation mode. As described above in detail, the test signal TEST is used for operating the F/Fs 6a, 6b, and 8 in the scan operation mode. As described below, the test signal TEST is used as a trigger signal for setting the data processing device in a test operation state. In Fig. 2, the scan input and the scan output are directly connected to the input terminal S of the F/F 6a and the output terminal Q of the F/F 6b. But the present invention is not limited to the embodiment. For example, the above scan input and the above scan output may be connected to other scannable circuit element in the data processing device. The number of scan chains composed of scannable F/Fs and registers in the device may be one or more by which the transfer time of the scanning inputs or outputs can be reduced. Thus, there are many configuration of the test circuit for executing the scan design method. In the present embodiment, the one scan chain is used for a simplified explanation of the data processing device with the test circuit. The scan chain for testing the macro blocks 1a and 1b, and the bus control circuit 2 comprises the F/Fs and registers. The total number of the F/Fs and the registers including the F/Fs 6a and 6b, and the register 5 as shown in Fig. 2, and if may, those in the macro blocks 1a and 1b, and in the bus control circuit 2 (not shown), is m. Moreover. it is defined in the embodiment that the first and the second F/Fs observed from the input terminal for the scanning input are the F/Fs 6a and 6b. The activation signal A as the output of the bus control circuit 2 or the output of an AND gate 9a is selected under the control of a selection signal SEL and then transferred to the bus buffers 3a to control the operation of the bus buffer 3a. The selector 7a selects the activation signal A when the selecting signal SEL is in the low state (L) and it selects the output of the AND gate 9a when the selecting signal SEL is in the high state (H) to provide this signal to the bus buffer 3a. The output of the F/Fs 6a is transferred to one of input terminals of the AND gate 9a, and the output of an inverter 10 is provided to another input terminal of the AND gate 9a. The activation signal B as the output of the bus control circuit 2 or the output of an AND gate 9b is selected under the control of the selection signal SEL and then transferred to the bus buffer 3b to control the operation of the bus buffer 3b. The selector 7b selects the activation signal B when the selecting signal SEL is in the low state (L) and it selects the output of the AND gate 9b when the selecting signal SEL is in the high state (H) to provide this signal to the bus buffer 3b. The output of the F/Fs 6b is provided to one of input terminals of the AND gate 9b, and the output of an inverter 10 is provided to another input terminal of the AND gate 9b. The F/F 8 latches the output of an OR gate 11 through its input terminal D in synchronization with the clock signal in order to output the selection signal SEL through its output terminal Q. The data stored in the F/F 8 is set at the low level (L) by a reset signal. In addition, once the test signal TEST becomes the high state (H) at a data-latch timing edge of the F/F 8, the output of the F/F 8 as the selecting signal SEL is kept at the high level so long as the reset signal is not given to the F/F 8. The data processing device with the testing circuit according to the present embodiment has the configuration described above. The operation of the data processing device according to the present embodiment will now be explained. First, the normal operation mode will be explained. The data processing device enters the normal operation mode after the required elements of the data processing device are initialized by an external reset signal. The F/F 8 is initialized by the reset signal given through its reset terminal R, then its output enters the low state (L). Thereby, either the activation signal A or B transferred from the bus control circuit 2 is selected by the selector 7a or 7b, and then provided to the bus buffer 3a or 3b. As one of the bus buffers 3a and 3b is placed in the active state (in which the contents of the macro block 1a or 1b are read out to the common bus 4) or the inactive state (in which no contents of the macro block 1a or 1b are read out to the common bus 4) by the activation signal A or B, the contents of one of the macro blocks 1a and 1b is transferred to the common bus 4 through the bus buffer 3a or 3b which is in the active state. Next, the test operation of the data processing device including the macro blocks 1a and 1b, the bus control circuit 2, and the F/Fs 6a, 6b and 8 is explained by using a test vector generated by the CAT with reference to Fig. 3 which shows the timing chart of the data processing device according to the embodiment. In the data processing device, there are three stages described below for the scan test operation. The test vector generated by the CAT is handled as follows: When the test vector is generated by the CAT and there is data conflict (bus conflict) or high impedance (bus high impedance) on the common bus 4 according to the state of the bus buffers 3a and 3b for the macro blocks 1a and 1b in the normal operation mode, the data processing device is placed in the test operation mode as the third operation mode in which test vectors are generated to use each test operation mode set from an external device by using scan input operation. Namely, only the bus buffer 3a enters in the active state in the first test operation mode, then the contents of the macro block 1a are provided to the common bus 4 (at this time, the bus buffer 3b is in the inactive state). On the other hand, only the bus buffer 3b enters in the active state in the second test operation mode, then the contents of the macro block 1b are provided to the common bus 4 (at this time, the bus buffer 3a is in the inactive state). In the prior art, when bus conflict or bus high impedance occurs, the resultant test data transferred to the common bus from the macro blocks 1a and 1b cannot be used as the useful test vectors. However, there is no bus conflict or bus high impedance in the data processing device according to the present invention. Accordingly, the time for generating test vectors can be reduced and the efficiency of the test vector generation can be increased in the data processing device according to the present invention. In the first stage (in the scan operation mode) as illustrated in Fig. 3, the test vectors are set in the m F/Fs which are scannable. In the first cycle in the first stage as shown in Fig. 3, the test signal TEST is set at the high level (H) from the low level. Thereby, in the second cycle in the first stage, the selection signal SEL as the output of the F/F 8 becomes the high level (H), so that the data processing device enters the scan operation mode. The test vectors are set in the macro blocks la and 1b, the F/Fs 6a and 6b, and the F/Fs which can be scanned in the bus control circuit 2 (not shown in Fig. 3) through the scan chain. The outputs of the AND gates 9a and 9b are selected by the selectors 7a and 7b during the second to the m-th cycles, since the selecting signal SEL is in the high state (H). Each output of the AND gates 9a and 9b is in the low state (L) because the low level (L) signal which is inverted from the test signal TEST in the high level (H) by the inverter 10 is provided to one of the input terminals of each of the AND gates 9a and 9b. Accordingly, the low level (L) signal is provided to a pair of control input terminals 30a and 30b of the bus buffers 3a and 3b. Thereby, both of the bus buffers 3a and 3b enter the high impedance state, so that their outputs are not transferred to the common bus 4, in order to avoid the bus conflict on the common bus 4 by the outputs of the macro blocks 1a and 1b in the test operation mode. In such a case, the electric potential of the common bus 4 cannot be kept at a constant value because no data is transferred to the common bus 4 (there are no macro blocks which give data to the common bus 4). In many case, when an electric potential of a common bus in a CMOS circuit becomes, for example, an intermediate electric potential, a DC current flows in transistors whose input terminals are connected to the common bus. To avoid the DC current flow in the transistors, small transistors which are normally set to the ON state and connected to the common bus are used in an actual case. As an another way, it is possible that one of the AND gates 9a and 9b can be exchanged for an OR gate and the test signal TEST instead of the reversed test signal TEST can be used to set the state that either the bus buffer 3a or 3b enters in the active state in the scan test operation mode. Next, in the (m+1)th cycle, the scan input data is entered into the F/F 6a through the input terminal S because the test signal TEST is in the high state. When the scan input data as the scan input is kept at the low level at the start of the (m+1)th cycle, the scan input data at the low level is provided to the F/F 6a, then the output of the F/F 6a is also at the low level. Next, in the (m+2)th cycle, the scan input data in the low state is transferred into the F/F 6b through the input terminal S, then maintained in the F/F 6b. On the other hand, when the scan input as the scan vector is at the high level in the (m+2)th cycle, as shown in Fig. 3, the scan input at the high level is provided to the F/F 6a, then maintained. Next, the test signal TEST enters the low level from the high level, then the second stage, in which the test operation is carried out starts. In the (m+2)th cycle of the second stage, when the test signal TEST enters the low level (L), the output of the inverter 10 enters the high level (H) and one of the inputs of each of the AND gates 9a and 9b enters the high level (H). At this time, the outputs of the AND gates 9a and 9b become high level and low level respectively, because the outputs of the F/Fs 6a and 6b as another input of each of the AND gates 9a and 9b are at the high level (H) and the low level (L), respectively. Moreover, the selectors 7a and 7b enter the test operation mode in which they select the outputs of the AND gates 9a and 9b because the selecting signal SEL is maintained at the high level (H). Thereby, the bus buffer 3a enters in the active state and the bus buffer 3b enters in the inactive state. As shown in Fig. 3, in the (m+3)th cycle, the output of the macro block 1a is transferred to the common bus 4 through the bus buffer 3a. The output is then stored in the register 5 or the registers in the macro blocks 1a an 1b. Next, when the test signal TEST is changed from the low level (L) to the high level (H), the data processing device enters the third stage (the scan operation mode), in which the resultant test data are read out to the outside of the device to analyze whether the device is fault free or not. At the beginning of the third stage, the resultant test data stored in the scannable F/Fs and registers on the scan chain is transferred out of the data processing device for analysis (in particular, the output of the macro block 1a is stored in the resister 5 or the registers in the macro blocks 1a an 1b through the common bus 4 and the output of the bus control circuit 2 is stored in the F/Fs 6a and 6b). In addition, a next scan test vector can also be input to the scan chain from outside the data processing device together with the readout operation for the resultant test data in the third stage. Therefore, the time for the test operation can be reduced because the first stage for the test vector and the third stage for the next test vector are carried out at the same time. Similarly, in order to let only the output of the macro block 1b be transferred to the common bus 4, the scan input is set at the high level in the m-th cycle and set at the low level in the (m+1)th cycle, then the output of the F/Fs 6a and 6b are set at the low level and the high level in the (m+2)th cycle, respectively. Thus, in the embodiment described above, whatever activation signals A and B are output from the bus control circuit 2, the outputs of the macro blocks 1a and 1b are obtained by the control of the outputs of the F/Fs 6a and 6b which are set by the scan input through the input terminal S of the F/F 6a without data conflict or high impedance on the common bus. Accordingly, all of the test vectors generated by the CAT can be utilized so that the efficiency of the test vector generation is much increased. By generating test vectors using the CAT, under the condition that the exclusive OR of the outputs of the F/Fs 6a and 6b is set at the high level (H), the efficiency of the test vector generation can be more improved. Finally, some precautions to be taken in the present embodiment described above will be explained. In the embodiment, when the test signal TEST is changed from the low level to the high level to input the first test vector to the scan chain, the output of the F/F 8 (the selecting signal SEL) enters the high level and the output of the F/F 8 can change to the low level only when the reset signal is input to the reset terminal R of the F/F 8. Accordingly, the test operation for the macro blocks 1a and 1b, and the bus control circuit 2 is carried out in the test operation mode in which the bus buffers 3a and 3b are controlled only by the F/Fs 6a and 6b. Therefore the test operation for a logical path through which the bus control circuit 2 controls the bus buffers 3a and 3b cannot be executed. However, the test operation for these logical paths can be easily carried out in the normal operation mode. When there are many macro blocks connected to the common bus 4 so that the test control operation is complicated and it is desirable that the above paths are surely tested, the test operation may require the test signal TEST and the selecting signal SEL to be controlled independently by an external element in order to execute the test surely. The present invention includes the scope described above. The scope of this invention is not limited to the data processing device with a test circuit as shown in Fig. 2, but included many variations that will be obvious to one skilled in the art. For example, in the case where two or more macro blocks are connected to the common bus, test vectors may be generated by the CAT under the condition where one of the outputs of scannable F/Fs each provided for the output control logic of one of the macro blocks, is set at the high level. Moreover, the number of common buses may be one or more. In the embodiment described above, the output of one of the macro blocks 1a and 1b is transferred into the register 5 or registers in the macro blocks 1a and 1b, then it is transferred to the outside of the data processing device for analysis thereof. In some cases, the output may be directly transferred to the outside of the data processing device. Moreover, in the present embodiment, the test vectors are set and then read out from the data processing device for external analysis under the control of the scan design method. But this setting test vectors and read out thereof may be carried out in the one cycle. Various modification will become possible for those skilled in the art after the teaching of the present disclosure without departing from the scope thereof. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A data processing device comprising: a plurality of functional blocks (1a, 1b); at least one common bus (4) for transferring output data received from said functional blocks (1a, 1b); output control means (3a, 3b) respectively associated to said functional blocks (1a, 1b), for transferring output data thereof to the common bus (4); first selection control means (2) for selecting the output control means (3a, 3b) through activation signals (A, B) in a normal operation mode in which the device performs its normal functions, then for transferring the output data of the functional blocks (1a, 1b) corresponding to the output control means (3a, 3b) selected by said first selection control means (2) through said activation signals (A, B), to the common bus (4); test vector generating means (CAT) for generating test vectors capable to be provided to said functional blocks (1a, 1b) and said first selection control means (2); register means (5) connected to the at least one common bus for temporarily storing resultant test data; second selection control means comprising flip-flop means (6a, 6b) respectively associated to said functional blocks (1a, 1b), for selecting the output control means (3a, 3b) in a test operation mode entered in the device, regardless of activation signals output from said first selection control means (2), wherein said test operation mode is a part of a scan test operation comprising said test operation mode and a scan operation mode for scanning resultant test data temporarily stored in said register means (5) so as to avoid test configurations in which all output control means (3a, 3b) are in a high impedance state, or in which more than one output control means (3a, 3b) simultaneously output data to the common bus (4), then for transferring the output data of the functional blocks (1a, 1b) corresponding to the output control means (3a, 3b) selected by said second selection control means, for being transferred to the common bus (4); and a mode setting means (8) for setting the functional blocks (1a, 1b), the first selection control means (2), the second selection control means, and the output control means (3a, 3b) to either the normal operation mode or the test operation mode. The data processing device according to claim 1, wherein said first flip-flop means (6a, 6b) each are provided to receive a test signal (TEST). The data processing device according to claim 1, wherein selector means (7a, 7b) are provided which are respectively connected to control signal input terminals (30a, 30b) of said output control means (3a, 3b). The data processing device according to claim 3, wherein input terminals of said selector means (7a, 7b) are connected to said first selecting means (2) for respectively receiving activation signals (A, B) therefrom. The data processing device according to claim 3, wherein said selector means (7a, 7b) are provided to receive from said mode setting means (8) a selection signal (SEL), when the test operation mode is set at said mode setting means. The data processing device according to claim 3, wherein input terminals of said selector means (7a, 7b) are respectively connected to said first flip-flop means (6a, 6b) of said second selecting means for respectively receiving output signals thereof. The data processing device according to any of the preceding claims, wherein said mode setting means (8) comprises second flip flop means (8), said first flip-flop means (6a, 6b) and said selector means (7a, 7b) being set in the test operation mode by said mode setting means (8) to carry out the test operation, wherein a test vector as a scan input is input to said first flip flop means (6a, 6b) in a scan operation mode, and the operation of the selector means (7a, 7b) is controlled in accordance with the test vector. The data processing device according to any of the preceding claims, wherein said common bus (4) is provided for transferring the output of one of said functional blocks (1a, 1b) to another of said functional blocks (1a, 1b).

Inventors: NOZUYAMA YASUYUKI, OHASHI KAZUHIKO, NOZUYAMA, YASUYUKI, OHASHI, KAZUHIKO
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1991
Main classification: G06F11
IPC codes: G01R31, G06F11