Method for reading a synchronizing signal from a record medium and an apparatus therefor

Abstract: The system operates with sync. and re-sync. signals that delimit sectors on the record medium. The sync. signals are detected in a comparator circuit (21, 22, 23) during a predetermined period. The detection of the re-sync. signals is performed by a second comparator circuit (24, 25, 26) under control of respective circuits (39, 34) depending on whether or not a preceding sync. signal has been detected. According to the invention, in the case of a non-detection of the sync. signal, the comparator circuit is given an enlarged time window within which the re-sync. signal may be detected.

Description: Background of the Invention Field of the Invention The present invention relates generally to a method and an apparatus for reading out a synchronizing signal from a recording medium and, more particularly, is directed to a method and an apparatus for reading out a synchronizing signal provided in a data portion of each sector stored in a recording medium such as an optical disc, a read only type optical disc or a write-in-once (WIO) type optical disc, a magneto-optical disc. Description of the Prior Art Recently, various reading methods and reading apparatuses have been proposed for reading out data recorded on an optical disc provided as a data recording medium. In accordance with these reading methods, by reading out an address from a storage area (ID portion) in which an address of a sector is stored, it is determined whether or not the sector is a sector (target sector) containing data to be read out. If it is the target sector, then data recorded in a data storage area (data portion) following the ID portion is read out next. Data is read out from the data portion on the basis of the sync. signal and re-sync. signal recorded in it. More specifically, the format of each sector on the optical disc is composed of an ID portion 10 and a data portion 11, as shown in Figure 1. The data portion 11 comprises: a sync. data portion (SYNC) 11a at its head, a number of divided data portions 11b composed of 15 bytes or 20 bytes are formed and a resync. data portion (RESYNC) 11c which is formed between the divided data portions 11b. Data recorded in the data portion 11 is recorded in a distributed manner in the respective divided data portions 11b. Sync. pattern data which becomes a sync. signal is recorded on the sync. pattern data portion 11a and re-sync. pattern data which becomes a re-sync. signal is recorded on the re-sync. data portion 11c. Then, on reading the data of the sector, data in the starting divided data portion 11b is read out on the basis of the data (sync. signal) in the sync. data portion 11a and data in the succeeding divided data portion 11b is read out on the basis of data (re-sync. signal) in the re-sync. data portion 11c. That is, data in the respective divided data portions 11b are read out at the detection timings of the sync. signal and the re-sync. signal. Accordingly, data in the data portion 11 cannot be read out without detecting the sync. signal and the re-sync. signal. However, conventionally, since the durations of the detection periods of the sync. signal and the re-sync. signal are determined beforehand, the sync. signal or the re-sync. signal must be detected within its detection period. Then, detection starting and ending timings of the limited detection period of the succeeding re-sync. signal are determined by the detection of the sync. signal. Thus, if the sync. signal cannot be detected, the succeeding re-sync. signal cannot be detected. There is then the substantial disadvantage that data cannot be read out from the optical disc at all. As the recording density of the optical disc is 1 bit/µm 2 which is more than one digit bigger comparing with magnetic disc or magnetic tape, it is apt to be affected by micro fault and many bit errors are apt to occur. The bit error rate is about 10 -5 (one reading error per 10 5 bits) which is 4 to 5 digits larger comparing with recording media such as magnetic disc. Therefore, particularly in an optical disc in which a read error occurs more frequently than with other recording media, frequent occurrence of such read errors of the sync. signal becomes a serious problem. As described above, as the burst error is likely to occur in the optical disc in comparison with the other recording media, data recording in the optical disc is performed such that the data (composed of user data and a control word) is divided into bits or word units and then is recorded by changing their orders. This is called interleave and by adapting this method burst errors are changed into random errors or short word errors, thereby the correcting capacity being increased. In case of data recording by interleave method, firstly an error check code called CRC (Cyclic Redundancy Check) or CRCC (Cyclic Redundancy Check Code) is formed in each one sector from data row of each interleave, then an error check code (ECC) composed of Read Solomon product code or Read Solomon Long Distance Code is generated based on above data and above CRC in each interleave. By recording by the interleave adding ECC in addition with the above CRC, correcting capacity of the data is increased and thus bit error rate is decreased until 10 -12 . By forming CRC and ECC at each interleave and by recording the CRC and the ECC together with the data on the optical disc by interleave, when 1 sector is composed of 10 24 bytes it is possible to restore the correct data even if 80 byte errors occur in one sector of the data. Further, when 1 sector is composed of 512 bytes it is possible to restore to the correct data even if 40 bytes errors occur in one sector of the data. Therefore, it is important to detect the succeeding re-sync. signal, even if detection of a sync. signal has failed, for increasing the reliability of the data of the optical disc. For an example of a prior art synchronization detection system e.g. for data sequences stored an helically scanned magnetic tape, reference can be made to EP-A-0 242 093. Summary of the Invention An object of the present invention is to provide a method and apparatus for reading out a sync. signal from a recording medium in which, even if the detection of the sync. signal fails, the succeeding re-sync. signal can be detected positively so that data following the first re-sync. signal can be read out reliably regardless of a drop-out of a first divided portion of data. Another object of the present invention is to provide a method and apparatus for reading out a sync. signal from a recording medium in which the data-read error rate can be reduced. As the first aspect of the present invention there is provided a method of reading a signal of a recording medium having a sector in which an address portion and a data portion are recorded, said data portion having synchronization pattern data at a front part thereof, a plurality of divided data portions and re-synchronizing pattern data between the divided data portions, said method comprising the steps of: detecting said synchronizing pattern data; setting predetermined time windows within which said re-synchronizing pattern data are to be detected; and detecting said re-synchronizing pattern data within said predetermined time windows; characterized in that said predetermined time window for the first re-synchronizing pattern data is set to be a first time window if the step of detecting said synchronizing pattern data is successful and set to be a second time window if the said detection is unsuccessful, the second time window having a starting time set before that of the first window and a closing time set after that of the first window. According to the present invention, there is also provided a synchronizing signal reading apparatus for a recording medium, said recording medium having a sector in which an address portion and a data portion are recorded, said data portion having synchronizing pattern data at a front part thereof, a plurality of divided data portions and re-synchronizing pattern data between the divided data portions, said synchronizing signal reading apparatus comprising: a synchronizing pattern detecting means for detecting said synchronizing pattern data provided at the front part of said data portion read from said recording medium on which a plurality of sectors arc formed on a track: re-synchronizing pattern detecting means for detecting re-synchronizing pattern data provided between the divided data portion read from said recording medium within predetermined time windows; synchronizing pattern detection judging means for judging whether the detection by said synchronizing pattern detection means is successful; and re-synchronizing pattern detecting judging means for judging within a predetermined time window whether the detection by said re-synchronizing pattern detecting means is successful; characterized in that said apparatus further comprises control means for setting said predetermined time window for the first re-synchronizing pattern data to be a first effective time window if said synchronizing pattern data detecting means is successful in detecting said synchronizing pattern data, and for setting said predetermined time window to be a second effective time window, longer than said first effective time period, if said synchronizing pattern detecting means is unsuccessful in detecting said synchronizing pattern data. In the above described method for reading synchronizing signal from the record medium when the detection of the sync. pattern data has failed, the detecting period of the re-sync. pattern data is prolonged to thereby detect the re-sync. pattern data. Thus, even if the detection of the sync. pattern data fails, as the duration of the detecting period of the re-sync. pattern data to be detected next is prolonged compared with the case where the detection of the sync. pattern data is successful, a probability that the re-sync. pattern data is detected is increased. Further, according to the above-described apparatus for reading the synchronizing signal from a record medium, when the sync. pattern data is not detected by the sync. pattern detecting means, the sync. pattern detecting and judging means determines that the sync. pattern detecting means has failed in detecting the synchronizing pattern data. The control means controls the re-sync. pattern detecting and judging means on the basis of the judged result of this detection failure such that the duration of the detecting and judging period of the re-sync. pattern detecting and judging means is longer than the case where the re-sync. pattern detecting and judging means successfully detects the re-sync. pattern data. As a result, when the detection of the synchronizing pattern is failed since the duration of the re-sync. pattern detecting period of the re-sync. pattern detecting means is automatically prolonged, the probability that the re-sync. pattern data is detected can be further increased. Brief Description of the Drawings Figure 1 is a schematic diagram showing the format of each sector in an optical disc; Figure 2 is a circuit block diagram of a sync. signal reading apparatus which embodies the present invention; Figure 3 shows one structure of the first, second and third control circuits; Figure 4 shows another structure of the second control circuit; Figure 5 shows a structure of a compound circuit of the first and the third control circuits; Figure 6 is a truth value table; Figure 7 is a timing chart of various signals used in the present invention, and to which references will be made in explaining a case where sync. pattern data is detected successfully; and Figure 8 is a timing chart of various signals used in the present invention, and to which references will be made in explaining a case where the detection of sync. pattern data fails. Description of the Preferred Embodiment Now, an embodiment of a sync. signal reading apparatus for an optical disc according to the present invention will hereinafter be described with reference to Figure 2. Referring to Figure 2, a shift register 21, a sync. pattern memory 22 and a comparator 23 constitute a sync. pattern detecting and a sync.pattern detection judging means. The shift register 21 is adapted to shift 48 bits of data one bit at a time each time data recorded and read out from an optical disc by a recording and reproducing optical head (not shown) is output one bit at a time from a signal processing circuit, not shown and to store therein a total of 48 bits of data. Accordingly, the shift register 21 stores the latest 48 bits of data. The sync. signal pattern memory 22 is formed of a read only memory (ROM) and stores the same sync. pattern data as the sync. pattern data recorded in a sync. data portion 11a shown in Figure 1, that is, the sync. pattern data comprising 48 bits of data. The comparator (digital comparator) 23 compares the latest 48 bits of data read from the optical disc stored in the shift register 21 with the 48 bits of sync. pattern data stored in the sync. signal pattern memory 22 to thereby detect whether or not the sync. pattern data is involved in the data sequentially read out from the optical disc. A detection time of the comparator 23 for comparing and detecting the above described two data is controlled on the basis of an enable signal EN1 which will be referred to later. If it is determined during the detection time that the sync. pattern data is included in the data sequentially read out from the optical disc, that is, the latest 48 bits of data stored in the shift register 21, the comparator 23 outputs a sync. signal detecting signal SG1 (the pulse of the logic [H]), as shown in Figure 7. A shift register 24, a re-sync. signal pattern memory 25 and a comparator (digital comparator) 26 constitute a re-sync. pattern detecting means and non-synchronizing pattern detection judging means. The shift register 24 shifts data one bit at a time each time 16 bits of data recorded and read out from the optical disc by means of the recording and reproducing head (optical head) as described above are output one bit at a time from a signal processing circuit, not shown and stores a total of 16 bits of data of totally 16 bits. Accordingly, the shift register 24 stores the latest 16 bits of data read from the optical disc. The re-sync. signal pattern memory 25 is a read only memory (ROM) and stores the same re-sync. pattern data as the re-sync. pattern data recorded in a re-sync. data portion 11c shown in Figure 1, that is, the 16 bits of re-sync. pattern data. Comparator 26 compares 16 bits of data stored in the shift register 24 and the re-sync. pattern data stored in 16 bits of the re-sync. signal pattern memory 25 to thereby detect whether or not the re-sync. pattern data is included in the data sequentially read out from the optical disc. A detection time for detecting the non-synchronizing pattern data of the comparator 26 is controlled on the basis of an enable signal EN2 which will be referred to later, and the comparator 26 outputs a re-sync. signal detecting signal SG2 (the pulse of the logical [H]) as shown in Figure 7, if it is determined during the detection time that the re-sync. pattern data is included in the shift register 24. Let us explain next a control means for controlling the detection times of the comparators 23 and 26 for detecting the sync. and re-sync. pattern data. A reference clock counter 27 which is an up-counter for performing a counting in synchronization with reference clock RFCLK generated from an external clock generator, not shown, is reset and restarts the count operation each time a detecting means (not shown), for deLecting data (VFO) recorded at the head of an ID portion of each sector outputs a detecting signal IDTOP. The count value of the reference clock counter 27 is supplied to a first control circuit 28. The first control circuit 28 outputs a set trigger signal (logic [H]) when the count value of the reference clock counter 27 reaches a pre-determined first value (hereinafter referred to as a sync. pattern detection starting time), whereas the first control circuit 28 outputs a reset trigger signal (logic [H]) when the count value of the reference clock counter 27 becomes a predetermined second value (referred to hereinafter as a sync. pattern detection ending time) which is larger than the sync. pattern detection starting time. The sync. pattern detection starting time and the sync. pattern detection ending time are values that are theoretically or experimentally obtained beforehand, and a time of highest probability in which the sync. pattern is stored in the shift register 21 and compared with the sync. signal pattern stored in sync. signal pattern memory 22 by comparator 23 is set within these times. A first flip-flop circuit (hereinafter simply referred to as a first FF circuit) 29 responds to the above-mentioned set trigger signal output from the first control circuit 28 to output the enable signal EN1 to the comparator 23. It also responds to the reset trigger signal to erase the enable signal EN1 so that, while the FF circuit 29 outputs the enable signal EN1, or while the control circuit 28 outputs the reset trigger signal after the set trigger signal is outputted, the comparator 23 detects the presence or absence of the sync. pattern data and judges the detected result. The set trigger signal from the first control circuit 28 is supplied to a second flip-flop circuit (hereinafter referred to as a second FF circuit) 30, and the reset trigger signal is output to an AND circuit 31. The second FF circuit 30 is supplied at a reset input terminal R with the sync. signal detection signal SG1 (logic [H]) from the comparator 23 and supplies the AND circuit 31 with a signal of logic [H] (high) level during the period in which the sync. signal detection signal SG1 is supplied thereto after the set trigger signal from the control circuit 28. Accordingly, when the comparator 23 cannot detect the sync. pattern during the period from the pre-determined sync. pattern detection starting time to the sync. pattern detection ending time, the AND circuit 31 outputs the set trigger signal logic [H] to a succeeding third flip-flop circuit (hereinafter referred to as a third FF circuit) 32. A re-sync. timing counter (hereinafter referred to as a timing counter) 33 is supplied with the sync. signal detection signal SG1 and the re-sync. signal detection signal SG2 from the comparators 23 and 26 and reset to start the count operation again in response to these signals. A count value of the timing counter 33 is output to a second control circuit 34 and a latch signal thereof is output to an external apparatus (not shown). The second control circuit 34 outputs a set trigger signal (logic [H]) to a set terminal S of the fourth flip-flop 35 later described when the count value of the timing counter 33 reaches a predetermined third value (hereinafter referred to as a first re-sync. pattern detection starting time), whereas the second control circuit 34 outputs a reset trigger signal (logic [H]) to a reset terminal R of the fourth flip-flop 35 when the count value of the timing counter 33 reaches a pre-determined fourth value (hereinafter referred to as a first re-sync. pattern detection ending time) that is larger than the re-sync. pattern detection starting time. Incidentally, the re-sync. pattern detection starting time and the re-sync. pattern detection ending time are theoretically-or experimentally-obtained value, and a time of highest probability in which the re-sync. pattern data is stored in the shift register 24 and compared is set within these times after the sync. pattern data is detected. A fourth flip-flop circuit (hereinafter referred to as a fourth FF circuit) 35 responds to the set trigger signal from the second control circuit 34 to output a signal of logic [H] (high) level to an AND circuit 36 and responds to the reset trigger signal to output a signal of logic [L] (low) level to the AND circuit 36. Further, the AND circuit 36 is supplied with a signal from the third FF circuit 32 through a NOT circuit 37. It outputs an enable signal EN2 of logic [H] level through an OR circuit 38 to the aforementioned comparator 26 while the fourth FF circuit 35 outputs the signal of logic [H] level when the signal of the third FF circuit 32 is maintained in its logic [L] level state. As described above, when comparator 23 detects the sync. pattern data, the sync. signal detecting signal SG1 is output and the second FF circuit 30 is reset. Therefore, the output of AND circuit 31 remains "L" and the output signal of the third FF circuit 32 maintains logic [L] state. Accordingly, when the sync. pattern data is detected, the comparator 26 detects the presence or absence of a re-sync. pattern and judges the detected result while the period the reset signal is being output after the set trigger signal has been output from the second control circuit 34. A third control circuit 39 is supplied with the count value from the reference clock counter 27 and outputs a set trigger signal when the count value reaches a pre-determined fifth value (hereinafter referred to as a second sync. pattern detection starting time) whereas the third control circuit 39 outputs a reset trigger signal when the input count value reaches a predetermined sixth value (hereinafter referred to as a second sync. pattern detection ending time). The second re-sync. pattern detection starting time is preset to be ahead of the first re-sync. pattern detection starting time which is counted by the timing counter 33 when the comparator 23 detects the sync. pattern data. Also, the second re-sync. pattern detection ending time is set beforehand to be behind the first re-sync. pattern detection ending time which is counted by the timing counter 33 when the comparator 23 detects the sync. pattern data. Accordingly, the detection time (window) determined by the second re-sync. pattern detection starting time and the second re-sync. pattern detection ending time becomes longer than the detection time (window) determined by the first re-sync. pattern detection starting time and the first re-sync. pattern detection ending time. The second re-sync. pattern detection starting time is shorter than the first re-sync. pattern detection starting time and the second re-sync. pattern detection ending time is longer than the first re-sync. pattern detection ending time. A fifth flip-flop circuit (hereinafter referred to as a fifth FF circuit) 40 responds to the set trigger signal of the third control circuit 39 to output a signal of logic [H] level to an AND circuit 41, and also responds to the reset trigger signal from the third control circuit 39 to output a signal of logic [L] level to the AND circuit 41. The AND circuit 41 is supplied with a signal from the third FF circuit 32, and outputs an enable signal EN2 of logic [H] level through an OR circuit 38 to the comparator 26 while the fifth FF circuit 40 is outputting a signal of logic [H] level when the signal from the third FF circuit 32 is maintained in its logic [H] level state. As described above, the comparator 23 does not output the sync. detection signal SG1 (logic [H]) when the sync. pattern data is not detected. Therefore, the second FF circuit 30 is not reset. Thus, the set trigger signal (logic [H]) is output to the third FF circuit 32 from the AND circuit 31 and the output signal from the third FF circuit 32 becomes logic [H]. In other words, when the sync. pattern data is not detected and the signal of the third FF circuit 32 is at its logic [H] level state, the comparator 26 detects the presence or absence of the re-sync. pattern only while the third control circuit 39 is outputting the set trigger signal after the reset trigger signal. The set trigger signal from the third control circuit 39 is output to a reset input terminal R of a sixth flip-flop circuit (hereinafter referred to as a sixth FF circuit) 42, and the reset trigger signal therefrom is output to the third FF circuit 32 and the AND circuit 45. The sixth FF circuit 42 is supplied at its set input terminal with the re-sync. signal detection signal SG2 from the comparator 26. The output from the FF circuit 42 is input to the AND circuit 45 through the NOT circuit (inverter) 44. The reset trigger signal output from the third control circuit 39 is input to the other input terminal of the AND circuit 45. Thus, if the re-sync. signal detection signal SG2 is not output from the comparator 26 until the reset trigger signal is output from the third control circuit 39, the signal RDNG which shows data read error is output from the AND circuit 45. While the output signal from the third FF circuit 32 remains [L], the AND circuit 41 is closed and the AND circuit 37 is opened. Then the set trigger signal and reset trigger signal output from the third control circuit 39 are not applied to the OR circuit 38. On the other hand, the set trigger signal and the reset trigger signal output from the second control circuit 34 are output to the comparator 26 through the OR circuit 38. That is, the detection of the re-sync. pattern data is inhibited at a timing based on the third control circuit 39 until the next sector from now on and the re-sync. pattern data is detected by the comparator 26 at a timing controlled by the second control circuit 34. Figure 3 shows a first structural example of the first control circuit 28, the second control circuit 34 and the third control circuit 39. In the drawing, the set timing register 61 stores the sync.pattern detection starting time (in case of the first control circuit 28), the first re-sync. pattern detection starting time (in case of the second control circuit 34) or the second re-sync. pattern detection starting time (in case of the third control circuit 39). The reset timing register 62 stores the sync. pattern detection ending time (in case of the first control circuit 28), the first re-sync. pattern detection ending time (in case of the second control circuit 34) or the second re-sync. pattern detection ending time (in case of the third control circuit 39). In case of the first control circuit 28, the comparator 63 compares the sync. pattern detection starting time stored in the set timing register 61 and the count value output from the reference clock counter 27 and if they coincide, a set trigger signal is output to set terminal S of the first FF circuit 29. Similarly, in case of the second control circuit 34, the first re-sync. pattern detection starting time and the count value of the timing counter 33, and in case of the third control circuit 39, the second re-sync. pattern detection starting time and the count value of reference clock counter 27 are compared and when they coincide, a set trigger signal is output to the set terminal S of the fourth FF circuit 35 and the set terminal S of the fifth FF circuit 40, respectively. In case of the first control circuit 28, the comparator 64 compares the sync. pattern detection ending time stored in the reset timing register and the count value of the reference clock counter 27, and when they coincide the reset trigger signal is output to reset terminal R of the first FF circuit 29. Similarly, in case of the second control circuit 34, the first re-sync. pattern detection ending time and the count value of the timing counter 33, and in case of the third control circuit 39, the second re-sync. pattern detection ending time and the reference clock counter 27 are respectively subjected to the comparison. When they coincide, the reset trigger signal is output to the reset terminal R of the fourth FF circuit 35 and the reset terminal R of the fifth FF circuit 40, respectively. Figure 4 shows the second structural example of the second control circuit 34. In the drawing, the registers 101 and 102 are for storing the first re-sync. detection starting time and the first re-sync. detection ending time synchronizing with a down edge of the clock CLK. Select terminal S in the selector 103 selectively outputs the data stored in the register 101 at logic [L] and the data stored in register 102 at logic [H]. The comparator 104 compares the selected data output from the selector 103 and the count value of the re-sync. timing counter 33 and when they coincide, a detecting signal d 1 with logic [H] is output to the clock terminal CK of the D-flip-flop 105. The D-flip-flops (called D-FF hereinafter) 105 and 106 connected serially, comprise a binary counter which counts up at a rising edge of a track signal supplied to a clock terminal CK. The Q output of the D-FF 105 is a select signal supplied to a select terminal S of selector 103 and is a set trigger signal supplied to a set terminal S of the fourth FF circuit 35 shown in Figure 2. The D-FF 106 operates at a rising edge of the Q output of the D-FF 105 supplied to the clock terminal CK and the Q output is a reset trigger signal supplied to a reset terminal R of the fourth FF circuit 35 shown in Figure 2. The D-FFs 105 and 106 are reset every time the detecting signal IDTOP is detected, which is produced upon detecting the head of the ID portion 10 of the respective sectors. An operation of the second control circuit 34 is explained. The first re-sync. pattern detection starting time and the first re-sync. pattern detection ending time are set in the registers 101 and 102, respectively, by an external control circuit, not shown. The D-FF 105 and 106 are initially set to logic [L]. Therefore, the selector 103 outputs the first re-sync. pattern detection starting time stored in the register 101 to the comparator 104. The comparator 104 compares the count value of the timing counter 33 with the first re-sync. pattern detection starting time and when the count value reaches the first re-sync. pattern detection starting time, detection signal d 1 of the logic [H] is output to the clock terminal CK of the D-FF 105. Thus, the Q output of the D-FF 105 changes from logic [L] to logic [H] to provide a set trigger signal to be output to set terminal S of the fourth FF circuit 35, thereby changing set terminal S of the selector 103 from logic [L] to logic [H]. Therefore, the selector 103 outputs the first re-sync. pattern detection ending time stored in register 102 to the comparator 104. Thus, the comparator 104 compares the first re-sync. pattern detection ending time with the count value of the timing counter 33. When the count value of the timing counter 33 reaches the first re-sync. pattern detection ending time, the detecting signal d 1 of logic [H] is again output. Therefore, the Q output of the D-FF 105 changes from logic [H] to logic [L], thereby enabling the set trigger signal to be in active. The Q output of D-FF 105 changes from logic [L] to logic [H] and the Q output of the D-FF 106 changes from logic [L] to logic [H] and is applied to reset terminal R of the fourth FF circuit 35 at a reset trigger signal. Further, a circuit obtained by combining the first control circuit 28 and the third control circuit 39 is shown in Figure 5. In Figure 5, the memory 201 is an SRAM (Static Random Access Memory) and has the sync. pattern detection starting time, sync. pattern detection ending time, and second re-synchronizing pattern detection starting time and second re-synchronizing pattern ending time stored in addresses "0" to "3", respectively. The memory 201 can perform a read/write when the chip select terminal CS is at logic [L]. When the output enable terminal of OE is at logic [L], CS is at logic [L], and write enable terminal WE is at logic [L], data is written. When write enable terminal WE is at logic [H], a data read out is performed. The address of the data read out is designated by read address signal input terminals A 0 and A 1 . The comparator 202 compares the data read from the memory 201 with the count value of the reference clock counter 27 and when the data accords with the count value, the detecting signal d 2 of logic [H] is output to the clock terminal CK of the D-flip-flop (called D-FF hereinafter) 203. The D-FF 203, 204 and 205, connected serially, comprise a binary counter and the Q outputs of the D-FFs 203 and 204 are read address signals A 0 and A 1 , respectively, of 2 bits of the memory 201. The Q outputs of the D-FFs 203, 204 and 205 are applied to input terminals I 0 , I 1 and I 2 , respectively, of decoder 206. The D-FFs 203, 204 and 205 are reset every time the detection signal IDTOP is output. This signal is produced when the head of ID portion 10 of respective sectors is detected. The decoder 206 has a function displayed in a truth table shown in Figure 6. It enables output terminals Y 0 , Y 1 , Y 2 , Y 3 to produce a set trigger signal to the set terminal S of the first FF circuit 29, a reset trigger signal to a reset terminal R of the first FF circuit 29, a set trigger signal to a set terminal S of the fifth FF circuit 35 and a reset trigger signal to a reset terminal R of the fifth FF circuit 35. Next, the operation of the above circuit shown in Figure 5 is explained. The sync. pattern detection starting time, sync. pattern detection ending time, the second re-synchronizing pattern detection starting time, and the second re-synchronizing pattern detection ending time are written in the addresses "0" to "3" of the memory 201 by an external control circuit, not shown. The read out of the optical disc starts through the record reproduction head and the data recorded at the head of the ID portion 10 of the sector is detected and when the detection signal IDTOP is output, the reference clock counter 27 is set and starts the count operation and the Q output of the D-FFs 203, 204 and 205 are reset to logic [L]. The chip select terminal CS , the output enable terminal OE are set at logic [L] and write enable terminal WE is set at logic [L] by the control circuit, not shown, and the sync. pattern detection starting time is thus read out from address "0" of the memory 201 and output to the comparator 202. When the count value of the reference clock counter 27 is equal to the sync. pattern detection starting time, a detection signal d 2 is output from the comparator 202 and the Q output of the D-FF 203 is set from logic [L] to logic [H]. Therefore, the input terminal I 0 of the decoder 206 turns to logic [H] and a set trigger signal is thus output from the output terminal Y 0 to the set terminal S of the first FF circuit 29. The read address signal terminal A 0 of the memory 201 changes from logic [L] to logic [H] and the sync. pattern detection ending time is read from address "1" of the memory 201 and output to the comparator 202. When a count operation continues in synchronization with the reference clock RFCLK of the reference clock counter 27 and the count value of the reference clock counter 27 becomes equal to the sync. pattern detection ending time, the detection signal d 2 is again output from the comparator 202. Therefore, the Q output of the D-FF 203 changes from logic [H] to logic [L] and the Q output of the D-FF 204 changes to logic [H]. Therefore, the input terminals I 0 , I 1 and I 2 of the decoder 206 become [L], [H] and [L], respectively, and the output of the output terminal Y 0 becomes logic [L]. This time also, the output of the output terminal Y 1 becomes logic [H], thereby outputting a reset trigger signal to a reset terminal of the first FF circuit 29. As the address signal input terminals A 0 and A 1 of the memory 201 become logic [L] and [H], respectively, this time the second re-sync. pattern detection starting time is read from address "2" of the memory 201 and is output to the comparator 202. When the count value of the reference counter 27 becomes equal to the second re-sync. pattern detection starting time, the third detection signal d 2 is output from the comparator 202. Therefore, the Q output of the D-FF 203 again becomes logic [H] and the Q output of the D-FF 204 is maintained at the logic [H]. Thus, the input terminals I 0 , I 1 and I 2 of the decoder 206 become [H], [H] and [L], respectively, and the output of the decoder 206 enables only output terminal Y 2 to be at logic [H]. The set trigger signal is thus output to the set terminal S of the fifth FF circuit 35. As both read address signal input terminals A 0 and A 1 of the memory 201 become logic [H], the second re-sync. pattern detection ending time is read out from memory address "3" of the memory 201 and is output to comparator 202. Further, when the count operation of the reference clock counter 27 continues in synchronization with the reference clock RFCLK, the count value of the reference clock counter 27 becomes equal to the second re-sync. pattern detection ending time and then the fourth detection signal d 2 is output from the comparator 202. Therefore, the Q outputs of the D-FFs 203, 204 and 205 are at the logic [L], [L] and [H], respectively, and these logic values are applied to the input terminals I 0 , I 1 and I 2 of the decoder 206. Only the output terminal Y 0 of the decoder 206 becomes logic [H] and the reset trigger signal is output to the reset terminal R of the fifth FF circuit 35. The read address signal input terminals A 0 and A 1 of the memory 201 are again initially set to [L]. An action of the thus arranged sync. signal reading apparatus of the optical disc is now explained. Initially, an action in which the sync. pattern data is accurately detected will be explained with reference to Figure 7. When the count value of the reference clock counter 27 becomes identical to the synchronization pattern detection starting time, the first control circuit 28 outputs the set trigger signal and the first FF circuit 29 outputs the enable signal EN1 (logic [H]) shown in Figure 7 to the comparator 23. Then, the comparator 23 responds to this enable signal EN1 to detect whether or not the sync. pattern data is included in the data sequentially read out from the optical disc. When the comparator 23 detects the sync. pattern data and outputs the sync. signal detection signal SG1 during the enable signal EN1 being output, the timing counter 33 is reset and restarts the counting operation, whereas the second FF circuit 30 is set in the reset state. When the count value of reference clock counter 27 reaches the sync. pattern detection time, the reset trigger signal is output from the first control circuit 28, the enable signal EN1 from the first FF circuit 29 is lost and the detection of the sync. pattern data and the judgment of the result detected by the comparator 23 are finished. As described above, since the comparator 23 detects the sync. pattern data, thereby to reset second FF circuit 30 and outputs the sync. signal detection signal SG1, the set trigger signal is not output from the AND circuit 31 to the third FF circuit 32. Accordingly, the output of the third FF circuit 32 is not inverted and its signal is maintained at the logic [L] level. Consequently, since the signal of logic [L] level maintained by the third FF circuit 32 is input to the AND circuit 41, the comparator 26 is inhibited from detecting the re-sync. pattern data at a detection timing based on the third control circuit 39 (i.e., from the second re-sync. pattern detection starting time to the second re-sync. pattern detection ending time). When the count value of the timing counter 33 reaches the first re-sync. pattern detection starting time, the second control circuit 34 outputs the set trigger signal to the fourth FF circuit 35 which outputs the signal of logic [H] level to the AND circuit 36. Thus the enable signal EN2 is output to the comparator 26 from the AND circuit 36 through the OR circuit 38, and the detection of the re-sync. pattern data is started by the comparator 26. When the comparator 26 detects the re-sync. pattern data and outputs the re-sync. signal detection signal SG2, the timing counter 33 is reset and restarts the count operation as noted earlier. The detection of data in each re-sync. data portion 11c of the data portion 11 in this sector by comparator 26 is continued from now on on the basis of enable signal EN2 controlled by the second control circuit 34. An action in which the comparator 23 fails to detect the sync. pattern data within a detection time based on the first control circuit 28 will be explained next with reference to Figure 8. When the comparator 23 fails to detect the sync. pattern data within the above detection period, the sync. signal detection signal SG1 is not output from the comparator 23. Thus the output of the second FF circuit 30 is not inverted and the second FF circuit 30 is maintained in its set state and the timing counter 33 is not reset. Accordingly, the reset trigger signal is output from the first control circuit 38, the set trigger signal is output to the third FF circuit 32 from the AND circuit 31, the output of the third FF circuit 32 being inverted and the third FF circuit 32 is placed in a set state in which the output signal thereof goes to logic [H] level. In this state, since the signal of logic [L] level is input to the AND circuit 36 through the NOT circuit 37, the detection of the re-sync. pattern data read out after the sync. pattern data by the second control circuit 34. Conversely, since the signal of logic level [H] is input to the AND circuit 41, the detection of the re-sync. pattern data read out after the sync. pattern data by the third control circuit 39. Then, when the count value of the reference clock counter 27 coincides with the second sync. pattern detection starting time, the third control circuit 39 outputs the set trigger signal to enable the comparator 26 to start the detection of the re-sync. pattern data. This detection is started earlier than the detection starting time at which the second control circuit 34 starts the detection. More specifically, since the detection of the sync. pattern data has failed, a reference timing (sync. signal detection signal SG1) for reading the re-sync. pattern data is not determined and the timing at which the re-sync. pattern data appears fluctuates by substantially the same amount as the timing at which the sync. pattern appears and thus the detection of the re-sync. pattern starts at an earlier stage. Further, the re-sync. pattern detection ending time is delayed as compared with the first re-sync. pattern detection ending time in an opposite manner to the second re-sync. pattern detection starting time. Accordingly, even when the detection of the sync. pattern data has failed, and as the re-sync. pattern data starts detection ending time of comparator 26 is more extended forward and backward as compared with the case the sync. pattern data detection is successful. The re-sync. pattern data following the sync. pattern data can be detected with certainty even in the case the timing for reading the following re-sync. pattern data being read out from the record reproduction head cannot be detected. If the comparator 26 detects and judges the re-sync. pattern data during this detection time determined by the second re-sync. pattern detection starting time and second re-sync. pattern detection ending time, then the comparator 26 outputs the re-sync. signal detection signal SG2 to the timing counter 33 and also outputs it to the sixth FF circuit 42. Then, the timing counter 33 is reset and the timing counter 33 starts the count operation for detecting the succeeding re-sync. pattern data in this sector. When the reset trigger signal is output from the third control circuit 39, the output of the third FF circuit 32 is inverted (from logic [H] level to logic [L] level). Accordingly, the following detection of the succeeding re-sync. pattern data is performed on the basis of the second control circuit 34 from the third control circuit 39. In this case, if the re-sync. detection signal SG2 is not output, the output of sixth FF circuit 42 is not reversed and signal RDNG designating a failure of the data read is output from AND circuit 45 in synchronization with a reset trigger signal output from the third control circuit 39 to the fifth FF circuit. In the prior art, the detection time of the succeeding re-sync. pattern data is determined so as to fall in a narrow range on the basis of the detection of the sync. pattern data so that, when the detection of the first sync. pattern data has failed, the succeeding re-sync. pattern data cannot be detected and the data of the sector cannot be read out. However, in accordance with this embodiment, since the detection time of the re-sync. pattern data is extended forward and backward, even if the detection of the first sync. pattern data has failed, the re-sync. pattern data can be positively captured and detected, and data following the detected re-sync. pattern data can be read out. Further, data of one divided unit between the sync. pattern dropped out and the first re-sync. pattern can be reproduced by the error correcting circuit, which can as a result reduce the data read error rate. The error correcting circuit produces a CRC for the interleaved data and ECC based on the data, the control word and the above CRC in units of an interleave, thereby adding CRC and ECC to data for recording. As set out above in detail, according to the present invention, even when the detection of the sync. signal has failed, the succeeding re-sync. signal can be detected positively so that, although the first divided unit of data is dropped out, the data following the first re-sync. signal can be reliably read out. This reduces the data read error rate, thus achieving a great advantage for a method and apparatus for reading a synchronizing signal from a recording medium.

Claims: A method of reading a signal of a recording medium having a sector in which an address portion (10) and a data portion (11) are recorded, said data portion having synchronization pattern data (11a) at a front part thereof, a plurality of divided data portions (11b) and re-synchronizing pattern data (11c) between the divided data portions, said method comprising the steps of : detecting said synchronizing pattern data; setting predetermined time windows within which said re-synchronizing pattern data are to be detected; and detecting said re-synchronizing pattern data within said predetermined time windows; characterized in that said predetermined time window for the first re-synchronizing pattern data is set to be a first time window if the step of detecting said synchronizing pattern data is successful and set to be a second time window if the said detection is unsuccessful, the second time window having a starting time set before that of the first window and a closing time set after that of the first window. A synchronizing signal reading apparatus for a recording medium, said recording medium having a sector in which an address portion (10) and a data portion (11) are recorded, said data portion having synchronizing pattern data (11a) at a front part thereof, a plurality of divided data portions (11b) and re-synchronizing patten data (11c) between the divided data portions, said synchronizing signal reading apparatus comprising : a synchronizing pattern detecting means (21, 22, 23) for detecting said synchronizing pattern data provided at the front part of said data portion read from said recording medium on which a plurality of sectors are formed on a track; re-synchronizing pattern detecting means (24, 25, 26) for detecting re-synchronizing pattern data (11c) provided between the divided data portion (11b) read from said recording medium within predetermined time windows; synchronizing pattern detection judging means (21, 22, 23) for judging whether the detection by said synchronizing pattern detection means is successful; and re-synchronizing pattern detecting judging means (24, 25, 26) for judging within a predetermined time window whether the detection by said re-synchronizing pattern detecting means is successful; characterized in that said apparatus further comprises control means (28) for setting said predetermined time window for the first re-synchronizing pattern data to be a first effective time window if said synchronizing pattern data detecting means is successful in detecting said synchronizing pattern data, and for setting said predetermined time window to be a second effective time window, longer than said first effective time window, if said synchronizing pattern detecting means is unsuccessful in detecting said synchronizing patten data. The signal reading apparatus according to claim 2, wherein said re-synchronizing pattern detecting means and said re-synchronizing pattern detection judging means (21, 22, 23; 24, 25, 26) comprise : pattern data storing means (22; 25) for storing said synchronizing and re-synchronizing pattern data; a reading data storing means (21; 24) for storing a latest data having the same number of bits as said synchronizing or re-synchronizing pattern data read from said recording medium; a comparing means (23; 26) for comparing whether the data stored in said first reading data storing means is equal to the respective pattern data stored in said re-synchronizing pattern data storing means; an effective time window setting means (28; 34; 39) for setting a respective effective time window in which said first comparing means performs a comparison of said synchronizing or re-synchronizing pattern and read out data. The signal reading apparatus according to claim 3, wherein said first effective time window setting means comprises : a counter (27, 33) for performing a count operation in synchronization with a clock, said counter generating a present count value; a first count value storing means (61) for storing a predetermined first count value; a second count value storing means (62) for storing a predetermined second count value; a first comparing means (63) for comparing whether the present count value of said counter accords with the predetermined first count value stored in said first count value storing means and for enabling said first comparing means to start the window enabling a comparison operation when both count values are consistent; and a second comparing means (64) for comparing whether said present count value of the counter accords with the predetermined second count value stored in the second count value storing means, for enabling said first comparison means to close the window enabling the comparison operation, and ensuring that the present count value of the first counter accords with the second count value. The signal reading apparatus according to claim 3, wherein said effective time window setting means comprises : a counter for performing a counting operation in synchronization with a clock: a first count value storing means (101) for storing a first count value; a second count value storing means (102) for storing a second count value; a selection means (103) coupled to said first count value storing means and said sixth count value storing means for selecting on the basis of instructions from said control means said first count value stored in said first count value storing means or the second count value stored in said second count value storing means; and a comparing means (104) coupled to said selection means and to said counter for comparing said first count value selected by said selecting means with the count value of said counter, starting the window for a comparison operation when the count value of the counter accords with the first count value, enabling said selection means to select the second count value, comparing the second count value output from said selection means with a count value of the counter and closing the window for a comparison operation when said count value of the counter accords with the second count value. The signal reading apparatus according to claim 5, wherein : said second comparing means (104) enables said selection means (103) to select the first count value stored in said first count value storing means when said count value of the counter accords with the second count value. The signal reading apparatus according to claim 3, wherein said effective time window setting means comprises : storing means (201) for storing a first count value designating a start of a first effective time window, a second count value designating a completion of the first effective time window, a third count value designating a start of a second effective time and a fourth count value designating completion of the second effective time window; read control means for performing a control so that the first count value, the second count value, the third count value and the fourth count value are stored in said storing means and are output therefrom in this order; a counter for performing a count operation in synchronization with a clock; detecting means (202) for detecting whether the count value of the counter coincides with the count value output from said storing means; and means for providing an instruction such that, when said detecting means detects that the count value of the counter coincides with the first count value, a first window for detecting a synchronization signal is opened; when said detecting means detects that the count value of the counter coincides with the second count value, the first window is closed; when said detecting means detects that the count value of the counter coincides with the third count value, a second window for detecting the re-synchronization signal in the case of an unsuccessful detection of the synchronization signal is opened; and when said detecting means detects that the count value of the counter coincides with the fourth count value, the second window is closed.

Inventors: KIKUTA KAZUYOSHI, KIKUTA, KAZUYOSHI
Applicants: FUJITSU LTD, FUJITSU VLSI LTD, FUJITSU LIMITED, FUJITSU VLSI LIMITED
Application year: 1991
Main classification: G11B7
IPC codes: G11B20, G11B7, G06K7, G11B27