Transmitter with nonlinearity correction circuit

Abstract: A feedback loop is composed in which a part of a transmission signal obtained by amplifying a modulation carrier signal by a power amplifier (2) is taken out by a monitor circuit (3), and is detected by an envelope detector (5), and a distortion-free envelope signal delivered from an envelope control signal generator (6) is compared in an error amplifier (7), and by this error signal a gain control terminal (8) of the power amplifier (2) is controlled. The envelope control signal generator (6) possesses a feedback loop which is controlled by a reference voltage (Vref) and a sample hold signal (Sh) to stabilize the mean voltage of a reference envelope signal (Vdetb), and also comprises a multiplier (14) for multiplying Vdetb and a ramping up-down signal (Vramp) to generate a burst-form transmission output.

Description: The present invention relates to a transmitter having a power amplifier for transmitting a modulated carrier signal. This kind of transmitter is hitherto composed as disclosed in U.S. Pat. No. 4,933,986. In this prior art, the transmission signal sent from the transmitter is received by the same transmitter and demodulated to produce a base band feedback signal, and this signal is applied to a modulation base band signal. By controlling in such feedback loop, distortion of the power amplifier is compensated. This approach, however, involves several disadvantages. First, the device size is increased because the receiver and demodulator are necessary for producing the base band feedback signal. Further, gain fluctuations of the receiver and demodulator induce variations of the transmission output, and the complicatedness of this part still worsens the problem. US-A-4,591,800 shows a further prior art amplifier which comprises a power amplifier, a transmission monitor circuit, a detector, an envelope control signal generating means and an error detector which generates an error signal to be supplied to a gain control terminal of the power amplifier to control its gain. The present invention provides a transmitter comprising: a power amplifier having a gain control terminal for amplifying an input modulation carrier signal to obtain a transmission signal; a transmission monitor circuit for picking up a part of the transmission signal from the power amplifier as a monitor signal; a first detector for detecting an envelope of the monitor signal to obtain a transmission envelope signal; an envelope control signal generating means for generating an envelope control signal from the input modulation carrier signal; and a first error detector for comparing the envelope control signal and the transmission envelope signal to generate a first error signal, and for supplying the first error signal to the gain control terminal of the power amplifier, thereby controlling a gain of the power amplifier; characterized in that said envelope generating means comprises: a linear amplifier having a gain control terminal for linearly amplifying the input modulation carrier signal; a second detector for detecting an envelope of the modulation carrier signal amplified by the linear amplifier to obtain a reference envelope signal; a second error detector for comparing the reference envelope signal with a reference voltage to generate a second error signal; a sample and hold circuit connected to the second error detector for sampling and holding the second error signal with an externally supplied sample and hold signal, and for supplying its output to the gain control terminal of the linear amplifier to control a gain of the linear amplifier; an envelope control signal generator connected to the second detector for multiplying the reference envelope signal by an externally supplied burst control signal, and for delivering a burst-form reference envelope signal as an envelope control signal. Preferably, the first detector and second detector are identical circuits and are arranged to be matched in characteristics, so that any nonlinearity of the detectors may be cancelled. Fig. 1 is a block diagram of a transmitter in an embodiment of the invention. Fig. 2 is a timing chart of the transmitter in Fig. 1. Fig. 3(a) is a block diagram showing a constitutional example of a power amplifier. Figs. 3 (b), 3 (c) are characteristic diagrams for explaining the operation of the power amplifier in Fig. 3 (a). Fig. 4(a) is a block diagram showing another constitutional example of the power amplifier. Fig. 4(b) is a characteristic diagram for explaining the operation of the power amplifier in Fig. 4(a). Fig. 5 is a block diagram showing a constitutional example of an envelope detector. Fig. 6 is a block diagram showing a constitutional example of a multiplier. Fig. 1 and Fig. 2 are block diagram and timing chart of the transmitter in an embodiment of the invention. In Fig. 1, numeral 1 is a modulation carrier signal input terminal, 2 is a power amplifier having a gain control terminal 8 for amplifying the modulation carrier signal to obtain a transmission signal, 3 is a monitor circuit for picking up a part of the transmission signal from the power amplifier 2 as a monitor signal, 4 is a transmission signal output terminal, 5 is an envelope detector for detecting the envelope of the monitor signal from the monitor circuit 3 and delivering a transmission envelope signal (Vdeta), 6 is an envelope control signal generator connected to the modulation carrier signal input terminal 1 for delivering an envelope control signal (Vcont), and 7 is an error detector connected between the monitor circuit 3 and the envelope control signal generator 6 for comparing the transmission envelope signal (Vdeta) with envelope control signal (Vcont) to generate an error signal and supplying the error signal to the gain control terminal 8 to control the gain of the power amplifier 2. The envelope control signal generator 6 comprises a linear amplifier 9 having a gain control terminal 13 for linearly amplifying the modulation carrier signal, an envelope detector 10 for detecting the envelope of the modulation carrier signal amplified by the linear amplifier 9 to obtain a reference envelope signal (Vdetb), an error detector 11 for comparing the reference envelope signal (Vdetb) with a reference voltage (Vref) supplied from a reference voltage input terminal 16 to generate an error signal, a sample hold circuit 12 connected to the error detector 11 for holding the error signal with a sample hold signal (Sh) supplied from a sample hold signal input terminal 15 and supplying its output to the gain control terminal 13 so as to control the gain of the linear amplifier 9, and a multiplier 14 connected to the detector 10 for multiplying the reference envelope signal (Vdetb) with a ramping up-down signal (Vramp) supplied from a ramping up-down signal input terminal 17. The output of the multiplier 14 is outputted as an envelope control signal (Vcont). The operation of the transmitter shown in Fig. 1 is explained according to the timing chart in Fig. 2. In Fig. 2, the period t0-t1 is a period for stabilizing the mean voltage of Vdetb, the period t1-t2 is a transmission signal rise time, the period t2-t3 is a modulation data transmission time, and the period t3-t4 is a transmission signal fall time. First, the operation in the period t0-t1 is explained. In this period, the modulation carrier signal supplied from the modulation carrier signal input terminal 1 is supposed to be a signal without amplitude variation. The sample hold signal (Sh) is supposed to be a sample signal. The ramping up-down signal (Vramp) is supposed to be 0 V. The reference voltage (Vref) is supposed to be a DC voltage determined depending on the transmission output power. The linear amplifier 9 and envelope detector 10 in the envelope control signal generator 6, the error amplifier 11 and the sample hold circuit 12 compose a first feedback loop, and it is controlled so that the voltage of Vdetb may be nearly equal to the voltage of Vref. On the other hand, in the multiplier 14, since Vdetb and Vramp(=0V) are multiplied, the output is 0 V. The power amplifier 2, monitor circuit 3, envelope detector 5, and error amplifier 7 compose a second feedback loop, and the output transmission signal is controlled by the output Vcont(=0V) of the envelope control signal generator 6. At time t1, the sample hold signal (Sh) becomes a hold signal, and the sample hold circuit 12 retains the control voltage for controlling the gain control terminal 13, thereby keeping constant the mean voltage of Vdetb thereafter. Between t1 and t2, (Vramp) rises gradually, and Vcont, or the output of the multiplier 14, rises gradually, so that the transmission signal rises gradually. Between t2 and t3, the modulation carrier signal is a modulated signal, and a distortion-free envelope signal is delivered from the envelope control signal generator 6. The second feedback loop is controlled by this distortion-free envelope signal, so that a distortion-free transmission signal is generated. Between t3 and t4, by the reverse sequence to that in t1-t2, the transmission signal falls gradually. It is demanded here that the power amplifier 2 should be small in phase fluctuation near the saturation point where the motion is nonlinear, which is realized by optimizing the output load impedance of the transistor in the power amplifier 2. It is also required that the power amplifier 2 should be small in phase fluctuation against changes of the control voltage supplied to the gain control terminal 8. This is known to be realized by controlling the drain voltage or collector voltage of the transistor in the power amplifier 2. It is also realized by using and controlling the second gate of a dual gate MOS-FET in the power amplifier 2. A constitutional example of the power amplifier 2 is shown in Fig. 3(a). In Fig. 3(a), numeral 201 is a final stage amplifier, 202 is a Younger amplifier, 203 is a GaAs FET (field-effect transistor) for composing the final stage amplifier 201, 204 and 205 are an input matching network and an output matching network of the final stage amplifier 201, and 206 is a choke coil connected to the drain of the GaAs FET 103. The other end of the choke coil is connected to the gain control terminal 8. The characteristic of the final stage amplifier 201 varies with the output matching network 205. The characteristic of the final stage amplifier 201 when the impedance of the output matching network 205 as seen from the GaAs FET 203 side is changed as shown in Fig. 3(b) is shown in Fig. 3(c). In Fig. 3(c), Pin denotes an input power, Pout is an output power, η add is the addition power efficiency, and Phase is the phase difference between the input and output. When the impedance of the output matching network is No. 1, the transmission output is maximum, and when No. 2, the addition power efficiency is maximum, and when No. 3, the phase change is minimum. By setting the impedance to No. 3, the phase fluctuation may be reduced also in the vicinity of the saturation point. By controlling the drain of the GaAs FET 203 through the choke coil 206 from the gain control terminal 8, the gain is changed by varying the saturated power of the GaAs FET 203. It is the characteristic of the GaAs FET that the phase change is small when controlled at the saturation point, and it is possible to realize the power amplifier 2 small in phase change even against the change of the control voltage supplied to the gain control terminal 8. Fig. 4(a) shows another constitutional example of the power amplifier 2. In Fig. 4(a), numeral 201 is a final stage amplifier, 202 is a Younger amplifier, 207 is a dual gate MOS FET for composing the Younger amplifier 202, 208 and 209 are an input matching network and an output matching network of the Younger amplifier 202, and 210 is a choke coil connected to the second gate of the dual gate MOS FET 207. The other end of the choke coil is connected to the gain control terminal 8. The characteristic of the Younger amplifier 202 is shown in Fig. 4(b). In Fig. 4(b), VG2 is a voltage supplied to the second gate, Gain is the power gain, and Phase is the phase difference between the input and output. While VG2 is in a range of 1 to 4 V, there is almost no phase fluctuation. That is, by controlling the second gate of the dual MOS FET 207 through the choke coil 210 from the gain control terminal 8 by setting the operation point in a range of 1 to 4 V, the power amplifier 2 of small phase change may be realized. Fig. 5 shows a constitutional example of the envelope detectors 5 and 10. In Fig. 5, numerals 501, 1001 are detector diodes, 502, 1002 are capacitors for bypassing the modulation carrier signal, 503, 1003 are bias resistors, 504, 1004 are load resistors, and 505 and 1005 are high frequency grounding capacitors. By composing the envelope detector 5 and the envelope detector 10 in identical circuit composition and matching the characteristics of the two, the nonlinearities of the detector diodes 501 and 1001 become identical, and they function so as to compensate for each other. The both characteristics may be matched further well by disposing the detector diodes 501 and 1001 on a same semiconductor chip, so that they act to cancel each other even against the changes of characteristics due to temperature. The multiplier 14 may be composed of an ordinary analog multiplier if Vdatb and Vramp are analog signals. If, however, Vramp is a digital signal, the multiplier 14 may be composed by using a D/A converter. Fig. 6 is a constitutional example of the multiplier 14 using a D/A converter. In Fig. 6, numeral 1401 is a D/A converter, 1403 is a reference voltage terminal of the D/A converter 1401, and 1402 is a low pass filter for removing the sampling clock from the output of the D/A converter 1401. Supposing the reference voltage terminal 1403 of the D/A converter 1401 to be an input terminal of Vdetb and that the D/A converter 1401 be an N-bit D/A converter, when the digital signal Vramp is set at 2 K , the output of the D/A converter 1401 will be Vdetb x (2 K /2 N ). Thus, by composing the multiplier 14 with the D/A converter 1401 and LPF 1402 and controlling with the digital signal Vramp, a signal of high precision not obtained in the analog multiplier may be generated. In this embodiment, hence, by using the power amplifier 2 of small phase changes and controlling the second feedback loop with the distortion-free envelope control signal which is the output of the envelope control signal generator 6, a distortion-free transmission output may be generated. Furthermore, by composing the envelope detectors 5, 6 in the same circuit construction to match their characteristics, the distortion generated in the envelope detector may be canceled. Besides, the signal Vdetb controls the first feedback loop by Vref between t0 and t1 in order to stabilize the mean voltage, so that the output level of the transmission signal is stabilized. Moreover, by multiplying Vdetb and Vramp by the multiplier 14, a burst transmission signal smooth in rise and fall is realized, and unnecessary spread of the signal in the frequency region due to rise or fall characteristics of the burst transmission signal is reduced.

Claims: A transmitter comprising: a power amplifier (2) having a gain control terminal for amplifying an input modulation carrier signal to obtain a transmission signal; a transmission monitor circuit (3) for picking up a part of the transmission signal from the power amplifier (2) as a monitor signal; a first detector (5) for detecting an envelope of the monitor signal to obtain a transmission envelope signal; an envelope control signal generating means (6) for generating an envelope control signal from the input modulation carrier signal; and a first error detector (7) for comparing the envelope control signal and the transmission envelope signal to generate a first error signal, and for supplying the first error signal to the gain control terminal of the power amplifier (2), thereby controlling a gain of the power amplifier; characterized in that said envelope generating means (6) comprises: a linear amplifier (9) having a gain control terminal for linearly amplifying the input modulation carrier signal; a second detector (10) for detecting an envelope of the modulation carrier signal amplified by the linear amplifier (9) to obtain a reference envelope signal; a second error detector (11) for comparing the reference envelope signal with a reference voltage to generate a second error signal; a sample and hold circuit (12) connected to the second error detector (11) for sampling and holding the second error signal with an externally supplied sample and hold signal, and for supplying its output to the gain control terminal of the linear amplifier (9) to control a gain of the linear amplifier; an envelope control signal generator (14) connected to the second detector (10) for multiplying the reference envelope signal by an externally supplied burst control signal, and for delivering a burst-form reference envelope signal as an envelope control signal. A transmitter of Claim 1, wherein the power amplifier (2) possesses a small phase distortion characteristic. A transmitter of Claim 1, wherein the power amplifier (2) comprises a transistor of emitter grounding or source grounding, a collector or a drain of the transistor being connected to the gain control terminal. A transmitter of Claim 1, wherein a Younger stage of the power amplifier (2) comprises a source-grounded dual gate MOS FET, a second gate of the dual gate MOS FET being connected to the gain control terminal. A transmitter of Claim 1, wherein the first detector (5) for generating the transmission envelope signal and the second detector (10) for generating the reference envelope signal are identical circuits, and matched in characteristics. A transmitter of Claim 1, wherein the multiplier (14) comprises a D/A converter and a low pass filter, and the reference envelope signal is fed into a reference voltage terminal of the D/A converter, and is controlled by the burst control signal of digital signal.

Inventors: KOSUGI HIROAKI, KOSUGI, HIROAKI
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1991
Main classification: H04B1
IPC codes: H04L27, H03F1, H03G3, H04B1