Process for forming semiconductor device isolation regions

Abstract: A process for forming a semiconductor device isolation region which comprises: a) forming on a silicon substrate at least a first thin silicon oxide film and a first silicon nitride film thereon, b) etching the substrate using a resist pattern to form a trench for providing an isolation region, c) forming a second silicon oxide film and a second silicon nitride film on the side walls and bottom wall of the trench, d) subsequently forming a first polycrystalline silicon film on the substrate including the trench, leaving the first polycrystalline silicon film only on the side walls of the trench by anisotropic etching and thereafter oxidizing the remaining first polycrystalline silicon film to form an oxide film on the side walls of the trench, and e) further forming a second polycrystalline silicon film over the semiconductor substrate including the trench, leaving the second polycrystalline silicon film only between the oxide film portions on the side walls of the trench by anisotropic etching and thereafter oxidizing the remaining second polycrystalline silicon film to thereby form an oxide film.

Description: The present invention relates to a process for forming isolation regions for electrically isolating devices constituting semiconductor integrated circuits, and more particularly to a process for forming trench isolation regions by forming device isolation trenches in a semiconductor substrate and refilling the trenches with an insulation film. The packing density, for example, of DRAMs (dynamic random access memories) has increased approximately at a rate of fourfold every three years, and with this trend, the minimum line width of circuits has decreased by about 60% to 70% from generation to generation. Consequently, 1 Mb DRAM and 4 Mb DRAM presently made available by mass production are 1.2µm and 0.8µm, respectively, in minimum line width. Further 16 Mb DRAMs which have yet to be produced in quantities are 0.6 to 0.5µm in minimum line width. 64 Mb DRAMs to be developed in the future will be 0.4 to 0.3µm in minimum line width. With semiconductor devices thus made more microscopic, the isolation regions for isolating the devices from one another have become gradually narrower. In minimum isolation width, 4 Mb DRAMs are 1.0 to 0.8 µm, 16 Mb DRAMs are 0.8 to 0.6 µm, and 64 Mb DRAMS will be reduced to 0.5 to 0.4 µm. The device isolation regions having a width of at least 0.6 µm can be formed by local oxidation of silicon isolation (LOCOS process) or improved LOCOS process. The LOCOS process is such that a silicon nitride film covering a silicon substrate is apertured by patterning, and the exposed silicon substrate surface is selectively oxidized to form a silicon oxide film serving as an insulation film. For the following reason, however, the LOCOS process is unable to form isolation regions of up to 0.5 µm. Unless the oxide film on the isolation regions is made extremely thin, the LOCOS process permits oxidation of the silicon substrate to progress to regions covered with the silicon nitride film to result in side-wise extensions of silicon oxide film called bird's beaks. Thus, the isolation regions spread out beyond the mask size, making it impossible to form narrow isolation regions. As an alternative to the LOCOS process, the so-called trench isolation process has been proposed. With this process, a resist pattern formed by lithography is used as an etching mask to form recessed trenches in a silicon substrate, and the trenches are filled up with an insulator such as a silicon oxide film. Fig. 3 is a diagram showing the conventional trench isolation process, which will be described with reference to Fig. 3. (1) First, a thin oxide film 44 is formed over the surface of a silicon substrate 41, a polycrystalline silicon film 45 is thereafter deposited on the film, and the portions 42, 43 to be made into isolation regions are etched by reactive ion etching to form a trench 42 of small width and a trench 43 of large width (Fig. 3,(a)). (2) Next, the inside of the trenches 42, 43 is cleaned, the surface is oxidized to form a thin oxide film 46 and subsequently coated with a thin silicon nitride film 47, and a silicon oxide film 48 of a thickness approximately corresponding to the depth of the trenches is deposited on the nitride film to fill up the trenches. This step produces a higher step 49 around the wide isolation region 43 (Fig. 3, (b)). (3) A dummy resist layer 50 is then formed on the wide isolation region 43 so that the silicon oxide film 48 will not be removed from this region 43 when the silicon oxide film 48 is removed from the active regions for forming transistors. After the dummy resist layer 50 has been formed, polyimide resin 51 is coated on the surface to fill up the space between the dummy resist layer 50 and the step 49 to form a planar surface (Fig. 3, (c)). (4) Next, to remove the polyimide resin 51 and the oxide film 48 on the active regions, the entire surface is etched by reactive etching at equal rates for the polyimide resin, the resist resin material and the oxide film. The etching is stopped upon the polycrystalline silicon film 45 appearing on the surface (Fig. 3, (d)). (5) The polycrystalline silicon film 45 is etched away, the surface is cleaned and the oxide film 44 is further removed with hydrofluoric acid, followed by a transistor forming process (Fig. 3, (e)). Thus, the use of the trench isolation process forms trench regions which only serve as the isolation regions, so that the isolation width can be reduced to a value limited by lithography. The trench isolation process is therefore suitable for isolating the devices of semiconductor integrated circuits of increased packing densities. In the conventional trench isolation process described above, however, the oxide film 48 deposited in the step (2) is as thick as about 1 µm. In order to fill the trenches completely, there is a need to resort to the LP CVD (Low Pressure Vapour Deposition) process with good step coverage. This method nevertheless has the drawbacks of being low in film deposition rate and poor in throughput. Further, in the case that the total thickness of the resin film and the oxide film is about 2 microns, the oxide film will be overetched by 800 angstroms at portions where the etching proceeds at the highest rate, even if the in-plane uniformity of the equal-rate etching condition for the resin film and the oxide film is within ±2%. Accordingly, unless the rate of etching of the polycrystalline silicon film 45 is very small under the equal-rate etching condition, the active regions are also etched and thereby damaged. Even if the etching is stopped at the polycrystalline silicon film 45 as desired, a distinct step with a height of about 800 angstroms will occur between the isolation region and the active region. When the surface of the oxide film within the trench is lower than the silicon surface in the active region, an electric field will be concentrated at the edge of the active region since the wiring for the gate electrode is so provided as to cover the corner position of the active region. This field concentration gives rise to the problem that a leak current occurs in the subthreshold region of the transistor. Further as shown in Fig. 3, (e), the treatment with hydrofluoric acid creates a wedgelike minute ditch 52 in the centre of the trench 42 with a large aspect ratio. Usually the formation of the isolation regions is followed by the formation of the gate insulation film and gate electrode wiring for MOS transistors. The presence of the minute ditch 52 in the isolation region entails the problem of a break in the wiring, or a short circuit between the wirings, which would occur if the wiring material remains in the minute ditch. The known references on semiconductor device isolation technology include: 1. "A NEW TRENCH ISOLATION TECHNOLOGY AS A REPLACEMENT OF LOCOS" H. Mikoshiba, T. Homma and K. Hamano IEDM Technical Digest, 1984 P 578 - 581 2. "A PRACTICAL TRENCH ISOLATION TECHNOLOGY WITH A NOVEL PLANARIZATION PROCESS" G. Fuse et al. IEDM Technical Digest, 1987 P 732 - 735 3. "BURIED-OXIDE ISOLATION WITH ETCH-STOP (BOXES)" Robert F. Kwasnick et al. IEEE ELECTRON DEVICE LETTERS. Vol. 9, No. 2 February 1988, pages 62-64 4. IBM Technical Disclosure Bulletin Vol. 23, No. 11 April 1981, pages 4917-4919 5. IBM Technical Disclosure Bulletin Vol 24, No. 7A December 1981, pages 3389-3392 6. "PROCESS HE: A HIGHLY ADVANCED TRENCH ISOLATED BIPOLAR TECHNOLOGY FOR ANALOGUE AND DIGITAL APPLICATIONS" P.C. Hunt and M.P. Cooke Proceedings of the IEEE 1988 Custom Integrated Circuits Conference, 16-19 May 1988, pages 22.2/1-4 The latter reference describes a process for forming narrow and wide device isolation regions, in which a narrow trench is filled with polysilicon whose upper portion is oxidised simultaneously with the formation of a field oxide in the wide isolation region. A process of trench sidewall isolation by polysilicon oxidation, according to the preamble of claim 1, is known from US-A-4,666,556. The present invention is concerned with the problems peculiar to the conventional trench isolation process, such as impairment of electrical characteristics due to etching damage, impairment of transistor characteristics due to a step produced on a border between an active region and isolation region, or short circuits between the wirings due to a minute ditch produced in the centre of an isolation region, and aims to provide a relatively simple isolation process with trench isolation technology, which is suitable for semiconductor integrated circuits with increased packing density. In accordance with the invention, a process for forming semiconductor device isolation regions comprises the features of claim 1. Thus, the LOCOS oxidation for wide isolation regions is done at the same time as the second polycrystalline silicon oxidation. Unlike the conventional process, the process of the present invention does not include the step of depositing a thick oxide film and etching back the oxide film. Therefore, the present process is free from the damage of the active region and steps between the active region and the device isolation region, which are induced by overetching. In accordance with the invention, the first polycrystalline silicon film has a thickness (for example, about 0.1µm) corresponding to about one-fourth of a minimum trench width. The second polycrystalline silicon film may have a thickness of about one-half of the depth of the trench. Such thin polycrystalline silicon films can be etched under conditions with a large selectivity relative to the underlying oxide film and nitride film. This remarkably diminishes the likelihood of causing damage to the active region and eliminates a large step at the boundary between the active region and the trench, consequently precluding the impairment of the electrical characteristics and the impairment of the transistor threshold characteristics. Furthermore as stated above, the first and second polycrystalline silicon films are much thinner than the 1µm-thick oxide film used in the conventional trench isolation process, so that the silicon films can be deposited within a short time to achieve an improved throughput. Since the oxide films inside the trench are not formed by deposition, no minute ditch appears at the centre of the trench. This prevents short circuits between the wirings due to such a ditch. Two embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which: Fig. 1 is a process diagram showing a first embodiment of the present invention; Fig. 2 is a process diagram showing a second embodiment of the invention; and Fig. 3 is a diagram illustrating the conventional trench isolation process. Fig. 1 is a process diagram showing a first embodiment of the invention for forming device isolation regions. The embodiment will be described below with reference to Fig. 1. The following steps (a), (b), (c), (d), (e), (f), (g) and (h) correspond to Fig. 1, (a), (b), (c), (d), (e), (f), (g) and (h), respectively. (a) A p-type silicon substrate 1 is oxidized to form a thin oxide film 2 on the substrate surface, a silicon nitride film 3 is then deposited on the film 2, and a silicon oxide film 4 is thereafter deposited on the film 3 by the CVD process. Subsequently, a resist pattern (not shown) of isolation regions is formed by stepper (aligner). Using the pattern as a mask, the superposed films 2, 3 and 4 are removed by reactive ion etching. After removing the resist pattern, the silicon substrate 1 is treated by reactive ion etching with the pattern of oxide film 4 serving as a mask to form a trench 5 which is 0.5 to 1.0 µm in width and 0.6 µm in depth. Although the mask of oxide film 4 is used for etching the silicon substrate in the present step, the substrate may be etched with use of the resist pattern as the mask in the absence of the oxide film 4. (b) The inside of the trench 5 is cleaned with an acid, the oxide film 4 is then etched away, and the inside of the trench is oxidized with a mixed gas of hydrochloric acid and oxygen. A thin oxide film formed by the oxidation treatment is etched away, and the inside of the trench is oxidized again to form a thin oxide film 6 again. A thin silicon nitride film 7 is further formed on the film 6 by LP CVD. The silicon nitride film 7 serves to prevent the oxidation of the inside walls of the trench in a later oxidation step. (c) Next, a polycrystalline silicon film with 0.1 µm in thickness is deposited by LP CVD. The entire surface of the film is subjected to a reactive ion etching process with anisotropic characteristics and a large selectivity relative to the silicon nitride film in order to leave the polycrystalline silicon film 8 only on the side walls of the trench 5. The polycrystalline silicon film has a thickness that provides an oxide film, by complete oxidation, having a thickness approximately one-half of the minimum width of trenches. Since a silicon film gives an oxide film with a thickness approximately twice the original silicon film thickness by oxidation, the thickness of the polycrystalline silicon film is about one-fourth of the minimum-trench width. (d) Next, the polycrystalline silicon film 8 is oxidized in a wet ambient at 1050°C to form an oxide film 9 on the inner side walls of the trenches. Consequently, there remains a groove 10 between the oxide film portions 9, 9. The groove 10 is narrow in the case where the trench has a small width, and is relatively wide in the case where the trench has a large width. The surface of the silicon substrate 1 is protected by the silicon nitride films 3 and 7 and therefore remains unoxidized in the present step. (e) To fill up the groove 10 remaining at the centre of the trench 5, a polycrystalline silicon film with a thickness of 0.3µm is deposited again and is etched back in the same manner as in the step (c) to fill the polycrystalline silicon 11 in the groove 10. The thickness of the polycrystalline silicon film deposited in this step is preferably larger than one-half of the width of the groove 10 in the trench of the largest width. (f) To oxidize the surface of the polycrystalline silicon in the trench 5 and to form a wide device isolation region 12 by local oxidation at the same time, the silicon nitride film 3 on the region 12 is etched off. (g) Then, wet oxidation at an oxidation temperature of 1050°C or above follows to grow an oxide film 13 on the surface of the polycrystalline silicon 11 in the groove 10 and to form a wide isolation region 14. According to the present embodiment, the LOCOS process is thus incorporated in the steps (f) and (g) to form the wide isolation region concurrently with the oxidation of the polycrystalline silicon film, so that isolation regions of varying widths can be formed efficiently. (h) The final step removes the silicon nitride film 3 and the thin oxide film 2 to complete the device isolation regions. After the completion of the foregoing processes for forming the isolation regions, MOS transistors and other devices are formed on the surface of the silicon substrate 1 by known processes. According to the present embodiment, device isolation regions having a very small width of 0.5µm were formed. Further N-type MOS transistors (not shown) were formed, which had a channel length of 0.5 µm and isolation regions of very small width. When the transistors were tested, no increase in the junction leak current was found as compared with that of transistors separated by the conventional LOCOS process. Further, despite the isolation width of 0.5µm, the leak current of the parasitic MOS transistors was not larger than the conventional level. Additionally, the transistors operated with satisfactory characteristics despite the channel width of 0.5µm which was not available by the LOCOS process. Fig. 2 shows a process diagram of the second embodiment of the present invention. The steps of the present embodiment illustrated in Fig. 2, (a), (b), (c), (d), (e), (f), (g) and (h) correspond to the steps of Fig. 1, (a), (b), (c), (d), (e), (f), (g) and (h), respectively, with the exception of the following feature. Therefore, a detailed description will not be given. The present embodiment employs the polycrystalline silicon pad LOCOS process which is an improvement of the LOCOS process, and in this respect, the embodiment differs from the first embodiment. In connection with the use of the polycrystalline silicon pad LOCOS process, a polycrystalline silicon film 21 serving as a pad is formed between the thin oxide film 2 and the nitride film 3 in the step (a). The second embodiment has the same advantages as the first embodiment. As will be apparent from the above description, the process of the present invention does not include the steps, peculiar to the conventional trench isolation process, of depositing a thick oxide film and etching back the thick film. So, the present process is therefore free from damage of the active region and steps at the boundary between the active region and the trench isolation region, which are induced by overetching. This precludes impairment of the electrical characteristics due to etching damage to the active region and impairment of the device characteristics due to imperfect flatness. Furthermore, the first and second polycrystalline silicon films are thinner than the 1 µm-thick oxide film used in the conventional trench isolation process. The film deposition time can therefore be shorter to achieve an improved throughput. Further, according to the present invention, polycrystalline silicon is buried in the trench and then oxidized to form an oxide film in the trench. This method obviates a minute ditch at the centre of the trench, which is inevitable with CVD-oxide film filled in trench. Consequently, the method prevents short circuits between the wirings. Accordingly, when integrated circuits are fabricated using the process of the present invention, the semiconductor devices can be insulated and isolated satisfactorily by very small isolation regions, so that the present process contributes to great improvement in the packing density and provides integrated circuits with high yield and high reliability. Further, according to the present invention, wide isolation regions are oxidized by the LOCOS process concurrently with the oxidation of the polycrystalline silicon film. This leads to the advantage that device isolation regions with varying widths can be formed efficiently.

Claims: A process for forming semiconductor device isolation regions which comprises: a) forming on a silicon substrate (1) a first thin silicon oxide film (2) and a first silicon nitride film (3) thereon, and forming an opening through said first silicon oxide and silicon nitride films, b) etching the substrate using a mask (4) through said opening to form a trench (5) for providing a first isolation region, c) forming a second silicon oxide film (6) and a second silicon nitride film (7) on the side walls and bottom wall of the trench, d) subsequently forming a first polycrystalline silicon film on the substrate including the trench, leaving the first polycrystalline silicon film (8) only on the side walls of the trench by anisotropic etching, and thereafter oxidizing the remaining first polycrystalline silicon film to form an oxide film (9) on the side walls of the trench, and e) further forming a second polycrystalline silicon film over the semiconductor substrate including the trench, leaving the second polycrystalline silicon film (11) only between the oxide film portions (9) on the side walls of the trench, characterised in that in the step d) the thickness of the first polycrystalline silicon film (8) is about one-fourth of a minimum width of the trench (5), and by the steps of: f) etching a part of said first silicon nitride film (3), remote from said trench, for providing a second isolation region (12) of said silicon substrate, and g) simultaneously oxidizing the surface of the remaining second polycrystalline silicon film (11) and the substrate under the etched part (12) of the first silicon nitride film (3), to form respective oxide films (13, 14). A process according to claim 1, in which, in the step (a), the first thin silicon oxide film (2) is formed by oxidizing the silicon substrate and a silicon oxide film (4) is further formed on the first silicon nitride film (3) by a CVD method. A process according to claim 2, in which, in the step (a), a polycrystalline silicon film (21) is further formed between the first thin silicon oxide film (2) and the first silicon nitride film (3). A process according to any one of claims 1 to 3, in which the second silicon nitride film (7) of the step (c) is formed by a LP CVD method. A process according to any one of the preceding claims, in which the thickness of the second polycrystalline silicon film (11) of the step (e) is one-half or more of a maximum width between the oxide film portions (9) on the side walls of the trench (5).

Inventors: IGUCHI KATSUJI, IGUCHI, KATSUJI
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1991
Main classification: H01L21
IPC codes: H01L21, H01L27