A column electrode driving circuit for a display apparatus

Abstract: The column electrode driving circuit is suitable for driving a display apparatus which has a delta arrangement display unit. The video signals for two rows in the display unit are sampled simultaneously by two sample-hold circuits with sampling timings which differ mutually by one-half of the sampling period. The outputs of the two sample-hold circuits are alternatingly supplied to column electrodes of the display unit.

Description: BACKGROUND OF THE INVENTION This invention relates to a column electrode driving circuit for a display apparatus, and more particularly it relates to a column electrode driving circuit for a matrix type display apparatus such as a liquid crystal display (LCD) apparatus. An LCD apparatus as shown in Figure 11 has been proposed as a matrix type display apparatus. The LCD apparatus of Figure 11 comprises a liquid crystal panel 110 in which pixel electrodes 113 are arranged in a matrix, a row electrode driving circuit 115 , a column electrode driving circuit 116 , and a control circuit 117 . The liquid crystal panel 110 comprises two opposing substrates, one of which has a plurality of row electrodes 111 and a plurality of column electrodes 112 intersecting the row electrodes 111 . At each of the intersections of the row electrodes 111 and column electrodes 112 , a transistor 114 is provided for applying a video signal to one of the pixel electrodes 113 through the corresponding column electrode 112 . Namely, a plurality of the pixel electrodes 113 constituting one column are connected to one column electrode 112 . The row electrode driving circuit 115 sequentially supplies scanning pulses to the row electrodes 111 , and the column electrode driving circuit 116 supplies a video signal which is a voltage signal to be applied to the pixel electrodes 113 , to the column electrodes 112 . When the row electrode driving circuit 115 supplies a scanning pulse to a certain row electrode 111 , the transistors 114 the gates of which are connected to that row electrode 111 are turned ON, and video signals on the column electrodes 112 are transmitted to the pixel electrodes 113 connected to the transistors 114 in ON state. The operation of the row electrode driving circuit 115 and column electrode driving circuit 116 is controlled by the control circuit 117 . A matrix type LCD apparatus such as that shown in Figure 11 in which every pixel is provided with a transistor 114 is capable of displaying images in high contrast by means of the switching function of the transistors 114 even in cases in which multiplex drive of a plurality of row electrodes 111 is performed, and therefore it is widely used as a display unit in a portable electronic apparatus and many other electronic apparatus. Figure 12 shows a configuration which has been proposed for the column electrode driving circuit 116 . The column electrode driving circuit 116 simultaneously processes video signals for two rows of the pixel electrodes 113 (i.e., two rows of pixels), and comprises a shift register 121 , two sample-hold circuits 122A and 122B , and two output buffer circuits 123A and 123B . In the shift register 121 , a sampling signal S input from an external unit is shifted in accordance with a clock signal  so that sampling signals q 1 , q 2 , ..., q n are sequentially output. The sample-hold circuit 122A samples and holds the voltage component of a video signal V A on the basis of the sampling signals q 1 to q n , and outputs voltage signals QA 1 to QA n . The other sample-hold circuit 122B samples and holds the voltage component of a video signal V B on the basis of the sampling signals q 1 to q n , and outputs voltage signals QB 1 to QB n . Each of the voltage signals QA 1 to QA n and QB 1 to QB n has a level which is substantially equal to the respective voltage level held in the circuits 122A and 122B . The output buffer circuit 123A takes in the voltage signals QA 1 to QA n according to an output pulse T , and outputs them in parallel to the column electrodes 112 during the period the level of a selection signal U is positive. In contrast, the output buffer circuit 123B takes in the voltage signals QB 1 to QB n according to the output pulse T , and outputs them in parallel to the column electrodes 112 during the period the level of the selection signal U is negative. The operation of the column electrode driving circuit 116 will be described with reference to Figure 13. The video signals V A and V B are both input serially. In the ith sampling period, at the timing the sampling signals q 1 , ..., q j , ..., q n are output from the shift register 121, the voltage components V Ai,1 , ..., V Ai,j , ..., V Ai,n of the video signal V A are sampled and held by the sample-hold circuit 122A . In the same sampling period, the voltage components V Bi,1 , ..., V Bi,j , ..., V Bi,n of the video signal V B are sampled and held by the sample-hold circuit 122B . The sample-hold circuit 122A outputs the voltage signals QA j (j = 1 to n) based on the held voltage V Ai,j (j = 1 to n ), and these voltage signals are output from the output buffer circuit 123A as the voltage signal Q j during the period the selection signal U in the first half of the next (i+1)th sampling period is positive. The sample-hold circuit 122B outputs the voltage signals QB j (j = 1 to n) based on the held voltage V Bi,j (j =- 1 to n), and these voltage signals are output from the output buffer circuit 123B as the voltage signal Q j during the period the selection signal U in the last half of the (i+1)th sampling period is negative. In the column electrode driving circuit 116, the video signals for two rows of the pixel electrodes 113 are sampled simultaneously. Therefore, by supplying a video signal belonging to odd fields to the column electrode driving circuit 116 as the video signal V A and supplying a video signal belonging to even fields to the column electrode driving circuit 116 as the video signal V B , a display system which receives a video signal for the non-interlace scanning and uses a field memory to perform the double-speed non-interlaced display can be easily realized without increasing the frequency of the video signal. Figure 14 shows another LCD apparatus having a liquid crystal panel 140 in which the pixel electrodes 113 are formed into a so-called delta arrangement. More specifically, the positions of the pixel electrodes 113 in one row are shifted along the row direction by one-half pixel from those of the pixel electrodes in the adjacent rows. In displaying images based on a television signal, the LCD apparatus of Figure 14 having pixel electrodes with a delta arrangement is superior in display quality to the LCD apparatus of Figure 12 with a conventional arrangement of the pixel electrodes, provided that the numbers of the pixel electrodes in both the apparatus are equal to each other. However, in the proposed column electrode driving circuit 116 described above, the two sample hold circuits 122A and 122B sample a video signal with the same sampling timing, and therefore a condition in which the sampling timing of a video signal does not conform with the position of the pixel electrode corresponding to the sampled video signal occurs every other row of the pixel electrodes 113 . This causes the degradation of the display quality. For this reason, the column electrode driving circuit 116 would not be suitable for driving a delta-arrangement display unit such as the panel 140 . A device for driving a delta arrangement display unit and having double-speed conversion means is disclosed in EP-A-0 441 661. JP-A-2-83584 discloses a drive circuit for a matrix-type display in which red, green and blue pixel electrodes are formed in a delta arrangement. A circuit including a shift register generates output pulses having an interval corresponding to a half-pixel pitch. Each adjacent pair of the output pulses is coupled to a respective column electrode of the display via a group of four gates, a group of four sample-hold circuits and a group of four analogue switches, the sample-hold circuits also receiving the red, green or blue video signal appropriate to the column electrode in question. In one horizontal scanning period, the pair of output pulses are supplied via respective gates to the corresponding sample-hold circuits. Two samples of the video signal differing in timing by a half-pixel are thereby stored. In the following horizontal scanning period, the two samples are sequentially released to the column electrode, via the corresponding analogue switches, in synchronism with the respective scannings of two adjacent pixel rows. In the same horizontal scanning period, two further samples of the video signal are stored by means of the two other gates and sample-hold circuits of the groups of four, which were not used in the preceding horizontal scanning period. These two further samples are released in the next horizontal scanning period via the corresponding two other analogue switches. SUMMARY OF THE INVENTION This invention is defined by independent claim 1. The dependent claims 2 to 12 are directed to embodiments of the invention. The invention disclosed herein makes possible the objectives: (1) providing a column electrode driving circuit which can drive a display apparatus having a delta arrangement of pixel electrodes, with an excellent display quality; (2) providing a column electrode driving circuit which can simultaneously drive two rows of pixels in a display apparatus, without requiring the double-speed conversion; and (3) providing a column electrode driving circuit which can simultaneously drive two rows of pixels in a display apparatus, without requiring an external field memory. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a circuit diagram illustrating a first embodiment of the invention. Figure 2 is a timing chart illustrating the operation of the embodiment of Figure 1. Figure 3 is a circuit diagram illustrating a second embodiment of the invention. Figure 4 is a timing chart illustrating signals input to the embodiment of Figure 3. Figures 5-7 illustrate the principal portions of third to fifth embodiments of the invention, respectively. Figure 8 is a circuit diagram illustrating a sixth embodiment of the invention. Figure 9 is a timing chart illustrating the operation of the embodiment of Figure 8. Figure 10 is a timing chart illustrating the other possible operation of the embodiment of Figure 8. Figure 11 diagrammatically illustrates a conventional LCD apparatus. Figure 12 is a circuit diagram illustrating a column electrode driving circuit used in the LCD apparatus of Figure 11. Figure 13 is a timing chart illustrating the operation of the circuit of Figure 12. Figure 14 diagrammatically illustrates a conventional LCD apparatus with a delta-arrangement. DESCRIPTION OF THE PREFERRED EMBODIMENTS Figure 1 shows a column electrode driving circuit according to the invention. The column electrode driving circuit 10 shown in Figure 1 drives the liquid crystal panel 140 (Figure 14) with a delta arrangement, and comprises a shift register 11, two sample-hold circuits 12A and 12B , and two output buffer circuits 13A and 13B . The number of the stages (2n stages) of the shift register 11 is twice that (n stages) of the shift register 121 shown in Figure 12, i.e., twice the number of column electrodes 112 of the liquid crystal panel 140 . The shift register 11 shifts a sampling signal S in accordance with a clock signal  D having a frequency twice that of the clock  for the shift register 121 , and sequentially outputs sampling signals q 1 , q 2 , ..., q 2n . The sample-hold circuits 12A and 12B have the same configuration as the sample-hold circuits 122A and 122B , but the sample-hold circuit 12A samples and holds the voltage component of the video signal V A in accordance with the odd sampling signals q 1 , q 3 , ..., q 2n-1 output from the shift register 11 , while the sample-hold circuit 12B samples and holds the voltage component of the video signal V B for the rows adjacent to the rows corresponding to the video signal V A in accordance with the even sampling signals q 2 , q 4 , ..., q 2n output from the shift register 11 . The output buffer circuit 13A simultaneously takes in the voltage signals QA 1 to QA n which are substantially equal to the voltage held by the sample-hold circuit 12A , in accordance with the output pulse T , and outputs them in parallel to the column electrodes 112 during the period the level of the selection signal U is positive. In contrast, the output buffer 13B simultaneously takes in the voltage signals QB 1 to QB n which are substantially equal to the voltage held by the sample-hold circuit 12B , in accordance with the output pulse T , and outputs them in parallel to the column electrodes 112 during the period the level of the selection signal U is negative. The operation of the column electrode driving circuit 10 will be described in more detail with reference to Figure 2. Both video signals V A and V B are input serially. The sample-hold circuit 12A samples the voltage components V Ai,1 , ..., V Ai,2j-1 , ..., V Ai,2n-1 (corresponding to the ith row of the pixel electrodes 113 ) of the video signal V A at the timings the odd sampling signals q 1 , ... q 2j-1 , ... q 2n-1 are output from the shift register 11 . The sample-hold circuit 12B samples the voltage components V Bi+1,2 , ..., V Bi+1,2j , ..., V Bi+1,2n (corresponding to the (i+1)th row of the pixel electrodes 113 ) of the video signal V B at the timings the even sampling signals are output from the shift register 11 . The sample-hold circuit 12A generates voltage signals QA j (j = 1 to n) based on the held voltages V Ai,2j-1 (j = 1 to n). The voltage signals QA j are output from the output buffer circuit 13A as voltage signals Q j whilst the selection signal U in the first half of the next sampling period (for the (i+2)th and (i+3)th rows) is positive. The sample-hold circuit 12B generates voltage signals QB j (j = 1 to n) based on the held voltages V Bi+1,2j (1 = 1 to n), and the voltage signals QB j are output from the output buffer circuit 13B as the voltage signals Q j whilst the selection signal U in the last half of the next sampling period is negative. Both the sampling period of the sample-hold circuit 12A and that of the sample-hold circuit 12B are one-half of the period of the clock signal  D . However, the sampling timing of the sample-hold circuit 12B is delayed behind that of the sample-hold circuit 12A by one-half of the above sampling period. According to this embodiment, therefore, the sampling of a video signal is performed in conformity with a delta arrangement, and therefore the liquid crystal panel 140 with a delta arrangement can be driven with an excellent image quality. Furthermore, video signals for two rows of pixel electrodes 113 are sampled simultaneously in one row sampling period, and the thus sampled video signals are then used to drive the column electrodes 112 in the time division manner in the next row sampling period. Therefore, the display quality equivalent to that of the double-speed conversion display can be achieved without using an external double-speed converter for a video signal. Figure 3 shows the principal components of a second embodiment of the invention. In place of the shift register 11 shown in Figure 1, this embodiment is provided with two shift registers 31A and 31B . The number (n) of stages of each of the shift registers 31A and 31B is equal to the number (n) of column electrodes 112 of the liquid crystal panel 140 . The shift register 31A receives a first clock signal  A , and a first sampling signal S A , and the shift register 31B receives a second clock signal  B , and a second sampling signal S B . The first and second clock signals  A and  B have the same frequency, but the phase of the clock signal  B is shifted from that of the clock signal  A by one-half of the clock period as shown in Figure 4. The second sampling signal S B is delayed by one pulse width from the first sampling signal S A . The shift register 31A shifts the sampling signal S A in accordance with the clock signal  A , and sequentially outputs the sampling signals qA 1 to qA n to the sample-hold circuit 12A . The shift register 31B shifts the sampling signal S B according to the clock signal  B which has the same period as the clock signal  A , and sequentially outputs the sampling signals qB 1 to qB n to the sample-hold circuit 12B . As described above, the phase of the clock signal  B differs from that of the clock signal  A by one-half of the clock period, and hence the sampling timing of the sample-hold circuit 12B differs from that of the sample-hold circuit 12A by one-half of the sampling period (equal to the clock period). Therefore, this embodiment can achieve the same results as the column electrode driving circuit 10 of Figure 1. Figure 5 shows the principal components of a third embodiment of the invention. In this embodiment, function switching circuits 54 1 to 54 n are provided at the output of the shift register 11, whereby the same operation as that of the column electrode driving circuit 116 (Figure 12) can be achieved. The function switching circuits 54 1 to 54 n are respectively provided for each combination of two sampling signals q 2j-1 and q 2j (j = 1 to n) of the sampling signals output from the shift register 11 . Each of the function switching circuits 54 1 to 54 n receives two sampling signals q 2j-1 and q 2j , and a function switching signal D , and comprises two AND gates 541 and 542 , an OR gate 543 , and an inverter 544 . The function switching circuits 54 1 to 54 n generate sampling signals q 2 ' to q 2n ' which are supplied to the sample-hold circuit 12B (Figure 1), respectively. For example, the sampling signal q 2 ' which is generated by the first function switching circuit 54 1 corresponding to the sampling signals q 1 and q 2 is equivalent to the sampling signal q 1 when the function switching signal D is HIGH, and is equivalent to the sampling signal q 2 when the function switching signal D is LOW. In other words, when the function switching signal D is HIGH, this embodiment functions in the same manner as the column electrode driving circuit 116 (Figure 12), and when the function switching signal D is LOW, this embodiment functions in the same manner as the column electrode driving circuit 10 of Figure 1. Figure 6 shows the principal parts of a fourth embodiment of the invention. In this embodiment, the sample-hold circuits 12A and 12B sample the same input video signal V . According to this embodiment, the sampling timings of the two sample-hold circuits 12A and 12B differ by one-half of the sampling period, and therefore the number of the sampling points for the video signal V is twice as compared that in the column electrode driving circuit 116 (Figure 12). The writing is performed at double speed in this way for two rows of pixels in a liquid crystal panel with a delta arrangement, based on the sampled video signal, resulting in that resolution is improved and slanted lines are displayed linearly. As described above, according to this embodiment, it is advantageous to sample the same video signal V , while there is no advantage for the two sample-hold circuits 122A and 122B to sample the same video signal in the column electrode driving circuit 116 (Figure 12). Figure 7 shows the principal parts of a fifth embodiment of the invention. The fifth embodiment is provided with an output buffer circuit 73 which comprises holding sections 731A and 731B , selection sections 732A and 732B and a common buffer section 733 for the signals from the sample-hold circuits 12A and 12B . In accordance with the output pulse T , the holding section 731A holds the voltage signals QA 1 to QA n transmitted from the sample-hold circuit 12A , and the holding section 731B holds the voltage signals QB 1 to QB n transmitted from the sample-hold circuit 12B . The selection section 732A transmits the signals held by the holding section 731A to the buffer section 733 when the selection signal U is positive. The selection section 732B transmits the signals held by the holding section 731B to the buffer section 733 when the selection signal U is negative. A sixth embodiment of the invention is shown in Figure 8. This embodiment has two shift registers 81A and 81B each of which comprises D-type flip-flops 811 connected in series. The sampling signal S is supplied to the D input of the first D-type flip-flops 811 of the shift registers 81A and 81B . A clock signal  with a duty ratio of 50% is supplied to the CK input of the D-type flip-flops of the shift register 81A . The output of an XOR gate 87 to which the clock signal  and a function selection signal D are input is supplied to the CK input of the D-type flip-flops of the other shift register 81B . When the function selection signal D is LOW, the same clock signal is supplied to both the shift registers 81A and 81B , so that this embodiment functions in the same manner as the column electrode driving circuit 116 (Figure 12). When the function selection signal D is HIGH, the output of the XOR gate 87 inverts the clock signal , so that the timing of the output of the sampling signals qB 1 , ··· from the shift register 81B is shifted by one-half of the clock period ts (i.e., ts/2) which is equal to the sampling period, from the timing of the output of the sampling signals qA 1 , ··· of the shift register 81A , thus causing this embodiment to operate in the same manner as the first embodiment. Like the signals qA 1 ' and qB 1 ' shown in Figure 10, the sampling signals output from the shift registers 81A and 81B may have a pulse width longer than the sampling period ts, so that the sampling timing of sample-hold circuits 82A and 82B (which will be described below) can be shifted one-half of the sampling period (i.e., ts/2). The sample-hold circuit 82A comprises analog switches 821 and sampling capacitors 822 . The analog switches 821 close according to the corresponding sampling signal from the shift register 81A , thereby supplying the input video signal V A to the sampling capacitor 822 . If the time required to charge the sampling capacitor 822 is sufficiently shorter than the sampling period ts, then the voltage of the video signal V A at the fall edge of each of the sampling signals qA 1 , ··· is held in the corresponding sampling capacitor 822 . The sample-hold circuit 82B has the same configuration as the sample-hold circuit 82A , but it samples and holds the video signal V B according to the sampling signals qB 1 , ··· output from the shift register 81B . The sampling points of the video signals V A and V B are shown in Figure 9. The outputs of the sample-hold circuits 82A and 82B are input to holding circuits 83A and 83B , respectively. The holding circuit 83A comprises analog switches 831 and holding capacitors 832 . The analog switches 831 close in accordance with the output pulse T , so that the voltages held in the sampling capacitors 822 of the sample-hold circuit 82A are simultaneously transmitted to the holding capacitors 832 . This transmission of voltages from the sampling capacitors 822 to the holding capacitors 832 is performed during the period in which the sample-hold circuit 82A is inhibited from sampling (e.g., the horizontal blanking period in a television signal). The holding circuit 83B has the same configuration as the holding circuit 83A , and the voltages held by the sample-hold circuit 82B are transmitted to the holding circuit 83B according to the output pulse T . The outputs QA 1 , ··· and QB 1 , ··· of the holding circuits 83A and 83B are supplied to an output selection circuit 84 . The output selection circuit 84 has analog switches 841 which selectively output either the outputs of the holding circuit 83A or those of the holding circuit 83B according to the selection signal U. The outputs from the output selection circuit 84 are transmitted to the column electrodes 112 of the liquid crystal panel 140 via the buffer circuit 85 . According to the invention, the column electrode driving circuit can drive a display apparatus which has a delta arrangement display unit, with an excellent image quality. In a column electrode driving circuit of the invention for driving a display unit with a delta arrangement, the video signals for two rows in the display unit can be processed simultaneously by two sample-hold means with sampling timings which differ mutually by one-half of the sampling period. Therefore, a high quality display which is equivalent to a double-speed conversion display can be performed without providing external double-speed conversion means or a line memory or frame memory for a video signal. Furthermore, when the same video signal is supplied to two sample-hold means in a column electrode driving circuit of the invention for driving a display unit with a delta arrangement, sampling is performed by the two sample-hold means according to timing that matches the delta arrangement. Since video signals sampled in this manner can be used to sequentially drive the display unit in half of the time of the sampling period, the advantages of the delta arrangement can be used to achieve high display quality without using an external memory or double-speed conversion circuit for the video signal.

Claims: A column electrode driving circuit for driving column electrodes of a display apparatus having pixel electrodes formed in a delta arrangement and driven by said column electrodes, comprising: two sample and hold means (12A,12B), each for simultaneously receiving a video signal (V;V A ,V B ), for sampling the video signal, and for holding the sampled video signal, the sampling periods of said two sample and hold means being of substantially the same duration, and the sampling timings of said two sample and hold means being different; and output means (13A,13B) for selecting one (12A) of said two sample and hold means, and for driving said column electrodes on the basis of the sampled video signal held in said one selected sample and hold means to drive a first row of said pixel electrodes, and for selecting the other (12B) of said two sample and hold means, and for driving said column electrodes on the basis of the sampled video signal held in said other selected sample and hold means to drive a second row of said pixel electrodes; wherein said first row of pixel electrodes drives one of two adjacent pixel rows and said second row of pixel electrodes drives the other of said two adjacent pixel rows, and wherein said output means (13A,13B) is controlled by one selection signal (U) for alternatingly selecting said one and other of the two sample and hold means; and wherein the sampling period of said one sample and hold means (12A) overlaps the sampling period of said other sample and hold means (12B) for said one and other of the two adjacent pixel rows, respectively. A column electrode driving circuit according to claim 1, comprising a sample signal generating means which includes two shift registers (81A,81B), wherein timings of the two shift registers are different by one-half of the clock period of a clock signal () by virtue of one (81B) of the two shift registers receiving said clock signal via an exclusive-OR gate (87), and the sampling timings of said two sample and hold means are different by one-half of said sampling period corresponding to a half-pixel pitch. A column electrode driving circuit according to claim 1, comprising two sample signal generating means (31A,31B), each for sequentially generating sample signals for a respective one of said two sample and hold means (12A,12B), the total number of said sample signals generated by said two sample signal generating means being twice the number of said column electrodes, wherein said sample signals generated by said two sample signal generating means are input directly to said two sample and hold means so as to control sampling timings of said two sample and hold means, respectively, and wherein timings of said sample signals are controlled based on two clock signals (A,B) input to said two sample signal generating means, respectively, said two clock signals having a phase difference corresponding to one-half of said sampling period. A column electrode driving circuit according to claim 3, wherein one (12A) of said two sample and hold means receives the odd-numbered ones of said sample signals in the sequence of total sample signals, and the other (12B) of said two sample-and-hold means receives the even-numbered ones of said sample signals in the sequence of total sample signals. A column electrode driving circuit according to claim 4, further comprising selection means (13A,13B) coupled to the outputs of said two sample signal generating means, for selectively outputting either of said odd-numbered and even-numbered ones of said sample signals. A column electrode driving circuit according to claim 1, comprising first and second sample signal generating means (31A,31B;81A,81B), each for sequentially generating sample signals, the number of said sample signals being equal to the number of said column electrodes, each one of said two sample and hold means (12A,12B;82A,83A,82B,83B) receiving a respective one of a first (V A ) and second (V B ) video signal, sampling the respective video signal, and holding the respective video signal, the sampling timings of said two sample and hold means being different by one-half of said sampling period. A column electrode driving circuit according to claim 6, wherein one (12A;82A,83A) of said two sample and hold means receives sample signals from said first sample signal generating means (31A;81A), and the other (12B;82B,83B) of said two sample and hold means receives sample signals from said second sample signal generating means (31B;81B). A column electrode driving circuit according to claim 1, comprising sample signal generating means for outputting sampling signals to each of said two sample and hold means, said sample signal generating means comprising a single shift register (11) having a plurality of stages, the number of said stages being greater than the number of column electrodes. A column electrode driving circuit according to claim 1, wherein said output means comprises output buffer means (13A,13B;73) for receiving said sampled video signals from each of said two sample and hold means, and for connecting said sampled video signals from each said respective sample and hold means to said column electrodes. A column electrode driving circuit according to claim 1, wherein said two sample and hold means (12A,12B) receive respective ones of a pair of video signals, the sampling timings of the two sample and hold means (12A,12B) differ by one-half of the sampling period, and said output means (13A,13B) selects said one and other of the two sample and hold means in response to first and second voltage levels of said selection signal (U) respectively. A column electrode driving circuit according to claim 10, wherein said output means comprises output buffer means (13A,13B) for receiving said sampled video signals from each of said two sample and hold means, and for transferring to said column electrodes the respective sampled video signals from each of said one and other selected sample and hold means in dependence upon the level of said selection signal. A column electrode driving circuit according to claim 1, wherein said output means includes a respective switching means (13A,13B) for each of said two sample and hold means (12A,12B).

Inventors: KAWAGUCHI TAKAFUMI, KAWANISHI JUNJI, TAKE HIROSHI, TAKEDA SHIRO, KAWAGUCHI, TAKAFUMI, KAWANISHI, JUNJI, TAKE, HIROSHI, TAKEDA, SHIRO
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1991
Main classification: H04N3
IPC codes: H04N5, G09G3, H04N3