Memory access system and method

Abstract: An access memory system according to pipeline processing realizing an access to both microprocessors operated by 2 clocks per cycle and 1 clock per cycle. This method improves the access speed of the main memory while keeping flexibility, wherein a transition request signal for the pipe line is received to generate a control signal continuing by the number of cycles corresponding to at least the number of first-out addresses of the pipeline from immediately after start of pipeline operation and a display signal for displaying the completion of data access to banks. Then, while either of these two signals is generated, an address latch signal synchronizing with a clock signal is generated, the address latch signal is distributed to each bank, and data access is executed at a high speed.

Description: FIELD OF THE INVENTION The present invention relates to a memory access system using a microprocessor, and in particular to a memory access system using a microprocessor capable of partitioning an address space into a plurality of regions called banks to improve access speed by parallel accessing the respective regions. BACKGROUND OF THE RELATED ART Conventionally, a procedure for improving a processing speed of computers has been proposed wherein a memory capable of operating at a very high speed, called a cache memory, is disposed between a main memory and a processor. The procedure provides the average access time of the computer to be upgraded to a higher speed corresponding to the access time of the cache memory. The cache memory is ordinarily based on a burst transition (at the time of read) access. Fig. 1 is a timing chart showing an example of bus cycle of the microprocessor when accessing a two-clock basic cycle. In Fig. 1, CLK depicts a clock signal, ADDRESS address data for a read or write output on a bus from the microprocessor, BS# a control signal for designating the start of the bus cycle (logic of the signal and CLK is taken and the address data is latched), DATA read (or write) data, DC# a signal designating that the read-out data is effective (or completion of write of the write data), where "#" represents negative logic and "O" represents timing. In this example, one cycle (basic cycle) is set to a length corresponding to two clocks to prevent a so called "bus conflict" wherein data of a read cycle and data of a write cycle collide on the bus. Thus, a series of operations are executed by the basic cycle of a two clock length, namely; the read (or write) address is fed on the bus; after the read (or write) address is latched by timing of BS# variation, read (or write) data are read (or written). However, a miss can arise, such as required data often does not exist within the cache memory, which has a smaller capacity compared to the main memory. In the event of such a miss, the contents of the cache memory is renewed any time by the contents of the main memory but the same lowers the operation speed of the computer depending on the access speed of the main memory. For such drawbacks countermeasures are proposed as below: (1) the capacity of the cache memory is enlarged, (2) a hit-rate is upgraded by improving the algorithm of caching of the cache memory, and (3) a high speed/high characteristic element like a cache memory is employed for the main memory. However, problems arise because the countermeasure (1) is limited with respect to system cost, (2) can reduce the miss-hit but it is difficult to eliminate it completely, and (3) requires a larger amount of system cost proportional to the increase of the capacity of the main memory. Therefore, any of the above countermeasures do not resolve the said problems. To meet the requirement of a large scale mathematical computation system in a computation field for science and technology there is provided a computer capable of a vector arithmetic operation. For such a vector operation, for example, during an operation for vertical, laterally aligned data such as a matrix, the cache memory capable of only a read of the laterally aligned data produces, on the read of the vertically aligned data, a considerable waste of operation and is not suitable therefor. Since the vector operation deals with large scale data, the cache memory finally causes a caching miss because an ordinary cache memory often cannot contain all the data. In the event of the caching miss, the main memory is accessed to cause a deterioration of the characteristics. A read/write speed of a general main memory is lower than that of the cache memory, which may carry out read/write by a high speed basic cycle. For example, consider a main memory to operate a one read (or write) cycle by a four-clock operation, such a structure of the main memory is shown in Fig. 2. The read or write operation in the structure is shown in a timing chart of Fig. 3. As is apparent from the drawing, in the read or write operation, although a basic cycle at the microprocessor side is completed by two clocks, the main memory side requires four clocks at every cycle before a signal DC#, which designates the read data to be in effect (or completion of write of the write data), is returned. Accordingly, a problem arises in the inability to improve the speed because the microprocessor stops operation during the time that a wait cycle, corresponding to two clocks, is produced at respective cycles. In the conventional example to solve the problems, it is well known that the main memory is divided into a plural number, as shown in Fig. 4 and, for example, an address space of the main memory is partitioned into two pieces that are referred to as a BANK. It is assumed that one bank has an address space of W × D, where W corresponds to a block length with a predetermined data width and D corresponds to the number of blocks and further the addresses used among the blocks with each other and positioned at the same height as adjacent banks are continued. Here, if the least significant address to the most significant address are continued for the two-bank main memory, the accesses are sequentially executed in the order of; where the least significant block is represented by L and the most significant block by 1. By using the main memory having the partitioned banks, "pipe-line" operations can be carried out as below. In Fig. 5, by means of operations that address data designating an optional address in bank 0 and the other address data designating an optional address in bank 1 are output repeatedly in the order of basic cycles C 1 , C 2 , C 3 , ···, a read (or write) data can be obtained, after a time lapse of the cycle number (the address first-out number) resulting from the total bank number minus one basic cycle, or on and after the basic cycle C 2 , in appearance, at every cycle basis. Accordingly, the read data corresponding to the address of the basic cycle C 1 is obtained by the next basic cycle C i+1 , and an output operation of the address data and read (or write) operation of the read (or write) data are parallel executed with a pipe-line operation of the stage number corresponding to the bank number, thus the main memory with a lowered speed compared to the cache memory can be utilized at a high speed corresponding to the cache memory. However, in the conventional memory access devices, latch timing of the address data is determined by a rising edge of a bus control signal "BS#" and a clock signal "CLK", and concurrently detect the timing of the read (or write) data determined by a signal "DC#" designating effectiveness (or completion of write of the write data) of the read data, and in connection with the foregoing, the following problems arisen (1) Due to the requirement for determining a logic level around the time of a rise of the signal "BS#", one cycle must be equal to at least the length corresponding to two clocks, thus resulting in an inability to perform a high speed one-clock operation. The processor for carrying out the vector operation requires a high speed processing of a large amount of data and is not met because of a lower access speed such as a two-clock operation. (2) For the partitioned banks, the address can be latched at every cycle, for example, only by continuously asserting every time using BS# but without repeating the assert and negate, hence there is a possibility of a one clock operation. However, this results in only carrying out a one-clock cycle operation. In this process, a main memory dedicated to the microprocessor having a basic clock of one-clock prevents the other microprocessor employing a basic clock from accessing the main memory, thus a problem arises with respect to applicability in general use. EP 283 115 A discloses a data processing system with a processor having a pipelined address mode which may be enabled by a slave device for any given access. WO 87 04822 A discloses an apparatus for latching addresses in an interleaved memory system so that a new address may be output every clock cycle. The present invention has been made to solve the abovementioned problems and an object of the invention is to provide a memory access system using a microprocessor and greatly improve the access speed of a memory to ensure applicability in general use. In the first aspect of the invention a microprocessor as defined in claim 1 is provided. In the second aspect of the invention, a memory access device as defined in claim 4 is provided. In the third aspect of the invention, a data processing system as defined in claim 6 is provided. In the fourth aspect of the invention, a method of accessing data as defined in claim 8 is provided. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a bus timing chart of a cache memory of a two-clock basic cycle, Fig. 2 is a connection diagram of a microprocessor having a two-clock basic cycle with a memory device having a four-clock operation, Fig. 3 is a bus timing chart of the structure in Fig. 2, Fig. 4 is a connection diagram of a microprocessor in case of a partitioned main memory for realizing a pipe-line, Fig. 5 is a bus timing chart of the structure in Fig. 4, Fig. 6 is a conceptual view of the pipe-line number 1 for an explanation of principle of the invention, Fig. 7 is a conceptual view of the pipe-line number 2 for an explanation of a principle of the invention, Fig. 8 is a conceptual view of the pipe-line number 4 for an explanation of a principle of the invention, Fig. 9 is the logical pipe-line number being set depending on the bank number and an address stride of a main memory, Fig. 10 is a bus timing chart without a wait in the pipe-line number 1, Fig. 11 is a bus timing chart with one wait in the pipe-line number 1, Fig. 12 is a bus timing chart without a wait in the pipe-line number 2, Fig. 13 is a bus timing chart with one wait in the pipe-line number 2, Fig. 14 is a bus timing chart without a wait in the pipe-line number 4, Fig. 15 is a bus timing chart with one wait in the pipe-line number 4, Fig. 16 is a block diagram of a first embodiment of a memory access device according to the invention, Fig. 17 is a block diagram of an example of the microprocessor in Fig. 16, Fig. 18 is a block diagram of an example of the memory access control section in Fig. 17, Fig. 19 is a block diagram of an example of the address producing section in Fig. 18, Fig. 20 is a block diagram of an example of the bus control section in Fig. 18, Fig. 21 is a block diagram of an example of the L/S pipe section In Fig. 18, Fig. 22 is a circuit diagram of example for producing a pipe-line enable signal, Fig. 23 (Figs. 23A and 23B) is a conceptual view showing operation of a timing sequencer, Fig. 24 is a bus timing chart of the device in Fig. 17, Fig. 25 is a circuit diagram of a second embodiment of a memory access device of the invention, and Fig. 26 is a bus timing chart of the device in Fig. 25. The invention will be described based on the drawings as below, and a principle of a method of accessing data will be explained in advance of the description of a memory access system using a pipe-line processing according to the invention. Figs. 6 to 8 show examples of formations of various pipe-lines with the "physical" pipe-line stage numbers respectively of one stage, two stages and four stages, where the bank numbers of respective drawings correspond to the pipe-line numbers. In the formations of the drawings there are shown a main memory formed of one bank (BANK 0) in Fig. 6, two banks (BANK 0, BANK 1) in Fig. 7, and four banks (BANK 0, BANK 1, BANK 2, BANK 3) in Fig. 8. An address bus and a data bus, and a microprocessor through a control line are connected to the main memory, and the numbers of the banks in the main memory can be sent from an external terminal to the respective microprocessors. Accordingly, for example, an external terminal for informing the bank number and a register for setting the bank number and the like are provided on the microprocessor. The microprocessor can suitably select the logic pipe-line number depending on an address variation width at the time of a data access. The variation width of the address is defined as a stride value (one data width), then the substantial pipe-line number determined by the bank number or the stride value is as shown in Fig. 9. In Fig. 9, consider the execution of the data access when stride value = 1, where bank "n" (a natural number) is accessed on the first data access, bank n + 1 is accessed on the next data access, and bank n + 2 is accessed on the following data access. In this process, the adjacent banks are sequentially accessed at an interval of the bank data width, thus the logic pipe-line number and bank number (or the physical pipe-line number) are equal to each other. When the stride value is equal to, for example, two times the bank data width (stride value = 2), bank "n" is accessed on the first data access, and bank n + 2 is accessed on the next data access. In this process, every second bank is accessed, and the logic pipe-line number is "one stage" at the bank number 1 and also "one stage" at the bank number 2 and "two stages" at the bank number 4. In this way, the bank number in this configuration and the logic pipe-line number depending on the address stride can be set independently of the physical pipe-line number, the pipe-line bus operation is executed depending upon that logic number. The following are features of the bus timing of the memory access system provided by the invention; (1) a dedicated input signal (pipeline enable signal) PEN# required by the pipe-line bus is provided; (2) a dedicated signal (address valid) AV# is provided for designating an entry to a pipe-line cycle and determination of the pipe-line address; (3) a bus start signal BS# is processed as described later. As a result, in response to an input of a signal PEN#, the microprocessor starts the pipe-line bus operation of the logic pipe-line number in Fig. 9. If a data complete signal DC# returns when the signal AV# is asserted, the microprocessor uses the signal DC# as a renewing signal of the address or as a latch signal of the external circuit. The signal BS# is in an asserting condition immediately after the start of the pipe-line operation, the asserting condition is maintained continuously at least as long as the cycle corresponding to the address first-out of the pipe-line. The signal BS# is used instead of the signal DC# in (2). If the address is not latched by the signals AV# and DC#, the address is latched by the signal BS# instead of the signal DC#. The pipe-line bus can execute the first-out of the addresses corresponding to the bank number, and the addresses exceeding the bank number enable the first-out operation but does not enable a renewing operation, until the signal DC# for the bank previously accessed is returned. The features of a bus timing for the method of memory access of the invention as abovementioned, or a bus timing operation corresponding to the pipe-line number or the bank number in Figs. 6 to 8, will be described with reference to Figs. 10 to 15. One clock cycle hereinafter used is defined to be the minimum time (cycle) during which the address data is processed on the bus, and is used to designate a processing limit capability of the arithmetic computing unit. Fig. 10 is a bus timing chart corresponding to Fig. 6, showing a read - write cycle of the pipe-line number = 1 without a wait. In the drawing, A0 to 31, BCO to 7# and BAT0 to 2 depict an address signal, a bus control signal and a bus access type signal respectively, BS# a bus start signal, DS# a data strobe signal, R/W# a read/write signal, AV# an address valid signal, D0 to 63 a data signal, DC# a data complete signal, and PEN# a pipe-line enable signal. Although a clock CLK is a two-clock basic cycle, the start of the pipe-line operation is detected by asserting the pipe-line enable signal PEN#, and in response to such detection the address valid signal AV# is asserted and concurrently the bus start signal BS# is asserted as much as the address first-out number (here, 1). The address data a3, a4, ··· ··· during a pipe-line operation are latched at every clock basis by an address valid signal AV# and data complete signal DC# (d2, d3, ··· ···). But, the address data a2 immediately after the start of the pipe-line operation is latched by one clock using the bus start signal BS# instead of the data complete signal DC# because the data complete signal DC# is not returned. During the pipe-line operation, the address data is latched at a one clock unit without a wait to realize high speed access to the main memory. Fig. 11 is a bus timing chart corresponding to the structure in Fig. 6, where a read - write cycle of the pipe-line number = 1 is shown and the bus timing chart shows the data complete signal DC# generated with a delay time of one clock (one wait). Although a clock CLK is a two-clock basic cycle, the start of the pipe-line operation is detected by asserting the pipe-line enable signal PEN#, and in response to such a detection, the address valid signal AV# is asserted but the bus start signal BS# is not asserted. The bus start signal BS# is not asserted because of one wait, output address a2 can be latched by the address valid signal AV# and the data complete signal DC#. For the address data a2, a3 ··· ···, the address data on and after a3 are latched at every second clock by the address valid signal AV# and the data complete signals DC# (d1, d2, ··· ···). Fig. 12 is a bus timing chart corresponding to the structure in Fig. 7, where a read - write cycle of the pipe-line number = 2 without a wait is shown. When the pipe-line operation is started by asserting the pipe-line enable signal PEN#, the bus start signal BS# is asserted as long as two clocks immediately after the start. Two address data a2 and a3 during the pipe-line operation are latched at every clock by the bus start signal BS#, and the address data on and after a4 or the remaining address data a4, a5 and a6 are latched at every clock by the data complete signals (d2, d3 and d4). The bus start signal BS# is asserted as long as two clocks because the data complete signal DC# does not return in the timing of latching the output address a3. Fig. 13 is a bus timing chart corresponding to the structure in Fig. 7, where a read -write cycle of the pipe-line number = 2 is shown and the bus timing chart illustrates the data complete signal DC# generated with a delay time of one clock (one wait). Although a clock CLK is a two-clock basic cycle, start of the pipe-line operation is detected by asserting the pipe-line enable signal PEN#, and in response to such a detection the address valid signal AV# is asserted and concurrently the bus start signal BS# is asserted as much as the address first-out number (here, 1). The address data a2, immediately after the pipe-line operation, is latched by one clock by the bus start signal BS# instead of the data complete signal DC# because the data complete signal DC# is not returned; the address data a3 and a5 are latched at every clock by the address valid signal AV# and the data complete signals DC# (d1, d3), and the address data a4 and a6 are latched at every second clock by the address valid signal AV# and the data complete signals DC# (d2, d4). Fig. 14 is an example of the pipe-line number = 4. The address data a2 to a5 are latched at every clock by the bus start signal BS#, which is asserted as long as four clocks immediately after the start of the pipe-line operation, and the remaining address data a6 to a8 are latched at every clock by the data complete signals DC# (d2 to d4). The bus start signal BS# is latched as long as four clocks because the data complete signal DC# does not return at the timing of latching the output address a5. Fig. 15 is a bus timing chart of the pipe-line number = 4 with one wait. The address data a2 to a5 and a7 other than the address data a6 are latched at every clock. The output address a5 can be latched by the data complete signal DC# and the address valid signal AV#, and the bus start signal BS# is not output. For simplifying the explanation, the pipe-line numbers were 1, 2 and 4 in the foregoing, but it is possible to increase the pipe-line number. According to the invention, a transition from the basic cycle to the pipe-line cycle can be performed in response to the start of the pipe-line operation to ensure applicability in general use between the microprocessors having the different basic cycles. The address data is latched by the address valid signal AV# and the data complete signal DC# that designates the enter to the pipe-line cycle, thereby enabling a one-clock operation with a higher speed of the main memory. The logical pipe-line number depending on the bank number and the address stride can be set to prevent deterioration of bus efficiency. Next, the embodiments of the memory access device using the pipe-line processing for realizing a method of memory access according to the invention will be described as following. First Embodiment Figs. 16 to 24 are views of the first embodiment of the memory access device according to the invention, where the bank number is 1. In Fig. 16, numeral 10 depicts a microprocessor. The microprocessor 10 having functions as a pipe-line operation detect means and a control signal generating means generates an address data ADDER to execute a predetermined arithmetic operation by outputting the data DATA corresponding to the ADDER on a data bus in a write cycle or by taking in for the same from the data bus in a read cycle. The microprocessor 10 can be informed of the bank number (in this example, 1) from the external, and is provided with, for example, a signal terminal 11 (register is also available) for information of the bank number. From among various control signals inputting in or outputting from the microprocessor 10, the DS# is a data strobe signal for displaying termination of the pipe-line bus operation, an R/W# is a read -write display signal for displaying a read cycle or write cycle, the BS# is a bus start signal for maintaining the asserting condition of the clock number corresponding to the first-out number of the pipe-line immediately after the start of the pipe-line operation, the AV# is an address valid signal for displaying the enter to the pipe-line and the assertion of the pipe-line address, and the DC# is a data complete signal for displaying the completion of data read from the main memory or data write to the main memory, and a PEN# is a pipe-line enable signal. The address data ADDER from the microprocessor 10 is taken into a main memory 14 through a master latch 12 and a slave latch 13. The data DATA from the main memory 14 is taken into the microprocessor 10 through a buffer 15, or the data DATA from the microprocessor 10 is brought into the main memory 14 through a master latch 16 and a slave latch 17. A latch circuit 18 functions as a latch signal generating means and a dividing means. When the address valid signal AV# and data complete signal DC# are negative logic or the bus start signal BS# is negative logic, the latch circuit 18 is provided with a multiple logic means 19 for making an output a positive logic and a flip-flop 20 for synchronizing the positive logic output with a clock signal CLK. A Q-output of the flip-flop 20 becomes a latch signal to be fed to the slave latches 13 and 17 through AND gates 21 and 22 and concurrently fed to a control circuit 23 for determining the operational timing of the main memory 14. Numeral 24 depicts a circuit (display signal generating means) for generating the data complete signal DC#. The circuit 24 sends the signal generated at the latch circuit 18 to the microprocessor 10 through an inverter gate 25 under the condition without wait, and on the other hand sends the same but after giving a one clock delay by a flip-flop 26 to the microprocessor 10 through an inverter gate 25 under the condition with one wait. The data complete signal DC# for indirectly displaying the completion of the access of the main memory 14 is produced by applying a delay depending on the presence of a wait to the signal generated at the latch circuit 18 depending on the response speed of the main memory. If it is possible to take out the signal corresponding to the data complete signal DC# from the main memory 14, the signal may preferably be fed directly to the microprocessor 10. Fig. 17 is a block diagram of an example of the microprocessor 10 of Fig. 16. In the microprocessor 10 there are provided an address producing section 60 for producing the data address, a memory access control section 100 including a bus control section 70 for controlling the bus and an L/S pipe section 80 for processing load/store of the data, a mask register VMR for temporarily storing the data, a mask pipe 91 connected to a vector register VR and a scalar register VSR and to a mask register VMR, the vector register VR and the scalar register VSR, a data buffer 92, a graphic pipe 93, an adder pipe (adder) 94, a multiplier pipe (multiplier) 95 and a divider pipe (divider) 96. The mask pipe 91, data buffer 92, graphic pipe 93, adder pipe 94 and multiplier pipe 95 other than the divider pipe 96 are operated by one clock. The data is stored in the vector register VR from the L/S pipe section 80 at every clock to be arithmetic processed by the data buffer 92, graphic pipe 93, adder pipe 94, multiplier pipe 95 and divider pipe 96. Fig. 18 is a block diagram of the memory control 100 in Fig. 17. The address producing section 60 includes an address computing section, a latch address converting section, an address producing control section, and an output section. The bus control section 70 includes an external terminal control section, a timing sequencer section and an external terminal. The L/S pipe section 80 includes a load -store control section, an input section, a load pipe section, a store pipe section and an output section. The stride value (or indirect value) and base value for producing the address stored in the register are input to the address computing section of the address producing section 60, and the inner processed data are output from the output section as the address signals A0 to 31, bus control signals BCO to 7# and bus access type signals BAT0 to 2. The address producing control section, timing sequencer section, external terminal control section and load -store control section are connected to each other as shown in the drawing to be supplied with the external input signals and timing signals as shown in the drawing. The data complete signal DC#, pipe-line enable signal PEN# and bus control signal are input to the timing sequencer section through the external terminal, and the bus control signal, bus start signal BS#, data strobe signal DS#, read/write display signal R/W# and address valid signal AV# are output. The load pipe section of the L/S pipe section 80 is for reading the data; the store pipe section is for outputting the data, and both pipes are connected with an inner data bus that is connected to the mask register VMR, vector register VR and scalar register VSR in Fig. 17. The data D0 to 63 are input to the input section and output from the output section. Fig. 19 is a block diagram of an example of the address producing section 60 in Fig. 18. On starting, an operand length is designated for a decrementer 61, from which an inner bus request signal IBR# is output. The timing sequencer output, data complete signal DC# and pipe-line enable signal PEN# are respectively input to a latch enable producing section 62, an output latch enable producing section 63 and three-state buffer control section 64. The address computing section 66, the latches 67a and 67b and the address converting section 68 are connected as shown in the drawing, and the output latch 67c and a three-state buffer 69 corresponds to the output section in Fig. 18. The signal from a latch enable producing section 62 is supplied to the decrementer 61 and latches 67a and 67b; the signal from an output latch enable producing section 63 is input to an output latch 67c, and the signal from a three-state buffer control section 64 is input to a three-state buffer 69 through a flip-flop 65. The three-state buffer 69 outputs the address signals A0 to 31 designating the data address, the bus control signals BC0 to 7# and the bus access type signals BAT0 to 2. Fig. 20 is a block diagram of an example of the bus control section 70 in Fig. 18. In the drawing, numerals 71a to 71f depict external terminals, and 72 a timing sequencer. Numeral 73 depicts an external terminal control section that includes a bus control section 74, flip-flops 75 and 77, and three-state buffers 76 and 78, and the external terminal control section is connected by a bus line 79 as shown in the drawing. A hold request signal HREQ# for acknowledging a bus right is output from the external terminal 71a; a hold acknowledge signal HACK# designating an acknowledgement of input of the bus right is input to the external terminal 71. The pipe-line enable signal PEN# and the data complete signal DC# input to external terminals 71e and 71f enter the bus line concurrently, and are input to the timing sequencer 72. The signals of symbols as shown in the timing sequencer 72 are coincident with the symbols attached to the clock CLK in Figs. 10 and 11. Fig. 21 is a block diagram of an example of the L/S pipe section 80 in Fig. 18. The inputted data D0 to 63 are input to a load pipe section 83 through an input latch section 82 that is controlled by an input latch enable producing section 81 and are output to the inner data bus of the microprocessor 10. The data input from the inner data bus is stored through a store pipe section 84 into an output latch section 86, which is controlled by the output latch enable producing section 85, and then is output from a three-state buffer 89, which is controlled by a three-state buffer control section 87 and a flip-flop 88. The clock signal CLK is input to the input latch section 82, output latch section 86 and flip-flop 88 to perform a synchronization of operation. The data complete signal DC# and timing sequencer output are input to the input latch section 82, output latch section 86 and three-state buffer 89. Fig. 22 is a circuit diagram of an example of producing the pipe-line enable signal PEN#. The pipe-line enable signal PEN# may preferably be asserted when detecting the address of the main memory capable of a pipe-line operation, and can be obtained by the process that a logical sum of the signal inverted after the address signal of the main memory is decoded by the decoder and a bus start signal BS# is produced by an NAND circuit 98 of an inverse input and then the logic sum is passed through a flip-flop 99. The pipe-line enable signal PEN# is asserted upon starting the pipe-line operation as shown in Figs. 10 to 15. Figs. 23A and 23B are conceptual views of the timing sequencer 72 in Fig. 20. In the drawings, symbol ○ designates an assert,  a negate, and □ a latch. The portion shown by symbol M is achieved by a circuit as shown by symbol N, and the portion shown by symbol P is achieved by a circuit as shown by symbol Q. For an explanation of a part of the operation described above, a start signal is asserted at a latch Ti to obtain the bus right, then the control proceeds from a latch T1 to a latch T2P1. Here, the data complete signal DC# and the inner bus request signal IBR# are asserted, and return to the latch T1 when the pipe-line enable signal PEN# is the negate. When the data complete signal DC#, inner bus request signal IBR# and pipe-line enable signal PEN# are all asserted, the control proceeds to a latch P1B, and when the data complete signal DC# is the negate and the inner bus request signal IBR# and pipe-line enable signal PEN# are asserted, then the control proceeds to a latch P1S. In the latch P1S, when the data complete signal DC# is the negate, the control proceeds to a latch P1SW to enter a wait, and when the data complete signal DC# and inner bus request signal IBR# are asserted, the control is to proceed to a latch P1. The operation of this conceptual view corresponds to symbols attached on the clock signal CLK, as shown Figs. 10 and 11. In the memory access device as described above, the bus timing is as shown Fig. 24. As is apparent from the drawing, the address data a1 immediately after the start of the pipe-line operation is determined by a timing of the master latch clock in an assert condition of the bus start signal BS# (see symbol A), the next address data a2 is determined by a timing of the master latch clock in an assert condition both of the address valid signal AV# and data complete signal DC# (see symbol B). Therefore, the main memory 14 is accessed at every clock at high speed. Second Embodiment Figs. 25 and 26 show the second embodiment of a memory access device according to the invention, where the bank number is 2. The embodiment includes a main memory 50 at the bank 0 side and a main memory 51 at the bank 1 side. In Fig. 25, numeral 30 depicts a microprocessor, 31 depicts one for informing the microprocessor 30 of the bank number, for example, an input terminal. An address data ADDER from the microprocessor 30 is taken and fed to either of the slave latches 33 or 34 through a master latch 32, the two slave latches 33 and 34, each corresponding to the bank number, receive respectively a bank-0 latch signal and a bank-1 latch signal from a latch signal generating circuit 35. When the address valid signal AV# and data complete signal DC# both are negative logic or when the bus start signal BS# is negative logic, when the address data ADDER is a 64-bit data bus, the latch signal generating circuit 35 is comprised of multiple logic circuits 36 and 37 in which either output thereof becomes positive logic depending on the logic of the lower fourth bit, and flip-flops 38 and 39 for synchronizing the abovementioned positive logic with a clock signal CLK. The latch signal generating circuit 35 determines the output of the multiple logic circuit 36 at bank 0 side to be true when the lower fourth bit of an address data ADDER is negative logic, and determines the output of the multiple logic circuit 37 at bank 1 side to be true when the lower fourth bit of an address data ADDER is positive logic. When the address data ADDER designates bank 0, if the address valid signal AV# and data complete signal DC# are negative logic or the bus start signal BS# is negative logic, then the main memory 50 at the bank 0 side is accessed by taking the address data ADDER into the slave latch 33 at bank 0 side, and when the address data ADDER designates bank 1, if the address valid signal AV# and data complete signal DC# are negative logic or the bus start signal BS# is negative logic, then the main memory 51 at the bank 1 side is accessed by taking the address data ADDER into the slave latch 34 at bank 1 side. Numeral 40 depicts a circuit for generating the data complete signal DC#, the circuit provides two circuits, one for the bank 0 and another for the bank 1. Each circuit is comprised of flip-flops 41 and 42, and switch 43, which can be turned with interlocking depending on the wait number (one or two). For example, the latch signal for the bank 0 side or the latch signal for the bank 1 side is delayed by one clock (or two clocks) and is input to the microprocessor 30 through an NOR gate 44. Numeral 45 depicts a master latch for data, 46 and 47 slave latches for data, and 48 and 49 buffers for data. According to the structure described above, the bus timing is as shown in Fig. 26, the address data a10 and a11, immediately after the start of a pipe-line operation are determined by a timing of the master latch clock under the asserting condition of the bus start signal BS# (see symbols C and D), and taken sequentially into the slave latches at the bank 0 side shown by #0 and at the bank 1 side shown by #1, depending on the logic state of the then lower fourth bit of the address, and at the same time, the succeeding address data a12, a13, ··· ··· are determined by timing of the master latch clock under the asserting condition of the address valid signal AV# and data complete signal DC# (see symbols E and F), and taken sequentially into the slave latches at the bank 0 (#0) side and at the bank 1 (#1) side, depending on the logic state of the then lower fourth bit of the address. Thus, the main memory 50 at the bank 0 side and the main memory 51 at the bank 1 side are accessed at every clock to be operated at a higher speed. As hereinbefore described, according to the embodiments, a transition can be executed from the basic cycle to the pipe-line cycle in response to the start of the pipe-line operation, thus ensuring a general applicability between the microprocessors having different basic cycles. The address data can be latched by the address valid signal AV# and data complete signal DC# both displaying the enter to the pipe-line cycle and the establishment of the address thereby to enable a one clock operation for producing a high speed process of the main memory. The logical pipe-line number depending on the bank number and address stride value can be set to prevent the deterioration of a bus efficiency. The embodiments hereinbefore described employ two kinds of bank numbers "1" and "2", nevertheless, the present invention is not limited to the numbers described. When the bank number is required to increase in the embodiments, the latch signal circuit and the data complete signal DC# generating circuit may be multiplexed in their structures, depending on the bank number. As hereinbefore fully described, in accordance with the present invention, after the start of the pipe-line operation there is generated a control signal that continues as long as the cycle corresponding to at least the address first-out of a pipe-line; concurrently the display signal for displaying the completion of the data access is produced, and the address latch signals are partitioned into respective banks by generating the address latch signal in synchronization with the clock signal during the time that either the control signal or display signal is generating, thus an access speed of the main memory is greatly improved ensuring applicability in general use.

Claims: A microprocessor (10, 30) for use in a data processing system in which the memory address space is partitioned into n interleaved banks, where n is an integer greater than or equal to 1, comprising : data processing means, capable of operating in normal address mode or address pipelining mode; means for receiving information indicating the number of memory banks present and an address stride value to be used in accessing memory and for determining therefrom the effective number of banks to be used for a pipelined transfer; means (60) for outputting an initial memory address; means (70) for receiving a pipeline enable signal (PEN); means (60, 70), responsive to said pipeline enable signal (PEN), for outputting a number of pipelined addresses, responsive to the effective number of banks, and for outputting an address valid signal (AV) indicating that addresses being output are pipelined; means (70) for receiving a data complete signal (DC) indicating the completion of a memory access; and means (70) for outputting a bus start signal (BS) while an initial address is output and, responsive to the effective number of banks and an active data complete (DC) signal for the initial access cycle, while a subsequent number of pipelined addresses are output. A microprocessor as claimed in claim 1, wherein in said address pipe lining access mode said address outputting means stops an address renewal operation between the time after a number of pipelined addresses is output and the time when the microprocessor receives an active data complete signal (DC). A microprocessor as claimed in claim 1, wherein said data processing means processes vector data. A memory access device for executing data access in a pipe-line manner for memory (14) in a data processing system in which the memory address space is partitioned into n interleaved banks (50, 51), where n is an integer greater than or equal to 1, comprising: means (12, 32) for receiving memory addresses; means (24,40) for generating a data complete signal (DC) indicating the completion of a memory access; means (97, 98, 99) for generating a pipeline enable signal (PEN) responsive to recept of a memory address; means for receiving an address valid signal (AV) indicating that pipelined addresses are being supplied to the memory access device; means for receiving a bus start signal (BS) indicating that an initial address or a subsequent number of pipelined addresses are being supplied to the memory access device; and means (18, 35) for generating an address latching signal for each respective memory bank (50, 51), in synchronization with a system clock signal (CLK), when the bus start signal (BS) is active or the address valid (AV) and data complete (DC) signals are simultaneously active. A memory access device as claimed in claim 4, wherein generating said address latching signals by said address latching signal generating means is executed based on the contents of address data. A data processing system in which the memory address space is partitioned into n interleaved banks, where n is an integer greater than or equal to 1, comprising : a processor (10, 30), capable of operating in normal address mode or address pipelining mode, with: means for receiving information indicating the number of memory banks present and an address stride value to be used in accessing memory and for determining therefrom the effective number of banks to be used for a pipelined transfer; means (60) for outputting an initial memory address; means (70) for receiving a pipeline enable signal (PEN); means (60, 70), responsive to said pipeline enable signal (PEN), for outputting a number of pipelined address, responsive to the effective number of banks, and for outputting an address valid signal (AV) indicating that addresses being output are pipelined; means (70) for receiving a data complete signal (DC) indicating the completion of a memory access; and means (70) for outputting a bus start signal (BS) while an initial address is output and, responsive to the effective number of banks and an active data complete (DC) signal for the initial access cycle, while a subsequent number of pipelined addresses are output; the data processing system further comprising a memory access device including: means (12, 32) for receiving memory addresses; means (24, 40) for generating said data complete signal (DC); means (97, 98, 99) for generating said pipeline enable signal (PEN); and means (18, 35) for generating an address latching signal for each respective memory bank (50, 51), in synchronization with a system clock signal (CLK), when the bus start signal (BS) is active or the address valid (AV) and data complete (DC) signals are simultaneously active. A data processing system as claimed in claim 6, wherein a signal designating one of said addresses comprises an address signal (A0-31), a bus control signal (BC0-7) and a bus access type signal (BAT0-2). A method of accessing data in a data processing system in which the memory address space is partitioned into n interleaved banks, where n is an integer greater than or equal to 1, comprising the steps of : receiving information indicating the number of memory banks present and an address stride value to be used in accessing memory and determining therefrom the effective number of banks to be used for a pipelined transfer; outputting an initial memory address; asserting a pipeline enable signal (PEN); responsive to said pipeline enable signal (PEN), outputting a number of pipelined addresses, responsive to the effective number of banks, and outputting an address valid signal (AV) indicating that addresses being output are pipelined; generating a data complete signal (DC) indicating the completion of each respective memory access; outputting a bus start signal (BS) while an initial address is output and, responsive to the effective number of banks and an active data complete (DC) signal for the initial access cycle while a subsequent number of pipelined addresses are output; and generating an address latching signal for each respective memory bank, in synchronization with a system clock signal (CLK), when the bus start signal (BS) is active or the address valid (AV) and data complete (DC) signals are simultaneously active. A method of accessing data as claimed in claim 8, wherein generating said address latching signals is executed based on the contents of address data. A method of accessing data as claimed in claim 8, wherein if said data complete signal (DC) is active when said address valid signal (AV) is asserted, said data complete signal (DC) is used as an address renewal signal. A method of accessing data as claimed in claim 8 in a system having one memory bank without wait states, wherein the start of said pipe-line operation is detected by asserting said pipe-line enable signal (PEN), and in response thereto said address valid signal (AV) is asserted, said bus start signal (BS) being asserted for the initial address; the address data immediately after the start of said pipe-line operation is latched after one clock cycle by said bus start signal (BS), and address data during said pipe-line operation is latched every clock cycle by said address valid signal (AV) and said data complete signal (DC). A method of accessing data as claimed in claim 8 in a system having one memory bank with one wait state and having said data complete signal (DC) generated with a delay of one clock cycle, wherein the start of said pipe-line operation is detected by asserting said pipe-line enable signal (PEN), and in response thereto only said address valid signal (AV) is asserted, for the second and thereafter address data during said pipe-line operation the third and thereafter address data are latched at every second clock by said address valid signal (AV) and said data complete signal (DC). A method of accessing data as claimed in claim 8 in a system having two memory banks without wait states, wherein said bus start signal (BS) is asserted in as many as two clock cycles immediately after said pipe-line operation is started by asserting said pipe line enable signal (PEN); two address data during said pipeline operation are latched at a rate of once per clock by said bus start signal (BS), and remaining address data on and after the fourth address data are latched at every clock by said address valid signal (AV) and said data complete signal (DC). A method of accessing data as claimed in Claim 8 in a system having two memory banks with one wait state, wherein the start of said pipe-line operation is detected by asserting said pipe-line enable signal, and in response thereto said address valid signal (AV) is asserted; said address data immediately after said pipe-line operation is latched by one clock by said bus start signal BS; the third and fifth address data are latched at a rate of once per clock by said address valid signal (AV) and said data complete signal (DC), and the fourth and sixth address data are latched at every second clock by said address valid signal (AV) and said data complete signal (DC). A method of accessing data as claimed in claim 8 in a system having four memory banks without wait states, wherein said second to fifth address data are latched at every clock by said bus start signal (BS) asserted for four clock cycles immediately after the start of said pipeline operation, and remaining address data are latched at every clock by said address valid signal (AV) and said data complete signal (DC). A method of accessing data as claimed in claim 8 in a system having four memory banks with one wait state, wherein the address data other than the sixth address data are latched at every clock.

Inventors: IINO HIDEYUKI, TAKAHASHI HIROMASA, IINO, HIDEYUKI, TAKAHASHI, HIROMASA
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1991
Main classification: G06F12
IPC codes: G06F13, G06F12