III-V compound semiconductor device, printer and display device utilizing the same, and method for producing said semiconductor device

Abstract: A III-V compound semiconductor device comprises the use of a compound semiconductor of groups III-V of the periodic table with a polycrystalline structure of an average grain size of 0.6 µm or larger.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a method for forming polycrystals of III-V compound semiconductive material, a light-emitting device utilizing said compound semiconductive material, and a printer and a display device utilizing said light-emitting device, particularly, such as a light-emitting diode or an electroluminescence device. Related Background Art Applications of polycrystalline semiconductors are already known in the following fields. In the materials of group IV of the periodic table, mainly polycrystalline Si is employed in solar cells and thin film transistors. Among polycrystals of groups II-VI, Cd-based materials are employed in thin film transistors and photosensors, and are investigated in part for applications to solar cells. Also Zn-based materials are used in electroluminescence devices and fluorescent materials, and chalcopyrite type polycrystals such as CuInSe 2 are being investigated for applications to solar cells. Among the polycrystals of group III-V group, for example, Ga- and In-based materials were once investigated for application to solar cells, but have not been developed to the level of commercialization. The III-V polycrystals appeared in many reports on solar cells, but their light emitting characteristic has only been dealt with in a few reports. Salerno, J. P. et al. reported their electron beam luminescence in Cont. Rec. IEEE, vol. 15, p.1174 - 1178, but no description has been made on the characteristic of light-emitting diode utilizing a p-n junction. Conventionally, display devices utilizing light-emitting diodes have been prepared by forming such light-emitting diodes (LED) on a monocrystalline wafer, then cutting said LED's individually or in a group of several diodes, and adhering such diodes on a supporting substrate in the form of a lamp or a display device for characters or numerals. Also there is already produced a hybrid device including plural LED's as an LED display device of a large area, but the use of such large-area LED display has been limited because of the high cost. In order to overcome the limitation in the display area of the LED display, the present inventors already proposed, in the EP Publication No. 284437A2, a selective nucleation method for forming III-V compound single crystal of a large area. This method consists of employing a substrate having a non-nucleation surface of a low nucleation density for the III-V compound crystals and a nucleation surface of an amorphous material positioned adjacent to said non-nucleation surface, and having a sufficiently small area for allowing crystal growth from a single nucleus and a nucleation density larger than that of said non-nucleation surface, and growing III-V compound single crystal from said single nucleus, eventually beyond the nucleation surface over the non-nucleation surface. Also the present inventors disclosed, in the EP Publication No. 285358A2, formation of an LED on a non-monocrystalline substrate, by switching the crystal forming conditions in the course of the above-mentioned single crystal formation, thus forming a p-n junction area therein. In case of the polycrystalline material produced according to a conventional polycrystalline material producing process, it was considered that, due to too small grain size or variation in the grain size, a light emission element such as LED cannot be produced. Accordingly, there was no motivation for trying to produce the LED. The above-mentioned selective nucleation method enables to obtain a large-area III-V single crystal on a non-monocrystalline substrate, but there may sometimes be formed polycrystals or a void on the nucleation site. The preparation of LED elements on such substrate may suffer from insufficient uniformity, since such polycrystals result in a lowered light emission intensity while such void gives rise to total lack of light emission. Besides, even the single crystal sometimes exhibits abnormal growth, assuming an oblong form with a strong anisotropy in the growth, thus hindering the device preparing process such as electrode formation. Furthermore, the selective nucleation method is associated with a contradicting property that the crystal occupancy rate is deteriorated under a crystal growth condition providing a high monocrystallinity, and vice versa. EP-A-0 180 751 discloses a method for the production of a GaAs solar cell. According to this reference single crystals are grown from each nucleation surface which will form a continuous layer. The use of polycrystalline GaAs thin film semiconductors for solar cells is also suggested in J. Appl. Phys. 60 (1), pages 413 to 417, M. Yamaguchi et al.: "Efficiency Considerations for Polycrystalline GaAs Thin-Film Solar Cells" and J. Appl. Phys. 51 (7), pages 3795 to 3800, J.J.J. Yang et al.:"Electrical Properties of Polycrystalline GaAs Films". EP-A-0 285 358 is directed to the growth of a single crystal from one nucleation surface. IBM Technical Disclosure Bulletin, vol. 16, No. 9, page 3072, B. K. Bischoff and J. J. Cuomo: "Selective Growth of GaAs" discloses generally a method for selectively depositing GaAs on nucleation surfaces such as tungsten on sapphire substrates, the grown GaAs material may be polycrystalline or monocrystalline. By the deposited GaAs a layer is formed. SUMMARY OF THE INVENTION In consideration of the foregoing, an object of the present invention is to provide a method as claimed in claim 1 for forming polycrystals of III-V compound semiconductor material and a III-V compound light-emitting device free from the above-mentioned drawbacks, a printer head and a display device employing such light-emitting device obtained by the method, as claimed in claims 10 and 14 to 16. Preferred embodiments of the method and the devices obtained by the method are claimed in claims 2 to 9 and 11 to 13, respectively. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1A to 1T are schematic views showing the method for producing an LED, as an example of the III-V compound light-emitting device of the present invention; Fig. 2 is a chart showing the relationship between the size of nucleation surface and the average grain size of polycrystals in GaAs selective deposition; Fig. 3 is a schematic view showing the method of evaluating the crystal grain size; Fig. 4 is a schematic view of an LED formed according to the present invention; Fig. 5 is a chart showing the relationship between the size of nucleation surface and the light emission intensity in the LED of the present invention; Fig. 6 is a schematic view showing the arrangement of nucleation surfaces and non-nucleation surface in a substrate for selective deposition, employed in the present invention; Fig. 7 is a chart showing the relationship among the size of nucleation surface, rate of polycrystalline island loss and rate of abnormal nucleus generation, in the selective deposition of the present invention; Fig. 8 is a chart showing the relationship among the density of nucleation surface rate of polycrystalline island loss and rate of abnormal nucleus generation, in the selective deposition of the present invention; Fig. 9 is a schematic view of an example of the MOCVD apparatus employable in the present invention; Figs. 10A to 10J are schematic views showing the process for producing an LED of the present invention, employing GaAlAs; Figs. 11A to 11J are schematic views showing the process for producing an LED of the present invention, employing GaAsP; Figs. 12A to 12G are schematic views showing the process for producing an LED of the present invention, employing GaAlAs; Figs. 13A to 13H are schematic views showing the process for producing an LED of the present invention, employing GaAs; Figs. 14A to 14H are schematic views showing the process for producing a light-emitting device not in accordance with the present invention; Figs. 15A to 15H are schematic views showing the process for producing a light-emitting device of the present invention and also showing an LED array head; Figs. 16A to 16H are schematic views showing the process for producing an electronic device of the present invention; Fig. 17 is a schematic view of an LED printer employing the light-emitting device of the present invention; Fig. 18 is a schematic view of an LED display employing the light-emitting device of the present invention; and Fig. 19 is a schematic view of a conventional LED array head. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred forms of the III-V compound semiconductor device of the present invention can be represented as follows (in the following also referred to "III-V compound semiconductor device" or "semiconductor device" only). The III-V compound semiconductor device of the present invention is featured by the use of a III-V compound semiconductor of a polycrystalline structure with an average grain size of 0.6 µm or larger. The III-V compound semiconductor device of the present invention is also featured by: a substrate having a surface composed of a non-monocrystalline material; a crystalline area of a first conductive type formed in a desired position on said substrate and composed of a polycrystalline III-V compound semiconductor; and a crystalline area of a second conductive type surrounding said crystalline area of the first conductive type and composed of a polycrystalline III-V compound semiconductor; wherein said crystalline area of the first conductive type has an exposed area. Also the preferred forms of the method for producing the III-V compound semiconductor device of the present invention can be represented as follows. The method for producing the III-V compound semiconductor device of the present invention is featured by applying a crystal growing process to a substrate having a free surface, on which a non-nucleation surface with a low nucleation density and a nucleation surface having a nucleation density larger than that of said non-nucleation surface and patterned to an optimum area for generating plural nuclei by crystal growth with an average crystal grain size of 0.6 µm are arranged in mutually adjacent manner, thereby forming III-V compound semiconductor with polycrystalline structure with an average grain size of 0.6 µm or larger, starting from said nuclei. Also the method for producing the III-V compound semiconductor device of the present invention is featured by a step for forming a crystalline area of a first conductive type and a crystalline area of a second conductive type, composed of a III-V compound semiconductor, in desired positions on a substrate having a non-monocrystalline surface; a step for forming a first electrode in a part of said crystalline area of the second conductive type; a step for eliminating the crystalline area of the second conductive type, excluding the area of formation of said first electrode, thereby exposing the crystalline area of the first conductive type; and a step for forming a second electrode in thus exposed area. The method of the present invention, for producing the III-V compound semiconductor device, enables to form a semiconductor device, such as LED, with a satisfactory yield, in an arbitrary position on an arbitrary substrate. Thus a large-sized monolithic display device or a one-dimensional LED array can be easily produced. Also the present invention allows to dispense with the device isolation step, since the semiconductor device such as LED can be formed in self-aligned and isolated manner on an insulating substrate. Also there can be achieved an improvement in the breakdown voltage of the device. Furthermore, the present invention can significantly reduce the cost of semiconductor device manufacture, since expensive monocrystalline wafer of compound semiconductor is not employed. Furthermore, when the semiconductor device of the present invention is employed in an LED array head, the space around the photosensitive drum need not be wide, and the mounting of the LED array on the supporting substrate can be achieved with only one optical alignment. Also the method of the present invention allows electrode formation without the planarization step, so that there can be avoided crystal peeling that may occur at the planarization step. According to the present invention, since the crystal formed on the substrate has a very low probability of mixed presence of single crystal and polycrystals and of voids on the nucleation sites, the characteristics of the semiconductor material are extremely stable. For example, when such semiconductor material is applied to a light-emitting device, the uniformity of the light-emitting characteristics is significantly improved in comparison with those of the conventional devices. In the following, in order to facilitate the understanding of details of the present invention, there will be explained the course of research which has lead to the present invention. [Experimentsj At first explanation will be given on the control method on crystal grain size and the light-emitting characteristics of III-V compound polycrystals. Fig. 2 shows the relationship between the size of a nucleation surface (square) and the average grain size of polycrystals when GaAs polycrystals are selectively deposited by MOCVD method. The average grain size is observed at a position of 2 - 3 µm from the surface of the crystal island. This is because, in the preparation of LED, the p-n junction is formed about the same distance of 2 - 3 µm from the surface, and the light emission intensity is most strongly affected by the crystallinity in this area. The crystal growth was conducted under the following conditions. Crystal growth conditions Trimethyl gallium (TMG) 2.4 x 10 -5 mol/min. Arsine (AsH 3 ) 1.4 x 10 -3 mol/min. Reaction pressure (20 Torr) 2.7 kPa Substrate temperature 775 °C Growth time 60 min. Diluting gas (H 2 ) flow rate 0.45 mol/min (10 l/min) Etching gas (HCl) flow rate 2.2 x 10 -5 mol/min. Nucleation surface poly Si (grain size (500Å) 50 nm) Non-nucleation surface SiO 2 Crystal island diameter 20 µm The average grain size was determined in the following manner, as illustrated in Fig. 3. An island of selectively deposited GaAs polycrystals was surfacially covered with epoxy resin, then ground with diamond paste to a thickness of about 60 µm in a cross-sectional direction perpendicular to the substrate surface, further thinned to about 20 µm by ion milling, and observed under a TEM (transmission electron microscope). The average grain size was determined by drawing a semi-circular line A at a position of about 2 µm from the surface of the crystals, and dividing the length of the curve on the cross section by the number of grain boundaries crossing said curve plus one. In this calculation, small grains generated between the larger grains and smaller than 10 % of the largest grain are excluded from the counting. The TEM observation revealed that the grain size was somewhat smaller within a range of about 2 - 3 µm from the nucleation surface, and was approximately uniform outside said range. On the other hand, as will be apparent from Fig. 2, the average grain size of crystals grew larger as the nucleation surface becomes smaller. These facts can be interpreted as follows. The nucleation density is determined by the material constituting the nucleation surface and the crystal growing conditions. The number of nuclei decreases as the size of the nucleation surface becomes smaller, and the size of crystal grain increases since the amount of raw material gas supplied per unit area or the total volume of crystals growing by consuming such raw material gas is constant if the density of arrangement of nucleation surfaces is at a certain high level. In the following there will be explained the light emission characteristics, investigated by an LED prepared with GaAs polycrystals of which grain size was controlled by the size of nucleation surface. The cyrstal growth was conducted under following conditions. Crystal growth conditions Trimethyl gallium (TMG) 3.0 x 10 -5 mol/min. Arsine (AsH 3 ) 2.0 x 10 -3 mol/min. Reaction pressure (20 Torr) 2.7 kPa Substrate temperature 775 °C Growth time 60 min. Diluting gas (H 2 ) flow rate 0.45 mol/min. Etching gas (HCl) flow rate 2.2 x 10 -5 mol/min. Doping gas p-type (DEZ) 6 x 10 -5 mol/min. n-type (SiH 4 ) 5 x 10 -7 mol/min. Nucleation surface poly Si Non-nucleation surface SiO 2 Fig. 4 is a schematic cross-sectional view of the LED, of which detailed preparation will be explained later in the examples. In short, the device was prepared by growing p-GaAs polycrystals 403 and n-GaAs polycrystals 404 in continuation on a polysilicon nucleation surface 401, and, after planarization, forming electrodes 405, 406 across an insulation film 407. The light intensity was investigated by measuring the light 409, generated from the junction, with a photomultiplier 410. Regardless of the grain size, all the polycrystalline GaAs LED's showed light emission spectra with a peak wavelength around 880 nm in the infrared region, and the light emission intensity was therefore compared at 880 nm. Fig. 5 shows the relationship between the size of nucleation surface (average grain size of crystals) and the light emission intensity. It will be understood that the light emission intensity of LED decreases with the increase in the size of nucleation surface (or decrease in the crystal grain size), with a particularly marked loss in the light emission intensity within a range of 6 - 7 µm of the size of nucleation surface (or 0.8 - 0.6 µm of the grain size). This phenomenon is probably ascribable to a fact that the decrease in grain size increases the grain boundaries, and the recombinations at such boundaries reduce the light emission efficiency. O. Paz et al. (J. Appl. Phys. 61(4) 15, 1987 p.1537 and M. Yamaguchi et al. (J. Appl. Phys. 60(1) 1, 1986 p.413) reported similar tendencies in the investigations of recombination rate of carrier and in the diffusion length of minority carriers. In the following explained is the relation among the size and density of nucleation surfaces, the rate of polycrystalline island voids lacking crystal growth on nucleation sites, and the rate of abnormal nucleus generation on non-nucleation surface. Fig. 6 is a schematic view of a substrate employed for the experiments of selective deposition. The nucleation surfaces were square-shaped, with a side a , and were arranged in a lattice pattern, with a pitch b between the centers, on a non-nucleation surface. Fig. 7 shows the void rate and the abnormal nucleation rate as a function of a , with b = 50 µm, when the nucleation surface and the non-nucleation surface were respectively composed of poly Si and SiO 2 . The crystal growth conditions were same as those in the case of Fig. 4. The void rate and the abnormal nucleation rate are both reduced with the increase of a . However, as the light emission efficiency of LED is deteriorated with the increase of a as explained before, an optimum value is determined according to the device specification. Fig. 8 shows the void rate and the abnormal nucleation rate as function of b , with a = 3 µm, under same crystal growing conditions. The void rate is reduced with the increase of b , but the abnormal nucleation increases rapidly when b exceeds 100 µm. This result indicates that, in consideration of possible troubles such as short-circuiting in the electrode wirings, dummy nucleations surfaces have to be prepared even in the areas where the light-emitting devices are not formed, in order to avoid unexpected abnormal nuclei generation. [Embodiments] The III-V compound semiconductors of the present invention are not limited to compounds of two elements, but also include mixed crystal compounds of III-V groups of the periodic table, involving three or more elements. In the following there will be explained embodiments of the present invention, with reference to the attached drawings. Following description will refer to Figs. 1A to 1J which are schematic views, showing steps of producing an LED by effecting selective nucleation and growing polycrystals of III-V compound semiconductor with controlled grain size, according to the method of the present invention. (A) On a substrate material 101 (for example a ceramic material such as Al 2 O 3 , AlN or BN; amorphous quartz; high-melting glass; or high-melting metal such as W or Mo), a thin film 102 of a material of low nucleation density (for example non-monocrystalline SiO 2 or Si 3 N 4 ) is deposited to constitute a non-nucleation surface 103. Said thin film may be formed by CVD, sputtering, evaporation or coating involving a dispersion medium (Fig. 1A). Also there may be employed a substrate 111 of a material of low nucleation density, as shown in Fig. 1K, instead of the substrate 101. (B) Nucleation surfaces 104 are obtained by forming a material of a nucleation density higher than that of the non-nucleation surface (for example non-monocrystalline polysilicon, AlN, Al 2 O 3 , Ta 2 O 5 , TiN, TiO 2 , WO 3 , etc.) in small areas (generally in squares of a size of 1 - 8 µm, preferably 1 - 6 µm and most preferably 1 - 3 µm, or in stripes with a small width which is generally 1 - 8 µm, preferably 1 - 6 µm and most preferably 1 - 3 µm). It is also possible, instead of fine patterning of the thin film, to deposit a thin film 104 of a material of a high nucleation density on a substrate, then to deposit thereon a thin film of a material of a low nucleation density thereby constituting the non-nucleation surface, and to open small windows therein by etching to exposure the nucleation surface 104 as shown in Fig. 1L, or, as shown in Fig. 1M, to form recesses in a film 104 of a material of a low nucleation density and opening small windows in the bottom of said recesses thereby exposing the nucleation surface. In the latter case, the crystal growth is conducted in said recesses. It is furthermore possible, as shown in Figs. 1N and 1O, to form a resist layer 112 except small areas, and to implant ions such as As, Ti, Ga, Al or In into a thin film 102 of a material of a low nucleation density, thereby forming ion implanted areas 113 of a high nucleation density. The distance between the nucleation surfaces is generally in a range of 20 - 200 µm, preferably 30 - 140 µm and most preferably 40 - 100 µm. (C) On the substrate thus prepared, a III-V compound (such as GaAs, GaAlAs, GaP, GaAsP, InP or GaInAsP) is grown by a MOCVD method to be explained later. (D) The nuclei grow with time, and new nuclei are generated, whereby the nucleation surfaces become covered with polycrystals 106. Then the polycrystals spread onto the non-nucleation surface 103. In this state, doping gas of n- or p-type is added to control the carrier concentration at a level of 10 18 cm -3 . (E) The n- or p-type polycrystalline layer 106 is grown to a desired size. Said layer grows in a semi-spherical shape, around the nucleation surface 104. (F) Then the doping gas is changed to grow, on the above-mentioned n- or p-type layer 106, a p- or n-type layer 107 of the opposite conductive type in a concentric spherical shape to a desired size. The external diameter of the polycrystalline compound semiconductor island 106 - 107 of semi-spherical shape is generally in a range of 10 - 120 µm, preferably 15 - 80 µm and most preferably 20 - 60 µm. (G) The upper surface of thus grown polycrystal island 106 - 107 is planarized by mechanical grinding to partially expose the internal layer 106. (H) A metal electrode 108, in ohmic contact with the external layer 107, is formed by photolithographic patterning. (I) An insulation film 109 is deposited, and is photolithographically patterned to form a contact hole 128 reaching the internal layer 106. (J) A metal electrode 110, in ohmic contact with the internal layer 106, is formed by a photolithographic process. Subsequently, annealing is conducted in inert gas such as Ar, at a predetermined temperature (generally in a range of 300 - 600 °C, preferably 400 - 550 °C and most preferably 450 - 500 °C) to optimize the contact resistances of the electrodes. A voltage application between the electrodes 108, 110 induces a charge injection between the layers 106, 107, whereby the device functions as an LED. The light may be taken out from the lower part of the device, through the substrate 101 if it is composed of a transparent material such as SiO 2 . Also the light may be taken out from the upper part of the device, by suitable selection of the forms of the electrodes 109, 110. In addition to the above-explained device structure with concentric spherical polycrystalline island grown from the nucleation surface, there may also be adopted a structure obtained, as shown in Fig. 1P, by forming a recess 120 on a substrate 114, positioning a nucleation surface 117 in an off-center position therein, growing polycrystals of p-n or n-p types 118, 119 in continuation, then planarizing said polycrystals as shown in Fig. 1Q and forming electrodes 115, 116 on the polycrystal layers of respective conductive types. The p-n junction may also be formed, in addition to the doping gas switching in the course of crystal growth, as shown in Figs. 1R to 1T by forming a layer 124 of n or p conductive type, then implanting ions 125 of the opposite conductive type and forming a layer 127 of said opposite conductive type of subsequent diffusion. In the following there will given a detailed explanation on the MOCVD method mentioned before in relation to Fig. 1C. Fig. 9 schematically shows an example of the MOCVD apparatus employed in the present invention. Although there is illustrated a low pressure apparatus of horizontal type, there may be employed a vertical type apparatus supporting the substrate in vertical position, or an apparatus of another type. Referring to Fig. 9, a chamber 909 is made of quartz, provided with a water-cooling jacket, and is evacuated to about 1,3 x 10 -4 Pa (10- 6 Torr) by means of a turbo molecular pump 917 except during the crystal growth. A substrate holder 910, made of carbon, can be heated up to 900 °C, by means of a high frequency coil (not shown) positioned outside the chamber. The substrate temperature is measured by a thermocouple 912 provided in the holder 910, and can be feedback controlled by the high frequency power. The raw material gases are introduced from the left-hand end of the chamber. Liquid materials such as trimethyl gallium and trimethyl aluminum, and liquid dopants such as diethylzinc are filled in bubblers 903 - 905 and are maintained at predetermined temperatures by thermostatic tanks. These materials are introduced into the chamber in the vapor state, by bubbling with hydrogen gas 906 of which flow rates are controlled by mass flow controllers MFC. Gaseous materials such as arsine and phosphine, and gaseous dopants such as silane or selenium hydride are filled in containers 901 - 902 and directly supplied to the chamber through mass flow controllers MFC. HCl 907, used as the etching gas, is introduced into the chamber through a separate piping system. The gasses introduced into the chamber pass around the substrate 911, and are discharged by a rotary pump 913. In such state the above-mentioned turbo molecular pump is separated from the system by a valve 916. The reaction pressure is controlled by a variable conductance valve 915. Examples of the material for III-V compound semiconductor include TMG (trimethylgallium), TEG (triethylgallium), TMA (trimethylaluminum), TEA (triethylaluminum) TMIn (trimethylindium), TEIn (triethylindium), TBAS (tert-butylarsine), TMAs (trimethylarsine), TEAs (triethylarsine), DMAs (dimethylarsine), DEAs (diethylarsine), AsH 3 , TBP (tert-butylphosphine), TMP (trimethylphosphine), TEP (triethylphosphine), PH 3 and NH 3 . Also examples of the dopant include DMSe (dimethylsellenium), DESe (diethylsellenium), DMTe (dimethyltellurium), DETe (diethyltellurium), SiH 4 , DEZn (diethylzinc), Cp 2 Mg (cyclopentamagnesium), and (MeCp) 2 Mg (methylcyclopentamagnesium). Crystal nuclei 105 of the III-V compound are generated on the substrate, by means of the low pressure MOCVD apparatus explained above. In said generation, the substrate temperature is generally in a range of 570 - 850 °C, preferably 600 - 800 °C and most preferably 660 - 780 °C, and the reaction pressure is generally 13.3 kPa (100 Torr) or less, preferably 6.7 kPa (50 Torr) or less, and most preferably in a range of 4.0 - 5.3 kPa (30 - 40 Torr). The molar ratio of supply of the raw materials of the groups V and III is generally in a range of 10 - 150, preferably 30 - 80 and most preferably 40 - 70. HCl is introduced as etching gas, with a flow rate in percentage to the total gas flow rate generally in a range of 7 x 10 -3 - 6 x 10 -4 mol.%, preferably 5 - 1 x 10 -3 mol.% and most preferably 3 - 2 x 10 -3 mol.%. The method of the present invention, for forming the III-V compound semiconductor device, may also be conducted as will be explained in the following, with reference to Figs. 14A to 14H. At first a non-monocrystalline layer 1402 for example of SiO 2 or SiN x constituting a low nucleation density is formed by thermal oxidation, evaporation or sputtering, on a heat-resistant substrate 1401 composed for example of a monocrystalline semiconductive substrate such as monocrystalline Si substrate or monocrystalline GaAs substrate, a non-monocrystalline substrate such as amorphous quartz glass substrate or ceramic substrate, or a high-melting metal substrate such as W or Ti substrate (Fig. 14A). Otherwise, there may be employed, as shown in Fig. 14G, a heat-resistant non-monocrystalline substrate 1408, such as quartz glass substrate, of which surface itself constitutes the non-nucleation surface. Then, on the non-monocrystalline non-nucleation surface 1402 for example of SiO x or SiN x , a non-monocrystalline layer of a high nucleation density, such as of Al 2 O 3 or Ta 2 O 5 , is formed by EB (electron beam) evaporation or resistance-heated evaporation. Then said layer is removed by etching such as RIBE (reactive ion beam etching) or IBE (ion beam etching), leaving areas constituting the nucleation surfaces 1403, which are generally square with a size not exceeding 10 µm, preferably not exceeding 6 µm and most preferably not exceeding 3 µm. Otherwise the nucleation surfaces may be formed by implanting ions such as Al or As ions into small areas by focused ion beam. It is also possible to form a mask leaving small areas, then implanting Al or As ions through said mask into the substrate surface, and then to remove said mask, thereby increasing the nucleation density in said small areas. The non-nucleation surface and the nucleation surfaces may also be formed as shown in Fig. 14H, by depositing a non-monocrystalline layer 1403 of a high nucleation density, for example of Al 2 O 3 or Ta 2 O 5 on a heat-resistant substrate, then depositing a non-monocrystalline layer 1402 of a material such as SiO 2 or SiN x of a nucleation density smaller than that of said non-monocrystalline layer 1403, and selectively removing said layer 1402, constituting the non-nucleation surface, in small areas thereby exposing the nucleation surface in said small areas. The non-monocrystalline layer may be deposited, for example, by EB evaporation, resistance-heated evaporation or sputtering. Then, on the substrate having the non-nucleation and nucleation surface, semiconductor crystals are grown by the MOCVD (metalorganic chemical vapor deposition) (Fig. 14B). The MOCVD can be conducted as explained before, thereby forming n- or p-semiconductor 1404. The conditions of growth depend on and vary according to the apparatus employed. The growth time is determined by the size of the semiconductor device. Subsequently the doping material is changed, thereby forming a semiconductor 1405 of n- or p-type, opposite to the conductive type of the first semiconductor formed in Fig. 14B. The conditions of growth are similar to those explained above (Fig. 14C). Subsequently an electrode 1406 is formed on a part of the crystal formed by MOCVD (Fig. 14D). The electrode may be formed, for example, by resistance-heated evaporation or electron beam-heated evaporation. The patterning of the electrode can be achieved, for example, by a lift-off process of patterning a photoresist layer at first, then forming the electrode and removing the photoresist layer subsequently, or a process of forming the electrode layer over the entire surface and removing said layer in the unnecessary parts. Then, the grown polycrystalline layer is removed in a part of the area other than the electrode areas, thereby exposing the semiconductor of the first conductive type. Said partial removal of the polycrystalline nuclei is conducted by dry etching such as RIBE or IBE, or by wet etching (Fig. 14E). Finally a semiconductor device is obtained by forming an electrode 1407 on thus exposed semiconductor (Fig. 14F). The formation of said electrode may be conducted as explained before. In the following the present invention will be clarified in more details by examples thereof. [Example 1 ] Figs. 10A to 10J are schematic views showing the process of producing an LED of the present invention, employing Ga 0.8 Al 0.2 As polycrystals. (A) On a Mo substrate of a thickness of 0.5 mm, a SiO 2 film 1002 of a thickness of 100 nm (1000 Å), constituting the non-nucleation surface, was deposited by CVD employing SiH 4 and O 2 . The deposition was conducted under the conditions of SiH 4 45 sccm, O 2 60 sccm, N 2 50 sccm, a substrate temperature of 440 °C, an atmospheric reaction pressure and a deposition time of 1 minute. (B) Then a polysilicon film of a thickness of 30 nm (300 Å) was deposited by LPCVD, and photolithographically etched, with etchant of HF : HNO 3 : CH 3 COOH = 1 : 60 : 60, into small squares with a side of 2 µm, constituting nucleation surfaces 1004. The distance between the adjacent nucleation surfaces was 40 µm. The polysilicon film deposition was conducted under conditions of SiH 4 45 sccm, a substrate temperature of 620 °C, and a pressure of 26.7 Pa (200 mTorr). (C) GaAlAs growth was conducted in the above-explained MOCVD apparatus, shown in Fig. 9. (D) At first n-GaAs 1005 was generated on the nucleation surfaces 1004, under the following conditions: TMG 2.4 x 10 -5 mol/min. AsH 3 1.8 x 10 -3 mol/min. SiH 4 (dopant) 9.0 x 10 -6 mol/min. HCl (etching gas) 1 x 10 -5 mol/min. H 2 (carrier gas) 10 l/min. Substrate teperature 775 °C Pressure (20 Torr) 2.7 kPa GaAs was employed because it enables easier selective growth and provides larger crystal grain size at the nucleation, in comparison with GaAlAs. (D) Growth was continued for 10 minutes, until the GaAs crystal islands grew to a diameter of 3 µm. (E) Then TAM was introduced into the raw material gas to grow n-GaAlAs 1006 on the GaAs 1005, under the following film forming conditions: TMG 2.0 x 10 -5 mol/min. TMA 4.0 x 10 -6 mol/min. AsH 3 1.8 x 10 -3 mol/min. SiH 4 (dopant) 9.0 x 10 -6 mol/min. HCl (etching gas) 1 x 10 -5 mol/min. H 2 (carrier gas) 10 l/min. Substrate temperature 775 °C Pressure (20 Torr) 2.7 kPa The growth time was 40 minutes, and the GaAlAs crystal islands grew to a size of 20 µm. (F) The dopant was switched from SiH 4 to DEZ to develop p-GaAlAs 1007. The film forming conditions were same as those in (E), except SiH 4 was replaced by DEZ with a flow rate of 1 x 10 -5 mol/min. The growth was conducted for 15 minutes, whereupon the crystal islands grew to a size of 23 µm. (G) Mechanochemical lapping was conducted with bromomethanol to grind off the surface of the crystal islands by about 7 µm, thereby exposing the internal n-GaAlAs 1006. (H) P-electrodes 1008 were formed by a lift-off process, consisting of forming photoresist patterns and depositing a Cr film of 50 nm (500 Å) and an Au film of 500 nm (5000 Å) in continuation by resistance-heated evaporation. (I) A SiN x insulating film 1009 of a thickness of 400 nm (4000 Å) was deposited by plasma CVD employing SiH 4 and NH 3 , under the conditions of SiH 4 100 sccm, NH 3 200 sccm, a substrate temperature of 350 °C, a pressure of 26.7 Pa (0.2 Torr) and a deposition time of 1 hour. Then contact holes 1010 were formed by photoresist patterning followed by RIE (reactive ion ethcing) with CCl 2 F 2 , under the following etching conditions of CCl 2 F 2 20 sccm, a pressure of 5.3 Pa (4 x 10 -2 Torr), an RF power of 100 W, a substrate temperature at the room temperature, and an etching time of 2 minutes. (J) n-electrodes 1011 were formed by a lift-off process, conducted by photoresist pattern formation followed by AuGe/Au evaporation with resistance heating, with thicknesses respectively of 100 and 500 nm (1000 and 5000 Å). The device structure, after completion, was annealed for 20 minutes at 450 °C in Ar atmosphere. The completed device was powered and subjected to the measurement with a spectrometer and a light power meter. The measurements on 10 devices showed a peak wavelength at 770 nm in the light emission spectrum. When a drive current of 50 mA was applied in pulse form (1 kHz, duration 500 nsec), the light emission intensity was in a range of 0.06 - 0.1 mW. [Example 2] Figs. 11A to llJ are schematic views showing the method of forming an LED device of the present invention, employing GaAsP. polycrystals. (A) On an alumina substrate 1101 of a thick-ness of 0.5 mm, an AlN film 1102 of a thickness of 150 nm (1500 Å), constituting the non-nucleation surface, was deposited by RF sputtering. The deposition was conducted under the conditions of a substrate temperature at the room temperature, a target composed of Al, Ar and N 2 gasses with a flow rate ratio of 2/3, a pressure of 6.7 Pa (5 x 10 -2 Torr), an RF power of 600 W, and a deposition rate of 6 nm/min (60 Å/min). (B) Then an amorphous SiN x film 1103 of a thickness of 30 nm (300 Å) was deposited by plasma CVD, under the conditions of a substrate temperature of 350°C, a reaction pressure of 26.7 Pa (0.2 Torr), with SiH 4 of 100 ccm (cc) and NH 3 of 200 ccm (cc). The SiN x film 1103 was partially removed by photolithographic patterning and reactive ion etching (RIE) to form small square windows of 2 µm with a pitch of 60 µm, thereby exposing AlN, constituting the nucleation surfaces for GaAs. Said reactive ion etching was conducted with CF 4 and O 2 gasses with a flow rate ratio of CF 4 /O 2 = 5/1, under the conditions of a pressure of 186.6 Pa (7 x 10 -2 Torr), an RF power of 100 W and an etching rate of 10 nm/min (100 Å/min). (C) Then the MOCVD was conducted to at first generate n-GaAs crystal nuclei 1104 on the nucleation surfaces 1102, under the following film forming conditions: TMG 2.4 x 10 -5 mol/min. AsH 3 1.8 x 10 -3 mol/min. SiH 4 (dopant) 9.0 x 10 -6 mol/min. HCl (etching gas) 1 x 10 -5 mol/min. H 2 (carrier gas) 10 l/min. Substrate temperature 775°C Pressure (20 Torr) 2.7 kPa (D) Growth was continued for 10 minutes, until the GaAs crystal islands grew to a diameter of 3 µm. (E) Then TBP was introduced into the raw material gas to grow n-GaAsP 1106 on the GaAs 1105, under the following film forming conditions: TMG 2 x 10 -5 mol/min. TBP 7 x 10 -4 mol/min. AsH 3 1.2 x 10 -3 mol/min. SiH 4 (dopant) 5 x 10 -3 mol/min. HCl (etching gas) 1 x 10 -5 mol/min. H 2 (carrier gas) 10 l/min. Substrate temperature 760°C Pressure (28 Torr) 3.7 kPa The growth time was 45 minutes, and the GaAsP crystal islands grew to a size of 22 µm. (F) The dopant was switched from SiH 4 to DEZ to develop p-GaAsP 1107. The growing conditions were same as those in (E), except that SiH 4 was replaced by DEZ with a flow rate of 3 x 10 -6 mol/min. The growth was conducted for 15 minutes, whereupon the crystal islands grew to a size of 25 µm. (G) Surface lapping was conducted with diamond paste with a particle size of 0.3 - 0.8 µm to grind off the surface of the crystal islands by about 6 - 7 µm, thereby exposing the internal n-GaAsP 1106. (H) P-electordes 1108 were formed by a lift-off process, consisting of forming photoresist patterns and depositing a Zn film of 50 nm (500 Å) and an Au film of 800 nm (8000 Å) in continuation by heated evaporation. (I) A SiO 2 film 1109 of a thickness of 500 nm (5000 Å) was deposited by magnetron sputtering, under the depositing conditions of a substrate temperature of 250°C, a target composed of SiO 2 , introduced gas of Ar, a pressure of 0.8 Pa (6 x 10 -3 Torr), an RF power of 1 kW and a deposition rate of 30 nm/min (300 Å/min). Then contact holes 1110 reaching the n-GaAsP 1106 were formed by photoresist patterning followed by etching with an etchant of HF : H 2 O = 1 : 40. (J) After photoresist pattern formation, Au and Sn were co-evaporated from separate sources to a thickness of 100 nm (1000 Å), and then Au alone was evaporated in continuation for obtaining a thickness of 600 nm (6000 Å). Then n-electrodes 1111 were formed by the lift-off process. At the end of the above-explained process, the obtained device was annealed for 20 minutes at 450°C in Ar atmosphere. The completed device was powered and subjected to the measurement with a spectrophotometer and a light power meter. The measurements on 10 devices showed a peak wavelength at 660 nm in the light emission spectrum. When a drive current of 50 mA was applied in pulse form (1 kHz, duration 500 nsec), the light emission intensity was 0.01 - 0.02 mW. [Example 3] Figs. 12A to 12G are schematic views showing the method of producing an LED device of the present invention, employing GaAlAs. (A) On a molybdenum substrate 1201 of a thickness of 0.2 mm, Au ions 1202 were implanted by an ion implater with a concentration of 1 x 10 14 cm -3 , thereby forming a nucleation surface. (B) Then a SiO 2 film 1203 of a thickness of 100 nm (1000 Å) was deposited, as a non-nucleation surface, by CVD employing SiH 4 and O 2 , under the condition of SiH 4 45 sccm, O 2 60 sccm, N 2 50 sccm, a substrate temperature of 440°C, a reaction pressure at atmospheric pressure, and a deposition time of 1 minute. Said SiO 2 film 1203 was photolithographically removed by RED in small squares of a size of 3 µm to expose molybdenum, thus constituting the nucleating surfaces. (C) At first n-GaAs crystal nuclei 1204 were generated on the nucleation surfaces 1201, under the following film forming conditions: TMG 2.4 x 10 -5 mol/min. AsH 3 1.8 x 10 -3 mol/min. SiH 4 (dopant) 9.0 x 10 -6 mol/min. HCl (etching gas) 1 x 10 -5 mol/min. H 2 (carrier gas) 10 l/min. Substrate temperature 775°C Pressure (20 Torr) 2.7 kPa (D) Growth was continued for 10 minutes, until the n-GaS crystal islands 1205 grew to a size of 3 µm. (E) Then TAM was introduced into the raw material gas to grow n-GaAsAs 1206 on the GaAs 1205, under the following film forming conditions: The growth time was 35 minutes, and the GaAlAs crystal islands grew to a size of 18 µm. (F) The dopant was switched from SiH 4 to DEZ to develop p-GaAlAs 1207. The growing conditions were same as those in (E), except that SiH 4 was replaced by DEZ with a flow rate of 1 x 10 -5 mol/min. The growth was conducted for 10 minutes, whereupon the crystal islands grew to a size of 20 µm. (G) After photoresist pattern formation, a Cr film of 50 nm (500 Å) and an Au film of 500 nm (5000 Å) were deposited in continuation by resistance-heated evaporation, and p-electrodes 1208 were formed by lift-off process. Thereafter annealing was conducted for 20 minutes at 450°C in Ar atmosphere. The completed device was powered and subjected to the measurement with a spectrophotometer and a light power meter. The measurements on 10 devices showed a peak wavelength at 770 nm in the light emission spectrum. When a drive current of 50 mA was applied in pulse form (1 kHz, duration 500 nsec), the light emission intensity was 0.03 - 0.06 mW. [Example 4] In the following explained is a method for producing an LED, utilizing stripe-shaped nucleation surfaces. Figs. 13A to 13E are schematic views showing the method of producing an infrared LED of the present invention, utilizing GaAs' polycrystals. (A) On an alumina substrate 1302 of a thickness of 1 mm, a SiO 2 film 1302 of a thickness of 100 nm (1000 Å) was deposited by a method similar to that explained before. (B) Then a polysilicon film was deposited with a thickness of 30 nm (300 Å), and was photolithographically patterned into small rectangles of 2 x 10 µm, constituting nucleation surfaces 1303. (C) On this substrate, n-GaAs 1304 was deposited with a thickness of 15 µm by MOCVD, under the same conditions as in the example 1. (D) Then p-GaAs 1305 was deposited with a thickness of 3 µm, by replacing SiH 4 with DEZ with a flow rate of 2 x 10 -5 mol/min. (E) After photoresist pattern formation, a Cr film of 50 nm (500 Å) and an Au film of 500 nm (5000 Å) were deposited, and p-electrodes 1306 were formed by lift-off process. (F) Surface lapping was conducted in a similar manner as in the example 2, thereby grinding off the surface of the crystal by about 6 µm and exposing the internal n-GaAs 1304. (G) A SiO 2 film 1308 of a thickness of 500 nm (5000 Å) was deposited by magnetron sputtering, and contact holes 1309 were formed by etching in the same manner as in the examples 1 and 2. (H) After photoresist pattern formation, an AuGe alloy film of 50 nm (500 Å) and an Au film of 200 nm (2000 Å) were deposited, and n-electrodes 1307 were formed by lift-off process. Finally annealing was conducted for 20 minutes at 450°C in Ar atmosphere. The completed device was powered and was subjected to measurement with a spectrophotometer and a light power meter. Measurements on 10 devices showed a peak wavelength at 880 nm in the light emission spectrum. When a drive current of 50 mA was applied in pulse form (1 kHz, duration 500 nsec), the light emission intensity was 0.08 - 0.2 mW. [Reference example] In the following description, reference is to be made to Figs. 14A to 14H. On a Si substrate 1401, a SiO 2 layer 1402 and an Al 2 O 3 layer 1403 were formed by EB evaporation, which was conducted, in vacuum of 13.3 mPa (1 x 10 -6 Torr), by supply of oxygen at a rate of 10 ccm/min (cc/min). Then, the Al 2 O 3 layer 1403 was removed by wet etching with an etchant liquid (H 2 SO 4 : H 2 O 2 : H 2 O = 1 : 1 : 2), photolithographically leaving small squares of a size of 0.8 µm with a pitch of 50 µm (Fig. 14A). Then monocrystalline n-GaAs 1404 (impurity concentration : 1 x 10 18 cm -3 ) was grown by MOCVD method, employing TMG (2.4 x 10 -5 mol/min.) and AsH 3 (1.8 x 10 -5 mol/min.), with SiH 4 (8.9 x 10 -6 mol/min.) as dopant and H 2 at 10 l/min. as the carrier gas. The substrate temperature was 670°C, and the pressure was 2.7 kPa (20 Torr). The growth time was 30 minutes. Then the dopant was changed to grow monocrystalline p-GaAs 1405 (impurity concentration: 1 x 10 18 cm -3 ) (Fig. 14B). The growth was conducted by employing TMG (2.4 x 10 -5 mol/min.) and AsH 3 (1.8 x 10 -4 mol/min.), with DEZn (1 x 10 -5 mol/min.) as the dopant and H 2 (10 l/min.) as the carrier gas, and with a temperature of 670°C, a pressure of 2.7 kPa (20 Torr) and a growth time of 15 minutes. Then a photoresist layer of a thickness of 5 µm was formed, except the areas where electrodes are to be formed. Then a Cr 50 nm (500 Å)/Au 500 nm (5000 Å) film 1406 was formed by resistance-heated evaporation, and ultrasonic washing was conducted for 20 minutes in photoresist stripper solution (Fig. 14D). Then RIE (reactive ion etching) was conducted with introduction of CCl 2 F 2 gas at a rate of 20 ccm/min (cc/min.), and with a pressure of 4 Pa, a power of 100 W and an etching time of 3 minutes, until monocrystalline n-GaAs was exposed, utilizing the electrodes as the mask (Fig. 14E). In a part of the exposed area of the monocrystalline n-GaAs of the first conductive type, an electrode was formed (Fig. 14F) by forming an AuGe (2000 Å)/Au (5000 Å) film 1407 in a similar manner to Fig. 14D. A GaAs diode was prepared in this manner. A comparative example involving a planarization step showed peeling of monocrystalline GaAs in about 8 % of the devices at the grinding operation, but, in the method of the present invention, GaAs peeling in the process after the crystal formation was reduced to about 2 %. [Example 5] In the following description, reference is to be made to Figs. 15A to 15H. On a Si substrate 1501, a SiO 2 layer 1502 and an Al 2 O 3 layer 1503 were formed by EB evaporation. The evaporation was conducted under vacuum of 13.3 mPa (1 x 10 -6 Torr), with supply of oxygen at a rate of 10 ccm/min. (cc/min.) Then the Al 2 O 3 layer 1503 was removed by wet etching with etching liquid (H 2 SO 4 : H 2 O 2 : H 2 O = 1 : 1 : 2), photolithographically leaving small squares of a size of 5 µm spaced by a pitch of 50 µm (Fig. 15A). Then polycrystalline n-GaAs 1504 (impurity concentration : 1 x 10 18 cm -3 ) was grown by MOCVD (Fig. 15B). The growth was conducted employing TMG (2.4 x 10 -5 mol/min.) and AsH 3 (1.8 x 10 -5 mol/min.) with SiH 4 (8.9 x 10 -6 mol/min.) as the dopant and H 2 (10 l/min.) as the carrier gas, with a substrate temperature of 670°C, a pressure of 2.7 kPa (20 Torr) and a growth time of 30 minutes. Then the dopant was switched to grow polycrystalline p-GaAs 1505 (impurity concentration : 1 x 10 18 cm -3 ) (Fig. 15C). The growth was conducted employing TMG (2.4 x 10 -5 mol/min.) and AsH 3 (1.8 x 10 -4 mol/min.), with DEZn (1 x 10 -5 mol/min.) as the dopant and H 2 (10 l/min.) as the carrier gas, with a growth temperature of 670°C, a pressure of 2.7 kPa (20 Torr) and a growth time of 15 minutes. Subsequently a photoresist layer of a thickness of 5 µm was formed, excluding areas where electrode are to be formed, and a Cr 50 nm (500 Å)/Au 500 nm (5000 Å) film 1506 was formed by resistance-heated evaporation. Then ultrasonic washing was conducted for 20 minutes in photoresist stripper (Fig. 15D). RIE (reactive ion etching) was conducted by the introduction of CCl 2 F 2 at a flow rate of 20 ccm/min. (cc/min). with a pressure of 4 Pa, a power of 100 W and an etching time of 3 minutes, utilizing the electrodes as the mask, until polycrystalline n-GaAs became exposed (Fig. 15E). In a part of the exposed area of polycrystalline n-GaAs, an electorde was formed by depositing an AuGe 200 nm (2000 Å)/Au 500 nm (5000 Å) film 1507 by a method similar to that in the example 1 (Fig. 15F). A GaAs LED was completed in this manner. Said GaAs LED's were formed as a one-dimensional array as shown in Fig. 15G and employed as an LED head for an electrophotographic printer as shown in Fig. 15H. In this manner the LED array could be mounted, without a large space, in the vicinity of a photosensitive drum 1508, and could also be adhered onto a supporting substrate 1509 with only one optical axis alignment. [Example 6] In the following description, reference is to be made to Figs. 16A to 16H. On a SiO 2 substrate 1601, a poly Si film 1602 of a thickness of 50 nm (500 Å) was deposited by CVD. Then said poly Si film was removed by dry etching, photolithographically leaving small square area 1602 of a size of 5 µm, spaced by a pitch of 50 µm (Fig. 16A). Said dry etching was conducted by the introduction of CF 4 (20 ccm/min. (cc/min.)) and O 2 (2 ccm/min. (cc/min.)), with a pressure of 10 Pa and a power of 100 W. Then polycrystalline n-GaAs 1603 (impurity concentration : 1 x 10 18 cm -3 ) was grown by MOCVD (Fig. 16B). The growth was conducted employing TMG (2.4 x 10 -5 mol/min.) and AsH 3 (1.8 x 10 -5 mol/min.), with SiH 4 (8.9 x 10 -6 mol/min.) as the dopant and H 2 (10 l/min.) as the carrier gas, and with a substrate temperature of 670°C, a pressure of 2.7 kPa (20 Torr) and a growth time of 30 minutes. Then the dopant was switched to grow polycrystalline p-GaAs 1604 (impurity concentration : 1 x 10 18 cm -3 ) (Fig. 16C). The growth was conducted by employing TMG (2.4 x 10 -5 mol/min.) and AsH 3 (1.8 x 10 -4 mol/min.), with DEZn (1 x 10 -5 mol/min.) as the dopant and H 2 (10 l/min.) as the carrier gas, and with a temperature of 670°C, a pressure of 2.7 kPa (20 Torr) and a growth time of 15 minutes. Then a Cr 50 nm (500 Å)/Au 500 nm (5000 Å) film 1606 was formed on the entire area of the substrate by resistance-heated evaporation, and a photoresist layer 1605 was formed only in areas where electrodes are to be formed (Fig. 16D). Subsequently etching was conducted, utilizing said photoresist as the mask, to remove said film 1606, thereby forming electrodes (Fig. 16E). In said etching, Au was removed by iodine-potassium iodine, and then Cr was removed by a solution of phosphoric acid : hydrochloric acid : water = 1 : 1 : 1. Then the polycrystalline n-GaAs was exposed by removal of polycrystalline p-GaAs with a solution of NH 3 OH H 2 O 2 = 1 : 50 (Fig. 16F). The photoresist layer was removed, and a photoresist layer was formed anew excluding areas where the other electrodes are to be formed (Fig. 16G). Then an AUGe 200 nm (2000 Å)/Au 500 nm (5000 Å) film 1607 was formed by resistance-heated evaporation. Then the electrodes were formed by the lift-off process, conducted by the removal of hte photoresist layer (Fig. 16H). A GaAs diode was formed in this manner. [Example 7] LED arrays were formed by arranging 200 light-emitting devices obtained in each of the examples 1 to 4, at a pitch of 80 µm, and an LED printer of the structure shown in Fig. 17 was constructed with each of the above-mentioned LED arrays. In such LED printer, the LED devices were so wired that they could be independently driven. In Fig. 17, there are illustrated an LED array printing head 1701; a photosensitive drum 1702; a developing unit 1703; a transfer unit 1704; a cleaner 1705; a pre-exposure lamp 1706; a charging roller 1707; a fixing unit 1708; toner 1709; and a recording sheet 1710. An image corresponding to electrical signals was formed on the recording sheet when this system was operated, thereby confirming that the LED's of the present invention can function as an optical printing head. [Example 8] Red-color LED display units were prepared by arranging the LED devices, obtained in each of the examples 1 and 3, in a 6 x 6 matrix with a pitch of 1 mm, in which the LED devices were matrix wired to enable independent drive. Fig. 18 schematically illustrates the prepared display unit, wherein shown are a drive unit 1801; a ceramic substrate 1802; an n-electrode wiring 1803; a polycrystalline GaAs/AlGaAs 1804; a p-electrode wiring 1805; and a SiO 2 insulation film 1806. An image was displayed according to electrical signals when this system is operated, thereby confirming that the LED's of the present invention can function as a display device.

Claims: A method for producing a III-V compound semiconductor device, comprising the steps of: providing a substrate surface (101) comprising a non-nucleation surface (103) of a low nucleation density and at least one non-monocrystalline nucleation surface (104) having a nucleation density larger than that of said non-nucleation surface (103), said at least one nucleation surface (104) being patterned in such a size so as to generate plural crystal nuclei crystal growth, wherein the non-nucleation surface (103) and the nucleation surface (104) are positioned in a mutually adjacent manner, conducting polycrystalline growth for forming a III-V compound semiconductor device of polycrystalline structure with an average grain size of 0.6 µm or larger from each of said non-monocrystalline nucleation surfaces (104). A method according to claim 1, wherein said nucleation surface (104) has a small area, formed as a square, a rectangle or a stripe with a side of a width of 1 to 8 µm. A method according to claim 1, wherein said polycrystalline III-V compound includes a p-n junction therein, by suitable addition of dopants in the crystal forming process. A method according to claim 3, wherein said crystal forming process is metal-organic chemical vapor deposition (MOCVD). A method according to claim 4, wherein said MOCVD is conducted in a gaseous atmosphere to which an etching material is added. A method according to claim 5, wherein said etching material is hydrochloric acid (HCl). A method according to claim 1, wherein the isolated crystals are formed in a self-aligned manner on said nucleation surface. A method according to claim 1, further comprising the steps of: forming in desired positions on a substrate having a non-monocrystalline surface, an area of a first conductivity type and an area of a second conductivity type, both composed of a polycrystalline III-V compound semiconductor, the area of the first conductivity type and the area of the second conductivity type being grown from one nucleation surface provided at the desired positions on the substrate; forming a first electrode in a part of said crystalline area of said second conductivity type; removing a portion of the area of the second conductivity type except the area used for the formation of said first electrode, thereby exposing said area of the first conductivity type; and forming a second electrode in the thus exposed area of the first conductivity type. A method according to claim 8, wherein said removal of said portion of said area of the second conductivity type is conducted by selective etching, utilizing the first electrode as a mask. A III-V compound semiconductor device obtained by the method according to any of the preceding claims. A III-V compound semiconductor device according to claim 10, wherein the semiconductor device is a light emitting device. A III-V compound semiconductor device according to claim 11, wherein the semiconductor device is a light emitting diode (LED). A semiconductor device according to claim 10, wherein said III-V compound is selected from GaAs, GaAlAs and GaAsP. An LED printer comprising an LED optical printer head, comprising an LED array consisting of a plurality of the III-V compound semiconductor devices according to claim 12, a photosensitive drum (1702); a developing unit (1703); a transfer unit (1704); a cleaning unit (1705); a pre-exposure lamp (1706); a charging roller (1707); and a fixing unit (1708). An LED device comprising an array of a plurality of the III-V compound semiconductor devices according to claim 12, wherein said III-V compound semiconductor devices are wired in a matrix so as to be independently drivable. An array of III-V compound semiconductor devices as defined in any of claims 10 to 13, which are arranged in a desired number and in desired positions.

Inventors: KAWASAKI HIDESHI, TOKUNAGA HIROYUKI, KAWASAKI, HIDESHI, TOKUNAGA, HIROYUKI, Kawasaki, Hideshi, c/o Canon Kabushiki Kaisha, Tokunaga, Hiroyuki, c/o Canon Kabushiki Kaisha
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1991
Main classification: C30B25
IPC codes: H01L27, C30B25, B41J2, H01L21, H01L33