Semiconductor memory device having reduced parasitic capacities between bit lines

Abstract: In a semiconductor memory device having a memory cell array (MCA) and sense amplifiers (SA₁, SA₂, ...) connected by bit lines (BL₁, BL ₂, ...), a conductive shield plate (SLD) is arranged over the bit lines and between memory cell array and the sense amplifiers.

Description: The present invention relates to a semiconductor memory device, and more particularly, to a dynamic MOS (metal-oxide-semiconductor, broadly MIS) random access memory (RAM) having a highly-integrated configuration. Recently, the integration and density of DRAMs has become greater, and this has given rise to serious problems with regard to the conductor - spacing capacity between internal connections, particularly, the parasitic electrostatic capacity between bit lines. For example, a small difference in potential between two folded bit lines is sensed by a sense amplifier, but a signal on one bit line affects other adjacent bit lines as noise, due to the parasitic electrostatic capacity therebetween, and this leads to an erroneous operation of the sense amplifier. To avoid such an erroneous operation, the following measures have been suggested. 1) A twisted connection method is applied to a pair of folded bit lines to cancel noise due to the parasitic electrostatic capacity therebetween. This is based upon a concept of a twisted pair connection method in telephone lines. In this method, however, due to the complexity of the connections of the bit lines inside of and near the sense amplifiers, it is substantial impossible to apply the above-mentioned twisted connection method to these connections. 2) A configuration and a material are selected that will reduce the parasitic electrostatic capacity between the bit lines. For example, a metal such as polycrystalline silicon and tungsten having a high melting point is used for the bit lines, instead of aluminium. Usually, aluminium is deposited by a sputtering process, and therefore, a layer of aluminium cannot be made too thin as this will lead to many disconnections. Conversely, a high melting point metal can be deposited by a vapor phase growth method such as a chemical vapor deposition (CVD) method, and therefore, a layer of such a metal can be made thin to thus reduce the parasitic electrostatic capacity between the bit lines. Even in this method, when the integration and density of DRAMs is made greater to thereby remarkably increase the number of bit lines, there is a limit to the thickness of the bit lines, since the resistance thereof is thereby remarkably increased. 3) A stacked capacitor-type cell configuration is adopted (see Fig. 3A) to increase the effective capacitance of a cell capacitor, thus obtaining a relatively large difference in potential between the bit lines. Accordingly, such a stacked capacitor cell configuration is not subject to noise due to the parasitic electrostatic capacity between the bit lines. Nevertheless, even in this stacked capacitor-type cell configuration, when the integration and density of DRAMs are made greater, there is a limit to the increase of the capacitance of the cell capacitor. Also, a special stacked capacitor-type cell configuration can be adopted (see Fig. 3 B). That is, bit lines are first formed on a cell transistor portion, and then a capacitor electrode portion (cell plate electrode) is formed over the bit lines, so that a capacitor is created on the bit lines. In this configuration, the cell plate electrode serves as a conductive shield plate for the bit lines, to thereby reduce the parasitic electrostatic capacity between the bit lines. This stacked capacitor cell configuration, however, has not been applied to the bit lines inside of and near the sense amplifiers. 4) The number of sense amplifiers is reduced. That is, in a folded bit line type device, a pair of bit lines, which are complementary to each other, are connected to one sense amplifier, but in this method, two pairs of such bit lines are connected to one sense amplifier. As a result, the pitch of connections within the sense amplifiers is broadened, to thus reduce the parasitic electrostatic capacity between the bit lines. In this case, however, the sense amplifiers are connected to both sides of a memory cell array. Also, a shared sense amplifier configuration can be adopted. In this shared sense amplifier configuration also two pairs of such bit lines are connected to both sides of one sense amplifier, to reduce the number of sense amplifiers. In this configuration, however, the pitch of connections such as bit lines within the sense amplifiers is still small. Further, transfer gates are usually provided on the bit lines between the sense amplifiers and the memory cells, thus complicating an area between the sense amplifiers and the memory cells. Therefore, it is impossible to reduce the parasitic electrostatic capacity between the bit lines, since the bit lines inside of and near the sense amplifiers have a large parasitic electrostatic capacity. An object of the present invention is to further reduce the parasitic electrostatic capacity between the bit lines in DRAMS. According to the present invention, in a semiconductor memory device having a memory cell array and sense amplifiers connected by bit lines, a conductive shield plate is arranged over the bit lines between the memory cell array and the sense amplifiers whereby a shield effect for noise generated between the bit lines is obtained. The present invention will be more clearly understood from the description as set forth below, with reference to the accompanying drawings, wherein: Fig. 1 is a circuit diagram illustrating a general shared sense amplifier type DRAM; Fig. 2A is a layout diagram illustrating a prior art shared sense amplifier type DRAM device; Fig. 2B is an equivalent circuit diagram of the DRAM device of Fig. 2A; Fig. 3A is a cross-sectional view of a memory cell of Fig. 2A; Fig 3B is another cross-sectional view of a memory cell of Fig. 2A; Fig. 4A is a layout diagram illustrating a first embodiment of the DRAM device according to the present invention; Fig. 4B is an equivalent circuit diagram of the DRAM device of Fig. 4A; Figs. 4C and 4D are cross-sectional views of the device of Fig. 4A; Fig. 5A is a layout diagram illustrating a second embodiment of the DRAM device according to the present invention; Fig. 5B is an equivalent circuit diagram of the DRAM device of Fig. 5A; Fig. 5C is a timing diagram showing the operation of the device of Fig. 5A; Fig. 6 is an equivalent circuit diagram illustrating a third embodiment of the DRAM device according to the present invention; Fig. 7 is a layout diagram illustrating a fourth embodiment of the DRAM device according to the present invention; Figs. 8A, 8B and 8C are timing diagrams showing the signals of Fig. 7; Fig 8D is a circuit diagram of a circuit for generating the signal  SD of Fig. 7; Fig. 9 is a layout diagram illustrating a fifth embodiment of the DRAM device according to the present invention; Fig. 10 is a detailed layout diagram of the DRAM device of Fig. 9; Fig. 11A is a modification of Fig. 4A; Fig. 11B is a modification of Fig. 4B; Fig. 12A is a diagram illustrating a modification of Fig. 5A; Fig. 12B is a cross-sectional view of the device of Fig. 12A; Fig. 13A is a modification of Fig. 12A; and Fig. 13B is a modification of Fig. 12B. DESCRIPTION OF THE PREFERRED EMBODIMENTS Before the description of the embodiments of the present invention, a prior art DRAM device will be explained below. Figure 1 illustrates a prior art DRAM device, which is a shared sense amplifier type device having, two memory cell arrays MCA and MCA′ are arranged on both sides of sense amplifiers SA₁, SA₂, ..., and SA m , and two pair of folded bit lines such as BL₁ and BL ₁′, and BL₁′ and BL ₁ are connected to one of the sense amplifiers such as SA₁. Reference numeral 1 designates an address multiplexer for receiving address signals A₁ through A n from the address buffer (not shown) to generate multiple X-address signals AX₁ through AX n and Y-address signals AY₁ through AY n . Reference numerals 2 and 2′ designate row decoders for selecting one of the word lines WL₁, WL₂, ... (or WL₁′, WL₂′, ...) of the memory cell arrays MCA and MCA′ in accordance with the X-address signals AX₁ through AX n . Reference numeral 3 designates a column decoder for selecting one pair of the bit lines such BL₁ and BL ₁ (BL₁′ and BL ₁′) of the memory cell arrays MCA and MCA′ in accordance with the Y-address signals AY₁ through AY n . Reference numeral 4 designates a clock generator for generating a clock signal BT or BT′ in accordance with the X-address signal AX n and the clock signal  s from the RAS clock system (not shown). Also, transfer gates Q T and Q T ′ are provided on the bit lines BL₁, BL ₁, ..., BL₁′, BL ₁′, ... between the sense amplifiers SA₁, SA₂, ..., SA m and the memory cell arrays MCA and MCA′. Further, one-transistor, one-capacitor type memory cells such as MC₁₁ are provided mosaicly at intersections between the word lines and the bit lines. In Fig. 2A, which is a layout diagram of a prior are shared sense amplifier type DRAM device and in Fig. 2B, which is a partial equivalent circuit diagram of the device of Fig. 2A, each of the sense amplifiers SA₁, SA₂, ... is formed by two cross-coupled N-channel MOS transistors Q ns and Q ns ′, which are enabled by a low potential of a clock signal NSA. In this case, each of the sense amplifiers also has two cross-coupled P-channel MOS transistors Q ps and Q ps ′, which are enabled by a high potential of a clock signal PSA, (not shown in Figs. 2A and 2B, but shown in Figs. 11A and 11B). Also, the memory cell array MCA has a cell plate CP common to all memory cells. This cell plate CP serves as a conductive shield plate for reducing the parasitic electrostatic capacity between the bit lines such as BL₁ and BL ₁, as showns in Figs. 3A and 3B, which illustrate one memory cell. In Fig. 3A, impurities such as phosphorus or arsenic are doped into a P⁻-type monocrystalline silicon substrate SUB to obtain a source region S and a drain region D, thus forming a cell transistor. Also, a word line WL₁, which serves as a gate electrode, is formed by depositing polycristalline silicon with a CVD method via the gate insulator (not shown) on the substrate SUB. Further, a storage electrode SE is formed by depositing polycrystalline silicon by a CVD method via a through hole TH on the source region S, and a common cell plate CP is formed opposite to the storage SE, with the insulating layer (not shown) therebetween, thus forming a cell capacitor. In Fig. 3A, a bit line such as BL₁ is formed on the cell plate CP. Therefore, in this case, the cell plate CP cannot properly serve as a conductive shield layer for the bit lines, since the cell plate CP covers only a part of the lower surface of the bit lines. Conversely, in Fig. 3B, after a cell transistor is formed, a common cell plate CP is formed thereon, so that the common cell plate CP completely covers the memory cell array MCA, particularly, the bit lines within the memory cell array MCA. Also, since the cell plate CP covers the both sides of the bit lines as well as the upper surface thereof, the shield effect of the cell plate CP against the bit lines is remarkably increased compared with that of the cell plate CP of Fig. 3A. This contributes to the reduction of the parasitic electrostatic capacity between the bit lines. Note that, if the device of Fig. 2A is manufactured by a CMOS technology, the memory cell array MCA, the transfer gates Q T and Q T ′, and one part sense amplifiers SA₁, SA₂, ... enabled by the clock signal NSA are formed on a P-well, and therefore, a bias voltage V BB is applied thereto. Also, in this case, the substrates SUB of Figs. 3A and 3B are formed by the P-well. In the device of Fig. 2A using the memory cells of Fig. 3B, however, since a portion indicated by CL is not covered by the cell plate CP, the reduction of the parasitic electrostatic capacity CBB between the bit lines is still insufficient. In Fig. 4A, which is a layout diagram illustrating a first embodiment of the present invention, and in Fig. 4B, which is an equivalent diagram of Fig. 4A, a conductive shield plate SLD is added to the device of Figs. 2A and 2B. This conductive shield plate SLD covers the portion CL in which the transfer gates Q T and the bias voltage line for V BB are formed. In this case, the cell plate CP of Fig. 3B is used, as illustrated in Fig. 4C. Therefore, the conductive shield plate SLD is integrated with the cell plate CP of the memory cell array MCA, i.e., the conductive shield plate SLD and the cell plate CP are made of the same metal layer such as polycrystalline, and therefore, the addition of the conductive shield plate SLD is carried out without increasing the number of manufacturing steps. As illustrated in Fig. 4C, a well bias voltage line V BB , which is made of aluminium, is deposited via a well contact WC to the P-well region. The voltage of the well bias voltage line V BB is, for example, -1.5 V. In practice, however, as illustrated in Fig. 4D, two separate well bias voltage lines V BB1 and V BB2 , having voltages 0 V and -1.5 V respectively, are connected to the P-well region for the transfer gates Q T and the P-well region for the memory cell array MCA. That is, the higher threshold voltage V BB1 (=OV) reduces the thereshold voltage of the transitors of the sense amplifiers SA to enhance the operation speed thereof, while the lower threshold voltage V BB2 (=-1.5V) increases the threshold voltage of the transistors of the memory cell array MCA to reduce the leackage current therefrom. In Figs. 4C and 4D, the width of each bit line is about 1µm, and the thickness thereof is about 0.2 µm. Also, the spacing between the bit lines is about 1.5 µm. According to the device of Figs. 4A through 4D, the parasitic electrostatic capacity CBS between the conductive shield plate SLD including the cell plate CP and each bit line is increased to thus reduce the parasitic electrostatic capacity CBB between the bit lines. As a result, a potential at one bit line generated during a read operation has little affect on potentials at other adjacent bit lines. Namely, each bit line is able to withstand the affects of noise generated at bit lines adjacent thereto, and thus an erroneous write operation due to a read operation can be avoided. Note that the above-mentioned parasitic electrostatic capacity CBS of the bit lines due to the conductive shield plate SLD (and CP) cannot lead to the above-mentioned erroneous operation, since noise generated by the parasitic electrostatic capacity CBS of each bit line is compensated at the conductive shield plate SLD and the cell plate CP. In Figs. 5A and 5B, which illustrate a second embodiment of the present invention, the conductive shield plate SLD is separate from the cell plate CP and is connected to a power supply source such as the ground. Nevertheless, the conductive shield plate SLD and the cell plate CP are made of the same material as used in the first embodiment of Figs. 4A through 4D. The separation of the conductive shield plate SLD and the cell plate CP is particularly effective when the amplitude of the restore voltage at the bit lines is different from the amplitude of the sense voltage of the sense amplifiers. For example, as shown in Fig. 5C, assuming that a reset voltage for the bit lines is 0.8 V, and a restore voltage, i.e., a rewritten voltage of "1", is 1.6 V, and further, that a reset voltage for the sense amplifiers is assumed to be 0.8 V. In this case, to enhance the drive power of the data buses (not shown) selectively connected to one pair of bit lines, the drive of the sense amplifiers is carried out by using an external power supply voltage such as 3.3 V, and thus the sense voltage is amplified to 3.3 V. To suppress the transfer of such a high voltage of 3.3 V to bit lines having a "1" level of only 1.6 V, the gate voltage BT of the transfer gates Q T is restricted to 1.6 V. Therefore, the mean voltage of the bit lines within the sense amplifiers is increased from 0.8 V (reset mode) to 1.65 V (= 3.3/2) (sense operation mode), and as a result, the conductive shield plate SLD receives this increase of voltage due to the parasitic electrostatic capacity CBS as a noise voltage. If the cell plate CP is connected to the conductive shield plate SLD, this noise voltage is transmitted as a bump noise to the cell plate CP, and thus leads to a change of the charges stored in the memory cells. The device of Figs. 5A and 5B stops the affect of such a bump noise on the memory cells. In Fig. 6, which is a third embodiment of the present invention, a resistor R SD is inserted between the conductive shield plate SLD and the ground in Figs. 5A and 5B. If the resistor R SD is not included, as in the device of Figs. 5A and 5B, when the sense amplifier is operated so that a noise supplied to the conductive shield plate SLD is supplied directly to the power supply such as the ground, such a noise also is transferred in other circuits, via the power supply. To avoid this, the resistor R is provided to smooth the noise with a time constant τ determined by CBS x R SD x n, where n is the number of bit lines. If this time constant is too large, however, a shield effect of the conductive shield plate SLD is reduced. Note that this shield effect is used to release a noise applied thereto to the power supply without releasing the noise to other adjacent bit lines. Therefore, the above-mentioned time constant τ must be smaller than a value which corresponds, for example, to a half of a cycle time of a row address strobe (RAS) signal. Note that the resistor R SD can be introduced into the conductive shield plate SLD, if the conductive shield plate SLD is made of high resistance polycrystalline silicon. In Fig. 7, which is a fourth embodiment of the present invention, an N-channel MOS transistor Q SD is added to the device of Fig. 6, and the transistor Q SD is controlled by a clock signal  SD , which is turned OFF after the activation of the sense amplifiers before a completion of the operation of the sense amplifiers. The clock signal  SD is explained with reference to Figs. 8A through 8C. As shown in Fig. 8A, for a time period (several nanoseconds) (t₁ - t₂) after the RAS signal is received, the clock signal  SD remains high and the transistor Q SD is turned ON, i.e., the conductive shield plate SLD is grounded to thereby exhibit a shielding effect. At a time t₂, the state of the sense amplifiers is determined, the conductive shield plate SLD is no longer present, and the clock signal  SD falls to turn OFF the transistor Q SD . As a result, the conductive shield plate SLD becomes substantially in a floating state, due to the OFF state of the transistor Q SD , and therefore, when the mean voltage of the bit lines near the sense amplifiers is increased from 0.8 V to 1.65 V, the voltage of the conductive shield plate SLD follows this mean voltage, as shown in Figs. 8B and 8C. At a time t₃, when the signal RAS rises to complete a RAS cycle as shown in Fig. 8A, the sense voltages of the sense amplifiers are reset to 0.8 V as shown in Fig. 8B, and accordingly, the voltage of the conductive shield plate SLD falls as shown in Fig. 8C. Finally, at a time t₄, the clock signal  SD returns to the initial stage. Note that the clock signal  SD can be easily obtained by using a circuit as illustrated in Fig. 8D. In Fig. 8D, 81 designates a delay circuit, 82 an invester, 83 a resistor, 84 a capacitor, 85 an invester, and 86 a NAND circuit. Thus, according to the device of Fig. 7, the change of the voltage of the conductive shield plate SLD due to the change of the mean voltage of the bit lines near the sense amplifiers is not led to the power supply (the ground), and thus the power consumption is reduced. Note, in Fig. 7, the resistor R SD can be omitted, i.e., the above-mentioned time constant τ has a lower limit equal to a half of a RAS cycle, but has no upper limit, and therefore, the value of the resistor R SD can be made infinite, i.e., the resistor R SD can be omitted. In Figs. 9 and 10, which show a fifth embodiment of the present invention, the conductive shield plate SLD also covers the sense amplifier portion SA, to further exhibit a shield effect for noise generated between the bit lines. Particularly, in Fig. 10, active areas for the source and drain regions of the cell transistors are indicated by AR. In Figs. 11A and 11B, which are modifications of Figs. 4A and 4B, P-channel MOS transistors Q ps and Q ps ' are added to each of the sense amplifiers SA₁, SA₂, Also, in Fig. 12A, which is a modification of Fig. 5A, P-channel MOS transistors Q ps and Q ps ' are added to each of the sense amplifiers SA₁, SA₂ , ... The P-channel transistors Q ps and Q ps ' are enabled by a low potential of a clock signal PSA. Figure 12B is a cross-section view of Fig. 12A, the P-channel transistor of the sense amplifier portion SA, the transfer gate portion CL', and the memory cell array MCA' are also illustrated in addition to Fig. 4D. Further, in Figs. 13A and 13B, which are modifications of Figs. 12A and 12B, an open bit line type device is illustrated. In this device, the transfer gates Q T and Q T ' are unnecessary. Note, the present invention obviously can be applied to a simple folded bit line type DRAMs. As explained above, according to the present invention, since the parasitic electrostatic capacity between the bit lines can be reduced by the conductive shield plate, an erroneous operation due to noise between the bit lines can be avoided. Also, since the provision of the conductive shield plate does not increase the occupied area of the device, the integration thereof is not reduced.

Claims: A semiconductor memory device, comprising a plurality of bit lines (BL₁, BL₁', ...); a plurality of word lines (WL₁, WL₂, ...); a memory cell array (MCA) including memory cells connected between said bit lines and word lines; a plurality of sense amplifiers (SA₁, SA₂, ...) connected to said bit lines, for sensing potentials at said bit lines; characterized by a conductive shield plate (SLD), arranged over said bit lines and arranged between said memory cell array and said sense amplifiers, for exhibiting a shield effect for noise generated between said bit lines. A device as set forth in claim 1, wherein said memory cells are a DRAM type having a common cell plate (CP), said conductive shield plate being electrically separated from said common cell plate. A device as set forth in claim 1, wherein said memory cells are a DRAM type having a common cell plate, said conductive shield plate being integrated with said common cell plate. A device according to any of the preceding claims, further comprising an insulating layer interposed between said bit lines and said conductive shield plate. A device according to claim 4, when dependant on claim 3, wherein said memory cells are a stacked capacitor type in which said common cell plate is arranged over said bit lines with the insulating layer therebetween. A device according to any of the preceding claims, wherein the conductive shield plate is arranged over the sense amplifiers. A device according to any of the preceding claims, wherein the conductive shield plate is connected directly or indirectly to a power supply. A device as set forth in claim 7, wherein said conductive shield plate is connected via a resistor (R SO ) to said power supply. A device as set forth in claim 7 or claim 8, wherein said power supply means is the ground. A device as set forth in claim 8, further comprising a switch (Q SD ), connected in parallel with said resistor, said switch being turned OFF after activation of said sense amplifiers before a completion of a sense operation by said sense amplifiers, said switch being turned ON after resetting said sense amplifiers. A device as set forth in claim 8, further comprising a switch (Q SD ), connected between said conductive shield plate and said power supply, said switch being turned OFF after activation of said sense amplifiers before a completion of a sense operation by said sense amplifiers, said switch being turned ON after resetting said sense amplifiers. A device according to any of the preceding claims, wherein said bit lines are a shared type in which folded bit lines are arranged on both sides of said sense amplifiers, and transfer gates (Q T , Q T ′) are interposed at said bit lines between said sense amplifiers and said memory cells, said conductive shield plate being arranged over said transfer gates. A device according to any of claims 1 to 11, wherein said bit lines are a folded type in which folded bit lines are arranged on one side of said sense amplifiers. A device according to any of claims 1 to 11, wherein said bit lines are an open type in which bit lines and their corresponding bit lines are arranged on bot sides of said sense amplifiers.

Inventors: TAGUCHI MASAO, TAGUCHI, MASAO
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1991
Main classification: G11C7
IPC codes: G11C11, G11C7, H01L27, H01L21