Method of manufacturing field effect transistors

Abstract: A method of producing a field effect transistor includes forming a first conductivity type active layer having a first concentration of dopant impurities producing the first conductivity type in a semi-insulating semiconductor substrate, forming a mask film on the substrate on part of the first conductivity type region, depositing a gate metal film on the mask film and on the substrate not covered by the mask film, etching the gate metal film and leaving a portion of the gate metal film on the substrate adjacent to and contacting the mask film as a gate electrode, implanting dopant impurities producing a second conductivity type in the substrate using the mask film and the gate electrode as an implantation mask, annealing the substrate at an elevated temperature to activate the implanted dopant impurities whereby some of the implanted dopant impurities diffuse laterally within the substrate to produce a second conductivity type region in the substrate underneath part of the gate electrode, removing the mask film, implanting dopant impurities producing the first conductivity type in the substrate using the gate electrode as an ion implantation mask to produce first and second doped regions in the substrate on opposite sides of the gate electrode and having a second concentration of dopant impurities larger than the first concentration, the second doped region being disposed within the second conductivity type region that extends underneath part of the gate electrode, and forming a source electrode on the first doped region and a drain electrode on the second doped region.

Description: Field Of The Invention The present invention relates to a method of manufacturing field effect transistors (FETs) and particularly compound semiconductor FETs having self-aligned gates in which the short channel effect is suppressed and the capacitance between the source and gate is limited. Background Of The Invention A known method of making a lightly doped drain (LDD) gallium arsenide (GaAs) FET is illustrated in Figures 2(a)-2(g). In Figure 2(a), a semi-insulating GaAs substrate 1 has an active layer 2', usually n-type, formed by a known technique, such as ion implantation, diffusion, or epitaxial growth. As shown in Figure 2(a), the active layer 2 appears to be disposed on the substrate 1 which is the situation when the active layer 2 is formed by epitaxial growth. Otherwise, the active layer 2 is an integral part of the substrate 1 and is disposed at a surface of the substrate. In this application, the active layer 2 is referred to as part of the substrate with the understanding that it may be a distinct layer if epitaxially grown. As illustrated in Figure 2(b), a film 3 (not shown) of a gate metal, such as a refractory metal like tungsten (W) or a refractory metal silicide such as tungsten silicide (WSi x ), is deposited on the surface of the substrate 1 by a known technique, such as sputtering or vapor deposition. A photoresist film 4 (not shown) is deposited on the gate metal film 3 and patterned by conventional photolithographic processing to produce a mask 4' where a gate electrode is to be present. Thereafter, the gate metal film 3 is etched by reactive ion etching (RIE), for example, using sulfur hexafluoride (SF 6 ) or a mixture of carbon tetrafluoride (CF 4 ) and oxygen (0 2 ). After the etching, a gate electrode 3' is left on the surface of the substrate. Subsequently, the photoresist mask 4' is removed and, as indicated in Figure 2(c), dopant impurities producing the same conductivity type as the conductivity type of the-active layer 2 are implanted in the substrate 1. The gate electrode 3' functions as an implantation mask so that the doped regions 5 and 5' on opposite sides of the gate electrode 3' are formed. In accordance with conventional processing, an annealing step follows in which the temperature of the substrate is raised to activate the implanted dopant impurities and to repair crystalline damage inflicted by the ion implantation step. The doped regions 5 and 5' have a dopant concentration larger than that of the active layer 2. A film 6, shown in Figure 2(d), preferably an electrically insulating film, is deposited on the surface of the substrate 1 and on the gate electrode 3' by a conventional process, such as vapor deposition. The film is etched by RIE. As well known in the art, by controlling the degree of etching, the film 6 can be removed from the gate electrode 3' and from the surface of the substrate 1, leaving side wall films 6' disposed on the surface of the substrate, adjacent to and contacting opposite sides of the gate electrode 3', as shown in Figure 2(e). Generally, those side wall films 6' have a width comparable to the thickness of the film 6. The gate electrode 3' and the side wall films 6' are used as an implantation mask and, in another implantation step, dopant impurities producing the same conductivity type as the conductivity type of the active layer 2 are implanted in the substrate. This implantation step produces doped regions 7 and 7' on opposite sides of the gate electrode 3' and the side wall films 6'. The dopant impurity concentration within regions 7 and 7' is larger than the dopant concentration in the regions 5 and 5'. Portions of the doped regions 5 and 5' protected by the respective side wall films 6' are left in the substrate adjacent to and electrically connecting the doped regions 7 and 7' to the active layer 2, respectively. The resulting structure appears in Figure 2(f). Finally, as shown in Figure 2(g), the FET is completed by the formation of source and drain electrodes 8a and 8b in contact with the most heavily doped regions 7 and 7', respectively. Regions 7 and 7' are the source and drain regions, respectively, of the FET. The LDD FET structure of Figure 2(g) is useful in suppressing the short channel effect in FETs that causes variations in the threshold voltage of the transistor as the gate length becomes smaller than a few micrometers (microns). In addition, the short channel effect causes the threshold voltage of the FET to depend upon the voltage between the source and drain, affects the current cut-off capability of the FET, and increases the drain conductance. These effects still appear in LDD FETs having gate lengths below about 1 micron. In the FET shown in Figure 2(g), current leakage through the semi-insulating GaAs substrate 1 between the doped regions 5, 5', 7, and 7' directly below the active layer 2 contribute to the undesirable characteristics collectively referred to as the short channel effect. An additional known FET structure for suppressing the short channel effect by preventing the flow of leakage currents in a semi-insulating substrate is shown in cross-section in Figure 3. That FET has the same structure as the transistor of Figure 2(g) and additionally includes a doped region 9 within the substrate adjacent to and contacting each of the regions 7, 5, 5', and 7' as well as the active layer 2. The doped region 9 has a conductivity type opposite the conductivity type of the active layer 2 and the regions 7, 5, 5', and 7', thereby forming a large area pn junction. The pn junction prevents the flow of leakage current within the substrate and further suppresses the short channel effect for gate lengths as short as about 0.5 micron. However, the presence of the doped region 9 in the substrate forming a relatively large area pn junction significantly increases the capacitance between the source and gate electrodes 8a and 3'. The increased capacitance limits the upper end of the frequency range in which the FET can be used. In order to overcome the reduction in frequency range brought about by the inclusion of the doped region 9 in the substrate 1, the FET structure shown in Figure 4 has been proposed. In the structure of Figure 4, the doped region 9 within the substrate 1 is present in the substrate only beneath and contacting the doped regions 5' and 7' and a part of the active layer 2 that is near the interface of the active layer 2 and the doped region 5'. Because the doped region 9 is not present beneath the source region 7, the capacitance between the source electrode 8a and the gate electrode 3' is not substantially increased by the presence of the doped region 9. However, the doped region 9 substantially prevents the flow of leakage current through the substrate because of the pn junction interposed between the doped regions on the source side of the FET and the doped regions on the drain side of the FET. Thus, the short channel effect is minimized without adversely affecting the high frequency performance of the FET. A method of making the FET structure of Figure 4 is illustrated in Figures 5(a)-5(g). Initially, as indicated in Figure 5(a), an ion implantation mask 11 is formed. A photoresist film (not shown) is deposited and patterned using conventional techniques to produce the photoresist ion implantation mask 11. Afterwards, ions producing the second conductivity type region 9, usually a p-type region, are implanted in the substrate 1. Mask 11 is removed and subsequently the steps illustrated in Figures 2(b)-2(g) are carried out as illustrated and described with respect to Figures 5(b)-5(g). Since those steps have already been described, it is not necessary to describe them again. However, in carrying out those steps, particularly the step illustrated in Figure 2(b) as applied in Figure 5(b), a mask alignment step is required. In order to produce the structure of Figure 4, the doped region 9 must extend slightly beneath the gate electrode 3'. In other words, the photoresist pattern 4' used to define the gate 3' must be aligned with the buried doped region 9 that has already been formed in the substrate. If the alignment is not precisely made, the structure of Figure 6, rather than the structure of Figure 4, may be produced. In the structure of Figure 6, the doped region 9 is present within the substrate 1 only adjacent part of the doped region, i.e., the drain region, 7'. Part of the doped regions 5' and 7' are still in direct contact with the semi-insulating substrate 1 and leakage currents can still flow through the substrate 1 between the source region 7 and drain regions 7'. Alternatively, as shown in Figure 7, if an alignment error opposite in direction from the error that produces the structure of Figure 6 occurs, the doped region 9 may extend all the way to the source region 7, causing an undesired increase in source-to-gate capacitance. As is apparent from the foregoing discussion, a method of producing the structure of Figure 4 without the problem of aligning a gate electrode mask with the doped region 9 is desired in order to produce the structure of Figure 4 reliably, minimising the short channel effect in narrow gate FETs without adversely affecting the high frequency performance of those transistors. EP-A-0181091 discloses a construction in which a barrier layer is formed under both the source and the drain regions. Relevant details of the method disclosed therein are reproduced in the preambles of claims 1 and 2 attached. Summary of the Invention An object of the present invention, which is defined in the claims appended hereto, is to provide a method of producing an FET including, in a semi-insulating substrate, a doped region that is precisely located with respect to the drain region so that leakage current flow through the substrate between the source and drain regions is minimised without increasing the capacitance between the source and drain electrodes. It is an important object of the invention that the method reliably and precisely reproduces the doped region relative to the drain region without the requirement of a mask alignment step. Other objects and advantages of the present invention will become apparent from the detailed description that follows. Brief Description of the Drawings Figures 1(a)-1(i) are sectional views illustrating a method of producing an FET according to an embodiment of the present invention. Figures 2(a)-2(g) are sectional views illustrating a method of producing an FET according to the prior art. Figure 3 is a cross-sectional view of a prior art FET. Figure 4 is a cross-sectional view of an FET that can be produced according to the present invention. Figures 5(a)-5(g) illustrate a prior art method of making the FET of Figure 4. Figures 6 and 7 are cross-sectional views of FETs that may be produced by the process illustrated in Figures 5(a)-5(g) when mask alignment errors occur. Description Of Preferred Embodiments Figures 1(a)-1(i) illustrate a method of manufacturing an FET according to the present invention. In these and all other figures, the same reference numbers are given to corresponding elements. Accordingly, it is not necessary to describe in detail the elements of Figures 1(a)-1(i) that have already been described with respect to other figures. In Figure 1(a), an active layer 2 has been formed in a semi-insulating compound semiconductor substrate 1, specifically a GaAs substrate, preferably by ion implantation. The active layer 2 may also be formed by the diffusion of dopant impurities into the substrate 1 or by epitaxial growth at the surface of the substrate. The active layer 2 contains dopant impurities producing a first conductivity type, generally n-type. For example, silicon (Si) ions may be implanted as a dopant impurity in GaAs to form the active layer 2. The Si ions are accelerated to about 50 kev and have a flux density of about 1.5 x 10 12 ions/cm 2 . The resulting active layer 2 is about 80 nanometers (nm) deep. Subsequently, a first mask film 10 (not shown), preferably of an electrically insulating material, that can function as an ion implantation mask is deposited on the active layer using a conventional process, such as a plasma chemical vapor deposition (CVD) process. The mask film 10 may be, for example, SiO x , SiO 2 , or SiN x . The mask film 10 is etched, for example, by RIE, using a conventional technique, for example,-in a mixture of equal quantities of SiF 6 and helium (He), at a pressure of 0.3 Torr with about 50 watts of radio frequency (RF) power supplied to the plasma. After the etching, an ion implantation mask 10' is left on part of the surface of the substrate 1. A gate metal film 3, for example, of a refractory metal or a refractory metal silicide, such as W or WSi x , is deposited over the mask 10' and the exposed surface of the substrate 1, as shown in Figure 1(b). The refractory metal or refractory metal silicide film may be deposited by known processes, including DC sputtering at about 400 watts power in argon (A) at a pressure of about 10 mTorr or by vapor deposition. The gate metal film 3 is etched by RIE so that the metal is substantially completely removed from the mask 10' and from most of the surface of the substrate 1, leaving a gate electrode 3' in place on the surface of the substrate 1 adjacent to and contacting the first film mask 10'. The refractory metal or refractory metal silicide gate metal film may be etched in a mixture of CF 4 and four percent O 2 driven by about 75 watts of RF power or in SF 6 . The gate length of the gate electrode 3', i.e., the dimension along the surface of the substrate 1 shown in Figure 1(c), is approximately the thickness of the gate metal film 3. Accordingly, a submicron gate width can be produced in the invention. The doped region 9 of a second conductivity type, opposite the conductivity type of the active layer 2, is formed by ion implantation, as illustrated in Figure 1(d). Before the removal of the first film mask 10', that mask and the gate electrode 3' are used as an ion implantation mask and dopant impurities producing the second conductivity type in the substrate are implanted to form region 9. For example, when region 9 is p-type, magnesium (Mg) ions having an energy of about 300 keV and a flux density of about 4 x 10 12 ions/cm 2 are implanted. Those ions produce a region 9 having a depth of approximately 800 nm. In order to activate those ions and repair crystalline damage produced by the ion implantation, the structure of Figure 1(d) is annealed. During that elevated temperature annealing step, the implanted ions diffuse within the substrate 1. As shown in Figure 1(e), that diffusion carries the doped region 9 laterally under a portion of the active layer 2 beneath the gate electrode 3'. Following the annealing step, the film mask 10' is removed by etching, preferably by wet etching. Using the gate electrode 3' as an ion implantation mask, first and second doped regions 5 and 5' are formed in the substrate on opposite sides of the gate electrode 3'. The impurity dopant concentration in regions 5 and 5' is higher than the dopant concentration of the active layer 2. The first and second doped regions 5 and 5' may be formed, for example, by implanting Si ions having an energy of about 60 keV and a flux density of about 2 x 10 12 ions/cm 2 . Using these conditions, the regions 5 and 5' extend from the surface of the substrate 1 to a depth of about 100 nm. As is apparent from Figure 1(e), because the second conductivity type doped region 9 extends partially underneath the gate electrode 3' and the gate electrode 3' functions as an ion implantation mask in the formation of the first conductivity type doped region 5', the region 5' is confined within the doped region 9. In other words, the method is self-aligning with respect to ensuring that the first-conductivity type doped region 5' is isolated from the substrate 1 by the second conductivity type doped region 9. Following the ion implantation step producing the doped regions 5 and 5', another annealing step is carried out to activate the implanted dopant impurities, to repair crystalline damage, and to complete the structure shown in Figure 1(e). The structure of Figure 1(e) can be employed as a completed FET if source and drain electrodes 8a and 8b are formed on the doped regions 5 and 5' as the source and drain regions, respectively. If the structure of Figure 1(e) is used directly, after the application of electrodes, as an FET, it is desirable to increase the doping concentration of regions 5 and 5' over that previously described. For example, the dopant concentration levels of the doped regions 7 and 7' described below would preferably be used to produce an FET without an LDD feature. The steps described below with respect to Figures 1(f)-1(h) are employed to produce an FET including an LDD feature. Turning to Figure 1(f), a second mask film 6, preferably an electrically insulating film of the same composition of the first film mask 10, is deposited on the surface of the substrate 1 and the gate electrode 3'. The second mask film 6 is anisotropically etched, for example, by RIE, in a plasma formed in a gas mixture of CHF 6 and ten percent O 2 at a pressure of about 1.0x10 4 Pa (75 Torr) and driven by RF power of about 100 watts. That etching removes the film 6 from the surface of the substrate and the top surface of the gate electrode 3', leaving in place portions 6' on the surf-ace of the substrate and adjacent to the gate electrode 3' at each of two opposite sides. These side wall films 6', shown in Figure 1(g), function as ion implantation masks in the third and final ion implantation step. That third ion implantation step is illustrated in Figure 1(h) in which dopant impurities producing in the substrate the first conductivity type are implanted using the gate electrode and side wall films 6' as a mask. As an example, Si ions may be implanted at an energy of about 150 keV and a flux density of about 3 x 10 13 ions/cm 2 , producing the doped regions 7 and 7' shown in Figure 1(h) to a depth of about 120 nm. The dopant impurity concentration in regions 7 and 7' exceeds the dopant concentrations in regions 5 and 5'. Residual portions of those doped regions 5 and 5' are thus sandwiched between the active layer 2 and regions 7 and 7', respectively, to form an LDD FET structure. After a final annealing step to activate the implanted ions, a source electrode 8a is deposited on the doped region 7, i.e., the source region, and a drain electrode 8b is formed on the doped region 7', i.e., the drain region. As shown in Figures 1(h) and 1(i), because the depth of the doped region 7' is shallower than that of the doped region 9, the second conductivity type doped region 9 envelopes both the residual region 5' and the region 7' so that no leakage current can flow through the semi-insulating substrate 1 directly between the source region 7 and the drain region 7' or the intermediately doped region 5'. The process described for producing the FET structure of Figure 4, whether the LDD elements 5 and 5' and masking film portions 6' are present, does not rely on or require any photolithographic mask alignment steps that could result in the undesired FET structures illustrated in Figures 6 and 7. The absence of the LDD elements in a simpler FET structure, achieved by depositing the electrodes 8a and 8b illustrated in Figure 1(i) directly on the structure of Figure 1(e), with the omission of the steps illustrated in Figures 1(f)-1(h), does not alter the advantages achieved in the invention. As described above, by using the self-aligning process described, the advantage of eliminating the flow of leakage current within the substrate, thereby minimizing the short channel effect, without increasing the capacitance between the source electrode and gate electrode, is reliably and reproducibly achieved.

Claims: A method of producing a field effect transistor comprising the following steps: providing a semi-insulative semiconductor substrate (1,2) having at its surface a first conductivity type active layer (2); producing a gate electrode (3') on the surface of said substrate (1,2); and producing respective source and drain regions (5,5') of the first conductivity type, but having a higher dopant impurity concentration than in said active layer (2), self-aligned to each side of said gate electrode (3'), and a barrier region (9) of second conductivity type, opposite in conductivity type to the first conductivity type of said active layer (2) and of said source and drain regions (5,5'), extending along the underside of one of said source and drain regions (5,5') and a portion of the underside of said active layer (2) beneath said gate electrode (3'), using steps of ion implantation; which method is characterised in that: the step of producing said gate electrode (3') comprises: producing a first mask film (10') covering part of said active layer (2); depositing a gate metal film (3) on said first mask film (10') and on the surface of said active layer (2) not covered by said first mask film (10'); and etching said gate metal film (3) to leave a portion (3') of the gate metal film (3') on said active layer (2), adjacent to and contacting the edge of said first mask film (10'), as the gate electrode (3'); the step of ion implantation for producing said barrier region (9) is performed first, using not only said gate electrode (3') but also said first mask film (10') as a mask, and is followed by an anneal treatment at an elevated temperature to activate the implanted dopant ions and to diffuse these laterally to produce said barrier region (9) extending along said portion of the underside of said active layer (2) beneath said gate electrode (3'); and the step of ion implantation for producing respective source and drain regions (5,5') is performed after said anneal treatment and after removing said first mask film (10'); which method also includes: forming a source electrode (8a) and a drain electrode (8b) on said source and drain regions (5,5') respectively. A method of producing a field effect transistor comprising the following steps: providing a semi-insulative semiconductor substrate (1,2) having at its surface a first conductivity type active layer (2); producing a gate electrode (3') on the surface of said substrate (1,2); producing respective first source and drain regions (5,5') of the first conductivity type but having a higher dopant impurity concentration than in said active layer (2), self-aligned to each side of said gate electrode (3'), and a barrier region (9) of second conductivity, opposite in conductivity type to the first conductivity type of said active layer (2) and of said first source and drain regions (5,5'), extending along the underside of one of said first source and drain regions (5,5') and a portion of the underside of said active layer (2) beneath said gate electrode (3'), using steps of ion implantation; depositing a second mask film (6) on the substrate (1,2) on both sides of said gate electrode (3') and on said gate electrode (3'); etching said second mask film (6), leaving portions (6') of said second mask film (6) on the substrate (1,2) adjacent to and contacting first and second opposed sides of said gate electrode (3'); implanting dopant impurities for producing the first conductivity type in the substrate (1,2) using said gate electrode (3') and said portions (6') of said second mask film (6) as an ion implantation mask, to form first conductivity type second source and drain regions (7,7') in the substrate (1,2) on opposite sides of said gate electrode (3'), having a higher concentration of dopant impurity than in said first source and drain regions (5,5'); and forming a source electrode (8a) and a drain electrode (8b) on said second source and drain regions (7,7'), respectively; which method is characterised in that: the step of producing said gate electrode (3') comprises: producing a first mask film (10') covering part of said active layer 2; depositing a gate metal film (3) of refractory metal or metal silicide on said first mask film (10') and on the surface of said active layer (2) not covered by said first mask film (10'); etching said gate metal film (3) and leaving a portion (3') of said gate metal film (3') on said active layer (2), adjacent to and contacting the edge of said first mask film (10'), as said gate electrode (3'); the step of ion implantation for producing said barrier region (9) is performed first using not only said gate electrode (3') but also said first mask film (10') as a mask, and is followed by an anneal treatment at an elevated temperature to activate the implanted dopant ions and to diffuse these laterally to produce said barrier region (9) extending along said portion of the underside of said active layer (2) beneath said gate electrode (3'); the step of ion implantation for producing respective first source and drain regions (5,5') is performed after said anneal treatment and after removing said first mask film (10'); and the step of implanting dopant impurities for said second source and drain regions (7,7') is performed to produce said second drain region (7') disposed within said barrier region (9). A method as claimed in claim 1 wherein the step of depositing gate metal film (3) is a step of depositing either refractory metal or a refractory metal silicide. A method as claimed in any preceding claim wherein the etching of said gate metal film (3) is performed by reactive ion etching. A method as claimed in any preceding claim wherein the step of producing said first mask film (10') covering part of said active layer (2), includes depositing one of SiO x , SiO 2 , and SiN x . A method as claimed in any preceding claim wherein said semi-insulative semiconductor substrate (1,2) comprises a body (1) of III-V semiconductor compound material. A method as claimed in claim 6 wherein said body (1) is of GaAs. A method as claimed in either of claims 6 and 7 wherein the step of providing said semi-insulative semiconductor substrate (1,2) includes implanting dopant impurities in the body (1) of said substrate to produce said active layer (2). A method as claimed in any preceding claim wherein said first conductivity type is n-type. A method as claimed in claim 2 or in any preceding claim 4 to 9, depending directly or indirectly from claim 2, wherein the etching of said second mask film (6) leaving portions (6') adjacent to opposite sides of said gate electrodes (3') is performed by reactive ion etching.

Inventors: FUJII TAKAYUKI, NAKATANI MITSUNORI, FUJII, TAKAYUKI, NAKATANI, MITSUNORI, Fujii, Takayuki, c/o Mitsubishi Denki K.K., Nakatani, Mitsunori, c/o Mitsubishi Denki K.K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1991
Main classification: H01L21
IPC codes: H01L29, H01L21