Stacked capacitor DRAM cell

Abstract: In a DRAM which includes a memory cell consisting of one MOS transistor and one stacked capacitor, the node electrode of the capacitor is constituted of a stacked layer formed by alternately stacking a first conductor film and a second conductor film. As the first conductor film use is made of, for example, an n-type polycrystalline silicon film, and as the second conductor film use is made of, for example, an oxygen-rich n-type polycrystalline silicon film, or a silicide film of a high melting point metal. On the side faces of the node electrode, the edges of the first conductor films are at the positions that are more indented than the edges of the second conductor films. Because of the indentations, the surface area of the node electrode is increased so that a stacked capacitor with large capacitance can be realized even when the occupancy area of the capacitor is small. A node electrode with the above-mentioned structure can be formed by first anisotropically etching the stacked film, then by isotropically etching the film. This formation process is succinct, and the manufacturing process is also easy to handle.

Description: The present invention relates to a dynamic random access semiconductor memory device (DRAM) and to a method of manufacturing such a device, and more particularly, to the structure and manufacture of the node electrode of a dynamic random access memory device including a memory cell consisting of one MOS transistor and one stacked capacitor. DRAMs having memory cells each consisting of one MOS transistor and one capacitor have been developed with the aim of reducing the occupancy area of the memory and augmenting the capacitance of the capacitor to the maximum extent possible. The reduction of the occupancy area of the memory cell has mainly been realized by assigning a fine geometry to the MOS transistor, but the occupancy area of the capacitor has also been reduced accordingly. The capacitors have been developed from the planar type through the trench type to the stacked type which has a vertical structure. In a DRAM which includes a stacked type capacitor, the MOS transistor is constituted of a gate electrode connected to a word line on a gate insulating film, a node diffused layer, and a bit diffused layer. The capacitor is constituted of a node electrode which is connected to the node diffused layer via a node contact hole, a capacitor insulating film, and a cell plate electrode. One of the methods for increasing the capacitance of such a DRAM is to increase the facing areas of the node electrode and the cell plate electrode. This is realized mainly by increasing the surface area of the node electrode. As a method for accomplishing this, there is a method of using a node electrode of "fin" structure, for example, as reported in IEDM Tech. Dig., 1988, pp. 592-595 by T. Ema, et al. In this report there is described a structure in which a bit line is formed in the tip layer of a stacked type capacitor, and a structure in which a stacked type capacitor is formed above a bit line. A method of forming a memory cell for a DRAM having a node electrode of fin structure, with the structure in the report, will be described below with reference to Figs 1A-1E. A structure of the type given in the report is described in more detail in European Patent Application EP-A-0 295 709 (Inventors: M. Taguchi and T. Ema). That application describes a DRAM with a storage capacitor having a plurality of stacked conductive films. As shown in Fig. 4E of that application, the stacked films comprise alternate layers of an undoped polycrystalline silicon film and an n⁺-type polycrystalline silicon film into which arsenic is highly doped. The end parts of the undoped polycrystalline silicon film are at positions more indented than the end parts of the n⁺-type As-doped polycrystalline film, thereby increasing the area of the node electrode and hence the capacitance. However, the manufacture of such a device is complicated and difficult. The present invention is defined in the independent claims below, to which reference should now be made. Advantageous features of the invention are set forth in the dependent claims. The invention will be described in more detail, by way of example, with reference to the accompanying drawings, in which: FIGs. 1A to 1E are schematic sectional views arranged in order illustrating the manufacturing method of a DRAM including a known stacked type capacitor having a fin type node electrode; FIGs. 2A to 2E are schematic sectional views arranged in order illustrating the manufacturing method of a preferred semiconductor memory device embodying the present invention; FIG. 3 is a diagram illustrating the method of manufacturing a stacked film which constitutes the node electrode of the semiconductor memory device of FIGs. 2A to 2E, which is a graph showing the change with the time of the flow rate of the gas used for film formation; FIG. 4 is a graph showing the depth profile of the oxygen concentration in the stacked film which constitutes the node electrode; FIG. 5 is a graph showing the change in the surface area of the node electrode as a function of the number of layers of the oxygen-rich polycrystalline silicon film; and FIGs. 6A and 6B are schematic sectional views illustrating an alternative process for producing alternately stacked polycrystalline silicon films and oxygen-rich polycrystalline silicon films. First, the structure and the method of manufacture of the node electrode of a DRAM having a memory cell consisting of a known stacked type capacitor will be described by referring to the drawings. As a method of increasing the surface area of the node electrode, one may mention the report by T. Ema, et al. who adopted a fin type node electrode. Referring to FIGs. 1A to 1E, the contents of the report will briefly be described. First, a field oxide film 202 is formed on the surface of a p-type silicon substrate 201, and an MOS transistor consisting of a gate electrode 203 connected to a word line on a gate oxide film 202a, an n-type node diffused layer 204a, and an n-type bit diffused layer 204b is formed. Then, a first interlayer insulating film 205 is deposited all over the surface. At least the surface of the interlayer insulating film 205 is formed of a silicon nitride film. Subsequently, a silicon oxide film 227, a first n-type polycrystalline silicon film 213, and a silicon oxide film 228 are formed sequentially (FIG. 1A). Next, a photoresist film 218 is formed which has an opening at the position where a node contact hole is to be created, and a node contact hole 206a which reaches the node diffused layer 204a is opened by etching sequentially the silicon oxide film 228, the polycrystalline silicon film 213, the silicon oxide film 227, and the interlayer insulating film 205. As a result of the etching, the silicon oxide film 228, the polycrystalline silicon film 213, and the silicon oxide film 227 become a silicon oxide film 228a, a polycrystalline silicon film 213a, and a silicon oxide film 227a, respectively (FIG. 1B). Next, the photoresist film 218 is removed, and a second n-type polycrystalline silicon film is formed all over the surface. A photoresist film 219 is formed in the region where a node electrode is to be formed, and the second n-type polycrystalline silicon film, the silicon oxide film 228a, the polycrystalline silicon film 213a and the silicon oxide film 227a are sequentially etched by an anisotropic etching such as RIE (reactive ion etching) that uses the photoresist film 219 as the mask. As a result of this etching, the second n-type polycrystalline silicon film, the silicon oxide film 228a, the polycrystalline silicon film 213a, and the silicon oxide film 227a are converted to a polycrystalline silicon film 223a, a silicon oxide film 228b, a polycrystalline silicon film 213b, and a silicon oxide film 227b, respectively (FIG. 1C). Next, after removal of the photoresist film 219, the silicon oxide film 228b sandwiched by the polycrystalline silicon film 223a and the polycrystalline silicon film 213b, and the silicon oxide film 227b sandwiched by the polycrystalline silicon film 213b and the interlayer insulati-ng film 205 are removed by a wet etching which uses hydrofluoric acid. As a result of this treatment, a node electrode 217 of fin structure constituted of an n-type polycrystalline silicon film 223a and an n-type polycrystalline silicon film 213b is formed (FIG. 1D). Next, a capacitor insulating film 207 is deposited all over the surface. Then, a third n-type polycrystalline silicon film is formed all over the surface, and a cell plate electrode 208 is formed by etching the third n-type polycrystalline silicon film. A stacked type capacitor is formed by removing the capacitor insulating film 207 by etching, using the cell plate electrode 208 as the mask. Next, a second interlayer insulating film 209 is deposited all over the surface, and a bit contact hole 206b is opened by sequentially etching the interlayer insulating films 209 and 205 above the bit diffused layer 204b. Next, a bit line 210 is formed, completing a DRAM (FIG. 1E). The node electrode 217 of fin structure as shown in FIG. 1D has a sufficiently large surface area. However, according to the method as described in the above, there are required two photolithography operations which makes the formation process long and complex. Moreover, in realizing the structure, in the stage of removing by etching the silicon oxide films 227b and 228b which are sandwiched by a polycrystalline silicon film and an interlayer insulating film or a polycrystalline silicon film, the mechanical strength of the node electrode 217 is deteriorated, making the process such as washing extremely difficult. Next, referring to the drawings an embodiment of the present invention will be described. Referring to FIGs. 2A to 2E which are schematic sectional views arranged in order illustrating the method of manufacture of the preferred semiconductor memory device embodying the present invention, first, an active region and an element isolation region are partitioned by forming a field oxide film 102 on the surface of a p-type silicon substrate 101. After formation of the gate oxide film 102a on the active region, a gate electrode 103 serving also as a word line is formed. An n-type node diffused layer 104a and a bit diffused layer 104b are formed on the surface of the active region by using the gate electrode 103 on the active region as the mask, completing a MOS transistor of a DRAM. A first interlayer insulating film 105 consisting of a silicon oxide film with thickness of, for example, about 300 nm is formed allover the surface. The interlayer insulating film 105 does not need to have its surface formed of a silicon nitride film, as is the case in the known device. Next, the structure shown in FIG. 2A is obtained by opening a node contact hole 106a by etching the interlayer insulating film 105 on the node diffused layer 104a. Next, an undoped polycrystalline silicon film 111 with thickness of, for example, about 150 nm is deposited by thermal decomposition of silane (SiH₄) within the temperature range of 500 to 600°C in an LPCVD apparatus. Subsequently, an oxygen-rich undoped polycrystalline silicon film 112 is formed by exposing the sample to an argon atmosphere containing 0.2 to 5% of oxygen (O₂) in the same apparatus. By repeating the similar operation for two more times, an undoped polycrystalline silicon film 121, an oxygen-rich undoped polycrystalline silicon film 122, a undoped polycrystalline silicon film 131, and an oxygen-rich undoped polycrystalline silicon film 132 are formed sequentially to form a stacked polycrystalline silicon film, obtaining the structure as shown in FIG. 2B. In the above-mentioned processing, the flow rate of silane and argon diluting oxygen are changed periodically as shown, for example, in FIG. 3. The film thicknesses of the oxygen-rich undoped polycrystalline silicon films 112, 122, and 132 formed on the surfaces of the undoped polycrystalline silicon films 111, 121, and 131, respectively, are determined by the temperature, pressure, and oxygen partial pressure within the LPCVD apparatus, duration of the operation, and the like, but they are considered to be the thicknesses corresponding to silicon layers with one to several atomic layers. At this time, it is considered that the bonding between oxygen and silicon does not form the complete structure of silicon dioxide (SiO₂). Next, the sample is taken out of the LPCVD apparatus and is subjected to diffusion by phosphoryl trichloride (POCℓ₃) bubbling at 800 to 850°C to diffuse phosphorus into the stacked film and convert the undoped polycrystalline silicon films 111, 121, and 131 and the oxygen-rich undoped polycrystalline silicon films 112, 122, and 132 to n-type semiconductor films. For the above-mentioned range of the temperature the thickness of the oxygen-rich n-type polycrystalline silicon film is 5 to 200 nm, and the sheet resistance of the film is 200 to 1000 Ω/□ or so. The reason for this is considered to be due to dispersion, in broader manner into the silicon crystals, of oxygen contained in the oxygen-rich undoped polycrystalline silicon film instead of forming the oxide of silicon, as a result of diffusion of phosphorus and the accompanying heat treatment. The fact that the lowermost undoped polycrystalline silicon film 111 is also converted to n-type by the phosphorus diffusion, lends support to the belief that oxygen in the oxygen-rich undoped polycrystalline silicon film does not form the completely bonded compound of SiO₂. In the stacked film consisting of n-type polycrystalline silicon formed over the interlayer insulating film 105 (the flat portion above the gate electrode 103), for example, the depth profile of the oxygen concentration is as shown in FIG. 4. This result represents a measurement by secondary ion mass spectrometry (SIMS). The oxygen concentration has three peaks; a first peak on the surface, a second peak at a depth of about 150 nm, and a third peak at a depth of about 300 nm. The second and the third peaks have a considerable spectral width, and the maximum oxygen concentrations at these peaks are about one order of magnitude smaller than the oxygen concentration of a silicon oxide film. The first peak is in the state of superposition of a region of extremely high oxygen concentration (about 5 x 10²¹ atoms/cm³ which is comparable to the oxygen concentration of the interlayer insulating film) in a very narrow range, and a region which is the same order as those of the second and the third peaks. The region of the first peak with extremely high oxygen concentration corresponds to the region of natural oxide formed on the surface of the stacked film. Next, a photoresist film 119 is formed in the region reserved for a node electrode, and anisotropic etching is applied to the stacked film consisting of the n-type polycrystalline silicon using the photoresist film as a mask. As a result, in the region for forming the node electrode, there is formed a stacked film consisting of an oxygen-rich n-type polycrystalline silicon film 134b, an n-type polycrystalline silicon film 133b, an oxygen-rich n-type polycrystalline silicon film 124b, an n-type polycrystalline silicon film 123b, an oxygen-rich n-type polycrystalline silicon film 114b, and an n-type polycrystalline silicon film 113b, as shown in FIG. 2C. The side faces of the stacked film are approximately flat. The anisotropic etching is an RIE that uses dichlorodifluoromethane (CCℓ₂F₂) of about 40 sccm as the etchant gas, carried out under a pressure of about 200 m Torr and an RF power of about 300 W. Next, isotropic etching is applied,without removal of the photoresist film 119, to the surfaces of the stacked film exposed by the anisotropic etching, by using sulfur hexafluoride (SF₆) as the etchant gas. As a result of the etching, the oxygen-rich n-type polycrystalline silicon film 134b, the n-type polycrystalline silicon film 133b, the oxygen-rich n-type polycrystalline silicon film 124b, the n-type polycrystalline silicon film 123b, the oxygen-rich n-type polycrystalline silicon film 114b, and the n-type polycrystalline silicon film 113b are converted respectively to an oxygen-rich n-type polycrystalline silicon film 134c, an n-type polycrystalline silicon film 133c, an oxygen-rich n-type polycrystalline silicon film 124c, an n-type polycrystalline silicon film 123c, an oxygen-rich n-type polycrystalline silicon film 114c, and an n-type polycrystalline silicon film 113c, as shown in FIG. 2D, completing a node electrode 117a of the stacked capacitor consisting of these stacked films. Here, by the adoption of isotropic etching by the use of sulfur hexafluoride there is formed a ruggedness on the side faces of the node electrode due to the indentations of the n-type polycrystalline silicon films 113c, 123c, and 133c, because of the slower rate of etching of the oxygen-rich n-type polycrystalline silicon film than the n-type polycrystalline silicon film that does not contain oxygen (or is oxygen-poor). The isotropic etching employed here is carried out, for example, using sulfur hexafluoride of 60 sccm as the etchant gas and helium (He) of 100 sccm as the carrier gas, under a pressure of 400 m Torr and an RF power of 400 W. The indentations in this case are about 0.1 to 0.3 µm. Although the increase in the surface area of the node electrode 117a due to individual indentation is small, for example, even if the increase in the surface area due to a single indentation is about 6%, the surface area of the node electrode can be increased by increasing the number of layers of the oxygen-rich polycrystalline films, as shown in FIG. 5. In the present embodiment the number of layers of the n-type polycrystalline silicon films that do not contain oxygen (or are oxygen-poor) is three, and the thickness of each film is about 150 nm, so that the increase in the surface area of the node electrode is about 18%. However, by reducing the thickness of the n-type polycrystalline silicon film containing no oxygen (or being oxygen-free) to about 50 nm, and increasing the number of films from 3 to 10 layers, for example, the increase in the surface area of the node electrode can be made about 60%. Next, the photoresist film 119 is removed, and a dieletric capacitor insulating film 107 and a cell plate electrode 108 are formed, completing a stacked capacitor. Subsequently, a second interlayer insulating film 109 is deposited all over the surface, and a bit contact hole 106b is opened by sequentially etching the interlayer insulating films 109 and 105 on the bit diffused layer 104b. Finally, a bit line 110 is formed to complete a DRAM which is equipped with the node electrode 117a of the first embodiment as shown in FIG. 2E. As described in the above, the present embodiment makes it possible to obtain the fin structure in a smaller number of steps of one photolithography operation (and two etching operations) compared with the method of Figs 1A to 1E. Furthermore, the depth of the indentation of the fins is about 0.3 µm at the most so that the mechanical strength at the stage of formation of the node electrode can be secured. Moreover, as described above, the number of indentations on the side faces of the node electrode can readily be increased, so that it is easy to obtain a capacitor having large capacitance even if the occupancy area of the stacked capacitor has to be decreased. FIGs. 6A and 6B are schematic sectional views illustrating an alternative method of manufacturing the semiconductor memory device, which is the same as that of the main embodiment up to the process shown in FIG. 2A. Next, an n-type polycrystalline silicon film 113 with thickness of about 150 nm, for example, is deposited in the LPCVD apparatus by means of thermal decomposition that uses a mixed gas of silane (SiH₄) and phosphine (PH₃) in the temperature range of 500 to 600°C. Then, an oxygen-rich n-type polycrystalline silicon film 114 is formed on the surface of the polycrystalline silicon film 113 by exposing the sample to an argon atmosphere containing 0.2 to 5% of oxygen (O₂) within the same apparatus. By the repetition of similar operations two more times, an n-type polycrystalline silicon film 123, an oxygen-rich n-type polycrystalline silicon film 124, an n-type polycrystalline silicon film 133, and an oxygen-rich n-type polycrystalline silicon film 134 are formed sequentially to form a stacked polycrystalline silicon film, obtaining the structure as shown in FIG. 6A. Next, by a heat treatment in an inert atmosphere at 600 to 850°C, the oxygen-rich n-type polycrystalline silicon film 134, the n-type polycrystalline silicon film 133, the oxygen-rich n-type polycrystalline silicon film 124, the n-type polycrystalline silicon film 123, the oxygen-rich n-type polycrystalline silicon film 114, and the n-type polycrystalline silicon film 113 are respectively converted to an oxygen-rich n-type polycrystalline silicon film 134a, an n-type polycrystalline silicon film 133a, an oxygen-rich n-type polycrystalline silicon film 124a, an n-type polycrystalline silicon film 123a, an oxygen-rich n-type polycrystalline silicon film 114a, and an n-type polycrystalline silicon film 113a, as shown in FIG. 6B. The purpose of the heat treatment is to disperse oxygen in, for example, the oxygen-rich n-type polycrystalline silicon film 114, and as a result, the thickness of the oxygen-rich n-type polycrystalline silicon film 114a is increased relative to the thickness of the oxygen-rich n-type polycrystalline silicon film 114. Subsequently, a node electrode is completed through processes similar to those shown in FIGs. 2C and 2D. Further, a DRAM equipped with the node electrode is completed by the same manufacturing method as shown in FIG. 2E. In the alternative method of Figs. 6A and 6B, a stacked film is formed consisting of polycrystalline silicon films which are n-type from the beginning. The growth rate of the n-type polycrystalline silicon film by the above-mentioned method is smaller than the growth rate of the undoped polycrystalline silicon film of FIGs. 2A to 2E. However, it becomes possible to form with high accuracy an n-type polycrystalline silicon film with small thickness. Moreover, the thickness of the oxygen-rich n-type polycrystalline silicon film 114a, for example, depends on the conditions of the heat treatment. Therefore, the thickness of the n-type polycrystalline silicon film 113a and the oxygen-rich n-type polycrystalline silicon film 114a, for example, can further be reduced compared with the main embodiment. As a result, the alternative method makes it possible to further increase the surface area of the side faces of the node electrode. It should be mentioned that the stacked film consisting of the polycrystalline silicon films were made by an LPCVD method. However, there exists an alternative method of forming the small thicknesses of the oxygen-rich polycrystalline film and of the polycrystalline silicon film which does not contain oxygen (or is oxygen-poor), with high controllability, by means of an MBE apparatus.

Claims: A dynamic random access memory comprising an MOS transistor having a gate electrode (103), a node diffused layer (104a) and a bit diffused layer (104b), and a capacitor having a node electrode (117a) connected to the node diffused layer, a dielectric film (107) formed on the node electrode and a cell plate electrode (108) formed on the dielectric layer, in which the node electrode consists of a first n-type polycrystalline silicon film (113c, 123c, 133c) stacked alternately with a second n-type polycrystalline silicon film (114b, 124b, 134b), the second polycrystalline silicon film having a higher oxygen content than the first polycrystalline silicon film, and that the end part of each first polycrystalline film is at a position more indented than the end part of each said second polycrystalline film. A method of manufacturing a node electrode of a dynamic random access memory including one MOS transistor and one stacked capacitor, comprising the steps of: forming an MOS transistor consisting of a gate electrode serving as a word line on a gate insulating film and an n-type node diffused layer and an n-type bit diffused layer that are formed on a surface of a p-type silicon substrate, depositing an interlayer insulating film all over the surface, and opening a node contact hole that reaches the node diffused layer in the interlayer insulating film; forming a stacked film by alternately depositing a first n-type polycrystalline silicon film and an second n-type polycrystalline silicon film, the second polycrystalline silicon film having a higher oxygen content than the first polycrystalline silicon film, causing a slower rate of etching; forming a photoresist film in a region for forming a node electrode, and anisotropically etching the stacked film using the photoresist film as the mask; and isotropically etching at least that surface of the stacked film which is exposed by the anisotropic etching. A method of manufacturing a semiconductor memory device as claimed in claim 2, in which the step of forming the stacked film comprises carrying out alternately deposition of an undoped polycrystalline silicon film, and formation of an oxygen-rich undoped polycrystalline silicon film on the surface of the undoped polycrystalline silicon film by exposing the undoped polycrystalline silicon film to an oxygen atmosphere, and forming a first stacked film consisting of the said undoped polycrystalline silicon film and the said oxygen-rich undoped polycrystalline silicon film; and diffusing phosphorus into the first stacked film. A method of manufacturing a semiconductor memory device as claimed in claim 2, in which the step of forming the stacked film comprises carrying out alternately deposition of the first n-type polycrystalline silicon film by a CVD method that uses silane gas containing phosphine, and formation of the second n-type polycrystalline silicon film on the surface of the first n-type polycrystalline silicon film by exposing the first n-type polycrystalline silicon film to oxygen and carrying out a heat treatment in an inert atmosphere. A method of manufacturing a semiconductor memory device as claimed in claim 4, wherein the isotropic etching is a dry etching which uses an etching gas that contains at least sulfur hexafluoride.

Inventors: SAEKI TAKANORI, SATO NATSUKI, SAEKI, TAKANORI, SATO, NATSUKI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: H01L27
IPC codes: H01L27, H01L21