Image filtering system

Abstract: An image filtering system which comprises a storage device for storing image data which are partitioned into blocks composed of a predetermined number of picture elements for an orthogonal transform and represent an entire input image therein, an address selecting device for selecting addresses of the storage device, from which image data corresponding to respective predetermined object regions of a frame and stored at the selected addresses are read, and a sum-of-products calculating device for multiplying each of the image data of picture elements read out of the storage device by a corresponding coefficient of an operator, which is comprised of a predetermined number of coefficients, for adding up the thus obtained products for each of the object regions and for outputting a sum signal representing a sum of the products for each of the object regions. In the image filtering system, the address selecting device selects the addresses such that a storage area of the storage device corresponding to each of the object regions does not spread over adjoining ones of the blocks. Thereby, can be prevented occurrence of a block noise originating from a block in which motion compensation is not appropriately performed. Consequently, a prediction error of a quantity of codes can be substantially decreased.

Description: This invention generally relates to an image processing and more particularly to an image filtering system suitable for predicting a quantity of codes included in a frame, for example, in case of performing compression of image data representing a colour image in blocks, each of which is composed of a predetermined number of picture elements. Generally, when effecting compression of image data representing a colour image, the image data are first partitioned into blocks each of which is comprised of a predetermined number of picture elements. Further, data of each block are then transformed by using an orthogonal transform. Subsequently, the transformed data are quantised. Thereafter, either zero run length coding or Huffman coding is performed on the quantised data. Alternatively, both of zero run length coding or Huffman coding are performed on the quantised data. The article" A Real Time Video Signal Processor Suitable for Motion Picture Coding Applications" by Tamitani et al, IEEE/IEICE Global Telecon Conf, Vol 1, 15, Nov 1987 discusses motion picture coding by division into 8 x 8 blocks and performing orthogonal transformation and quantisation. EP-A-0 272 794 discloses a method of matching 8 x 1 pixel areas of an 8 x 8 block of an image with predefined patterns to find the closest match. The eight values representing the closest match are then formed into a scalar sum which is used to access a look-up memory to find a code word indicative of a standard pattern. In case of performing compression of data representing a moving picture, a conventional image filtering system employs a method such as that described in EP-A-0444918 which is part of the state of the art by virtue of Article 54(3) EPC. Namely, in case of this conventional method, for example, as illustrated in FIG. 4, one segment is made up of a plurality of frames (four frames in this case). Further, in this conventional method, a frame (hereunder referred to as an intra-frame) on which intra-frame compression is performed is employed as one of the four frames of a segment. Moreover, three frames (hereunder referred to as first to third inter-frames), each of which is composed of difference data representing differences between picture elements of a motion-compensated frame and corresponding picture elements of the intra-frame, are employed as the other frames of the segment. In case of performing compression of data of frames in this manner, a quantity of information regarding frequency (i.e., a quantity of codes) included in each frame is predicted by performing a filtering processing of data contained in each frame and computing a sum of absolute values of results of the filtering processing. Then, a quantization step and a band-limited value which correspond to the predicted value of the quantity of codes are established. Subsequently, a band-limitation of the data included in each frame is effected by using the established band-limited value. Thereafter, the band-limited data are orthogonally transformed in blocks, and further the transformed data are quantized by using the established quantization step. Thereby, a quantity of codes included in an entire segment can be controlled in such a manner to be a desired constant value. However, for instance, in case where an object, which is not present in a previously processed frame, appears in a currently processed frame when performing the filtering processing, or in case where a motion of an object is complex, motion compensation cannot appropriately be performed in the inter-frames. A block, of which motion compensation is not appropriately performed, is not closely correlated with surrounding blocks. Consequently, when reproduction of an image is effected from data obtained by compression of the frame including such a block, there occurs a noise (hereunder sometimes referred to as a block noise) originating from such a block. More particularly, this results from the fact that when computing a sum of absolute values of data obtained as results of the filtering processing of data of such a block, a part of the thus obtained data corresponding to boundary picture elements of the block, which are not used in the orthogonal transform to be performed later on the data of each of the blocks, adjacent to another block to next be read is included in a computed value of the sum. This further increases a prediction error of a quantity of codes obtained as a result of the coding of the data of such a frame. The present invention is accomplished to resolve such problems of the conventional image filtering system. Accordingly, an object of the present invention is to provide an image filtering system which can extremely decrease a prediction error of a quantity of codes. According to the present invention, there is provided an image filtering system comprising: storage means for storing image data representing an entire input image therein, the image data being partitioned into blocks for an orthogonal transform, each of the blocks being composed of a predetermined number of picture elements; address selecting means for selecting addresses of said storage means, from which image data corresponding to respective object regions and stored at the selected addresses are read, each of said object regions being a predetermined region of said blocks and being smaller than said blocks; and sum-of-products calculating means for multiplying each of the image data of picture elements read out of said storage means by a corresponding coefficient of an operator, which is comprised of a predetermined number of coefficients, for adding up the thus obtained products for each of the picture elements in a given object region and for outputting a sum signal representing a sum of the products for the given object region, said sum signal containing information of a predicted quantity of codes included in said given object region, wherein said address selecting means selects the addresses such that the read storage areas of said storage means corresponding to each of the object regions do not spread over ones of adjacent blocks. Thereby can be prevented occurrence of a block noise originating from a block in which motion compensation is not appropriately performed. Consequently, a prediction error of a quantity of codes can be substantially decreased. The present invention will be further described by way of example in the following description of a preferred embodiment, with reference to the drawings in which like reference characters designate like or corresponding parts throughout several views, and in which: - Figure 1 is a schematic block diagram for showing the construction of an image filtering system embodying the present invention; Figures 2 and 3 are diagrams for illustrating an operation of the image filtering system of Figure 1; and Figure 4 is a diagram for illustrating a method for performing image data compression, which is employed in a conventional image filtering system. Referring first to Figure 1, there is shown the construction of an image filtering system embodying the present invention. In this Figure, reference numeral 1 denotes a frame memory 1 for receiving and storing input image data; 2 a sum-of-products calculating circuit for reading data of a predetermined region (corresponding to an object region) of an image represented by the input image data and for performing a filtering processing; 3 a sum-of-absolute-values calculating circuit 3 for receiving and calculating a sum of absolute values of outputs of the sum-of-products calculating circuit 2; 4 a counter for receiving and counting the outputs of the sum-of-products calculating circuit 2; 5 an address selecting circuit 5 for receiving outputs of the counter 4, for generating addresses corresponding to a value of a count obtained by the counter 4, for outputting the generated addresses to the frame memory 1 and for issuing a signal (hereunder referred to simply as an incrementing signal) for incrementing the value of the count obtained in the counter 4 when the value of the count reaches a predetermined one. Next, an operation of the image filtering system of FIG. 1 will be described in detail hereinbelow. First, input image data are inputted to the frame memory 1. At that time, image data of one frame are written to the frame memory 1. Then, the image data stored in a predetermined storage area of the frame memory 1 corresponding to addresses generated by and inputted from the address selecting circuit 5 are read from the frame memory 1. The thus read data are inputted to the sum-of-products calculating circuit 2. Incidentally, the predetermined storage area of the frame memory 1 corresponds to an object region. Subsequently, in the circuit 2, the inputted data are multiplied by a corresponding operator including predetermined coefficients, and in addition results of the multiplication are added together. Thereafter, a result of the addition is outputted to the sum-of-absolute-values calculating circuit 3. The sum-of-absolute-values calculating circuit 3 computes absolute values of the results of the addition inputted from the sum-of-products calculating circuit 2, and serially adds up the computed absolute values corresponding to data of one frame. Incidentally, an output of the sum-of-products calculating circuit 2 (namely, a result of the addition) is supplied to a standard code quantity converting circuit (not shown) wherein the supplied result of the addition is converted to a value of a predicted quantity of codes. The output of the sum-of-products calculating circuit 2 is also fed to the counter 4. Then, the counter 4 counts the number of times of receiving the outputs of the sum-of-products calculating circuit 2 and outputs the value of the count to the address selecting circuit 5. Subsequently, the address selecting circuit 5 generates addresses corresponding to the value of the count received from the counter 4 and further outputs the generated addresses to the frame memory 1. As a result, the predetermined storage area of the frame memory 1 to be read is successively shifted in response to the count value of the counter 4. Namely, the object region is successively displaced in the frame. The address selecting circuit 5, in which the number of picture elements composing a block and that of the coefficients of the operator are preliminarily stored, compares the value of the count outputted from the counter 4 with the preliminarily stored values, and outputs an incrementing signal to the counter 4 according to a result of the comparison. This operation of the address selecting circuit 5 will be described in detail hereinafter by referring to FIG. 2. In case of image data illustrated in FIG. 2, each of blocks B1 and B2 into which the image data is partitioned for an orthogonal transform is comprised of 8 × 8 picture elements; and an operator 1 × 5 coefficients. As illustrated in FIG. 2(a), the address selecting circuit 5 first generates addresses assigned to, for instance, 1 × 5 data of a hatched region (corresponding to an object region) A located leftwardly and upwardly in the first block B1, as viewed in this figure. Then, the five data indicated by these addresses are read from the frame memory 1 and are inputted to the sum-of-products calculating circuit 2 wherein each of the five data is multiplied by a corresponding one of the five coefficients of the operator. Subsequently, five values respectively obtained as results of the multiplications (i.e., products) are added up therein, and thereafter a result of this addition is outputted therefrom to the sum-of-absolute-values calculating circuit 3. Further, the value of the count held in the counter 4 is increased by 1 every time the result of the addition effected in the circuit 2 (i.e., the sum) is outputted to the counter 4. When the value of the count held in the counter 4 is increased by 1, the address selecting circuit 5 shifts each of addresses included in the hatched region corresponding to the object region A (hereunder sometimes referred to simply as the object region A) one place (corresponding to a picture element) to the right as illustrated in FIG. 2(b). Then, 1 × 5 data corresponding to addresses included in the thus updated object region A of FIG. 2(b) are inputted to the sum-of-products calculating circuit 2 wherein the inputted data are multiplied by the corresponding coefficients of the operator. Moreover, the five products thus obtained are added together, and a sum of these products is inputted to the sum-of-absolute-values calculating circuit 3 which further computes an absolute value of the inputted sum and adds the computed absolute value to the sum of the absolute values, which is previously calculated and stored therein. When the sum-of-products calculating circuit 2 outputs the new sum of the products, the value of the count held in the counter 4 is increased by 1 once again. As a result of this, each of the addresses of the current object region A of FIG. 2(b) is shifted one place (corresponding to a picture element) to the right, as illustrated in FIG. 2(c). After that, similar operations are repeatedly carried out. When a rightmost address of the current object region A is matched with an address of a boundary of the block B1 as shown in FIG. 2(d), the address selecting circuit 5 outputs an incrementing signal to the counter 4 without generating addresses at the next increment of the value of the count held in the counter 4, so that the count stored in the counter 4 is increased by 1. Since then, only the incrementing of the count held in the counter 4 is repeated without generation of addresses until the left end of the region A reaches the left boundary of the block B2. Namely, the generation of addresses is controlled such that each object region A does not spread over adjoining ones of blocks into which the image data are partitioned for an orthogonal transform, whereby each sum of the products is derived from data of a sole block. Referring next to FIG. 3, there is shown another case in which each block for an orthogonal transform is composed of 4 × 4 picture elements of image data, and an operator is made up of 3 × 3 coefficients. In this case, an object region A is serially shifted one place (corresponding to a picture element) to the right as illustrated in FIGS. 3(a) to 3(c). Further, when the right end of the object region A reaches a right boundary of a rightmost block of a top row of the image data, the object region A is shifted one place (corresponding to a picture element) to the bottom. Moreover, a reading of image data is once again started from a leftmost block of the top row of the image data by shifting the object region A from a leftmost position to the right as illustrated in FIGS. 3(d) and 3(e). When such an operation of reading image data of the blocks of the top row is completed, a similar operation of reading image data of blocks of the next row is performed as illustrated in FIG. 3(f). However, during these operations of reading image data, the generation of addresses is controlled such that each object region A does not spread over adjoining ones of blocks into which the image data are partitioned for an orthogonal transform, whereby each sum of the products is derived from data of a sole block B, similarly as in case of FIG. 2. While a preferred embodiment of the present invention has been described above, it is to be understood that the present invention is not limited thereto and that other modifications will be apparent to those skilled in the art without departing from the spirit of the invention. For example, in the above described embodiment, a unit of an amount of shift of the object region A is not limited to one place (corresponding to a picture element) but may be more than one place, for instance, two places (two picture elements) or three places (three picture elements). Further, in cases of the operations of the above described embodiment explained by referring to FIGS. 2 and 3, the operation of reading image data of an entire input image is performed by serially shifting the object region A in the direction of a row, namely, in the horizontal direction as viewed in the figures. However, an operation of reading image data of an entire input image may be effected by moving the object region A in each block (namely, after all of image data corresponding to addresses of a block are read, image data corresponding to addresses of the next block are read).

Claims: An image filtering system comprising: storage means (1) for storing image data representing an entire input image therein, the image data being partitioned into blocks (B1,B2) for an orthogonal transform, each of the blocks (B1,B2) being composed of a predetermined number of picture elements; address selecting means (4,5) for selecting addresses of said storage means (1), from which image data corresponding to respective object regions (A) and stored at the selected addresses are read, each of said object regions (A) being a predetermined region of said blocks (B1,B2) and being smaller than said blocks (B1,B2); and sum-of-products calculating means (2) for multiplying each of the image data of picture elements read out of said storage means (1) by a corresponding coefficient of an operator, which is comprised of a predetermined number of coefficients, for adding up the thus obtained products for each of the picture elements in a given object region (A) and for outputting a sum signal representing a sum of the products for the given object region (A), said sum signal containing information of a predicted quantity of codes included in said given object region (A), wherein said address selecting means (4,5) selects the addresses such that the read storage areas of said storage means (1) corresponding to each of the object regions (A) do not spread over ones of adjacent blocks (B1,B2). An image filtering system as set forth in claim 1, wherein said address selecting means (4,5) comprises: counter means (4) for receiving the sum signals from said sum-of-products calculating means (2), for increasing a count by 1 every reception of the sum signal, for storing the increased count therein and for outputting a shift signal when the count is increased by 1; and address shifting means (5) for receiving the shift signal from said counter means (4), for shifting a start address, from which a reading of image data is started, by a predetermined amount in response to the shift signal, for generating addresses of picture elements corresponding to an object region (A) to next be accessed unless a storage area of said storage means (1) corresponding to the object region include boundary picture elements of both of the adjoining blocks (B1,B2), and for issuing to said counter means (4) an incrementing signal for increasing the count stored in said counter means (4) without generation of addresses if the storage area of said storage means (1) corresponding to the object region (A) includes the boundary picture elements of both of the adjoining blocks (B1,B2), said counter means (4) increasing the count by 1 in response to the incrementing signal. An image filtering system as set forth in claim 1 or 2, further comprising absolute-values-of-sums calculating means (3) for receiving the sum signals from said sum-of-products means (2), for calculating absolute values of the sums represented by the received sum signals, for accumulating the calculated absolute values of the sums of the products for a frame and for outputting results of the accumulation which contain information of a predetermined quantity of codes included in said frame.

Inventors: ANDO ICHIRO, SUGAHARA TAKAYUKI, ANDO, ICHIRO, SUGAHARA, TAKAYUKI
Applicants: VICTOR COMPANY OF JAPAN, VICTOR COMPANY OF JAPAN, LIMITED
Application year: 1991
Main classification: H04N7
IPC codes: H04N7