A delay line providing an adjustable delay

Abstract: First and second complementary input voltages control the flow of current through first and second switches (20,22) (e.g. semiconductors) each respectively connected in first and second control circuits with a first constant current source (24). When the input voltages change, current starts to increase through one of the control circuits to produce increases in the voltage drop across an impedance (32,34) (e.g. resistor) in such circuit. When a particular voltage difference is produced between the impedance voltage and an adjustable biasing voltage, a third switch (26,28) (e.g. semiconductor) closes to produce a first resultant voltage. The resultant delay in the closure of the third switch is dependent upon the adjustable magnitude of the biasing voltage. As the voltage increases across the impedance in the one control circuit, the voltage decreases across an impedance in the other control circuit. This decreasing voltage causes a second resultant voltage to be produced at a fourth switch (28,26) (e.g. semiconductor). The resultant voltages are respectively introduced to fifth and sixth switches (40,42) (e.g. semiconductors) each connected in a circuit with an individual one of second and third constant current sources (44,46). When the resultant voltages change, the particular one of the fifth and sixth switches receiving an increase in current passes a portion of this current through the associated current source and another portion of this current through a coupling member (48) and the other current source. This delays the state of non-conductivity of the switch connected to the other current source. Output voltages further delayed from the input voltages are accordingly obtained from the fifth and sixth switches.

Description: This invention provides a stage with a delay according to the preamble part of claim 1. Two types of delay lines generally exist in the prior art. One type consists of a family of passive delay lines which use distributed inductance (L) - capacitive (C) components. The sum of the distributed L-C delays add to the desired total delay. Taps connected to the L-C components provide particular fractions of the total delay dependent upon the positions of the taps. The delay resolution is accordingly limited by the number of taps which are in turn limited by the physical dimensions of the taps. This family of passive delay lines also has other undesirable characteristics including output waveform distortion and delay sensitivity to input frequency as a result of changes in the values of the inductances (L) and capacitances (C) with changes in frequency. A second type of delay line constitutes a monolithic delay line designed with a string of stages connected in series. Output signal delay can be achieved by multiplexing taps along the string of stages. Because of this, the resolution of the delay in the monolithic line is limited by the number of taps. Furthermore, since the delay per stage is quite small (less than 100 picoseconds), the total range of delay is limited to the delay per stage multiplied by the number of stages in the monolithic line. Delay lines have existed for a long period of time, probably in the order of at least several decades. In all of that period of time, the limitations of existing gates have been known. These include the limited range of delay provided by a delay line (or delay lines in series), the inability to provide precise and predictable delays and the effect on the delay of changes in the frequency of signals introduced to the line. JP-A- 63 131720 discloses a circuit having a variable delay line. A base potential is introduced to a pair of transistors which are serially connected between a voltage supply and a differential amplifier having transistors whose emitters are connected to a common constant current source. When the base potential is lowered, the base-collector potential of the pair of transistors receiving the base potential is increased and the base-collector of the transistors of the differential amplifier is decreased. Thus, the switching time of the differential amplifier is slowed down. From IBM Technical Disclosure Bulletin, Vol. 16, No. 11, April 1974, a variable delay pulse circuit for receiving a differential pulse input signal and enabling precise pulse delays is known. The circuit comprises a pair of input transistors to which the differential pulse input signal is applied. The collector terminals of the input transistors is connected to a current source and the emitter terminals of the input transistors is connected to a control transistor. The pulse delay is determined by the amplitude of current flowing through the input transistors which in turn is controlled by the control transistor. As the current through the control transistor increases, the delay time from the input terminals to the output terminals of the circuit is decreased. By making the current through the control transistor variable, any intermediate delay can be obtained. The problem of the present invention is to provide a circuit for providing a delay stage which is simple in construction and provides such a delay with low power consumption. The problem is solved according to the present invention by a circuit comprising the features of claim 1. Preferred embodiments are subject to the various dependent claims. One embodiment provides a delay line which overcomes, or at least minimizes, the disadvantages discussed above. For example, the embodiment provides a plurality of stages in series and provides for each stage a delay of as much as six tenths of a nanosecond (0.6 ns) per stage. Furthermore, the delay for each stage can be adjustable to any value within this maximum range. The invention also provides a minimal sensitivity in the changes in delay in each stage as a result of changes in frequency. The invention is able to provide these precise delays in a frequency range greater than two hundred megahertz (200 MHz). The delay line of this invention has a small size and consumes a low amount of power. In one further embodiment of the invention, first and second complementary input voltages control the flow of current through first and second switches (e.g. semiconductor) each respectively connected in first and second control circuits with a first constant current source. When the input voltages change, current starts to increase through one of the control circuits to produce increases in the voltage drop across an impedance (e.g. resistor) connected in such circuit. When a particular voltage difference is produced between the impedance voltage and an adjustable biasing voltage, a third switch (e.g. semiconductor) closes to produce a first resultant voltage. The resultant delay in the closure of the third switch is dependent upon the magnitude of the adjustable biasing voltage. As the voltage increases across the impedance in the one control circuit, the voltage decreases across an impedance connected in the other control circuit. This decreasing voltage causes a second resultant voltage to be produced at a fourth switch (e.g. semiconductor). The resultant voltages are respectively introduced to fifth and sixth switches (e.g. semiconductors) each connected in a circuit with an individual one of second and third constant current sources. When the resultant voltages change, the particular one of the fifth and sixth switches receiving an increase in current passes a portion of this current through the associated current source and another portion of this current through a coupling member and the other current source. This delays the state of non-conductivity of the switch connected to the other current source. Output voltages further delayed from the input voltages are accordingly obtained from the fifth and sixth switches. A plurality of delay stages may be provided, each including the first through sixth switches (e.g. semiconductors). To shorten the response time of each stage while maintaining the delay provided in such stages, the outputs from the third and fourth semi-conductors in each delay stage may be respectively introduced through coupling capacitors to the fifth and sixth transistors in the previous delay stage. This shortens the time between the successive productions of the additional delay by the fifth and sixth semiconductors in each stage in response to the first and second complementary resultant voltages in that stage without affecting the production of such additional delay. In the drawings: Figure 1 is a somewhat simplified circuit diagram of a gate constituting one embodiment of the invention, the gate being included in a delay line also constituting an embodiment of the invention; Figure 2 is a block diagram of the delay line which is formed from a series arrangement of a plurality of the gates shown in Figure 1; Figure 3 illustrates voltage waveforms produced by the gate shown in Figure 1 and illustrates the time delay provided by a first stage in the gate of Figure 1; Figure 4 illustrates voltage waveforms produced by a second stage in the gate shown in Figure 1 and illustrates the time delay provided by such stages; Figure 5 is a schematic diagram indicating how metal layers in an integrated circuit chip may be applied to the emitters of a pair of semiconductors in the gate shown in Figure 1 to enhance the performance of the gate; Figure 6 is a somewhat expanded circuit diagram of the gate shown in Figure 1; Figure 7 is an even more expanded circuit diagram of the gate shown in Figure 1; Figure 8 is a schematic circuit diagram of another embodiment of the invention, this embodiment including two successive delay stages and connections from the second delay stage to the first stage to accelerate the time that the first delay stage is able to respond to successive input voltages; and Figure 9 illustrates voltage waveforms produced by the embodiment shown in Figure 8 to accelerate the time that the first delay stage is able to respond to successive input voltages. Figure 1 is a somewhat simplified circuit diagram of a gate generally indicated at 10 and constituting on embodiment of the invention. The gate includes a plurality of switches each of which may constitute a semiconductor. The gate is preferably formed by bi-polar techniques but may also be formed by other techniques such as C-MOS techniques. When the gate is formed as by bi-polar techniques, a line 12 providing a reference potential such as ground and a line 14 providing an energizing voltage such as -5 volts are provided. A pair of lines 16 and 18 are also included to provide complementary input voltages which may be respectively designated as IN and INN. The voltages on the lines 16 and 18 are respectively introduced to first terminals of a pair of switches such as the bases of semiconductors 20 and 22, both of which may be npn transistors. The emitters of the semiconductors 20 and 22 are common with one terminal of a constant current source 24, the other terminal of the constant current source receiving the energizing voltage on the line 14. The constant current source 24 may be constructed in a conventional manner well known in the prior art. The collectors of the semiconductors 20 and 22 are respectively connected to the first terminals of switches such as the emitters of semiconductors 26 and 28, both of which may be npn transistors. The bases of the semiconductors 26 and 28 receive an adjustable biasing voltage on a line 30. The biasing voltage may be adjustable in a conventional manner well known in the prior art. The collectors of the semiconductors 26 and 28 are common with the reference potential such as ground on the line 12. The collectors of the semiconductors 20 and 22 are also respectively connected to first terminals of impedances such as resistors 32 and 34. The second terminals of the resistors 32 and 34 are common with the cathode of a diode 36, the anode of which is connected to the cathode of a diode 38. The anode of the diode 38 is in turn common with the line 12 providing the ground potential. Each of the diodes 36 and 38 may be constructed to provide a particular potential across the diode. For example, this potential may be approximately seven-tenths of a volt (0.7V.). Connections are also respectively made from the collectors of the semiconductors 20 and 22 to first terminals of switches such as the bases of semiconductors 40 and 42. Constant current sources 44 and 46 constructed in a manner similar to the constant current source 24 are respectively connected between the emitters of the semiconductors 40 and 42 and the line 14 providing the energizing potential of approximately -5 volts. A capacitor 48 is respectively connected between the emitters of the semiconductors 40 and 42. Output lines 50 and 52 respectively extend from the emitters of the semiconductors 40 and 42. The collectors of the semiconductors 40 and 42 are common with the line 12 providing the reference potential such as ground. Assume that current flows through the semi-conductor 22 because of the production of a high voltage on the line 18 to represent a binary "0" and that current does not flow through the semiconductor 20 because of the production of a low voltage on the line 16. A portion of the current through the transistor 22 flows through a circuit including the line 12, the diodes 38 and 36, the resistor 34, the semiconductor 22 and the constant current source 24. The remaining portion of this current flows through the transistor 28. The current through the transistor 22 is substantially constant because of the action of the constant current source. When a high voltage is produced on the line 16 to represent a binary "1", current starts to flow through the semiconductor 20. At the same time, the current through the semiconductor 22 starts to decrease because a low voltage is simultaneously produced on the line 18. A line 74 in Figure 3 indicates the time that the voltage on the base of the semiconductor 20 exceeds the voltage on the base of the semiconductor 22. Since the current through the source 24 is constant and since the diodes 38 and 36 are connected to both the semiconductor 20 and the semiconductor 22, the current through the diodes 38 and 36 remains constant even as the current through the semiconductor 20 is increasing and the current through the semiconductor 22 is decreasing. This constant current causes constant voltages to be produced across the diodes 38 and 36. The voltage across each of the diodes 38 and 36 may be in the order of seven tenths of a volt (0.7V ). As the current through the semiconductor 20 increases, an increasing voltage is produced across the resistor 32. The resultant voltage across the diodes 38 and 36 and the resistor 32 is introduced to the emitter of the semiconductor 26. The semiconductor 26 is constructed to become conductive when the voltage on the base of the semiconductor is greater by a particular value than the voltage on the emitter of the semiconductor. This particular value may be approximately seven tenths of a volt (0.7V ). As will be seen, the time for producing the conductivity of the semiconductor 26 is dependent upon the biasing voltage applied to the line 30. For example, when a biasing voltage of approximately -0.8 volts is provided on the line 30, the semiconductor 26 becomes conductive when the voltage on the emitter of the semiconductor 26 reaches -1.5 volts. similarly, when a biasing voltage of approximately - 1.6 volts is provided on the line 30, the semiconductor 26 becomes conductive when the voltage on the emitter of the semiconductor 26 reaches -2.3 volts. The biasing voltage on the line 30 accordingly controls the voltage swings on the collectors of the semiconductors 20 and 22. As will be-appreciated, since a greater current is required through the resistor 32 for the voltage on the collector of the semiconductor 20 to reach -2.3 volts than to reach -1.5 volts, the delay in the conductivity of the semiconductor 26 is dependent upon the magnitude of the biasing voltage provided on the line 30. This delay increases as the magnitude of the biasing voltage on the line 30 increases. As will be seen in Figure 3, a vertical line 74 is schematically indicated to indicate the time that the voltage on the base of the semiconductor 20 exceeds the voltage on the base of the semiconductor 22 when a high voltage is introduced to the line 16 and a low voltage is introduced to the line 18. When the semiconductor 26 thereafter starts to become conductive, the resultant voltage on the emitter of the semiconductor 26 starts to rise toward ground. This is indicated at 80 in Figure 3. At the same time, the resultant voltage on the emitter of the semiconductor 28 starts to fall. This is indicated at 84 in Figure 3. The time at which the voltage on the emitter of the semiconductor 26 exceeds the voltage on the emitter of the semiconductor 28 is indicated at 86 in Figure 3. The delay in the time required to produce a greater voltage on the emitter of the semiconductor 26 (or the collector of the semiconductor 20) than on the emitter of the semiconductor 28 (or the collector of the semiconductor 22) as a result of the delay provided by the semiconductor 26 is indicated at 88 in Figure 3. As will be seen from the previous discussion, the delay 88 can be adjusted by adjusting the biasing voltage on the line 30. The resultant voltages on the collectors of the semiconductors 20 and 22 are respectively introduced to the bases of the semiconductors 40 and 42. Assume that the voltage on the base of the semiconductor 40 is low and that the voltage on the base of the semiconductor 42 is high, and that the semiconductors are in a non-transient state. The current in the semiconductor 40 corresponds to the current in the current source 44 and the current in the semiconductor 42 corresponds to the current in the current source 46. Assume now that the voltage on the base of the semiconductor 40 rises on a transient basis from low to high as indicated at 84 in Figure 4 and that the voltage on the base of the semiconductor 42 simultaneously falls on a transient basis from high to low as indicated at 80 in Figure 4. The voltage on the emitter of the semiconductor 40 follows the voltage on the base of the semiconductor such that a transient voltage is generated on the emitter of the semiconductor as indicated at 92 in Figure 4. This causes a transient current to flow through the capacitor 48. As a result, a current is generated in the semiconductor 40 during this transient period as a result of the operation of the current source 44 and the flow of a transient current through the capacitor 48. Since the other side of the capacitor 48 is connected to the current source 46, the current through the capacitor 48 (whose direction is the same as the current through the current source 46) will not exceed the current in the source 46. This causes the current through the semiconductor 42 to be equal to the current through the current source 46 minus the current through the capacitor 48. This causes the semiconductor 42 to be deprived of its normal current during the transient period. Thus, even though the base of the semiconductor 42 has assumed a steady state after the transient decrease in voltage on the base, the voltage on the emitter of the semiconductor lags the voltage on the base of the semiconductor until the emitter has received an appropriate share of the current. The transient voltage on the emitter of the semiconductor 42 is indicated at 96 in Figure 4. The delay in the response of the semiconductor 42 relative to the response of the semiconductor 40 may be seen from a comparison in the times for the beginning of the voltage transients 92 and 96. The resultant delay is indicated at 98 in Figure 4. The circuit shown in Figure 1 accordingly provides two (2) time delays. One of these time delays is produced by the stage including the semiconductors 20, 22, 26 and 28 and the constant current source 24. The delay provided by this stage can be adjusted by varying the biasing voltage applied to the line 30. As will be appreciated, this delay can be continuously adjustable to any desired value within the range of delays provided by the semiconductor 20, 22, 26 and 28. A second delay can be provided in a stage including the semiconductors 40 and 42 and the constant current sources 44 and 46. The total amount of delay provided by the circuit shown in Figure 1 can be as much as six tenths of a nanosecond (0.6 ns). The circuit shown in Figure 1 has other important advantages in addition to providing a continuously adjustable delay. As will be seen, the circuit shown in Figure 1 has no inductances and only a single capacitor constituting the coupling capacitor 48. The delay provided by the circuit shown in Figure 1 is accordingly affected only minimally, if at all, by changes in frequency. This is true through a frequency range in excess of two hundred megahertz (200 MHz). Furthermore, the circuit (or gate) shown in Figure 1 has a small size and low power consumption. As will be appreciated, the circuit (or gate) shown in Figure 1 can be included in a delay line formed from a plurality of stages of identical construction. This is shown in Figure 2. In that Figure, a plurality of delay stages generally indicated at 10a, 10b, 10c, etc., of identical construction are connected in series. The output lines from each delay stage correspond to the lines 50 and 52 in Figure 1. The input lines to the next delay stage correspond to the lines 16, 18 and 30 in Figure 1 and to the line 94 in Figures 6 and 7. In order to provide the semiconductors 40 and 42 in Figure 1 with substantially equal characteristics, connections are made symmetrically to the emitters of the semiconductors. These symmetrical connections are shown schematically in Figure 5. As illustrated in Figure 5, a "metal 3" line at a position above the semiconductor 40 is coupled to a "metal 2" line which is connected to the emitter of the semiconductor 42. Similarly, a "metal 3" line at a position above the semiconductor 42 is coupled to a "metal 2" line at a position above the semiconductor 40, and the "metal 2" line is connected to the emitter of the semiconductor 40. The "metal 2" and "metal 3" lines are normally found in bi-polar chips to provide voltages at various terminals in the chips. Capacitors 99 shown connected between the "metal 2" and "metal 3" lines are schematic representations of distributed capacitances between the lines. Cross connections are provided between the metal 2 and metal 3 lines so that the distributed capacitances (other than those defining the capacitance 48) at the emitters of the transistors 40 and 42 will be balanced. The circuit shown in Figure 6 is substantially identical to the circuit shown in Figure 1 except for certain minor changes and additions. The circuit shown in Figure 6 includes a capacitor 100 connected between the lines 12 and 30 to filter noise. The circuit shown in Figure 6 also includes a capacitor 102 connected between the line 14 and a line 94 tQ filter noise. The line 94 provides a biasing voltage. In Figure 6, the constant current sources 24, 44 and 46 of Figure 1 are respectively shown as transistors 106, 108 and 110, all of which may be npn transistors. The bases of the transistors 106, 108 and 110 are biased at a constant voltage by the voltage on the line 94. Resistors 114, 116 and 118 are respectively connected between the emitters of the transistors 106, 108 and 110 and the line 14. Resistors 120 and 122 may also be respectively connected between the collectors of the semiconductors 108 and 110 and the emitters of the semiconductors 40 and 42. As will be seen, the diodes 38 and 36 constitute in Figure 6 npn semiconductors 130 and 132 in each of which the base and collector have a common connection. Furthermore, the collectors of the semiconductors 26 and 28 are shown in Figure 6 as being connected to the base and collector of the semiconductor 132 and the emitter of the semiconductor 130. These connections do not affect the operation of the circuit as described above. The circuit shown in Figure 7 is identical to the circuit shown in Figure 6 except for some minor changes. As shown in Figure 7, the filter capacitor 100 is formed from a pair of semiconductors 140 and 142 each of which may be npn semiconductors. The base of each of the semiconductors 140 and 142 may be connected to the biasing line 30 and the emitter and collector of each semiconductor may be connected to the reference line 12. Similarly, the filter capacitor 102 may be formed from a pair of semiconductors 144 and 146 which may be npn transistors. The base of each of the transistors 144 and 146 may be connected to the line 14 and the emitter of each of these semiconductors may be connected to the biasing line 94. The collectors of the semiconductors 144 and 146 are connected to the reference line 12. Figure 8 illustrates a circuit for accelerating the response time to successive input voltages on the lines 16 and 18 of the gate shown in Fig 1. The circuit shown in Figure 8 includes the delay stages shown in Figure 2, only the delay stages 10a and 10b being shown in Figure 8 for purposes of illustration. In the circuit shown in Figure 8, the voltages on the collectors of the semiconductors 20b and 22b in the delay stage 10b are respectively coupled through capacitors 400 and 402 to the emitters of the semiconductors 108a and 110a (see Figure 6) in the delay stage 10a. Similar connections may be made from each delay stage in Figure 2 to the previous stage in Figure 2. Figure 9 illustrates the voltages respectively produced on the emitters of the transistors 108a and 110a in the delay stage 10a in Figure 8 when the voltages produced on the collectors of the transistors 20b and 22b in the delay stage 10b are respectively introduced through the coupling capacitors 400 and 402 to the emitters of the semiconductors 108a and 110a (see Figure 6) in the delay stage 10a. As will be seen in Figure 9, the feedback of the voltages on the collectors of the semiconductors 20b and 22b in the delay stage 10b to the emitters of the semiconductors 108a and 110a in the delay stage 10a accelerates the time that the emitters of the semiconductors 108a and 110a reach a steady state voltage. This shortens the time in which the semiconductors 108a and 110a in the delay stage 10a become ready to respond to updated input voltages on the lines 16 and 18 in Figure 1. This may be seen by comparing (in Figure 4) the slope of the voltage 96 on the emitter of the semiconductor 108a in Figure 6 with the slope (in Figure 9) of the voltage 404 on the emitter of the semiconductor 110a in Figure 8.

Claims: Circuit for providing a delay stage comprising a current means (44,46,108,110), first and second switching means (40,42), means including the first switching means (40) for defining a first current path, means including the second switching means (42) for defining a second current path, means for introducing a first voltage to the first switching means (40) to produce a current through the first current path in response to the first voltage, and means for introducing a second voltage to the second switching means (42) to produce a current through the second current path in response to the second voltage, characterized in that said current means comprises a first and second current source (44,46), each providing a substantially constant current, the first current path includes the first current source (44) and the first switching means (40) for providing a substantially constant current and the second current path includes the second current source (46) and the second switching means (42) for providing a substantially constant current, and coupling means (48) are connected between the first and second paths for passing a portion of the current flowing through the switching means (42) in the second path to the current source (44) in the first path in response to differences between the first voltage introduced to the first switching means (40) and the second voltage introduced to the second switching means (42) to maintain the constant current through the first current source (44) and the constant current through the second current source (46) while providing a delay in the production of an output voltage between the first switching means (40) and the second switching means (42). Circuit according to claim 1, characterized in that the coupling means (48) are connected between the first and second switching means (40,42). Circuit according to claim 1 or 2, characterized in that the coupling means are a capacitance (48). Circuit according to one of claims 1 to 3, characterized in that the coupling means include means (48) connected to the first and second switching means (40,42) for obtaining first and second output voltages delayed relative to each other. Circuit according to one of claims 1 to 4, characterized by further comprising means (30) for providing an adjustable biasing voltage, and means (26,28) responsive to the adjustable biasing voltage for providing the first and second voltages. Circuit according to claim 5, characterized by further comprising means (16,18) for providing first and second input voltages, means (20,22,24) responsive to the first and second input voltages and the adjustable biasing voltage for providing the first and second voltages which are delayed from the first and second input voltages in accordance with the adjustments in the biasing voltage. Circuit according to claim 6, characterized in that the means for providing the first and second voltages comprise means (24) for providing a constant current, means (20) responsive to changes in the first input voltage for producing changes in the first voltage at a first particular terminal in accordance with such changes in the first input voltage, means (22) responsive to changes in the second input voltage for producing changes in the second voltage at a second particular terminal in accordance with such changes in the second input voltage, means (26) operatively coupled to the first particular terminal and responsive to the adjustable biasing voltage and the changes in the first voltage at the first particular terminal for maintaining the first voltage at the first particular terminal at a first particular level when a relationship exists between the adjustable biasing voltage and the first voltage, and means (28) operatively coupled to the second particular terminal and responsive to the adjustable biasing voltage and the changes in the second voltage at the second particular terminal for maintaining the second voltage at the second particular terminal at a second particular level when the particular relationship exists between the adjustable biasing voltage and the second voltage. Circuit according to one of claims 1 to 7, characterized by further comprising means (12) for providing a reference potential, the first and second switching means (40,42) respectively including first and second semiconductor devices each having first, second and third terminals, the first terminal in each semiconductor device being connected to receive an individual one of the first and second voltages, the second terminal in each semiconductor device being connected to an individual one of the first and second constant current means, the third terminal of each semiconductor device being connected to the reference potential means (12). Circuit according to claim 7, characterized in that the means for providing the first and second voltages further comprise a first and second impedance (32,34); a third and fourth switching means (20,22) being responsive to an individual one of the first and second input voltages for producing at the individual one of the impedances the voltage with changes in magnitudes in accordance with the changes in the individual one of the first and second input voltages, a fifth and sixth switching means (26,28) each having open and closed states and each responsive to the adjustable biasing voltage and to the changes in the magnitude of the voltage at an individual one of the first and second impedances (32,34) for becoming operative in the closed state in accordance with voltage difference between the adjustable biasing voltage and the voltage at the individual one of the first and second impedances to limit any further changes in the magnitude of the voltages at the first and second impedances (32,34) upon becoming operative. Circuit comprising two circuits according to one of claims 1 to 9, each providing for a first and second delay stage respectively, characterized by further comprising means for introducing the output voltages from the first delay stage (10a) as the input voltages to the second delay stage (10b), means (400,402) respectively coupling the first delay stage (10a) to the second delay stage (10b) to accelerate the time in which the first delay stage is able to respond to the first and second input voltages.

Inventors: MOLIN STUART B, MOLIN, STUART B.
Applicants: BROOKTREE CORP, BROOKTREE CORPORATION
Application year: 1991
Main classification: H03H11
IPC codes: H03H11