Initialising computer systems

Abstract: An initialisation system is disclosed for a close-coupled multiprocessor system which includes a plurality of processors (P1 to P4) and one main memory (2) connected to the processors through a system bus (SB). The initialisation system (31 to 34) is connected to the processors (P1 to P4) through the system bus, and includes: a first storage (31) for storing identification (ID) codes corresponding respectively to the processors, one of the ID codes designating a master processor and other ID codes having a priority for designating the next master processor; a second storage (32) for storing a program to initialise the system and a program to supervise an initialisation time; a first information unit (33) for indicating the start of operation of the processors; and a second information unit (34) for indicating the completion of initialisation of the master processor. Such an initialisation system can permit the main system to be initialised properly even if the first designated master processor fails to complete the initialisation operation successfully.

Description: The present invention relates to initialising system such as, for example, close-coupled multiprocessor systems which include a plurality of processors and one main memory connected to the processors through a system bus. Recently, multiprocessor systems have been widely used in computer systems. In general, there are two kinds of multiprocessor systems, namely a close-coupled type and coarse-coupled type. The former has one main memory used in common for all processors, whereas the latter has a plurality of memories each connected to the processor. An embodiment of the present invention relates to the close-coupled multiprocessor system. In a close-coupled multiprocessor system, any one of processors (referred to as a "master processor") runs an initial programm loading (referred to hereinafter as IPL) operation when setting up the system, and other processors wait until the IPL operation is completed. After the IPL operation is normally completed by the master processor, the system can operate. In a previously-proposed system the processor that becomes the master processor has been previously determined by a computer maker. Accordingly, if a fault accidentally occurs in the master processor, the IPL operation can not be completed so that the system can not operate. In this case, since other processors must wait until the master processor is operational, it is impossible to immediately constitute a new system based on other processors other than the master processor. To overcome this problem JP-A-63-83856 proposes data processing apparatus including a plurality of individual processors; and initialisation means, connected to the said processors and including processor designating means designating a first one of the processors as a higher priority processor than a second one of the processors, for causing the designated first processor to commence an initialisation operation in response to a predetermined event and, if that processor fails to complete the operation successfully, for causing the designated second processor to commence the said initialisation operation. In this prior apparatus the processor designating means includes a flag register which has one flag bit for each of the processors PO - Pn. The order (0, 1, ... n) of the flag bits in the flag register denotes the priority order of the processors for performing the initialisation operation. Each time the initialisation operation is commenced the processors PO - Pn check the flag register and one of them determines that it is the designated processor if its flag bit is set and all the higher-priority flag bits are reset. The flag bits are initially all set before the start of the initialisation operation so that when the initialisation operation is first commenced the processor P0 is designated to perform the operation (bit 0 = 1, no higher-priority flag bits). If the processor P0 fails to complete the initialisation operation successfully, flag bit 0 is reset so that when the initialisation operation commences again the processor P1 is designated (bit 0 = 0; bit 1 = 1). However, in this prior apparatus the priority order of the processors is determined by the order of the flag bits in the flag register and it is not possible to select the processors for use in the initialisation operation freely from the available processors or to choose the priority order of those selected processors. According to the present invention the designated first and second processors have different respective identification codes and the processor designating means includes a first storage unit storing the identification codes of the designated first and second processors and assigning an order of priority to the stored identification codes so that the identification code of the designated first processor is assigned a higher priority than that of the designated second processor; and the order in which the processors perform the initialisation operation is determined by the assigned priority order of the stored identification codes; the determination of such failure of the currently-designated processor being made after expiry of a predetermined time interval following commencement by that processor of the operation. Reference will now be made, by way of example, to the accompanying drawings; in which: Fig. 1 is a schematic block diagram of a close-coupled multiprocessor system having an initialization system embodying the present invention; Fig. 2 is a detailed block diagram of the close-coupled multiprocessor system shown in Fig. 1; and Fig. 3 is a flowchart for explaining operation of an initialization system shown in Fig. 2. Figure 1 is a schematic block diagram of a close-coupled multiprocessor system having an initialization system embodying the present invention. In Fig. 1, reference number 1 denotes processors (MPU), 2 a storage (MEM), 3 an initialization system, and SB a system bus. The close-coupled multiprocessor system 1 includes a plurality of processors P1 to Pn and the main memory 2 connected to the processors P1 to Pn through the system bus SB. Further, the initialization system 3 is connected to the processors P1 to Pn through the system bus SB. The initialization system 3 includes: a first storage 31 for storing identification (ID) codes corresponding respectively to the processors,one of ID codes designating a master processor, and other ID codes having a priority for designating the next master processor; a second storage 32 for storing a program to initialize the system and a program to supervise an initialization time (predetermined time interval); a first information unit 33 for informing of the start of operation of the processors; and a second information unit 34 for informing of the completion of initialization of the master processor. Figure 2 is a detailed block diagram of the close-coupled multiprocessor system shown in Fig. 1. In Fig. 2, reference number 4 denotes an adaptor (ADP), 5 an external storage device (DISK), and 6 a display device (DPL). The external storage device 5 stores a system program. The adaptor 4 is used for controlling the read of the system program from the external storage device 5 and for writing it into the memory 2. Each processor P1 to P4 has a register ID1 to ID4 for storing the ID code of its own processor (referred to hereinafter as the "self ID code"). The first storage 31 has, for example, a non-volatile memory for storing ID codes corresponding respectively to the ID codesof the processors. In this case, one of the ID codes is designated as the master processor (referred to hereinafter as the "master ID code") and other ID codes have a priority to designate the master processor. For example, the processor P1 may be designated as the master, and the priority of the other processors P2 to P4 may be given by P2>P3>P4. Accordingly,if a fault occurs in the designated first processor P1 in the IPL operation, the processor P2 is designated as the master processor (designated second processor) as explained in detail below. The second storage 32 has, for example, a read only memory (ROM) for storing an initialization program to initialize the system. The initialization program is shown in Fig. 3. The ROM further includes a supervisory program for supervising initialization time of the master processor and a flag for indicating completion of the initialization. The first information unit 33 has, for example, registers R1 to R4 corresponding respectively to the processors P1 to P4. Each register R1 to R4 stores a flag indicating the start of an operation (referred to hereinafter as "start flag"). In this system, all start flags (when all processors are normal) are turned ON when the system is set up. The second information unit 34 has, for example, a register R5. The register R5 stores a flag indicating completion of the initialization by the master processor (referred to hereinafter as the "completion flag"). When the initialistion operation is normally completed by the master processor P1, the completion flag is turned ON in the register R5. As explained below, other processors P2 to P4 supervise or monitor this completion flag. If the completion flag is not turned ON after a predetermined initialization time (predetermined time interval), one of other processors having the highest priority becomes the master processor instead of the master processor P1. Figure 3 is a flowchart for explaining operation of the initialization system shown in Fig. 2. This flowchart is stored in the ROM 32 as the initialization program. When the power is turned ON or the system is set up (i.e. in response to a predetermined event), all processors set the start flag in the corresponding register R1 to R4 in the first information unit 33 (step 1). Next, each processor P1 to P4 compares its self ID code with the ID codes in the non-volatile memory 31, and determines whether or not its self ID code coincides with the master ID code (step 2). Since in the example of Fig. 2 the self ID code of processor P1 coincides with the master ID code (YES), the master processor P1 runs the IPL operation (step 3). Further, the master processor P1 determines whether or not the IPL operation is normally completed (step 4). When the IPL operation is normally completed (YES), the master processor P1 sets the completion flag in the register R5 of the second information unit 34 (step 5). Further, in step 4, the master processor P1 reads the system program stored in the DISK 5 and stores it into the memory 2 through the adaptor 4. However, when a fault occurs in other devices, for example, the adaptor 4, the DISK 5 and the display 6, the system is down as an abnormal failure (step 9). Meanwhile, other processors P2 to P4 monitor the completion flag of the master processor P1 for a predetermined supervisory time based on the initialisation time of the master processor P1 (step 6). The initialisation time is determined by the time necessary for initialising the system. If the completion flag of the second information unit 34 is not turned ON within the predetermined supervisory time, i.e. if the initialization time is longer than the predetermined supervisory time (YES), because a fault has occured in the master processor P1, another processor, having the highest priority after the processor P1, must be identified to become the new master processor (step 10). Next, the new master processor, for example the processor P2 determines whether or not its self ID code coincides with the ID code having the highest priority (step 11). If its self ID code coincides with the ID code (YES) as the master processor, the IPL operation of the master processor P2 restarts from step 3. When the self ID code of the master processor P2 does not coincide with the ID code having the highest priority, any other processor having the next priority becomes the new master processor in step 10. Further, other processors P3 and P4 supervise the completion flag of the master processor P2 during initialization time thereof. When the initialization time is not over (NO, in step 6) and the completion flag is turned ON (YES, in step 7), this means that the IPL operation by the master processor P2 is completed (step 8). Still further, if a fault occurs in the processor P2, another of the processors having the next priority, for example the processor P3, performs the same operation of the initialization as explained above from the steps 10 and 11. Accordingly, even if a fault occurs in any of the processors, it is possible to quickly set up the system. In other embodiments, it is possible to use a dipswitch instead of the non-volatile memory 31. The dipswitch has a plurality of ON/OFF contacts. Accordingly, it is possible to designate the master ID code based on the ON state of the contact.

Claims: Data processing apparatus including a plurality of individual processors (P1 to P4); and initialisation means (3), connected to the said processors and including processor designating means (31) designating a first one (P1) of the processors as a higher priority processor than a second one (P2) of the processors, for causing the designated first processor to commence an initialisation operation in response to a predetermined event and, if that processor fails to complete the operation successfully, for causing the designated second processor to commence the said initialisation operation; characterised in that the designated first and second processors (P1, P2) have different respective identification codes and the processor designating means includes a first storage unit (31) storing the identification codes of the designated first and second processors and assigning an order of priority to the stored identification codes so that the identification code of the designated first processor is assigned a higher priority than that of the designated second processor; and in that the order in which the processors perform the initialisation operation is determined by the assigned priority order of the stored identification codes; the determination of such failure of the currently-designated processor being made after expiry of a predetermined time interval following commencement by that processor of the operation. Data processing apparatus as claimed in claim 1, being of the close-coupled type including a single main memory (2) connected to each of the said processors by way of a system bus (SB), the said initialisation means (3) also being connected to the said processors (P1 to P4) by way of the said system bus. Data processing apparatus as claimed in claim 1 or 2, wherein the said first storage unit (31) comprises a non-volatile memory. Data processing apparatus as claimed in claim 1, 2 or 3, wherein the said initialisation means (3) further include: a second storage unit (32) storing a program used to initialise the apparatus and a program used to detect the said expiry of the said predetermined time interval; first information means (33) for indicating whether or not each processor has started to operate normally; and second information means (34) for indicating whether or not the said initialisation operation has been completed successfully by one of the designated processors. Data processing apparatus as claimed in claim 4, wherein the said second storage unit (32) comprises a read only memory (ROM). Data processing apparatus as claimed in claim 4 or 5, wherein the said first information means (33) comprise registers (R1 to R4) corresponding respectively to the said processors (P1 to P4), each such register serving to store a flag indicating the start of normal operation by the processor concerned. Data processing apparatus as claimed in any one of claims 4 to 6, wherein the said second information means (34) comprise a register (R5) for storing a flag indicating successful completion of the initialisation operation by one of the designated processors. Data processing apparatus as claimed in claim 7, wherein the completion flag is turned ON when the said initialisation operation is completed successfully by the designated first processor (P1), the other processors (P2 to P4) being operative to monitor the said completion flag and, if it is not turned ON within the said predetermined time interval, to determine from the identification codes stored in the said first storage unit (31) which one of them is the designated second processor, whereupon that designated second processor (P2) then commences the initialisation operation.

Inventors: IKEDA KAZUHIKO, SAKAI SATORU, IKEDA, KAZUHIKO, SAKAI, SATORU, Ikeda, Kazuhiko, c/o PFU Limited, Sakai, Satoru, c/o Fujitsu Limited
Applicants: FUJITSU LTD, PFU LTD, FUJITSU LIMITED, PFU LIMITED
Application year: 1991
Main classification: G06F15
IPC codes: G06F15