Superimposition of still pictures consisting of characters

Abstract: A video display apparatus (18,20) includes a video data generator (12) which generates video data of a still picture (32) and a moving picture (34) (graphic data) on the basis of still picture pattern, still picture character code, moving picture character code and etc. programmed in an external storage (16) unit in advance. A microprocessor (10) applies, in accordance with priority data for the still picture and the moving picture and mode data (26) both programmed in the external storage unit in advance, first priority data (46) to the video data of the still picture character and second priority data (66) to the video data of the moving picture character, respectively. A priority encoder (130) selects a still picture character or a moving picture character having the highest priority on the basis of the first and second priority data, and applies the number of that character to a decoder (132). The decoder outputs a gate control signal (144) in accordance with the number. In response to the gate control signal, the video data of the character having the highest priority among the respective still picture character and the moving picture character is outputted from a gate (80).

Description: BACKGROUND OF THE INVENTION Field of the invention The present invention relates to a video display apparatus and a combination of an external storage unit and the video display apparatus. More specifically, the present invention relates to a video display apparatus which displays a plurality of still picture cells (and moving picture) in an overlaid state onto a monitor screen. description of the prior art For example, Japanese patent publication No. JP-A-2-7478 published on February 19, 1990 (corresponding to US Patent No. US-A-4 824 106) discloses a video display apparatus to be utilized effectively for a television game machine or the like. In the prior art, when a moving picture (object character) and a background or still picture (still picture character) are displayed in overlaid state, in order to determine which is to be displayed at a front side of a monitor screen, priority data denoted by "0" or "1" is applied, and in a multiplexer, a moving picture or a still picture having the priority data being "1" is selected to be displayed. When a plurality of still picture cells are used, the still picture cells can be displayed with the order inverted utilizing the prior art as above described. In this method, however, only each still picture cell as a whole can be inverted. On the other hand, in order to increase variety of a game or to improve visual effect, a request occurs to display a plurality of still picture cells inverted partially, for example, per each character. In order to respond to such a request, in a case of utilizing the prior art as above described, still picture video data may be rewritten during a vertical (V) blanking period. However, the still picture video data to be rewritten are video data of a whole monitor screen of all of the still picture cells. Particularly, when the still picture cells are many in number, amount of the data to be rewritten becomes enormous. Consequently, in the prior art, in fact, a plurality of still picture cells cannot be displayed partially changing the priority. EP-A-0160549 describes a video special effects circuit which operates to mix multiple video images from different channels into a single image using key and priority signals and providing scaling, positioning and fading effects. Different portions of the image may be overlaid in a "transparent" fashion. SUMMARY OF THE INVENTION Therefore, a principal object of the present invention is to provide a video display apparatus in which portions of a plurality of still picture cells can be displayed with the order inverted when the still picture cells are overlaid. This object is realised by a video display apparatus as claimed in appended claim 1 and a combination of a video display apparatus and an external storage unit, as claimed in appended claim 7. According to the present invention, since the first priority data is applied per each character of the still picture cells, and based on this, the selecting means selectively outputs the video data of the still picture character of one still picture cell having the highest priority, the still picture cells can be easily displayed with the order inverted per each character. The objects and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the embodiments of the present invention when taken in conjunction with accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram showing an embodiment in accordance with the present invention; Figure 2 is a block diagram showing a timing signal generator of the embodiment in Figure 1; Figure 3 is a block diagram showing a background picture data generator of the embodiment in Figure 1; Figure 4 is an illustrative view showing an example of a data format of background pattern data; Figure 5 is a block diagram showing a moving picture data generator of the embodiment in Figure 1; Figure 6 is an illustrative view showing an example of a data format of object data (attribute data); Figure 7 is a circuit diagram of a transparency detecting circuit included in a composite circuit of the embodiment in Figure 1; Figure 8 is a block diagram showing a picture data control circuit included in the composite circuit of the embodiment in Figure 1; Figure 9 is a circuit diagram showing a picture data selecting circuit included in the composite circuit of the embodiment in Figure 1; Figure 10 is a circuit diagram showing a modification of the embodiment in Figure 9; and Figures. 11A - 11D are illustrative views showing different display states in the embodiment respectively, where Figure 11A shows mode 0, Figure 11B shows mode 1, Figure 11C shows mode 2, and Figure 11D shows mode 3. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to Figure 1, a CPU 10 controls overall operation of a picture display apparatus such as a video processor 12 in accordance with program data from a program data memory unit 14 included in a memory cartridge of detachable type, for example. As the CPU 10, for example, a microprocessor of 16 bits may be used. The video processor 12 reads graphic data (dot data) from a video data memory unit 16 in accordance with command based on the program from the program data memory unit 14 and thus the microprocessor or CPU 10, and applies read data to a TV interface 18. The video data memory unit 16 comprises an SRAM (Static Random Access Memory) of 64K bytes for example, and includes a background pattern area 16a and a character data area 16b. The background pattern area 16a and the character data area 16b are in one SRAM as above described, because the operation speed is rapid and size of the memory area can be arbitrarily set with respect to the character (object) and background pattern. The TV interface 18 converts the graphic data from the video processor 12 into an RGB signal or TV signal, and supplies the signal to a monitor 20. Consequently, on a screen of the monitor 20, with progress of the program set in advance to the program data memory unit 14, a moving picture (object) of a video game and a still picture (background picture) are displayed. The video processor 12 includes a CPU interface 22 which includes an address decoder 24, a mode register 26 and a mode decoder 28. The address decoder 24 decodes address data outputted from the CPU 10 to an address bus and applies a latch signal to the mode register 26, and outputs other necessary timing signals VRAMDT, VRAMDTWR, VRAMAD and OBJDT. The mode register 26 latches mode data outputted from the CPU 10 to a data bus in response to the latch signal from the address decoder 24, and supplies latched data to the mode decoder 28. In addition, such mode data is programmed in the program data memory unit 14 in advance, as data of one byte. The mode data is normally programmed at the beginning of the program, but a plurality of mode data may be programmed as necessary. Then, the mode data is read by the CPU 10 to be transferred to the mode register 26. The mode decoder 28 decodes the mode data from the mode register 26, and outputs a mode signal M0-M3 representing each mode described later referring to FIGs. 11A - 11D. In addition, from the mode register 26, a signal BG3TOP is outputted so as to indicate whether or not a specific background picture cell (in this embodiment, a third background picture cell BG3 as later described) is to be displayed at a nearest side on the screen of the monitor 20. However, as the signal BG3TOP, the most significant bit of the mode register 26 is outputted as it is. The video processor 12 is provided with a timing signal generator 30 as shown in Figure 2. The timing signal generator 30 receives a base clock of 21. 47727 MHz for example, and processes the base clock, for example, by a counter, a decoder, a logic circuit or the like thereby prepares necessary timing signals and supplies the same to respective circuits included in the video processor 12. For example, if the base clock is subjected to frequency dividing at 1/2, a timing signal /10M (in the specification, a symbol "/" means inversion) can be obtained. The signal /10M is further subjected to frequency dividing at 1/2, and a resulting signal corresponds to a display period of one dot (pixel) on the screen of the monitor 20 (Figure 1). So by counting this signal, V position data and H position data respectively indicating a vertical position (V position) and a horizontal position (H position) on the screen of the monitor 20 can be obtained. A timing signal BGEN is applied to a background picture data generator 32 (Figure 3) as described later so as to specify a timing when an address is to be applied to the video data memory unit 16, and a timing signal OBJEN is applied to a moving picture data generator 34 as described later so as to specify a timing when an address is to be applied to the video data memory unit 16. A timing signal ADSW is a signal to command address changing in the background picture data generator 32. A timing signal NDR functions as a latch signal for a name register 44 (Figure 3) as described later. A timing signal PDR functions as a latch signal for a priority data register 46 (Figure 3) as described later. A timing signal DDR functions as a latch signal for a dot data register 50 (Figure 3) as described later. A timing signal PSLOAD is a latch signal which is applied to a P/S converter 52 and a priority data latch 54 (Figure 3) as described later. A timing signal PSSHFT is applied to the P/S converter 52 (Figure 3), and functions as a conversion command signal of the P/S converter 52. A timing signal DDLD functions as a latch signal for a dot data register 70 (Figure 5) as described later. A timing signal PRLD functions as a latch signal for a priority data register 66 (Figure 5) as described later. A timing signal PSSH is applied to a line buffer address circuit 64 and a P/S converter 72 (Figure 5) as described later, and the P/S converter 72, receiving the timing signal PSSH, shifts the character data, and in synchronization with the P/S converter 72 shifting the data, the line buffer address circuit 64 increments an address value of a line buffer 74 (Figure 5) as described later. A timing signal PSLD functions as a latch signal for the P/S converter 72. A timing signal HB is a signal representing a horizontal blanking period, and is applied to the moving picture data generator 32 shown in Figure 5 so that the moving picture data is rewritten during the horizontal blanking period. The background picture data generator 32 shown in Figure 1 will be shown in Figure 3 in detail. In the background pattern area 16a of the video data memory unit 16, background (still picture) pattern data shown in Figure 4 are stored per each background (still picture) character. More specifically, the background character data representative of one character includes name data (character code) of ten(10) bits, color data of three(3) bits, priority data of one(1) bit and flip data of two(2) bits. Such background pattern data, in response to the signal VRAMDTWR from the address decoder 24 (Figure 1), is written from the program data memory unit 14 into the video data memory unit 16 by the CPU 10 through the background picture data generator 32. At an initialized state or during the vertical blanking period, the CPU 10 (Figure 1) outputs a VRAM address value to the data bus corresponding to a position of the character on the screen in accordance with the program incorporated in the program data memory unit 14, and outputs a port address to the address bus corresponding to the address latch 36. The address decoder 24, receiving the port address, outputs the latch signal VRAMAD to the address latch 36. The address latch 36, receiving the signal VRAMAD, latches the address value outputted from the CPU 10 at that time. Thereafter, the CPU 10 outputs the name data indicating a kind of character and the priority data indicating priority of the character to the data bus in accordance with the program, and outputs a port address to the address bus corresponding to the video data memory unit 16. The address decoder 24, receiving the port address, supplies the signal VRAMDT to a data gate 38 and an address changing circuit 40, and supplies the signal VRAMDTWR to the video data memory unit 16. The data gate 38, receiving the signal VRAMDT, outputs the data transmitted from the CPU 10 to the data bus at that time to the video data memory unit 1. Receiving the signal VRAMDT from the address decoder and the signal BGEN from the timing signal generator 30 (Figure 2), the address changing circuit 40 applies a content of the address latch 36 to the video data memory unit (VRAM) 16. In response to the signal VRAMDTWR, the video data memory unit 16 writes the name data and the priority data (Figure 4) from the CPU 10 into the address outputted from the address changing circuit 40. Thus, at the initialized state or during the V blanking period, the background pattern data shown in Figure 4 are written from the CPU 10 into the video data memory unit 16. From the video data memory unit 16, the background pattern data shown in Figure 4 are read during a horizontal scanning period. More specifically, a VRAM address arithmetic circuit 42 calculates an address value of the background pattern area 16a in the video data memory unit 16 corresponding to a position of a scanning line on the screen of the monitor 20 (Figure 1) based on the H position data and the V position data from the timing signal generator 30, and supplies the address value to the address changing circuit 40. The address changing circuit 40 receives the signals ADSW and BGEN from the timing signal generator 30, and outputs the address value from the VRDM address arithmetic circuit 42 to the video data memory unit 16. When the address value is applied, the background pattern data shown in Figure 4 are outputted from the video data memory unit 16. The name data included in the background pattern data is latched to the name register 44 in response to the signal NDR from the timing signal generator 30. The priority data is latched to the priority data register 46 in response to the signal PDR from the timing signal generator 30. A character data address arithmetic circuit 48 calculates an address value of the character data area 16b in the video data memory unit 16 corresponding to a position of a scanning line on the screen based on the character code, i.e., the name data latched in the name register 44 and the V position data applied from the timing signal generator 30, and outputs an address value to the address changing circuit 40. The address changing circuit 40 applies the address value from the character data address arithmetic circuit 48 to the video data memory unit 16 in response to the signals ADSW and BGEN from the timing signal generator 30. Accordingly, from the video data memory unit 16, graphic data (dot data) constituting the character expressed by the name data is outputted. The dot data is latched to a dot data register 50 in response to the signal NDR from the timing signal generator 30. When data of a plurality of bits per one dot is necessary, reading of the video data memory unit 16 by the previous character data address arithmetic circuit 48 is repeated by the number corresponding to the bit number, and the dot data corresponding to each bit is latched to the dot data register 50. Furthermore, when a plurality of background picture cells are displayed, reading of the above-mentioned name data and the priority data and reading of the dot data are repeated by the number corresponding to the number of the background picture (still picture) cells, and the priority data and the dot data corresponding to respective still picture cells are latched to the priority data register 46 and the dot data register 50. The dot data of the background picture characters thus latched to the dot data register 50 is latched by the P/S converter 52 in response to the signal PSLOAD from the timing signal generator 30. At the same time, the priority data stored in the priority data register 46 are latched by the priority data latch 54. The P/S converter 52 and the priority data latch 54 are prepared respectively by the number corresponding to the number of the background picture cells, and the dot data and the priority data of respective background picture cells are latched simultaneously to the P/S converter 52 and the priority data latch 54. In addition, in this embodiment, at most four background picture cells can be displayed, and it is determined by the signal M0-M3 from the mode decoder 28 (Figure 1) which background picture cell(s) should be used. The P/S converter 52 converts previousty latched dot data into video data of one dot unit in response to the signal PSSHFT from the timing signal generator 30. At the same time, the priority data latch 54 outputs the priority data to a composite circuit 76 (Figure 1) described later. The moving picture data generator 34 shown in Figure 1 will be shown in Figure 5 in detail. The moving picture data generator 34 shown in Figure 5 includes an OAM (Object Attribute Memory) 56, which has storage capacity of 34 bits x 128, for example, and can store object data (attribute data) of objects of total 128 pieces. The object data as shown in Figure 6 is composed of total 34 bits, and includes object designating data (name data) of nine(9) bits, V position data of eight(8) bits, H position data of nine(9) bits, color data of three(3) bits, priority data of two(2) bits, flip data of two(2) bits and object size selecting data of one(1) bit. Such object data is also written from the program data memory unit 14 into the OAM 56 by the CPU 10 through the moving picture data generator 34. In addition, an address of the OAM 56 is designated by an OAM address circuit 58. More specifically, at an initialized state or during the V blanking period, the CPU 10 (Figure 1) outputs an OAM address value to the data bus in accordance with the program incorporated in the program data memory unit 14 (Figure 1), and outputs a port address corresponding to the OAM address circuit 58 into the address bus. The address decoder 24 (Figure 1), receiving the port address, outputs a latch signal OBJAD to the OAM address circuit 58. The OAM address circuit 58 latches the address value of the OAM 56 outputted from the CPU 10 at that time in response to the signal OBJAD. Thereafter, the CPU 10 outputs the object data indicating a kind and position of the moving picture (object) and the priority data indicating the priority of the object to the data bus, and outputs a port address corresponding to the OAM 56 into the address bus. Consequently, the signal OBJDT is outputted from the address decoder 24, and in response to the signal OBJDT, the object data and the priority data (attribute data) from the CPU 10 are written into an address designated by the OAM address circuit 58 of the OAM 56. The OAM address circuit 58 receives the signal HB from the timing signal generator 30 and becomes an in-range detection mode and, in the in-range detection mode, the OAM address circuit 58 sequentially applies addresses from "0" to "maximum object number minus 1" to the OAM 56. The OAM 56 receives the addresses in sequence from the OAM address circuit 58, and applies the V position data and the H position data included in the object data (Figure 6) to an in-range detection circuit 60. In the in-range detection circuit 60, based on the V position data from the timing signal generator 30, determination is effected as to whether or not the object is an object to be displayed in a next scanning line. Regarding only the object to be displayed, the in-range detection signal is applied to the OAM address circuit 58. The OAM address circuit 58, receiving the in-range detection signal from the in-range detection circuit 60, writes addresses of the OAM 56 storing the object data at the in-range state into an internal memory (not shown). At the V blanking period, the OAM address circuit 58 becomes a buffer write mode in response to the signal HB from the timing signal generator 30. In this mode, addresses of the object data of the objects decided being at the in-range state by the in-range detection circuit 60 are applied in sequence to the OAM 56. On receiving the address from the AM address circuit 58, the OAM 56 outputs the name data and the position data among the object data as shown in Figure 6 to a character data address arithmetic circuit 62, and applies the position data to a line buffer address circuit 64 and also applies the priority data to a priority data register 66. The priority data register 66, receiving a signal PRLD from the timing signal generator 30, latches the priority data. The character data address arithmetic circuit 62 calculates an address value of the character data area 16b in the video data memory unit 16 (Figure 1) based on the name data and the position data of the object as well as the V position data from the timing signal generator 30. The address value is applied to an address changing circuit 68. The address changing circuit 68 supplies the address value outputted from the character data address arithmetic circuit 62 to the character data area 16b in response to the signal OBJEN from the timing signal generator 30. Consequently, from the character data area 16b, graphic data (dot data) of the character are outputted and applied to a dot data register 70. The dot data register 70 latches the dot data of the object outputted from the character data area 16b in response to the signal DDLD from the timing signal generator 30. A P/S converter 72 loads the dot data of the dot data register 70 in response to the signal PSLD from the timing signal generator 30. The line buffer address circuit 64 is set to a line buffer write mode in response to the signal HB from the timing signal generator 30. In this mode, the line buffer address circuit 64 calculates an address value of the line buffer 74 based on the position data included in the object data inputted from the OAM 56. The line buffer 74, receiving the address from the line buffer address circuit 64, stores the dot data from the P/S converter 72 and the priority data from the priority data register 66. After the line buffer 74 stores the dot data of one dot, the P/S converter 72 shifts the dot data in response to the signal PSSH from the timing signal generator 30, and applies the picture data in one dot unit to the line buffer 74. Also the line buffer address circuit 64 increments the address value in synchronization with data shifting in the P/S converter 72. At the horizontal scanning period, the line buffer address circuit 64 is set to a tine buffer read mode in response to the signal HB from the timing signal generator 30. In this mode, the tine buffer address circuit 64 sequentially supplies the address values from "0" to "maximum dot number in horizontal direction minus "1" to the line buffer 74. Accordingly, from the line buffer 74, the object dot data and the priority data are outputted in sequence to be applied to a subsequent composite circuit 76 (Figure 1). Thus, the dot data and the priority data per each character of the background picture are outputted from the background picture data generator 32, and the dot data and the priority data of the object character are outputted from the moving picture data generator 34. These data are applied to the composite circuit 76 shown in Figure 1. That is, respective dot data are applied to a transparency detecting circuit 78 and a picture data selecting circuit 80, and the priority data are applied to a picture data control circuit 82. The signals M0-M3 and BG3TOP from the CPU interface are supplied to the picture data control circuit 82. The transparency detecting circuit 78 includes five OR gates 84, 86, 88, 90 and 92 as shown in Figure 7. Inverted dot data of a first background picture cell BG1 from the P/S converter 52 (Figure 3) of the background picture data generator 32 are inputted to the OR gate 84, inverted dot-data of a second background picture cell BG2 are inputted to the OR gate 86, inverted dot data of the third background picture cell BG3 are inputted to the OR gate 88, and inverted dot data of a fourth background picture cell BG4 are inputted to the OR gate 90. The dot data of these background picture cells BG1-BG4 are 2-8 bits. On the other hand, inverted dot data of the object being four(4) bits are applied to the OR gate 92. From the OR gates 84, 86, 88, 90 and 92, when any of each input is "0", decision is effected that each character is transparent, and signals /BG1CLR, /BG2CLR, /BG3CLR, /BG4CLR and /OBJCLR to make the priority data ineffective are outputted to be supplied to the picture data control circuit 82 (Figure 1 and Figure 8). The signal /BG1CLR from the transparency detecting circuit 78 is supplied to respective one inputs of NAND gates 94 and 96 of the picture data control circuit 82 shown in Figure 8. Priority data BG1PRI and its inversion of the first background picture cell are applied to respective other inputs of the NAND gates 94 and 96. Also the signal /BG2CLR from the transparency detecting circuit 78 is inputted to one inputs of NAND gates 98 and 100, and the priority data BG2PRI and its inversion of the second background picture cell are applied to other inputs of the NAND gates 98 and 100. The signal /BG3CLR from the transparency detecting circuit 78 is supplied to one inputs of NAND gates 102 and 104, and the priority data BG3PRI and its inversion of the third background picture cell are applied to other inputs of the NAND gates 102 and 104. The signal /BG4CLR is supplied to one inputs of NAND gates 106 and 108, and the priority data BG4PRI and its inversion of the fourth background picture cell are applied to other inputs of the NAND gates 106 and 108. Furthermore, the signal /OBJCLR from the transparency detecting circuit is supplied to respective one inputs of four NAND gates 110, 112, 114 and 116. Priority data OBJPRI (two bits) included in the object data are applied to a decoder 118. The decoder 118 decodes the priority data OBJPRI of two(2) bits and outputs signals indicating the four states, and the signals are supplied to other inputs of the NAND gates 110, 112, 114 and 116, respectively. Inverted signals of the signals M0 and M1 from the mode decoder 28 (Figure 1) are supplied to two inputs of a OR gate 120, and the signal M1 is supplied to one input of an OR gate 122. Inversion of the signal BG3TOP is supplied to one input of the OR gate 122, and inversion of output of the NAND gate 102 is further supplied to one input of the OR gate 122. Respective inverted outputs of NAND gates 112, 114 and 116 are supplied to respective one inputs of OR gates 124, 126 and 128, and inverted output of the OR gate 120 is supplied to respective other inputs of these OR gates 124 - 128. A priority encoder 130 selects one having the highest priority among pictures where priority data are effective, and applies its number to a subsequent decoder 132. The priority encoder 130 has 16 inputs P0 - P15. The input P0 is grounded. The inputs P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12, P13, P14 and P15 are supplied with outputs of the NAND gates 108, 104, 116, 106, 102, 114 and 100, the OR gate 128, the NAND gates 96 and 112, the OR gate 126, the NAND gate 98, the OR gates 124 and the NAND gates 94 and 110, respectively. Thus, respective priority data are decoded by respective NAND gates and become a plurality of picture output signals, but only one picture output signal shown by the priority data is effective. Since the priority data exist per each screen (still picture cell and object), effective picture output signals exist by the screen number. On the other hand, all the picture output signals of the screen having the transparent picture data are made ineffective by the clear signals from the transparent detecting circuit 78, and only the picture output signals of the screen having the dot data being not transparent are made effective. Respective picture output signals are inputted to NAND gates together with the mode signals, and are further made effective or ineffective by values of the mode signals M0 and M1 to be inputted to the priority encoder 130. Consequently, signals being made effective by the priority encoder 130 are (a) the priority data of the background picture and the moving picture in the number set by the mode at that time, (b) the picture output signals generated respectively by selecting only one screen position among a plurality of picture positions peculiar to each screen (cell) by value of the priority data, (c) the picture output signals of the screen where the picture data are not transparent, and (d) the picture output signals made effective by setting the basic priority by the mode data. Thus, the priority encoder 130 selects one having the highest priority among the effective picture output signals. Signals outputted from the priority encoder 130 are supplied to the decoder 132 which decodes the number from the priority encoder, and only one picture output signal shown by the number is made effective among all picture output signals. Only one picture output signals being made effective is latched to a data latch 144 by AND gates 134 - 140 as a dot data output selection signal that shows which dot data should be outputted. Consequently, from the data latch 144, dot data output selection signals /OBJSEL, /BG1SEL, /BG2SEL, /BG3SEL and /BG4SEL are outputted. Since the priority data input terminal P0 of the priority encoder 130 is always supplied with an output signal of the background color data, when all the picture output signals are made ineffective, the background color data selection signal /BACK is outputted. The selection signal is supplied to the picture data selecting circuit 80 (Figure 1 and Figure 9 ) . The picture data selecting circuit 80 with its detail shown in Figure 9 includes six tri-state buffers 146 - 156 and further has a background color data generator 158. BG1 dot data from the background picture data generator 32 is inputted to the tri-state buffer 146, and the signal /BG1SEL from the picture data control circuit 82 is applied as its control input. Also the tri-state buffers 148, 150, 152 and 154 are respectively supplied with BG2 dot data and the signal /BG2SEL, BG3 dot data and the signal /BG3SEL, BG4 dot data and the signal /BG4SEL as well as OBJ dot data and the signal /OBJSEL. The tri-state buffer 156 is supplied with an output from the background color data generator 158, and its control input is supplied with the background color selection signal /BACK. Consequently, the picture data selecting circuit 80 selects the dot data corresponding to only one picture output signal made effective by the picture data control signal 82 or the background color data, and supplies the selected data as color data to a subsequent video signal generator 160. In addition, the picture data selecting circuit 80 may be modified as shown in Figure 10. In Figure 10, an output of each of the tri-state buffers 146 - 154 and the background color selection signal /BACK are supplied to an AND gate of the background data generator 158. Consequently, only when the background color selection signal /BACK is at a low level, dot data outputted from any of the tri-state buffers 146 - 154 are selected. Thus, the color data outputted from the picture data selecting circuit 80 are supplied to the video signal generator 160 shown in Figure 1. The video signal generator 160 includes a color RAM 162 and a D/A converter 164. The color RAM 162 is a color table to derive color data using the dot data as address, and the color table is first written by the CPU 10. Consequently, a color signal selected in accordance with the color data from the picture data selecting circuit 80 is supplied to the D/A converter, and the color data is converted into a voltage level to be supplied to the TV interface 18. Thus, the priority is applied per each character, and based on this, the priority is determined so that the picture data having the highest priority per each character unit is displayed on the monitor 20 (Figure 1). This will be described in detail referring to FIGs. 11A - 11D. Figure 11A shows a case of mode 0 specified by the signal M0 from the mode decoder 28 (Figure 1). In this case, the first, second, third and fourth background picture cells BG1, BG2, BG3 and BG4 are all used. When the priority data PRI of the background pattern data (Figure 3) of each background picture cell are all set to "0" in the characters of the background picture cells expressed by the name codes, as shown by a dotted line in Figure 11A, the background picture cells BG1, BG2, BG3 and BG4 are displayed from the front side of the monitor screen towards the back side in this order, and the background color is displayed at the most back side of the monitor screen by the background color data prepared in Figure 9 or Figure 10. When the priority data of the characters of the second background picture cell BG2 is set to "1" and the priority data of other background picture cells BG1 BG3 and BG4 are set to "0", the characters of the second background picture cell BG2 is displayed at the front side of the monitor screen with respect to the first background picture cell BG1 as shown by a solid line in Figure 11A. That is, in this case, the character of the second background picture cell BG2 is displayed with priority. Also when the priority data of the characters of the fourth background picture cell BG4 are only set to "1", the character of the fourth background picture cell BG4 are displayed at the front side with respect to the characters of the third background picture cell BG3 as shown by a solid line in Figure 11A. In the mode 0, the signal /BG3TOP to display the third background picture cell BG3 at the nearest side of the monitor screen is ineffective. Regarding the object, when the priority data PRI included in the object data (attribute data) shown in Figure 6 is set to "11", irrespective of the priority data of the background pattern data, the object character is displayed at the front side of the monitor screen with respect to all background picture cells. When the priority data of the object data is set to "10", the object is displayed at the nearest side of the monitor screen if the priority data of any of the first background picture cell BG1 and the second background picture cell BG2 are set to "0". When the priority data included in the object data is set to "01", the object is displayed at the rear side with respect to the second background picture cell BG2 having the priority data being set to "0". When the priority data included in the object data is set to "00", the object is disptayed at the front side with respect to the characters of the third background picture cell BG3 if the priority data of the third background picture cell BG3 are set to "0". The mode 1 shown in Figure 11B is specified by the signal M1 from the mode decoder 2B (Figure 1). In this case, the fourth background picture cell BG4 is not used although it is used in Figure 11A, and the signal BG3TOP to display the third background picture cell at the nearest side of the monitor screen is made effective. Consequently, when the signal BG3TOP is set from the CPU 10 to the mode register 26 (Figure 1), the third background picture cell BG3 is displayed at the nearest side of the monitor screen as shown by a solid line in Figure 11B. However, when the signal BG3TOP is set to "0", the character of the third background picture cell BG3 is displayed at the most back side of the monitor screen, irrespective of the priority data PRI. The third background cell BG3 is set, for example, as the screen with little color number such as numeric characters. When the signal BG3TOP to display the third background picture cell BG3 at the nearest side is set, the third background picture cell as a whole is displayed at the nearest side. When the priority data PRI (Figure 4) of the background pattern data of any of the first, second and third background picture cells is set to "0" and the signal BG3TOP is set to "0", as shown in Figure 11B, the first, second and third background picture cells BG1, BG2 and BG3 are displayed from the front side of the monitor screen in this order. If the priority data of the second background picture cell is set to "1", in similar manner to Figure 11A, the character of the second background picture cell BG2 is displayed at the front side with respect to the first background picture cell BG1. The object is as described in Figure 11A. Referring to Figure 11C, the mode 2 is specified by the signal M2 from the mode register 28 (Figure 1), and only the first and second background picture cells BG1 and BG2 are used. Consequently, in the mode 2, the third and fourth background picture cells BG3 and BG4 as well as the signal BG3TOP are ineffective. When the priority data of any of the first and second background picture cells BG1 and BG2 is set to "0", as shown in Figure 11C, the characters of the the first background picture cell BG1 and the second background picture cell BG2 are displayed from the front side of the monitor screen in this order. When the priority data of the second background picture cell BG2 is set to "1", the character of the second background picture cell BG2 is displayed at the front side with respect to the first background picture celt BG1. Regarding the object, when the priority data included in the object data is "11", the object is displayed at the front side with respect to the character of the first background picture cell BG1 having the priority data being "1". When the priority data of the object data is set to "10", the object is displayed at the back side with respect to the character of the first background picture cell BG1 having the priority data being "1" and at the front side with respect to the character of the second background picture cell BG2 having the priority data being set to "1". When the priority data of the object data is set to "01", the object is set between the second background cell BG2 having the priority data being "1" and the first background cell BG1 having the priority data being "0". When the priority data of the object data is set to "00", the object is displayed between the first and second background picture cells BG1 and BG2, both having the priority data being set to "0". The mode 3 shown in Figure 11D is specified by the signal M3 from the mode register 28 (Figure 1), and only the first background picture cell BG1 is used in the mode 3. Consequently, the second - fourth background picture cells BG2 - BG4 as well as the signal BG3TOP are ineffective. In the mode 3, when the priority data of the object data is set to "11", the object is displayed at the front side with respect to the first background picture cell BG1 having the priority data being set to "1". However, when the priority data of the object data is set to "10" or "01", the object is displayed at the back side with respect to the characters of the first background picture cell BG1 having the priority data being set to "1". However, when the priority data of the first background picture cell BG1 is set to "0", the object having the priority data being set to "10" or "01" is displayed at the front side. The object having the priority data being set to "00" is displayed at the most back side of the monitor screen. In addition, a memory cartridge incorporating a semiconductor memory is used as an external storage unit in the above described embodiments; however, it is possible to use an external storage unit such as a CD-ROM in the present invention. In a case of use of the memory cartridge, the program data including the character data, color data, priority data, mode data and etc. that are described previously is stored in the semiconductor memory, and the CPU 10 generates control data for the moving picture characters and the still (background) picture characters on the basis of the program data read from the semiconductor memory and outputs the same to the video processor 12. In contrast, in a case of use of the CD-ROM, the above described program data is optically recorded as digital data in the CD-ROM (not shown). In addition, an optical reader for optically reading recorded date on the CD-ROM is connected to a suitable connector such as a expansion connector. When the CD-ROM is used as the external storage unit, a memory cartridge is also used. In this case, the memory cartridge is comprised with a ROM (not shown) that stores a starting program for controlling an operation of the optical reader, a buffer RAM (not shown) for temporarily storing the program data read from the CD-ROM, and etc. Then, prior to a start of a display operation, the CPU 10 applies control data to the optical reader on the basis of the starting program of the ROM to cause the optical reader read the recorded data of the CD-ROM. A portion of the character data read from the CD-ROM is transferred to the character RAM and the program data is transferred to the buffer RAM included in the memory cartridge. The CPU 10 controls the video processor 12 on the basis of the program data stored in the buffer RAM. That is, after the data read from the CD-ROM by the optical reader has been transferred to the respective memories, the CPU 10 and the video processor 12 execute the display operation by accessing the respective memories as done in the previous embodiments. Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only.

Claims: A video display apparatus (18,20) comprising: still picture video data generating means (32) for generating video data of still picture characters to be displayed, characterised by said video apparatus being arranged to display a plurality of still picture cells in an overlaid state, each cell comprising a plurality of still picture characters, by first priority data applying means (46) arranged to apply first priority data to said video data of the still picture characters; by selecting means (130) arranged to determine priority based on said first priority data applied to each still picture character input thereto and arranged to output selectively the video data of one still picture character of a still picture having highest priority amongst the respective characters of said plurality of overlaid still picture cells; and by display means (20) arranged to display the still picture character output by said selecting means. A video display apparatus (18,20) according to claim 1, further comprising mode signal generating means (26,28) for generating a mode signal to designate a number of the plurality of still picture cells which can be overlaid, said still picture video data generating means (32) being arranged to generate video data of the still picture characters of the still picture cells designated by the mode signal, wherein said selecting means (130) is arranged to select the video data of one still picture character having highest priority amongst the still picture characters of the picture cells which can be overlaid in the designated mode based on the mode signal and the first priority data. A video display apparatus according to claim 1 or claim 2, further comprising transparency detecting means (78) arranged to detect whether or not each still picture character is a transparent picture based on the video data output from said still picture video data generating means, wherein said selecting means (130) is arranged to determine the priority except when the video data of the detected still picture character detected is found to be transparent by said transparency detecting means. A video display apparatus (18,20) according to claim 3, wherein said selecting means (130) is provided with means arranged to generate specific video data when it is detected by said transparency detecting means (78) that all of said still picture characters are transparent. A video display apparatus (18,20) according to claim 1, further comprising: moving picture video data generating means (34) for generating video data of a moving character; and second priority data applying means (66) for applying second priority data to the video data of the moving picture character from said moving picture video data generating means, wherein said selecting means (130) is arranged to output selectively the video data of said one still picture character or the picture data of said moving picture character based on the first priority data and the second priority data. A video display apparatus (18,20) according to claim 5, further comprising mode signal generating means (26) for generating a mode signal to designate a number of the plurality of still picture cells which can be overlaid, said still picture video data generating means (32) generating video data of the still picture characters associated with the still picture cells designated by the mode signal, wherein said selecting means (130) selects the video data of the still picture character of one still picture character having the highest priority amongst the still picture characters of the picture cells which can be overlaid in the designated mode or the video data of the moving picture character based on the mode signal and the first priority data as well as the second priority data. A video display apparatus according to any of claims 1 to 6 in combination with an external storage unit comprising: still picture character code storing (16b) means for storing a still picture character code that designates a still picture character to be displayed, said still picture character video data generator of said video display apparatus generating the video data on the basis of the still picture character code; and priority data storing means (16a) for storing first priority data that designates priority of each still picture character; wherein said selecting means (130) of said video display apparatus for determines the priority of each still picture character on the basis of the first priority data and selectively outputs the video data of one still picture character having highest priority amongst the respective characters of said plurality of overlaid still picture cells. A combination according to claim 7, further comprising mode data storing means (26) arranged to store mode data that designates a number of said plurality of still picture cells which can be overlaid said still picture video data generator (32) being arranged to generate the video data of the still picture characters of the still picture cells designated by said mode data. A combination according to claim 7 or claim 8, further comprising: moving picture character code storing means (16b) arranged to store a moving picture character code that designates a moving picture character to be displayed; and second priority data storing means (66) arranged to store second priority data that designates priority of the moving picture character, wherein said video display apparatus includes moving picture video data generator for generating video data of the moving character using said moving picture character code, and said selecting means (30) of said video display apparatus selectively outputs the video data of said one still picture character or the video data of said moving picture character based on the first priority data and the second priority data.

Inventors: KITAGAWA KUMIKO, NISHIUMI SATOSHI, OTAKE MASAHIRO, TAKAHASHI TOYOFUMI, KITAGAWA, KUMIKO, NISHIUMI, SATOSHI, OTAKE, MASAHIRO, TAKAHASHI, TOYOFUMI, Kitagawa, Kumiko, c/o Ricoh Co., Ltd., Nishiumi, Satoshi, c/o Nintendo Co. Ltd., OTAKE, MASAHIRO, C/O NINTENDO CO., LTD., TAKAHASHI, TOYOFUMI, C/O RICOH CO., LTD.
Applicants: NINTENDO CO LTD, RICOH KK, NINTENDO CO. LIMITED, RICOH COMPANY, LTD
Application year: 1991
Main classification: H04N5
IPC codes: G09G5, A63F13, H04N5, G06T15