Fault analysis apparatus for memories having redundancy circuits

Abstract: An apparatus for analyzing faults in a memory having a redundancy circuit, comprises an algorithmic pattern generator (2) that generates address signals that select a memory cell of a memory under test (50) and that has a redundancy circuit and that generates data that is written to a selected memory cell; a comparison circuit (4) for performing read after data which has been written to a selected memory cell by address signals and then compares the read data and the data from the algorithmic pattern generator (2) for whether or not it is in agreement and if it is not in agreement generates a fault signal that indicates that that the memory cell is faulty; a fault analysis memory (8) having a plural number of memory cells; and an address allocation circuit (6) that receives address signals from the algorithmic pattern generator (2) and performs address allocation for the fault analysis memory (8) so that a plural number of memory cells of the memory under test (MUT) (50) correspond on the basis of a predetermined rule to a single memory cell of the fault analysis memory (8).

Description: BACKGROUND OF THE INVENTION The present invention relates to a memory fault analysis apparatus for analyzing whether or not an analyzed memory having a redundancy circuit is faulty or not, and whether replacement with a redundancy circuit is possible. In general, a memory fault analysis apparatus performs individual fault analysis is performed for the memory cells of a memory that has redundancy circuits and which is being analyzed, and when there is a faulty memory cell, a judgment is made for whether or not that fault can be saved by a redundancy circuit. FIG. 1 shows a conventional memory fault analysis apparatus. This memory fault analysis apparatus is provided with an algorithmic pattern generator (hereinafter termed an ALPG) 2, a comparator 4, and a fault analysis memory (hereinafter termed a FAM) 8. First, address signals and data signals for testing are sent from the ALPG 2 to a memory under test (MUT) 50 that is a memory having a redundancy circuit, and read is performed after data has been written to memory cells of the MUT 50 and in accordance with these address signals. Then, the written data and the read data are compared by the comparator 4 and fault signals are sent to the FAM 8 if the two are different. This FAM 8 has a memory area that is the same size as the memory cell array of the MUT 50, and each of the memory cells of the FAM 8 are allocated the same address as a memory cell that corresponds to the MUT 50. Then, when a fault signals is sent from the comparator 4, the data "1" is written to the corresponding memory element of the FAM 8 . More specifically, as shown in FIG. 2 (a) for example, when there is a fault in a memory cell having the row address is X 4 and the column address is Y 0 of the MUT 50, then as shown in FIG. 2 (b), the data "1" is written in the row address is X 4 and the column address is Y 0 of the corresponding memory cell. In the following, the address of a memory cell having the row address X and the column address Y is simply expressed as (X, Y). In the same manner, when there is a fault in memory cells that have the addresses (X 1 , Y 1 ) and (X 3 , Y 3 ) in the MUT 50, there is the data "1" written in the memory cells of the FAM 8 that have the addresses (X 1 , Y 1 ) and (X 3 , Y 3 ). Moreover, the memory cells of the FAM 8 are initialized so as to store the data "0" prior to the performance of analysis processing. In this manner, the address signals and the data signals from the ALPG 2 are used as the basis for analyzing whether or not each of the memory cells in the MUT 50 has a fault, and for writing "1" to corresponding memory cells in the FAM 8 where there is a fault. The data that is written to this FAM 8 is used as the basis for a judgement apparatus not shown in the figure, to judge whether or not the MUT 50 can be saved by a redundancy circuit. In a conventional memory fault analysis apparatus such as described above, it is necessary to have a FAM 8 that has a large-capacity measurement memory of the same size as the MUT 50 and so it is necessary to have a FAM 8 having an extremely large memory when there is the analysis of large-scale memories and when there is the simultaneous analysis of a plural number of memories. For example, if sixteen memories each having a storage capacity of 4 Mbits for example are to be analyzed, then it is necessary to have a FAM that has a minimum capacity of 64 Mbits. Then, when the capacity of the FAM 8 becomes larger, there is the problem of a large increase in the judgement time for whether or not rescue is possible by a redundancy circuit. In C. Evans, Testing Repairable RAMs and Mostly Good Memories, in IEEE Test Conference 1981, a method is described where in a row and/or column redundancy scheme a memory failure map is stored in a reduced version by mapping entire columns and rows, respectively, onto an address tracking RAM . A method to repair a semiconductor memory device is described in the US-A- 4627053. The test result of a memory test is stored in a memory failure map. For the repair process defective bits are counted in rows and columns and a reduced defective bit matrix is generated. However, first a time consuming recording of the device failure pattern in the memory failure map is performed. The EP-A- 0125 633 describes to reduce the time needed for the memory testing by storing during testing only data necessary for a repair judgment. In this scheme, the locations of defective bits are stored in a compressed data matrix. Repair judgment is performed using each defective bit stored in the compressed data matrix. SUMMARY OF THE INVENTION In the light of the problems associated with the conventional apparatus, the present invention has as an object the provision of a memory fault analysis apparatus that can reduce the memory capacity of the FAM, and that can also reduce the time for judging whether or not rescue is possible. The memory fault analysis apparatus of the present invention is provided with the features according to claim 1. In the memory fault analysis apparatus of the present invention and having the configuration described in claim 1, the address allocation means performs address allocation, that is, address compression for the fault analysis memory so that a plural number of memory cells of the MUT correspond on the basis of a predetermined rule to one of the memory cells of the fault analysis memory, when at least one memory cell of said plural number of memory cells is faulty, there is the write of fault information to the memory cell corresponding to the fault analysis memory. By performing address compression, it the size of the area necessary for the FAM becomes smaller than that required in the conventional apparatus and by this it is possible to reduce the judgment time for fault rescue. According to the present invention as has been described above, performing address compression by the fault analysis memory enables the capacity of the FAM to be reduced and also enables the time required to judge fault rescue to be shortened. BRIEF DESCRIPTION OF THE DRAWINGS In the appended figures, FIG. 1 is a block diagram indicating the configuration of a conventional memory fault analysis apparatus; FIG. 2 is a view describing the operation of a conventional memory fault analysis apparatus; FIG. 3 is a block diagram showing the configuration of a first embodiment of a memory fault analysis apparatus according to the present invention; FIG. 4 is a view for describing the write of fault information to a fault analysis memory (FAM) of the present invention; FIG. 5 is a view describing address allocation in the present invention; FIG. 6 is a view describing the configuration of a memory under test (MUT) being analyzed by the present invention; FIG. 7 is a block diagram showing the configuration of a second embodiment of a memory fault analysis apparatus according to the present invention; FIG. 8 is a view describing the operation of a second embodiment of a memory fault analysis apparatus according to the present invention; and FIG. 9 is a view describing the operation of a third embodiment of a memory fault analysis apparatus according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 is a block diagram showing the configuration of a first embodiment of a memory fault analysis apparatus according to the present invention. The memory fault analysis apparatus of this embodiment is the conventional memory fault analysis apparatus shown in FIG. 1, to which an address allocation apparatus 6 has been newly provided. This address allocation apparatus 6 receives address signals from the ALPG 2 and performs address allocation with respect to the FAM 8. This address allocation is performed on the basis of the number of rows and columns that are switched when one faulty row or one faulty column of the MUT 50 is switched for one redundant cell row or one redundant cell column. This is shown in FIG. 5 and FIG. 6. FIG. 6 shows the MUT 50 and this MUT 50 has a memory cell array 51, a row redundancy circuit 52 and a column redundancy circuit 53. When the cell line of the memory cell array 51 for which the row address is 2X and the column address is 2Y is faulty and the cell row for which the row address is 2X is replaced with the redundancy cell row 52a of the row redundancy circuit 52, the cell row for which the row address is 2X+1 is also replaced at the same time with the other redundancy cell row 52b of the row redundancy circuit 52, and when the cell column for which the column address is 2Y is replaced with the redundancy cell column 53a of the column redundancy circuit 53, the cell column for which the column address is 2Y+1 is also replaced at the same time with the other redundancy cell column 53b of the column redundancy circuit 53, then the number of rows and columns that are replaced at the same time is two each. FIG. 5 shows the address allocation of the FAM 8 for this case. The two continuous cell rows X 2i , X 2i+1 (i = 0, 1, ...) of the memory cell array 51 of the MUT 50 are allocated addresses so as to correspond to cell rows Xi of the FAM 8 and the two continuous cell rows Y 2i , Y 2i+1 (i = 0, 1, ...) of the memory cell array 51 of the MUT 50 are allocated addresses so as to correspond to cell rows Yi of the FAM 8. More specifically, as shown in FIG. 5 for example, each memory cell for which the address of the cell array 51 is (X 4 , Y 2 ), (X 4 , Y 3 ), (X 5 , Y 2 ) and (X 5 , Y 3 ) is allocated so as to correspond with the memory cell of the FAM 8 for which the address is (X 2 , Y 1 ). Accordingly, it is possible to have address compression. When the address of the cell row Y or the cell row X of the memory cell array 51 of the MUT 50 is expressed in binary notation as A n A n-1 ... A 1 A 0 (A i (i = 0, ... n) where A is either 0 or 1), then with the lowest order ignored, the binary A n A n-1 ... A 1 can be obtained as the address corresponding with the cell row or cell column of the FAM 8. The following is a description of fault analysis performed using a FAM 8 for which address allocation such as this has been performed, with reference to FIG. 4. Now, as shown in FIG. 4, the memory cell array 51 of the MUT 50 is faulty at addresses (X 1 , Y 1 ), (X 4 , Y 1 ), (X 5 , Y 1 ), (X 0 , Y 4 ), (X 0 , Y 5 ) and (X 1 , Y 5 ). When this occurs, the memory cell with the address of (X 0 , Y 0 ) is faulty and so even if the memory cells of the memory cell array 51 and having addresses (X 0 , Y 0 ), (X 1 , Y 0 ) and (X 0 , Y 1 ) are not faulty, the data "1" will be written to the FAM 8. Then the addresses (X 0 , Y 4 ), (X 1 , Y 4 ), (X 0 , Y 5 ) and (X 1 ,Y 5 ) are faulty and so the data "1" is written to the memory cell which has the corresponding address in the FAM 8. After fault analysis has been performed in this manner, the data that is written to the FAM 8 is used as the basis for the judgment apparatus (not indicated in the figure) to judge whether or not the MUT 50 can be rescued. For example, when the data that is written to the FAM 8 is as shown in FIG. 4 (b), the number of row redundancy circuits and column redundancy circuits necessary for rescue are one each and so rescue is possible. According to the first embodiment as described above, the size of the necessary area of the FAM 8 becomes approximately one quarter that conventionally required. And the judgment time for fault rescues to be reduced by scanning small area. Moreover, in the first embodiment described above, the description was given for when there were two rows and two columns for replacement at the same time but when the number of rows and the number of columns for replacement at the same time are each m (≥ 1) and n (≥ 1) (with the exception of where m = n =1), then it is possible to have address allocation in the same manner, and the size of the necessary area of the FAM 8 becomes 1/(m×n) that conventionally required. FIG. 7 shows the configuration of a second embodiment of the memory fault analysis apparatus according to the second embodiment. The memory fault analysis apparatus of this second embodiment is the memory fault analysis apparatus of the first embodiment and shown in FIG. 3, and which is newly provided with a fault analysis memory (FAM) 10. This FAM 10 has a memory area of the same size as the MUT 50 which is being analyzed, and when there is a fault in the memory cell having the address (X, Y) of the memory cell array 51 of the MUT 50, the fault signals from the comparator 4 are used as the basis to write the data "1" to the memory cell that has the address (X, Y) and corresponding to the memory array of the FAM 10. More specifically, as shown in FIG. 8(a), when there are faults in memory cells of the memory cell array 51 of the MUT 50 and having the addresses of (X 2 , Y 1 ), (X 2 , Y 2 ), (X 4 , Y 4 ), (X 4 , Y 5 ), (X 5 , Y 4 ) and , (X 5 , Y 5 ), then the data "1" is written to the corresponding memory array of the FAM 10 and having the addresses of (X 2 , Y 1 ), (X 2 , Y 2 ), (X 4 , Y 4 ), (X 4 , Y 5 ), (X 5 , Y 4 ) and, (X 5 , Y 5 ). Moreover, the FAM 10 performs address compression at this time and the data "1" is written to the memory cells that have the addresses (X 1 , Y 0 ), (X 1 , Y 1 ) and (X 2 , Y 2 ). In this second embodiment, the FAM 8 that has the fault information that has undergone address compression is used for judgment as to whether or not rescue is possible using the redundancy circuits, and the FAM 10 that has the fault information that has not undergone address compression is used in the output of the field map and the like for fault analysis. Needless to say, the second embodiment can obtain the same effect as the first embodiment. FIG. 9 shows a configuration of a third embodiment of a memory fault analysis apparatus according to the present invention. The memory fault analysis apparatus of this third embodiment is for the simultaneous analysis of a plural number (four, in this embodiment) of MUT 50 1 , 50 2 , 50 3 and 50 4 , and is provided with an ALPG 2, comparators 4 1 , 4 2 , 4 3 and 4 4 , an address allocation apparatus 6, a FAM 8, a data selector 9 and a FAM 10. The FAM 8 performs address allocation (address compression) by the address allocation apparatus 6 but the FAM 10 does not perform address compression. When a memory cell of the MUT 50 1 (i = 1, ... 4) is faulty, the comparator 4 1 generates fault signals and the fault information (the data "1") is written to the corresponding memory cell of the divided area of the FAM 8. On the other hand, of the four MUT (50 1 , 50 2 , 50 3 , 50 4 ) the fault information is written to the FAM 10 for the one MUT 50i that was selected by the data selector 9. This is performed when it is not necessary to have the original fault address since original fault addresses are not known when there is fault analysis by field mapping. Needless to say, the third embodiment can obtain the same effect as the first embodiment, and it is possible to have simultaneous fault analysis for a plural number of memories under test. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: An apparatus for analyzing faults in a memory having a redundancy circuit, comprising: an algorithmic pattern generator (2) for generating address signals that select a memory cell of a memory under test (50) having a redundancy circuit and for generating data that is written to a selected memory cell of the memory under test (50); comparison means (4) for performing a data read operation on a selected cell of the memory under test (50) after data has been written to a memory cell selected by said address signals and then for comparing said read data and said data from said algorithmic pattern generator (2) for whether or not it is in agreement and if it is not in agreement generates a fault signal that indicates that the memory cell is faulty; and a fault analysis memory (8) having a plural number of memory cells; and said apparatus for analyzing faults being characterized by further comprising: address allocation means (6) for receiving address signals from said algorithmic pattern generator (2) and performing address allocation for said fault analysis memory (8) so that a block of a plural number of memory cells of said memory under test (50) corresponds on the basis of a predetermined rule to a single memory cell of said fault analysis memory (8), the dimensions of one block being at least two cells in the column direction and at least two cells in the row direction; and means for writing a fault information in a single memory cell of said fault analysis memory (8) if a fault signal has been generated for at least one of said corresponding plural number of memory cells. The memory fault analysis apparatus of claim 1, wherein: said fault analysis memory (8) is adapted to write said fault information to a memory cell corresponding to a memory cell that is faulty, when fault signals are sent from said comparison means (4) indicating a fault in said memory cell in said memory under test (50). The memory fault analysis apparatus of claim 2, further comprising : a second fault analysis memory (10), having a memory area of the same size as said memory under test (50), wherein said second fault analysis memory (10) is adapted to write data to a memory cell on the basis of said fault signals output from said comparison means when said memory under test (50) is faulty. The memory fault analysis apparatus of claim 2, wherein: said memory under test (50) is provided in a plural number, and said fault analysis apparatus performs simultaneous analysis of said plural number of memories under test (50 1 , 50 2 , 50 3 , 50 4 ). The memory fault analysis apparatus of claim 4, further comprising: a second fault analysis memory (10), having a memory area of the same size as said memory under test (50), wherein said second fault analysis memory (10) is adapted to write data to a memory cell on the basis of said fault signals output from said comparison means when said memory under test (50) is faulty. The memory fault analysis apparatus of claim 5, wherein: said first fault analysis memory (8) is adapted to perform address allocation by said address allocation means (6) and said second fault analysis memory (10) is adapted to write fault information of one selected memory under test (50 1 -50 4 ) and does not perform address allocation.

Inventors: TSUKAKOSHI HISAO, TSUKAKOSHI, HISAO
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: G11C29
IPC codes: G11C29, G01R31