Digital chirp generator

Abstract: A digital chirp generator for generating linear frequency modulated signals, comprises a plurality of frequency/phase accumulators 10 pipelined together. Each frequency/phase accumulator includes a frequency accumulator driving phase accumulator. In the pipelined configuration the frequency accumulator and the phase accumulator of each frequency/phase accumulator are interconnected with the corresponding accumulator of the neighbouring frequency/phase accumulator.

Description: This invention relates to a digital chirp generator. Digital chirp generation is a well known technique for generating linear frequency modulated signals widely used in radar and sonar applications. A conventional form of digital chirp generator is illustrated in Figure 1 of the accompanying drawings. It comprises a frequency accumulator, a phase accumulator, sine/cosine look-up tables, and digital to analogue converters. The frequency and phase accumulators are n-bit accumulators. US-A-3,842,354 discloses a digital chirp generator comprising a frequency accumulator driving a phase accumulator. GB-A-2,224,899 discloses a digital data synthesiser for synthesising a periodic waveform which comprises a phase accumulator with pipeline register stages for producing a signal at a desired frequency. A need exists for a digital chirp generator which can be implemented using existing technology but which is capable of operating at higher speeds than conventional generators. Accordingly, in one aspect, this invention provides a digital chirp generator comprising a plurality of chirp generator nodes (otherwise referred to herein as frequency/phase accumulators), each said chirp generator node including frequency accumulator means driving a phase accumulator means, said plurality of chirp generator nodes being pipelined together so that the frequency accumulator means and the phase accumulator means in a given chirp generator node are interconnected with the corresponding accumulator means in the or each adjacent chirp generator node. It is to be understood that, whilst described as a digital chirp generator, the apparatus may be used simply as a frequency generator if the ramp rate input (otherwise referred to herein as the frequency increment value) of the chirp generator is set at zero. The frequency and phase accumulators referred to herein are typically digital accumulators which accumulate digital values representative of frequency or phase, as the case may be. In another aspect, this invention provides a digital chirp generator of the type defined above having means for loading the start frequency value and/or the start phase value into the associated frequency accumulator and/or phase accumulator. In a further aspect, this invention provides a digital chirp generator of the type described above having means for loading the frequency increment value into the chirp generator nodes without the need to provide an array of pipeline registers or similar to compensate for the pipeline delay in the chirp generator node array. In another aspect, the invention provides a digital chirp generator of the type described above having means for substantially simultaneously loading the frequency increment value and at least one of the frequency start value and phase start value into the chirp generator nodes using a single pipelined control signal, without the need for an array of pipeline registers to compensate for the pipeline delay in the chirp generator node array. The invention may be performed in various ways and five embodiments thereof will now be described by way of example only, reference being made to the accompanying drawings, in which:- Figure 1 is a block diagram of a conventional digital chirp generator; Figure 2 is a block diagram of a first embodiment of a parallel-pipelined digital chirp generator in accordance with the invention; Figure 3 is a block diagram of one of the p-bit frequency/phase accumulators defining a chirp generator node used in the chirp generator of Figure 2; Figure 4 is a block diagram of a second emobidment of a parallel-pipelined digital chirp generator in accordance with the invention; Figure 5 is a block diagram of a chirp generator node comprising a frequency/phase modulator modified to allow loading of the start frequency; Figure 6 is a block diagram of a third embodiment of a parallel-pipelined digital chirp generator in accordance with the invention and with pipelined control of the loading of the start frequency value; Figure 7 is a timing diagram which illustrates the pipelined loading of the start frequency in the third embodiment; Figure 8 is a block diagram of a chirp generator node comprising a frequency/phase accumulator including a frequency increment register, for use in the fourth and fifth embodiments of a digital chirp generator; Figure 9 is a block diagram of a fourth embodiment of a digital chirp generator with pipelined control of the loading of the frequency increment value in accordance with the invention and omitting the start frequency inputs and selectors for clarity; Figure 10 is a timing diagram which illustrates the pipelined loading of the frequency increment value; Figure 11 is a block diagram of a fifth embodiment of a parallel-pipelined digital chirp generator with simultaneous loading of the frequency increment and start frequency and/or start phase values, in accordance with the invention; and Figure 12 is a timing diagram which illustrates the pipelined loading of the frequency increment and start frequency values in the fifth embodiment. In each of the five embodiments, the conventional arrangement of Figure 1 which comprises an n-bit frequency accumulator and an n-bit phase accumulator is replaced by a pipelined array of smaller accumulator circuits each defining a chirp generator node. For example, if n-bit frequency and phase accumulators are required then the embodiments may be constructed as m pipelined chirp generator nodes each made up of a chirp generator node of p-bits, where n = m x p. A first embodiment of pipelined chirp generator node is shown in Figure 2. It comprises m, p-bit frequency/phase accumulators 10. A master clock signal is used to load intermediate results into all the pipeline registers simultaneously. Note that, for clarity, the loading of the start frequency parameter will be considered later. Consider first one of the p-bit frequency/phase accumulators (see Figure 3). It consists of a p-bit frequency accumulator 12 and a p-bit phase accumulator 14. The frequency accumulator is constructed from a p-bit full adder (frequency adder) 16 and a (p+1)-bit pipeline register (frequency register) 18. Similarly the phase accumulator is constructed from a p-bit adder (phase adder) 20 and a (p+1)-bit pipeline register (phase register) 22. The inputs to the frequency/phase accumulator comprise a pipelined carry input (FCIN[n]) and a p-bit frequency increment input (FIN[n]). These inputs are added to the current frequency (CF[n]) held in the frequency register 18 by the frequency adder 16. The result is a new p-bit frequency value (CF[n+1]) and a carry output (FCOUT[n]). These new values are loaded into the current frequency pipeline register 18 by the master clock. The p-bit pipelined current frequency value (CF[n]) is fed back to the input of the frequency adder 16 and also passed on to the input of the phase accumulator 14. The phase accumulator operates in the same way as the frequency accumulator. It adds the pipelined phase carry input (PCIN[n]) and the phase accumulator input (CF[n]), to the current phase value (CP[n]) held in the phase register 22. The result is a new current phase value (CP[n+1]) and a phase carry output signal (PCOUT[n]). Consider now, the position of one p-bit frequency/ phase accumulator 10 in the middle of the chain of m frequency/phase accumulators. This N th frequency/phase accumulator will receive its frequency and phase carry inputs (FCIN[N]) and (PCIN[N]) from the carry outputs of the N-1 th frequency/phase accumulator (FCOUT[N-1] and PCOUT[N-1]). Similarly the N th frequency/phase accumulator will pass its carry outputs (FCOUT[N] and PCOUT[N] to the carry inputs of the N+1 th frequency/phase accumulator (FCIN[N+1] and PCIN[N+ 1]). The required n-bit frequency increment value is split into m, p-bit sections each of which must be made available to the appropriate p-bit frequency/phase accumulator input, at the right time. This may be accomplished by pipelining the input values to the same depth as the corresponding frequency/phase accumulator, as shown in Figure 2. The p-bit phase outputs of each of the m, p-bit frequency/phase accumulators must be pipelined to compensate for the pipeline delay across the array of frequency/phase accumulators. This again is shown in Figure 2. Each frequency/phase accumulator produces one part of the required phase output value. At time T the first frequency/phase accumulator adds its frequency input, FIN[1,T], to its current frequency, CF[1,T-1] to produce a new current frequency CF[1,T] when the master clock is asserted. At time T the first phase accumulator adds the current frequency, CF[1,T-1] to the current phase CP[1,T-2] to produce the new current phase CP[1,T-1] when the master clock is asserted. Now consider the second frequency/phase accumulator in the chain. At time T the second frequency/phase accumulator adds its frequency input FIN[2,T-1] with the carry input from the previous (first) frequency/phase accumulator, FCIN[2,T-1], to the current frequency CF[2,T-2]. This gives a new current frequency CF[2,T-1] when the master clock is asserted. Similarly, at time T, the second phase accumulator is adding CF[2,T-2] with carry PCIN[2,T-2] to CP[2,T-3] to produce the new current phase CP[2,T-2] when the master clock is asserted. In general the N th frequency/phase accumulator in the chain will be performing the following calculations:- CF[N,T-N+1] = FIN[N,T-N+1] + FCIN[N,T-N+1] + CF[N,T-N] CP[N,T-N] = CF[N,T-N] + PCIN[N,T-N] + CP[N,T-N-1] At time T, the output of the first frequency/phase accumulator is that for time T-2. The output for the N th frequency/phase accumulator is that for time T-N-1. Thus the output of the first accumulator must be delayed using M-1 pipellne registers to be correctly aligned with the output of the M th unit. Not all the outputs of the phase accumulators are required. The phase outputs are used to look-up a sine and/or cosine value from a look-up table as in the arrangement of Figure 1. The look-up table will generally require an 8 to 10-bit address input to give adequate phase error in the generated chirp signal. This means that only the most significant Y-bits of the phase output are required where Y is the number of address bits for the sine/cosine look-up table. Consequently the pipeline registers connected to the remaining (least significant) phase outputs can be removed. The second embodiment, shown in Figure 4, includes this modification. For digital chirp generation it is necessary to set the start frequency at the beginning of the chirp. This may be done by loading the start frequency value into the frequency register 18 at the beginning of the chirp, instead of loading the output of the frequency adder 16 (i.e. sum of the frequency increment and current frequency value). To do this it is necessary to be able to select either the output of the frequency adder 16 or the start frequency value as the source to be loaded into the frequency register. This scheme is shown in Figure 5 where the frequency/phase accumulator of Figure 3 is modified by inserting a select circuit 24 between the frequency adder 16 and the frequency register 18. The selection logic may be included within the adder logic depending upon the detailed circuit design. A selection control signal, LD_SF[n], selects the start frequency, STARTF[n], as the source for the frequency register, when it is asserted. Otherwise the output of the frequency adder is selected. Note that it is not necessary to load the carry bit of the register when loading the start frequency because this will not be used by the next stage. The next stage (i.e. next frequency/phase accumulator in the chain) will load its start frequency value on the next clock pulse so it will not require the carry input from the previous stage. Referring now to Figures 6 to 7, a third embodiment implements a method of loading an initial start frequency value and/or an initial phase value which will now be described. The third embodiment is similar to Figure 4, and makes use of the modified chirp generator node shown in Figure 5. The proposed method for loading an initial phase value is analogous to the method for loading the start frequency value. A master clock signal is used to load all the pipeline registers at the same time. The digital start frequency input is not pipelined but separated into sections which are fed directly into respective chirp generator nodes. As described above, each frequency accumulator includes a select circuit 24 which controls the source for the frequency register, see Figure 5. When asserted, the selector control signal, LD_SF[n], selects the start frequency input, STARTF[n], as the input for the frequency register. Otherwise the output of the frequency adder is selected. The select circuits 24 are pipelined together via intermediate pipeline registers 26 and connected to a load terminal 28. When it is required to load a new start frequency a "load start frequency strobe" signal, LD_SF[1] which is active for the duration of one period of the master clock is applied to the load terminal 28. This strobe signal is used as the select control signal for the first frequency/phase accumulator in the pipelined array. It selects the start frequency input as the source for the frequency register of the first frequency/phase accumulator, see figures 6 and 7. The LD_SF[1] strobe signal is pipelined by a 1-bit register 26 and passed on to the second frequency/phase accumulator in the chain. Now, during the next master clock period, the first frequency/phase accumulator performs normally, using the output of the frequency adder as the source for the frequency register. However, the LD_SF[2] signal for the second frequency/phase accumulator is now asserted so the start frequency input to the second frequency/phase accumulator is selected as the source for its frequency register. The LD_SF[n] signal propagates down the associated chain of 1-bit pipeline registers 26, advancing one step after each master clock pulse. When the LD_SF[n] input to any frequency/phase accumulator is asserted it selects the start frequency input as the source for its frequency register. Thus each part of the entire start frequency value is loaded during the correct pipeline time slot. It should be noted that it takes M cycles to load the complete start frequency value, where M is the number of frequency/phase accumulators in the array. The start frequency/phase value must not be altered during this period. The fourth embodiment, described with reference to Figures 8 to 10, implements a method for loading the frequency increment value into the frequency/phase accumulator without the need for an array of pipeline registers to compensate for the pipeline delay in the frequency/phase accumulator array. In the fourth embodiment, the frequency/phase accumulator is similar to that of Figure 5 except that it includes a p-bit frequency increment register 30 for storing a frequency increment and being enabled by a signal pipelined between the adjacent frequency/phase accumulators. A master clock signal is used to load all the pipeline registers at the same time. The p-bit frequency increment registers 30 hold the current value of the frequency increment, see Figure 8. The digital frequency increment inputs to the digital chirp generator are not pipelined but separated into sections and fed directly to the input of the respective frequency increment registers 30 in all the frequency/phase accumulators. The latch enabling signal ENn is used, in each of the frequency/phase accumulators, to enable the loading of the new frequency increment value into the frequency increment register 30 when the master clock signal is asserted. When it is required to load a new frequency increment value a "load ramp rate strobe" signal, EN1, is generated, which is active for the duration of one period of the master clock. This strobe signal is used as the frequency increment latch enable signal for the first frequency/phase accumulator in the pipelined array. It loads the new frequency increment value into the frequency increment register of the first frequency/phase accumulator, see Figures 9 and 10. The EN1 strobe signal is pipelined by a 1-bit register 26 and passed on to the second frequency/phase accumulator in the chain. Now, during the next master clock period, the first frequency/phase accumulator will be able to use the new frequency increment value for its frequency accumulation operation. However, the EN2 signal for the second frequency/phase accumulator is now asserted so the new frequency increment value will be loaded into the frequency increment register of the second frequency/phase accumulator. The ENn signal propagates down the associated chain of 1-bit pipeline registers 26, advancing one step after each master clock pulse. When the ENn input to any frequency/phase accumulator is asserted it causes the new frequency increment value to be loaded into the corresponding frequency increment register. Thus each part of the entire frequency increment value is loaded into the frequency increment registers during the correct pipeline time slot. It should be noted that it takes M cycles to load the complete frequency increment value, where M is the number of frequency/phase accumulators in the array. The new frequency increment value must not be altered during this period. This method may be extended to include simultaneous loading of the start phase value, start frequency value and frequency increment value. In this fourth embodiment, the start frequency value may be injected either in the manner described in connection with the third embodiment or in any other suitable manner. The fifth embodiment is similar to the previous embodiments and implements a method for simultaneously loading the frequency increment value and the start frequency value into the frequency/phase accumulator using a single pipelined control signal, without the need for an array of pipeline registers to compensate for the pipeline delay in the frequency/phase accumulator array. The embodiment will be described with reference to Figures 8,11 and 12. A master clock signal is used to load all the pipeline registers at the same time. A p-bit frequency increment register 30 has been included in each of the frequency/phase accumulators, to hold the current value of the frequency increment, together with a select circuit 24 which controls the source for the frequency register, see Figure 8. The frequency increment inputs to the digital chirp generator are not pipelined but are separated into sections and fed directly to the input of the frequency increment register 30 in all the frequency/phase accumulators. A load signal LD-IN[n] is used, in each of the frequency/phase accumulators, to enable the loading of the new frequency increment value into the frequency increment register 30 when the master clock signal is asserted. Similarly, the start frequency input is not pipelined but separated into sections and is fed directly into all the frequency/phase accumulators. The LD-IN[n] signal, when asserted, causes the select circuit 24 to select the start frequency input as the source for the frequency register. When it is required to update the frequency increment and start frequency values a "load strobe" signal, LD-SF[1], is generated, which is active for the duration of one period of the master clock. This strobe signal is used both as the frequency increment latch enable signal and as the selector control signal for the first frequency/phase accumulator in the pipelined array. It loads the new frequency increment value into the frequency increment register 30 of the first frequency/phase accumulator. Simultaneously it selects the start frequency input as the source for the frequency register 18, see Figures 11 and 12. The LD-SF[1] strobe signal is pipelined by the 1-bit register 26 and passed on to the second frequency/ phase accumulator in the chain. Now, during the next master clock period, the first frequency/phase accumulator will be able to use the new frequency increment value and new start frequency value (current frequency) for its frequency accumulation operation. However, the LD-SF[2] signal for the second frequency/ phase accumulator is now asserted so the new frequency increment value will be loaded into the frequency increment register 30 of the second frequency/phase accumulator and the new start frequency will be loaded into its frequency register 18. The LD-SF[n] signal propagates down the associated chain of 1-bit pipeline registers 26, advancing one step after each master clock pulse. When the LD-SF[n] input to any frequency/phase accumulator is asserted, it causes the new frequency increment value to be loaded into the corresponding frequency increment register 30 and the new start frequency value to be loaded into the corresponding frequency register 18. Thus each part of the entire frequency increment value and start frequency value is loaded into the frequency increment registers 30 and frequency registers 18, respectively, during the correct pipe-line time slot. It should be noted that it takes M cycles to load the complete frequency increment value and start frequency value, where M is the number of frequency/phase accumulators in the array. The new frequency increment value and start frequency value must not be altered during this period. This method may be extended to include simultaneous loading of the start phase value, start frequency value and frequency increment value.

Claims: A digital chirp generator comprising a plurality of chirp generator nodes (10), each said chirp generator node (10) including frequency accumulator means (12) driving a phase accumulator means (14), said plurality of chirp generator nodes being pipelined together, whereby the frequency accumulator means (12) and the phase accumulator means (14) in a given chirp generator node (10) are interconnected with the corresponding accumulator means of the or each adjacent chirp generator node (10). A digital chirp generator according to Claim 1 including ramp rate input means for supplying successive sections of a digital frequency increment signal to successive ones of the frequency accumulators means (12). A digital chirp generator according to Claim 2, wherein the second and succeeding chirp generator nodes (l0),have associated therewith pipeline register means for progressively delaying the supply of said frequency increment signal sections, there being further pipeline register means associated with the outputs of said chirp generator nodes (10), to align the outputs thereof. A digital chirp generator according to Claim 1 or 2, wherein each chirp generator node (10) includes or has associated therewith a frequency increment register (30) for storing a section of a digital frequency increment signal, and enabling means for loading the section into the frequency accumulator means (12). A digital chirp generator according to Claim 4, wherein said enabling means are pipelined or otherwise interconnected to a rate load terminal, whereby a rate load signal applied to said rate load terminal causes the respective sections to be loaded into associated frequency accumulator means. A digital chirp generator according to claim 5, including pipeline register means (26) between each of said enabling means whereby the respective sections are loaded successively. A digital chirp generator according to Claim 5 or 6, wherein the sections of said digital frequency increment signal are supplied directly, without pipelining to the frequency accumulator means (12). A digital chirp generator according to any preceding Claim, including frequency start input means for loading into each frequency accumulator means (12) a respective section of a digital frequency start signal. A digital chirp generator according to Claim 8, wherein each frequency accumulator means (12) includes a selector means (24) responsive to a frequency control signal to input a respective section of a digital frequency start signal into the frequency accumulator means (12), there being frequency control means pipelining or otherwise interconnecting each of said selector means to a frequency load terminal, whereby a control signal supplied to said frequency load terminal causes the respective section of the digital frequency start signal to be injected into the associated frequency accumulator means. (12) A digital chirp generator according to Claim 9, wherein said frequency control means includes a pipeline register intermediate each of said frequency accumulator means (12), whereby the respective sections are injected in sequence into the associated frequency accumulator means. A digital chirp generator according to any one of Claims 8 to 10, wherein the frequency start signal is supplied directly without pipelining, to the frequency accumulator means (12). A digital chirp generator according to any preceding Claim, including phase start input means for loading into each phase accumulator means (14) a respective section of a digital phase start signal. A digital chirp generator according to Claim 12, wherein each phase accumulator means (14) includes a selector means responsive to a phase control signal to input a respective section of a digital phase start signal into the phase accumulator means (14), there being phase control means pipelining or otherwise interconnecting each of said selector means to a phase load terminal whereby a control signal supplied to said phase load terminal causes the respective sections of the digital phase start signal to be injected into the associated phase accumulator means (14). A digital chirp generator according to Claim 13, wherein said phase control means includes a pipeline register intermediate each of said phase accumulator means (14), whereby the respective sections are injected in sequence into the associate phase accumulator means. A digital chirp generator according to Claim 14, wherein the phase start signal is supplied directly, without pipelining, to the phase accumulator means (14). A digital chirp generator according to any preceding claim, wherein changes in at least two of frequency increment, start frequency and start phase are initiated in response to a common control signal. A digital chirp generator according to any preceding Claim, wherein each chirp generator node is a one bit accumulator. A digital chirp generator according to any preceding Claim, wherein each chirp generator node is a two or more bit accumulator. A digital chirp generator according to any preceding Claim, wherein the frequency accumulator means has a bit capacity different to that of the phase accumulator means. A digital chirp generator according to any preceding Claims, wherein only some of the outputs from the chirp generator nodes are used to provide an address signal for a look-up table.

Inventors: PARKES STEPHEN MAXWELL, PARKES, STEPHEN MAXWELL, Parkes, Stephen Maxwell, c/o British Aerospace
Applicants: MATRA MARCONI SPACE UK LTD, MATRA MARCONI SPACE UK LIMITED
Application year: 1991
Main classification: H03B23
IPC codes: H03B23, G01S13