Dynamic latch circuit

Abstract: A dynamic latch circuit which is fabricated in a semiconductor integrated circuit comprises a first circuit such as a clocked inverter and a second circuit such as an inverter. The first and second circuits are connected by a holding line. In the semiconductor integrated circuit, at least three interconnection layers are provided on a semiconductor substrate to be insulated by insulating layers, such that the holding line is provided as the secondly highest interconnection layer, and an output line of the second circuit is provided as the uppermost interconnection layer to be positioned on the straight upper side of the holding line. For this structure, a coupling capacitance which is formed between the holding line and a through line connected to a third circuit and provided as the uppermost interconnection layer is decreased.

Description: FIELD OF THE INVENTION This invention relates to a dynamic latch circuit of a semiconductor integrated circuit, and more particularly to, a dynamic latch circuit having a multilayer structure of at least three interconnection layers. BACKGROUND OF THE INVENTION A dynamic latch circuit of a semiconductor integrated circuit generally consists of a clocked inverter and an inverter, or a transfer gate and an inverter. A first conventional dynamic latch circuits is composed of a clocked inverter and an inverter connected through a holding line to the clocked inverter. In this conventional dynamic latch circuit, when an input signal is supplied to the clocked inverter, the input signal is inverted based on the timing of a clock signal applied to the clocked inverter, so that the inverted signal is supplied on the holding line to be connected to the inverter. Thus, an output signal which is obtained by inverting the inverted signal is generated on an output line of the inverter. This conventional dynamic latch circuit has an integrated circuit structure, such that an input line for the input signal, a clock line for the clock signal and a part of the holding line which is an input line of the inverter are provided as a first interconnection layer on a semiconductor substrate, the other part of the holding line which is an output line of the clocked inverter and a part of the output line of the inverter are provided as a second interconnection layer which is insulated from the first interconnection layer by an insulating layer, and the other part of the output line of the inverter is provided as a third interconnection layer which is insulated from the second interconnection layer by an insulating layer. A second conventional dynamic latch circuit includes a through line in addition to the structure of the first conventional dynamic latch circuit. The through line is assumed to be formed as the third interconnection layer which is positioned above the second interconnection layer. The through line is connected with other circuits, and operates independently with the latch circuit. Therefore, interfaces of each insulating layer can be used efficiently to increase an integration degree. According to the second conventional dynamic latch circuit, however, there is a disadvantage in that the holding line is affected by a coupling capacitance with the through line, so that a malfunction occurs by a crosstalk between the holding line and the through line. SUMMARY OF THE INVENTION According to the invention, a dynamic latch circuit comprises: a first circuit having an input line to which an input signal is applied, a second circuit having an output line from which a latched output signal is obtained, and a holding line connecting the first and second circuits, the input line, output line and the holding line being of at least three interconnection layers which are provided on a semiconductor substrate, and insulated by insulating layers grown on the semiconductor substrate, characterized in that the output line is positioned over and insulated from the holding line by an insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS The invention will be explained in more detail in conjunction with appended drawings; wherein: Fig. 1A is a plan view showing a first conventional dynamic latch circuit; Fig. 1B is a sectional view taken on line Y-Y′ of Fig. 1A; Fig. 2 is is a equivalent circuit of the first conventional dynamic latch circuit; Fig. 3A is a plan view showing a second conventional dynamic latch circuit; Fig. 3B is a sectional view taken on line Y-Y′ of Fig. 3A; Fig. 4 is a equivalent circuit of the second conventional dynamic latch circuit; Fig. 5 is a timing chart showing operation of the second conventional dynamic latch circuit; Fig. 6A is a plan view showing a dynamic latch circuit of a preferred embodiment according to the invention; Fig. 6B is a sectional view taken on line Y-Y′ of Fig. 6A; Fig. 7 is a equivalent circuit of the preferred embodiment; and Fig. 8 is a timing chart showing operation of the preferred embodiment. DESCRIPTION OF THE PREFERRED EMBODIMENTS Before describing a dynamic latch circuit according to the invention, the conventional dynamic latch circuits briefly described before will be explained in conjunction with Figs. 1A, 1B and 2 to 5. In Figs. 1A and 1B, a first conventional dynamic latch circuit includes a semiconductor substrate 10 having a diffused layer 14 formed thereon, first to third interconnection layers 16, 18 and 20 formed on the semiconductor substrate 10, and insulating layers 22, 24, 26 and 28 by which the interconnection layers 16, 18 and 20 are insulated, respectively. The first to third interconnection layers 16, 18 and 20 are connected with a plurality of contact regions 12, respectively. The first, interconnection layer 16 includes a first interconnection line 30 which is an input line of an inverter, an input line 32 of the dynamic latch circuit, and clock lines  and  each supplying a clock pulse to a clocked inverter. The second interconnection layer 18 includes a second interconnection line 34 which is an output line of the clocked inverter. The second interconnection line 34 is designed to be as short as possible to decrease a coupling capacity with other interconnection lines. The third interconnection layer 20 includes an output line 36 of the latch circuit. Fig. 2 shows an equivalent circuit of the dynamic latch circuit shown in Figs. 1A and 1B. The dynamic latch circuit includes a clocked inverter composed of two P-channel transistors P1 and P2 and two N-channel transistors N1 and N2 connected in series between a power supply and ground, respectively, and an inverter composed of a P-channel transistor P3 and an N-channel transistor N3 connected in series between a power supply and ground, respectively. In the clocked inverter, gates of the P-channel transistor P2 and the N-channel transistor N1 are connected with the clock lines  and  , respectively, and a common gate of the P-channel transistor P1 and the N-channel transistor N2 is connected with the input line IN(32). An output line of the clocked inverter (P1, P2, N1 and N2) is connected to a common gate of the P-channel transistor P3 and the N-channel transistor N3 through a holding line composed of the first and second interconnection lines 30 and 34, and an output line of the inverter (P3 and N3) is connected to the output line OUT(36). Next, a second conventional dynamic latch circuit will be explained in conjunction with Figs. 3A, 3B, 4 and 5. In Figs. 3A and 3B, the dynamic latch circuit includes a semiconductor substrate 10 having a diffused layer 14 formed thereon, first to third interconnection layers 16, 18 and 20 formed on the semiconductor substrate 10, and insulating layers 22 to 28 which are sandwiched among the interconnection layer s 16 to 20, respectively. The, first to third interconnection layer s 16 to 20 are, connected with a plurality of contact regions 12, respectively. The first interconnection layer 16 includes a first interconnection line 30 which is an input line of an inverter, an input line 32 of the dynamic latch circuit, and clock lines  and  each supplying a clock pulse to a clocked inverter. The second interconnection layer 18 includes a second interconnection line 34 which is an output line of the clocked inverter. The second interconnection line 34 is designed to be as short as possible to decrease a coupling capacity with other interconnection lines. The third interconnection layer 20 includes an output line 36 of the latch circuit and a through line T2 positioned above the second interconnection line 34. Fig. 4 shows an equivalent circuit of, the second conventional dynamic latch circuit shown in Figs. 3A and 3B. The dynamic latch circuit includes a clocked inverter composed of two P-channel transistors P1 and P2 and two N-channel transistors N1 and N2 connected in series between a power supply and ground, respectively and an inverter composed of a P-channel transistor P3 and an N-channel transistor N3 connected in series between a power supply and ground, respectively. In the clocked inverter, gates of the P-channel transistor P2 and the N-channel transistor N1 are connected with the clock lines  and  , respectively, and a common gate of the P-channel transistor P1 and the N-channel transistor N2 is connected with the input line IN(32). An output line of the clocked inverter (P1, P2, N1 and N2) is connected to a common gate of the P-channel transistor P3 and the N-channel transistor N3 through a holding line composed of the first and second interconnection lines 30 and 34, and an output line of the inverter (P3 and N3) is connected to the output line OUT(36). A coupling capacitance C2 is formed between the second interconnection line 34 and the through line T2. In the second conventional semiconductor integrated circuit, when a level of the clock line  becomes high from low at the time t₁ under a state that a level of the input line 32 is high, a level of the holding line (30 and 34) becomes low from high, as shown in Fig. 5. This signal level is maintained on the holding line. Next, when a level of the through line T2 becomes high from low at the time t₂ under a state that a level of the clock line  is low, a level of the holding line (30 and 34) rises up by the coupling capacity C2. Then, if the level of the holding line (30 and 34) rises over a threshold level of the N-channel transistor N3, a malfunction occurs in the latch circuit. That is, a level of the output line 36 becomes low from high at the time t₂, nevertheless the output level should be kept high until a level of the clock line  becomes high at the time t₃ as shown by a dashed line in Fig. 5. Next, a dynamic latch circuit of a preferred embodiment according to the invention will be explained in conjunction with Figs. 6A, 6B, 7 and 8. In Figs. 6A and 6B, a dynamic latch circuit includes a semiconductor substrate 10 having a diffused layer 14 formed thereon, first to third interconnection layers 16, 18 and 20 formed on the semiconductor substrate 10, and insulating layers 22, 24, 26 and 28 by which interconnection layers 16, 18 and 20, respectively are insulated. The first to third interconnection layers 16 to 20 are connected with a plurality of contact regions 12, respectively. The first interconnection layer 16 includes a first interconnection line 30 which is a part of an input line of an inverter, an input line 32 of the dynamic latch circuit, and clock lines  and  each supplying a clock pulse to a clocked inverter. The second interconnection layer 18 includes a second interconnection line 34 which is a part of an output line of the clocked inverter and an output line 36a of the inverter (P3 and N3) which is connected to the output line 36 of the latch circuit. The second interconnection line 34 is designed to be as short as possible to decrease a coupling capacity with other interconnection lines. The third interconnection layer 20 includes an output line 36 of the latch circuit positioned above the second interconnection line 34 and a through line T1 positioned above the first interconnection line 30. Fig. 7 shows an equivalent circuit of the dynamic latch circuit according to the preferred embodiment shown in Figs. 6A and 6B. The dynamic latch circuit includes a clocked inverter composed of two P-channel transistors P1 and P2 and two N-channel transistors N1 and N2 connected in series between a power supply and ground, respectively, and an inverter composed of a P-channel transistor P3 and an N-channel transistor N3 connected in series between a power supply and ground, respectively. In the clocked inverter, gates of the P-channel transistor P2 and the N-channel transistor N1 are connected with the clock lines  and  , respectively, and a common gate of the P-channel transistor P1 and the N-channel transistor N2 is connected with the input line IN(32). An output line of the clocked inverter (P1, P2, N1 and N2) is connected to a common gate of the P-channel transistor P3 and the N-channel transistor N3 through a holding line composed of the first and second interconnection lines 30 and 34, and an output line 36a of the inverter (P3 and N3) is connected to the output line OUT(36). In this structure, a coupling capacitance C1 which is formed between the second interconnection line 34 and the through line T1 can be decreased to a negligible value because the through line T1 is provided at a predetermined position, from which the second interconnection line 34, that is the holding line, is apart, to negate the coupling capacitance C1 substantially. In operation, when a level of the clock line  becomes high from low at the time t₁ under a state that a level of the input line 32 is high, a level of the holding line (30 and 34) becomes low from high and a high output signal is obtained, as shown in Fig. 8. After that, when a level of the clock line  becomes high from low at the time t₂ under a state that a level of the input line IN(32) is low, a level of the holding line (30 and 34) becomes high from low. Thus, a level of the output line OUT(36) becomes low from high in response to a correct change of the holding line (30 and 34). As described above, according to the preferred embodiment, the first interconnection line 30 is positioned through the insulating layer 24 on the lower side of the through line T1, and the second interconnection line 34 is positioned with a sufficient distance from the through line T1. Then, the coupling capacitance C1 is sufficiently small. Therefore, the holding line (30 and 34) is not affected by the coupling capacitance C1, so that the latch circuit always operates correctly, as shown in Fig. 8. An advantage of the invention is that the dynamic latch circuit embodying the invention is not affected by cross-talk between a holding line and other lines carrying unrelated signals, for example a through line, which could cause a malfunction in the circuit.

Claims: A dynamic latch circuit comprising: a first circuit having (P1,P2,N1,N2) an input line (32) to which an input signal is applied, a second circuit (P3,N3) having an output line (36) from which a latched output signal is obtained, and a holding line (30,34) connecting the first and second circuits, the input line (32), output line (36) and the holding line (30,34) being of at least three interconnection layers which are provided on a semiconductor substrate (10), and insulated by insulating layers (22,24,26,28) grown on the semiconductor substrate (10), characterized in that the output line (36) is positioned over and insulated from the holding line (30,34) by an insulating layer (24). A dynamic latch circuit, according to claim 1, further comprising a through line (T1) connected to a third circuit having a predetermined function; wherein said through line (T1) is provided as an uppermost interconnection layer to have a predetermined distance from said holding line (30, 34) to decrease the coupling capacitance therebetween. A dynamic latch circuit, according to claim 2, wherein said first circuit is a clocked inverter (P1,P2,N1,N2) said second circuit is an inverter (P3, N3); and an input line (32) and a clock line (,  ) of said clocked inverter (P1,P2,N1,N2) are provided as a lowermost interconnection layer. A dynamic latch circuit, according to claim 3, wherein said holding line (30,34) is provided as the secondly highest and lowermost interconnection layers which are connected by a contact hole (12).

Inventors: ISHIBASHI TAKASHI C O NEC CORP, ISHIBASHI, TAKASHI, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: H01L27
IPC codes: H01L21, H01L23, H01L27, H03K3, H03K19