Frequency and/or phase characteristic control circuit

Abstract: A frequency and/or phase characteristic control circuit comprising a current multiplier (8) and an operational amplifier (9), the current multiplier (8) containing a pair of diode junctions (Q₄,Q₅) and a transistor (Q₁,Q₂,Q₃) arrangement for differential amplification (10), the operational amplifier (9) having a capacitor (18) connected to the out-of-phase input terminal thereof. The multiplying ratio of the current multiplier (8) is varied so as to control the frequency and/or phase characteristic. This makes the circuit conductive to being implemented in an IC (integrated circuit). This circuit is particularly suitable for use as a circuit that switches the servo circuits of a laser disc player and a compact disc player.

Description: The present invention generally relates to a frequency and/or phase characteristic control circuit. More particularly, the invention relates to a frequency and/or phase characteristic control circuit conducive to being formed in an IC (integrated circuit) for the phase compensation of servo circuits in applications such as optical disc recording and reproducing apparatus. In Japanese Laid-open Utility Model No. 63-6516 there is disclosed a phase compensation circuit that includes a switching circuit for selecting a time constant. FIG. 1 of the present application is a reproduction of such circuit and illustrates a circuit diagram of a typical frequency and/or phase characteristic control circuit wherein a signal is fed from a photo detector 1 to a focus error amplifier 3 via current/voltage converters 2. The signal is then applied to an in-phase input terminal of an operational amplifier 4. From there, the signal is sent to a voltage/current converter 5 which in turn drives a focus coil 6. As illustrated, coupled to another input of the operative amplifier 4 are two selectable time constant establishing branches 4a and 4b. Branch 4a comprises serially coupled reactor R₁ and capacitor C₁. Branch 4b comprises serially coupled resistor R₂ and capacitor C₂. These time constant branches are selected in accordance with the application of a control signal at a control terminal C T . Inverters IV₃ and IV₁ and IV₂ are operatively disposed between the control terminal CT and the branches 4a and 4b, respectively, to provide for such selection. One disadvantage of this prior art phase compensation circuit is its inability to be readily formed in an IC. This is because the time constant capacitor C₁ or C₂ needs to have a capacity of about 0.1 µF when the responsive frequency is to be switched between 1KHz (e.g., for a compact disc player) and 2 KHz (e.g., for a laser disc player). A circuit comprising the features in the preamble of claim 1 is known from EP-A-0 273 425. This document discloses a double integration type filter circuit consisting essentially of a pair of integrators connected in series with each other. Depending on which terminals of the integrators are supplied with the input signal or are grounded allows various types of filters (e.g. LPF, HPF, BPF, trap) to be realised. SUMMARY OF THE INVENTION The present invention overcomes the above-described drawbacks and disadvantages and provides a frequency and/or phase characteristic control circuit wherein the frequency characteristic is stabilized against temperature fluctuations. Further, the present invention provides a frequency and/or phase characteristic control circuit wherein the capacitance of a capacitor interposed between the output terminal of a current multiplier and the out-of-phase input terminal of an operational amplifier is equivalent to a multiplying ratio M of the current multiplier, thereby making the capacitance of the actual capacitor small enough so that the frequency and/or phase characteristic control circuit can readily be implemented in an IC. Yet further, the present invention provides a frequency and/or phase characteristic control circuit in an IC where the resistance value of the load resistor for the current multiplier is made variable, thereby minimizing temperature-induced changes in frequency or phase characteristic. To these ends, the present invention provides a frequency and/or phase characteristic control circuit comprising: a) a current multiplier having a multiplying ratio and containing an input terminal to be supplied with an input voltage, a voltage/current converter supplied with the input voltage so as to produce a pair of current signals at an output thereof, a pair of diode junctions supplied with the pair of current signals, a differential amplifier having first and second transistors and a current source, the first and second transistors being supplied with the voltage across the pair of diode junctions to produce a multiplied output current, and an output terminal connected to the output of the differential amplifier; b) an operational amplifier having an in-phase input terminal, an out-of-phase input terminal and an output terminal; and c) a first impedance connected between the out-of-phase input terminal and the output terminal of the operational amplifier; wherein the frequency and/or phase characteristic of the output signal of the operational amplifier is controlled by varying the multiplying ratio of the current multiplier; said control circuit being characterised in that d) a load resistor is connected to the output of the differential amplifier so as to produce an output voltage across the load resistor proportional to the multiplied output current; and e) a capacitor is connected between the output terminal of the current multiplier and the out-of-phase input terminal of the operational amplifier; and f) a second impedance is connected between the input terminal of the current multiplier and the out-of-phase input terminal of the operational amplifier. These and other features of the invention will become more apparent with reference to the following detailed description of the presently preferred embodiment and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a typical prior art frequency and/or phase characteristic control circuit. FIG. 2 is a circuit diagram of a frequency and/or phase characteristic control circuit embodying the present invention. FIG. 3 is a variation of the circuit diagram of the embodiment of FIG. 2. FIG. 4 is another equivalent circuit diagram of the circuit diagram of the embodiment of FIG. 2. FIGS. 5A and 5B are a gain characteristic chart and a phase characteristic chart, respectively, for use in describing the invention. DESCRIPTION OF THE PRESENTLY PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described with reference to FIGS. 2-6. FIG. 2 is a circuit diagram of a first frequency and/or phase characteristic control circuit embodying the invention. In FIG. 2, reference numeral 8 identifies a current multiplier, and numeral 9 identifies an operational amplifier. The current multiplier 8 comprises: a differential amplifier 10 having a pair of transistors Q₁ and Q₂ and a constant current supply transistor Q₃; a pair of transistors Q₄ and Q₅ interposed as a pair of diode junctions between each base of the pair of transistors Q₁ and Q₂ on the one hand and a reference voltage supply V r on the other hand, the bases of the transistors Q₄ and Q₅ being interconnected; and a V/I converter 12 for converting an input voltage V i supplied to an input terminal 11 into an input current I₁. The V/I converter 12 comprises transistors Q₆ and Q₇. The transistor Q₆ has its base and collector connected respectively to the input terminal 11 and to the emitter of the transistor Q₄. The transistor Q₇ has its base and collector connected respectively to a bias voltage supply V b and to the emitter of the transistor Q₅. The emitters of the transistors Q₆ and Q₇ are interconnected through a resistor 13 having a resistance value of R₁. These emitters are also connected to the collectors of the transistors Q₈ and Q₉ whose emitters are connected to a reference potential point (i.e., ground). Two equivalent bias currents I₁ flowing through the transistors Q₈ and Q₉ are supplied to the emitters of the transistors Q₄ and Q₅ via the collector emitter circuit of the transistor Q₆ and Q₇. The base and emitter of the constant current supply transistor Q₃ are connected in parallel with the base and emitter of a diode connected transistor Q₁₀ to constitute a current mirror circuit. The base and emitter of the transistors Q₈ and Q₉ are connected in parallel with the base and emitter of a diode connected transistor Q₁₁ thereby to constitute a current mirror circuit. The collector of the transistor Q₁₁ is connected to a voltage supply V CC via a resistor 14 having a resistance value of R₂. The collector of the transistor Q₁₀ is also connected to the voltage supply V CC via a resistor 15 having a resistance value of R₃. A current 2I₂ flowing through the constant current supply transistor Q₃ of the differential amplifier 10 branches out to the transistors Q₁ and Q₂. This causes a current I₂ to be supplied to transistors Q₁₂ and Q₁₃ which are connected to the collectors of the transistors Q₁ and Q₂ to another current mirror circuit. A common connection point of the collectors of the transistors Q₁₃ and Q₂ is connected to an output terminal 16. The collectors of the transistors Q₁ and Q₂ in the differential amplifier 10 are supplied with an output current i₂ (wherein, i₂ = i₁ · I₂/I₁). This output current i₂ is obtained by multiplying the input current i₁ by the ratio of half of the current 2I₂ flowing between the collector and emitter of the constant current supply transistor Q₃ to the bias current I₁ flowing between the collector and emitter of the transistors Q₄ and Q₅. From the above current flow, a current 2₁₂ is obtained by a push-pull connection. The output current 2I₂ generates an output voltage V₀ at a load resistor which has a resistance value of R L and is connected to the output terminal 16, the output voltage V₀ being proportional to the output current i₂. A capacitor 18 having a capacitance of C is connected between the output terminal 16 of the current multiplier 8 and the out-of-phase input terminal (negative) of the operational amplifier 9. A first impedance element 19 having an impedance value of Z₁ is connected between the input terminal 11 of the current multiplier 8 and the out-of-phase input terminal (negative) of the operational amplifier 9. A second impedance element 20 having an impedance value of Z₂ is connected between the out-of-phase input terminal (negative) and output terminal 21 of the operational amplifier 9. In operation, when the two transistors Q₁ and Q₂ in the differential amplifier 10 have the same characteristic as the transistors Q₄ and Q₅ whose base and emitter circuit constitute a pair of diode junctions, the sum of a voltage V BE4 between the base and emitter of the transistor Q₄ and a voltage V VBE1 between the base and emitter of the transistor Q₁ becomes equal to the sum of a voltage V BE5 between the base and emitter of the transistor Q₅ and a voltage V BE2 between the base and emitter of the transistor Q₂. Thus, the following equation is obtained: V BE4 + V BE1 - V BE5 - V BE2 = 0 Meanwhile, each emitter-to-base voltage can be expressed as follows: V BE4 = KT q 1 n I ₁ + i ₁ i s V BE1 = KT q 1 n I ₂ - i ₂ i s V BE5 = KT q 1 n I ₁ - i ₁ i s V BE2 = KT q 1 n I ₁ + i ₂ i s where, q stands for the electric charge of an electron, K for Boltzmann's constant, T for the absolute temperature, and i s for the reverse saturation current. It is assumed that the current i s of each transistor is the same. By substituting equations (2) through (5) in equation (1), one obtains the following equation i ₂ = I 2 I ₁ . i ₁ If the resistance value R₁ of the resistor 13 is sufficiently larger than the emitter resistance (26Ω/1 mA), then i ₁ = V in R ₁ Thus, the output voltage V₀ of the current multiplier 8 is given by the equation V ₀ = 2 i ₂ · R L = V in R ₁ · V CC R ₃ · R ₂ V CC · R L = V in R ₁ · R ₂ R₃ · R L = MV in where, a multiplying ratio of M = R ₂ · R L R ₁ · R ₃ A transfer function G (S) across the input terminal 11 to the output terminal 21 is obtained using the equation G (S) = Z ₂ Z ₁ ( 1 + S M C Z ₁ ) Therefore, the frequency characteristic is controlled by varying the multiplying ratio M of the current multiplier 8. As is evident from equation (8), MCZ₁ indicates that the time constant apparently is given as if multiplied by M. This reduces the required capacitance of the capacitor 18, which makes it easier to form the circuit in an IC. If the resistor 14 having the resistance value R₂ is externally installed, the resistance ratio inside the IC becomes: Z ₁ · R L R ₁ · R₃ This keeps the frequency characteristic stabilized against temperature fluctuations. Referring now to FIG. 3, in one embodiment, the multiplying ratio M of the current multiplier 8 is set to 5.5. The first impedance element 19 comprises attentuation resistors 19a (130 KΩ) and 19b (37 KΩ) and a feedback resistor 19c (330 KΩ). The second impedance element 20 comprises attenuation resistors 20a (110 KΩ) and 20b (7.5 KΩ), a feedback resistor 20c (463 KΩ) and a capacitor (1 pF) for preventing oscillation. The capacitor 18 has a capacitance (c) of 68 pF, and the load resistor 17 has a resistance (R L ) of 165 KΩ. In this embodiment, one obtains the following relationships: r ₁ = R L M = 165 5.5 = 30KΩ C₀ = CM = 5.5 x 68 pF = 374 pF r ₂ = 130 x 37 + 37 x 330 + 330 x 130 37 = 1.62MΩ r ₃ = 110 x 7.5 + 7.5 x 463 + 463 x 110 7.5 = 7.3MΩ The frequency characteristic of the equivalent circuit in FIG. 3 has an inflection point at f ₁ = 1 2 π C o (r ₁ + r₂) = 258Hz and at f ₂ = 1 2 π C o r ₁ = 14KHz This is indicated by character G in FIG. 5 (A). The equivalent circuit is illustrated in FIG. 4. The peak frequency f₀ of the phase characteristic is obtained using the following equation: f₀ = f ₁ + f ₂ = 258 x 14000 as depicted in FIG. 5 (B) in which a peak Φ is observed at around 2 KHz. In the equation providing the multiplying factor M for the current multiplier 8, M = R ₂ · R L R₁ · R ₃ the resistance value R L of the load resistor 17 is multiplied by 1/n so as to turn f₁ into nf₁, f₂ into nf₂, and f₀ into n f ₁ · n f ₂ = n f ₁ · f ₂ Thus, the frequency and phase characteristic is varied as desired. For example, if n = 1/2, then f₀ is set at approximately for 1 kHz. The load resistor 17 preferably comprises an electronic switch that controls a plurality of resistors using a control signal external to the IC. That is, the resistance value R L may alternatively be varied by operating the electronic switch. As described, the frequency and/or phase characteristic control circuit according to the invention is a circuit wherein the capacitance of the capacitor interposed between the output terminal of the current multiplier and the out-of-phase input terminal of the operational amplifier is multiplied by the multiplying ratio M of the current multiplier. This means that the actual capacitance of the capacitor is small enough to permit the circuit to be readily formed in an IC. Where the resistance value of the load resistor arrangement in the current multiplier is varied in a frequency and/or phase characteristic control circuit formed in an IC, temperature-induced fluctuations in the frequency or phase characteristic are significantly reduced. It is to be understood that while the invention has been described in conjunction with specific embodiments, it is evident that many alternatives, modifications and variations will become apparent to those skilled in the art in light of the foregoing description. Accordingly, it is intended that the present invention embrace all such alternatives, modifications and variations which fall within the scope of the appended claims.

Claims: A frequency and/or phase characteristic control circuit comprising: a) a current multiplier (8) having a multiplying ratio (m) and containing an input terminal (11) to be supplied with an input voltage (V in ), a voltage/current converter (12) supplied with said input voltage so as to produce a pair of current signals at the output thereof, a pair of diode junctions (Q₄,Q₅) supplied with said pair of current signals, a differential amplifier (10) having first and second transistors (Q₁,Q₂) and a current source (Q₃), said first and second transistors (Q₁,Q₂) being supplied with the voltage across said pair of diode junctions (Q₄,Q₅) to produce a multiplied output current, and an output terminal (16) connected to the output of said differential amplifier (10); b) an operational amplifier (9) having an in-phase input terminal, an out-of-phase input terminal and an output terminal; and c) a first impedance (20) connected between the out-of-phase input terminal and the output terminal of said operational amplifier (9); wherein the frequency and/or phase characteristic of the output signal of said operational amplifier (9) is controlled by varying the multiplying ratio of said current multiplier (8); said control circuit being characterised in that d) a load resistor (17) is connected to the output of said differential amplifier so as to produce an output voltage across said load resistor (17) proportional to said multiplied output current; e) a capacitor (18) is connected between the output terminal of said current multiplier (8) and the out-of-phase input terminal of said operational amplifier (9); and f) a second impedance (19) is connected between the input terminal (11) of said current multiplier (8) and the out-of-phase input terminal of said operational amplifier (9). A frequency and/or phase characteristic control circuit according to claim 1, wherein the multiplying ratio of said current multiplier is controlled by varying the resistance (R L ) of said load resistor (17). A frequency and/or phase characteristic control circuit according to claim 1, wherein the multiplying ratio of said current multiplier is controlled by varying the current ratio of said voltage/current converter (12) and said differential amplifier (10). A frequency and/or phase characteristic control circuit according to any one of claims 1 to 3, wherein said input voltage of said current multiplier (8) is a servo signal and the output signal of said operational amplifier (9) is used for driving a focus coil. A frequency and/or phase characteristic control circuit according to any one of claims 1 to 4, wherein said frequency and/or phase characteristic of said operational amplifier (9) is controlled by varying the resistance (R L ) of said load resistor (17) in response to a signal generated by a device such as a laser disc player or a compact disc player. A frequency and/or phase characteristic control circuit according to any one of claims 1 to 5, wherein said current multiplier (8) and said operational amplifier (9) are formed in a single-chip integrated circuit.

Inventors: TERADO IKUO C O SONY CORPORATI, TERADO, IKUO, C/O SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1991
Main classification: H03H11
IPC codes: H03H11, G11B7