Non-volatile semiconductor memory

Abstract: A memory cell array is divided into a plurality of blocks. In altering data for a block (selected block), a moderating voltage is applied to the source or control gate of a memory cell in another block (non-selected block) to moderate stress between the floating gate and source/drain, thereby preventing write error and erase error. In the program operation, the source and drain of a memory cell in the non-selected block are equalized to moderate an electric field between the control gate and source/drain and not to flow a channel current, thereby preventing write error. In carrying out a negative voltage erase method, prior to setting the source line and word line of a cell in a non-selected block to an erase voltage, the source and word lines are equalized. The equalization operation is released after the erase operation, thereby preventing malfunction of a non-selected cell.

Description: The present invention relates to a non-volatile semiconductor memory, and more particularly to a non-volatile semiconductor memory having a plurality block of non-volatile memory cells of two-layered structure, capable of altering data in units of block. BACKGROUND OF THE INVENTION From EP 0 02 566 A2 there is known an electrically erasable programmable read-only memory that utilizes an inhibit voltage applied to unselected word lines during writing to prevent writing in unselected rows. Further, from IEEE International Solid State Circuits Conference, Vol. 32, 1 February 1989, page 132/133, 313 XP000066856 Sebastiano D'Arrigo et al: "Nonvolatile Memories A 5V-Only 256K Bit CMOS Flash EEPROM" there is a 5V-only 256K bit CMOS flash EEPROM-memory which requires only 5V for program, erase and read operations, respectively, and has performance and cost comparable to that of the recently reported dual power supply flash EEPROM-memories that require 12V for program and erase and 5V for read. All-bit flash erase type memories have drawn attention as electrically erasable, programmable read-only memories (E 2 PROM). Recent requirements for such memories are to provide a function of altering data in each of a plurality of memory blocks in units of block. For example, a 4 M bit device is divided into 16 blocks each having 32 K bytes or into 4 blocks each having 256 K bytes, and data erasure is required to be performed on the block unit basis. With such block division of a cell array, cells in a plurality of different blocks are connected to the same word line or data line. Therefore, repeating write/erase of a particular block may apply stress to cells in other non-selected blocks. The degree of such stress will be discussed for cells of two-layered structure. In the case of cells of two-layered structure used in flash type E 2 PROM, data write is performed in a manner similar to EPROM. Namely, a control gate is applied with V CG = 12 V, a drain with V D = 6 V, and a source with V S = 0 V. In this state, hot electrons generated by an avalanche effect are injected to the floating gate. For data erase, the control gate is applied with V CG = 0 V, the source with V S = 12 V. In this state, electrons are taken out of the floating gate as F-N tunnel current between the floating gate and source. The characteristic structure of such a cell resides in that the gate oxide film under the floating gate is about 100 angstroms thinner than that of an EPROM cell because a tunnel current flows between the floating gate and source during data erase, and that the superposing area of the source n + region and the floating gate is made wider than that of EPROM. In a cell array having a plurality of blocks comprised by cells of such structure, stress applied to a cell in an erase state or write state in a non-selected block is shown in Table 1. A cell in an erase state in a non-selected block connected to a selected word line is applied to an electric field of about 7.5 MV/cm between its floating gate and source, and a cell in a write state in a non-selected block connected to a selected data line is applied to an electric field of about 6.5 MV/cm between its floating gate and drain. Next, there will be discussed the time period while stress is applied to a cell in a non-selected block during data erase or data write. Consider a 4 M bit device divided into blocks at intervals of 32 K bytes in the data line direction. Assuming that cells in a block are subject to write/erase as many as 10 5 times with a write time of 10 µs and write occurrence frequency of 25 times for each cell, a cell in a non-selected block is applied with V CG = 12 V during the total time period of 800 sec. Stress of 7.5 MV/cm is therefore applied between the floating gate and source during the time period 800 sec, inevitably leading to write error. As an alternate, consider a 4 M bit device divided into blocks at intervals of 32 K bytes in the word line direction, a cell in a non-selected block is applied with 6 V at its drain during the total time period 6400 sec. Stress of 6.5 MV/cm is therefore applied between the floating gate and drain during the time period 6400 sec, inevitably leading to erase error. As described above, a conventional device is associated with the problem that as data write and erase are effected to a selected block, data write error and erase error may occur at non-selected blocks. In a conventional data erase scheme, electrons accumulated in a floating gate FG are emitted toward the source by applying a high voltage to the cell source, as discussed previously. With this scheme, it is unable to use a source voltage equal to or higher than the breakdown voltage of a source junction, there arises some restriction that cell sources are required to be formed separately in order to allow block erase (simultaneous erase of a plurality of cells contained within one block). Another scheme using a negative voltage has been considered which can erase data without applying a high voltage to the cell source. An apparatus performing such scheme is conceptually shown in Fig. 29, and timings of waveforms used by the apparatus are shown in Fig. 30. Table 2 shows examples of voltages set to cells at different modes. Mode Cell WL DL Source Erase Selected Cell -10 V 3 V 5 V Non-selected Cell 5 V 3 V 5 V Program Selected Cell 12 V 6 V 0 V Read Selected Cell 5 V 1 V 0 V This scheme is characterized in that a plurality of memory cells connected to one selected word line can be erased at the same time. It is now assumed that a word line WL 1 is selected and another word line WL 2 is not selected in a data erase mode. Specifically, the selected word line WL 1 is applied with a voltage VWL 1 of -10 V, the non-selected word line WL 2 is applied with a voltage VWL 2 of 5 V, a source voltage VS is set to 5 V, and data lines DL 1 and DL 2 are set to a floating state. In this state, memory cells M1 and M2 enter an erase state, and memory cells M3 and M4 enter a non-erase state. In a program mode (in a data write mode), hot electrons are injected into a floating gate FG. In a read mode, a sense amplifier judges whether a selected cell is being turned on (a cell current flows) or off (a cell current will not flow). The above-described scheme has the following problems. At the non-selected cells M3 and M4 in the erase mode, WL 2 is set to 5 V, VS is set to 5 V, and DL 1 and DL 2 enter the floating state. As a result, the data lines DL 1 and DL 2 are charged via the non-selected cells M3 and M4 up to (5 V - V th ) where V th is a cell threshold value. A cell current for charging the data lines DL 1 and DL 2 flows in the non-selected cells M3 and M4 during the time period from t 1 to t 2 , therefore leading to a possibility of write error at the non-selected cells M3 and M4. Also in the end of erase mode, electric charges used for charging the data lines DL 1 and DL 2 are discharged so that a cell current will flow during the time period from t 3 to t 4 , leading to a possibility of write error. In addition, if charge/discharge relative to the source and word lines is carried out rapidly, a peak current will flow which may break wiring material. SUMMARY OF THE INVENTION It is an object of the present invention to provide a non-volatile semiconductor memory capable of preventing malfunction such as write error, erase error and the like, during the data write and data erase. It is another object of the present invention to provide a non-volatile semiconductor memory capable of preventing malfunction of a non-selected memory cell upon data write or erase for an optional number of memory cells selected from a plurality of memory cells. It is a further object of the present invention to provide a non-volatile semiconductor memory wherein the memory cell are divided into a plurality of blocks each having a plurality of memory cells, data can be altered on the block unit basis, and malfunction of a cell in a non-selected block can be prevented even if data in a cell in a selected block is written or erased. A memory cell array according to claim 1 is divided into a plurality of blocks. In altering data for a block (selected block), a moderating voltage is applied to the source or control gate of a memory cell in another block (non-selected block) to moderate stress between the floating gate and source/drain, thereby preventing write error and erase error. In the program operation, the source and drain of a memory cell in the non-selected block are equalized to moderate an electric field between the control gate and source/drain and not to flow a channel current, thereby preventing write error. In carrying out a negative voltage erase method, prior to setting the source line and word line of a cell in a non-selected block to an erase voltage, the source and data lines are equalized. The equalization operation is released after the erase operation, thereby preventing malfunction of a non-selected cell. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a diagram showing the overall arrangement according to the present invention. Fig. 2 is a circuit diagram showing the details of a portion of the arrangement shown in Fig. 1. Figs. 3 to 7 are deleted. Fig. 8 is a circuit diagram showing the details of the column gate section. Fig. 9 is a circuit diagram showing the main portion of the row decoder. Fig. 10 is a graph showing the characteristics of a memory cell in a non-selected block. Figs. 11 to 20 are deleted. Fig. 21 is a conceptual view showing another embodiment of the present invention. Fig. 22 is a timing chart explaining the operation of the embodiment shown in Fig. 21. Figs. 23A and 23B illustrate the states of a selected word line and non-selected word line shown in Fig. 21 during an erase mode. Figs. 24A and 24B illustrate the states of a selected word line and non-selected word line shown in Fig. 21 during the program mode. Fig. 25 illustrates the state of the row decoder shown in Fig. 21 during the read mode. Figs. 26A and 26B illustrate the state of the negative bias circuit shown in Fig. 21 during the erase mode and other modes. Fig. 27 is a circuit diagram of the source bias circuit shown in Fig. 21. Fig. 28 is a conceptual diagram showing the overall arrangement of another embodiment according to the present invention. Fig. 29 is a conceptual diagram of a conventional memory device. Fig. 30 is a timing chart explaining the operation of the conventional memory device. PREFERRED EMBODIMENTS OF THE INVENTION Fig. 1 shows a device whose memory cell array is divided into sixteen blocks in the data line direction. The memory cell array 1 is divided into sixteen blocks 2 each provided with a block erase circuit 3. In Fig. 1, reference numeral 5 represents a row decoder, reference numeral 6 represents a column decoder, and reference numeral 7 represents a row pre-decoder. The details of each block 2 are shown in Fig. 2. As seen from Fig. 2, each block erase circuit 3 is commonly connected to the sources of cells C XY in each block 2. Cells commonly connected to one data line DLαβ are located within the same block. Cells commonly connected to one word line WL i are located over a plurality of blocks. A data alteration operation of one block of the device constructed as above will be described below. In the erase sequence for cells of two-layered structure described above, in order to prevent a read error of a cell due to transformation to the depletion type of a cell to be caused by over erase, all cells in a subject block are first written with data and then erased at the same time. In a write mode, a sequence similar to the case of EPROM is executed. In other words, for the data alteration, a write operation is carried out twice. In this case, stress is applied to the control gates of cells in non-selected blocks connected to the same word line of the block to be altered. In order to moderate an electric field between the floating gates and sources of cells in an erase state in non-selected blocks, a predetermined potential (moderating potential) is applied to the cell sources. For example, if a potential of 2 V is applied to a cell source, the electric field between the floating gate and source becomes about 5 MV/cm which moderates the electric field by about 2.5 MV/cm as compared with about 7.5 MV/cm when 0 V is applied to the cell source. Fig. 8 shows the structure of the column gate. Fig. 8 corresponding to Fig. 1 shows the column structure of one block, a row decoder buffer, a word line, and cells C 111 to C 1ml connected to the word line. This device is obtained, for example, by dividing a 4 M bit cell array into sixteen blocks in the data line direction at intervals of 32 K bytes. One block has 128 data lines for 8 I/O units each I/O assigned 16 data lines. One byte is selected by one of column signals hl to h16. Each block is selected by one of column signals sl to s16. In Fig. 8, T200 to T207 represent column gate transistors for selecting a block, and T210 to T287 represent column gate transistors selected by the column signal hl to h16. Fig. 9 shows the structure of the row decoder 5. In Fig. 9, MD represents a main decoder having a plurality of transistors T350 to T355 and selected by outputs RAi, RBi, and RCi from the row pre-decoder, T300, T310, T320, T330, T340 to T343 represent transfer gates selected by outputs RDR i and RDL i from the row pre-decoder, T300', T310', T320', and T330' represent charge transistors, T301 to T303, T311 to T313, T321 to T323, and T331 to T333 represent feedback-type inverters. A circuit CIR at the left side of Fig. 9 has the same structure as the circuit CIR at the right side. If a word line WL 1 for example is to be selected, the main decoder MD selected by the outputs RAi, RBi, and RCi takes a state of RA = RB = RC = "H", so that a node MAIN becomes "L". RDR 1 for selecting the word line WL 1 becomes "H", and NRDR 1 becomes "L". Other RDR 2 to RDR 4 become "L", and other NRDR 2 to NRDR 4 become "H". As a result, the transistor T302 turns on and the transistor T303 turns off, so the word line WL 1 takes an SW potential. At this time, the transistors T312, T322, and T332 turn off T313, T323, and T333 turn on, so the other word lines WL 2 to WL 4 take a ground level. In the memory device having divided blocks, first to eighth blocks 2 and ninth to sixteenth blocks 2 are grouped on opposite sides of the row decoder 5 as shown in Fig. 1. The right transfer gate RDRi executes a logical calculation with a block selecting column signal Si to drive only the right word line connected to the selected block. Similarly, the left transfer gate RDLi executes a logical calculation with the block selecting column signal Si to drive only the left word line connected to the selected block. Fig. 10 is a graph showing the relationship between time duration of stress applied to the control gate of an erased cell in a non-selected block and a change in cell V TH . The cell source is assumed to be set to 0 V. As the control gate stress time period becomes long, the cell V TH rises. This rise is dependent upon the control gate potential. For V CG = 13 V, a large rise is observed at about 100 sec. For V CG = 9 V on the other hand, a rapid rise will not be observed up to 1000 sec. The above cases are observed when setting the cell source to 0 V. If the cell source is set to 2 V, the characteristics obtained at the electric field between the floating gate and source corresponding to V CG = 13 V are substantially equal to the characteristics obtained at the electric field corresponding to V CG = 9 V and cell source set to 0 V. Assuming that the coupling ratio C cf is 0.5 between the control gate and floating gate and the coupling ratio C sf is 0.1 between the source and floating gate, the floating gate potential V FG at the cell source set to 0 V and V CG = 13 V becomes: V FG = C cf × V CG = 6.5 V, and so the electric field E sf between the source and floating gate becomes 6.5 MV/cm. At the cell source set to 0 V and V CG = 9 V, then V FG becomes 4.5 V and E sf becomes 4.5 MV/cm. If the cell source is set to 2 V and V CG = 13 V, then the floating gate potential V FG becomes: V FG = V CG × C cf + V s × C sf = 13 × 0.5 + 2 × 0.1 = 6.7 V, and so E sf = 6.7 - 2 = 4.7 MV/cm. As described above, by raising the cell source potential of a non-selected block by about 2 V, it is possible to sufficiently suppress the variation of the V TH of a cell in an erase state. The terms V TH0 and V THMax are herein introduced, the term V TH0 being a V TH of a cell in an erase state without no stress, and the term V THMax being a limit V TH of a cell providing no access time delay and no read error. If there is provided no effective countermeasure for a cell source, the cell V TH becomes V THMax at V CG = 13 V and in stress time period of about several hundreds sec. In contrast, if a countermeasure for raising a potential at a cell source, the cell V TH will not reach V THMax even at V CG = 13 V and in stress time period of about 1000 sec or longer, by raising to V s = 2 V which corresponds to a drop of V CG = 4 V. If data alteration is repeated 10 5 times to a particular block of a memory device divided as shown in Fig. 1, the stress time period of cells in a non-selected block is about 800 sec, enabling to prevent malfunction to be caused by stress. Next, another embodiment will be described wherein a potential is set without allowing a cell current to flow in a non-selected cell during the erase operation, thereby preventing malfunction of the non-selected cell. In this embodiment, in order to realize such a function, prior to applying an erase mode potential to the source line SL and word line WL, the source line SL and data line DL are equalized. The conceptual diagram illustrating such an embodiment of the present invention is shown in Fig. 21, and its timing chart is shown in Fig. 22. For the erase operation, an erase signal Erase becomes "H" level at time t 1 . In the erase state, an output EQ of a source bias circuit SBC becomes "H" level. Accordingly, equalizing transistors TEQ 1 and TEQ 2 turn on to connect together a source line SL and data lines DL 1 and DL 2 . At time t 2 , the potential VS of a cell source takes the same potential (e.g., 5 V) as that of the cell drain (data line DL 1 , DL 2 ). Thereafter, a selected word line (e.g., WL 2 ) are set to predetermined potentials. For example, the selected word line WL 1 is set to -10 V, and the non-selected word line WL 2 is set to 5 V( at time t 3 ). The important points in setting such voltages are that the voltages of the word lines WL 1 and WL 2 are set after completely equalizing the potentials of the source and drain, and that a cell current is not allowed to flow while charging the word line WL 2 of the non-selected cell to 5 V. After the end of data erase at time t 4 , discharging the word lines WL 1 and WL 2 is completed at time t 5 , and thereafter the source line SL and data lines DL 1 and DL 2 are discharged. After completion of discharging the source line SL and data lines DL 1 and DL 2 , the equalization is released at time t 7 . With such timing settings, a cell current will not flow during the time periods from t 1 to t 3 and from t 4 to t 6 , thereby preventing write error in a non-selected cell. As the degree of integration becomes high, the capacities of source lines, data lines, and word lines also increase. In such conditions, if rapid charge/discharge is carried out for data erase, an excessive current will flow to source lines, data lines, and word lines, leaving a fear of breaking the chip. In view of this, according to the present embodiments, gentle charge/discharge is performed. Voltages of the Invention Mode Cell WL DL Source SW Erase Erase Selected Cell -10 5 5 5 5 Non-selected Cell 5 5 5 5 5 Program Selected Cell 12 6 0 12 0 Non-selected Cell 0 (12) 0 (6) 0 12 0 Read Selected Cell 5 1 0 5 0 Non-selected Cell 0 (5) 0 (1) 0 5 0 Table 5 shows examples of setting voltages in various operation modes. While referring to Table 5, there will be described examples of the row decoder RD, negative bias circuit NBC, and source bias circuit SBC, respectively shown in Fig. 21. Figs. 23A to 25 show circuit portions of the row decoder RD. Specifically, Fig. 23A shows a circuit which generates a potential of -10 V to be applied to a selected word line during the erase operation. A NAND gate at the input side of the circuit of Fig. 23A is applied with signals RA, RB, and RC all being 5 V outputted from a pre-decoder to which an address is inputted. The circuit of Fig. 23A operates as illustrated to output -10 V as an output WL. The operation of the circuit of Fig. 23A is well known by those skilled in the art, so the detailed description thereof is omitted. Fig. 23B shows a circuit which generates a potential of 5 V to be applied to a non-selected word line during the erase operation. A NAND gate at the input side is applied with three signals RA, RB, and RC, at least one of which is 0 V. The circuit of Fig. 23B operates as illustrated to output 5 V as an output WL. Fig. 24A shows a circuit which generates a potential of 12 V to be applied to a selected word line during the program operation. A NAND gate at the input side is applied with signals all being 5 V. The circuit of Fig. 24A operates as illustrated to output 12 V as an output WL. Fig. 24B shows a circuit which generates a potential of 0 V to be applied to a non-selected word line during the program operation. A NAND gate at the input side is applied with three signals RA, RB, and RC, at least one of which is 0 V. The circuit of Fig. 24B operates as illustrated to output 0 V as an output WL. Fig. 25 shows a circuit which generates a potential of 5 V to be applied to a selected word line during the read operation. A NAND gate at the input side is applied with signals RA, RB, and RC all being 5 V. The circuit of Fig. 25 operates as illustrated to output 5 V as an output WL. Figs. 26A and 26B show examples of the negative bias circuit NBC. Fig. 26A shows a circuit which generates - 10 V as an output VMS during the erase operation. Specifically, during the erase operation, clocks OSC oscillating between 0 and 5 V as shown is applied to a transistor T1, and an erase signal (5 V) is applied to a transistor T2. As a result, an oscillation signal 0 to 12 V as shown appears at a node n1. This oscillation signal is inputted to a pump circuit PC1 at the next stage which then starts operating. An oscillation signal 0 to (-12 V) as shown appears at a node n2 of the pump circuit PC1. To one input terminal of a NAND gate, clocks OSC oscillating between 0 and 5 V as shown are inputted, and to the other input terminal, a non-erase signal (0 V) is inputted. As a result, 0 V appears at a node n4. Therefore, another pump circuit PC2 does not operate. 5 V appears at a node n7 and so a transistor T3 turns off. Accordingly, -10 V is obtained at a node n3 at the output side of the pump circuit PC1 as the output VMS. Fig. 26B is a circuit which generates 0 V as the VMS during the operations other than the erase operation. In such a mode, the circuit operates in the manner different from that shown in Fig. 26A in that an erase signal (0 V) is inputted to a transistor T2, and a non-erase signal (5 V) is inputted to the input terminal of a NAND gate. In this mode, a voltage lowering pump circuit PC1 does not operate. An oscillation signal oscillating between 0 and 5 V as shown appears at a node n5. A pump circuit PC2 therefore starts operating. An oscillation signal oscillating between 0 and (-5 V) appears at a node n6 in the pump circuit PC2. At a node n7 at the output side of the pump circuit PC2, there appears an oscillation signal oscillating between (-2 V) and (-3 V). As a result, a transistor T3 turns on and a node n3 outputs 0 V as a VMS. Fig. 27 shows an example of the source bias circuit SBC. An output V s takes 5 V only during the erase operation, and takes 0 V during the program and read operations. As a means for suppressing a peak current flowing through word lines, data lines, and source lines, during charge/discharge, there is a method of dividing the cell array as described previously to thereby reduce the capacities of word lines, data lines, and source lines. Fig. 28 is a diagram for realizing such a method. In this example, a cell array is divided into eight cell array units SAU1 to SAU8. Each cell array unit SAUi is divided into n blocks BLK1 to BLKn. In Fig. 28, RD represents a row decoder, and CG represents a column decoder. In the memory device shown in Fig. 28, one of the eight cell array units is selected to drive word lines, source lines, and data lines in only the selected unit. In this manner, power required for charge/discharge can be reduced. As an alternative means, there is a method of reducing the current drive capabilities of transistors for charging/discharging word lines and source lines, to thereby reduce a charge/discharge current and suppressing a peak current.

Claims: A non-volatile semiconductor memory having a plurality of non-volatile memory cells each having a control gate, a floating gate, a source and a drain, comprising: a) a memory cell array comprising said plurality of memory cells disposed in a matrix form, the control gates of a plurality of memory cells on the same row being connected to the same word line (WL), a plurality of drains of a plurality of memory cells on the same column being connected to the same data line (DL), and a plurality of sources of a plurality of memory cells being connected to a common erase line; b) a row decoder (RD) connected to said plurality of word lines (WL) for activating a desired one of said plurality of word lines (WL); c) a column gate (CG) connected to said plurality of data lines (DL) for activating a desired one of said plurality of data lines (DL); d) source biasing means (SBC) for applying a source potential to equalize said data lines (DL), prior to selection of a memory cell and non selection of other memory cells during an erase mode; characterized in that e) data in each memory cell are erasable by applying a negative voltage to the control gate (CG) of said memory cell; f) switching means (TEQ) connect said common erase line (SL) to a plurality of data lines (DL); and g) the sourse biasing means (SBC) serves also for applying a positive source potential to said common erase line (SL) connected to a plurality of memory cells and turning on said switching means (TEQ) to equalize said common erase line (SL), prior to selection of a memory cell and non selection of other memory cells during an erase mode. A non-volatile semiconductor memory according to claim 1, characterized in that said source biasing means (SBC) is arranged to control turn on of said switching means (TEQ) for connecting together a plurality of sources and drains of a plurality of memory cells, during said erase mode prior to lowering the potentials of said control gates of memory cells to be erased and prior to raising the potential of said control gates of memory cells not selected, to thereby equalize said sources and drains, and is also arranged to control stopping of the application of said source potential outputted from said source biasing means after the erase operation after raising the potentials of said control gates of said selected memory cells and after lowering the potentials of said control gates of said non-selected memory cells. A non-volatile semiconductor memory according to claim 2, characterized in that said source biasing means (SBC) is arranged to control turn off of said switching means (TEQ) after stopping the application of said source potential. A non-volatile semiconductor memory according to claim 1, characterized in that said source biasing means (SBC) is arranged to control turn on of said switching means (TEQ) for connecting together a plurality of sources and drains of a plurality of memory cells to equalize said sources and drains, and is also arranged to control stopping of the application of said source potential outputted from said source biasing means. A non-volatile semiconductor memory according to claim 4, characterized in that said source biasing means (SBC) is arranged to control turn off of said switching means (TEQ).

Inventors: ASANO MASAMICHI, MIYAKAWA TADASHI, ASANO, MASAMICHI, MIYAKAWA, TADASHI
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: G11C16
IPC codes: G11C16