A system for inserting a synchronizing pattern in digital audio data on an optical disk

Abstract: A system for inserting a synchronizing pattern in digital voice data on an optical disk comprising a synchronizing pattern input controller for generating the synchronizing pattern in accordance with a synchronizing pattern insert signal outputted from a microprocessor to control the serial data and the beat clock from the optical disk digital signal processor and indicate that inserting the synchronizing pattern has been completed. The synchronizing pattern input controller includes a clock generator, a timing controller, a counting unit, a synchronizing pattern generator, a control signal generator, and a switching unit. Therefore, the data having no synchronizing pattern such as the digital voice data loaded on the optical disk, which is outputted from the optical disk digital signal processor, can be normally inputted to the optical disk ROM decoder by the synchronizing pattern generated externally. Also, the synchronizing pattern can be inputted to the optical disk ROM decoder before the serial data stream is outputted from the optical disk digital signal processor.

Description: The present invention relates to an optical disk reproducing apparatus, more particularly, to a system for inserting a synchronizing pattern in a serial digital audio signal reproduced from an optical disk. In this way a signal having no synchronizing pattern such as a digital audio signal loaded on the optical disk, which is outputted from a digital signal processor, can be inputted to an optical disk ROM decoder by the synchronizing pattern generated externally. In a conventional optical disk reproducing apparatus, an optical disk digital signal processor processes a digital audio signal on the optical disk read from a disk pickup and outputs predetermined data in serial format to an optical disk ROM decoder which then inputs the serial data, only after it detects 12 bytes of synchronizing patterns FF, OO, FF, FF, FF, FF, FF, FF, FF, FF, OO, FF in the serial data. The data cannot be input to the optical disk ROM decoder in an appropriate timing, if the digital signal data format on the optical disk does not include this synchronizing pattern. Therefore, an object of the present invention is to provide a system for inserting a synchronizing pattern in a digital audio signal read from an optical disk, whereby the synchronizing pattern can be inputted to an optical disk ROM decoder before a serial data stream is outputted from an optical disk digital signal processor. In accordance with the present invention, there is provided a system according to claim 1. The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Fig. 1 is a view showing an arrangement of a system for inserting a synchronizing pattern in digital audio data on an optical disk in accordance with the present invention; Fig. 2 is a schematic circuit diagram of a synchronizing pattern input controller shown in Fig. 1; and Figs. 3A to 3C are views showing output waveforms of an optical disk digital signal processor. Fig. 1 is a view showing an arrangement of a system for inserting a synchronizing pattern in a digital audio signal read from an optical disk in accordance with the present invention. As shown in the drawing, the system of the present invention comprises an optical disk digital signal processor 1 for inputting digital audio data CD-DA read from the optical disk, outputted from a disk pickup and for processing the input digital audio data to output a serial data SD, a bit clock BCK, a sync signal SCOR, and a channel clock defining the left and right audio channels, hereinafter called the left and right clock LRCK; a synchronizing pattern input controller 2 for inputting the serial data SD, the bit clock BCK, the sync signal SCOR, and the left and right clock LRCK outputted from the optical disk digital signal processor 1 and for generating a synchronizing pattern in accordance with a synchronizing pattern insert signal SIC outputted from a microprocessor 4 to control the serial data SD and the bit clock BCK and indicate that insertion of the synchronizing pattern is completed; and an optical disk ROM decoder 3 for detecting 12 bytes of synchronizing pattern FF, OO, FF, FF, FF, FF, FF, FF, FF, FF, OO, FF generated from the synchronizing pattern input controller 2 to decode the serial data SD and the bit clock BCK. Fig. 2 is a schematic circuit diagram of the synchronizing pattern input controller 2 shown in Fig. 1. As shown in the drawing, the synchronizing pattern input controller 2 comprises a clock generator 2b including an integrator IC1 and an exclusive OR gate XOR1, for inputting the left and right clock LRCK signal outputted from the optical disk digital signal processor 1 to generate a clock signal in a desired timing; an AND gate AND4 for ANDing a reset signal RESET and the synchronizing pattern insert signal SIC from the microprocessor 4 to generate a clear signal; a counting unit 2a including a counter IC3, AND gates AND2 and AND3, inverter gates I1 and I8, and an integrator IC2, for counting 12 bytes of bit clock BCK outputted from the optical disk digital signal processor 1 in accordance with the level of clear signal from the AND gate AND4 and the level of clock signal from the clock generator 2b; an OR gate OR1 for ORing the output from the clock generator 2b and the output from the counting unit 2a to generate a clock signal; a timing controller 2c including a flip-flop FF1, an inverter gate I2 and an AND gate AND1, for inputting the sync signal SCOR from the optical disk digital signal processor 1 and the clear signal from the AND gate AND4 to produce a first synchronization; a synchronizing pattern generator 2d including a counter IC4, inverter gates I3 and I4, AND gates AND7 and AND8, and OR gate OR2, for generating 12 bytes of synchronizing pattern in accordance with the level of clear signal from the timing controller 2c and the level of clock signal from the OR gate OR1; a control signal generator 2e including inverter gates I6 and I7, AND gates AND5 and AND6, and a flip-flop FF2, for inputting count signal from the synchronizing pattern generator 2d, count signal from the counting unit 2a, and clear signal from the AND gate AND4 to generate a control signal and a synchronizing pattern end signal SIE; and a switching unit 2f including an inverter gate I5, an OR gate OR3, an AND gate AND9, and buffers B1 and B2, for being enabled or disabled in accordance with the control signal and the synchronizing pattern end signal SIE from the control signal generator 2e and the synchronizing pattern insert signal SIC from the microprocessor 4 to select the serial data SD from the digital signal processor 1 and the synchronizing pattern from the synchronizing pattern generator 2d. Now, the operation of the system of the present invention configured as stated previously will be described in detail with reference to Fig. 3. When the power is turned on and the reset signal RESET is applied, the optical disk digital signal processor 1 reads digital audio data CD-DA on the optical disk outputted from the disk pickup and processes the read digital audio data to apply the beat clock BCK, the left and right clock LRCK, the serial data SD and the sync signal SCOR as shown in Figs. 3A to 3C to the switching unit 2f, the counting unit 2a, the clock generator 2b and the timing controller 2c, respectively. At this time, the synchronizing pattern insert signal SIC being maintained at an inactive L state is applied from the microprocessor 4 via the and gate AND4 to clear terminal CLR of the flip-flop FF1 in the timing controller 2c and clear terminal CLR of the flip-flop FF2 in the control signal generator 2e for clearing. Also, the synchronizing pattern insert signal SIC at the inactive L state is applied from the microprocessor 4 via the AND gate AND4 to clear terminal CLR of the counter IC3 in the counting unit 2a and clear terminal CLR of the counter IC4 in the synchronizing pattern generator 2d for clearing. As a result, while the buffer B1 in the switching unit 2f is enabled at an initial state, the buffer B2 in the switching unit 2f is disabled at the initial state. Consequently, the serial data SD from the optical disk digital signal processor 1 along with the bit clock BCK can not be inputted to the optical disk ROM decoder 3 through the buffer B1 in an appropriate timing. Thereafter, the synchronizing pattern insert signal SIC being maintained at an active high H state is applied from the microprocessor 4 via the AND gate AND4 in the synchronizing pattern input controller 2 to clear terminal CLR of the flip-flop FF1 in the timing controller 2c, clear terminal CLR of the flip-flop FF2 in the control signal generator 2e and one input terminal of AND gate AND3 in the counting means 2a. On the other hand, while a high H pulse of the left and right clock LRCK is applied from the optical disk digital signal processor 1 to one input terminal of the exclusive OR gate XOR1, a low L pulse thereof is applied from the optical disk digital signal processor 1 via the integrator IC1 to the other input terminal of the exclusive OR gate XOR1, as shown in Fig. 3B. As a result, the high H pulse is outputted from the exclusive OR gate XOR1 in a moment (for a predetermined period of time that a capacitor of the integrator IC1 is to be charged with a current corresponding to the left and right clock LRCK), and then the low L pulse continues to be outputted from the exclusive OR gate XOR1. The high H pulse outputted from the exclusive OR gate XOR1 is inverted into the low L pulse by the inverter gate I1, so that the inverted low L pulse is applied to other input terminal of the AND gate AND3. On the other hand, the sync signal SCOR outputted from the optical disk digital signal processor 1 is inverted into the high H pulse by the inverter gate I2, so that the inverted high H pulse is applied to clock terminal CLK of the flip-flop FF1. consequently, the high H pulse can be applied from output terminal Q of flip-flop FF1 to one input terminal of the AND gate AND1 and another input terminal of the AND gate AND3 in the counting unit 2a. On the other hand, data bytes "O,O,O,O,O" outputted from output terminals Q0-Q4 of the counter IC3 are ANDed by the AND gate AND2, and then are inverted into a high H pulse by inverter gate I8 through the integrator IC2, so that the inverted high H pulse is applied to another input terminal of the AND gate AND3. In result, the low L pulse outputted from the AND gate AND3 in counting unit 2a can be applied to clear terminal CLR of the counter IC3. Therefore, data bytes "O,O,O,O,O" are outputted from output terminals Q0-Q4 of the counter IC3 since the counter IC3 can be cleared for the 16th clock period of the beat clock BCK output from the optical disk digital signal processor 1 as shown in Fig. 3A. Then, the output data bytes are ANDed by the AND gate AND2, and then are applied to clock terminal CLK of the counter IC4 in the synchronizing pattern generator 2d through the OR gate OR1. On the other hand, the high H pulse outputted from output terminal Q of the flip-flop FF1 in the timing controller 2c and the high H pulse outputted from the AND gate AND4 are applied to clear terminal CLR of the counter IC4 as a high H pulse ANDed by the AND gate AND1 in the timing controller 2c. Consequently, 1 byte of the bit clock BCK can be counted by the counter IC4 in the synchronizing pattern generator 2d, and then data bytes 1,O,O,O can be outputted from output terminals Q0-Q3 of the counter IC4. At this time, the low L pulse outputted from output terminal Q1 of the counter IC4 is inverted into the high H pulse by the inverter gate I3, so that the inverted high H pulse along with the high H pulse outputted from output terminal Q0 is applied to one input terminal of the AND gate AND8 through the OR gate 0R2. Also, signals outputted from terminals Q0, Q1 and Q3 of the counter IC4 are inverted into a high H pulse signal by the inverter gate I4 through the AND gate AND7, so that the inverted high H pulse is applied to the other input terminal of the AND gate AND8. Thus, the high H pulse is outputted from the AND gate AND8 to be applied to input terminal of the buffer B2. On the other hand, the low L pulse is outputted from output terminals Q0-Q3 of the counter IC4 in the synchronizing pattern generator 2d through inverter gates 16 and 17 and AND gates AND5 and AND6 to be applied to clock terminal CLK of the flip-flop FF2 in the control signal generator 2e. Also, the high H pulse is outputted from the AND gate AND4 to which the synchronizing pattern insert signal SIC is inputted, so that it is applied to clear terminal CLR of the flip-flop FF2. As a result, the low L pulse is outputted from output terminal Q of the flip-flop FF2 to be applied to the OR gate OR3 to which the synchronizing pattern insert signal SIC is applied through the inverter gate I5. Thus, the low L pulse is applied to control terminal of buffer B2 in the switching unit 2f via the OR gate OR3, so that it enables the buffer B2. Therefore, 1 byte of synchronizing pattern signal "1" outputted from the synchronizing pattern generator 2d can be applied to the optical disk ROM decoder 3 via the buffer B2. Thereafter, a second synchronizing pattern signal can be applied to the optical disk ROM decoder 3. Namely, the counter IC3 outputs data bytes 1,O,O,1,1 at output terminals Q0-Q4 thereof at the 25th leading edge of the bit clock BCK after it counts from the 17th leading edge of the bit clock BCK just next to edge of the left and right clock LRCK to the 24th leading edge of the beat clock BCK. If a second clock from the optical disk digital signal processor 1 is applied to clock terminal CLK of the counter IC4 through the associated AND gate AND2 and OR gate OR1, data bytes O,1,O,O are outputted from output terminals Q0-Q3 to be applied to the AND gate AND8. .As a result, the AND gate AND8 outputs the low L pulse causing a second byte "O" to be applied to the optical disk ROM decoder 3 via the enabled buffer B2 in the switching unit 2f. When these procedures proceed until the edge of the left and right clock LRCK is generated 6 times, a 12th byte of the last synchronizing pattern is outputted, so that it can be applied to the optical disk ROM decoder 3. Namely, the 12th synchronizing pattern can be applied to the optical disk ROM decoder 3. In other words, the counter IC3 outputs data bytes 1,O,O,1,1 at output terminals Q0-Q4 thereof at the 25th leading edge of the bit clock BCK after it counts from the 17th leading edge of the bit clock BCK just next to edge of the left and right clock LRCK to the 24th leading edge of the beat clock BCK. If a 12th clock from the optical disk digital signal processor 1 is applied to clock terminal CLK of the counter IC4 through the associated AND gate AND2 and OR gate OR1, data bytes O,1,O,O are outputted from output terminals Q0-Q3 to be applied to the AND gate AND8. As a result, the AND gate AND8 outputs-the high H pulse causing the 12th byte "1" to be applied to the optical disk ROM decoder 3 via the enabled buffer B2 in the switching unit 2f. Also, data bytes O,O,1,1 outputted from output terminals Q0-Q3 of the counter IC4 are inverted by inverter gates I6 and I7 in the control signal generator 2e, and then are ANDed by the AND gate AND5. Thus, the high H pulse is outputted from the AND gate AND5 to be applied to one input terminal of the AND gate AND6. On the other hand, the high H pulse is outputted from output terminal Q3 of the counter IC3 to be applied to the other input terminal of the AND gate AND6. In result, the high H pulse is outputted from the AND gate AND6, so that it can be applied to clock terminal CLK of the flip-flop FF2. Therefore, the synchronizing pattern end signal SIE as the high H pulse is outputted from output terminal Q of the flip-flop FF2, so that it can inform the microprocessor 4 that inserting the synchronizing pattern has been completed. Also, this high H pulse is inputted to the OR gate OR3 to which the synchronizing pattern insert signal SIC is inputted, so that it can disable the buffer B2 in the switching unit 2f. Thus, the synchronizing pattern outputted from the synchronizing pattern generator 2d is blocked. On the other hand, the low L pulse outputted from output terminal Q of the flip-flop FF2 is applied to the AND gate AND9 along with the synchronizing pattern insert signal SIC in order to enable the buffer B1 in the switching unit 2f. As a result, the optical disk ROM decoder 3 inputs the serial data outputted from the optical disk digital signal processor 1, only after it detects 12 bytes of synchronizing pattern outputted from the synchronizing pattern generator 2d. While inserting the synchronizing pattern, data bytes 1,O,1,1,1,1,1,1,1,1,O,1 are outputted from the 4 bit counter. Thus, these data bytes can satisfy the synchronizing pattern "FF,OO,FF,FF,FF,FF,FF,FF,FF,FF,OO,FF". Also, a means adapted to output to the microprocessor 4 the result that the synchronizing pattern has been inserted may be used as a means informing that inserting the synchronizing pattern has been completed. As apparent from the above description, in accordance with the system of the present invention, data having no synchronizing pattern such as a digital voice signal loaded on the optical disk, which is outputted from the optical disk digital signal processor, can be normally inputted to the optical disk ROM decoder due to the synchronizing pattern generated externally. Also, the synchronizing pattern can be inputted to the optical disk ROM decoder before the serial data stream is outputted from the optical disk digital signal processor. Although preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope of the accompanying claims.

Claims: A system for inserting a synchronising pattern in the serial digital audio signal reproduced from an optical disk, said system comprising: a signal processor (1) for signal-processing digital audio data reproduced from the optical disk by a pick-up for outputting said serial digital audio signal (SD), a bit clock (BCK) defining a bit cell of the serial audio signal, a sync-signal (SCOR) , and a left and right clock (LRCK) defining the left and right audio channels; a synchronizing pattern input control unit (2) controlled in synchronism with the sync signal and the clocks supplied by the signal processor signal and comprising a synchronizing pattern generator (2d) for generating a 12 byte synchronizing pattern in response to an insert signal (SIC) output from a microprocessor (4), a switching unit (2f) for selecting either the serial audio signal or the synchronization pattern and means (FF2) for generating a signal (SIE) indicating that inserting of the synchronizing pattern has been completed; and an optical disk ROM decoder (3) receiving the output signal from said switching means and the bit clock (BCK) to decode the serial audio signal. The system as claimed in claim 1, wherein said synchronizing pattern input control unit (2) comprises a clock generator (2b) for detecting a timing of the left and right clock inputted from said signal processor (1) to generate a clock in a desired timing; an AND gate (AND4) for ANDing a reset signal and the synchronized pattern insert signal from said microprocessor; a counting unit for counting 12 bytes of bit clock inputted from said signal processor in accordance with an output from said AND gate (AND4) and a clock pulse from said clock generator; an OR gate (OR1) for ORing an output from said clock generator and an output from said counting unit; a timing controller for inputting the sync signal from said optical disk digital signal processor and an output from said AND gate (AND4) to produce a first synchronization; the synchronizing pattern generator (2d for generating 12 bytes of synchronizing pattern in accordance with an output from said timing controller and an output from said OR gate (OR1); a control signal generator (2e) for inputting an output from said synchronizing pattern generator, an output from said counting unit and an output from said AND gate (AND4) to output an enable/disable signal and a synchronizing pattern end signal; and a switching unit (2f) enabled and disabled in accordance with an output from said control signal generator and the synchronizing pattern insert signal from said microprocessor to select the serial data from said digital signal processor and the synchronizing pattern from said synchronizing pattern generator. The system as claimed in claim 2, wherein said clock generator (2b) includes an integrator (IC1) and an exclusive OR gate (XOR1) for XORing the left and right clock inputted directly and via said integrator (IC1) from said optical disk digital signal processor to generate the clock. The system as claimed in claim 2, wherein said timing controller (2c) includes an inverter gate (I2) for inverting the sync signal from said optical disk digital signal processor, a flip-flop (FF1) for inputting an output from said inverter gate (I2) at a clock terminal thereof and an output from said AND gate (AND4) at a clear terminal thereof, and an AND gate (AND1) for ANDing the output from said flip-flop (FF1) and the output from said AND gate (AND4). The system as claimed in claim 2, wherein said counting unit includes an integrator (IC2), an inverter gate (I8) for inverting an output from said integrator (IC2), an inverter gate (I1) for inverting an output from said clock generator, an AND gate (AND3) for ANDing an output from said flip-flop (FF1), an output from said AND gate (AND4) and an output from said inverter gate (I1), a counter (IC3) for inputting an output from said AND gate (AND3) at a clear terminal thereof and the bit clock from said optical disk digital signal processor at a clock terminal thereof, an AND gate (AND2) for applying outputs (Q0 and Q4) from said counter (IC3) to an input of said AND gate (AND3) via said integrator (IC2) and inverter gate (I8) to count the bit clock. The system as claimed in claim 2, wherein said synchronizing pattern generator (2d) includes an AND gate (AND7), an inverter gate (I4) for inverting an output from said AND gate (AND7), a counter (IC4) for inputting an output from said timing controller at a clear terminal thereof and an output from said OR gate (OR1) at a clock terminal thereof, an inverter gate (I3) for inverting an output (Q1) from said counter (IC4), an OR gate (OR2) for ORing other outputs (Q0, Q2 and Q3) from said counter (IC4) and an output from said inverter gate (13), and an AND gate (AND8) for ANDing an output from said OR gate (OR2) and an output from said inverter gate (I4) to generate 12 bytes of synchronizing pattern. The system as claimed in claim 2, wherein said control signal generator includes inverter gates (I6 and I7) for inverting outputs (Q0 and Q1) from said counter (IC4) respectively, an AND gate (AND5) for ANDing outputs from said inverter gates and outputs from said counter (IC4), an AND gate (AND6) for ANDing the output from said AND gate (AND5) and the output from said counter (IC3), and a flip-flop (FF2) for inputting the output from said AND gate (AND6) at the clock terminal thereof and the output from AND gate (AND4) at the clear terminal to output the enable signal and the synchronizing pattern end signal. The system as claimed in claim 2, wherein said switching unit (2f) includes an inverter gate (I5), an AND gate (AND9) for ANDing the output (Q) from said flip-flop (FF2) and the synchronizing pattern signal, an OR gate (OR3) for ORing the output (Q) from said flip-flop (FF2) and the synchronizing pattern signal inverted by said inverter gate (I5), and buffers (B1 and B2) being enabled respectively by outputs from said AND gate (AND9) and OR gate (OR3) to select the serial data from said optical disk digital signal processor and the synchronizing pattern from said synchronizing pattern generator (2d).

Inventors: KIM DAE YOUNG, KIM, DAE YOUNG
Applicants: LG ELECTRONICS INC, LG ELECTRONICS INC.
Application year: 1991
Main classification: G11B20
IPC codes: G11B27, G11B20