Field effect device with polycrystaline silicon channel

Abstract: A CMOS SRAM cell has a polycrystalline silicon signal line between a common node, which is the data storage node, and the power supply. A field effect device is fabricated within this polycrystalline silicon signal line. The channel of the field effect device is separated from an active area in the substrate by a thin gate dielectric, and the active region within the substrate functions as the control gate for the field effect device. Such a device can be used to provide polycrystalline silicon P-channel transistors for use in CMOS SRAM cells.

Description: The present invention relates generally to integrated circuit devices, and more specifically to a field effect device having a polycrystalline silicon channel. CMOS static random access memories (SRAM) are increasingly used in the electronics, industry due to their combination of speed, low power, and no requirement for refresh. A CMOS SRAM cell is built around a cross-coupled latch and accessed by, typically, 2 control gates for a standard SRAM cell. Four control gates are used to access the cell for 1-port memory devices. The basic SRAM cell can be formed using cross-coupled CMOS inverters, having 2 each N-channel and P-channel transistors. To conserve physical layout space, the P-channel transistors are often replaced with resistive loads. Typical loads include a polycrystalline silicon resistor, and 2 back-to-back polycrystalline silicon diodes. An example of the latter is described in granted US Patent US-A-5,196,233, filed January 18, 1989, titled METHOD FOR FABRICATING SEMICONDUCTOR CIRCUITS. US-A-5 196 233 describes a method for fabricating a resistive load element for a semiconductor device that can be used with standard semiconductor processes. A layer of second level poly is deposited and lightly doped P-type. A resist mask is used to dope selected regions of the poly layer N-type. The poly layer is then patterned to define conductors and resistive load elements. The resistive load elements are formed by back-to-back PN diodes formed at the interfaces between the P-type and N-type regions. Resistive loads of either type are formed to have a very high resistance in order to reduce power consumption by the cell. EP-A-0 104 616 was published on 4 April 1984 and describes a memory cell in which two switching transistors of a first channel type are arranged on a semiconductor body, each connected to a supply voltage via a load device of the second channel type. The object is to achieve an area-saving design of the memory cell. This is achieved by each load device being composed of heavily doped sections of a layer of polycrystalline silicon applied in an insulated fashion to the semiconductor body and also of a lightly doped or undoped part of the layer situated between said sections. This layer forms a channel region. Beneath the layer there is an undoped region of the semiconductor body which acts as gate region. EP-A-0 392 540 was published on 17 October 1990, but was filed on 14 April 1989 thus is regarded as prior art according to Article 54(3) of the EPC for the states of the United Kingdom, Germany and France. This document describes a static memory in which polysilicon thin film transistors (TFTs) serve as load elements in a memory cell and the gate electrodes of these transistors are formed of diffusion regions. In the static memory, high-quality uniform TFTs are formed, and the oxidation films of the TFTs can be thin, without using a complex manufacturing technique. Use of a P-channel transistor as the load for the SRAM cell results in a cell having better electrical characteristics. Such cells are faster than those using resistive loads, since the P-channel transistors can provide a higher drive current than high resistance devices. Also, use of P-channel transistors gives higher immunity to soft errors, such as those caused by alpha particle impacts and noise. The primary disadvantage of SRAM cells incorporating P-channel load transistors is that the layout area for each cell is significantly larger than those using resistive loads. This reduces device density and increases chip costs. It would be desirable to provide an SRAM cell which combined the advantages of P-channel loads with the cell layout area requirements of resistive load cells. It would be further desirable to provide a field effect device loads, suitable for use with an SRAM cell, which provides increased current drive over resistive loads, and which provides a high OFF resistance. This application is divided from EPO 91304676.9. According to one aspect of the present invention there is provided an integrated circuit, comprising: first and second active regions in a substrate, the active regions having a first conductivity type; a first field effect device in the substrate, said field effect device having source/drain regions of a first conductivity type in said first active region opposite a gate electrode formed from a first polycrystalline silicon layer and a channel under the gate electrode within the substrate; gate dielectric over said active region and underlying said gate electrode; a second polycrystalline silicon layer over said gate dielectric, said second polycrystalline silicon layer patterned to form the channel of a second field effect device; source/drain regions having a second conductivity type in said second polycrystalline silicon layer on opposite sides of said second active region, wherein a channel is formed between said source/drain regions over said second active region, and wherein said second active region functions as a control gate for the second field effect device; and a contact region of the first conductivity type in said second polycrystalline silicon layer in contact with said first active region, wherein an electrical connection is formed between one of the source/drain regions of the first field effect device and one of the source/drain regions of the second field effect device, said contact region being of a first conductivity type wherein a lateral junction is formed between said contact region and the source/drain region nearest said contact region within said second polycrystalline silicon layer, said lateral junction forming a diode; characterised in that the gate electrode of the first field effect device is electrically connected to the control gate of the second field effect device whereby the first and second field effect devices are connected to form an inverter and in that said second polycrystalline silicon layer is distinct from said first polycrystalline silicon layer. Therefore, according to an embodiment of the present invention, a CMOS SRAM cell has a polycrystalline silicon signal line between a common node, which is the date storage node, and the power supply. A field effect device is fabricated within this polycrystalline silicon signal line. The channel of the field effect device is separated from an active area in the substrate by a thin gate dielectric, and the active region within the substrate functions as the control gate for the field effect device. Such a device can be used to provide polycrystalline silicon P-channel transistors for use in CMOS SRAM cells. For a better understanding of the present invention and to show how the same may be carried into effect, reference will now be made by way of example to the accompanying drawings, in which: Figures 1-4 illustrate fabrication of a polycrystalline silicon field effect device according to the present invention; Figure 5 is a plan view showing the layout of a CMOS SRAM cell utilizing a polycrystalline silicon field effect device according to the present invention; Figure 6 is a schematic diagram of the SRAM cell of Figure 5. The process steps and structures described below do not form a complete process flow for manufacturing integrated circuits. The present invention can be practiced in conjunction with integrated circuit fabrication techniques currently used in the art, and only so much of the commonly practiced process steps are included as are necessary for an understanding of the present invention. The figures representing cross-sections of portions of an integrated circuit during fabrication are not drawn to scale, but instead are drawn so as to illustrate the important features of the invention. Referring to Figure 1 , a cross-section of a portion of a CMOS SRAM cell is shown as being fabricated in a P-type substrate 10. Field oxide regions 12, 14 separate active regions of the device. Active region 16 is located between field oxide regions 12, 14, and forms a common source/drain region for 2 field effect transistors (not shown). Active region 18, although shown as separated into 2 parts, is actually a single active region as will be shown in connection with Figure 5. Polycrystalline silicon gate line 20 is formed over a thin gate oxide layer 22 as known in the art. Sidewall spacers 24 are formed using an anisotropic etch as known in the art, causing the formation of lightly doped drain (LDD) regions 26. Although polycrystalline silicon line 20 appears to function as the gate of a field effect device in the cross sectional view of Figure 1, it will actually become the location of a shared contact region to be described below. The impurity doping profiles in the region of the polycrystalline silicon line 20 are the same as those for an actual transistor, but this is merely an artifact of the fabrication process as known in the art. Active regions 18 are connected other than in the plane of the cross section of Figure 1, and direct electrical contact will be made between the polycrystalline silicon signal line 20 and the underlying active region 18 as will be further described below. To this point, standard fabrication techniques for a CMOS SRAM are used. Variations from the standard process flows will now be performed in order to fabricate a polycrystalline silicon field effect device according to the present invention. A thin oxide layer 28 is deposited over the surface of the device, preferably using Plasma Enhanced Chemical Vapor Deposition (PECVD). This allows formation of a good quality oxide layer at relatively low temperatures, between 400°C and 700°C. Layer 28 is preferably deposited to a thickness of approximately 500 angstroms, followed by a densification step performed by heating the device to a temperature of preferably above 850°C. This densification step, in addition to improving the quality of the oxide layer 28, is also preferably used to anneal and activate the N + and P + implants in the active areas of the device. The oxide layer 28 will be used as a dielectric for a field effect device, so the quality of oxide layer 28 is important. Referring to Figure 2, a shared contact region 30 is formed in the oxide layer 28 with a mask and etch step, followed by the deposition of an undoped polycrystalline silicon layer 32 to a depth of approximately 2000 angstroms. A mask is then used to define the shared contact region, and an N + implant is made to form region 34. This N + region within the polycrystalline silicon layer 32 makes good electrical contact with both the active region 18 and the polycrystalline silicon signal line 20. The N + implant area is larger than the actual shared contact region 30 and preferably extends part way onto the field oxide region 12. Referring to Figure 3, a P + implant mask is then made, followed by a P + step to form regions 36 and 38. Region 38 forms one source/drain region of the polycrystalline silicon transistor, and the V cc interconnect lines. P + region 36 forms the other source/drain region of the polycrystalline silicon transistor, and also forms a diode at its interface 40 with N + region 34. Preferably, the layout of the photomasks causes the implanted N + and P + regions 34, 36, to overlap slightly, to insure diode formation at the resulting interface 40. N - channel region 42 is then formed by means of a blanket N - implant over the surface of the device. This implant need not be masked, since its doping level is relatively light compared to that of the N + and P + regions 34, 38, 40. Region 42 forms the conductive channel of the polycrystalline silicon P-channel transistor for which the P + regions 36, 38 are the source and drain. After all implants have been made into the second polycrystalline silicon layer 32, a masking and etch step is performed to define the polycrystalline silicon transistors, the shared contact regions, and the V cc interconnect lines. It is preferable to make all implants into the second layer of polycrystalline silicon before patterning such layer so that the polycrystalline silicon layer can be used to protect underlying areas of the device. The order in which the N + , P + , and N - implants are made is not important. Although these implants have been described above as being performed in the order N + , P + , N - , they could just as easily have been made in the order N - , N + , P + , or any other desired order. As described above, it is not necessary to use a mask for the N - implant. Referring to Figure 4 , once the second layer of polycrystalline silicon has been patterned, a thick oxide layer 44 is then formed over the surface of the chip. Oxide layer 44 is preferably formed from a deposited undoped oxide layer to a thickness of approximately 2000 angstroms, and a PSG or BPSG layer to a thickness of approximately 6000 angstroms. Insulating layer 44 may then be subjected to reflow in order to smooth its contours prior to metal deposition. After formation of insulating layer 44 is complete, a metal layer is deposited in patterned to form signal lines 46. The remainder of the processing steps for the device are conventional. Figure 5 shows a preferred layout for a CMOS SRAM cell which utilizes the P-channel polycrystalline silicon transistors fabricated as designed above for use as load devices. Further details of such SRAM cell layout are described in the co-pending, related reference which has been incorporated hereinto as described above. In addition to the first level polycrystalline silicon lines 20, word lines 48 are also formed from the first level polycrystalline silicon layer. Contact regions 50 are opened through the overlying insulating layer 44 to make contact with the various metal data signal lines. A metal device ground line makes contact with the SRAM cell through contact region 52. The cell layout shown in Figure 5 is an 8-T, dual-port SRAM cell. Each of the polycrystalline silicon lines 48 forms the gate for two N-channel transistors. Each of the signal lines 20 forms the gate for a signal N-channel transistor, and the active regions 16 act as gates for the two P-channel polycrystalline silicon devices having channels in regions 42. The P-channel devices are used as load devices between the shared contacts 30 and the V cc signal lines 38. A schematic diagram corresponding to the cell layout of Figure 5 is shown in Figure 6. N-channel transistors 60, 62 combine with polycrystalline silicon P-channel transistors 64, 66 to form the cross-coupled latch of the cell. N-channel transistors 68 and 70 are connected to the true and complement data write lines (DW) and (DWB) respectively. N-channel transistors 72 and 74 are connected to the true and complement data write signal lines (DR) and (DRB) respectively. Diodes 76 , 78 are those formed by the P-N interfaces 40, and connect to common nodes 80 , 82 , respectively. The common nodes 80 and 82 correspond to the active region 16 shown in Figures 1-4 and act as the gate regions for the P-channel transistors 66, 64. Transistors 68, 70 are gated by the word write signal line WW, and read transistors 72, 74 are controlled by the word read signal line WR. Lines WW and WR correspond to the polycrystalline word lines 48 shown in Figure 5. The lines DW, DR, DWB, DRB, and the ground connection are the metal signal lines which make contact to contact regions 50 and 52 of Figure 5. Operation of the 8-T SRAM cell of Figure 6 is conventional, and is readily apparent to those skilled in the art. It will apparent to those skilled in the art that the techniques described above can be used in many different situations. For example, the polycrystalline silicon P-channel loads can be used in single port 6-T cells as well as the dual-port 8-T cells described. Cell layouts other than that shown in Figure 5 may also be used. If desired, the gate oxide layer 28 can be grown instead of deposited, although this relatively high temperature step may not be desirable in some process flows. In addition, circuit designs other than SRAM cells may be able to make use of N-channel polycrystalline silicon transistors, and these can be fabricated using the described techniques simply by forming N + source/drain regions and a P - channel. The CMOS SRAM cell described above has several important advantages over prior art cells. The high value polycrystalline silicon resistor and back-to-back diode load devices limited current flow therethrough to approximately a few picoamps, limiting the overall speed of the device. The use of the polycrystalline silicon P-channel devices allows a load of a few hundred nanoamps to drive switching of the SRAM cell. The quality of the polycrystalline silicon transistors is not high compared to those formed in a monocrystalline silicon substrate, but their performance in an SRAM cell is significantly better than that of the previous high resistance load devices. Since the P-channel devices provide a high resistance when turned off, and a relatively low resistance when turned on, giving a lower impedance path to the power supply, the SRAM cell is more stable to noise and soft errors such as alpha particle impacts. The cell is faster due to the higher switching current, and works well with lower supply voltages. The particular layout described in connection with Figure 5 has the advantage that a relatively long, narrow P-channel device is formed. This gives a high OFF resistance desired for the reasons described above, while also providing a significantly lower ON resistance compared to resistive load devices. It should be appreciated that the above-described embodiment of the present invention provides a load for CMOS SRAM cells utilising P-channel transistors which can be fabricated in the same amount of chip area as resistive load cells. The FET device has a conductive channel in the polycrystalline silicon line.

Claims: Claims for the following Contracting States : FR, DE, GB An integrated circuit, comprising: first and second active regions (18,16) in a substrate (10), the active regions having a first conductivity type; a first field effect device (62) in the substrate (10), said field effect device having source/drain regions of a first conductivity type in said first active region (18) opposite a gate electrode (20) formed from a first polycrystalline silicon layer (20) and a channel under the gate electrode within the substrate (10); gate dielectric (28,22) over said active region and underlying said gate electrode (20); a second polycrystalline silicon layer (32) over said gate dielectric (28), said second polycrystalline silicon layer (32) patterned to form the channel (42) of a second field effect device (66); source/drain regions (36,38) having a second conductivity type in said second polycrystalline silicon layer (32) on opposite sides of said second active region (16), wherein a channel (42) is formed between said source/drain regions (36,38) over said second active region (16), and wherein said second active region (16) functions as a control gate for the second field effect device (66); and a contact region (34) of the first conductivity type in said second polycrystalline silicon layer (32) in contact with said first active region (18), wherein an electrical connection is formed between one of the source/drain regions of the first field effect device and one of the source/drain regions of the second field effect device, said contact region (34) being of a first conductivity type wherein a lateral junction is formed between said contact region (34) and the source/drain region (36) nearest said contact region (34) within said second polycrystalline silicon layer, said lateral junction (40) forming a diode (78); characterised in that the gate electrode of the first field effect device (62) is electrically connected to the control gate of the second field effect device (66) whereby the first and second field effect devices are connected to form an inverter and in that said second polycrystalline silicon layer is distinct from said first polycrystalline silicon layer. An integrated circuit according to claim 1, wherein the channel of the second field effect device is substantially longer than it is wide. An integrated circuit according to claim 1 or 2, wherein said first field effect device is a first N-channel field effect device, with n-type source/drain regions. An integrated circuit according to any one of claims 1 to 3, wherein said second field effect device is a first P-channel field effect device, with p-type source/drain regions. An integrated circuit according to claim 4, wherein said source/drain regions of the second polycrystalline silicon layer are highly p-type doped and the channel is lightly n-type doped. An integrated circuit according to claim 4 when dependent upon claim 3, further comprising: a second N-channel field effect device (62) having source/drain regions opposite a gate electrode (20) formed from the first layer of polysilicon (20) and a channel under the gate electrode within the substrate (10) ; a second P-channel field effect device (66) having source/drain regions (36,38) in said second polysilicon layer (32) wherein a channel (42) is formed between said source/drain regions opposite a gate electrode (16) comprised of the substrate; wherein a first source/drain region of the second N-channel field effect device (62) is common with a first source/drain region of the first N-channel field effect device (60), the second source/drain regions of the first and second N-channel field effect devices (60,62) act as the gate electrodes for the second and first P-channel field effect devices (64,66) respectively, the first source/drain regions (38) of the P-channel field effect devices connect to a power line and the second source/drain regions (36) of the first and second P-channel field effect devices respectively connect to the gates (20) of the second and first N-channel field effect devices and respectively connect to the second source/drain regions (18) of the first and second N-channel field effect devices to form a cross-coupled latch wherein the second N-channel field effect device (62) has a gate dielectric (22) underlying said first layer of polysilicon (20) which has the same physical characteristics as the gate dielectric (22) of the first N-channel field effect device and the second P-channel field effect device (66) has a gate oxide (28) underlying said second polysilicon layer (32) which has the same physical characteristics as the gate oxide (28) of the first P-channel field effect device (64). An integrated circuit according to any one of claims 1 to 6, wherein said gate dielectric layer is an oxide layer formed by chemical vapour deposition. An integrated circuit according to any one of claims 1 to 6, wherein said gate dielectric is a thermal oxide layer. Claims for the following Contracting State : IT An integrated circuit, comprising: first and second active regions (18,16) in a substrate (10), the active regions having a first conductivity type; a first field effect device (62) in the substrate (10), said field effect device having source/drain regions of a first conductivity type in said first active region (18) opposite a gate electrode (20) formed from a first polysilicon layer (20) and a channel under the gate electrode within the substrate (10); gate dielectric (28,22) over said active region and underlying said gate electrode (20); a second polycrystalline silicon layer (32) over said gate dielectric (28), said second polycrystalline silicon layer (32) patterned to form the channel (42) of a second field effect device (66); source/drain regions (36,38) having a second conductivity type in said second polycrystalline silicon layer (32) on opposite sides of said second active region (16), wherein a channel (42) is formed between said source/drain regions (36,38) over said second active region (16), and. wherein said second active region (16) functions as a control gate for the second field effect device (66); and a contact region in said second polysilicon layer (32) in contact with the first active region (18) wherein an electrical connection is formed between one of the source/drain regions of the first field effect device and one of the source/drain regions of the second field effect device; characterised in that the gate electrode of the first field effect device (62) is electrically connected to the control gate of the second field effect device (66) whereby the first and second field effect devices are connected to form an inverter and in that said second polycrystalline silicon layer is distinct from said first polycrystalline silicon layer. An integrated circuit according to claim 1, wherein the contact region (34) in said second polycrystalline silicon layer (32) in contact with the first active region (18) is of a first conductivity type wherein a lateral junction is formed between said contact region (34) and the source/drain region (36) nearest said contact region (34) within said second polycrystalline silicon layer, said lateral junction (40) forming a diode (78). An integrated circuit according to claim 2, wherein the channel of the second field effect device is substantially longer than it is wide. An integrated circuit according to claim 2 or 3, wherein said first field effect device is a first N-channel field effect device, with n-type source/drain regions. An integrated circuit according to any one of claims 1 to 4, wherein said second field effect device is a first P-channel field effect device, with p-type source/drain regions. An integrated circuit according to claim 5, wherein said source/drain regions of the second polycrystalline silicon layer are highly p-type doped and the channel is lightly n-type doped. An integrated circuit according to claim 5 when dependent upon claim 4, further comprising: a second N-channel field effect device (62) having source/drain regions opposite a gate electrode (20) formed from the first layer of polysilicon (20) and a channel under the gate electrode within the substrate (10); a second P-channel field effect device (66) having source/drain regions (36,38) in said second polysilicon layer (32) wherein a channel (42) is formed between said source/drain regions opposite a gate electrode (16) comprised of the substrate; wherein a first source/drain region of the second N-channel field effect device (62) is common with a first source/drain region of the first N-channel field effect device (60), the second source/drain regions of the first and second N-channel field effect devices (60,62) act as the gate electrodes for the second and first P-channel field effect devices (64,66) respectively, the first source/drain regions (38) of the P-channel field effect devices connect to a power line and the second source/drain regions (36) of the first and second P-channel field effect devices respectively connect to the gates (20) of the second and first N-channel field effect devices and respectively connect to the second source/drain regions (18) of the first and second N-channel field effect devices to form a cross-coupled latch wherein the second n-channel field effect device (62) has a gate dielectric (22) which has the same physical characteristics as the gate dielectric (22) of the first N-channel field effect device and the second P-channel field effect device (66) has a gate oxide (28) underlying said second polysilicon layer (32) which has the same physical characteristics as the gate oxide (28) of the first P-channel field effect device (64). An integrated circuit according to any one of claims 1 to 7, wherein said gate dielectric layer is an oxide layer formed by chemical vapour deposition. An integrated circuit according to any one of claims 1 to 7, wherein said gate dielectric is a thermal oxide layer.

Inventors: CHAN TSIU C, GURITZ ELMER, HAN YU-PIN, CHAN, TSIU C., GURITZ, ELMER, HAN, YU-PIN
Applicants: ST MICROELECTRONICS INC, STMICROELECTRONICS, INC.
Application year: 1991
Main classification: H01L27
IPC codes: H01L21, H01L27