Semiconductor memory cell

Abstract: Disclosed is a semiconductor memory cell comprising a word line (WL), a pair of bit lines (BL AND BL ) crossing the word line (WL), a resistance (R1) of which the one side is connected to a high power source (VDD) and the other side to a first connecting node (M1), a first FET (FET1) connected between the first connecting node (M1) and a low power source (VSS) and of which the gate is connected to a second connecting node (M2), a second FET (FET2) connected between the second connecting node (M2) and the low power source (VSS) and of which the gate is connected to the first connecting node (M1), a third FET (FET3) connected between the first connecting node (M1) and one of the pair of bit lines (BL) and of which the gate is connected to the word line (WL) to control the operation of the third FET (FET3) by changing the potential of the word line (WL), and a fourth FET (FET4) connected between the second connecting node (M2) and the other of the pair of bit lines ( BL ) and of which the gate is connected to the word line (WL) to control the operation of the fourth FET (FET4) by changing the potential of the word line (WL).

Description: This invention relates to a semiconductor memory cell comprising: a word line; a pair of bit lines crossing the word line; a first resistance of which one side is connected to a high power source and the other side to a first connecting node; a second resistance of which one side is connected to a high power source and the cther side to a second connecting node; a first field effect transistor connected between the first connecting node and a low power source; a second field effect transistor connected between the second connecting node and the low power source; a third field effect transistor connected between the first connecting node and one of the pair of bit lines and the gate of which is connected to the word line to control the operation of the third field effect transistor by changing the potential of the word line; and a fourth field effect transistor connected between the second connecting node and the other of the pair of bit lines and the gate of which is connected to the word line to control the operation of the fourth field transistor by changing the potential of the word line. Such a memory cell is described in JP-A-55-160 392. Further such memory cells are described in JP-A-54-146 935 and JP-A-58-094 186. A gate array method as a design method or a development method for various kinds of custom LSIs is widely used because this gate array method has a short development period. In the gate array method, a plurality of basic cells are arranged regularly and secured to a chip. These basic cells are used for designing various kinds of random logic LSIs to reduce the development period. In the gate array method, there are two methods of designing memory circuits which are commonly used. In the first method, the basic cells are wired by using mask patterns (which have been registered in a library) to form various types of memory cells. The RAM and ROM cells can be formed as memory cells with different configurations because the memory cells used in the first method are a general purpose type memory cell. However, the required areas of the RAM and ROM on the chip are increased because the configurations of the RAM and the ROM cells are wasteful and the wiring required in the RAM and ROM is relatively long. Namely, it is difficult to design a LSI by using the first method. On the other hand, in the second method, special memory cells for various memory circuits are registered in the library, and a memory cell is designed by using the special memory cells. By using the second method, the problems inherent in the first method (wasted area in the RAM and ROM cells) can be eliminated. However, the special memory cells such as the RAM cells and the ROM cells must be registered because the functions of the RAM and ROM cells are different. Moreover, differrent capacity memory cells must be registered for the RAM cells and the ROM cells in the second method. There are, therefore, more kinds of memory cells than in the first method. When a custom LSI incorporating memory circuits is designed by using the second method, special memory cells for required functions must be developed or the memory cells having such functions must be registered beforehand in a library, so that the design cost is increased. An object of the present invention is to provide a semiconductor memory cell which is capable of easily forming memory cells of different functions, such as a RAM and a ROM, for example. According to one aspect of the invention, the memory cell initially defined is characterised in that the first field effect transistor is of enhancement type and has its gate connected to said low power source; and the second field effect transistor is of depletion type and has its gate connected to said low power source. According to another aspect of the invention, the memory cell initially defined is characterised in that the first field effect transistor has its gate connected to the high power source; and the second field effect transistor has its gate connected to the low power source. By the present invention, the design period or the development period of a semiconductor device such as a custom LSI having semiconductor memory cells can be decreased and the degree of integration of the memory cells in a semiconductor device can be enhanced. The object, features and advantages of the present invention will be more apparent from the following description of the preferred embodiments, taken in conjunction with the accompanying drawings, in which: Fig. 1 is an electrical diagram of a first configuration of a memory cell; Fig. 2 is an electrical diagram of a second configuration of a memory cell; Fig. 3 is an electrical diagram as a configuration of of a memory cell of a first embodiment according to the present invention; Fig. 4 is an electrical diagram as a configuration of a memory cell of a second embodiment according to the present invention; Fig. 5 is a composite layout (pattern layout) of the memory cell as shown in Fig. 1; Fig. 6 is a composite layout (pattern layout) of the memory cell of the embodiment as shown in Fig. 3; Fig. 7 is another composite layout (pattern layout) of the memory cell of the embodiment as shown in Fig. 3; Fig. 8 is a composite layout (pattern layout) of the memory cell of the embodiment as shown in Fig. 4; Fig. 9 is another composite layout (pattern layout) of the memory cell of the embodiment as shown in Fig. 4; and Fig. 10 is an electrical diagram of a high resistance load type memory cell. DETAILED DESCRIPTION OF THE EMBODIMENTS The preferred embodiments will be explained with reference to the drawings. Fig. 1 is an electrical diagram of a first configuration of a memory cell. The memory cell is formed as an one bit RAM by using a memory cell of a resistance load type which is widely used as a static RAM by a master slice method. In the same diagram, a high resistance R1 is connected to an N channel conductivity type (an enhancement type) field effect transistor (FET) T1 in series between a power source VDD and a power source (ground) VSS through a connection node M1. A high resistance R2 is connected to an N channel conductivity type (an enhancement type) field effect transistor (FET) T2 in series between a power source VDD and a power source (ground) VSS through a connection node M2. The connection node M1 is connected to the gate of the FET2 and to a bit line BL through a FET3, the gate of which is connected to a word line WL. The connection node M2 is connected to the gate of the FET1 and to a bit line BL through a FET4, the gate of which is connected to a word line WL. In the memory cell having the configuration described above, the high resistance R2 is disconnected from the power source VDD or the power source VSS to stop the function thereof. Next, a write operation of the memory cell of the present embodiment is explained. When the power VDD is turned on, the FET3 and the FET4 enter the inactivation state because the potential of the word line WL enters low level. then, the potential of the connection node M1 becomes high level, the potential of which is that of the power source VDD. At the same time, the connection node M2 does not enter the high level because the connection node M2 is disconnected from the power source VDD. Accordingly, the FET2 enters the active state and the connection node M2 enters the low level of which the potential is that of the power source (ground) VSS. Thus, the information in one bit is stored in the memory cell because the FET1 enters the inactive state, the connection node M1 enter the high level of VDD and the connection node M2 enters the low level of VSS. Next, a readout operation of the memory cell of the present embodiment will be explained. When the word line WL enters the high level to active the FET3 and FET4, charges on the bit line BL flow into the power source (ground) VSS through the FET2 and FET4 (both of which are in the active state), then the potential of the bit line BL enters the low state. On the other hand, the bit line BL maintains the high level because the FET1 is in the inactive state. In this case, both the bit lines BL and BL have been precharged at the high level. The change in potential of each bit line can be detected by using a sense amplifier connected to the bit lines BL and BL , for example. Thus, the information in the memory cell can be read out as described above. When the word line WL enters the low level after the readout operation of the memory cell, the FET3 and the FET4 enter the inactive state, so that the state of the connection nodes M1 and M2 are not changed. Namely, the information in the memory cell cannot be changed. In this case, when the power is OFF, the connection nodes M1 and M2 enter the low level. However, when the power is again ON, the potentials of the connection node M1 switched to the high level and the potential of the connection node M2 enters the low level in the same manner as described above, so that these connection nodes M1 and M2 can be maintained in the state preceding the cutting off the power. Namely, the information in the memory cell can be maintained even if the power is OFF and the memory cell has the function of a ROM. In the present embodiment, the ROM can be easily formed from the resistance load type memory cell as a RAM cell which is widely used in the prior art. In the embodiment, the high resistance R2 is disconnected from the power source VDD, the high resistance R1 may be disconnected from the VDD or the connection node M1 and the high resistance R2 may be connected to the power source VDD and the drain of the FET2. In this case, the operation of the memory cell is reversed to that of the memory cell of first embodiment, but the same effect can be obtained. Fig. 2 is an electrical diagram of a second configuration of a memory cell. Compared with the memory cell as shown in Fig. 1, FET5 shown in Fig. 2 consists of a depletion type FET, other elements are same as that of Fig. 1. Even if the connection node M1 has been at the low level when the power is ON, the FET5 enters the active state, so that the connection node M2 enters the low level of VSS (ground) and the FET1 enters the inactive state when the power is ON. Thereby, the potentials of the connection nodes M1 and M2 as shown in Fig. 2 are determined faster than that of the connection nodes M1 and M2 as shown in Fig. 1. The operation speed of the memory cell as shown in Fig. 2 can be increased after the power is ON. Fig. 3 is an electrical diagram as a configuration of of a memory cell of a first embodiment according to the present invention. Compared with the configurations as shown in Figs. 1 and 2, in the memory cell of the first embodiment, the FETS consists of a depletion type FET, which is provided between the connection node M2 ans the power source (ground) VSS. In addition, the gates of the FET1 and the FET5 are connected to the power source (ground) VSS. Thereby, the two bits of information can be stored in the connection nodes M1 and M2. In the memory cell of the third embodiment having the configuration above described, the connection node M1 is kept in the high level because the FET1 can be maintained in the inactive state while the power is ON. On the other hand, the potential of the connection node M2 is kept in the low level because the FETS can be maintained in the active state while the power is ON. Accordingly, two bits of information can be kept at the connection nodes M1 and M2. In this case, when the power is OFF, the potential of the connection node M1 enters the low level. Then, when the power is again ON, the potential of the connection node M1 may recover the high level. As described above, as in the first and the second configurations, the memory cell of the first embodiment can operate as a nonvolatile memory cell, for example a ROM. Fig. 4 is an electrical diagram as a configuration of a memory cell of a second embodiment according to the present invention. Compared with the memory cell of the first embodiment as shown in Fig. 3, each of the FET6 and the FET7 consists of a enhancement type FET. Each gate of the FET6 and the FET7 is connected to the power source VDD or the VSS (ground). In the memory cell having the configuration described above, the potentials of the connection nodes M1 and M2 enter the low level when the gates of the FET6 and the FET7 are connected to the power source VDD. Conversely, the potentials of the connection nodes M1 and M2 enter the high level when the gates of the FET6 and the FET7 are connected to the power source (ground) VSS. Thus, the memory cell of the second embodiment can store two bits of information in a manner similar to the memory cell of the first embodiment. Next, we will explain the actual composite diagrams of the memory cells according to the configurations of Figs. 1-4. Fig. 5 is a composite layout (pattern layout) of the memory cell of the first configuration as shown in Fig. 1. In the same diagram, the gates of FET3 and FET4 and the word line WL comprise a first polysilicon layer. Diffusion regions in the first polysilicon layers of the FET3 and the FET4 are connected to the bit lines BL and BL which consist of aluminum. The gate of each of the FET1 and the FET2 consist of the first polysilicon layer. The source region of the FET1 and the FET2, and the power source VSS consist of a diffusion layer. A drain region of the FET1 is connected to the connection node M1 through a wiring region which consists of a second polysilicon layer of low resistance doped with dopants such as impurities. The drain region of the FET2 is connected to the connection node M2 through a wiring region which consists of a diffusion layer. The high resistances R1 and R2 consuist of the second polysilicon layer. Another resion of the high resistance regions R1 and R2 is doped with dopants and the power source VDD is formed on one side of the resistances R1 and R2, and the wiring regions are formed on the other side for the connection nodes M1 and M2. In the composite layout as shown in Fig. 5, when one of the regions designated by the characters K1 and K3 of the second polysilicon layer of both side of the high resistance R1 and the regions designated by the characters K2 and K4 of the second polysilicon layer of both side of the high resistance R2 is not formed, the memory cell of the first configuration as shown in Fig. 1 can be easily provided from the basic cell as the RAM in a short development period without increasing the fabrication processes. The configuration of the memory cell as shown in Fig. 2 can be easily formed by doping with impurities in a region designated by a reference character IP as shown in Fig. 5. Thereby, the FET2 is changed to the deplation type FET5. The doping of the impurities can be operated by using a master slice method after the polysilicon and the aluminum layers are formed. Similar to the memory cell shown in Fig. 1, the ROM can be formed from thebasic cell of the RAM. The doping step of the impurities can be provided in the diffusion step at which the FETs are formed . Fig. 6 is a composite layout (pattern layout) of the memory cell of the first embodiment as shown in Fig. 3. In the composite layout as shown in Fig. 6, no contact holes C3 amd C4 by which the gates of the FET1 and the FET5 consisting of the first polysilicon layer are connected to the connection nodes M1 and M2 are formed, and the gates of the FET1 and the FET5 are disconnected from the connection nodes M1 and M2. In addition. the side of the first polysilicon layer is formed at the side of the diffusion layer of the power source VSS, then the first polysilicone layer is connected to the diffusion layer through the contact holes C1 and C2. Accordingly, the memory cell of the first embodiment as shown in Figs. 3 and 6 can be easily formed according to the presence or absence of the contact holes C1, C2, C3, and C4. Fig. 7 is another composite layout (pattern layout) of the memory cell of the first embodiment as shown in Fig. 3. Compared with the composite layout of the memory cell of the first embodiment as shown in Fig. 6, the composite layout (pattern layout) further comprises contact holes C5 and C6 by which the first polysilicon layer of the gates of the FET1 and the FETS is connected to the power source (ground) VSS by the master slice method. Thus, the memory cell as a ROM can be easily fabricated in the manner described above. Fig. 8 is a composite layout (pattern layout) of the memory cell of the second embodiment as shown in Fig. 4. Compared with the composite layout of the memory cell of the first embodiment as shown in Fig. 6, the side portion of the first polysilicon layer as the gates of the FET1 and the FET2 is extended to the second polysilicon layer as the power source VDD. In addition, the first polysilicon layer as the gates of the FET1 and the FET2 and the diffusion layer as the power source VSS or the second polysilicon layer as the power source VDD are connected selectively to the contact holes C1, C2, C7, and C8. Thereby, the memory cell of the second embodiment as shown in Fig. 4 can be easily formed according to the presence or absence of the contact holes C1, C2, C7, and C8. Fig. 9 is another composite layout (pattern layout) of the memory cell of the second embodiment as shown in Fig. 4. Compared with the composite layout of the memory cell as shown in Fig. 8. in the composite layout of the memory cell as shown in Fig. 9, the first polysilicon layer as the gates of the FET6 and the FET7 is connected selectively to the diffusion layer as the power source VSS or the second polysilicon layer as the power source VDD through the contact holes C1, C2, C7, and C8 which are preformed from aluminum wiring by the master slice method. The memory cell of the second embodiment can be easily formed by the above manner. As described above, the memory cells as the ROM having the composite layouts as shown in Figs. 1 to 4 and Figs 5 to 9 can be easily fabricated in a relatively short period from the basic cells as the RAM. Fig. 10 is an electrical diagram of a high resistance load type memory cell. In the same diagram, the value of a resistance R1 differs from that of the resistance R2. The difference of the values of resistances R1 and R2 must be determined without losing the function of the memory cell as a RAM. Thereby, the initial state of the memory cell can be provided. The difference between the values of the resistances R1 and R2 can be provided by controlling the concentration of the doping impurities because the resistances R1 and R2 consist of the polysilicon layer. Accordingly, for example, when the value of the resistance R1 is greater than that of the resistence R2, then the power is ON, the FET1 enters the active state, the FET2 enters the inactive state, the connection node M1 enters the low level and the connection node M2 enters the high level because the potential of the connection node M1 becomes lower than that of the connection node M2. Accordingly, when the power is ON, the stored information in the memory cell is never destroyed because the states described above can be set as the initial state of the memory cell. Various modification will become possible for those skilled in the art after the teaching of the present disclosure without departing from the scope thereof. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A semiconductor memory cell comprising: a word line (WL); a pair of bit lines (BL AND BL ) crossing the word line (WL); a first resistance (R1) of which one side is connected to a high power source (VDD) and the other side to a first connecting node (M1); a second resistance (R2) of which one side is connected to a high power source (VDD) and the other side to a second connecting node (M2); a first field effect transistor (FET1; FET6) connected between the first connecting node (M1) and a low power source (VSS); a second field effect transistor (FET5; FET7) connected between the second connecting node (M2) and the low power source (VSS); a third field effect transistor (FET3) connected between the first connecting node (M1) and one of the pair of bit lines (BL) and the gate of which is connected to the word line (WL) to control the operation of the third field effect transistor (FET3) by changing the potential of the word line (WL); and a fourth field effect transistor (FET4) connected between the second connecting node (M2) and the other of the pair of bit lines ( BL ) and the gate of which is connected to the word line (WL) to control the operation of the fourth field transistor (FET4) by changing the potential of the word line (WL), characterised in that: the first field effect transistor (FET1; FET6) is of enhancement type and has its gate connected to said low power source (VSS); and the second field effect transistor (FET5; FET7) is of depletion type and has its gate connected to said low power source (VSS). A semiconductor memory cell according to claim 1, wherein the threshold voltage of the first field effect transistor (FET1) differs from that of the second field effect transistor (FET2; FET5). A semiconductor memory cell according to claim 1 or 2, wherein the resistance value of the first resistance (R1) differs from that of the second resistances (R2). A semiconductor memory cell comprising: a word line (WL); a pair of bit lines (BL AND BL ) crossing the word line (WL); a first resistance (R1) of which the one side is connected to a high power source (VDD) and the other side to a first connecting node (M1); a second resistance (R2) of which the one side is connected to a high power source (VDD) and the other side to a second connecting node (M2); a first field effect transistor (FET6) connected between the first connecting node (M1) and a low power source (VSS); a second field effect transistor (FET7) connected between the second connecting node (M2) and the low power source (VSS); a third field effect transistor (FET3) connected between the first connecting node (M1) and one of the pair of bit lines (BL) and of which the gate is connected to the word line (WL) to control the operation of the third field effect transistor (FET3) by changing the potential of the word line (WL); and a fourth field effect transistor (FET4) connected between the second connecting node (M2) and the other of the pair of bit lines (BL) and of which the gate is connected to the word line (WL) to control the operation of the fourth field effect transistor (FET4) by changing the potential of the word line (WL); characterised in that: the first field effect transistor (FET6) has its gate connected to the high power source (VDD); and the second field effect transistor (FET7) has its gate connected to the low power source (VSS). A semiconductor memory cell according to claim 4, wherein the threshold voltage of the first field effect transistor (FET6) differs from that of the second field effect transistor (FET7). A semiconductor memory cell according to claim 4 or 5, wherein the first field effect transistor (FET6) is a depletion type field effect transistor and the second field effect transistor (FET7) is an enhancement type field effect transistor. A semiconductor memory cell according to any of claims 4 to 6, wherein the resistance value of the first resistance (R1) differs from that of the second resistances (R2).

Inventors: TAKASE SHINSUKE, TANAKA YUTAKA, TAKASE, SHINSUKE, TANAKA, YUTAKA
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1991
Main classification: G11C7
IPC codes: G11C17, G11C7, H01L27, H01L21, G11C11