A controller for distributing loads among call processors

Abstract: A main processor (3) assigns originated-call processings to each of a plurality of call processors (2a ... 2n) in the sequence of call originations according to the first principle of this invention. A switching state controller (4) collects usage information about a plurality of buffers composing the switching network (1) in the ATM exchanger. The call processors (2a ... 2n) to which call processings are assigned perform the call processings based on the content of switching state controller (4). A main processor (3) assigns a call processing for an originated call to one of a plurality of call processors (2a ... 2n) by referring to the call processing assignment table memory (5) with the virtual channel identifier corresponding to an originated call according to the second principle of this invention. Thus, call processing loads are distributed among call processors (2a ... 2n).

Description: Background of the Invention Field of the Invention This invention pertains to a broadband exchange and more particularly to a controller according to the preamble of claim 1. Description of the Related Art Such a controller is known from DE 36 29 406 A1 and DE 36 29 466 A1, respectively. With the widespread use of data communication, public switched networks are now required to provide high-quality data communication, as well as the traditional voice communication. Broadband ISDN (B-ISDN) has begun to be utilized for a communication networks not only for low-speed data, such as voice data, but also for high-speed data, such as moving images, and various interfaces have been standardized. Unlike the traditional switching method, a B-ISDN utilizing an asynchronous transmission mode (ATM) can commonly carry at different speeds various sorts of information, e.g. voice data, moving image data and even continuous information mixed with bursty information. An ATM communication network transmits and exchanges information of different bands divided and housed in fixed-length data units called cells, instead of in variable-length packets as in traditional packet communication. Cells containing channel data and packet data are indiscriminately multiplexed, transmitted over optical fibers at high speed, and rapidly exchanged by hardware switches. Thus, an ATM communication network can offer flexible service requiring different transmission speeds and makes efficient uses of transmission paths. As described above, user information is divided into several pieces according to its length and cells are configured by adding headers, e.g. of a few bytes, to respective data, e.g. of 32 to 120 bytes, comprising the divided pieces of information. A header contains a virtual channel identifier (VCI) for identifying the originating user of the corresponding data. Thus, user information stored in cells is multiplexed over ATM highways and transmitted and exchanged to a destined terminal. An exchanger adds to inputted cells information as to how they should be exchanged in the exchange system, so that they are autonomously transmitted over a transmission path in the exchange network with their added header information read by respective switches in the exchanger. Hence, this switching method is called a self-routing method, and the group of switches within the exchanger is called a self-routing part. Figure 1 shows an exemplary configuration of a multistage self-routing part (MSSR) being a switching part in an ATM exchanger. The MSSR comprises plural [generally three (3)] stages of self-routing modules (SRMs) each comprising a plurality of input and output terminals. An ATM exchanger is equipped with two such MSSRs, as shown in Figure 1, for both directions of data transmission. Figure 2 shows an exemplary configuration of an SRM shown in Figure 1. An SRM has pluralities of input and output lines, and a crossing point of an input line and an output line is provided with a buffer. In Figure 2, the SRM has four (4) input lines, four (4) output lines and sixteen (16) buffers at respective crossing points. As described earlier, at the entrance of an MSSR, the respective inputted cells have added to themselves information, called tag information, as to which input line they are inputted to and which output line they are outputted from. Thus, tag information routes cells in an MSSR. For instance, when SRMs are connected in three (3) stages as shown in Figure 1 and respective SRMs have four (4) output lines as shown in Figure 2, respective inputted cells have added to themselves 6-bit tags comprising three (3) sets of 2-bit tags specifying which of the four (4) output lines is selected for outputting corresponding to the three (3) SRM stages. Meanwhile, as described earlier, the header of each inputted cell has added to itself a VCI for identifying the originating user of the cell. This VCI is defined for respective logical links among exchangers. Therefore, the header of an inputted cell from an originating user has added to itself the VCI specifying the link with the exchanger of the preceding stage, over which link the cell is transmitted. The respective exchangers replace the VCI added to the header of an inputted cell with the new VCI specifying the link with the exchanger of the succeeding stage, over which link the cell is transmitted. Thus, cells are sequentially transmitted to a plurality of exchangers towards a destined terminal. A part called a Virtual Channel Converter (VCC) in the MSSR of an exchanger performs the above two processes, i.e. replacing VCIs and adding tag information, for the inputted cells. The new VCI for replacing the old VCI attached to an inputted cell and the new tag information for replacing the old tag information are uniquely determined by the old VCI. Accordingly, a VCC is provided with a conversion table enabling it to obtain, from the old VCI of an inputted cell, the new VCI to be added to the inputted cell when it is outputted and the tag information. When a user originates a call, a call processor determines, based on the traffic condition in the entire ATM network, the content of a VCC conversion table for obtaining, from the old VCI, the appropriate tag information and the new VCI, which specify the optimal transmission path for the cells of the originated call. Hence, the larger the MSSR and the more SRM stages it contains, the more complex the processes the call processor must perform. As such, if one call processor performs all the processes for all incoming calls, which is ordinarily considered for all processings. The network's response degrades. An ordinary solution to such a problem is to distribute load among a plurality of call processors. However, there has been no known load distribution controlling method for effectively controlling MSSRs comprising plural stages of SRMs. When an MSSR comprises three (3) SRM stages, for instance, three (3) processors may share the switching control in respective stages. However, since the switch loads in respective stages are not uniform, a crucial problem still remains as to how efficiently a switching can be performed by distributing loads equally among all call processors. Summary of the Invention This invention is conceived based on the above background and aims at controlling the switching network of an ATM exchanger by uniformly distributing loads among a plurality of call processors. It is premised on a device for controlling the load distribution among a plurality of call processors by controlling the switch network in an ATM broadband exchanger. The invention provides a controller of the initially defined type having the characterizing features of claim 1. Preferred embodiments are listed in the dependent claims. Brief Description of the Drawing Those in the same field can easily understand additional purposes and features of this invention from the descriptions of the principles and the preferred embodiments of this invention together with the attached drawings. In the drawings; Figure 1 shows an exemplary configuration of a multistage self-routing part in an ATM exchanger; Figure 2 shows an exemplary configuration of a self-routing module; Figure 3A is a block diagram illustrating the on the way to this invention; Figure 3B is a block diagram illustrating the principle of this invention; Figure 4 is a block diagram illustrating the schematic configuration of an exemplary ATM exchanger; Figure 5 is a block diagram illustrating the configuration of an exemplary self-routing module; Figure 6 is a block diagram illustrating the configuration of an exemplary VCI converter (VCC); Figure 7 shows a switching state control table (SST); Figure 8 shows exemplary data, for assigning call processing on the way to this invention, stored in a memory (not shown) of an main processor (MPR); Figure 9 is a flowchart of a call processing assignment operation executed by an MPR on the way to this invention; Figure 10 is a flowchart of a call connection processing operation executed by a call processor (CPR); Figure 11 is a flowchart of a bandwidth control processing operation executed by an MPR; Figure 12 shows an embodiment of a call processing assignment table provided in a memory of an MPR according to the principle of this invention; and Figure 13 is a flowchart of a call processing assignment operation executed by an MPR according to the principle of this invention. Description of the Principles of This Invention Before describing the preferred embodiments of this invention, its principles are explained by referring to Figures 3A and 3B. This invention pertains to a method for controlling load distribution among a plurality of call processors (CPRs) 2a through 2n, for controlling a switching network 1, provided in an asynchronous transmission mode (ATM) exchanger. Figure 3A is a block diagram illustrating the way to this invention. In Figure 3A, a main processor (MPR) 3 sequentially assigns call processings for call-ups to CPRs 2a through 2n in the call-up origination sequence. A switching state controller 4 collects usage information about a plurality of buffers composing the switching network 1 in the ATM exchanger. Figure 3B is a block diagram illustrating the principle of this invention. As shown, a call processing assignment table memory 5 is provided, e.g. in a memory of the MPR 3, for memorizing which CPR performs the call processing corresponding to respective channel identifiers attached to the cells in an originated call. The switching state controller 4 shown in Figure 3B operates similarly to that shown in Figure 3A. By referring to the call processing assignment table memory 5 with the channel identifier corresponding to an originated call, the MPR 3 assigns a call processing for the originated call to one of the CPRs 2a through 2n. Further, for uniformly distributing loads among CPRs 2a through 2n, the MPR 3 periodically updates the contents of the call processing assignment table 5 based on the information stored in the switching state controller 4. According to this invention, the MPR 3 integrally controls the assignment of call processings to CPRs 2-1 through 2-N for controlling the switching network 1 in the ATM exchanger by the channel identifiers attached to the cells, so that loads are distributed uniformly among CPRs 2-1 through 2-N, which route cells of the originated call based on the information stored in the switching state controller. Description of the Preferred Embodiments The way to the invention and preferred embodiments of this invention are explained in more detail, below. Figure 4 is a block diagram illustrating the schematic configuration of an exemplary ATM exchanger. In Figure 4, a VCI converter (VCC) 6 replaces the virtual channel identifier (VCI) in an ATM cell corresponding to the link with the exchanger in the preceding stage, with the VCI corresponding to the link with the exchanger in the succeeding stage, and adds to the ATM cell a tag giving routing information in a multistage self-routing part (MSSR) 7 comprising plural stages of self-routing modules (SRMs). Three call processors (CPRs) 2a, 2b and 2c, as well as a signaling device (SIG) for detecting a call origination, are connected to a common bus 8 and controlled by the main processor (MPR) 3. Figure 5 is a block diagram illustrating the configuration of an exemplary self-routing module. In Figure 5, self-routing modules (SRMs), composing the MSSR 7 shown in Figure 4, comprise four (4) buffers at 2*2 crossing points C 00 through C 11 , where ATM cells are exchanged by switching ATM cells inputted from input highways IHW #0 and #1 to output highways OHW #0 and #1. Figure 6 is a block diagram illustrating the configuration of the VCI converter (VCC) 6 shown in Figure 4. The VCC 6 comprises VCNVs (VCC driver) 10-0 through 10-3 for converting VCI and attaching tag information to the cells inputted from input highways IHW0 through IHW3 according to an instruction from CPR2 and a VCCC (VCC channeler) 11 for interfacing between respective VCNVs 10-0 through 10-3 and respective CPRs 2-1, 2-2 and 2-3. The MPR 3 shown in Figure 4 is provided with a bandwidth controller (BWC) which corresponds to the switching state controller 4 shown in Figures 3A and 3B. An originating terminal making a call connection request notifies the exchanger of the information on the bandwidth occupied by the call together with the information on the destining terminal. The BWC controls the switching state by tracking the information on the bandwidth occupation, e.g. values such as 64Kbps for a voice transmission and 50Mbps for a moving image transmission, from the originating terminal and information on the path over which the cells of the call are routed in the MSSR 7 when the call is actually connected, instead of by monitoring the actual usage of the buffers in the switching network. Through such software processing controls, the BWC easily realizes the switching state. Figure 7 shows a switching state control table (SST) retained in the above described band information controller (BWC). The SST is retained in a memory (not shown in the drawings) and contains the sums of the bandwidths of the calls currently being switched for the twenty-four (24) combinations of S XY (in the respective SRMs S 00 , S 01 , S 02 , S 10 , S 11 and S 12 each comprising 2*2 buffers) and C LM (at the respective crossing points C 00 , C 01 , C 10 and C 11 ) and the maximum value MAX of the back widths switchable at a particular crossing point (of an input line and an output line in an SRM). In the example of this embodiment shown in Figure 7, the MAX is set to 150Mbps and 75Mbps bandwidth is currently being used for switching calls at crossing point C 00 in SRM S 00 . Since the MAX is greater than the sum of the bandwidths of the calls currently being switched at crossing point C 00 in SRM 00 , additional calls having total bandwidths of 75Mbps can be switched at this particular crossing point. Figure 8 shows exemplary data, for call processing assignments , stored in a memory (not shown) of MPR 3. The exemplary data comprise two data MAXCPF and CPF, where MAXCPF indicates the total number of CPRs in an exchanger and CPF indicates the number of CPRs in the exchanger to which the next call processing is assigned. Accordingly, the MAXCPF is constant unless the configuration of the exchanger is changed. Since there are three (3) CPRs 2a, 2b and 2c in the schematic configuration shown in Figure 4, MAXCPF is set to 3 here. CPF, the call processing assignment flag, currently indicates #2 for 2b, but it changes cyclically from #1 to #2 to #3 and then back to #1. The call processing assignments and bandwidth controls by the MPR3 , as well as the call connection processings by the CPRs 2a, 2b and 2c, are explained in more detail. Here, the MPR 3 independently executes two processings (programs) of call processing assignments and bandwidth controls, and the CPRs 2a, 2b and 2c independently execute their respectively assigned call connection processings. Figure 9 is a flowchart of a call processing assignment operation executed by the MPR 3 on the way to this invention. Described below are the operations in the flow sequence according to Figure 9. STEP 91: A connection request is received from the signaling device (SIG) 9. (Refer to Figure 4.) STEP 92: The call processing assignment flag (CPF) (Refer to Figure 8.) is read from a memory (not shown). STEP 93: The CPR corresponding to the number indicated by the CPF (CPR 2a for CPF #1, CPR 2b for CPF #2, and CPR 2c for CPF #3) is assigned with a call processing and receives the information necessary for the call processing, such as the VCI attached to the header of an inputted cell. STEP 94: 1 is added to the CPF value, which is stored in the memory as the new CPF. STEP 95: The CPF is compared with the MAXCPF and the processes are concluded when the CPF does not exceed the MAXCPF. STEP 96: When the CPF exceeds the MAXCPF (Refer to Figure 8.) read from the memory, the CPF reverts to 1, which is stored in the memory. Figure 10 is a flowchart of a call connection processing operation executed by a call processor (CPR) corresponding to the value of CPF. The operation of the MPR3 assigns the call processing to the CPR, based on the actions described in the flowchart shown in Figure 9. Described below are the operations in the flow sequence according to Figure 10. STEP 101: Based on the information (such as the inputted VCI indicating the link with the SRM in the preceding stage, the input highway number and the destining terminal number) received from the MPR 3, the new VCI indicating the link with the SRM in the succeeding stage and the output highway number are determined. STEP 102: All possible route plans are determined from among the input highway number and the determined output highway number. STEP 103: One of the route plans determined in STEP 102 and the bandwidth of the call to be connected are notified to the bandwidth controller (to be described later). STEP 104: If the MPR 3 judges that the route plan can be instituted, the control moves on to STEP 105. Otherwise, it moves on to STEP 106. STEP 105: The new VCI determined in STEP 101 and the tag information corresponding to the route plan selected in STEP 103, together with the input VCI corresponding to the calls to be connected, are notified to the VCC 6. (Refer to Figures 4 and 5.) STEP 106: The control reverts to STEP 103, after the route plan selected in STEP 102 and judged incapable of being instituted in STEP 104 is eliminated. If there is no route plan, the call being processed is not connected and the calling process is terminated. Figure 11 is a flowchart of a bandwidth control processing operation executed by the MPR 3. The MPR 3 notified of the bandwidth of a call and a route plan according to the processing by a CPR in STEP 103 shown in the flowchart of Figure 10 activates the bandwidth controller for executing the processes shown in the flowchart of Figure 11, and notifies the CPR of the applicability of the route plan. Described below are the operations in the sequence of the flow according to Figure 11. STEP 111: The MPR3 is notified of the route plan of the MSSR 2 (Refer to Figure 4.) selected by the CPR corresponding to a CPF, i.e. the transmission path through the crossing points of the three stage SRMs over which a cell in a call is transmitted, and the size of the bandwidth occupied by the call. STEP 112: The content of the switching state control table (SST) is read. (Refer to Figure 7.) STEP 113: The bandwidth value of the call connected by the CPR corresponding to a CPF is added to the used bandwidth value read from the SST corresponding to respective crossing points on the route plan obtained from the CPR corresponding to the CPF. STEP 114: It is judged whether or not respective bandwidths in use obtained from the addition performed in STEP 113 exceed the maximum bandwidth MAX usable for switching read in STEP 112. STEP 115: If there is no crossing point whose usable bandwidth exceeds the MAX, the CPR corresponding to the CPF is notified that the route cannot be set. STEP 116: The content of the SST shown in Figure 7 is updated according to these usable bandwidth values. STEP 117: If there is any crossing point whose usable bandwidth exceeds the MAX, the CPR corresponding to the CPF is notified that the route cannot be set. The above bandwidth controls and call processing assignments performed by the MPR 3 according to the first principle of the call processing assignments, as well as a concrete example of the call connection processing by a CPR is described below as procedures (1) through (16). (1) The signaling device (SIG) 9 notifies the MPR 3, over the common bus 8 shown in Figure 4, of a request to connect a call to a desired destining terminal number and the input VCI(=3). The call is assumed to be routed to input highway IHW #0 in the MSSR 7. (2) The MPR 3 activates the call processing assignments shown in the flowchart of Figure 9. (3) The MPR3 refers to a CPF stored in a memory, not shown in the drawings. (Refer to Figure 8.) If the CPF value is 3, the MPR 3 notifies CPR 2c corresponding to the CPF, over the common bus 8, of the information necessary for the call processing, such as the input VCI and the destining terminal number. (4) The MPR 3 terminates its call processing assignments. (5) Based on the notification in procedure (3), the CPR 2c corresponding to the CPF value 3 activates the call connection processings shown in the flowchart of Figure 10. (6) The CPR 2c corresponding to the CPF value 3 determines the output VCI and the output highway number OHW (#2, for instance), based on the information notified in procedure (3). (7) The CPR 2c corresponding to the CPF value 3 determines the possible route from IHW #0 to OHW #2. (Refer to Figures 4 and 5.) In the above example, the possible routes are as follows. Route plan 1: S 00 , C 00 ---→ S 01 , C 01 ---→ S 12 , C 01 Route plan 2: S 00 , C 01 ---→ S 11 , C 01 ---→ S 12 , C 10 (8) The CPR 2c corresponding to the CPF value 3 notifies the MPR 3 of route plan 1 and the bandwidth (e.g. 100Mbps) of a call and waits for the reply on the applicability of route plan 1. (9) Upon being notified by the CPR 2c, the MPR 3 activates the bandwidth controller shown in Figure 11. (10) The MPR 3 reads, from the switching state control table (SST) shown in Figure 7, the respective bandwidths used by the crossing points in route plan 1 notified in procedure (8). (11) If, for instance, S 00 , C 00 = 30, S 01 , C 01 = 45, and S 12 , C 01 = 10, are read from the SST as a result of procedure (10), the MPR 3 adds to these values 100, which is the bandwidth of the call to be connected. (12) Since the bandwidth at no point exceeds the MAX (=150) as a result of procedure (11), the MPR 3 judges that the present route plan is appropriate and writes new values in the SST. That is, S 00 , C 00 = 130, S 01 , C 01 = 145, and S 12 , C 01 = 110. (13) The MPR 3 notifies the CPR 2c corresponding to the CPF value 3, over the common bus 8, of the permission for a call connection. (14) The MPR 3 terminates its bandwidth controls. (15) Upon being notified of the permission for a call connection, the CPR 2c corresponding to the CPF value 3 notifies the VCC 6, over the SP bus 12 shown in Figure 4, of the output VCI and the tag information being route setting data, together with the input VCI corresponding to the call to be connected. Thus, the VCC 6 finalizes the content of the VCI conversion table corresponding to the tag information and the output VCI for an input VCI. (16) The CPR 2c corresponding to the CPF value 3 terminates its call connection processings. Embodiments of this invention according to the principle of the call processing assignments are explained in further detail. Figure 12 shows an embodiment of a call processing assignment table provided in a memory of an MPR according to the principle of this invention. An embodiment according to the principle of the call processing assignments is equipped with a call processing assignment table (ATBL), as shown in Figure 12, in a memory (not shown) within the MPR 3, instead of the data for call processing assignments according to the way to the invention shown in Figure 8. The call processing assignment table (ATBL) is equivalent to the call processing assignment table memory 5 according to the principle of this invention shown in Figure 3B and is provided inside the MPR 3, together with the switching state controller 4. The ATBL comprises values for the input VCIs (hereafter called IVCIs), which are virtual channel identifiers attached to the calls requesting connections, and values for CNO, which are numbers of the call processors (CPRs) assigned with the processings of the calls corresponding to respective IVCIs. In the example shown in Figure 12, there are six (6) IVCIs 1 through 6. For instance, the processings of connecting the call with its IVCI value 3 are assigned to the CPR with its CNO value 2. As described later, the MPR 3 adjusts the loads for the respective CPRs by updating the content of the ATBL. Now an embodiment of the call processing assignments performed by the MPR 3 according to the principle is explained in more detail. The bandwidth controls by the MPR 3 and the call connecting processes by a CPR are essentially similar to those processes based on the flowcharts shown in Figures 10 and 11, explained for the call processing assignments on the way to the invention. Figure 13 is a flowchart of a call processing assignment operation executed by an MPR according to the principle of this invention. Described below are the operations in the sequence of the flow according to Figure 13. STEP 131: The MPR 3 receives connection request from the signaling device (SIG) 9. (Refer to Figure 4.) STEP 132: The MPR 3 determines the particular CPR to which call processings are assigned by referring to the ATBL shown in Figure 12 with the input VCI (IVCI) of the call requesting a connection. STEP 133: The MPR 3 receives information necessary for the call processing e.g. of the VCI attached to the header of the inputted cell in correspondence with the particular CPR determined in STEP 132. As shown in the above flow, according to the principle of the call processing assignments, by using the ATBL such as that shown in Figure 12, the MPR 3 performs a control to realize proper load distributions among all pertinent CPRs. Here, the MPR 3 adjusts the load for respective CPRs by updating the content of the ATBL according to the traffic condition in the network. For instance, the MPR 3 determines the content of ATBL according to the content of the switching state control table (SST) shown in Figure 7. Alternatively, the MPR 3 determines the content of the ATBL, so that frequently used IVCIs are assigned to different to CPRs as much as possible.

Claims: A controller for distributing loads among call processors (2a, 2b, ..., 2n; 2-1, 2-2, ... , 2-N), which control a switching network (l) in an asynchronous transmission mode broadband exchanger, said controller comprising: a call processing assigning means (3) for assigning originated-call processing to one of said plurality of call processors (2a, 2b, ..., 2n; 2-1, 2-2, ... , 2-N) by referring to a call processor assigning table memory means (5); and a switching state controlling means (4) for controlling respective usages of a plurality of buffers comprises in said switching network; wherein call processors to which call processing is assigned by said call processing assigning means (3) perform said call processing based on the control state of said switching state controlling means (4); characterized in that said call processing assignment table memory means (5) is arranged to memorize a table (ATABL) showing which call processor takes charge of the processing of a call dependent on each channel identifier (VCI) attached to each cell of an originated call. The controller according to claim 1, further comprising an updating means (3) for updating the content of the table (ATABL) of said call processing assignment table memory means (5) according to the control state by said switching state controlling means (4). The controller according to claim 1, further comprising an updating means (3) for updating the content of the table (ATABL) of said call processing assignment table memory means (5), so that frequently used channel identifiers (VCI) are assigned to different call processors as much as possible. The controller according to claim 1 or 2, wherein: said call processing assigning means (3) and said switching state controlling means (4) are realized as functions of a main processor (3) connected to said plurality of call processors (2a, 2b, ..., 2n; 2-1, 2-2, ... , 2-N); and said plurality of call processors (2a, 2b, ..., 2n; 2-1, 2-2, ... , 2-N) sequentially perform call processing while contemporaneously communicating with said main processor. The controller according to one of the preceding claims, wherein said switching state controlling means (4) comprises: a switching state control table (SST) for controlling respective bandwidths used by said plurality of buffers comprised in said switching network; and a bandwidth controlling means (4) for judging the applicability of route plans by determining the bandwidths to be used by said respective buffers corresponding to route plans notified by said call processors, the bandwidths occupied by the calls to be connected, and the actual content of said switching state control table (SST), and for notifying said call processors of said applicability of said route plans notified by said call processors. The controller according to claim 5, wherein said bandwidth controlling means is arranged to: read bandwidths used by the buffers on the route plan notified by said call processor from said switching state control table (SST); add the bandwidths, to be occupied by a call to be connected, notified by said call processors to said bandwidths, used by said respective buffers, read from said switching state control table (SST); and judge the applicability of said route plans by determining whether or not the respective sums exceed a maximum usable bandwidth (MAX).

Inventors: ASO YASUHIRO, KAKUMA SATOSHI, MURAYAMA MASAMI, UCHIDA YOSHIHIRO, YOSHIMURA SHUJI, ASO, YASUHIRO, KAKUMA, SATOSHI, MURAYAMA, MASAMI, UCHIDA, YOSHIHIRO, YOSHIMURA, SHUJI, KAKUMA, SATOSHI, 101 AZERIA-HAITSU, MURAYAMA, MASAMI, 203, KOJIMA-COPO, UCHIDA, YOSHIHIRO, W-10-117 FUJITSU NAKAHARA HOUSE, YOSHIMURA, SHUJI, 101 DAI-2 YAMATO-COPO
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1991
Main classification: H04L12
IPC codes: H04Q3, H04L12