HIGH SPEED COLOR DISPLAY PROJECTION SYSTEM AND METHOD OF USING SAME

Abstract: A high speed color display system (10) including a modulation circuit (11) electrically coupled between a high speed display device (16), such as an active matrix liquid crystal display panel, and a video output signal source (26, 14A) such as a video output card of a personal computer. The modulation circuit (11) including both a scaling circuit (35A) for eliminating or substantially reducing contouring caused by quantizing errors associated with approximations of digital pictures and a duty cycle scaling circuit (42A) for eliminating or substantially reducing repetitive beats in a displayed image. The display panel (16) is adapted for positioning on a conventional photographic projector for displaying large video images. Such a system (10) is modular and employs relatively inexpensive subassembly units such as a user selected television signal generating type device, such as a video cassette recorder (20), and a high speed display device, such as an active matrix display panel (16) adapted for positioning on a projector.

Description: Description HIGH SPEED COLOR DISPLAY PROJECTION SYSTEM AND METHOD OF USING SAME Technical Field The present invention relates in general to a video display system, and a method of using it. The invention more particularly relates to a method and apparatus for producing a full color image generated from a video signal, such as a television video signal on a high speed display panel, such as a liquid crystal active matrix panel and for displaying a large projected full color image generated. The present invention also relates in general to a video display system, and a method of using it. The invention more particularly relates to a method and apparatus for displaying a large projected full color display image generated from a television video signal. Background Art There have been various different types and kinds of full color video display systems. Inventive techniques for producing such a full-color display include the use of direct view video or television monitors. While such techniques have been satisfactory for some applications direct video and television monitors have generally limited with respect to the size of the viewed video image, due to the limited screen area associated with the cathode ray tube employed by such monitor units. Moreover, such systems have been relatively expensive to manufacture, as a result of the cost associated with the direct view video monitors. Therefore, it would be highly desirable to have a new and improved full-color display system that can produce for a user or audience a large television image, without employing an expensive direct view television monitor. One attempt to over come the problem of having a limited viewing area has been to employ a rear view projection system where a television signal is converted into its component color parts of red, green and blue to drive a set of red, green and blue lights which are projected onto the rear side of a large transparent screen for viewing purposes. While this technique has proven to be satisfactory for some applications, it has proven to be relatively expensive and requires a large cumbersome display unit cabinet which is difficult to move from place to place. In addition, the brightness of the viewed images is somewhat impaired because of the loss of light in traversing the transparent screen. Therefore, it would be highly desirable to have a new and improved video display system for displaying large color images produced from a television signal which would be relatively inexpensive and that would not be difficult to move from place to place for viewing purposes. Another attempt to overcome the problem associated with poor luminance in a large screen viewing system, has been to employ a direct front projection system. The direct projection system is similar to the rear view system except that the red, green and blue lights are projected onto the front surface of a large reflective screen from a projection unit disposed in front of the screen. Again, while such a technique has proven satisfactory for some applications, it has not proven entirely satisfactory, since the projection unit has typically been mounted in a permanent location relative to the screen, for proper focusing and to assure that a sufficient amount of light is projected onto the screen to provide an image with sufficient brightness for viewing purposes. Therefore, it would be highly desirable to have a new and improved video display system, which could produce large screen viewing images having a relatively high luminance level and which would not be required to be permanently mounted or otherwise positioned. There have been various different types and kinds of full-color display systems, such as for use with computer-driven projection display panels, computer monitor screens, and television screens. Inventive techniques for producing such a full-color display, are disclosed in the foregoing-mentioned parent patent applications. The techniques include the use of twisted nematic liquid crystal display panels, which are stacked or arranged in series along a common optical path. Each one of the panels, together with a set of interleaved polarizers, pass three different primary colors, such as red, blue and green. The three primary colors are selectively and additively combined to provide a group of full colors. In this regard, by selectively either energizing or deenergizing certain ones of the panels, combinations of colors can be achieved from the output stage of the display system. According to the inventive techniques employed in the foregoing mentioned pending patent applications, each one of the three stages of the stacked panel system, can produce multiple numbers of shades of each one of the three primary colors. The patentable techniques, thus, enable a large number of combinations of colors to be passed by the display system. The twisted nematic liquid crystal display panels, while being quite effective, are limited in their speed of operation. Thus, the more modern high-speed active matrix display panels have been developed. Such an active matrix panel is a single panel employing three different color elements for each pixel. Therefore, SUBSTITUTE SHEET there is no need to have three separate panels to provide a multi-color display. The active matrix panel, employs pixel elements each having three color subpixel components, and operates at a much higher speed than its earlier twisted, nematic panel. By employing three color components for each pixel, a color additive process, of selecting individual ones of the three colors, permits a total of eight colors, which may be passed for each pixel. However, in order to increase the number of colors from the pixel, various different shades or intensity levels for each color component is required. One approach to achieve such intensity levels would be to provide additional hardware circuits for driving the pixel elements through various different color intensity levels for each one of the three color components in a pixel element. While this approach may be satisfactory for some applications, such an approach would be quite expensive to manufacture. In the foregoing mentioned patent applications, intensity levels have been produced by employing a duty- cycle modulation system. In this regard, each one of the three color element is either turned on or off, each raster display frame. However, when a color element is to be energized to produce a desired shade of a color, it will remain on for a certain averacfe percentage of the time over a series of raster frames. The persistence of the eye of the viewer perceives a resulting color to be of a certain desired intensity or shade. In this approach, electronic control circuits are provided to cause the individual color pixel elements to be turned ON selectively, and OFF selectively, to achieve a desired color intensity level. When employing such an electronically controlled modulation or duty cycle system in a high-speed display system, such as an active matrix display system, the UBSTITUTESHEET difference of speed between the computer controlled modulation circuit, and the much higher speed display panel, causes an undesirable movement of the image. Such a movement of the image is undesirable and unwanted for certain applications. In order to match the speed of the computer controlled circuit, as governed by the maximum speed of the computer driving it, to the much higher speed display panel, the use of memories, such as a bit map memory for storing an image to be displayed, can provide the necessary matching of the speeds. However, this technique is not entirely desirable for some applications, since there is a quantizing error introduced by employing such an approach. The resulting image is a digitized image, which is an approximation only of the desired analog signal. For more information relating to the problems of quantizing error, reference may be made to a book entitled "Digital Pictures Representation and Compression" by Arun N. Netravali and Barry G. Haskell. The quantizing error causes an undesirable "contouring" or splotchiness of the resulting color images. In other words, when the number of shades or intensities of a given color is increased, due to the quantization of the picture image, the resulting color image is merely an approximation of a corresponding analog signal image of the color to be displayed, and the resulting image produced, is not entirely satisfactory. In order to reduce the quantizing error to such a level that the contouring or splotchiness is reduced to an acceptable level, at least eight or nine bits of color information are required for a given color intensity. However, such a bit map memory required for a high speed display, would be excessively large in size, and unduly expensive, in order to match the speeds of the computer SUBSTITUTE SHEET with the high-speed display. Additionally, should the modulation or duty cycle technique be employed to increase the number of possible color intensity levels, the duty cycle control circuits would be excessively complex, and thus be too expensive to manufacture for some applications. Therefore, it would be highly desirable to produce a very large number of full colors from a high-speed display, without causing an undesirable movement of the resulting image caused by improper matching of speeds between the computer and the display, and also without contouring or splotchiness caused by excessive quantizing error associated with approximations of digital pictures. There have been various different types and kinds of full color video display systems. Inventive techniques for producing such a full-color display include the use of direct view video or television monitors. While such techniques have been satisfactory for some applications, direct video and television monitors are generally limited with respect to the size of the viewing image, due to the limited screen area associated with the cathode ray tube employed by such monitor units. Moreover, such systems have been relatively expensive to manufacture, since direct view video monitors are expensive. Therefore, it would be highly desirable to have a new and improved full-color display system, which can produce a large television image for group viewing, without employing an expensive large direct view television monitor. One attempt to over come the problem of having a limited viewing area has been to employ a rear view projection system, where a set of red, green and blue images are projected onto the rear side of a large transparent screen for viewing purposes. While this technique may satisfactory for some applications, it has proven to be relatively expensive to manufacture and requires a large cumbersome display unit cabinet which is difficult to move from place to place. In addition, the brightness of the viewed images is somewhat restricted or impaired due to the loss of light in traversing the transparent screen. Therefore, it would be highly desirable to have a new and improved video display system for displaying large color images produced from a television signal which would be relatively inexpensive and that would not be difficult to move from place to place for viewing purposes. Another attempt to overcome the problem associated with poor luminance in a large screen viewing system, has been to employ a direct front projection system. The direct projection system is similar to the rear view system except that the red, green and blue images are projected onto the front surface of a large reflective screen from a projection unit disposed in front of the screen. Again, while such a technique has proven satisfactory for some applications, the projection unit has typically been mounted in a permanent location relative to the screen, for proper focusing and to assure that a sufficient amount of light is projected onto the screen to provide an image with sufficient brightness for viewing purposes. Therefore, it would be highly desirable to produce large screen viewing images having a relatively high luminance level and not being required to be permanently mounted or otherwise positioned. Another attempt to overcome the problem associated with poor luminance has been to use a high speed active matrix panel with an overhead projector for the display of information. Such flat high speed active matrix SUBSTITUTE SHEET δ panels have been capable of producing full color displays with thousands of bright colors. Such a large number of colors however has been possible only by using very sophisticated duty cycling techniques so that individual pixels in the liquid crystal display device may be selectively modulated to produce multiple intensity levels. While such duty cycle techniques have been successful for the high speed active matrix liquid crystal panels, a less sophisticated approach may be warranted for slower speed active matrix panels. Therefore, it would be highly desirable to be able to produce thousands of different bright colors in a low speed liquid crystal display panel without using a sophisticated duty cycle technique. Disclosure of Invention Therefore, the principal object of the present invention is to provide a new and improved video display system and method of using it to produce large displayable images generated from conventional television signals. Another object of the present image is to provide a new and improved video display system that is relatively inexpensive to manufacture and which is easily transmitted for convenient viewing purposes. Still yet another object of the present invention is to provide a new and improved video display system which produces a video image having a relatively high luminance level where the luminance level is directly related to the size of the displayed image. Another object of the present invention is to employ a new and improved multiple color display systems employing high-speed display panels, for reduced or eliminated quantizing error, to produce a very large number of colors from the display. SUBSTITUTESHEET Therefore, the principal object of the present invention is to provide a new and improved video display system and method of using it to produce large displayable images generated from conventional signals. Another object of the present image is to provide such a new and improved video display system, which is relatively inexpensive to manufacture and which is easily transmitted for convenient viewing purposes. Yet another object of the present invention is to provide such a new and improved video display system which produces a video image having a large number of discrete color shadings having relatively high luminance levels. Briefly, the above and further objects of the present invention are realized by providing a multiple color display system employing a high speed display panel adapted for positioning on a conventional photographic projector for displaying large video images. The high speed display panel is coupled to an interface unit for converting conventional television video signals into analog signals for driving a controller employing a modulation or duty cycle circuit coupled between the high speed display panel and a memory storage device which is driven by the interface unit. The controller also employs a format timing generator for formatting the television video signal so that it may be displayed in a conventional matrix array, such as a 640 by 480 matrix array, employed by the high speed display device. The system utilizes relatively inexpensive subassembly units, such as a video cassette recorder, a conventional photographic projector and screen, a high speed color enhancing interface controller and a high speed display device, such as an active matrix display panel adapted for positioning on the photographic projector. SUBSTITUTESHEET The above and further objects of the present invention are further realized by providing a controller employing a modulation or duty cycle circuit coupled between the high-speed display and a memory, which is driven by a computer. In order to increase greatly the number of color intensity levels, additional modulation or duty cycle circuits may be employed between the computer and the bit map memory. Such a technique enables a concentration of a large number of signals encoding digitally a desired one of a large number of color intensity levels, down to a much smaller number of such signals for storage in the memory. By employing the modulation circuit between the memory and the display, a high-speed concentration flow of information is achieved, thereby reducing the quantizing error, and desired high operating speed of the display. Briefly, the above and further objects of the present invention are realized by providing a multiple color display system employing a relatively low speed display panel, such as an LCD active matrix panel, adapted for positioning on a conventional photographic projector for displaying large video images. The display panel is coupled to an interface unit for converting conventional video signals into analog signals for driving a controller employing a pattern circuit coupled between the display panel and a memory storage device driven by the interface unit. The pattern circuit enables pixel elements in the low speed active matrix panel to be configured in a group, such as a group of four pixel elements. In this regard, the four pixel elements are combined to define a single composite pixel group where combinations of subpixels in each of the groups are selectively energized to 1 of 8 levels so that in excess of 24,000 different color shading may be exhibited by the composite pixel group. SUBSTITUTESHEET The controller also employs a format timing generator for formatting the video signal so that it may be displayed in a conventional matrix array, such as a 640 by 480 matrix array, employed by the low speed display device. The system utilizes relatively inexpensive subassembly units, such as a video cassette recorder, a conventional photographic projector and screen, a color enhancing interface controller and a display device, such as an active matrix display panel adapted for positioning on the photographic projector. Brief Description of Drawings The above mentioned and other objects and features of this invention and the manner of attaining them will become apparent, and the invention itself will be best understood by reference to the following description of the embodiment of • le invention in conjunction with the accompanying drawings, wherein: FIG. 1 is a pictorial, partially diagrammatic view of a television projection system, which is constructed in accordance with the present invention, and which is illustrated being employed in a television signal driven, overhead projection arrangement; FIG. 2 is a diagrammatic view of the system and the arrangement of FIG. 1; FIG. 3 is a block diagram of a high speed display drive unit of FIG. 1; FIG. 4 is a block diagram of a high speed color enhancing interface controller of FIG. 3; and FIG. 5 is a functional block diagram of a format timing generator of the high speed color enhancing interface controller of FIG. 3; FIG. 6 is a flow diagram of the operation of the microprocessor of the high speed display drive unit of FIG. 1; FIGS. 7A-B is a flow chart diagram of the operation of the format processor of the high speed color enhancing controller of FIG. 3; FIG. 8 is a schematic diagram illustrating a matrix array developed by the format timing generator of FIG. 5; and FIG. 9A is a horizontal formatting timing diagram for helping to understand the operation of the format timing generator of FIG. 5; FIG. 9B is a vertical formatting timing diagram for helping to understand the operation of the format timing generator of FIG. 5; and FIG. 10 is a flow chart diagram of the interrupt firmware of the high speed color enhancing controller of FIG. 3. FIG. 11A is a pictorial, partially diagrammatic view of a high speed color display system, which is constructed in accordance with the present invention, and which is illustrated being employed in a computer driven, overhead projection arrangement; FIG. 11B is a diagrammatic view of the system and the arrangement of FIG. 11A. FIG. 11C is a block diagram of a high speed color enhancing interface controller of FIG. 11A; FIG. 12 is a functional block diagram of one of the color enhancing units of the high speed color enhancing interface controller of FIG. 11C; FIG. 12A is a functional block diagram of a buffer latch and scaling generator of the unit of FIG. 12; FIG. 13 is a functional block diagram of a bit map memory array of the unit of FIG. 12; FIG. 14 is a functional block diagram of a scaling generator of the unit of FIG. 12; FIG. 15 is a functional block diagram of a video controller of the high speed color enhancing interface controller of the system of FIG. 11A; FIGS. 15A and 15B, when arranged as shown in FIG. 15C, illustrate a functional block diagram of a data format drivers of the video controller of FIG. 15; FIG. 16A is a functional block diagram of a video clock generator of the system of FIG. 11A; FIG. 16B is a functional block diagram of a pixel clock generator of the system of FIG. 11A; FIG. 17 is a block diagram of another high speed color enhancing interface controller, which is also constructed in accordance with the present invention, and which may be employed in a personal computer employing a high speed display; FIG. 18 is a block diagram of one of the color enhancing units in the high speed color enhancing interface controller of FIG. 17; FIG. 19 is a block diagram of the buffer latch and scale generator of the color enhancing unit of the unit of FIG. 18; FIG. 20 is a block diagram of the scaling generator of the unit of FIG. 18; and FIG. 21 is a diagrammatic view of the high speed color enhancing interface controller of FIG. 17, and the personal computer employing it. FIG. 21A is a pictorial, partially diagrammatic view of a television projection system, which is constructed in accordance with the present invention, and which is illustrated being employed in a television signal driven, overhead projection arrangement; FIG. 22 is a diagrammatic view of the system and the arrangement of FIG. 21A; FIG. 23 is a block diagram of a display drive unit of FIG. 21A; FIG. 24 is a block diagram of a color enhancing interface controller of FIG. 23; and FIG. 25 is a functional block diagram of a format timing generator of the color enhancing interface controller of FIG. 23; FIG. 25A is a block diagram of an enhancing unit of FIG. 24; FIG. 25B is a schematic diagram of the encoder logic for the enhancing unit of FIG. 25A; FIG. 26 is a flow diagram of the operation of the microprocessor of the display drive unit of FIG. 21A; FIGS. 27A-B is a flow chart diagram of the operation of the format processor of the color enhancing controller of FIG. 23; FIG. 28 is a schematic diagram illustrating a matrix array developed by the format timing generator of FIG. 25; and FIG. 29A is a horizontal formatting timing diagram for helping to understand the operation of the format timing generator of FIG. 25; FIG. 29B is a vertical formatting timing diagram for helping to understand the operation of the format timing generator of FIG. 25; FIG. 30 is a flow chart diagram of the interrupt firmware of the color enhancing controller of FIG. 23. FIG. 31 is a block diagram of a video controller of FIG. 24; FIG. 32 is a diagrammatic representation of a group of pixel element within an active matrix panel of FIG. 24; and FIG. 33 is another diagrammatic representation of a group of pixel elements within the active matrix panel of FIG. 24, illustrating a phase reversal. Best Mode for Carrying Out the Invention Referring to the drawings, and more particularly to FIG. 1, there is illustrated a television signal projection system 10, which is constructed in accordance with the present invention, and which is adapted for use as a video display system capable of displaying a very large full color screen image. Thus, the system 10 is a display projection system, and is employed in an overhead projection arrangement. As shown in FIG. 1, the system 10 is adapted for use in an arrangement employing a television signal generating source, such as a video cassette recorder 20 with a conventional video cassette (not shown) , and an overhead projection system 80. The video cassette recorder 20 supplies a conventional National Television Standards Committee (RF) (NTSC) signal (USA) or a PAL signal (Europe) as generated for displaying an image from a broadcast television signal source. The system 10 generally comprises a high speed display drive unit 11 for translating the conventional television video output signal from the video cassette recorder 20 into high speed video signals capable of hundreds of thousands of different color shadings and hues for display by a high speed display device, such as a thin film transistor active matrix liquid crystal display panel 16 for displaying color images produces from the high speed video signals. The drive unit 11 is also capable of translating the conventional computer video output signals produced by a personal computer 21 having a video drive module 26 as more fully disclosed in U.S. patent Serial No. 07/586,506 mentioned herein. In this regard, the drive unit 11 includes a high speed color enhancing interface controller 12 coupled by an interface unit 13 to either the video cassette recorder 20 or the v ^ deo drive module 26. The interface unit 13 is connected to SUBSTITUTE SHEET the recorder 20 and the module 26 by a pair of cables 13A and 13B respectively. Although in the preferred embodiment of the present invention, the drive unit 11 is shown interfaced to the video cassette recorder 20 it will be understood by those skilled in the art that other similar television signal generating sources, such as a video disc unit 22, a video camera 24 a television tuner 41 or a television receiver 43 having an antenna 43A could also be employed as shown in FIG. 3. The high speed color enhancing interface controller 11 is more fully described in U.S. patent application Serial No. 07/586,506 but includes a format timing generator 45 for formatting the television signal for displaying images on the high speed display device 16. The interface unit 13 converts the NTSC signal into an analog signal indicative of the red, green, blue color components of the display image along with the horizontal and vertical synchronizing or scanning signals HSYNC and VSYNC for generating a standard television scan raster in which the image is displayed. The high speed color enhancing interface controller 12 not only provides the necessary control functions to couple the interface unit 13 to the high speed display device 16 but also quantizes the conventional RGB analog signal so that a very large number of colors can be displayed by the active matrix panel 16. As best seen in FIG. 1, the high speed color enhancing interface controller 12 is coupled to the active matrix panel by a cable 25. The video cassette recorder 20 may be any conventional video cassette recorder, such as manufactured by SONY Corporation or RCA, Inc. which is capable of generating a standard NTSC signal when playing a video cassette with prerecorded video television image information. The video cassette recorder 20 can be connected to a CATV cable 41A or a standard television antenna for coupling line broadcast signals to the drive unit 11. The high speed display device 16 in cooperation with the video cassette recorder 20 and the overhead projector system 80 enables a user to view any prerecorded video television image information in a large projected image format. Considering now the overhead projection devii. ..0 in greater detail with reference to FIGS. 1 and 2, the projection device 80 generally includes a flat transparent projection surface 82 which is adapted to support the active matrix panel 16 for image projection purposes. The overhead projection device 80 includes an illumination bulb and a reflector shown generally at 83 (FIG. 2) for transmitting light through the panel 16. In order to collimate the light produced by the bulb and reflector 83 into the panel, a collimating Fresnel lens 85 is disposed on the underside of the active matrix panel 16. A focusing lens 87, preferably a Fresnel lens is disposed on the upper side of the panel 16 for converging the light exiting the panel 16 into an overhead projection optics assembly 88. In this regard the optics assembly 88 enables light passing through the panel 16 to be focused onto a projection screen or other suitable viewing surface (not shown) , for audience display purposes. While in the preferred form of the present invention the Fresnel lens 85 and 87 are disposed on the panel 16, it will be understood by those skilled in the art that the lens may be disposed in a case (not shown) for supporting the lens 85 and 87 in a spaced-apart manner from the panel 16. In this regard, the television signal projection system 10 and the method of using it, enables a full color display image to be projected on to any suitable viewing surface in a relatively easy and convenient manner using relatively inexpensive commercially available equipment which may be easily set up for viewing purposes. The active matrix thin film transistor liquid crystal panel 16 includes a pixel matrix array for generating a selected number of image elements in a 640 by 480 pixel array having a primary color arrangement (red, green, blue) for forming the prerecorded television video image stored on the video cassette cartridge (not shown) . It will be understood by those skilled in the art that the television video image may be generated from a television signal which is broadcast and received by a television receiver or generated by a television camera directly coupled to the interface unit 13 as shown in FIG. 3. The active matrix panel 16 is more fully described in copending U.S. patent application Serial No. 07/586,506 referenced herein. Table I As best seen in FIGS. 1 and 3, the system 10 is adapted for use with any conventional television signal source for producing a video image, such as the NTSC and VGA GRAPHIC signals. Table I specifies the HSYNC rate for two of the conventional video signal sources. As will be explained hereinafter in greater detail, the system 10 converts such signals, into re-formatted signals that are capable of driving the active matrix panel 16 having a 640 by 480 pixel array. FIG. 8 illustrates a typical display method of the present system 10. In this regard, for illustrative purposes a typical NTSC display format of 525 lines is shown with a 640 by 480 pixel array, shown generally at 801. The NTSC signal occupies a display area shown generally at 802 and consists of two interlaced 60Hz fields of 262.5 line each, combining to give a 30Hz, 525 lines of video information. Because the vertical resolution of the panel 16 is less than the vertical resolution provided by the NTSC signal, the present system 10 effectively fits the NTSC display configuration into the 480 lines of vertical resolution for the panel 16. The high speed controller 12 formats the NTSC signal by ignoring the first twenty two horizontal lines and the last twenty three horizontal lines in each frame of video information, resulting in 480 valid or displayable lines (525 lines - 22 lines - 23 lines = 480 lines) . This is an effective practice since the disregarded lines consist of the "overscan" (invisible) lines of the extreme top and bottom portions of the displayed image, which typically contains little or no meaningful video information. The width of the NTSC picture is also matched or formatted into a 640 pixel width for use by the panel 16. In this regard, the controller 12 adjusts the sampling rate of the video signal as will be explained hereinafter in greater detail. Considering now the interface unit 13 in greater detail with reference to FIG. 3, the interface unit 13 generally includes a signal converter 32 for converting the NTSC television signal from the video cassette recorder 20 into an analog RGB signal suitable for driving the controller 12. The NTSC television signal is coupled to the input of the signal converter 32 by a conductor 20A. As best seen in FIG. 3, the interface unit 13 has its input also coupled to the video drive module 26 whose output signals are already in an analog RGB format suitable for driving the controller 12. In this regard, the video drive module 26 in the personal computer 21 has five output signals red, green, blue, horizontal synchronization (HSYNC) , and vertical synchronization (VSYNC) coupled to the interface unit 13 on the cable 13B having a set of conductors 26A-E respectively. In order to enable a user to select between input signals from the video cassette recorder 20 and the video drive module 26, the interface unit 13 also includes an analog multiplex unit 34 and a microprocessor 36. The analog multiplex unit 34 is a conventional multiplexer allowing either the output signals from the signal converter 32 or the output signals from the video drive module 26 to be coupled to the high speed color enhancing interface controller 12. The microprocessor 36 determines which of the video source standards (VGA Graphics, NTSC, PAL, etc.) are to be coupled to the high speed color enhancing interface controller 12. In this regard, the microprocessor 36 allows only one of the source standard signal to be coupled to the controller 12. Signals are coupled from the analog multiplex unit 34 to the high speed controller 12 on a set of conductors 34A-E respectively. Once the microprocessor 36 determines the type of video standard to be supplied to the controller 12, the microprocessor 36 generates appropriate format data and commands on a command/data line 36A (FIG. 5) for establishing a proper sample rate and format of lines and pixels locations for driving the high speed active matrix unit 16. The microprocessor 36 also generates a control signal (MUX CONTROL) which switches the multiplex unit 34 to receive and pass to the controller 12, either the input signals from the signal converter 32 or the input signals from the video drive module 26. The control signal, MUX CONTROL is coupled to the multiplex unit 34 on a conductor 36B. The interface unit 13 also includes an infrared receiver 38 having a receptor 39 for receiving infrared signals from a remote infrared transmitter unit (not shown) . In this regard, a user may actuate the infrared transmitter unit for generating a signal which causes the microprocessor 36 to search for a different type of video source signal by switching the multiplex unit 34. The infrared receiver 38 is a conventional infrared receiver unit whose output is coupled to the microprocessor 36 on a conductor 38A. For the purpose of amplifying the low level audio signal that accompanies the video source signals, the interface unit 13 also includes an audio amplifier 33 having an output jack adapted to be connected to a conventional speaker, such as speaker 33A. The audio amplifier 33 is conventional, such as a model TDA1013B sold and manufactured by Signetics and described in the Signetic "Linear Data Manual," Volume 1 (1989) pages 7- 207. Considering now the signal converter 32 in greater detail with reference to FIG. 3, the converter 32 is of a type well known to those skilled in the art, such as a TDA 3330 unit manufactured by Motorola and described in the Motorola Linear/Interface Divides Data Book, page 9- 183 through 9-190, and in Motorola Application note AN1019D. Other type of converters for converting a PAL signal or a SECAM signal to an RGB signal are also well known. For example a combination PAL-SECAM-NTSC to RGB converter is available from SGS THOMSON at 1000 East Bell Road, Phoenix, Arizona under part number TEA 5640C as described in the SGS THOMSON Video IC's Data Book, pages 1211-1227. As the signal converter 32 is well known, it will not be described herein in greater detail. The output signals of the signal converter 32 are coupled to the analog multiplex unit 34 on a set of conductors 32A-E UTESHEET carrying the respective signals of red, green, blue, horizontal synchronization (HSYNC) and vertical synchronization (VSYNC) . Considering now the high speed color enhancing interface controller 12 in greater detail with reference to FIGS. 3 and 4, the high speed controller 12 is coupled between the active matrix panel 16 via cable 25 and the output of the analog multiplex unit 34. In this regard, the output signals from the analog multiplex unit 34, red, green, blue, horizontal synchronization and (HSYNC) vertical synchronization (VSYNC) are coupled to the input of controller 12 on a set of conductors 34A-E respectively. The high speed color enhancing interface controller 12 as best seen in FIG. 4, is fully described in copending U.S. patent application Serial No. 07/586,506 and generally comprises video controller 18, a set of color enhancing units 40, 42, 44, a memory controller 50, a format timing generator 45 and a video clock generator 48. The high speed color enhancing interface controller 12 is substantially identical to the high speed color enhancing controller described in copending U.S. patent application Serial No. 07/586,506 except that the controller 12 employs the format timing generator 45 instead of a pixel clock generator for formatting the television signal produced by the video cassette recorder 20 into a format that is acceptable for driving the active matrix panel 16. As the high speed controller 12 is substantially similar to the controller described in copending U.S. patent application Serial No. 07/586,506 only those aspects of the controller 12 that are different such as the format timing generator 45, will be described herein in greater detail. Considering now the format timing generator 45 in greater detail with reference to FIGS. 4 and 5, the format timing generator 45 generally comprises a programmable counter arrangement 46 for helping to format the video data to be stored in the controller 12, and a programmable pixel clock generator 47 for establishing a proper sampling rate based upon the type of video signal being coupled to the controller 12. As best seen in FIG. 5, the programmable pixel clock generator 47 is a conventional phase lock loop arrangement including a phase comparator 66, a low pass filter 67, a voltage control oscillator 68, and a programmable divider or divide by N counter 69. The programmable pixel clock generator 47 utilizes a reference clock signal coupled from the output of the analog multiplex unit 34. The reference signal is identified by the HSYNC signal and is coupled on a conductor 34D to the input of the phase comparator 66. An output pixel clock signal PXCLK for synchronizing the storing of the video data in the respective enhancing units 40, 42 and 44 is derived from the output of the voltage controlled oscillator 68. The sampling rate of the voltage controlled oscillator 68 is a function of the output of the programmable divider 69 as will be described hereinafter in greater detail. Considering now the programmable divider 69 in greater detail with reference to FIG. 5, the programmable divider 69 is programmed by the microprocessor 36 to help establish a proper sampling rate for storing the video data. The following example will be instructive. Assuming the video standard coupled to the high speed controller 12 is a NTSC standard requiring a sampling rate of 14.333 MHz or 910 samples for every line of display data. In this regard, a division of 910 is required to produce the desired sampling rate as shown by the following formula: HSYNC rate (NTSC standard) « 15.750 KHz Sampling rate = 15.750 KHz x 910 = 14.333 MHz. As will be explained hereinafter, 910 pixels are sampled per line, however 270 pixels of the 910 pixel samples represent overscan or retrace data and is disregard. In this regard, the first 135 pixel scan locations and the last 135 pixel scan location are disregarded with respect to the video data stored in the controller 12. The non-stored location are referred to as non-valid data. If the video standard is VGA graphics, for example, a division of 800 is required to produce a sample rate of 25.175 MHz. In this regard, the HSYNC signal is 31.47 KHz multiplied by 800 to produce the desired sampling rate of 25.175 MHz. Again, a given number of the 800 samples represent overscan or retrace data, i.e. 160 samples. These 160 samples are disregarded, the first 80 samples and the last 80 samples in every line. Referring now to FIG. 9A, a horizontal synchronization signal (HSYNC DATA) is shown generally at 901. The pixel location disregard for storage purposes as described above are shown as a non-valid data group 902 immediately before the HSYNC DATA signal 901 goes to a logical high level and a non-valid data group 903 immediately after the HSYNC DATA signal 901 goes to a logical high level. The pixel locations between groups 902 and 903 represents a valid data group 904 for displaying on the panel 16. For the purpose of further explanation, the HORIZONTAL RETRACE period occurs when the HSYNC DATA signal 901 is a logical high. Considering now the programmable counter arrangement 46 in greater detail with reference to FIG. 5, the programmable counter arrangement 46 generally comprises a retrace counter 73 for helping to establish the number of vertical retrace lines in a frame of displayed information, a pixel counter 75 for helping to establish SUBSTITUTESHEET the number of valid pixels in a single line of displayed information and for helping to establish the number of horizontal retrace pixels between lines of displayed information, a line counter 77 for helping to establish the number of valid lines in a frame of displayed information and a format processor or controller 79 for helping to coordinate the operation of the above mentioned counters in cooperation with the microprocessor 36. The format controller 79 under the control of the microprocessor 36 generates load signals LOAD R, LOAD P, and LOAD L which enables the loading of predetermined counts into the retrace counter 73, the pixel counter 75 and the line counter 77 for storing video data in each of the color enhancing units 40, 42 and 44 in a proper format for access and display on the display unit 16. The load signals, LOAD R, LOAD P and LOAD L are connected between the format controller 79 and the retrace counter, pixel counter 75 and line counter 77 on a set of conductors 79D, 79C and 79B respectively. A connector 36A connected between the microprocessor 36, the format controller 79, the programmable divider 69, and each of the above referenced counters 73, 75 and 75 allows command instructions and the predetermined formatting data to be transferred from the microprocessor 36 for establishing proper formatting. In order to enable the format processor 79 to generate the necessary control signal for enabling the memory controller 50 to store the video information and control memory operations, each of the counters 73, 75 and 75 provide terminal count signals TCR, TCP, and TCL to the format processor 79. The terminal count signals are conducted to the processor 79 on conductors 73A, 75B and 77B respectively. The format processor 79 enables the memory controller 50 to store all even field lines of SUB even memory addresses in the bit map memories and odd field lines at odd memory addresses. Storing video information in this manner, enables the video information to be retrieved from the bit map memories in each respective enhancing unit 40, 42 and 44 in a double scanning line format to generate the 480 vertical line resolution utilized by the high speed display device 16. In operation, the microprocessor 36 determines what video source is to be displayed and sends the proper divide by command to the programmable divider 69 via a command/data line signal on a conductor 36A. The operation of the microprocessor 36 will now be described in greater detail with reference to the flow diagram of FIG. 6 which illustrates the steps executed by the microprocessor 36. Referring now to the flow chart of FIG. 6, when power is applied to the drive unit 11, a CONFIGURE PROGRAM 600 begins in a START instruction 601 and proceeds to an instruction box 603 to set the default settings for the preferred types of video signal source, i.e. NTSC, PAL, VGA GRAPHICS, etc. After the default settings have been established, the program proceeds to a decision instruction 605 in which a determination is made whether the microprocessor is currently receiving an HSYNC signal from the analog multiplex unit 34. If there is no signal being received, the program proceeds to instruction box 607 to cause the analog multiplex control signal MUX CONTROL to be switched allowing the HSYNC and VSYNC signal from another video signal source to be coupled to the microprocessor 36. After the MUX CONTROL signal has been enabled the program returns to decision 605 to once again determine whether an HSYNC is being received from the next selected or enabled source. The above described procedure repeats itself until an enabled SUBSTITUTESHEET video signal source begins sending video synchronization information (HSYNC, VSYNC) . If it is determined at decision instruction 605 that an HSYNC signal is present, the program branches to instruction 612 to cause the microprocessor 36 to analyze the period and polarity of the HSYNC and VSYNC signals respectively. After execution of instruction 612, the program proceeds to instruction 614 where the exact video signal standard is determined by the microprocessor 36 using a conventional comparing technique. Once the video signal standard is determined, the program steps to instruction 616 which configures the programmable divider 69 and programmable counter arrangement 46 by causing the proper sample rate and format count data to be set for formatting purposes. In this regard, the format processor 79 causes the LOAD R signal, LOAD P signal and LOAD L signal each to be enabled, as will be explained hereinafter in greater detail, so that the format data supplied by microprocessor 36 on line 36A can be loaded into each of the counters 73, 75 and 77. Once the programmable divider 69 and programmable counter arrangement 46 has been configured, the program proceeds to decision instruction 618 which determines whether a user has changed the video standard. If the video standard has not been changed, the program waits at instruction 618 until the video source is changed. When the video source is changed, the proceeds to decision instruction 620 to determine whether the HSYNC signal is being received from the video source. If the HSYNC signal is present, the program goes to instruction 612 and proceeds as previously described. If a HSYNC signal is not present, the program will advance from instruction 620 to decision instruction 605 and proceed as previously described. SUBSTITUTE SHEET Considering now the operation of the format controller 79 in greater detail with reference to FIG. 7A and 7B, in order for the format controller to properly control the formatting of video data for storage in the various bit map memories in the enhancing units 40, 42 and 44, the microprocessor 36 must first determine (1) the number of vertical retrace lines required for the displayed information; 2) the number of valid or displayable lines in any given frame of displayable information; 3) the number of horizontal retrace pixels between each displayable line of information; and 4) the total number of valid or displayable pixels in each line of displayable information. The microprocessor 36 is preprogrammed to determine the type of video source signal as a function of the HSYNC and VSYNC signal produced by the video source and then to generate the proper counter arrangement 46 data for storing in each of the respective counters 73, 75 and 77 to achieve proper formatting. Table II illustrates the base count information required for converting a VGA and a NTSC video source signal. Table II * represen s pixe pairs, an mus e mu ip ied by two for actual number of displayable pixels as display consists of two interlaced 60Hz fields of 262.5 lines each, combined to give 525 lines of video information. SUBSTITUTESHEET Once the microprocessor 36 has determined the type of video source signal, the microprocessor 36 sends formatting commands and format data for utilization by the counter arrangement 46. Referring now to FIG. 7, the format processor 79 upon receiving a configuration or format command starts a FORMAT program 700. The FORMAT program 700 begins in a START instruction 701 and processed to a decision instruction 703 to determine whether a VSYNC signal from the video source is present. If the VSYNC signal is not present, the program waits at decision instruction 703. When the VSYNC signal occurs, the program proceeds to an instruction box 704 to start a vertical retrace period or a new frame by resulting the time counter 77. The program then goes to decision box 705 to determine whether a HSYNC signal is present. If the HSYNC signal is not present the program waits at box 705. When an HSYNC signal occurs the program advances to instruction box 707 to cause the line counter 77 to be incremented. After the line counter 77 has been increment, the program proceeds to a decision instruction 708 to determine whether a valid number of retrace line has occurred. If a valid number of retrace lines has not occurred, the program returns to decision box 705 and proceeds as previously described. In this regard, it should be understood that the first twenty two horizontal lines of data will be disregarded as best seen in FIGS. 8 and 9. If a valid number of retrace lines has occurred, the program advances to instruction 709 to reset the line counter 77. Once the line counter 77 has been reset, the program proceeds to instruction 710 to start a horizontal retrace period for generating the first valid line of the 480 lines to be stored. The program then advances to decision instruction 711 to wait for the next HSYNC signal. If the HSYNC signal is not present, the program SUBSTITUTE SHEET waits at decision instruction 711. When the HSYNC signal occurs, the program advances to instruction 713 to increment the pixels counter 75. The program then proceeds, to decision instruction 715 (FIG. 7B) to determine whether a valid number of retrace pixels has occurred. If a valid number of retrace pixels has not occurred, the program returns to instruction 713 (FIG. 7A) and continues as previously described. If a valid number of retrace pixels has occurred, the program advances to instruction 716 to start storing valid video data into the bit map memories of the enhancing units 40, 42 and 44. In this regard, at instruction box 716 the pixel counter 75 is reset and the row and column count is set for utilization by the memory controller 50. After the row and column count has been set, and the pixel counter 75 reset, the program advances to instruction box 717 transfer the row and column count to the memory controller, enables the latching of the even and odd pixels and generates the memory control signals to enable the storing of data into the bit map memories. The control signals (such as the odd enable and even enable signals) for storing data int the individual bit map memories of enhancing units 40, 42, and 44 are more fully described in copending U.S. patent application Serial No. 07/586,506. As will be explained hereinafter in greater detail, the memory control signals include an interrupt signal when generated by the video controller 18 whenever the video controller 18 requires access to the bit map memories in the enhancing units 40, 42 and 44. In this regard, the Request New Data signal generated by the video controller 18 cause the storing of data via the format timing generator 45 to be temporarily disabled while a line of displayable video data is read from the enhancing units 40, 42 and 44 for display purposes. The interrupt signal from the format timing SU generator 45 via the memory controller 50 and the memory control store data lines. After the transfer of the data into memory, the program then proceeds to instruction 721 to increment the pixel counter 75. After the pixel counter 75 has been incremented the program advances to a decision instruction 723 to determine whether a valid number of pixels has been generated by the pixel counter 75. If a valid number has not occurred, the program returns to instruction 717 and repeats the above described sequence. When a valid number of pixels occurs, the program goes from decision instruction 723 to instruction box 725 to increment the line counter 77. After the line counter 77 has been incremented, the program advances to decision instruction 727 to determine whether a valid number of lines has occurred. If the frame is not completed, the program returns to decision instruction 711 (FIG. 7A) to start another line of information as previously described. If the frame is completed, the program goes to instruction 730 and reset the line counter 77. After counter 77 has been reset, the program returns to instruction 703 to wait for the next VSYNC signal. From the foregoing, it should be understood that the format controller 79 in cooperation with the microprocessor 36 enables a conventional video signal such as a NTSC signal having 525 lines of horizontal video information to be formatted for display into 480 lines of horizontal video information as used by the high speed display device 16. More particularly, the microprocessor 36 and controller 79 cause the 525 lines of horizontal information for each displayable frame of video information to be centered for display in the 640 x 480 pixel array of panel 16. In this regard, the first twenty two lines of horizontal data are blanked and the last twenty three lines of horizontal data are blanked so SUBSTITUTE SHEET that only 480 lines of the horizontal information for each displayable frame of video information is displayed. This is effective in practice since the majority of the disregarded horizontal lines consists of "overscan" or "invisible" lines and the extreme top and bottom of the displayable frame usually contains little or no displayable video information. For example, referring to FIG. 9B, a timing diagram is illustrated for horizontal line formatting. In this regard, a group of non-valid lines is shown generally at 910 and a group of valid lines are shown generally at 920. The group of non-valid lines 910 are disposed immediately before and immediately after the VSYNC signal goes to a logic high. The first 23 lines before the VSYNC signal and the first 22 lines after the VSYNC signal represent non-valid lines. The VSYNC signal is indicative of the vertical retrace lines. In a similar manner the width of the displayable frame of video information is matched to the 640 lines of the vertical information for each frame by adjusting the sampling rate of the video signal. The sampling or PXCLK rate is set, then a horizontal divisor (ratio of PXCLK to HSYNC rate) is set using the programmable divider 69 to match the horizontal frequency of the television signal produced by the video source. As the signals from the video drive module 26 already have a proper format, the above described formatting technique is not required. In this regard, the microprocessor 36 is coupled to the format timing generator 45 to select the desired format for the video drive module 26. Considering now the memory controller 50 in greater detail with reference to FIG. 11, the memory controller 50 controls the storing and reading of video data from each of the enhancing units 40, 42 and 44. In this regard, the memory controller 50 is more fully described in copending U.S. patent application Serial No. 07/586,506 and will not be described hereinafter in greater detail except for the interrupting of the format processor 79 (FIG. 5) via an INTERRUPT firmware program 1100 whenever the bit memories of the enhancing units 40, 42 and 44 are accessed by the video controller 18. Considering now the video controller 18 in greater detail with reference to FIG. 4, the video controller 18 includes a row counter and a column counter which generated the H.S. HSYNC and H.S. VSYNC signals used by the panel 16. The counters also control the retrieval of the video data from the enhancing unit 40, 42 and 44. In this regard, whenever the row counter reaches its terminal count, it generates the H.S. VSYNC signal. Similarly, whenever the column counter reaches its terminal count it generates the H.S. HSYNC signal. The video controller 18 is more fully described in copending U.S. patent application Serial No. 07/586,506 and will not be described hereinafter in greater detail except with relation to the INTERRUPT program 1100. More particularly, as video data is loaded into each respective SAM of the enhancing units 40, 42 and 44 on a line by line basis, it should be understood that cooperation is r quired between the format timing generator 45 and its formatting of data for storage into the enhancing units 40, 42 and 44, and the video controller 18 and its reading of the formatted data from the bit map memory in the enhancing units 40, 42 and 44. The above-mentioned cooperation or handshaking is accomplished through the INTERRUPT firmware program 1100. Considering now the INTERRUPT program 1100 in greater detail with reference to FIGS. 4 and 11, whenever the video controller 18 requires video data for display purposes, the video controller 18 generates an interrupt control signal on the request new data line buss between the video controller 18 and the memory controller 50. The interrupt control signal starts the INTERRUPT firmware program 1100. In this regard, the INTERRUPT firmware program 1100 starts at box 1101 and advances to instruction box 1103 which halts or interrupts the storing of data into the bit map memories of the enhancing units 40, 42 and 44. The program then advances to instruction box 1105 which enables the memory address lines from the row counter in the video controller 18 to be placed on the address buss for the enhancing units 40, 42 and 44. The address buss for the enhancing units 40, 42 and 44 is a common address buss shared by the format timing generator memory addressing and the video controller memory addressing. After the memory address lines have been enabled, the memory controller 50 generates the RAS signal at instruction box 1107 transferring the row counter into the VRAMs or bit map memories of the enhancing units 40, 42 and 44. The program then advances to instruction box 1109 which disables the memory address buss from being controlled by video controller 18. The program then proceeds to instruction box 1111 and outputs all zeros onto the address buss via the memory controller 50. The program then goes to instruction 1113 where the memory controller enables the CAS signal to cause the column position to be coupled to the bit map memories of the enhancing units 40, 42 and 44. The program then proceeds to instruction 1115 and loads the video data into the respective SAMs, of the bit map memories in each enhancing unit 40, 42 and 44 for access by the video controller 18. In this regard, it should be understood that an entire row of video data is loaded into the respective SAMs for display purposes. After the video data has been loaded into the SAMs, the program advances to instruction 1117 to acknowledge that the loading of the SAM has been completed which is indicative that a new line of data may now be displayed on the high speed active matrix panel 16. More particularly, the H.S. HSYNC produced by the column counter is driven to a logical low level and remains low until the column counter in the video controller 18 reaches its terminal count indicating that another new line of video data is required. When another line of data is required, another interrupt signal is generated. It should be understood that when the request new data signal is generated by the video controller 18, the H.S. HSYNC goes to an active level. After the acknowledgement of loading the SAMs is completed, the program goes to instruction 1119 which returns control of the memory address buss to the format timing generator 45. The program then advances to instruction 1121 which enables the row and column count in the format timing generator 45 to be set as previously described. The program then proceeds to box 1123 which causes the FORMAT program 700 to be resumed from where it was interrupted. While the preferred embodiment of the present invention is shown as adapted for use with a conventional overhead projector it will be understood by those skilled in the art that other types of photographic projector systems, could also be used with the present inventive system. Referring to the drawings, and more particularly to FIG. 11A, there is illustrated a high speed color display system 10A, which is constructed in accordance with the present invention, and which is adapted for use as a video color display system capable of displaying a very large number of, different color shadings. Thus, the system 10A is a high speed video color display system, and is employed in a computer-driven overhead projection arrangement, a direct view system or any similar type of SUBSTITUTESHEET color display system, such as a high speed color monitor, or a direct view display panel. As shown in FIG. 11A, the system 10A is adapted for use in an arrangement employing a conventional personal computer 12A having a video drive module 14A, and an overhead projector system 80A. The system 10A generally comprises a high speed color enhancing interface controller 11A for translating conventional computer video output signals from the video drive module 14A into high speed video signals capable of producing a large number, such as hundreds of thousands of different color shadings and hues, for display by a high speed display device, such as a thin film transistor active matrix liquid crystal display panel 16A for displaying color images produced from the high speed video signals. The video drive module 14A supplies a convention RGB analog video signal including horizontal and vertical synchronizing signals to the color enhancing interface controller 11A. The controller 11A not only provides the necessary control functions to interface the personal computer 12A to the high speed display device 16A, but also quantizes the conventional RGB analog signal so that a minimum of approximately 256,000 (2 6 + 6 + 6 ) colors can be displayed by the active matrix panel 16A. The personal computer 12A may be an Apple MAC II personal computer which includes a computer processing unit 15A to which data and commands may be entered via a keyboard unit 17A. The high speed display device 16A in cooperation with the overhead projector system 80A enables large audience viewing of the computer generated information. Considering now the overhead projection device 80A in greater detail with reference to FIGS. HA and 11B, the projection device 80A generally includes a flat transparent projection surface 82A which is adapted to support the active matrix panel 16A for projecting purposes. The overhead projection device 80A includes an illumination bulb and reflector shown generally at 83A (FIG. 11B) for transmitting light through the panel 16A. In order to collimate the light produced by the bulb and reflector 83A into the panel 16A, the device 80A also includes a collimating Fresnel lens 85A disposed below the transparent surface 82A. The active matrix panel 16A also includes a focusing lens 87A, preferably a Fresnel lens for converging the light exiting the panel 16A onto an overhead projection optics assembly 88A. In this regard, the projection assembly 88A enables light passing through the panel 16A to be focused onto a projection screen or other suitable surface (not shown) , for audience display purposes. While in the preferred form of the present invention, the lens 87A is disposed on the panel 16A, it will be understood by those skilled in the art that the focusing lens may also be disposed in a projection assembly, such as assembly 88A. In this regard, the high speed color system 10A and method of using it, enables the number of colors displayed by the active matrix panel 16A to be greatly expanded from a conventional eight color system based on an RGB video signal to an extremely large number of colors, approaching 2 18 simultaneous colors. It will be understood by those skilled in the art that, although the preferred form of the present invention includes an Apple II computer generated RGB analog video drive source, other conventional computer video drive systems, such as the IBM Enhanced Graphic Adapter ("EGA") , a CGA system, a VGA system or an RGB digital system, may be employed, in accordance with the present invention. SUBSTITUTESHEET The active-matrix thin-film transistor liquid crystal display panel 16A includes a pixel matrix array for generating a selected number of image elements in a primary color arrangement (red, green, blue) for forming the computer generated color image. Each pixel location or element in the pixel matrix array, includes a set of three subpixel components, one for each of the corresponding primary colors of red, green and blue respectively. In this regard, the active matrix panel 16A is capable of producing a full color image having at least 250,000 different color shading and hues. The active matrix panel 16A is conventional and manufactured by such suppliers as Hitachi, Sharp, Toshiba and Seiko Instruments. While the preferred form of the present invention is designed to be used with an active matrix panel in a color additive configuration, it will become apparent to those skilled in the art that the present invention may be employed in a color subtractive configuration. In this regard, each pixel element in the subtractive configuration is normally fully actuated and then modulated off and on to produce the desired levels of shading. In such a color subtractive system, a complementary color arrangement (magenta, yellow, cyan) would be employed. Considering now the high speed color enhancing interface controller 11A in greater detail with reference to FIG. 11C, the controller 11A generally includes a video controller 18A for interfacing the personal computer video drive module 14A to the active matrix panel 16A and, a set of three color enhancing units 20AA, 22A and 24A for quantizing the RGB analog video drive signals from the computer video drive module 14A into a set of digital signals for producing up to approximately 256,000 different color shadings and hues. In accordance SUBSTITUTESHEET with the present invention, the video controller 18A causes each of the pixels in the active matrix panel 16A to be switched rapidly on and off to generate a color image by a color additive blending process, without causing patterning or flicker in this displayed image. The high speed panel 16A operates at a much higher speed than the personal computer 12A. Therefore, the controller 11A serves as an interface between the slower computer, and the faster display 16A. As mentioned, previously, the controller 11A also serves the function of increasing greatly the number of different levels of color shadings and hues, without substantial patterning or flicker distortions of the resulting image displayed by the panel 16A. In order to translate or convert the slower conventional RGB analog signals into quantized digital signals acceptable for driving the active matrix panel 16A, the controller 11A includes a memory controller 40A for permitting the quantized digital signals to be stored and retrieved from the enhancing unit 20AA, 22A and 24A. In this regard, the controller 11A also includes a pair of clock generators, a slower pixel clock generator 26AA for helping to facilitate the storing of video digital data in the units 20AA, 22A and 24A at a slow rate and a video clock generator 28A for enabling the stored quantized data to be retrieved at a substantially higher rate. In this regard, the enhancing units 20AA, 22A and 24A permit the refresh rate of the RGB video data from the personal computer 12A to be accelerated by converting the RGB analog signals into a set of quantized digital signals, storing the converted signals at a slow rate, and subsequently permitting the retrieval of the quantized data therefrom at a much faster rate for utilization by the display 16A. SUBSTITUTE SHEET In operation, the personal computer 12A via its video drive module 14A generates conventional RGB video signals indicative of computer generated colored images composed of a large number of pixel elements. The RGB video analog signal is indicative of three individual primary color components (red, green, blue) for each pixel element, including the respective brightness of each component for reproducing a color image. The computer generated signals also include corresponding control signals, namely, horizontal sync (HSYNC) and vertical sync (VSYNC) indicative of a pixel matrix address for selecting the individual pixel elements to reproduce the desired color image. For the purpose of simplifying the block diagrams of FIG. lie, memory addressing writing line, memory addressing reading lines, and memory control lines are multiple leads, but they have been shown as a single lines from the memory controller 40A to each of the color enhancing units 20AA, 22A and 24A. The control signal HSYNC produced by the video drive module 14A is coupled to the pixel clock generator 26AA in order to generate the pixel clock signal (PXCLK) for controlling the storage of the RGB video data into the bit map memory arrays, such as a memory array 30A of the color enhancing unit 20AA, as shown in FIG. 12. The pixel clock generator 26AA is a conventional phase lock loop circuit and is well known to those skilled in the art. Considering now the pixel clock generator 26AA in greater detail with reference to FIG. 16B, the pixel clock generator 26AA is a conventional phase lock loop arrangement including a phase comparator 66A, a low pass filter 67A, a voltage control oscillator 68AA, and a divider 69A. The reference clock signal HSYNC received from the video drive module 14A is coupled to the input to the phase comparator 66A. The output pixel clock signal PXCLK is derived from the output of the voltage control oscillator 68AA. As will be explained hereinafter in greater detail, the active matrix panel 16A requires digital RGB video data in order to display information properly. More particularly, the digital RGB video data must be assembled into two 8-bit bytes of subpixel component information. For this purpose, in order to drive a selected set of corresponding subpixel components from the data stored in the bit map memory arrays, such as the array 30A (FIG. 12) , the video controller 18A and video clock generator 28A cooperate together for switching rapidly a selected set of subpixel components into their respective color-producing states or conditions for each pixel location or element. Considering now the assemblying and transferring of data to the active matrix panel 16A in greater detail, the video controller 18A couples the RGB digital signals stored in the bit map memory arrays, such as array 30A, to the active matrix panel 16A so that each subpixel component is turned on and off, to cause a viewer to perceive distinct color shadings and hues of a displayed image visually. As best seen in FIG. 11C, each of the color enhancing units convert one color element of the RGB video analog signal into a converted binary digital signal indicative of a weighted intensity or shading level of the primary color to be produced at the addressed pixel location in the active matrix panel 16A. In this regard, unit 20AA converts the red component of the RGB signal for all the red subpixels components, unit 22A converts the green component of the RGB signal for all the green subpixels components, and unit 24A converts SUBSTITUTE SHEET the blue component of the RGB signal for all the blue subpixels components in the active matrix panel 16A. Considering now the operation of the controller 11A in greater detail, each of the color enhancing units 20AA, 22A and 24A convert an associated color component portion of the RGB analog signal into an 8-bit digital signal which is subsequently quantized into a 3-bit digital signal. As will be explained hereinafter in greater detail, each three bit digital signal is assembled into a six bit byte for storage and subsequent retrieval from the associated enhancing unit. In this regard, it should be understood that the six bit byte is indicative of the color shading or hue of one primary color for two pixel locations. For example, the first 3-bit group would be for the red component of pixel location 1 while the second 3-bit group would be for the red component of pixel location 2. The memory controller 40A in cooperation with the video controller 18A and video clock generator 28A enables the stored quantized data to be rapidly and asynchrously retrieved from each color enhancing unit. In this regard, as each 6-bit byte is retrieved from storage, the associated color enhancing unit further reduces or scales each three bit grouping to a single bit binary single. Each single bit binary signal is than latched into the video controller 18A with its associated color component single bit binary signals from the other color enhancing units to form a color grouping (red, green, blue) for a given pixel location. As will be explained hereinafter, each subsequent grouping of three bits for each pixel location is also latched into the video controller 18A until a minimum of nine bits of video data has been stored. The first eight bits of the assembled BSTITUTE SHEET data is then transferred to the active matrix panel 16A for display purposes. The video controller 18A controls the assembly of the video data from the color enhancing units 20AA, 22A and 24A so that the quantized data is properly assembled and transferred to the active matrix panel 16A. From the foregoing, it should be understood that the video controller 18A actively assembles two 8-bit bytes of video data, and even bit grouping and an odd bit grouping because data is retrieved from the color enhancing units in a single 6-bit byte which is indicative of two 3-bit groupings as previously explained. Considering further the operation of the controller 11A, the quantized binary digital signals in each one of the enhancing units 20AA, 22A and 24A are synchronously coupled to the video controller 18A for each pixel location and interfaced to the active matrix panel 16A so that the selected pixel or picture elements may be turned off and on, for predetermined periods of time, to produce the desired shading in each of the primary colors. In operation, the individual ones of the RGB color component signals are into an 8-bit digital signal for quantizing purposes. In this regard, the digitized signals are coupled to a buffer and scaling generator 35A which quantizes selected portion of the digital signals to produce a 3-bit digital signal indicative of a shading level of color. The 3-bit digital signal is then stored so that it may be repeatedly retrieved at a sufficiently fast rate to enable the high speed display device 16A to be properly refreshed for visual display purposes. In order to reduce the 3-bit quantized signal into a single bit binary signal for driving the high speed display device 16A, the quantized digital signal is retrieved from storage and compared with a repetitive set of randomly generated digital signals in scaling generator 42A. The repetitive set of digital signal are arranged in a predetermined order and are indicative of a corresponding fixed or predetermined weighted intensity or shading level of color. The randomly generated digital signals are compared against the quantized digital signals to determine whether the numerical value of the quantized signals is greater than the numerical value of a randomly generated signal. If the quantized digital signal is greater than the repetitive digital signal, a single bit binary signal is generated for that subpixel component causing the addressed subpixel component of the corresponding pixel location address to be switched on and off to produce the desired color shading, without introducing any substantial flicker in the displayed color image and without causing unwanted and undesired patterning in the displayed image. In summary, the predetermined sequence of the repetitive digital signal has an averaging effect over a series of image frames to substantially eliminate flicker as described in the above-mentioned parent patent application as well as patterning associated with repetitive "beats" in the displayed image. In addition, scaling the converted analog video signal eliminates or at least substantially reduces both contouring or splotchiness caused by the quantizing error associated with approximations of digital pictures. Considering now the interface controller 11A in greater detail with reference to FIGS. 11C and 12, the three enhancing units 20AA, 22A and 24A are coupled to the R, G and B video drive signals respectively generated by the personal computer 12A video drive module 14A. As the circuitry and operation of each of the enhancing units 20AA, 22A and 24A are substantially identical only SUBSTITUTESHEET the red color enhancing unit 20AA will be described hereinafter in greater detail. Considering now the enhancing unit 20AA in greater detail with reference to FIG. 12, the enhancing unit 20AA comprises a translating arrangement 32AA that generally includes a conventional analog to digital converter 34AA for translating the red component of the video analog signal into an 8-bit digital signal that is indicative of a weighted intensity or shading level of a single color such as red, and a buffer latch and scaling generator 35A for quantizing a selected portion of the lower order bits of the digital signal into a single digital signal shown as g * (FIGS. 12 and 12A) . In this regard, the quantizing of the lower order bits of the digital signal, controls the hue of the red color component of the RGB video signal so that it may be properly mixed with the other color components (green hues and blue hues) produced by the enhancing units 22A and 24A respectively to produce over a quarter of a million different colors for display purposes. The buffer latch and scaling generator 35A temporarily storing the two most significant bits of the digital signal, so that data moving through the enhancing unit 20AA can be properly synchronized and stored in the bit map memory array 30A. The enhancing unit 20AA also includes the bit map memory array 30A for storing the red hue data and a sealing generator 42A for reducing the red hue data to a sample binary bit for each of the red subpixel components in the active matrix panel 16A. Considering now the buffer latch and scaling generator 35A in greater detail with reference to FIGS. 12 and 12A, the scaling generator 35A includes a pair of buffer registers 71A and 73AA for temporarily storing the 6 most significant bits of the 8-bits of video digital data. As best seen in FIG. 12, the two least significant bits of the 8-bit digital signal indicative of the red color components are insignificant for quantizing purposes and are thus, not coupled to the buffer and scaling generator 35A. As best seen in FIG. 12A, the output video digital data from the analog to digital converter 34AA is latched into buffers 71A and 73AA respectively by the PXCLK signal generated by the pixel clock generator 26AA. The output of the buffers 71A and 73AA are connected to a secondary buffer latch 72A and a bit quantizing arrangement 74A respectively. In this regard, the bit quantizing arrangement 74A converts the 4-bit output signal of buffer 73AA into a single bit binary signal while the secondary buffer 72A continues the temporary storage of the two most significant bits of the video data. Considering now the bit quantizing arrangement 74A in greater detail with reference to FIG. 12 , the bit quantizing arrangement 74A generally comprises a comparator circuit 75AA and a signal generator circuit 76A whose output signals change in a predetermined randomly sequenced manner on every pixel clock signal (PXCLK) . In this regard, the output signals of the signal generator 76A are arranged to quantize the 4-bit video digital signal from latch buffer 73AA into a single bit binary signal based upon a predetermined randomized sequence that effects quantization with substantially less quantizing errors. In order to convert the 4-bit output signal of buffer 73AA into a single bit binary single, the comparator circuit 75AA is coupled between the 4-bit output signal generator 76A and the 4-bit output signal of the buffer 73AA. Comparator circuit 75AA determines whether the numerical value of the 4-bit digital output signal (signal B) of buffer 73AA exceeds the numerical SUBSTITUTESHEET value of the 4-bit digital output signal (signal A) of generator circuit 76A, and generates a single bit digital output signal (R g *) whenever the numerical value of signal B exceeds the numerical value of signal A. The output signal (signal R 5 * ) of the comparator circuit 75AA is synchronized with the pixel clock signal (PXCLK) for storing the quantized video data signal R5 * along with the two most significant bits (R7 and R6) of the converted signal into the bit map memory array 30A. Considering now the signal generator circuit 76A in greater detail with reference to FIG. 12A, the signal generator 76A has a predetermined counting sequence for 16 levels of quantizing. The counting sequence of the signal generator 76A permits the quantized signals to be average over a large number of frames of pixel data without introducing a significant amount of quantizing errors. In this regard, the counting sequence could be substantially identical to that of the signal generator described in U.S. patent application Serial No. 07/472,668 which may be referenced for a fuller explanation of the counting sequence. In order to facilitate the orderly converting, scaling and storing of the analog video data signal indicative of the red color component into the bit map memory array 30A, a pixel clock signal produced by the pixel clock generator 26AA sequentially steps the data into the array 30A. For example, on a first pixel clock, the analog data signal is converted into a set of digital signals (R0-R7, FIG. 12) by the analog to digital converter 34AA. On a second pixel clock, the converted data is latched by buffers 71A and 73AA. On the next pixel clock the data is simultaneously scaled and latched by the quantizing arrangement 74A and the buffer latch 72A. On the next pixel clock, the latched and quantized data is transferred to and stored in the bit map memory array 30A. In order to accelerate the transferring of the red hue data stored in the bit map memory array 30A to the active matrix panel 16A, the data in the memory array 30A is stored and retrieved in one 6-bit byte having 3-bits of even data and 3-bits of odd data. In this regard, the bit map memory array 30A includes a VRAM memory 85A having a pair bit map memory units 37A and 34AA respectively (FIG. 13) for storing the two most significant bits (R7 and R6) of the 8-bit digital red color signal as well as the quantized single bit value (R5*) for the next four most significant bits of the 8- bits of digital data. The retrieved data from the bit merge memory array 30A is designated as R7E-R5E and R7φ and R5φ respectively (FIGS. 12 and 13). Also, in order to accelerate the transferring of the red hue data stored in the bit map memory array 30A to the active matrix panel 16A, the video clock generator 28A produces a very fast memory access clock signal (CLKA) for helping to pack the retrieved video data into 16 bit bytes and a slower video clock signal (CLKB) for transferring the 16 bit byte video data to the active matrix panel 16A. In this regard, the memory access clock signal CLKA is used to read the red hue component data from the array 30A and to continue stepping the data into the video controller 18A. When the red hue component data is read from the memory array 30A, it is transferred to the scaling generator 42A (FIGS. 12 and 14) for eliminating patterning and flickering in the red hue components of the displayed image. Considering now the memory array 30A in greater detail with reference to FIG. 13, the memory array 30A includes the VRAM memory 85A having the pair of bit map SUBSTITUTE SHEET memory units 37A and 34AA for storing the quantized video data. The VRAM memory 85A is a 256K x 4 VRAM Mos memory such as manufactured by Texas Instrument under part number TMS44C251-10 and more particularly described in a Texas Instrument book entitled "Mos Memory Data Book" (1989) Section IV pages 79-118. The VRAM memory 85A generally includes a set of 6 DRAM's in a 512 x 512 x 4 configuration coupled to a corresponding set of SAM's having a 512 x 1 x 4 configuration. In this regard, it should be understood that although the bit map memory array 30A is shown including a full VRAM memory it will be understood that a single VRAM memory could be used for all the bit map memory arrays in controller 11A. As best seen in FIGS. 12 and 13, the memory array 30A is coupled between the buffer and scaling generator 35A and the scaling generator 42A and is utilized for storing the quantized video data produced by the buffer latch and scaling generator 35A. In order to assembly subpixel data for two pixel elements bytes, the memory array 30A includes a pair of buffer latches 82A and 84A for temporarily storing the video data produced by the buffer and scaling generator 35A. The mem.ry controller, shown generally at 40A, provides all the control signals for transferring data into and out of the various bit map memory arrays, such as array 30A. In this regard, the memory controller 40A generates a pair of signals synchronized with the horizontal sync signal (HSYNC) and pixel clock (PXCLK) for loading video data alternately first into latch 82A and then into latch 84A. Once two three-bit bytes of data have been loaded into the latches 82A and 84A the memory controller 40A generates a write control signal for causing the latched data to be stored into a selected portion of the VRAM T memory 85A of the memory array 30A. It should be understood loading the data in a 6-bit bytes enables the stored data to be retrieved from the memory arrays at a much faster rate. Considering now the scaling generator 42A in greater detail with reference to FIGS. 12 and 14, the scaling generator 42A includes an even bit unit 44A and an odd bit unit 48A. Each of the units 44A and 48A are substantially identical so only even bit unit 44A will be described hereinafter in greater detail. As best seen in FIG. 14, the even bit unit 44A includes an even bit buffer latch 45A for temporarily storing the three even bit output signals R7E, R6E, and R5E of the bit map memory array 30A. The output of latch 45A is connected to a scaling arrangement 47A that converts the 3-bit output signal from memory array 30A into a single bit binary signal shown as R e that helps to produce the desired shading level of the red component of the subpixel elements without introducing any substantial flicker in a selected pixel element. The scaling arrangement 47A includes a comparator 47AA and a signal generator 48BA for generating a single bit binary output signal (R e ) . The scaling arrangement 47A is similar to the quantizing arrangement 74A discussed earlier herein except that it compares the 3 bit output signal from latch 45A with a 3-bit binary signal produced by signal generator 47BA. In this regard, the signal generator has a different counting sequence than generator 76A, but its function is substantially similar; i.e., to reduce the 3-bit signal to a single bit binary signal. As the 3-bit signal generator is more fully described in the aforementioned patent application it will not be described in greater detail. SUBSTITUTESHEET Considering now the video controller 18A in greater detail with reference to FIGS. 11C and 15, the video controller 18A generally includes a data format driver 51A for arranging the red, green and blue color hue components received from translators 20AA, 22A and 24A in proper format for driving the active matrix panel 16A as well as a row counter 53A and a column counter 55A for generating the high speed vertical sync and high speed horizontal sync signals respectively. As best seen in FIG. 15, the row counter 53A also generates the memory address signals for the memory controller 40A as well as the high speed vertical sync signal for the active matrix panel 16A. The row counter 53A is coupled to the column counter 55A and is synchronized with the high speed horizontal sync signal generated by the column counter 55A. In this regard, the high speed horizontal sync signal increments the row counter 53A on every high speed horizontal sync signal. The column counter 55A also generates a request data line signal for the memory controller 40A in order to retrieve data from the bit map memory arrays, such as array 30A. In operation, the video controller 18A operates synchronously from the conventional video output signals produced by the personal computer 14A. In this regard, the video controller 18A, accesses the quantized video data in enhancing units 20AA, 22A and 24A at a rate that is sufficiently fast that any translation data gaps that may occur between storing and reading data to and from the bit map memory arrays cannot be visually perceived by a viewer of the display system. Referring now to FIGS. 11C, 12 and 12A, RGB video data from the computer video output 14A is sequentially stepped into the enhancing units 20AA, 22A and 24A, converted into an 8-bit digital signal, and then quantized into 3-bits of data for each respective primary SUBSTITUTESHEET color. The 3-bits of data for each primary color is then stored into the respective bit map memory arrays, such as array 30A in enhancing unit 20AA, synchronously of the high speed memory access clock signal (CLKA) generated by the video clock generator 28A. Once the quantized data has been stored in the respective bit map memory arrays, the video controller 18A generates a request for new line data signal via the column counter 55A and a memory address via the row counter 53A. These signals are coupled to the memory arrays, such as array 30A, which respond by transferring the data stored in the selected bit map memory locations to the scaling generator 42A (FIGS. 12 and 14). Subsequently, on each memory access clock signal (CLKA) , the accessed data is stepped through the generator 42A (FIG. 14) until a pair of single on/off color hue component signals (R e and R g ) are generated for the selected pixel addresses. As will be explained hereinafter in greater detail, the pair of on/off color hue component signals R e and R 0 are assembled with corresponding signals G e , B e and G 0 , B 0 respectively to form two separate subpixel groupings (R e , G e , B e and R 0 , G 0 , B 0 ) for two separate pixel elements in the pixel array of the active matrix panel 16A. The separate red, green and blue color hue component signals from each respective enhancing units are then latched into the data format driver 51A (FIG. 15A) which sequentially formats the color hue data for transfer to the active matrix panel 16A as will be described hereinafter in greater detail. Data transferred to driver 51A is stepped to the active matrix panel 16A on the high speed horizontal sync signal which is synchronized with the video clock signal (CLKB) . Considering now the data format driver 51A in greater detail with reference to FIGS. 15A, 15B and 15C, BSTITUTESHEET the data format driver 51A generally comprises a pair of 10 bit shift by three registers 53A and 54A for storing the subpixel data from units 20AA, 22A and 24A and a pair of 8 bit selector registers for transferring the data assembled in registers 53A and 54A to the active matrix panel 16A. As best seen in FIG. 15A, register 53A stores the even-bit data (R e , G e , B e ) while register 54A stores the odd-bit data (R Q , G 0 , B 0 ) from units 20AA, 22A and 24A. Subpixel data is loaded into the shift registers 53A and 54A every CLKA time from the enhancing units 20AA, 22A and 24A and is shifted three bit every CLKA time. Data from the shift registers 53A and 54A is loaded in parallel into registers 55A and 56A respectively every CLKB time. In this regard, CLKA and CLKB are synchronized so that only after the shift registers are fully loaded with subpixel data does the transfer to the selector registers 55A and 56A. As best seen in FIG. 15B, the data format driver 51A also includes a control logic circuit 57A for controlling the latching or transferring of video data from the 10 bit shift by three registers 53A and 54A into the 8-bit selector registers 55A and 56A respectively. In this regard, the control logic circuit 57A is a conventional two bit counter and decoder arrangement for generating three control signals SELA, SELB and SELC respectively. The two bit counter changes states on every CLKB signal. In this regard, only one of the three control signals SELA, SLKB, or SELC will be a logic high or "1" during any given period of time. As previously noted, the control signals SELA, SELB and SELC enable selected groups of the video data bits stored in the 10 bit shift by three registers to be latched into the 8-bit selector register. E HEET FIG. 15C illustrates the arrangement of FIGS. 15A and 15B to show the data format driver 51A. Table I shows the relationship between the control signals and which bits are latched into the selector register: TABLE I BITS 1-8 REG. 53A TO BITS 1-8 REG. 55A BITS 3-10 REG. 53A TO BITS 1-8 REG. 55A BITS 2-9 REG. 53A TO BITS 1-8 REG. 55A BITS 1-8 REG. 54A TO BITS 1-8 REG. 56A BITS 3-10 REG. 54A TO BITS 108 REG. 56A BITS 2-9 REG. 54A TO BITS 1-8 REG. 56A As best seen in FIG. 15A video data from the scaling generators, such as scaling generator 42A, are transferred into the 10-bit shift by three registers 53A and 54A. Bits 1-3 of the shift registers 53A and 54A are loaded on every CLKA signal and shifted 3 bits to the left on every subsequent memory access clock signal (CLKA) until transferred and latched into the 8-bit selector registers 55A and 56A respectively. Considering now the video clock generator 28A in greater detail with reference to FIG. 16A, the video clock generator 28A includes a crystal oscillator 60A for generating a reference clock signal (RCLK) . The reference clock or RCLK signal is coupled to a pair of conventional clock generators 62A and 64A for generating the high speed memory access clock signal (CLKA) and the slower video clock signal (CLKB) . As the clock generators 62A and 64A are conventional they will not be described hereinafter in greater detail. As best seen in FIG. 16A, the video data clock CLKB produces a clock signal on every third RCLK signal for permitting the video data retrieved from the memory arrays, such as memory array 30A, to be packed into two eight bit bytes for transfer to the active matrix panel 16A. The manner in how the retrieved memory array data is packed into the eight bit bytes will be described hereinafter in greater detail. With reference to the memory access clock signal (CLKA) , it should be noted that it corresponds to the reference clock signal (RCLK) except that every ninth clock of the RCLK signal, the CLKA clock signal is inhibited. Inhibiting the clock signal as described above, permits the memory access clock signal (CLKA) and the video data clock signal (CLKB) to remain in synchronization as best seen in FIG. 16A. Considering now the memory controller 40A in greater detail with reference to FIGS, lie, 12 and 13, the memory controller 40A is configured from a field programmable gate array (FPGA) configured to provide the necessary control an iddressing signal based upon the data provided in the Texas Instrument "MOS Memory Data Book" previously referenced. In this regard, as one skilled in the art could easily program the FPGA to provide the necessary control and addressing signals, the memory controller 40A will not be described in greater detail. Referring now to FIGS. 17-21, there is illustrated another high speed display system 109A which is also constructed in accordance with the present invention, and which is adapted for use as a direct view video display system capable of displaying millions of different color shadings. Thus, system 109A is a high speed video color display system. As shown in FIG. 21, the system 109A is adapted for use in an arrangement employing a lap top computer 112A having a video drive module 114A, a direct view monitor, such as a thin film transistor active matrix liquid crystal display panel 116A, and a keyboard 117A. The system 109A is similar to system 10A except that it employs a direct view active matrix panel 116A in a TITUTESHEET lap top computer arrangement with a high speed color enhancing controller 110A which is capable of enabling the panel 116A to display approximately (2 16 + 16 + 16 = 2 48 ) different shadings of colors. The interface controller 110A is used to accelerate the slower conventional video drive signals produced by the video drive module 114A of a conventional personal computer, such as the computer 112A, into high speed video drive signals for use by the high speed display device 116A and to quantizes the analog signal into a set of digital signals for helping to facilitate the production of millions of different color shadings and hues. More particularly, the interface controller 110A permits the active matrix panel 116A to display up to 2 48 simultaneous different colors. In this regard, the video drive module 114A sends conventional RGB video signals including horizontal and vertical sync signals to the interface controller 110A while the controller 110A provides the necessary control functions to interface the high speed display device 116A with the computer 112A. As best seen in FIG. 21, a cable 121A and means not shown interconnect the interface controller 110A between the video drive module 114A and the high speed display device 116A, respectively. The unit 110A receives information from the computer processing unit 115A via module 114A for storage and display on the high speed display device 116A via cable 121A. The keyboard 117A is interconnected to the processing unit 115A by a cable 123A. Referring now to FIG. 17, there is shown a high speed color enhancing interface controller 110A which is also constructed in accordance with the present invention. The controller 110A is adapted to be used with a conventional personal computer having a video SUBSTITUTESHEET drive module 114A for generating a video output signal indicative of a color image for visual display purposes. The controller 110A is substantially identical to controller 11A but includes a set of color enhancing units 120A, 122A and 124A adapted to quantize 16-bits of video RGB data for each primary color into 4-bits of color hue data. The controller 110A includes a pixel clock generator 126A, a memory controller 140A, a video controller 118A and an associated video clock generator 128A for interfacing the video drive module 114A to an active matrix panel 116A which is substantially similar to panel 16A. As the video controller 118A, memory controller 14OA, pixel clock generator 126A and video clock generator 128A are substantially similar to controllers 18A and 40A and clock generators 26AA and 28A they will not be described hereinafter in greater detail. Considering now the high speed color display controller 110A in greater detail with reference to FIGS. 17 and 18, the three enhancing units 120A, 122A and 124A are electrically coupled between the video drive module 114A and the video controller 118A in order to eliminate or at least substantially reduce contouring or splotchiness caused by quantizing the analog RGB signal produced by the computer 114A. As the enhancing units 120A, 122A and 124A are substantially identical, only unit 12OA will be described hereinafter in greater detail. Considering now the enhancing unit 12OA in greater detail with reference to FIG. 18, the unit 120A generally comprises a scaling arrangement 132A for quantizing the analog video data indicative of the red color components of the RGB video signal into 4-bits of data to substantially reduce or eliminate contouring or splotchiness. In order to store the quantized data for accelerating purposes, the unit 12OA also includes a bit HEET map memory array 13OA having two bit map memory units (not shown) . Bit map memory array 13OA is substantially identical to bit map memory array 30A except that it stores 8 bits of data as opposed to 6 bits of data. In order to reduce the red hue component data a single bit binary signal the enhancing unit 12OA also includes a scaling generator 142A. In this regard, the bit map memory array 13OA is electrically coupled between the scaling arrangement 132A and a scaling generator 142A. In operation, the scaling arrangement 132A converts the analog video data indicative of the red color components of the RGB video signal into sixteen bits of discrete digital data which is quantized into 4-bits of data. The 4-bits of quantized data are sequentially stored in the bit map memory array 13OA where the quantized data is subsequently retrieved for display purposes by the video controller 118A. As the operation of video controller 118A is substantially identical to controller 18A it will not be described hereinafter in greater detail. Considering now the scaling arrangement 132A in greater detail with reference to FIGS. 18 and 19, the scaling arrangement 132A includes an analog to digital converter 133A for converting the analog video data signal into 16-bits of digital data, and a buffer and scaling generator 135A for quantizing the 16-bits of digital data into 4-bits of digital video data in order to eliminate or at least substantially reduce contouring or splotchiness otherwise caused by quantizing errors associated with approximations of digital pictures. The analog to digital converter 133A is conventional circuitry. Considering now the buffer and scaling generator 135A in greater detail with reference to FIG. 17, the ITUTESHEET buffer and scaling generator 135A includes four quantizing units 146A, 147A, 148A and 149A respectively. As each quantizing unit is substantially identical, only quantizing unit 146A will be described hereinafter in greater detail. In order to synchronize the scaling generator 135A signals with the bit map memory array 13OA, the pixel clock generator 126A is utilized to step the analog video data indicative of the red color components through each successive stage of the respective color enhancing units 12OA, 122A and 124A respectively. In this regard, each enhancing unit consists of 4 successive stages: a first stage for converting the analog video data to digital data; a second stage for quantizing the 16-bits of digital data into 4-bits of video data; a third stage for storage of the quantized video data to allow its subsequent repetitive retrieval at a much greater retrieval rate; and a fourth stage for scaling the 4-bits of video data into a single digital signal indicative of the red hue color components for the image to be displayed. Considering now the quantizing scaling unit 146A in greater detail with reference to FIG. 17, the quantizing unit 146A generally includes a buffer or latch 151A that temporarily stores the four most significant bits of digital data (R15-R12) coupled from the analog to digital convertor 133A. The output of latch 151A is electrically connected to a duty cycle signal generator 153A that converts the 4-bit output signal of latch 151A into a single bit binary signal that produces the desired quantization without introducing any substantial quantizing errors as will be explained hereinafter in greater detail. As best seen in FIG. 17, the duty cycle signal generator 153A generally comprises a comparator circuit 156A and a signal generator circuit 158A whose output signal changes in a predetermined randomly sequenced manner on every pixel clock signal. In this regard, the output signals of the signal generator 158A are arranged to translate the 4-bit output signal of buffer 151A in a predetermined randomized sequence that minimizes quantizing error associated with approximations of digital pictures. In order to convert the 4-bit output signal of the buffer 151A into a single bit binary signal, the comparator circuit 156A is coupled between the 4-bit output signal generator 158A and the 4-bit output signal of the latch 151A. Comparator circuit 156A determines whether the numerical value of the 4-bit digital output of the buffer 151A exceeds the numerical value of the 4- bit digital output signal of the signal generator circuit 158A, and generates a single bit digital output signal whenever the numerical value of the output of latch 151A exceeds the numerical value of the output of generator 158A. The binary output signal of the comparator 156A is synchronized with the output of each of the other quantizing arrangements 147A, 148A and 149A so all 4 output data signal can be stored simultaneously in the bit map memory array 13OA. The signal generator 153A is substantially similar to the scaling arrangement 74A described herein as well as the signal generator circuit described in U.S. patent application Serial No. 07/472,668 and will not be described hereinafter in greater detail. Although the preferred embodiment of the present invention the quantizing unit 146A translates a 4-bit digital signal into a single bit binary signal, it will be understood by those skilled in the art that the converted digital signal may contain fewer than or more than 4-bits to represent a different quantizing arrangement. Considering now the scaling generator 142A in greater detail with reference to FIGS. 18 and 19, the scaling generator 142A generally comprises a pair of scaling units 162A and 164A for eliminating or substantially reducing patterning associated with repetitive "beats" in the displayed image. The scaling units 161A and 162A include a pair of buffers 163A and 164A and a pair of scaling arrangements 165A and 167A. The scaling generator 142A is substantially identical to the buffer and scaling generator 135A except that it operates at a substantially high rate because it is stepped by a memory video clock signal (CLKA) as opposed to the pixel clock signal (PXCLK) . As the generator 142A is otherwise substantially identical to the buffer and scaling generator 135A it will not be described hereinafter in greater detail. Although in the preferred embodiment of the present invention the high speed display device has been described as a thin film transistor active matrix panel, it will be understood by those skilled in the art that other types of high speed color display devices such as a high speed color television monitor* unit could also be driven by the color enhancing interface controller. Referring to the drawings, and more particularly to FIG. 21A, there is illustrated a television signal projection system 10B, which is constructed in accordance with the present invention, and which is adapted for use as a video display system capable of displaying a very large full color screen image. Thus, the system 10B is a display projection system, and is employed in an overhead projection arrangement. As shown in FIG. 21A, the system 10B is adapted for use in an arrangement employing a television signal generating source, such as a video cassette recorder 2OB with a conventional video cassette (not shown) , and an overhead projection system 8OB. The video cassette recorder 2OB supplies a conventional National Television Standards Committee (NTSC) signal (USA) or a PAL signal (Europe) as generated for displaying an image from a broadcast television signal source. The system 10B generally comprises a display drive unit 11B for translating the conventional television video output signal from the video cassette recorder 2OB into video signals capable of thousands of different color shadings and hues for display by a display device, such as a thin film transistor active matrix liquid crystal display panel 16B for displaying color images produces from the video signals. The drive unit 11B is also capable of translating the conventional computer video output signals produced by a personal computer 2IB having a video drive module 26B as more fully disclosed in copending U.S. patent Serial No. 07/586,506 mentioned herein. In this regard, the drive unit 11B includes a color enhancing interface controller 12B coupled by an interface unit 13BB to either the video cassette recorder 20B or the video drive module 26B. The interface controller 12B includes a format timing generator 45B for formatting the television signal for displaying images on the display device 16B. The interface unit 13BB is connected to the recorder 20B and the module 26B by a pair of cables 13AB and 13BBB respectively. Referring now to FIG. 32, there is shown the active matrix panel 16B illustrating a group of composite pixels 300B-305B arranged in rows or lines, such as lines 240B, 242B, 244B and 246B, and columns or pixels 241B, 243B, 245B and 247B. As each composite pixel 300B-305B is substantially the same only composite pixel 300B will be described hereinafter in greater detail. S B TIT TESHEET Considering now the composite pixel 300B in greater detail with reference to FIG. 32, the composite pixel 300B consists of a 2x2 pixel element matrix divided into a group of pixel elements 22OB, 225B, 23OB and 23IB identified as 0, 1, 2 and 3 in dotted lines. The four pixel element matrix consists of two lines or rows 240B and 242B, respectively and two columns of pixel groupings 24IB and 243B, respectively. The rows and columns of pixel elements define a pixel group, such as the group 300B for example. As will be explained hereinafter in greater detail, a color enhancing interface controller 12B, causes selected ones of the active matrix pixel elements in each of the composite pixel groups, such as group 300B, to be assigned intensity levels for forming the composite pixel grouping. In this regard, as best seen in FIG. 32, the input data for the pixel element 22OB is the same for pixel element 23OB and thus, is used to define an intensity level to the pixel element at line ?"0B, column 241B as well as the pixel element at line i OB, column 243B. In a similar manner, the input data for pixel element 225B at line 242B column 22OB is used to define the intensity level for the pixel element 23IB at line 242B, column 243B. Each pixel element, such as pixel element 220B includes three sub-pixel elements (not shown) one for each primary color red, green, and blue. In such an arrangement therefore, it should be understood that in each one of the groups, such as the group 300B, the individual pixel elements, such as pixel elements 220B, 225B, 230B and 231B will be selectively energized to form up to eight shades of color for each of the primary colors red, green and blue. Thus, by combining selectively certain ones of the pixel elements, such as the pixel elements in composite group 300B, in excess of 24,000 different color combinations may be produced in the composite pixel 300B. Although in the preferred embodiment of the present invention, the drive unit 11B is shown interfaced to the video cassette recorder 2OB it will be understood by those skilled in the art that other similar television signal generating sources, such as a video disc unit 22B, a video camera 24B a television tuner 41B or a television receiver 43B having an antenna 43AB could also be employed as shown in FIG. 23. The interface unit 13BB converts the NTSC signal into an analog signal indicative of the red, green, blue color components of the display image along with the horizontal and vertical synchronizing or scanning signals HSYNC and VSYNC for generating a standard television scan raster in which the image is displayed. The color enhancing interface controller 12B not only provides the necessary control functions to couple the interface unit 13BB to the display device 16B but also quantizes the conventional RGB analog signal so that a very large number of colors can be displayed by the active matrix panel 16B. As best seen in FIG. 21A, the color enhancing interface controller 12B is coupled to the active matrix panel by a cable 25B. The video cassette recorder 2OB may be any conventional video cassette recorder, such as manufactured by SONY Corporation or RCA, Inc. which is capable of generating a standard NTSC signal when playing a video cassette with prerecorded video television image information. The video cassette recorder 2OB can be connected to a CATV cable 41AB or a standard television antenna for coupling line broadcast signals to the drive unit 11B. The display device 16B in cooperation with the video cassette recorder 2OB and the overhead projector system 8OB enables a user to view any prerecorded video television image information in a large projected image format. Considering now the overhead projection device 80B in greater detail with reference to FIGS. 21A and 22, the projection device 8OB generally includes a flat transparent projection surface 82B which is adapted to support the active matrix panel 16B for image projection purposes. The overhead projection device 80B includes an illumination bulb and a reflector shown generally at 83B (FIG. 22) for transmitting light through the panel 16B. In order to collimate the light produced by the bulb and reflector 83B into the panel, a collimating Fresnel lens 85B is disposed on the underside of the active matrix panel 16B. A focusing lens 87B, preferably a Fresnel lens is disposed on the upper side of the panel 16B for converging the light exiting the panel 16B into an overhead projection optics assembly 88B. In this regard the optics assembly 88B enables light passing through the panel 16B to be focused onto a projection screen or other suitable viewing surface (not shown) , for audience display purposes. While in the preferred form of the present invention the Fresnel lens 85B and 87B are disposed on the panel 16B, it will be understood by those skilled in the art that the lens may be disposed in a case (not shown) for supporting the lens 85B and 87B in a spaced-apart manner from the panel 16B. In this regard, the television signal projection system 10B and the method oi using it, enables a full color display image to be projected on to any suitable viewing surface in a relatively easy and convenient manner using relatively inexpensive commercially available equipment which may be easily set up for viewing purposes. The active matrix thin film transistor liquid crystal panel 16B includes a pixel matrix array for generating a selected number of image elements in a 640 by 480 pixel array having a primary color arrangement SUB (red, green, blue) for forming the prerecorded television video image stored on the video cassette cartridge (not shown) . It will be understood by those skilled in the art that the television video image may be generated from a television signal which is broadcast and received by a television receiver or generated by a television camera directly coupled to the interface unit 13BB as shown in FIG. 23. The active matrix panel 16B is more fully described in copending U.S. patent application Serial No. 07/586,506 referenced herein. Table I As best seen in FIGS. 21A and 23, the system 10B is adapted for use with any conventional television signal source for producing a video image, such as the NTSC and VGA GRAPHIC signals. Table I specifies the HSYNC rate for two of the conventional video signal sources. As will be explained hereinafter in greater detail, although the system 10B converts such signals, into re-formatted signals that are capable of driving the active matrix panel 16B having a 640 by 480 pixel array only a 320 x 480 pixel image is displayed when displaying the NTSC video signals. FIG. 28 illustrates a typical display method of the present system 10B. In this regard, for illustrative purposes a typical NTSC display format of 525 lines is shown with a 640 by 480 pixel array, shown generally at 801B. The NTSC signal occupies a display area shown generally at 802B and consists of two interlaced 60Hz fields of 262.5 line each, combining to give a 30Hz, 525 lines of video information. Because the vertical SUB TIT resolution of the panel 16B is less than the vertical resolution provided by the NTSC signal, the present system 10B effectively fits the NTSC display configuration into the 480 lines of vertical resolution for the panel 16B. The controller 12B formats the NTSC signal by ignoring the first twenty two horizontal lines and the last twenty three horizontal lines in each frame of video information, resulting in 480 valid lines (525 lines - 22 lines - 23 lines = 480 lines) . This is an effective practice since the disregarded lines consist of the "overscan" (invisible) lines of the extreme top and bottom p' tions of the displayed image, which typically contains little or no meaningful video information. The width of the NTSC picture is also matched or formatted into a 640 pixel width for use by the panel 16B. In this regard, the controller 12B adjusts the sampling rate of the video signal as will be explained hereinafter in greater detail. Considering now the interface unit 13BB in greater detail with reference to FIG. 23, the interface unit 13BB generally includes a signal converter 32BB for converting the NTSC television signal from the video cassette recorder 20B into an analog RGB signal suitable for driving the controller 12B. The NTSC television signal is coupled to the input of the signal converter 32BB by a conductor 20AB. As best seen in FIG. 23, the interface unit 13BB has its input also coupled to the video drive module 26B whose output signals are already in an analog RGB format suitable for driving the controller 12B. In this regard, the video drive module 26B in the personal computer 2IB has five output signals red, green, blue, horizontal synchronization (HSYNC) , and vertical synchronization (VSYNC) coupled to the interface unit 13BB on the cable 13BBB having a set of conductors 26AB- EB respectively. SUBSTITUTESHEET In order to enable a user to select between input signals from the video cassette recorder 2OB and the video drive module 26B, the interface unit 13BB also includes an analog multiplex unit 34BB and a microprocessor 36BB. The analog multiplex unit 34BB is a conventional multiplexer allowing either the output signals from the signal converter 32BB or the output signals from the video drive module 26B to be coupled to the color enhancing interface controller 12B. The microprocessor 36BB determines which of the video source standards (VGA Graphics, NTSC, PAL, etc.) are to be coupled to the color enhancing interface controller 12B. In this regard, the microprocessor 36BB allows only one of the source standard signal to be coupled to the controller 12B. Signals are coupled from the analog multiplex unit 34BB to the controller 12B on a set of conductors 34AB-EB respectively. Once the microprocessor 36BB determines the type of video standard to be supplied to the controller 12B, the microprocessor 36BB generates appropriate format data and commands on a command/data line 36AB (FIG. 25) for establishing a proper sample rate and format of lines and pixels locations for driving the active matrix unit 16B. The microprocessor 36BB also generates a control signal (MUX CONTROL) which switches the multiplex unit 34BB to receive and pass to the controller 12B, either the input signals from the signal converter 32BB or the input signals from the video drive module 26B. The control signal, MUX CONTROL is coupled to the multiplex unit 34BB on a conductor 36BBB. The interface unit 13BB also includes an infrared receiver 38B having a receptor 39B for receiving infrared signals from a remote infrared transmitter unit (not shown) . In this regard, a user may actuate the infrared transmitter unit for generating a signal which causes the microprocessor 36BB to search for a different type of SUB T video source signal by switching the multiplex unit 34BB. The infrared receiver 38B is a conventional infrared receiver unit whose output is coupled to the microprocessor 36BB on a conductor 38AB. For the purpose of amplifying the low level audio signal that accompanies the video source signals, the interface unit 13BB also includes an audio amplifier 33B having an output jack adapted to be connected to a conventional speaker, such as speaker 33AB. The audio amplifier 33B is conventional, such as a model TDA1013B sold and manufactured by Signetics and described in the Signetic "Linear Data Manual," Volume 1 (1989) pages 7- 207. Considering now the signal converter 32BB in greater detail with reference to FIG. 23, the converter 32BB is of a type well known to those skilled in the art, such as a TDA 3330 unit manufactured by Motorola and described in the Motorola Linear/Interface Devices Data Book, page 9- 183 through 9-190, and in Motorola Application note AN1019D. Other type of converters for converting a PAL signal or a SECAM signal to an RGB signal are also well known. For example a combination PAL-SECAM-NTSC to RGB converter is available from SGS THOMSON at 1000 East Bell Road, Phoenix, Arizona under part number TEA 5640C as described in the SGS THOMSON Video IC's Data Book, pages 1211-1227. As the signal converter 32BB is well known, it will not be described herein in greater detail. The output signals of the signal converter 32BB are coupled to the analog multiplex unit 34BB on a set of conductors 32AB-EB carrying the respective signals of red, green, blue, horizontal synchronization (HSYNC) and vertical synchronization (VSYNC) . Considering now the color enhancing interface controller 12B in greater detail with reference to FIGS. 23 and 24, the controller 12B is coupled between the S active matrix panel 16B via cable 25B and the output of the analog multiplex unit 34BB. In this regard, the output signals from the analog multiplex unit 34BB, red, green, blue, horizontal synchronization and (HSYNC) vertical synchronization (VSYNC) are coupled to the input of controller 12B on a set of conductors 34AB-EB respectively. The color enhancing interface controller 12B as best seen in FIG. 24, generally comprises a video controller 18B for controlling the video data supplied to the active matrix panel 16B, a set of color enhancing units 4OB, 42B, 44B for quantizing the video data supplied from the interface unit 13BB, a memory controller 5OB for controlling the storing and retrieval of the quantized video data, and a format timing generator 45B for helping to format the video data to be displayed. As the memory controller 50B is substantially similar to the controller described in copending U.S. patent application Serial No. , only the color enhancing units 4OB, 42B, 44B and formatting timing generator 45B will be considered in greater detail. Considering now the format timing generator 45B in greater detail with reference to FIGS. 24 and 25, the format timing generator 45B generally comprises a programmable counter arrangement 46B for helping to format the video data to be stored in the controller 12B, a programmable pixel clock generator 47B for establishing a proper sampling rate based upon the type of video signal being coupled to the controller 12B, and a divide by two counter 102B for helping to establish a proper storing sequence of video data. As best seen in FIG. 25, the programmable pixel clock generator 47B is a conventional phase lock loop arrangement including a phase comparator 66B, a low pass filter 67B, a voltage control oscillator 68B, and a programmable divider or divide by N counter 69B. The programmable pixel clock generator 47B utilizes a reference clock signal coupled from the output of the analog multiplex unit 34BB. The reference signal is identified by the HSYNC signal and is coupled on a conductor 34DB to the input of the phase comparator 66B. An output pixel clock signal PXCLK for synchronizing the storing of the video data in the respective enhancing units 40B, 42B and 44B is derived from the output of the voltage controlled oscillator 68B. The sampling rate of the voltage controlled oscillator 68B is a function of the output of the programmable divider 69B as will be described hereinafter in greater detail. Considering now the programmable divider 69B in greater detail with reference to FIG. 25, the programmable divider 69B is programmed by the microprocessor 36BB to help establish a proper sampling rate for storing the video data. The following example will be instructive. Assuming the video standard coupled to the controller 12B is a NTSC standard requiring a sampling rate of 14.333 MHz or 910 samples for every line of display data. In this regard, a division of 910 is required to produce the desired sampling rate as shown by the following formula: HSYNC rate (NTSC standard) « 15.750 KHz Sampling rate = 15.750 KHz x 910 = 14.333 MHz. As will be explained hereinafter, 910 pixels are sampled per line, however 270 pixels of the 910 pixel samples represent excess data and is disregard. In this regard, if the video standard is VGA graphics, for example, a division of 800 is required to produce a sample rate of 25.175 MHz. In this regard, the HSYNC signal is 31.47 KHz multiplied by 800 to produce the desired sampling rate of 25.175 MHz. Again, a given number of the 800 samples represent excess data, i.e. 160 samples. These 160 samples are disregarded, the first 80 samples and the last 80 samples in every line. Referring now to FIG. 29A, a horizontal synchronization signal (HSYNC DATA) is shown generally at 90IB. The pixel location disregard for storage purposes as described above are shown as a non-valid data group 902B immediately before the HSYNC DATA signal 901B goes to a logical high level and a non-valid data group 903B immediately after the HSYNC DATA signal 901B goes to a logical high level. The pixel locations between groups 902B and 903B represents a valid data group 904B for displaying on the panel 16B. For the purpose of further explanation, the HORIZONTAL RETRACE period occurs when the HSYNC DATA signal 901B is a logical high. Considering now the programmable counter arrangement 46B in greater detail with reference to FIG. 25, the programmable counter arrangement 46B generally comprises a retrace counter 73B for helping to establish the number of vertical retrace lines in a frame of displayed information, a pixel counter 75BB for helping to establish the number of valid pixels in a single line of displayed information and for helping to establish the number of horizontal retrace pixels between lines of displayed information, a line counter 77BB for helping to establish the number of valid lines in a frame of displayed information and a format processor or controller 79BB for helping to coordinate the operation of the above mentioned counters in cooperation with the microprocessor 36BB. The format controller 79BB under the control of the microprocessor 36BB generates load signals LOAD R, LOAD P, and LOAD L which enables the loading of predetermined counts into the retrace counter 73B, the pixel counter 75BB and the line counter 77BB for storing video data in each of the color enhancing units 40B, 42B and 44B in a SUBSTITUTESHEET proper format for access and display on the display unit 16B. The load signals, LOAD R, LOAD P and LOAD L are connected between the format controller 79BB and the retrace counter, pixel counter 75BB and line counter 77BB on a set of conductors 79DB, 79CB and 7yBBB respectively. A connector 36AB connected between the microprocessor 36BB, the format controller 79BB, the programmable divider 69B, and each of the above referenced counters 73B, 75BB and 75BB allows command instructions and the predetermined formatting data to be transferred from the microprocessor 36BB for establishing proper formatting. In order to enable the format processor 79BB to generate the necessary control signal for enabling the memory controller 50B to store the video information and control memory operations, each of the counters 73B, 75BB and 75BB provide terminal count signals TCR, TCP, and TCL to the format processor 79BB. The terminal count signals are conducted to the processor 79BB on conductors 73AB, 75BBB and 77BBB respectively. The format processor 79BB enables the memory controller 50B to store all even field lines of even memory addresses in the bit map memories and odd field lines at odd memory addresses. Storing video information in this manner, enables the video information to be retrieved from the bit map memories in each respective enhancing unit 4OB, 42B and 44B in a combined interlaced line format to generate the 480 vertical line resolution utilized by the display device 16B. In operation, the microprocessor 36BB determines what video source is to be displayed and sends the proper divide by command to the programmable divider 69B via a command/data line signal on a conductor 36AB. The operation of the microprocessor 36BB will now be described in greater detail with reference to the flow SUBSTITUTESHEET diagram of FIG. 26 which illustrates the steps executed by the microprocessor 36BB. Referring now to the flow chart of FIG. 26, when power is applied to the drive unit 11B, a CONFIGURE PROGRAM 60OB begins in a START instruction 60IB and proceeds to an instruction box 603B to set the default settings for the preferred types of video signal source, i.e. NTSC, PAL, VGA GRAPHICS, etc. After the default settings have been established, the program proceeds to a decision instruction 605B in which a determination is made whether the microprocessor is currently receiving an HSYNC signal from the analog multiplex unit 34BB. If there is no signal being received, the program proceeds to instruction box 607B to cause the analog multiplex control signal MUX CONTROL to be switched allowing the HSYNC and VSYNC signal from another video signal source to be coupled to the microprocessor 36BB. After the MUX CONTROL signal has been enabled the program returns to decision 605B to once again determine whether an HSYNC is being received from the next selected or enabled source. The above described procedure repeats itself until an enabled video signal source begins sending video synchronization information (HSYNC, VSYNC) . If it is determined at decision instruction 605B that an HSYNC signal is present, the program branches to instruction 612B to cause the microprocessor 36BB to analyze the period and polarity of the HSYNC and VSYNC signals respectively. After execution of instruction 612B, the program proceeds to instruction 614B where the exact video signal standard is determined by the microprocessor 36BB using a conventional comparing technique. Once the video signal standard is determined, the program steps to instruction 616B which configures the programmable divider 69B and programmable counter arrangement 46B by causing the proper sample rate and format count data to be set for formatting purposes. In this regard, the format processor 79BB causes the LOAD R signal, LOAD P signal and LOAD L signal each to be enabled, as will be explained hereinafter in greater detail, so that the format data supplied by microprocessor 36BB on line 36AB can be loaded into each of the counters 73B, 75BB and 77BB. Once the programmable divider 69B and programmable counter arrangement 46B has been configured, the program proceeds to decision instruction 618B which determines whether a user has changed the video standard. If the video standard has not been changed, the program waits at instruction 618B until the video source is changed. When the video source is changed, the program proceeds to decision instruction 62OB to determine whether the HSYNC signal is being received from the video source. If the HSYNC signal is present, the program goes to instruction 612B and proceeds as previously described. If a HSYNC signal is not present, the program will advance from instruction 620B to decision instruction 605B and proceed as previously described. Considering now the operation of the format controller 79BB in greater detail with reference to FIG. 27A and 27B, in order for the format controller to properly control the formatting of video data for storage in the various bit map memories in the enhancing units 40B, 42B and 44B, the microprocessor 36BB must first determine (1) the number of vertical retrace lines required for the displayed information; 2) the number of valid or displayable lines in any given frame of displayable information; 3) the number of horizontal retrace pixels between each displayable line of information; and 4) the total number of valid or displayable pixels in each line of displayable information. The microprocessor 36BB is preprogrammed to SUBSTITUTESHEET determine the type of video source signal as a function of the HSYNC and VSYNC signal produced by the video source and then to generate the proper counter arrangement 46B data for storing in each of the respective counters 73B, 75BB and 77BB to achieve proper formatting. Table II illustrates the base count information required for converting a VGA and a NTSC video source signal. Table II Once the microprocessor 36BB has determined the type of video source signal, the microprocessor 36BB sends formatting commands and format data for utilization by the counter arrangement 46B. Referring now to FIG. 27B, the format processor 79BB upon receiving a configuration or format command starts a FORMAT program 700B. The FORMAT program 700B begins in a START instruction 701B and processed to a decision instruction 703B to determine whether a VSYNC signal from the video source is present. If the VSYNC signal is not present, the program waits at decision instruction 703B. When the VSYNC signal occurs, the program proceeds to an instruction box 704B to start a vertical retrace period or a new frame by resulting the time counter 77BB. The program then goes to decision box 705B to determine TITUTESHEET whether a HSYNC signal is present. If the HSYNC signal is not present the program waits at box 705B. When an HSYNC signal occurs the program advances to instruction box 707B to cause the line counter 77BB to be incremented. After the line counter 77BB has been increment, the program proceeds to a decision instruction 708B to determine whether a valid number of retrace line has occurred. If a valid number of retrace lines has not occurred, the program returns to decision box 705B and proceeds as previously described. In this regard, it should be understood that the first twenty two horizontal lines of data will be disregarded as best seen in FIGS. 28 and 29B. If a valid number of retrace lines has occurred, the program advances to instruction 709B to reset the line counter 77BB. Once the line counter 77BB has been reset, the program proceeds to instruction 710B to start a horizontal retrace period for generating the first valid line of the 480 lines to be stored. The program then advances to decision instruction 711B to wait for the next HSYNC signal. If the HSYNC signal is not present, the program waits at decision instruction 711B. When the HSYNC signal occurs, the program advances to instruction 713B to increment the pixels counter 75BB. The program then proceeds, to decision instruction 715B (FIG. 27B) to determine whether a valid number of retrace pixels has occurred. If a valid number of retrace pixels has not occurred, the program returns to instruction 713B (FIG. 27A) and continues as previously described. If a valid number of retrace pixels has occurred, the program advances to instruction 716B to start storing valid video data into the bit map memories of the enhancing units 40B, 42B and 44B. In this regard, at instruction box 716B the pixel counter 75BB is reset and the row and column count is set for utilization by the memory controller SOB. After the row and column count has been SUBSTITUTE SHEET set, and the pixel counter 75BB reset, the program advances to instruction box 717B transfer the row and column count to the memory controller, enables the latching of the even and odd pixels and generates the memory control signals to enable the storing of data into the bit map memories. The control signals (such as the odd enable and even enable signals) for storing data int the individual bit map memories of enhancing units 4OB, 42B, and 44B are more fully described in copending U.S. patent application Serial No. 07/586,506. As will be explained hereinafter in greater detail, the memory control signals include an interrupt signal when generated by the video controller 18B whenever the video controller 18B requires access to the bit map memories in the enhancing units 4OB, 42B and 44B. In this regard, the Request New Data signal generated by the video controller 18B cause the storing of data via the format timing generator 45B to be temporarily disabled while a line of displayable video data is read from the enhancing units 40B, 42B and 44B for display purposes. The interrupt signal from the format timing generator 45B via the memory controller 50B and the memory control store data lines. After the transfer of the data into memory, the program then proceeds to instruction 72IB to increment the pixel counter 75BB. After the pixel counter 75BB has been incremented the program advances to a decision instruction 723B to determine whether a valid number of pixels has been generated by the pixel counter 75BB. If a valid number has not occurred, the program returns to instruction 717B and repeats the above described sequence. When a valid number of pixels occurs, the program goes from decision instruction 723B to instruction box 725B to increment the line counter 77BB. After the line counter 77BB has been incremented, the SUBSTITUTESHEET program advances to decision instruction 727B to determine whether a valid number of lines has occurred. If the frame is not completed, the program returns to decision instruction 711B (FIG. 27A) to start another line of information as previously described. If the frame is completed, the program goes to instruction 730B and reset the line counter 77BB. After counter 77BB has been reset, the program returns to instruction 703B to wait for the next VSYNC signal. From the foregoing, it should be understood that the format controller 79BB in cooperation with the microprocessor 36BB enables a conventional video signal such as a NTSC signal having 525 lines of horizontal video information to be formatted for display into 480 lines of horizontal video information as used by the display device 16B. More particularly, the microprocessor 36BB and controller 79BB cause the 525 lines of horizontal information for each displayable frame of video information to be centered for display in the 640 x 480 pixel array of panel 16B. In this regard, the first twenty two lines of horizontal data are blanked and the last twenty three lines of horizontal data are blanked so that only 480 lines of the horizontal information for each displayable frame of video information is displayed. This is i 'fective in practice since the majority of the disregarded horizontal lines consists of "overscan" or "invisible" lines and the extreme top and bottom of the displayable frame usually contains little or no displayable video information. For example, referring to FIG. 29B, a timing diagram is illustrated for horizontal line formatting. In this regard, a group of non-valid lines is shown generally at 910B and a group of valid lines are shown generally at 920B. The group of non- valid lines 910B are disposed immediately before and SUBSTITUTESHEET immediately after the VSYNC signal goes to a logic high. The first 23 lines before the VSYNC signal and the first 22 lines after the VSYNC signal represent non-valid lines. The VSYNC signal is indicative of the vertical retrace lines. In a similar manner the width of the displayable frame of video information is matched to the 640 lines of the vertical information for each frame by adjusting the sampling rate of the video signal. The sampling or PXCLK rate is set, then a horizontal divisor (ratio of PXCLK to HSYNC rate) is set using the programmable divider 69B to match the horizontal frequency of the television signal produced by the video source. As the signals from the video drive module 26B already have a proper format, the above described formatting technique is not required. In this regard, the microprocessor 36BB is coupled to the format timing generator 45B to select the desired format for the video drive module 26B. Considering now the divide by two counter 102B, in greater detail with reference to FIG. 25, the divide by two counter 102B, divides the pixel or dot clock signal PXCLK in half to produce an output signal having one half the frequency of the dot clock signal. The divide by two counter 102B operate in a manner such that those skilled in the art will understand the operation. Specifically, the divide by two counter 102B divides the pixel clock signal PCLK and produces as an output signal a synchronizing clock signal PCLK2 for helping to sequence the storing of input video data by the enhancing units 40B, 42B and 44B. Considering now the memory controller 50B in greater detail with reference to FIG. 31, the memory controller 50B controls the storing and reading of video data from each of the enhancing units 40B, 42B and 44B. In this regard, the memory controller 50B is more fully described in copending U.S. patent application Serial No. 07/586,506 and will not be described hereinafter in greater detail except for the interrupting of the format processor 79BB (FIG. 25) via an INTERRUPT firmware program 1100B whenever the bit memories of the enhancing units 40B, 42B and 44B are accessed by the video controller 18B. Considering now the video controller 18B in greater detail with reference to FIG. 31, the video controller 18B includes a row counter 61B and a column counter 62B which generated the PHSYNC and PVSYNC signals used by the panel 16B as well as the memory address and request data signals used by the memory controller 50B to control the retrieval of the video data from the enhancing unit 4OB, 42B and 44B. In this regard, whenever the row counter 61B reaches its terminal count, it generates the PVSYNC signal, and whenever the column counter 62B reaches its terminal count it generates the PHSYNC signal. The PHSYNC and PVSYNC signals are used by the panel 16B to control the display of video information. As will be explained hereinafter in greater detail, the video controller 18B also includes a pair of dividers 63B and 64B for dividing the frequency of the respective PHSYNC and PVSYNC signals by two in order to help facilitate the comparison of pixel patterns for color shading purposes. The frequency of the above mentioned signals (PHSYNC and PVSYNC) is divided in half for data retrieval purposes by a pair of dividers 63B and 64B respectively. For the purpose of helping to reduce, if not substantially eliminate flicker patterns, the video controller also includes an exclusive or gate 100B (FIG. 31) . The exclusive "or" gate generates a flicker inhibit signal PVSYNC2, for synchronizing the video data output from a pattern logic component 59B (FIG. 25A) , which is SUBSTITUTESHEET described in greater detail hereinafter. As best seen in FIG. 31, the gate 7OB has two inputs, one from the divide by two counter 64B and the other one from the panel video clock oscillator 60B. The video controller 18B also includes a mode select multiplexer 111B and a firmware INTERRUPT program 1100B. More particularly, as video data is loaded into each of the respective enhancing units 40B, 42B and 44B on a line by line basis, it should be understood that cooperation is required between the format timing generator 45B and its formatting of data for storage into the enhancing units 40B, 42B and 44B, and the video controller 18B and its reading of the formatted data from the bit map memory in the enhancing units 40B, 42B and 44B. The above- mentioned cooperation or handshaking is accomplished through the INTERRUPT firmware program 1100B. The video controller 18B also includes a mode select multiplexer 111B for multiplexing data to the panel 16B from other color shading units (not shown) . In this regard, the mode select multiplexer 111B in greater detail with reference to FIG. 25A, the mode select multiplexer 111B permits a user, via the infrared receiver 38B to select the format of video data to be displayed. In this regard, the system may display video data from either a television signal source mode or a computer video output signal source mode. Considering now the INTERRUPT program 1100B in greater detail with reference to FIGS. 24 and 31, whenever the video controller 18B requires video data for display purposes, the video controller 18B generates an interrupt control signal on the request new data line buss between the video controller 18B and the memory controller 50B. The interrupt control signal starts the INTERRUPT firmware program 1100B. In this regard, the INTERRUPT firmware program 1100B starts at box 1101B and SUBSTITUTESHEE advances to instruction box 1103B which halts or interrupts the storing of data into the bit map memories of the enhancing units 4OB, 42B and 44B. The program then advances to instruction box 1105B which enables the memory address lines from the row counter in the video controller 18B to be placed on the address buss for the enhancing units 4OB, 42B and 44B. The address buss for the enhancing units 40B, 42B and 44B is a common address buss shared by the format timing generator memory addressing and the video controller memory addressing. After the memory address lines have been enabled, the memory controller SOB generates the RAS signal at instruction box 1107B transferring the row counter into the VRAMs or bit map memories of the enhancing units 4OB, 42B and 44B. The program then advances to instruction box 1109B which disables the memory address buss from being controlled by video controller 18B. The program then proceeds to instruction box 1111B and outputs all zeros onto the address buss via the memory controller 50B. The program then goes to instruction 1113B where the memory controller enables the CAS signal to cause the column position to be coupled to the bit map memories of the enhancing units 40B, 42B and 44B. The program then proceeds to instruction 1115B and loads the video data into the respective bit map memories in each enhancing unit 40B, 42B and 44B for access by the video controller 18B. In this regard, it should be understood that an entire row of video data is loaded into the respective bit map memories for display purposes. After the video data has been loaded into the bit map memories, the program advances to instruction 1117B to acknowledge that the loading of the memory has been completed which is indicative that a new line of data may now be displayed on the active matrix panel 16B. More particularly, the PHSYNC produced by the column counter 62B is driven to a logical low level and remains low until the column counter 62B in the video controller 18B reaches its terminal count indicating that another new line of video data is required. When another line of data is required, another interrupt signal is generated. It should be understood that when the request new data signal is generated by the video controller 18B, the PHSYNC goes to an active level. After the acknowledgement of loading the bit map memories is completed, the program goes to instruction 1119B which returns control of the memory address buss to the format timing generator 45B. The program then advances to instruction 112IB which enables the row and column count in the format timing generator 45B to be set as previously described. The program then proceeds to box 1123B which causes the FORMAT program 700B to be resumed from where it was interrupted. Considering now the enhancing units 40B, 42B and 44B with reference to FIG. 24, only one enhancing unit, enhancing unit 40B, will be described in greater detail as each of the enhancing units 4OB, 42B and 44B are substantially similar to one another. Considering now the color enhancing unit 4OB in greater detail with reference to FIGS. 24 and 25A, the color enhancing unit 4OB generally comprises an analog to digital converter 51B for converting the red component of the raw RGB analog signal into a digital signal for processing and storage purposes by an encoder arrangement 52B and a bit map memory 57B respectively. The encoder arrangement 52B includes an encoder logic unit 53B coupled between the output of the analog to digital converter 51B, and the input of an output buffer unit 55B for temporarily storing or latching the video data to be stored into the bit map memory 57B. The enhancing unit 4OB also includes a pattern logic unit 59B connected between the bit map memory 57B and the video controller 18B for forming video data to enable individual pixel elements to be activated. The analog to digital converter 51B, the buffer 55B, and the bit map memory 57B are substantially similar to the corresponding units more fully described in copending U.S. patent application. Serial No. and will not be described hereinafter in greater detail. Considering now the encoder logic unit 53B, with reference to FIG. 25A and 25B, the encoder logic unit 53B generally includes an input buffer unit 102AB and an array of tri-state buffers gates 103B-109B for quantizing the inpu signal from the analog to digital converter 51B in a multiplexing technique. In this regard, the encoder arrangement 52B, quantizes each 8-bit digitized video signal into a 4-bit quantized video signal consisting of the signals RO*, Rl*, R2*, and R3*. As best seen in FIG. 25A, the unit 53B also includes an invertor HOB for helping to multiplex the digital information for storage into the bit map memory 57B via the buffer 55B. In this regard, although the analog to digital converter 51B, on every pixel clock (PXCLK) , converts each analog signal into a digital signal, only every other converted signal is latched into the buffer 55B, as will be explained hereinafter in greater detail. In order to transier the digitized data from the analog to digital converter 51B to the encoder arrangement 52B, the output signals (R7-R3) from the analog to digital converter 51B are coupled to the input buffer 102A on every PCLK2 signal. The output signals (R7-R4) from the buffer 102AB, in turn, are coupled to the inputs of gates 103B, 105B, 107B and 109B respectively, while the output signal R3 from the buffer 102AB is coupled to gate 104B. Each of the gates 103B, 105B, 107B and 109B are enabled by the clock signal PCLK2 SUBSTITUTESHEET produced by the divide by the two counter 102B in the format timing generator 45B, while gate 104B is enabled by the clock signal, PCLK2 supplied by the invertor HOB. In operation, as will be explained hereinafter in greater detail, the encoder logic unit 53B quantizes and encodes the input video data for processing by the pattern logic unit 59B in order to combine video pixel element signals to form a low resolution composite pixel to increase the number of displayable color shadings. In this regard, the encoder logic 53B reduces or quantizes the amount of data that is stored in the bit map memory 56B by disregarding the three least significant bits for each pixel element location and by enabling only the data for every other pixel element to be latched in the buffer 102AB. In this regard, when data is latched into the buffer 102AB on the leading edge of the PCLK2 signal, the four most significant bits of the latched digital signal (e.g. R7-R4) are latched into the output buffer 55B, as signals R3*-R0* respectively. In a similar manner, on the trailing edge of the PCLK2 signal the fourth most significant bit of the latched digital signal (e.g. R3) is latched into the output buffer 55B, (the other digital signals disregarded) . From the foregoing it should be understood that an even byte of video data consisting of 4 bits is temporarily stored in the buffer 55B, along with an odd byte of video data also consisting of 4 bits of which only one bit (e.g. R3*) is of significance for processing purposes (e.g. the other three bits) have been disregarded for processing purposes as will be explained hereinafter in greater detail. Considering now the pattern logic unit 59B in greater detail, with reference to FIG. 25A and Table III, the pattern logic unit 59B comprises a XILINX unit programmed to produce weighted pixel intensities levels according to the truth table shown in Table III. In this regard, the pattern logic unit 59B is coupled between the bit map memory 57B and the video controller 18B for processing the data stored in the bit map memory 57B to increase the number of displayable shading levels of the red component of video data from 8 levels to 29 levels. More particularly, the pattern logic unit 59B in cooperation with the video controller 18B considers the intensity level of individual pixels elements in specific pixel element groupings to generate weighted intensity level panel pixels. In this regard, the pattern logic unit 59B in cooperation with the video controller 18B, retrieves data from the bit map memory 57B for energizing selected pixel elements in the display panel matrix 16B. In this regard, the pattern logic unit 59B compares each five bits of data retrieved from bit map memory 57B relative to an array group or grouping of four pixel elements such a pattern group (FIG. 32) forming single composite panel pixel, such as the panel pixel 30OB (FIG. 32) forming. As explained earlier the encoder arrangement 52B quantizes the NTSC digital video signal by encoding each eight-bit digital signal into a five-bit digital signal indicative of a given color component for a panel pixel. Also as explained earlier, the encoder arrangement 52B also ignores every other NTSC digital video signal. As the encoder arrangement 52B ignores every other panel pixel element for quantizing purposes, each frame of displayed information in the active matrix panel 16B will contain certain columns of pixel elements, such as pixel elements 230B and 231B respectively that will be assigned arbitrary intensity level based upon the input data from the bit map memory 57B. Because of such quantizing, it can best be seen in FIGS. 32 that a pattern array is established in the pixel groupings, to define composite SUBSTITUTE SHEET pixel groups, such as groups 300B-305B (FIG. 32) . Each composite group consists of four pixel elements. As will be explained hereinafter in greater detail, the pattern logic 59B will selectively energize one or more of the pixel elements in each composite group, such as composite group 300B, to form a composite pixel image. It should be understood however, that a set of four possible pixel elements, such as pixel elements 23OB, 225B, 23OB and 23IB may be active in one of the grouping, such as the grouping 300B at one time. However, as the human eye is incapable of distinguishing the individual pixel elements in the rows and columns from one another, the grouping of pixel elements are utilized to define the single composite panel pixel image having in excess of twenty four thousand different shading levels. Stated otherwise, the selectively activated pixel elements 22OB, 225B, 234B and 23IB are combined to form a weighted intensity level of 29 different levels for the red component (as well as the blue and green components) of a given composite panel pixel, such as the panel pixel 300B. In a similar manner, other pixel elements such as pixel elements 221B, 227B, 232B and 223B are also combined to form other composite panel pixels, such as the composite pixel 302B. From the foregoing it should be understood that although the liquid crystal panel 16B normally provides only 8 shades for each of the principal primary colors of red, green and blue, the pattern logic 59B, the combining of video pixel element signals enables in excess of 24 thousand possible color shading combinations for each composite pixel in the active matrix panel 16B. The aforementioned pixel element combining process is possible because the standard NTSC signal is developed for displaying a color image in a pixel element matrix of 320 by 480 pixel elements whereas the active matrix SUBSTITUTE SHEET display panel 16B, is capable of displaying a color image in a pixel element matrix of 640 by 480 pixel element matrix. Accordingly, the video data supplied via the analog to digital converter 5IB includes twice the amount of information that is actually displayed by the panel 16B thus, permitting the combining process. Considering now the pattern logic 59B in greater detail with reference to FIGS. 32 and 33, as each panel pixel element is addressed, such as the panel pixel element 220B, a location signal (PIXEL and LINE) is generated indicative of a quadrant location 0, 1, 2 or 3, for the addressed panel pixel element in the grouping such as the grouping 300B. In this regard, the grouping 300B is configured in - 2x2 matrix array of rows (LINE) and columns (PIXEL) having four quadrant locations 0, 1, 2 and 3. The location signal is then logically combined in the pattern logic 59B with the quantized data retrieved from the bit map memory 57B, identified as i4, i3, i2, il and iO, (Table III) according to the following equations: Ipd2 = (!i4 & pixel & lline # '.iO & U4 & lline # lil & !i4 & pixel # !il & !i4 & "line . # !i0 & !il & U4 # Ii2 & Ii4 # !i3 & !i4) ; !pdl = (!i0 & !i3 & lline # lil & ii3 & pixel # !il & !i3 & lline # !i0 & !il & U3 -# iO & il & i2 & i3 & !i4 & 1pixel # iO & i2 & i3 & !i4 & !pixel & line # !i2 & !i3) ; !pd0 = (lil & ii2 & pixel # lil & 1 x2 & lline # iO & il & i2 & !i3 & !pixel # iO & i2 & !i3 & !pixel & line # il & i2 & !i4 & line # iO & i2 & !i4 & !pixel & line # !i2 & pixel & lline # iO & il & i2 & !i4 & !pixel # il & i2 & !i3 & line # !iO & !i2 & lline # !iO & !il & !i2) ; where the signals !pd2, !pdl, and !pdO are indicative of the 3 bit red component signal (R) shown generally at 59AB (FIG. 31) . The intensity of the color emitted from each panel pixel element, such as a panel pixel element 22OB, is thus dependent upon the four even bits R e and the one odd bit R g retrieved from the bit map memory 57B, identified as input data i4, i3, i2, il and iO, combined with the pixel (PIXEL) and a line (LINE) location. Considering now the Table III in greater detail. Table III is a truth table which represents the operation of the pattern logic unit 59B. The truth table comprises three columns, an input data column, a location data column, and an output data column. It should be noted that the data in the truth table is given in base 10 representation rather than base 2. The following examples are designed to illustrate how the truth table functions. EXAMPLE 1. The input bits i4, i3, i2, il and iO are 00000 2 or 0 10 . The PIXEL and LINE bits are 00 2 or 0 10 . With these bits as input data the pattern logic unit 59B computes the output data, pd2, pdl and pdO according to the equations given above. In this example, the output bits are 000 2 or 010, as shown in column three of the truth table. Note that in this example, where the input bits i4, i3, i2, il and iO are 00000 2 or 0 10 , the output bits will always be 0 10 , the output bits will always be 0 10 , no matter what the value of PIXEL and LINE may be. SUBSTITUTESHEET EXAMPLE 2. The input bits i4, i3, i2, il and iO are 01101 2 or 13 10 . The PIXEL and LINE bits are 00 2 or 0 1Q . From column three, output data, of the truth table the output bits pd2, pdl, and pdO are determined to be 011 2 or '10* EXAMPLE 3. The input bits i4, i3, i2, il and iO are 01101 2 or 13 10 as in EXAMPLE 2. However, PIXEL and LINE bits have a value of 11 2 or 3 10 . The output bits pd2, pdl, and pdO are determined to be 011 2 or 3 1Q . EXAMPLE 4. The inputs bits i4, i3, i2, il and iO are 10100 2 or 20 10 . As in EXAMPLE 1, the value of the output bits pd2, pdl, and pdO in this example are not dependent upon the value of the PIXEL and LINE bits. In this EXAMPLE the output will be 101 2 or 5 10 irregardless of the value of PIXEL and LINE. Using the above examples as guides, one skilled in the art will be able to determine the value of all the possible output data bits pd2, pdl, and pdO which establishes the intensity level of each of the color components for any given panel pixel element, such as the panel pixel element 12OB, based upon the input data bits i4, i3, i2, il and io PIXEL and LINE. TABLE III SUBSTITUTE SHEET TABLE III TABLE III SUBSTITUTE SHEET TABLE III TABLE III FIG. 33 is similar to FIG. 32 except that the phase of the assigned pixel locations 0, 1, 2, 3 has been reversed in order to reduce, if not substantially eliminate pattern formation is between successive frames of displayed information. Phase reversal is produced through the video controller 18B, and more specifically the exclusive or gate 70B. In this regard, the or gate 100B generates the flicker inhibit signal PVSYNC2 which reverses the ASSIGNED columns and lines as shown in dotted line FIG. 32 to conform to the assigned columns and lines as shown in dotted line FIG. 33. Such phase reversal occurs every other frame. While particular embodiments of the present invention have been disclosed, it is to be understood that various different modifications are possible and are contemplated within the true spirit and scope of the appended claims. There is no intention, therefore, of limitations to the exact abstract or disclosure herein presented.

Claims: What is claimed is: 1. A video display unit for coupling a television formatted video signal for driving a television monitor into a digital video signal for driving a high speed display device, said unit comprising: signal conversion means for converting the video signal into an analog video signal; analog to digital conversion means for transforming the analog video signal into a digital signal; scaling means for formatting said digital signal into a digital video signal suitable for driving a high speed display device. 2. A high speed color display unit for interfacing a television signal producing device to a high speed display device, comprising: signal conversion means for converting a television signal into an analog video signal; analog to digital conversion means for transforming said analog video signal into a digital signal indicative of a full color displayable image; quantizing means coupled to said analog to digital conversion means for substantially eliminating contouring in said full color displayable image; scanning means for formatting said digital signal into a sequence of frames of full color displayable images, each frame having a pixel array format suitable for display by the high speed display device; and acceleration means for modulating the formatted digital signals into video signals for driving the high speed display device. 3. A high speed color display system for use with a signal producing device for producing a television formatted signal, said system comprising: SHEET high speed display means for displaying a color image; and high speed color enhancing interface controller means for coupling said high speed display means to said video drive module; said controller means including: analog to digital conversion means for transforming the analog video signal into a digital signal; quantizing means coupled to said analog to digital conversion means for substantially eliminating contouring in a displayed video image; acceleration means for modulating the video signal to drive said high speed display device; and scaling means for substantially eliminating extraneous beat patterns and flicker in said displayed video image. 4. A high speed color display system for use with a personal computer having a video drive module for producing an analog video signal, said system comprising: high speed display means for displaying a color image; and high speed color enhancing interface controller means for coupling said high speed display means to said video drive module; said controller means including: analog to digital conversion means for transforming the analog video signal into a digital signal; quantizing means coupled to said analog to digital conversion means for substantially eliminating contouring in a displayed video image; acceleration means for modulating the video signal to drive said high speed display device; and scaling means for substantially eliminating extraneous beat patterns and flicker in said displayed video image. T HEET 5. A method of displaying a color video image, comprising the steps of: transforming an analog color video signal into a digital signal; quantizing said digital signal; inhibiting contouring caused by quantizing said digital signal; modulating said quantized digital signal to drive a high speed display device; and eliminating extraneous beat patterns and flicker causing signals in said modulated digital signal. 6. A high speed color display unit for interfacing a personal computer to a high speed display device, comprising: coupling means for electrically connecting the personal computer to the high speed display device; said coupling means including analog to digital conversion means for transforming an analog color video signal into a digital signal; quantizing means coupled to said analog to digital conversion means for substantially eliminating contouring in a displayed video image; acceleration means for modulating the video signal to drive a high speed display device; and scaling means for substantially eliminating extraneous beat patterns and flicker in said displayed video image. 7. A high speed color enhancing interface controller for coupling a personal computer to a high speed display device, said controller comprising: said controller means including: analog to digital conversion means for transforming the analog video signal into a digital signal; scaling means for substantially eliminating extraneous beat patterns and flicker in said displayed video image. 8. A method for displaying a color image comparing the steps of: said controller means including: analog to digital conversion transforming the analog video signal into a digital signal; scaling substantially eliminating extraneous beat patterns and flicker in said displayed video image. 9. An arrangement for interfacing a television formatted video signal to a display device, said arrangement comprising: signal conversion means for converting a received signal into an analog video signal; analog to digital conversion means for transforming said analog video signal into a digital signal; and pattern means for formatting said digital signal into a digital video signal for defining a portion of a composite pixel displayed by the display device. 10. A color display unit for interfacing a television signal producing device to a display device, comprising: signal conversion means for converting a composite television signal into an RGB analog video signals; analog to digital conversion means for transforming said analog video signal into individual digital signals indicative of a full color displayable image; scaling means coupled to said analog to digital conversion means for quantizing said digital signaxs for storage purposes; bit memory means for storing said quantized digital signals; and pattern means for retrieving individual ones of said digital signals and for formatting said digital signals into groups of binary signals for driving individual pixel elements defining a composite pixel to produce a full color image. 11. A method for producing a full color image: converting a composite television signal into a continuous series of RGB analog video signals; transforming said analog video signals into groups of digital signals said groups of signals being indicative of a full color displayable image; quantizing selected ones of said digital signals for storage purposes; storing the quantized digital signals; retrieving the quantized digital signals; and formatting the retrieved quantized digital signals into groups of binary signals for driving individual pixel elements in a matrix defining a composite pixel to produce a full color image. 12. A method for displaying a full color image, comprising: receiving an analog signal; converting said analog signal into a video analog signal indicative of different color shading levels and control signals for displaying a color image; converting said video analog signal into a digital signal; quantizing said digital signal into a plurality of pairs of pixel information; grouping said pairs of pixel information into pixel information arrays corresponding to groups of pixel elements arrays in a matrix display; SUBSTITUTE SHEET comparing individual ones of said pixel information arrays with a group of pattern arrays; and generating a group of binary signals indicative of a shading level for an individual pixel element in said matrix display whenever individual ones of said pixel information arrays compares with an individual pattern array in said group of pattern arrays.

Inventors: FARWELL RANDALL S, HAUCK LANE T, SHAPIRO LEONID, SHAW ROBERT, FARWELL, RANDALL, S., HAUCK, LANE, T., SHAPIRO, LEONID, SHAW, ROBERT
Applicants: PROXIMA CORP, PROXIMA CORPORATION
Application year: 1991
Main classification: G09G5
IPC codes: G09G5, H04N5