Cell array of a non-volatile semiconductor memory device

Abstract: A cell array of non-volatile memory semiconductor memory device includes a semiconductor substrate (1) having a first conduction type, a first insulating film (2, 4) formed on the semiconductor substrate, and a plurality of active regions (8) formed in the semiconductor substrate, each of the active regions having a second conduction type opposite to the first conduction type. The cell array also includes a plurality of floating gate electrodes (5, 15) formed on the first insulating film, a second insulating film (6) covering the floating gate electrodes, a plurality of control gate electrodes (7, 17) which are formed on the second insulating film and which run above the floating gate electrodes, and bit lines (BL) electrically coupled to the active regions. Each of the active regions has a substantially H-shaped surface portion close to adjacent four of the floating gate electrodes.

Description: BACKGROUND OF THE INVENTION The present invention generally relates to non-volatile semiconductor memory devices, and more particularly to a cell array of an erasable and programmable read only memory device having a floating gate and a control gate. FIG.1 shows a conventional erasable and programmable read only memory (EPROM) disclosed in USP 4,839,705 or Japanese Laid-Open Patent Publication No. 56-130975 (which corresponds to U. S. Patent Application S. N. 88,789 (US-A-4 281 397) filed on October 29, 1979). Active regions of a plurality of EPROM cells T11, T12, T21 and T22 are electrically coupled through a bulk interconnection line. The EPROM cells T11, T12, T21 and T22 are arranged as follows. Selective oxide films (field insulation (oxidation) films) 1b having rectangular plans are formed on a top surface of a semiconductor substrate 1a and spaced apart from each other so that the field insulation films 1b are arranged in a matrix. Regions surrounded by the field insulation films 1b are arranged in a grid and serve as element formation regions 1c. Floating gate electrodes 1e are formed at a center part of belt-shaped portions 1d. An insulating film is formed on the entire surface including the floating gate electrodes 1e, and control gate electrodes 1f are formed on the insulating film so that the control gate electrodes 1f overlap with the floating gate electrodes 1e. Active regions 1g are formed on both sides of the gate electrodes 1e and 1f by a self-alignment process. The active regions 1g are integrally formed in X-shaped regions of the element formation regions 1c so that the EPROM cells T11, T12, T21 and T22 are coupled. The control gate electrodes 1f are formed at an angle of about 45° with respect to the direction in which the belt-shaped portions run, and arranged so that the control gate electrodes 1f run above the floating gate electrodes 1e. The floating gate electrodes 1e and the control gate electrodes 1f have belt-shaped portions so that they are orthogonal to the belt-shaped portions 1d. An interlayer insulating film (not shown) is formed on the control gate electrodes 1f. Contact holes 1h are formed at positions of the interlayer insulating film which correspond to the center portions of the X-shaped portions of the active regions 1g. Bit lines BL, which are formed on the interlayer insulating film, are formed so that the bit lines BL are electrically in contact with the active regions 1g through the contact holes 1h. A device including the EPROM cells T11, T12, T21 and T22 has an equivalent circuit shown in FIG.2. For example, when the cell T22 is selected, a signal is applied to the control gate electrode 1f of the cell T22 via a word line WL2, and signals are applied to the two active regions 1g through bit lines BL2 and BL3. The floating gate electrodes 1e and the control gate electrodes 1f are formed as follows. Referring to FIG.3A, a first polysilicon film 1i provided for forming the floating gate electrodes 1e is formed on the entire surface. Next, the first polysilicon film 1i is patterned so that patterned portions run parallel to the bit lines BL, that is, the patterned portions are inclined at approximately 45° with respect to the long-side directions of the belt-shaped portions 1d in which the long-side edges thereof run. As shown in FIG.3B, a second polysilicon film 1j provided for forming the control gate electrodes 1f is formed on the entire surface including the interlayer insulating film. After that, as shown in FIG.3C, the first and second polysilicon films 1i and 1j are patterned. Thereby, the floating gate electrodes 1e and the control gate electrodes 1f are formed so that they have no positional error in the width direction thereof. It should be noted that ends of the floating gate electrodes 1e are close to the belt-shaped portions 1d of the element formation regions 1c. If a patterning error occurs during the step where the first polysilicon film 1i is patterned, as shown in FIG.4A, one of the two ends of the floating gate electrode 1e is positioned above the belt-shaped portion 1d and the floating gate electrode 1f is positioned above the belt-shaped portion 1d. Thus, as shown in FIG.4B, the control gate electrode 1f has a portion which does not overlap with the floating gate electrode 1e. As is well known, the threshold voltage of the EPROM cell transistor varies due to the existence/non-existence of a charge stored in the floating gate electrode 1e of the transistor. This variation in the threshold voltage is used for storing information. For example, when the floating gate electrode 1e is electrified so that it has a negative polarity, a channel is not formed in the semiconductor substrate 1a even if a predetermined voltage is applied to the control gate electrode 1f. Thus, no current passes between the active regions 1a located on both sides of the floating gate electrode 1e, so that the transistor is maintained in the OFF state. In this way, data is written into the EPROM cell. On the other hand, when the floating gate electrode 1e is not electrified, the electric field caused by applying a voltage to the control gate electrode 1f is not reduced by the floating gate electrode 1e. Thus, a channel is formed under the floating gate electrode 1e, so that a current passes between the active regions 1g located on both sides of the floating gate electrode 1e. In this way, no data is written into the EPROM cell. In the case where the control gate electrode 1f positionally deviates from the floating gate electrode 1d with respect to the belt-shaped portion 1d, the electric field formed by the control gate electrode 1f directly affects the semiconductor substrate 1a. The above-mentioned positional deviation of the floating gate electrode 1e forms a portion which cannot prevent the formation of the channel. This increases errors in readout data. From US-A-4,281,397 and DE-A-3833726 a cell array of a non-volatile semiconductor memory device according to the preamble of claim 1 is known. Furthermore, US-A-4,281,397 proposes to use each of the active regions commonly for each of the four adjacent transistors and DE-A-3833726 describes a floating gate which has a rectangular surface portion. SUMMARY OF THE INVENTION It is a general object of the present invention to provide an improved cell array of a non-volatile semiconductor memory device, in which the above-mentioned disadvantages are eliminated. A more specific object of the present invention is to provide a cell array in which data can be definitely read even if a positional error caused at the step where the floating gate electrodes are formed occurs. The above-mentioned objects of the present invention are achieved by a cell array of a non-volatile semiconductor memory device as defined in claim 1. BRIEF DESCRIPTION OF THE DRAWINGS Other objects, features and advantages of the present invention will become apparent from the following detailed description when read in conjunction with the accompanying drawings, in which: FIG.1 is a plan view of a conventional array of EPROM cells; FIG.2 is a circuit diagram of a conventional EPROM device having the array shown in FIG.1; FIGS.3A, 3B and 3C are diagrams illustrating a process of producing the array shown in FIG.1; FIGS.4A and 4B are diagrams illustrating a disadvantage of the conventional array shown in FIG.1; FIG.5 is a plan view of an example of an array of EPROM cells; FIG.6A is a cross-sectional view taken along line VI A -VI A shown in FIG.5; FIG.6B is a cross-sectional view taken along line VI B -VI B shown in FIG.5; FIGS.7A, 7B and 7C are diagrams showing a process of producing the array shown in FIG.5; FIGS.8A and 8B are diagrams showing an advantage of the example shown in FIG.5; FIG.9 is a plan view of an array according to a preferred embodiment of the present invention; and FIGS.10A and 10B are diagrams showing an advantage of the array shown in FIG.9. DESCRIPTION OF THE PREFERRED EMBODIMENT A description will now be given of an example of a cell array with reference to FIGS.5, 6A and 6B. The cell array has a silicon semiconductor substrate 1 having a predetermined conduction type. A plurality of selective oxide films (field insulation films) 2 are formed on a top surface of the silicon substrate 1, and long-side edges of the field insulation films 2 run in an identical direction. The field insulation films 2 are spaced apart from each other at a definite distance and alternately arranged. Regions surrounded by the field insulation films 2 are element formation regions 3, on which thermal oxidation films 4 are formed. Floating gate electrodes 5 are formed on the thermal oxidation films 4 on the element formation regions 3 as if the floating gate electrodes 5 couple the adjacent field insulation films 2. As shown in FIG.6B, two end portions of each of the floating gate electrodes 5 lie on the two adjacent field insulation films 2. Each of the floating gate electrodes 5 has two opposite ends parallel to the direction in which the long-side edges of the field insulation films 2 run. In addition, the opposite ends of the floating gate electrodes 5 arranged in the direction in which the long-side edges of the field insulation films 2 run are located on identical imaginary lines. As shown in FIG.6A, an insulating film 6 formed of SiO 2 is formed on the floating gate electrodes 5. Control gate electrodes 7 are formed on the SiO 2 film 6. Each of the control gate electrodes 7 is arranged so that it crosses the long-side edges of the field insulation films 2 and it runs above some of the floating gate electrodes 5. Each of the control gate electrodes 7 has a width which is substantially identical to that of each of the floating gate electrodes 5. The control gate electrodes 7 are made of, for example, doped polysilicon. If the side-end portions of the floating gate electrodes 5 and the side-end portions of the control gate electrodes 7 are very close to the short-side edges of the field insulation films 2, abrupt step portions will be formed between the surface of the silicon substrate 1 and the control gate electrodes 7. In order to eliminate this problem, the floating gate electrodes 5 and the control gate electrodes 7 are positioned so that they are spaced apart from the short-side edges of the field insulation films 2 at a distance enough to obtain smooth step portions (in other words, they are located to positions close to center portions of the thermal oxidation films 4). The floating gate electrodes 5 and the control gate electrodes 7 are obliquely arranged at an angle of approximately 45° with respect to the long-side edges of the field insulation films 2 so that they obliquely cross the element formation regions 3. Active regions 8, which have a conduction type opposite to that of the silicon substrate 1, are formed by a self-alignment process in which impurities are introduced into the element formation regions 3 on both sides of each of the floating gate electrodes 5. Each of the active regions 8 is integrally formed along the long-side and short-side edges of the field insulation films 2 and extends up to the side-end portions of the other floating gate electrodes 5. Each of the active regions 8 has a substantially H-shaped surface portion illustrated by a thick solid line shown in FIG.5. Channel formation regions are formed in portions of the silicon substrate 1 which are located under the floating gate electrodes 5 and which are sandwiched between the neighboring active regions 8. An EPROM cell T is formed by the portion of the silicon substrate 1 in the element formation region 3, the floating gate electrode 5, the control gate electrode 7 and the active regions 8 located on both sides of these electrodes. As shown in FIG.6B, an insulating film 9 formed of, for example, SiO 2 , is formed on the entire surface. As shown in FIG.5, contact holes 10, which are located at positions interposed between the short-side edges of the field insulation films 2, are formed in the SiO 2 film 9 and the thermal oxidation films 4. Bit lines BL are formed on the SiO 2 film 9 so that they run parallel to the long-side edges of the field insulation films 2. The bit lines BL are electrically in contact with the center portion of the H-shaped active regions 8 through the contact holes 10. A description will now be given of the operation of this example. Four EPROM cells T, which are coupled via the H-shaped active region 8, are electrically coupled to the bit line BL which runs over the above H-shaped active region 8. The control gates 7 are coupled to the word lines WL. Thus, this example has the same equivalent circuit as the device shown in FIG.2. A voltage is applied to the control gate electrode 7 via the corresponding word line WL, and a voltage is applied across the active regions 8 via the neighboring two bit lines BL, so that a desired EPROM cell T is selected. When no charge is stored in the floating gate electrode 5 in the selected EPROM cell T, a channel is generated in the portion of the silicon substrate 1 under the floating gate electrode 5, so that the carrier is allowed to move. Thus, a current passes through the bit line BL, so that it can be recognized that no information is stored in the selected EPROM cell T. On the other hand, when a charge is stored in the floating gate electrode 5, no channel is generated and no current passes through the bit line BL, so that information has been written into the selected EPROM cell T. A description will now be given of a process of producing this example First, the field insulation films 2 formed of SiO 2 are formed to a thickness equal to, for example, 5000 angstroms (1 angstrom = 0.1 nm) by a LOCOS process. After the SiO 2 films 4 are formed to a thickness of about 200 angstroms by a thermal oxidation process, a polysilicon film for forming the floating gate electrodes 5 is deposited to a thickness of, for example, 1000 angstroms on the SiO 2 film 4 by a CVD process. POCl 3 is thermally diffused into the polysilicon film at 850°C. After that, as shown in FIG.7A, the polysilicon film is patterned into films 5a running parallel to the long-side edges of the field insulation films 2 by a conventional photolithography technique and an RIE etching in which a gas of CCl 4 /O 2 is used. Then, the SiO 2 film 6 is thermally formed to a thickness of, for example, 250 angstroms. Then, as shown in FIG.7B, a polysilicon film 7a used for forming the control gate electrodes 7 is deposited to a thickness equal to, for example, 2000 angstroms by a CVD process. POCl 3 is thermally diffused into the polysilicon film at 850°C. After that, the polysilicon films 5a and 7a are patterned into a belt shape at the same time, so that the floating gate electrodes 5 and the control gate electrodes 7 are defined. After that, the SiO 2 film 9 is formed to a thickness of, for example, 200 angstroms on the surface of the control gate electrodes 7 by a thermal oxidation process. As + ions are introduced at 4 x 10 15 /cm 2 at 70 keV, and an insulating film is formed by a CVD process . It is preferable to form a BPSG (boron phosphosilicate glass) film to a thickness of, for example, 5000 angstroms, on the entire surface. Then, the BPSG film is subjected to a reflow process in order to flatten the surface thereof. The contact holes 10 are formed in the BPSG film, the SiO 2 film 9, and the SiO 2 film 4 by the photolithography technique and RIE process in which a gas of CHF 3 /He is used. After that, Al bit lines are formed. If a positional error occurs during the patterning process in which the polysilicon films 5a (FIG.7B) are defined occurs, as shown in FIG.8A or FIG.8B, one of the ends of the floating gate electrode 5 does not enter the element formation region 3, and the floating gate electrode 5 and the control gate electrode 7 completely overlap with each other. It should be noted that the two opposite short-side ends of the floating gate electrodes 5 run substantially parallel to the long-side edges of the element formation regions 3. Since the floating gate electrode 5 and the control gate electrode 7 completely overlap with each other, all the electric field resulting from the control gate electrode 7 in the element formation region 3 is applied to the silicon substrate 1 through the floating gate electrode 5. On the other hand, when the charge is stored in the floating gate electrode 5, no channel is formed under the control gate electrode 7. It should be noted that each field insulation film 2 has a substantially square plan area in place of the rectangular plan area. A description will now be given of a preferred embodiment of the present invention with reference to FIGS.9, 10A and 10B. In the aforementioned example, the floating gate electrodes 5 and the control gate electrodes 7 run on the thermal oxidation films 4 in the direction perpendicular to the direction in which the long-side edges of the thermal oxidation films 4 extend, and obliquely cross the element formation regions 3. Thus, the floating gate electrodes 5 and the control gate electrodes 7 have bent portions in the vicinity of the element formation regions 3. The adjacent control gate electrodes 17 are spaced apart from each other at a maximum or minimum distance at each bent portion thereof. On the other hand, as shown in FIG.9, control gate electrodes 17 have less-than-sign (greater-than-sign) shaped surface portions on the field insulation films 2. Floating gate electrodes 15 beneath the control gate electrodes 17 have a substantially parallelogram surface shape. That is, two opposite short-side ends of each of the floating gate electrodes run in parallel to the long-side edges of the field insulation films 2, and two opposite long-side ends thereof run parallel to each other. It should be noted that the area of each floating gate electrode 15 on the element formation region 3 does not change even if the floating gate electrode 15 has any positional error, as shown in FIG.10A or 10B. Thus, the readout potential and write potential are not affected by such a positional error. That is, a potential V FG of the floating gate electrode 15 is defined as follows: V FG = K(V CF + Q/C1) where C1 is a coupling capacitance C1 between the floating gate electrode 15 and the control gate electrode 7, C2 is a coupling capacitance between the floating gate electrode 15 and the semiconductor substrate 1, Q is a charge stored in the floating gate electrode 15, V CF is a voltage applied to the control gate electrode 17, and k is a coupling ratio defined as k = (C1/(C1 + C2)) . It can be seen from the above formula that if the coupling capacitance C1 and/or coupling capacitance C2 change, the potential V FG changes, so that the stability of data reading or writing is deteriorated. It will be noted that the arrangement according to the array shown in Fig.5-8 has a possibility that the coupling capacitance C2 changes due to a positional error of the floating gate electrode 5. The embodiment shown in Fig.9 and 10 does not have such a possibility.

Claims: A cell array of non-volatile semiconductor memory devices, comprising a semiconductor substrate (1) having a first conduction type; a first insulating film (2, 4) formed on said semconductor substrate, said first insulating film (2, 4) comprising field insulation films spaced apart from each other; a plurality of active regions (8) formed in said semiconductor substrate, each of said active regions having a second conduction type opposite to said first conduction type; a plurality of floating gate electrodes (5, 15) formed on said first insulating film, wherein each of said floating gate electrodes (5, 15) comprises two opposite portions on two adjacent field insulation films (2); a second insulating film (6) covering said floating gate electrodes; a plurality of control gate electrodes (7, 17) which are formed on said second insulating film und which run above said floating gate electrodes; and bit lines (BL) electrically coupled to said active regions and being in contact with the center of said active regions at positions which are symmetrically located with respect to four adjacent transistors, wherein each of said active regions (8) is commonly provided to said four adjacent transistors, characterized in that each of said floating gate electrodes (15) has a substantially parallelogram shape, wherein two adjacent edges of said substantially parallelogram shape enclose an angle other than 90°. A cell array as claimed in claim 1, wherein each of said active regions (8) has a substantially H-shaped surface portion close to four of said floating gate electrodes (15), said H-shaped surface portion comprising two substantially parallel elongated side portions connected by a middle portion which is substantially perpendicular to said elongated side portions, wherein each of said floating gate electrodes (15) has two opposite side ends extending in the same direction as the respective control gate electrode (17) and running substantially parallel to an adjacent side edge of one of said elongated side portions of said substantially H-shaped surface portion, wherein the other elongated side portion of said H-shaped surface portion has a side edge being opposite and parallel to said side edge of said elongated side portion adjacent to said side ends of said floating gate electrode (15). A cell array as claimed in claim 1, wherein each of said active regions (8) has a substantially H-shaped surface portion close to four of said floating gate electrodes (15); said adjacent four of the floating gate electrodes (5, 15) comprise respective oblique portions which extend obliquely with respect to predetermined opposite edges of said field insulation films; and said substantially H-shaped surface portion (8) has edges defined by said respective oblique portions. A cell array as claimed in claim 3, wherein said substantially H-shaped surface portion (8) has edges defined by two adjacent field insulation films out of said field insulation films. A cell array as claimed in claim 1, wherein each of said active regions (8) has a substantially H-shaped surface portion close to four of said floating gate electrodes (15); said first and second insulating films have a contact hole (10) located at a substantially central portion of said substantially H-shaped surface portion; and said H-shaped surface portion is electrically in contact with predetermined bit lines out of said bit lines. A cell array as claimed in claim 1 wherein each of said control gate electrodes (17) has a substantially less-than-sign shaped portion located on one of said field insulation films. A cell array as claimed in claim 1, wherein each of said control gate electrodes (17) has a first bent portion where two adjacent control gate electrodes are spaced apart from each other at a first distance, and a second bent portion where said two adjacent control gate electrodes are spaced apart from each other at a second distance less than said first distance. A cell array as claimed in claim 1, wherein each of said field insulation films has a substantially rectangular surface portion. A cell array as claimed in claim 1, wherein each of said field insulation films has a substantially square surface portion. A cell array as claimed in claim 1, wherein each of said active regions (8) has a substantially H-shaped surface portion close to four of said floating gate electrodes (15), said H-shaped surface portion comprising two substantially parallel elongated side portions connected by a middle portion which is substantially perpendicular to said elongated side portions; and wherein said side portions of said substantially H-shaped surface portion of each of said active regions (8) each run parallel to predetermined opposite edges of said field insulation films. A cell array as claimed in claim 10, wherein said predetermined opposite edges of said field insulation films (2) run in a direction in which said bit lines run. A cell array as claimed in claim 1, wherein said field insulation films (2) are spaced apart from each other by a predetermined distance and are alternately arranged. A cell array as claimed in any one of claims 1-2, wherein said first insulating film (2, 4) has two opposing ends which are substantially parallel to two opposing ends of each of said floating gate electrodes (5, 15).

Inventors: EMA TAIJI, EMA, TAIJI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1991
Main classification: H01L27
IPC codes: H01L27, H01L21, H01L29