Process of fabrication of a semiconductor device having element regions being electrically isolated from each other

Abstract: A semiconductor device of this invention is characterized in that one element region (14a) is electrically isolated from another element region (14b) adjacent thereto by forming a groove (15a) surrounding the one element region (14a) and a distance between the groove (15a) surrounding the one element region (14a) and a groove (15b) surrounding the another element region (14b) is set to be equal to or larger than 3 µm.

Description: This invention relates to a process for fabricating a semiconductor device, and more particularly to the improvement of a technique for isolation between element regions. general, in a semiconductor integrated circuit, a plurality of element regions which are electrically isolated from one another are formed in the main surface of a semiconductor substrate and active elements and passage elements are formed in the element regions. As a method of isolating the element regions from one another an isolation technique using PN junctions, an isolation technique using oxide films and an isolation technical using grooves are known. The conventional semiconductor device and the method for manufacturing the same are explained below by using the isolation technique using the oxide films as an example. Fig. 1 shows the conventional semiconductor integrated circuit in which the isolation technique using the oxide films is used. In a silicon substrate 1, element regions 2a, 2b, ... are formed. The element regions 2a, 2b, ... are surrounded by grooves 3a, 3b, ... An oxide film 4 is formed on the field region and the internal surfaces of the grooves 3a, 3b, ... Polysilicon layers 5 are buried in the grooves 3a, 3b, ... in which the oxide film 4 is formed. Thin cap oxide films 6 are formed on the grooves 3a, 3b, ... in which the polysilicon layers 5 are buried. The element isolation in the above semiconductor integrated circuit is effected as follows. First, the grooves 3a, 3b, ... surrounding the element regions 2 are formed in the silicon substrate 1 by an anisotropic etching technique. Then, a non-oxide film (Si 3 N 4 ) such as a nitride film is formed on the element regions 2. After this, the oxide film 4 is formed on the field region and the internal surfaces of the grooves 3a, 3b, ... with the non-oxide film used as a mask. After formation of the oxide film 4, the polysilicon layers 5 are buried in the grooves 3a, 3b, ... Further, the polysilicon layers 5 are made flat and then the thin cap oxide films 6 are formed on the grooves. In the integrated circuit thus formed, a distance W TT between the side wall of the groove 3a and the side wall of the groove 3b is designed to a minimum possible length in order to enhance the integration density of the elements. However, it is generally known that as the distance between the grooves becomes shorter, thermal stress is more concentrated on the corner portions of the grooves 3a, 3b, ... in the oxidation process for forming the oxide films 4 on the field region and the internal surfaces of the grooves 3a, 3b, ... More specifically, as shown in Fig. 2, dislocation defects 9 may be caused in the upper corner portions 7 and bottom corner portions 8 because of the concentration of thermal stress at the time of oxidation. The dislocation defects 9 increase leak current between the collectors of transistors formed in the silicon substrate. Further, the transistor characteristic such as the I C (collector current)-h FE (grounded emitter current amplification factor) characteristic will be deteriorated. That is, if the dislocation defects 9 occur at a certain density, recombination current around the defect increases to deteriorate the element characteristic and element isolation characteristic, making the semiconductor device definitely impractical. European application 0 402 897 discloses a semiconductor device having elements isolated by a trench having a width of about 1 to 2 µm, an interval between adjacent trenches being about 3µm. Oxide films each having a thickness of less than 0,9 µm are formed on field regions located between the element regions and the trenches and on the side walls of the trenches. Bipolar transistors are formed in the isolated elements. From EP 0 020 994 a method of making isolation trenches is known. This invention has been made to solve the above problems, and an object of this invention is to provide a semiconductor device in which occurrence of dislocation defects in the upper and bottom corner portions of the element isolation grooves can be suppressed and deterioration of the element characteristic and the element isolation characteristic can be prevented. This object is solved by claim 1. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figs. 1 and 2 are cross sectional views each showing the conventional semiconductor device; Fig. 3 is a perspective view showing a semiconductor device according to one embodiment of this invention; Figs. 4A to 4C are cross sectional views showing a method of manufacturing the semiconductor device shown in Fig. 3; Fig. 5 is a characteristic diagram showing a characteristic of the semiconductor device of this invention; and Fig. 6 is a cross sectional view showing a semiconductor device according to another embodiment of this invention. Now, a method for manufacturing a semiconductor device is explained in detail. The process of Fig 3 to 5, carried out on a substrate which is not a SOI substrate, is used for explanation purposes, but does not form part of the invention. Fig. 3 shows a semiconductor device. The semiconductor device has bipolar transistor arrays formed in element regions. That is, an N + -type buried layer 12 is formed on a P-type monocrystalline silicon substrate 11. N-type epitaxial layers 13 are formed on the N + -type buried layer 12. Element isolation grooves 15a, 15b, surrounding element regions 14a, 14b, ... are formed in the silicon substrate 11 and N-type epitaxial layers 13. P + -type impurity regions 16 are formed on the bottom portions of the element isolation grooves 15a, 15b, ... An oxide film 17 is formed on a field region and the internal surfaces of the element isolation grooves 15a, 15b, ... Polysilicon layers 18 are buried in the element isolation grooves 15a, 15b, ... on which the oxide film 17 is formed. Thin cap oxide films 19 are formed on the grooves 15a, 15b, ... in which the polysilicon layers 18 are buried. Further, an N + -type collector lead-out region 20, P-type base region 21 and N + -type emitter region 22 are formed in the N-type epitaxial regions of the element regions 14a, 14b, ... In the above semiconductor device, a W TT distance between the adjacent element regions 14a, 14b, ... is set to 3 µm or more. Further, the width of the element isolation grooves 15a, 15b, ... is set in the range of 1 to 2 µm. The oxide film 17 having a film thickness of not larger than 0.9 µm (9000 Å) is formed on the internal surfaces of the element isolation regions 14a, 14b, ... With the above construction, occurrence of dislocation defects in the upper corner and bottom corner of the element isolation region can be suppressed and therefore the element characteristic and element isolation characteristic will not be deteriorated. Figs. 4A to 4C show a method of manufacturing the semiconductor device shown in Fig. 3. First, as shown in Fig. 4A, an SiO 2 film 21 is formed on the main surface of a monocrystalline silicon substrate 21 formed of a P-type substrate 21a, N + -type buried layer 21b and N-type epitaxial layer 21c by use of a CVD method or thermal oxidation method. Further, a resist pattern 24 is formed on the SiO 2 film 23. After this, the monocrystalline silicon substrate 21 is etched in a vertical direction by use of an RIE (reactive ion etching) method so as to form element isolation grooves 25a, 25b, ... having a width of 1 to 2 µm and a depth of approx. 5 µm. Each of the element isolation grooves 25a, 25b, ... is formed to surround a corresponding one of element regions 26a, 26b ..., and the element isolation grooves 25a, 25b, ... are arranged so that a distance W TT between the adjacent two element isolation grooves may be set to be larger than 3 µm. Next, as shown in Fig. 4B, the SiO 2 film 23 and resist pattern 24 are removed. After this, thermal oxidation is effected in an H 2 and O 2 gas atmosphere at a temperature of approx. 950 °C to form an SiO 2 film 27 having a film thickness of approx 50 nm (500 Å). Further, an Si 3 N 4 film 28 having a film thickness of approx. 0,1 µm (1000 Å) is formed by deposition at a temperature of approx. 780°C by use of an LP-CVD method. Then, a resist pattern 29 is formed on the Si 3 N 4 film 28 by a photo-etching technique. Next, the Si 3 N 4 film 28 is selectively etched by a plasma-etching technique to leave the Si 3 N 4 film (non-oxide film) 28 only in positions above the element regions 26a, 26b, ... Next, as shown in Fig. 4C, the resist pattern 29 is removed. After this, wet oxidation is effected at a temperature of approx. 1000°C with the Si 3 N 4 film 28 used as a mask. As a result, an oxide film 30 having a film thickness of less than 0,9 µm (9000 Å), for example, 0,8 µm (8000 Å) is formed on the field region and on the internal surface of the element isolation grooves 25a, 25b, ... After this, polysilicon layers are buried into the element isolation grooves 25a, 25b, ... by a well known manufacturing method, although not shown in the drawing. After the polysilicon layers are made flat, thin cap oxide films are formed on the element isolation grooves 25a, 25b, ... Further, bipolar transistors are formed in the element regions 26a, 26b, ... Now, the characteristic of the so formed semiconductor device is explained with reference to Fig. 5. Bipolar transistor arrays were formed with a distance W TT between the side wall of one of the element isolation grooves and the side wall of an adjacent one of the element isolation grooves used as parameter. The distance W TT was set at four different values of 1.0, 2.0, 3.0 and 4.0 µm. The film thickness of the field oxide film was set at approx. 0,9 µm (9000 Å) and a distance W TL between the element isolation grooves 15a, 15b, ... and the non-oxide films formed in the surface area of the substrate was set to approx. 3.0 µm. The defects occurring in the upper corners and bottom corners of the element isolation grooves 15a, 15b, ..., the stress applied to the surrounding portion of the element isolation grooves 15a, 15b, ... at the normal temperature, and the density of leak current between the elements were selected as the items to be evaluated. The defects were evaluated by etching off the entire substrate surface after the step of forming the elements and then effecting the Wright etching to selectively etch the defects. After this, the number of defects were counted by observation of the defects by use of an optical microscope and were expressed by the density of defects occurring for the length of 1 mm of the element isolation grooves 15a, 15b, ... The stress applied to the surrounding portion of the element isolation grooves 15a, 15b, ... was measured by a laser Raman microspectroscopy and the maximum stresses applied to the bottom portions of the element isolation grooves 15a, 15b, ... were expressed as the measurements. Further, the density of leak current between the cells was expressed as the current density when the application voltage was set at 12 V by using the I-V characteristic between the current and voltage between the collectors of the transistor cells. In Fig. 5 in which the evaluated items are collectively shown, the abscissa indicates the distance W TT (µm) between the adjacent element isolation grooves, the ordinate (a) indicates the density (A/cm 2 ) of leak current flowing between the cells when a voltage of 12 V is applied between the elements, the ordinate (b) indicates the density of defects (defects/mm 2 ) in the upper corner and bottom corner, and the ordinate (c) indicates the stress (N/m 2 ). That is, when the distance W TT (µm) between the adjacent element isolation grooves is sequentially set to 4.0 m, 3.0 µm, 2.0 µm and 1.0 µm in this order, the stress basically increases and at the same time the defect density increases. The reason why the stress decreases near the point of 1.0 µm is that a large umber of defects are caused by application of an extremely strong stress to reduce the stress. Further, as the distance W TT decreases, the density of leak current between the cells indicating the element isolation characteristic increases. As a result, it is proved that it is preferable to set the distance W TT between the adjacent element isolation grooves 15a, 15b, ... to at least 3.0 µm in order to prevent the element characteristic and element isolation characteristic from being deteriorated. The results presented above have been found also valid when the substrate is a silicon-on-insulator substrate. Fig. 6 shows a semiconductor device according to the invention. The semiconductor device uses a bonded wafer or SOI wafer as a substrate. That is, an oxide film 42 is formed on a monocrystalline silicon substrate 41. Further, a monocrystalline silicon substrate 43 is formed on the oxide film 42. The monocrystalline silicon substrate 43 is polished to have a sufficiently small thickness, for example, a thickness of approx. 5 µm after it is bonded with the substrate 41. Element isolation grooves 44a, 44b, ... are formed in the monocrystalline silicon substrate 43. Oxide films 45 are formed on the field region and the internal surface of the element isolation grooves 44a, 44b, ... Polysilicon layers 46 are buried in the element isolation grooves 44a, 44b, ... on which the oxide films 45 are formed. Thin cap oxide films 47 are formed on the element isolation grooves 44a, 44b, ... in which the polysilicon layers 46 are buried. The distance W TT between the adjacent element isolation grooves 44a, 44b, ... is set to at least 3.0 µm. Further, the oxide films 46 having a film thickness of not more than 0.9 µm (9000 Å) are formed on the internal surfaces of the element isolation grooves 44a, 44b, ... having a width in the range of 1 to 2 µm. With the above construction, occurrence of the dislocation defects in the upper corner and bottom corner of the element isolation groove can be suppressed, and at the same time, the element characteristic and element isolation characteristic will not be deteriorated. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A method of manufacturing a semiconductor device, comprising the following steps: a) providing a SOI wafer, comprising an oxide film (4) between a silicon substrate (41) and a silicon layer (43) as a substrate; b1) forming in said silicon layer (43) insulation grooves (44a, 44b) respectively surrounding an element region (14a, 26a) to electrically isolate the element regions (14a, 26a) from each other; b2) wherein in step b1) a distance W TT between a first element insulation groove (44a) surrounding a first element region (14a, 26a) and a second element insulation groove (44b) surrounding an adjacent element region (14b, 26b) is set to be equal to or larger than 3 µm; c1) thermal oxidizing the resultant structure to form a thermal oxide film (45) on a field region and in each of said element insulation grooves (44a, 44b) surrounding said element regions (14a, 14b, 26a, 26b); and c2) wherein in step c1) said thermal oxide film (45) is formed to have film thickness of not larger than 0.9 µm; and c3) wherein the width of each of said insulation grooves (44a, 44b) respectively surrounding said one and another element regions is set to 1 to 2 µm. A method according to claim 1, characterized in that polysilicon layers (46) are buried into the element insulation grooves (44a, 44b). A method according to claim 1, characterized in that bipolar transistors are formed in said element regions.

Inventors: KOYAMA MITSUTOSHI, MIYASHITA NAOTO, SONOBE HIRONORI, TAKAHASHI KOICHI, KOYAMA, MITSUTOSHI, MIYASHITA, NAOTO, SONOBE, HIRONORI, TAKAHASHI, KOICHI, KOYAMA, MITSUTOSHI, C/O INTELLECTUAL PROPERTY DIV., MIYASHITA, NAOTO, C/O INTELLECTUAL PROPERTY DIV., SONOBE, HIRONORI, C/O INTELLECTUAL PROPERTY DIV., TAKAHASHI, KOICHI, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: H01L21
IPC codes: H01L29, H01L21, H01L27