Method for forming a semiconductor device isolation region

Abstract: A method for forming a semiconductor device isolation region including steps of forming a first silicon oxide film (2) on a silicon substrate (1), depositing a first silicon nitride film (3) over the first silicon oxide film (2), and removing the first silicon oxide film (2) and first silicon nitride film (3) in a device isolation region (5) by using a resist pattern (4), which is formed by a one-time photolithographic step, as a mask so as to expose the surface of the silicon substrate, removing the resist pattern, and oxidizing the exposed surface of the silicon substrate so as to form a second silicon oxide film (4) having a smaller thickness than the first silicon oxide film and to deposit a second silicon nitride film (7), removing the second silicon nitride film (7) by anisotropic etching until the second silicon oxide film (4) is exposed in the device isolation region so as to make the second silicon nitride film remain as the side wall portion (7a,7b) of the silicon nitride film in only the opening side wall portion of the first silicon nitride film, etching the second silicon oxide film in the opening (8) of the first silicon nitride film on a self-aligning basis by using as etching masks the first silicon nitride film and the side wall portion (7a,7b) of the second silicon nitride film remaining on the opening side wall portion of the first silicon nitride film, and selectively carrying out oxidation so as to form a thick silicon oxide film (9) in the device isolation region.

Description: 1. Field of the Invention The present invention relates to a method for forming a semiconductor device isolation region to electrically isolate devices constituting a semiconductor integrated circuit on a silicon substrate. 2. Description of the Prior Art There has been increased the capacity of a VLSI (Very Large Scale Integrated Circuit) such as a DRAM (Dynamic Random Access Memory) or a SRAM (Static Random Access Memory) by four times every three years. At present, the DRAM which is mainly manufactured has the capacities of 256 Kb and 1 Mb. There has earnestly been examined the DRAM having the capacities of 4 Mb and 16 Mb which will be the mainstream in future. Probably, there will be developed the DRAM having the capacities of 64 Mb and 256 Mb. The device constituting an integrated circuit is made fine, so that integration can be improved in a limited chip area as described above. By way of example, the minimum dimension of a MOS transistor used in the 1Mb DRAM is about 1 µm. In future, the above-mentioned minimum dimension will surely be reduced to 0.5 µm and further to 0.25µm. Similarly, it is required to reduce a device isolation region for higher integration. In addition, it is necessary to reduce an isolation width from 1 µm to about 0.5 µm. In general, the device isolation region is formed by a selective oxidation process. Fig. 2 shows the prior art in which the device isolation region is formed by the selective oxidation process. There will be described the conventional selective oxidation process with reference to Fig. 2. (1) As shown in Fig. 2 (a), the surface of a silicon substrate 21 is thinly oxidized to form a silicon oxide film 22 having a thickness of 100 to 700 Å (1 nm = 10Å). Then, a silicon nitride film 23 having a thickness of 1000 to 2000 Å is deposited over the silicon oxide film 22 by LPCVD (Low-Pressure Chemical Vapor Deposition). Then, a resist pattern 24 is formed to define an active region and a device isolation region constituting a semiconductor device. A region K covered by the resist pattern 24 is the active region. An opening 25 of the resist pattern 24 is a device isolation region S . (2) The silicon oxide film 22 and silicon nitride film 23 in the opening 25 of the resist pattern 24 are etched by using the resist pattern 24 as an etching mask. Then, the resist pattern 24 is removed [see Fig. 2 (b)]. (3) When silicon is oxidized by a thermal oxidation process, oxygen is supplied to the exposed surface of the silicon substrate 21 through the opening 25 so as to oxidize the surface of the silicon substrate 21. Consequently, a silicon oxide film 26 is formed. In the active region K , the surface of the silicon substrate 21 is covered by the silicon nitride film 23. Consequently, the oxygen is not supplied to the silicon substrate 21, so that the silicon oxide film is not grown. In the vicinity of the opening 25, the oxygen is diffused through the thin silicon oxide film 22. Consequently, the silicon substrate 21 is oxidized. In addition, the silicon oxide film 26 is widely grown so as to push up the silicon nitride film 23 in the direction of an arrow A . The silicon oxide film 26 is extended below the silicon nitride film 23 so as to form a region 27 having a length of d . The region 27 is generally called a bird's beak [see Fig. 2 (c)]. (4) The silicon nitride film 23 is removed by a heated phosphoric acid solution. Then, the silicon oxide film 22 is removed by a diluted hydrofluoric acid solution. Thus, there is completed device isolation steps by the selective oxidation process [see Fig. 2 (d)]. Then, the semiconductor device such as a transistor is formed in the region 27 in which the surface of the silicon substrate 21 is exposed. The semiconductor devices are electrically isolated from each other by the silicon oxide film 26. As described above, the device isolation region can be formed very easily by the selective oxidation process. Therefore, the selective oxidation process has widely been used as the device isolation technique of the semiconductor device. However, it is required to reduce the device isolation region for the high integration of the semiconductor integrated circuit. In addition, it is necessary to reduce an isolation width from 1 µ m to about 0.5 µ m. The selective oxidation process has the following problems with respect to the reduction of the device isolation region. Consequently, it is difficult to use the selective oxidation process as the device isolation technique of the semiconductor integrated circuit having the higher integration. Referring to the selective oxidation process in Fig 2 (c), the thick silicon oxide film 26 for electrically isolating the devices is grown in the opening 25 of the silicon nitride film 23 as the device isolation region S. In addition, the intrusion of the silicon oxide film 26, which is a bird's beak 27, is generated in the active region K covered by the silicon nitride film 23. The bird's beak 27 has a width of d . Consequently, the isolation region is enlarged by a width of 2d on its both sides. On the other hand, the active region K is reduced by 2d. By way of example, if the width d is 0.3 µm and the minimum pattern opening width is 0.4µm in a photolithographic step, the device isolation region is enlarged by 0.6 µm on both its sides. Consequently, the formable minimum isolation width is 1.0 µm. At present, there is required the device isolation region having a width which is a little less than 0.5 µm as described above. Consequently, it is more difficult to form the device isolation region by the selective oxidation process. DE-A-37 38 643 discloses a method for making isolation layers in high-integration semiconductor circuits which utilizes sidewall spacers formed prior to field oxidation. US-A-4 965 221 also describes a method for providing isolation regions. Sidewall spacers of CVD oxide or polycrystalline silicon are employed. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for forming a semiconductor device isolation region which better meets the requirements for high integration of a semiconductor integrated circuit. The present invention is defined by independent claim 1. The dependent claims 2 to 4 relate to preferred embodiments. The present invention is characterized in that the opening side wall portion of a first silicon nitride film is provided with an offset which is formed by a thin silicon oxide film and a second siliccn nitride film. Consequently, the fineness of a device isolation region can be realized. According to the method of the present invention, the device isolation region can be prevented from being enlarged owing to a bird's beak by a conventional selective oxidation process, i.e., the so-called intrusion of the bird's beak can be controlled. Consequently, the silicon oxide film can almost surely be formed in the device isolation region which is defined in a photolithographic step. Thus, a fine device isolation region can be formed to greatly contribute to the fineness of a semiconductor integrated circuit. Furthermore, the method of the present invention can be realized by only adding a number of steps to the conventional selective oxidation process. Consequently, the increase of manufacturing costs associated with that of the number of steps is comparatively slight. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is an illustration of steps of forming a device isolation region on a silicon substrate according to an embodiment of the present invention; and Figure 2 is an illustration of manufacturing steps of a selective oxidation process as a device isolation method according to the prior art. DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT A preferred embodiment of the preset invention will be described in more detail with reference to the drawings. The present invention is not limited to the following embodiment. Figs. 1(a) to (h) illustrate the method by which a semiconductor device isolation region is formed according to the embodiment of the present invention. (i) As shown in Fig. 1 (a), the surface of a silicon substrate 1 is thinly oxidized to form a first silicon oxide film 2 having a thickness of 100 to 500 Å. Then, a first silicon nitride film 3 is deposited over the first silicon oxide film 2 at a thickness of 1000 to 2000Å by LPCVD. Thereafter, a resist pattern 10 for defining the isolation region is formed in a photolithographic step. With the resist pattern 10 thus formed, a device isolation region S is defined by an opening 5 having a width D of 0.4 µm as shown in Fig. 1 (a). The surface of the silicon substrate 1 in the region covered by the resist pattern 10 is an active region K on which a semiconductor device is to be formed. (ii) As shown in Fig. 1 (b), the first silicon nitride film 3 is processed using the resist pattern 10 as an etching mask by RIE (Reactive Ion Etching). Then, the resist pattern 10 is removed. The first silicon oxide film 2 exposed in the opening 5 is removed by a diluted hydrofluoric acid solution. Consequently, there is exposed a surface 1a of the silicon substrate 1 on which the isolation region is formed. (iii) As shown in Fig. 1 (c), the surface la of the silicon substrate 1 exposed in the opening 5 is thinly oxidized to form a second silicon oxide film 4. It is necessary to make a thickness L of the second silicon oxide film 4 be smaller than that of the first silicon oxide film 2. According to the present embodiment, the thickness L is 80 Å. (iv) As shown in Fig. 1 (d), a second silicon nitride film 7 having a thickness of 500 to 1000 Å is deposited over the whole surface by LPCVD. (v) As shown in Fig. 1 (e), the second silicon nitride film 7 is anisotropically etched by RIE until the second silicon oxide film 4 is exposed in the opening 5. Then, the second silicon oxide film 4 thus exposed is removed by the diluted hydrofluoric acid solution. The residual second silicon oxide film is indicated at 6. As a result, the second silicon nitride film 7 remains only in the stage difference side wall portions of the first silicon nitride film 3. The residual second silicon nitride film 7 is a side wall portion 7a. A width F of the side wall portion 7a is equal to the thickness of the second silicon nitride film 7 which is deposited, and is 500 to 1000 Å. (vi) As shown in Fig. 1 (f), a trench 8 having a depth G of 500 to 2000 Å is formed on the silicon substrate 1 on a self-aligning basis by using as etching masks the first silicon nitride film 3 and the side wall portion 7a of the second silicon nitride film which remains on the stage difference side wall portion of the opening 5. While the second silicon nitride film 7, second silicon oxide film 6 and trench 8 are separately etched in the steps shown in Figs. 1 (d) to (f) in the present embodiment, they may be etched in the same step. (vii) As shown in Fig. 1 (g), when thermal oxidation is carried out, a silicon oxide film 9 is grown in the trench 8 in which the silicon substrate 1 is exposed. In this case, oxygen is not supplied to the surface of the silicon substrate 1 covered by the first silicon nitride film 3 at the time of oxidation. Consequently, the silicon oxide film is not grown. The thin second silicon oxide film 6 is provided just below the side wall portion 7a of the second silicon nitride film. The silicon oxide film is grown so as to push up the second silicon nitride film 7a in the direction of an arrow B by using the second silicon oxide film 6 as an oxygen supply passageway. Since the second silicon oxide film 6 is very thin, a lot of oxygen is not supplied. In addition, the second silicon oxide film 6 is pressed by the first and second silicon nitride films 3 and 7, so that the intrusion of a bird's beak can be made much smaller than in a conventional selective oxidation process. The intrusion of the bird's beak causes a thin silicon oxide film to be grown in the pattern end of the first silicon nitride film 3 which is the boundary of the device isolation region. A thickness d of the silicon oxide film is almost equal to the decrease of the silicon oxide film 9 from the completion of the device isolation step to a step of forming a gate insulating film. The thickness d is about 500 to 1000 Å. The silicon oxide film 9 is grown at the rate of about 1 : 1 around the silicon surface before oxidation. According to the present embodiment, the trench 8 is formed before oxidation. Consequently, the surface of the silicon oxide film 9 can be made comparatively smooth relative to the surface of the silicon substrate 1. On the other hand, there is increased the rate of the silicon oxide film 9 which is grown on the silicon substrate 1 side. Consequently, there can effectively be increased the distance between the semiconductor devices which are formed in the active regions on both sides of the silicon oxide film 9. Consequently, device isolation characteristics can be improved. (viii) The first and second silicon nitride films 3 and 7 are removed by thermal phosphoric acid. Then, the first silicon oxide film 2 is removed by the diluted hydrofluoric acid solution. Consequently, there can be obtained a structure shown in Fig. 1 (h). Thus, a series of steps of forming a device isolation region are completed. Then, a gate insulating film (not shown) is formed in the active region in which the surface of the silicon substrate 1 is exposed. As described above, the decrease of the thickness of the silicon oxide film 9 is equal to the thickness d of the silicon oxide film in the pattern end of the first silicon nitride film 3 [see Fig. 1 (g)]. Consequently, a width W of the silicon oxide film 9 as the device isolation region is equal to the width D of the opening 5 of the resist pattern 4 which defines the device isolation region in Fig. 1 (a) (W = D). A maximum thickness H of the silicon oxide film 9 is about 0.5µm. Even if a maximum thickness T of a silicon oxide film 26 shown in Fig. 2 (d) is about 0.5µm, a distance y between the surface la of the silicon substrate 1 and the top of the silicon oxide film 9 is smaller by 20 to 40 % than a distance x between the corresponding surface of the silicon substrate 21 and the top of the silicon oxide film 26. Consequently, there can be reduced the stage difference owing to the silicon oxide film. The device isolation region is formed in the above-mentioned steps. Then, the semiconductor devices such as MOS transistors or capacitors are formed n normal steps. Consequently, a semiconductor integrated circuit can be obtained. MOS transistors thus formed were measured. As a result, it was found that the MOS transistors were not inferior to transistors which are isolated by the conventional selective oxidation process and have the same size. There cannot be formed by the conventional selective oxidation process MOS transistors having a very small channel width of 0.4 µm because of the spreading of the bird's beak. Also, in these MOS transistors, good characteristics can be obtained. In the case where the distance between adjacent devices is 0.4 µm, there can be obtained very good device isolation characteristics in that both a field punchthrough characteristic and a field inverted voltage are 10V or more. According to the method for forming a semiconductor device isolation region of the present invention, it is possible to extremely control the intrusion of the bird's beak in the active region of the silicon oxide film formed in the isolation region. Consequently, the active region and isolation region can easily be made finer. Accordingly, the present invention can greatly contribute to the high integration of the semiconductor integrated circuit. Referring to the steps of forming a device isolation region, it is sufficient that a number of steps are added to the conventional selective oxidation process. Thus, manufacturing costs can be reduced. The invention may be embodied in other specific ways without departing from its scope as defined by the claims.

Claims: A method for forming a semiconductor device isolation region, comprising: forming a first silicon oxide film (2) on a silicon substrate (1), depositing a first silicon nitride film (3) over the first silicon oxide film (2), and removing the first silicon oxide film (2) and the first silicon nitride film (3) in a device isolation region (5) by using a resist pattern (10), which is formed by a photolithographic step, as a mask so as to form an opening in the first silicon oxide film and the first silicon nitride film and to expose the surface (1a) of the silicon substrate (1); removing the resist pattern (10) oxidizing the exposed surface (1a) of the silicon substrate so as to form a second silicon oxide film (4) having a smaller thickness than the first silicon oxide film (2), and depositing a second silicon nitride film (7); removing the second silicon nitride film (7) by anisotropic etching until the second silicon oxide film (4) is exposed in the device isolation region (5) thus leaving only sidewall portions (7a) of the second silicon nitride film (7) on the side walls of the opening in the first silicon nitride film (3); etching the second silicon oxide film (4) in the opening of the first silicon nitride film (3) on a self-aligning basis by using as etching masks the first silicon nitride film (3) and said side wall portions (7a) of the second silicon nitride film; and selectively carrying out oxidation so as to form a thick silicon oxide film (9) in the device isolation region (5). A method for forming a semiconductor device isolation region according to claim 1, wherein the silicon substrate (1) is also etched to form a shallow trench (8) when etching the second silicon oxide film (4). A method for forming a semiconductor device isolation region according to claim 1, wherein the silicon substrate (1) is etched to form a shallow trench (8) between the step of etching the second silicon oxide film (4) and the selective oxidation step. A method for forming a semiconductor device isolation region according to claim 2 or claim 3, wherein the shallow trench (8) of the silicon substrate (1) has a depth of 50 to 200 nm.

Inventors: KAWAMURA AKIO, KAWAMURA, AKIO
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1991
Main classification: H01L21
IPC codes: H01L21