Workstation and method of configuring same

Abstract: A method for configuring a work station, in particular a system board thereof, by connecting all units (e.g. 62, 64, 66) to be configured in series, and loading one unit after the other with respective configuration data through a latch register and a pointer register.

Description: This invention relates to a work station or a similar data processing system of the kind having a plurality of units which are configured during start up. Known work stations use a specific CPU, e.g. an Intel 80386 microprocessor, provided on a system board together with other chip units such as memories, various peripheral interfaces and a system bus controller. The CPU and the above mentioned units communicate with each other, partially through buffers, over a local bus comprising control, address and data lines. In general, the system design is tailored for the specific CPU. This means that a large variety of different chip units are required for work stations using different CPUs. The local bus also is tailored for the specific configuration. In order to maintain compatibility with other systems, detailed specifications rigidly determine the features and functions of the various units and their I/O registers. Thus, it is difficult to modify the system for expansion and improved performance. Depending on the specific design of the system board and the units to be connected thereto, it is necessary to configure the units of the system board and the cards to be connected thereto, for example when installing the system or making any changes thereto. At one time this was done by switches and other mechanical devices. Recently such mechanical means have been replaced by a so-called Programmable Option Select (POS) installing program which serves to configure the system board and the adapters in a set up mode. With a predetermined rigid system board design, a very small predetermined number of units of the system board are activated via separate set up lines and configured accordingly. However, if it is desired to have the system board considerably expanded by a varying number of further units, configuring thereof becomes difficult. The main reason for that is that the I/O registers on the system board are rather limited and are occupied or reserved for various purposes. It is an object of the present invention to provide a method for configuring a work station having flexible configuration capabilities. It is further object of the present invention to provide a work station having widely expanded configuration capabilities for the system board thereof. In published UK Patent Application No. GB 2 209 079A there is described an arrangement of a CPU connected by a bus to a number of working units themselves each individually connected to associated operational units. The working units are also serially connected to enable them to be activated in sequence. Each working unit comprises an address means hard wired to a functional means which in turn is hardwired to an operational unit. According one aspect of the invention there is provided a work station including a central processing unit and a plurality of functional units, a local bus connecting the central processing unit and the functional units, the functional units being also connected in a series chain by signal lines, each of the functional units generating an activating signal on a respective signal line to activate the next unit in the series, characterised in that each functional unit has: i) a plurality of configuration registers, the configuration registers of different functional units sharing common addresses which are divided into several address ranges receiving predetermined configuration data for each of the functional units; ii) a pointer register, for receiving, when its unit is activated, a sequence of addresses of configuration registers of that unit and selecting the corresponding configuration register, and iii) a latch register, for receiving, when its unit is activated, a sequence of items of configuration data and writing each of such items of data to the configuration register selected by the address in the pointer register. According to another aspect of the invention there is provided a method of configuring a work station which includes a central processing unit, a plurality of functional units and a local bus connecting the central processing unit and the functional units comprising the steps of: supplying data for the functional units from the central processing unit to the local bus, and activating each functional unit in sequence to receive such data, characterised in that each functional unit has a plurality of configuration registers, a pointer register and a latch register and the configuration registers of different units share common addresses which are divided into several address ranges receiving predetermined configuration data for each of the functional units; and the method includes, for each functional unit when activated, the steps of: writing multiple address data and configuration data from the local bus to the pointer register and the latch register respectively, selecting configuration registers in accordance with the address data present in the pointer register, and writing the configuration data present in a latch register to the configuration registers thereof as they are selected by the address data present in the pointer register. In a work station in accordance with the invention, the configuration registers of the functional units share common addresses. The units are activated one at a time with the activated unit being given configuration data corresponding to the common addresses. In this manner, an unlimited number of units of a work station can be configured with a limited number of I/O addresses. One embodiment of the invention will now be described by way of example with reference to the accompanying drawings, in which:- Fig. 1 is a schematic overall view of an embodiment of a work station according to the invention illustrating the various units used and the connections therebetween; Fig. 2A-2E together constitute a schematic drawing showing in detail a host P/M bus as used to connect the various units with each other; Fig. 3 is a block diagram for explaining the specific feature of the invention; and Fig. 4 is a diagram of the registers used with the configuration procedure according to the invention. Fig. 1 shows a preferred embodiment of a work station or data processing system according to the invention. Basically, a CPU 10 communicates through a host P/M bus 20 functional blocks 30, 40, and 50, and in particular with one or a plurality of bus interface blocks BIB 30 for Micro Channel bus access, with one or a plurality of memory interface blocks MIB 40 for memory and cache control, and with a local peripheral and video graphics array (VGA) interface block PIB 50. It should be noted that different types of microprocessors may be used for the CPU 10, such as the Intel 80386, 80386SX, and 80486 microprocessors. Also, a coprocessor 12, such as a mathematical coprocessor Intel 80387, or 80387SX, may be added. The functional block BIB 30 is provided as an interface between the host P/M 20 and a Micro Channel bus 32 provided with a plurality of slots 32a for attaching conventional adapter boards, including adapter boards provided with a microprocessor which may act as a master in communication with other units of the work station. Furthermore, an SCSI control 32b is connected to the Micro Channel 32 for controlling a fixed disk drive. The functional memory interface block (MIB)40 forms an interface between the host P/M bus 20 and a DRAM memory 42 which may have different sizes. Furthermore, the MIB 40 controls access to the usual BIOS ROM memory 42a. The functional peripheral interface block (PIB) 50 forms an interface between the host P/M bus 20 and various conventional system devices and peripheral units through respective control blocks. Thus, there is provided a VGA control 53a, a peripheral controller 52b, a flexible disk control 52c, a keyboard/mouse control 52d, and a RTC/CMOS RAM unit 52e. All these units are well known in the art, and therefore they will not be described in further detail. According to the preferred embodiment of the invention, each of the functional blocks BIB 30, MIB 40, and PIB 50 has been specifically designed as one chip each containing all elements such as registers and logic circuitry necessary to establish and perform communication between the host P/M bus 20 and the individual devices connected to each functional block 30, 40, and 50. As indicated in Fig. 1, it should be noted that a number m of BIBs 30 and a number n of MIBs 40 may be provided all connected to the host P/M bus 20. Thus, a large variety of configurations with different CPUs and significantly different memory capacities may be implemented. Each functional block 30, 40, 50 is provided with some intelligence providing an operation which is relatively independent of the CPU operation generally governing all functions of the system. Basically, each functional block 30, 40, 50 includes an interface unit between the host P/M bus and an individual interface transaction bus. Although the timing is based on the CPU clock, all operations within the functional block such as read or write operations will be independently performed in one cycle, while the CPU requires at least two cycles of the CPU clock. Accordingly, this type of system architecture offers a considerably improved performance in view of the reduction of wait states for the CPU resulting in a higher overall operating speed. An important feature of the invention is achieved by a specifically extended host P/M bus which is illustrated in Fig. 2. Specifically, within the block CPU 10 the conventional input/output ports of a microprocessor such as Intel 80386, etc. are listed as address ports A(2,...31), data ports D(0,...31), byte enable ports BEb(0,...3), and an address status output port ADSb which indicates that a valid bus cycle definition and address are available and which is driven active in the same clock as the addresses are given. ADSb is active low. The system clock PCLK is generated by a clock oscillator 60 and supplied to the input port PCLK of the CPU 10 and the input port PCLK of the functional blocks BIB 30, MIB 40, and PIB 50. These and all other input/output ports of the CPU 10 and the signals presented there are conventional. Thus, they will not be explained in further detail. As may be gathered from Fig. 2, the functional blocks BIB 30, MIB 40, and PIB 50 are provided with input/output ports similar to those of the CPU. However, there are several additional ports and associated bus lines connecting corresponding ports of the functional blocks BIB 30, MIB 40 and PIB 50 and the CPU 10 with each other. The ports CIN, COUT, CSETUPb and RESET, and corresponding signals, are of specific interest since they are used in the configuration procedure of the present invention. As may be gathered from Fig. 2, the signal CSETUPb originates from PIB 50 and is received by all other functional blocks BIB 30 and MIB 40 of which a plurality may be provided. The signal CSETUPb when active low acts as an enabling signal which puts all functional blocks in the SETUP mode. The signal RESET, which also originates from the PIB 50, is used to clear all internal configuration registers inside the functional blocks to a standard or default state before starting a configuration procedure. The signals CIN, COUT CSETUPb and RESET indicated in Fig. 2 are also shown in Fig. 3. Fig. 3 illustrates a feature of the present invention, i.e. the chaining of all functional blocks and their successive configuration. The first block, block 1, is the PIB 50, while each of the subsequent blocks such as block 2... block n... block last (respectively indicated 62, 64, 66) may be either a BIB 30 or a MIB 40. Prior to describing the configuring procedure in more detail, it appears necessary to give some explanation of the input/output (I/O) registers used in this procedure, which is done with reference to Fig. 4. Some registers are directly addressable and accessible from the local bus, e.g. registers 76, 74, and 72 as shown in Fig. 4. Furthermore, each functional block includes a larger number of 1-byte configuration registers, e.g. 256 with register addresses from 0 to FFhex (= 255). In Fig. 4 such a block of registers is marked with reference numeral 70. It should be understood that most of the registers are pre-occupied in that they have a standard assignment. Thus, the configuration information to be stored therein is narrowly limited. In order to overcome this limitation, the configuration procedure of the present invention uses just one of the registers in each block, e.g. the register 74 of PIB 50 for storing one of the subaddresses 0 to FFhex of the register block 70 of any of the functional blocks 30, 40, and 50. Register 72 of a block is used for latching configuration data to be stored in a subaddress indicated by the relevant pointer register 74. As indicated in Fig. 4, PIB 50 includes a further register 76. Whenever bit position 7 of the register 76 is set to "0" the system board is set into the SETUP mode. As regards the individual registers of the register block 70 of each of the functional blocks 30, 40 and 50, the subaddresses 0 to FFhex are divided into several address ranges receiving predetermined configuration data for each of the functional units of each block. As an example, address range Olhex to 3Fhex may be used for the host P/M interface respectively associated with the BIB 30, MIB 40, and PIB 50. An address range 40hex to 7Fhex may be used for configuration data relating to a DMA unit of the BIB 30, a cache controller of the MIB 40, and a synchronizing unit of the PIB 50, and so on. As will be appreciated, configuration data is used to provide a system with information related to the types and number of devices connected to the system and with other operational information. Generally, register OOhex is used for storing an ID number for the associated functional block. The SETUP procedure according to the invention will now be described. First, in an I/O write cycle, the digit 0 is written in bit 7 of the register 76 of the PIB 50, which initiates a SETUP mode for the system board. Normally, the CPU or other device controlling the configuration of the system will write to register 76 a data byte (a code) having a 0 in bit position 7. PIB 50 will then generate the CSETUPb signal on line 68 which is applied to all of the functional units to enable them for configuration. The controlling device will also provide a RESET signal on line 69 to reset all of the units prior to activating the first one for configuration. While the signal RESET on line 69 and the signal CSETUPb on line 68 are high, all functional blocks clear their COUT signals to logic 0. All blocks check their CIN signals when the signals RESET and CSETUPb go low. It should be noted that all blocks are connected in series chain for the configuration procedure, with an input line 77 (Fig. 3) receiving the output signal COUT from the preceding unit. Referring to Fig. 3, the CIN port of the first block PIB 50 is connected via a pull up resistor 82 to a + 5 V source so that an activating signal (logic 1) is continuously applied to the CIN port of block 1. With CIN = 1 of block 1, this block is activated for configuration when the block receives an active low signal CSETUPb over line 68. Configuration of a unit starts with an address being provided to pointer register 74. The first address in register 74 will normally be 00h which points to the register 00h containing the block ID number. After the ID number of the current block is read, an address and corresponding configuration data are provided to the pointer register 74 and latch register 72, respectively. The pointer register 74 uses the address to point to or select a configuration register (normally the one with the next subaddress, e.g. Olhex), and the corresponding configuration data in latch register 72 is then written in register address 01 of the register block 70. Address and corresponding configuration data are consecutively provided to pointer register 74 and latch register 72, respectively. With the pointer sequencing through all the addresses 00hex to FFhex of the register block 70, various configuration data is entered into the block 70. When the pointer arrives at address FFhex, signal COUT is generated (see Figure 3) causing signal CIN2 to go to logic 1 activating block 2 by setting it into the SETUP mode. A functional block is activated for set up only when its input signal CIN is active and output signal COUT is inactive. Thus, when block 62 is activated by CIN2 going active high, block PIB 50 is deactivated by COUT1 going active high. The above mentioned steps are repeated until all blocks 62 to 66 have been appropriately configured. Finally, bit position 7 of register 76 is set to "1", thereby releasing the system from the SETUP mode. It should be understood that the present invention is not limited to the use of the predetermined final address FFhex to activate COUT, and other predetermined values may be selected. It should be noted that all configuration data for a specific system configuration is usually stored on a flexible reference disk. In the foregoing description there has been explained a novel configuration procedure for the system board of a work station. Similarly, this procedure may be applied to a configuration procedure for adapters added to the system. Since all functional blocks are connected in a chain, any number of functional blocks may be used for the system and these functional blocks are configured appropriately in the manner explained above using only one pointer register and one latch register in each block or unit for addressing and configuring of the multiple configuration register block 70 of its respective functional block, such as BIB 30, MIB 40, or PIB 50.

Claims: A work station including a central processing unit (10) and a plurality of functional units (30, 40, 50), a local bus (20) connecting the central processing unit (10) and the functional units (30, 40, 50), the functional units (30, 40, 50) being also connected in a series chain by signal lines (77), each of the functional units generating an activating signal (COUT) on a respective signal line (77) to activate the next unit in the series, characterised in that each functional unit (30, 40,50) has: i) a plurality of configuration registers (70), the configuration registers (70) of different functional units (30, 40, 50) sharing common addresses (00h ..Ffh) which are divided into several address ranges (01hex-3Fhex; 40hex-7Fhex) receiving predetermined configuration data for each of the functional units (30, 40, 50); ii) a pointer register (74), for receiving, when its unit is activated, a sequence of addresses (00h...FFh) of configuration registers (70) of that unit and selecting the corresponding configuration register, and iii) a latch register (72), for receiving, when its unit is activated, a sequence of items of configuration data and writing each of such items of data to the configuration register selected by the address in the pointer register (74). A work station according to claim 1 characterised in that an input port of a first functional unit (50) of the series is connected to a voltage source via resistive means (82) to activate the said first functional unit (50) for configuration in response to receipt of an enabling signal, and said signal line (77) connects an output port of each functional unit in the series (other than the last) to an input port of the next functional unit of the series, each functional unit of the series (other than the last) being arranged to supply the activating signal (COUT) to the next functional unit in the series along said signal line (77) upon completion of its configuration. A work station according to claim 2 characterised in that each unit in the series (other than the last) is arranged to generate an activating signal (COUT) when its pointer register (74) receives a predetermined address (FFh) in respect of that unit. A work station according to any one of the preceding claims characterised in that a SETUP line (68) is connected to all the functional units (30, 40, 50) to supply an enabling signal (CSETUPb) to all said functional units (30, 40, 50) so that each functional unit is enabled to be activated for configuration. A work station according to claim 4 characterised in that the first functional unit has a further register (76) from which, whenever a predetermined bit is entered into a predetermined bit position therein, the enabling signal (CSETUPb) is generated on the SETUP line (68). A work station according to any one of the preceding claims characterised in that a RESET line (69) is connected to all of the functional units (30, 40, 50) for resetting all configuration registers (70) of the functional units. A method of configuring a work station which includes a central processing unit (10), a plurality of functional units (30, 40, 50) and a local bus (20) connecting the central processing unit (10) and the functional units (30, 40, 50) comprising the steps of supplying data for the functional units (30, 40, 50) from the central processing unit (10) to the local bus (20), and activating each functional unit in sequence to receive such data characterised in that each functional unit has a plurality of configuration registers (70), a pointer register (74) and a latch register (72)) and the configuration registers of different units share common addresses (00h..FFh) which are divided into several address ranges receiving predetermined configuration data for each of the functional units (30, 40, 50); and the method includes, for each functional unit when activated, the steps of writing multiple address data and configuration data from the local bus (20) to the pointer register (74) and the latch register (72) respectively, selecting configuration registers (70) in accordance with the address data present in the pointer register (74), and writing the configuration data present in a latch register (72) to the configuration registers (70) thereof as they are selected by the address data present in the pointer register. A method according to claim 7 characterised by the step of resetting all of the said units (30, 40, 50) prior to activating a first one of said units for configuration. A method according to claim 7 or claim 8 characterised by the step of applying an enabling signal (CSETUPb) to all of the said functional units and wherein a functional unit is activated only when it is receiving both an enabling signal and an activating signal. A method according to claim 9 characterised by the step of continuously supplying an activating signal to a first one of said functional units.

Inventors: GOEPPEL ANTON, GOEPPEL, ANTON
Applicants: NCR INT INC, NCR INTERNATIONAL, INC.
Application year: 1991
Main classification: G06F9
IPC codes: G06F9, G06F13, G06F15