D/A converter

Abstract: The D/A converter comprises a bias circuit (10) including a series circuit of the drain-source of a bias FET (Q A ) and a bias resistor (10b) connected between a power source terminal (Vcc) and a reference potential point. The bias circuit includes a negative feedback amplifier (10a) having a same phase input terminal (10c) to which a reference voltage is supplied and an inverted phase input terminal connected to a junction between the source of the bias FET (Q A ) and the bias resistor (10b). An output terminal of the negative feedback amplifier (10a) is connected to the gate of the bias FET (Q A ). A digital to analog converting section (11) includes a plurality of constant-current source FETs (Q₁...Q n ) having a current value substantially equal to the current value of the bias FET (Q A ) of the bias circuit (10). The digital to analog converting section further includes a plurality of current switches (S₁...S n ) for selectively supplying currents of the constant-current source FETs (Q₁...Q n ) to an output terminal (11c) in response to a digital input signal. By means of this circuit the amplitude value of the output signal can be controlled accurately. A load resistor (11b) is connected to the output terminal (11c) to produce an analog output voltage. The resistance value of the bias resistor (10b) is set to 2 n -1 times the resistance value of the load resistor (11b) so that the full scale voltage at the output terminal becomes substantially equal to the reference voltage, n being a number of bits of the digital input signal. Thus, the maximum amplitude value (full scale value) of an output signal can be set accurately.

Description: FIELD OF THE INVENTION This invention relates to a D/A (digital to analog) converter, and more particularly to a D/A converter with which a maximum amplitude value (full scale value) of an output signal can be set accurately and which is suitable for use with a digital apparatus. DESCRIPTION OF THE PRIOR ART A current adding type D/A converter is conventionally known and disclosed, for example, in Japanese Patent Laid-Open Application No. 61-20434. An exemplary one of conventional D/A converters of the type mentioned is shown in Fig. 1. Referring to Fig. 1, the D/A converter shown includes an input circuit 1 for receiving a digital signal of three high order bits N 11 to N 13 , a decoder 2 connected to outputs of the input circuit 1, a flip-flop set 3 including a plurality of flip-flops connected to outputs of the decoder 2, and a constant-current source set 4 including a plurality of constant-current sources connected to outputs of the flip-flops of the flip-flop set 3. The D/A converter further includes another input circuit 5 for receiving a digital signal of five low order bits M 11 to M 15 , another flip-flop set 6 including a plurality of flip-flops connected to outputs of the input circuit 5, and another constant-current source set 7 including a plurality of constant-current sources connected to outputs of the flip-flops of the flip-flop set 6. Switch circuits are provided for the constant-current source set 4 and the constant-current source set 7 and controlled in response to an input digital signal to produce an analog signal corresponding to opening and closing conditions of the switch circuits. As such constant-current source set 4 for high order bits, a constant-current source circuit is already known which employs such an FET (field effect transistor) for a constant-current source as shown in Fig. 2 in which also an exemplary one of conventional bias circuits is shown. Referring to Fig. 2, the constant-current source set includes a plurality of FETs Q N1 to Q N7 for a constant-current source, and a bias circuit 8. The bias circuit 8 includes a negative feedback amplifier 8a for receiving a reference voltage Vref at a same phase input terminal thereof, and a bias FET Q A and a buffer FET Q B . The buffer FET Q B and the constant-current source FETs Q N1 to Q N7 are set such that an equal current Io flows therethrough. The constant-current source circuit shown in Fig. 2, however, is disadvantageous in that, while the electric current Io flowing through the source of the buffer FET Q B is stabilized against a temperature variation and so forth by the negative feedback amplifier 8a, the electric current Io may not be equal among the bias FET Q A and the constant-current source FETs Q N1 to Q N7 because of a possible dispersion among elements of them. Further, such conventional bias circuit has another drawback that a maximum amplitude value (full scale value) of an output signal cannot be set accurately. In the EP-A-0 281 116 there is a digital to analog converter according to the pre-characterizing part of claim 1 disclosed. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a digital to analog converter with which a maximum amplitude value (full scale value) of an output signal of a bias circuit can be set accurately. In order to attain the objects, according to the present invention, there is provided a digital to analog converter which comprises a bias circuit including a series circuit of the drain-source of a bias FET and a bias resistor connected between a power source terminal and a reference potential point, the bias circuit further including a negative feedback amplifier having a same phase input terminal to which a reference voltage is supplied and an inverted phase input terminal connected to a junction between the source of the bias FET and the bias resistor, the negative feedback amplifier further having an output terminal connected to the gate of the bias FET, and a digital to analog converting section including a plurality of constant-current source FETs having a current value substantially equal to the current value of the bias FET of the bias circuit, the digital to analog converting section further including a plurality of current switches for selectively supplying currents of the constant-current source FETs to an output terminal in response to a digital input signal, said digital to analog converter further comprises a load resistor connected to the output terminal to produce an analog output voltage across the load resistor, and is characterized in that the resistance value of the bias resistor being set to 2 n -1 times the resistance value of the load resistor so as to make the full scale voltage at the output terminal substantially equal to the reference voltage, n being a number of bits of the digital input signal. Thus, the maximum amplitude value (full scale value) of an output signal can be set accurately. The above and other objects, features and advantages of the present invention will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings in which like parts or elements are denoted by like reference characters. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing an exemplary one of conventional D/A converters; Fig. 2 is a circuit diagram showing an exemplary one of conventional bias circuits; Fig. 3 is a circuit diagram showing basic construction of a D/A converter according to the present invention; Fig. 4 is a diagram illustrating a conversion characteristic of the D/A converter shown in Fig. 3; and Fig. 5 is a circuit diagram of a D/A converter showing a preferred embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENT Referring first to Fig. 3, there is shown basic construction of a D/A converter according to the present invention. The D/A converter shown includes a bias circuit 10 and a D/A converting section 11. The bias circuit 10 includes a series circuit of the drain-source of a bias FET Q A and a bias resistor 10b connected between a power source terminal Vcc and a reference potential point (for example, of the ground potential), and a negative feedback amplifier 10a having a same phase input terminal 10c to which a reference voltage Vref is supplied, an inverted phase input terminal connected to a junction between the source (S) of the bias FET Q A and the bias resistor 10b, and an output terminal connected to the gate (G) of the bias FET Q A . The D/A converting section 11 includes a plurality of FETs Q 1 to Q n for a constant-current source having the gates connected commonly to the gate G of the bias FET Q A . The sources of the constant-current source FETs Q 1 to Q n are connected to an output resistor 11b by way of a corresponding plurality of current switches S 1 to S n which are controlled in response to outputs of a decoder 11a, and an output terminal 11c is led out from a junction between the output resistor 11b and the current switches S 1 to S n . In the D/A converter of the construction described above, since the gates-sources of the bias FET Q A and the constant-current source FETs Q 1 to Q n are connected in parallel to each other, they have a similar current characteristic and the potentials at the gate and the source of the bias FET Q A are made equal to the reference voltage Vref due to a feeding back operation of the negative feedback amplifier 10a. Further, a possible dispersion among elements of the bias FET Q A and the constant-current source FETs Q 1 to Q n can be minimized where they are constructed in a single chip as an integrated circuit. Then, with the D/A converter, as seen from a characteristic curve p shown in a diagram of Fig. 4, the current switches S 1 to S n are controlled in response to a digital input signal (which consists of 3 bits in Fig. 4) to a decoder 11a so that an output voltage Vo corresponding to the digital input signal may be outputted from the output terminal 11c. Referring now to Fig. 5, there is shown in circuit diagram a D/A converter according to an embodiment of the present invention. The D/A converter shown has a generally similar construction to the D/A converter shown in Fig. 3 but is constituted such that a digital input signal of three bits D1, D2 and D3 is supplied to the decoder 11a and the resistance value of the bias resistor 10b is set to seven times the resistance value r of the output resistor 11b. When all of the bits D1, D2 and D3 of a digital input signal are equal to 1, the output voltage Vo from the output terminal 11c is given by Vo = 7Ir and accordingly is equal to the reference voltage Vref. Thus, since the full scale value of the output voltage Vo from the output terminal 11c is equal to the reference voltage Vref when all of the bits D1, D2 and D3 of a digital input signal are equal to 1, setting of an output amplitude can be performed accurately. In other words, where the number of bits of a digital input signal is represented by n, if the resistance value of the bias resistor 10b is set to 2 n -1 times the resistance value of the output resistor 11b, then the full scale value at the output terminal 11c can be made accurately equal to the reference voltage Vref. Further, the reference voltage Vref can be selected if a variable resistor is employed as the bias resistor 10b so as to make the resistance value variable. Thus, a suitable reference voltage which is supplied, for example, to another IC (integrated circuit) can be used commonly for the reference voltage Vref. In this instance, the full scale value of the output voltage Vo from the output terminal 11c is compressed to Vm as seen from a characteristic curve q shown in Fig. 4. As apparent from the foregoing description, with a digital to analog converter, as the gate of a bias FET is controlled in response to an output of a negative feedback amplifier, the amplitude value of an output terminal can be controlled accurately against a possible dispersion among elements of the bias FET and constant-current source FETs of a digital to analog converting section. Further, as a load resistor is connected to the output terminal to produce an analog output voltage across the load resistor and the resistance value of a bias resistor is set to 2 n -1 times the resistance value of the load resistor so as to make the full scale voltage at the output terminal substantially equal to a reference voltage, n being a number of bits of the digital input signal, the maximum amplitude value (full scale value) of an output signal can be set accurately. Having now fully described the invention, it will be apparent to one of ordinary skill in the art that many changes and modifications can be made thereto without departing from the spirit and scope of the invention as set forth herein.

Claims: A digital to analog converter, comprising a bias circuit (10) including a series circuit of the drain-source of a bias FET (Q A ) and a bias resistor (10b) connected between a power source terminal (V cc ) and a reference potential point, said bias circuit further including a negative feedback amplifier (10a) having a same phase input terminal (10c) to which a reference voltage is supplied and an inverted phase input terminal connected to a junction between the source of said bias FET and said bias resistor, said negative feedback amplifier further having an output terminal connected to the gate (G) of said bias FET, and a digital to analog converting section (11) including a plurality of constant-current source FETs (Q 1 ...Q n ) having a current value substantially equal to the current value of said bias FET of said bias circuit, said digital to analog converting section further including a plurality of current switches (S 1 ...S n ) for selectively supplying currents of said constant-current source FETs to an output terminal (11c) in response to a digital input signal, said digital to analog converter further comprising a load resistor (11b) connected to said output terminal to produce an analog output voltage across said load resistor, characterized in that the resistance value of said bias resistor (10b) being set to 2 n -1 times the resistance value of said load resistor so as to make the full scale voltage at said output terminal substantially equal to the reference voltage, n being a number of bits of the digital input signal. A digital to analog converter according to claim 1, wherein said bias FET, negative feedback amplifier, constant-current source FETs and current switches are constructed as a single chip integrated circuit. A digital to analog converter according to claim 1. wherein said bias resistor is a variable resistor. A digital to analog converter according to claim 3, wherein the resistance value of said bias resistor is decreased to compress an analog output voltage produced across an output resistor connected to said output terminal.

Inventors: FUKUSHIMA NORIYUKI, KUMAZAWA NAOKI, FUKUSHIMA, NORIYUKI, KUMAZAWA, NAOKI
Applicants: SONY CORP, SONY CORPORATION
Application year: 1991
Main classification: H03M1
IPC codes: H03M1