High speed driving circuit for MOSFET transistors

Abstract: The high speed driving circuit for MOSFET transistors comprises a first coupling transformer (T1), which is driven on the side of the driving logic (IC1) and has a turns ratio of 2:1, with minimum reactance and very high immunity to dV/dt. The circuit comprises a first stage of the driver, constituted by a small MOSFET transistor (Q1), and a second stage of the driver, which is directly coupled to the drain pin of the first stage (Q1). The circuit furthermore comprises a third stage of the driver, which is supplied with two distinct voltages; these power supplies are provided by a second transformer (T2).

Description: The present invention relates to a high speed driving circuit for MOSFET transistors. The invention relates to the entire range of electronic circuits commonly termed "switching power supplies", with particular reference to the conceptual layouts which use electronic switches the drivers whereof are not connected to the same voltage. In this field, the most common and known types included in these layouts are those usually called "half-bridge", "asymmetrical half-bridge" and "full-bridge". These indicated configurations are, among known ones, those which allow to reach the highest power values. However, these known circuits have some disadvantages, which are essentially due to difficulty in correctly driving the electronic switches, which are actually provided by means of active electronic components (bipolar transistors, SCRs, MOSFET transistors). Thus, if MOSFET transistors are used in the half-bridge and full-bridge circuit, by using N-channel transistors with respect to P-channel ones, the former being markedly privileged in semiconductor technology, the problem of adequately driving these MOSFET transistors and in particular the one connected to V cc (or power supply) is rather complex. For this purpose, some solutions are already known; one is known as "level shifter" and uses a low-power transistor which is connected to the negative voltage and can withstand the entire power supply; this transistor drives, more or less directly, the MOS power transistor; however, disadvantages are still observed, since optimization is not easy and the choice of the component is rather troublesome if V cc (the direct power supply) is high (300 or 500 Volts, as often occurs when rectifying 220 Volts AC or three-phase 380 Volts). Another known solution which has already been adopted is that of so-called high speed photocouplers; although it has some advantages, this solution requires a floating power supply connected to the source pin of the final power stage. Propagation delays for more easily available devices (commercially indicated by the code 6N 137 of Company HP) are not negligible at high frequencies such as those which can be reached by MOSFET transistors. Common-mode noise rejection (1000/2000 V/µsec) can also be insufficient with these devices and with high voltages. Another solution which has already been adopted is to use the new integrated circuits by I.R.; this solution, which is very recent, is satisfactory from some points of view but also has disadvantages, since the devices used do not operate at high voltages and the current available for driving is rather limited. Another solution which has already been adopted consists in using coupling transformers: this, too, is a solution which is satisfactory from some points of view, but even in this case some disadvantages can be observed: if special precautions are not taken, the inductance dispersed between the two multiturn coils, even if they are well-coupled, limits the rise rate of the drive, especially if the MOSFET transistor has considerable intrinsic capacitances, as in the case of high-current and high-voltage voltage MOSFET transistors. This dispersed inductance, which thus occurs "in series", can furthermore resonate with input capacitances ("in parallel"), causing spurious over-oscillations which are dangerous for the MOSFET transistor (20 V between gate pin and source pin are already critical), and this requires clipping and damping circuits which invalidate the advantage of simplicity and reduce driving quality. With this solution it is furthermore virtually impossible to transmit drive signals with a highly variable duty cycle as in the case of PWM signals. With some provisions, it is instead possible to pass through the transformers signals with a duty cycle comprised between 0 and 50%, as in the case of many circuits of switching power supplies. As a partial solution to these disadvantages, the inventor of the present application has filed, on April 13, 1989, Italian Patent Application no. 41571 A/89, related to a driving circuit for power MOSFET transistors which has a low cost and is extremely fast and which, despite solving most of the above disadvantages, was not optimum if a power of 2 KW at the frequency of 2.5 MHz was to be handled. At such values, the frequency involved is five times higher than that used in the circuit according to application no. 41571 A/89, and this leads to a drastic increase in the power required to drive the power switches, since they must be switched on and off as fast as possible in a total time of approximately 400 nanoseconds, which is the period which corresponds to 2.5 MHz. A high speed driving circuit for MOSFET transistors including the features of the preamble of claim 1 is known from EP-A-177 148. The aim of the present invention is therefore to eliminate the disadvantages described above in known types by providing a high speed driving circuit for MOSFET transistors which allows to provide a full-bridge device which operates at 2.5 MHz and is capable of handling a power of up to approximately 2.4 KW. Within the scope of the above aim, an important object is to provide a circuit which is structurally simple and can be manufactured with known facilities and machinery. Not least object is to provide a circuit which is reliable and safe in use. This aim, these objects and others which will become apparent hereinafter are achieved by a high speed driving circuit for MOSFET transistors, as defined in claim 1. Further characteristics and advantages of the invention will become apparent from the detailed description of a particular but not exclusive embodiment, illustrated only by way of non-limitative example in the accompanying drawings, wherein: figure 1 is a circuit layout of the high speed driving circuit for MOSFET transistors according to the invention. With reference to the above figure, the reference sign T1 indicates a first coupling transformer, which is driven on the drive logic side IC1, has a turns ratio equal to 2:1 and is wound with such a method as to have minimal dispersed reactance, although it has a very high immunity to dV/dt, which in this application reaches 10 KV/µsec. The circuit furthermore comprises a first stage of the actual driver, indicated by Q1, which is constituted by a small MOSFET transistor with an IDmax of a few hundred mA. The first stage Q1 is the most suitable for using the signal which is present on the secondary coil of the first transformer T1 without at the same time excessively loading the logic IC1 and the primary coil. The first stage Q1 is furthermore suitable for driving the subsequent second stage, indicated by Q2 and Q3, with rather steep fronts. The second stage Q2 and Q3, which is directly coupled to the drain pin of the first stage Q1, is constituted by a pair of medium-power bipolar transistors, for example of the type commercially known by the code BD 137 - BD 138; the pair of medium-power bipolar transistors Q2 and Q3 must be suitable for providing a current with an amplitude sufficient to directly drive two MOSFET transistors of a third stage of the driver which are indicated by Q4 and Q5. The third stage of the driver is constituted by two medium-power complementary MOSFET transistors Q4 and Q5, with auxiliary circuitry, indicated in the drawing, which is included essentially in order to reduce the dissipation of the two MOSFET transistors Q4 and Q5, limiting simultaneous conduction and in any case decreasing the "transverse" current, and to drive the final MOSFET transistor according to two distinct paths, thus allowing to easily and independently vary the on and off switching speeds. In resonant converters, for example, it is in fact convenient to switch the final MOSFET transistors off very rapidly, whereas switching on can be much slower. The driving circuit furthermore has a driver power supply with two voltages, at +12 V and at -3 V with respect to the source pin of the final stage; this has been found to be the best compromise between the need to powerfully drive the final stages, making them immune with respect to oscillations on the gate pin circuit, and containing the dissipation on the two MOSFET transistors Q4 and Q5 of the third stage. The power supplies are provided by means of a second ferrite transformer, indicated by the T2, which operates at 100 KHz; the transformer T2 is built so as to have good insulation and a rather low capacitance between the primary and secondary multiturn coils without penalizing it excessively with a high dispersed reactance. It has thus been observed that the invention has achieved the intended aim and objects, a high speed driving circuit for MOSFET transistors having been obtained which, by virtue of the use of four drivers, driven by an adequate control logic IC1, and with four final MOSFET transistors with adequate characteristics, has allowed to provide a full-bridge circuit which operates at 2.5 MHz and can handle power up to approximately 2.4 KW. The invention is naturally susceptible to numerous modifications and variations, all of which are within the scope of the claims. Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included for the sole purpose of increasing the intelligibility of the claims and accordingly such reference signs do not have any limiting effect on the scope of each element identified by way of example by such reference signs.

Claims: High speed driving circuit for MOSFET transistors comprising: a first coupling transformer (T1) which is driven at its primary coil and has a turns ratio of 2:1, said turns being wound such that said first coupling transformer has a minimal reactance and very high immunity to dV/dt; and a first stage (Q1); characterized in that said driving circuit further comprises a second stage (Q2,Q3) and a third stage (Q4,Q5), said first stage (Q1) being constituted by a small MOSFET transistor, said first stage (Q1) being adapted for using a signal which is present on the second coil of said first coupling transformer (T1) for driving a second stage (Q2,Q3) without at the same time excessively loading the primary coil of said first coupling transformer (T1); said second stage (Q2,Q3) being directly coupled to the drain terminal of said first stage (Q1), such as to be driven by said first stage (Q1), said second stage (Q2,Q3) being adapted to provide for a current with an amplitude sufficient to directly drive said third stage (Q4,Q5); said third stage (Q4,Q5) for driving a final MOSFET transistor, said third stage (Q4,Q5) being supplied with two distinct voltages, said two distinct voltages being provided by a second transformer (T2). Circuit according to claim 1, characterized in that said first coupling transformer (T1) is driven at its primary coil by means of two HC-MOS quadruple buffers (IC1) in full-bridge connection. Circuit according to claims 1 and 2, characterized in that said dV/dt reaches values which are approximately equal to 10 KV/µsec. Circuit according to one or more of claims 1-3, characterized in that said small MOSFET transistor of said first stage (Q1) has an IDmax value of a few hundred mA, said small MOSFET transistor using the signal which is present on the secondary coil of said first coupling transformer (T1). Circuit according to claims one or more of claims 1-4, characterized in that said second stage (Q2,Q3) is constituted by a pair of medium-power bipolar transistors (Q2,Q3). Circuit according to one or more of claims 1-5, characterized in that said third stage is comprised of two complementary medium-power MOSFET transistors (Q4,Q5) which are connected to an auxiliary circuitry (R1,R2,R3,R4, R5,D21,D22,C1,C2,C3,C4) which is adapted to reduce dissipation, to reduce a transverse current between said complementary medium-power MOSFET transistors (Q4,Q5) and to drive a final MOSFET transistor according to two distinct paths in order to independently and easily vary the switching speed during switching on and switching off. Circuit according to one or more of claims 1-6, characterized in that said drive circuit can be supplied with voltages at +12 V and -3 V with respect to the source pin of said final MOSFET transistor. Circuit according to one or more of claims 1-7, characterized in that said second transformer (T2) is made of ferrite, preferably operates at 100 KHz, has good insulation, a reduced capacitance between the primary and secondary coils, and a modest dispersed reactance. Circuit according to one or more of the preceding claims, characterized in that said auxiliary circuitry is comprised of a plurality of resistors (R1,R2,R3,R4, R5), capacitors (C1,C2,C3,C4) and diodes (D21,D22).

Inventors: CORTICELLI GIULIANO, CORTICELLI, GIULIANO
Applicants: SEIT ELETTRONICA SRL, SEIT ELETTRONICA S.R.L.
Application year: 1991
Main classification: H02M1
IPC codes: H02M1, H03K17