BICMOS input circuit for detecting signals out of ECL range

Abstract: A BiCMOS input circuit which is capable of detecting signals below a particular range, such as ECL signals, is presented. The circuit is useful in conserving the number of pins in a BiCMOS integrated circuit in that a signal below normal ECL levels can trigger special functions, such as testing. The circuit has a plurality of CMOS inverter circuits connected in series with the input node (41) of the first inverter connnected to the input terminal of the circuit and the output node of the last inverter circuit (44) connected to the output terminal (45) of the circuit. Diode-connected bipolar transistors created a potential difference between V cc and the source electrode of PMOS transistor of each CMOS inverter circuit in a declining fashion from the first inverter to the last inverter. The last inverter circuit has no potential difference at all so that its output has a full CMOS swing.

Description: The present invention is related to input circuits in integrated circuits and, more particularly, to tristate input circuits useful in BiCMOS integrated circuits. A common problem with integrated circuits is the limited number of pins which are available to make the electrical connections between an integrated circuit and the outside world. As integrated circuits become more complex and more capable of performing advanced functions, physical constraints keep the number of available pins low. The low pin number can often create a communications bottleneck. The present invention provides for a technique by which an input pin responds to three states of voltage signals, in contrast to two-state pins in most integrated circuit. This "tristate" technique is particularly adapted to BiCMOS integrated circuits. BiCMOS integrated circuits are semiconductor devices in which bi polar technology is combined with c omplementary m etal o xide s emiconductor (CMOS) technology. In such an BiCMOS integrated circuit, the higher speed, greater power-consuming bipolar transistor circuits are located at the suitable locations in the semiconductor device to use the speed and drive capabilities inherent in bipolar transistors. The CMOS circuits are used wherever higher packing densities and lower power consumption of CMOS circuits are suitable. Some BiCMOS integrated circuits communicate with the outside world with signal levels appropriate for bipolar logic circuits. CMOS level signals are used within the device. A common bipolar logic used in BiCMOS devices is e mitter- c oupled l ogic (ECL) which has a signal range from -0.9 to -1.7 volts. On the other hand, CMOS signals swing in a 5-volt range. The present invention provides for an input circuit which is responsive to signals having voltage levels below the ECL range. This allows the same pin to transmit ECL signals for normal communication to the rest of the integrated circuit and a special signal at a voltage level below the ECL range for special functions in the BiCMOS device, such as testing and the like. The documents GB-A 2 130 833, JP-A 58 034 956, JP-A 59 003 787, "Electronic Components and Applications", 7 (1986), No. 3, pages 151-162, US-A 4 469 959, JP-A 62 194 732, and EP-A 0 405 441 each disclose a circuit having the features set forth in the preamble of claim 1. JP-A 60 136 418 and JP-A 62 125 713 show similar circuits but in all-MOS technique. The present invention provides for a BiCMOS circuit having a plurality of CMOS inverter circuits. The input terminal of the first inverter circuit is connected to the input pad which is connected to an input pin. The source electrode of the PMOS transistor forming the inverter circuit is coupled to a first voltage reference through a first potential difference circuit. The second CMOS inverter circuit is connected in series with the first inverter circuit with the output terminal of the first inverter connected to the input terminal of the second. Likewise, the source electrode of the PMOS transistor forming the second inverter circuit is coupled to a voltage reference through a second potential difference circuit. The amount of potential difference by this circuit is less than of the first potential difference circuit. The sequence of series-connected CMOS inverter circuits with corresponding voltage generating circuits continues with the amount of potential difference until the last CMOS inverter circuit has the source electrode of its PMOS transistor of the inverter circuit connected directly to the first voltage reference under ECL input conditions. The last CMOS inverter circuit is capable of a full CMOS voltage swing for CMOS operation. In implementation it has been found that three CMOS inverter circuits are sufficient. Diode-connected bipolar transistors form the potential difference circuits between the PMOS transistors and the first voltage reference. A current source connected to the diode-connected bipolar transistors maintains the bipolar transistors in their on state. Fig. 1 is a circuit diagram illustrative of the present invention. Fig. 1 is a circuit diagram illustrating the present invention. An input pad 41 receives signals from a connected input pin (not shown) for transmission to the integrated circuit of which the Fig. 1 circuit is a part. Conventionally most BiCMOS integrated circuits operate between two voltage supplies, references V CC at 0 volts and V EE at -5.2 volts. The input circuit of Fig. 1 operates between the pad 41 and the output terminal 45. The input circuit has three CMOS inverter circuits formed by a complementary transistor pair 21 and 22, 23 and 24, 25 and 26. The input terminal of first inverter, the commonly connected gate electrodes of the transistors 21, 22, is connected to the input pad 41. The output terminal of that inverter, the common node of the complementary transistor pair 21, 22, is connected to the input node of the next CMOS inverter circuit formed by the complementary transistor pair 23, 24. The output node of the transistor pair 23, 24 is, in turn, connected to the input node of the last inverter circuit formed by the complementary transistor pair 25, 26. The common node of the transistor pair 25, 26, the output node of the inverter, is connected to an output terminal 45. With respect to the first inverter circuit formed by the transistors 21, 22, the source electrode of the PMOS transistor 21 is coupled to the first voltage reference V cc by two diode-connected bipolar transistors 11, 12. Each of the NPN bipolar transistors 11, 12 have their base and collector electrodes tied together. The bipolar transistors 11, 12 form a first potential difference circuit, which drops the voltage 2V BE from 0 volts to about -1.7 volts. The source electrode of the NMOS transistor 22, on the other hand, is connected to the second voltage reference at V EE , -5.2 volts. Additionally, the N-doped substrate in which the PMOS transistor 21 is located, is biased at the source electrode voltage, -1.7 volts. Thus, for input signals in the ECL range, -0.8 to -1.1 volts, the NMOS transitor 22 remains on and the output signal of the inverter remains low. The inverter can switch high only when the input signal voltage falls below (-1.7 - V T ), where V T is the threshold voltage of the PMOS transistor 21. The output voltage of the CMOS inverter of complementary transistor pair 21, 22 can then swing from -5 volts to -1.7 volts. The CMOS inverter of the complementary transistor pair 23, 24 are also similarly connected. The source electrode of the PMOS transistor 23 is coupled to the first voltage reference V CC through a potential difference circuit, a single NPN diode-connected bipolar transistor 13. The transistor 13 has its base and collector electrodes connected to the first voltage reference and its emitter electrode connected to the source electrode of the transistor 23. The source electrode of the transistor 24 is connected to the second voltage reference at V EE . Similar to the transistor 21, the N-substrate of the PMOS transistor 23 is also biased at its source electrode voltage, one V BE below V CC . Thus output signal of the CMOS inverter circuit of the transistors 23, 24 operates in a range between -0.8 volts, one V BE below V CC , to -5.2 volts, while the input signal range is from - 0.8 - V T volts, where VT is the threshold voltage of the PMOS transistor 23. In most CMOS processes V T is typically in the range of 0.75 to 1.1 volts. The third CMOS inverter circuit formed by the complementary transistor pair 25, 26 is connected to the first voltage reference without any potential difference circuit. The source electrode of the PMOS transistor 25 is at 0 volts, V CC , and the source electrode of the NMOS transistor 26 is at -5.2 volts, V EE . Thus the output signal from the output node of the inverter, the common drain node of the PMOS transistor 25 and the drain node of the NMOS transistor 26, swings in a full CMOS voltage range. The output terminal 45 can provide signal levels to other CMOS circuits in the rest of the integrated circuit. The Fig. 1 circuit also has additional circuits to keep the two diode-connected bipolar transistors 11, 12 and single diode-connected bipolar transistor 13 turned on all the time. A current source (actually a current sink) formed by an NMOS transistor 31 provides this function to the transistors 11, 12. The transistor 31 has its gate and drain electrodes connected to the emitter electrode of the bipolar transistor 12. The transistor 31 is thus in a diode configuration and draws current from the bipolar transistors 11, 12 to the second reference voltage V EE . The drawn current is just large enough to keep the bipolar transistors turned on. Similarly, to keep the bipolar transistor 13 on, a second current source formed by an NMOS transistor 32, draws current through the bipolar transistor 13. The drain electrode of the transistor 32 is connected to the emitter electrode of the bipolar transistor 13 and the source electrode of the transistor 32 is connected to the second voltage reference V EE . The gate electrode of the transistor 32 is coupled to the emitter electrode of the bipolar transistor 12. This connection ensures that the current drawn through the bipolar transistor 13 by the transistor 32 does not become excessively large, but sufficiently large to keep the NPN transistor 13 turned on. Also connected to the input pad 41 is an input terminal 47 which may be connected to the standard ECL circuits which form the input buffer circuits to a BiCMOS integrated circuit. Thus, signals in the ECL range are propagated into the integrated circuit through the line 46 and terminal 47 for standard operation. When a special operation is required, an input signal lower than the ECL, or more specifically, lower than -1.7 - V T volts, is impressed upon the input pad 41. This results in a CMOS high level signal at the terminal 45 which could be connected to CMOS circuits to perform a special operation, such as a test operation of the integrated circuit. In this manner an additional input pin is not required for testing; the number of input pins is conserved. While the above is a complete description of the preferred embodiments of the invention, various alternatives, modifications and equivalents may be used. For example, the present invention has been described with particular voltage displacment circuits and three CMOS inverter circuits. It should be evident that by modifying the voltage displacement circuits and possibly varying the number of inverter circuits, the present invention could detect signals below predetermined voltage ranges, levels different from ECL. Thus the present invention could be adapted to different requirements. Therefore, the above description should not be taken as limiting the scope of the invention which is defined by the appended claims.

Claims: A BiCMOS circuit having an input terminal (41) and an output terminal (45), said circuit capable of detecting signals on said input terminal below a predetermined range of voltages, said BiCMOS circuit comprising a plurality of CMOS inverter circuits (21+22, 23+24, 25+26), each inverter circuit having a first power supply node coupled to a first voltage reference, a second power supply node coupled to a second voltage reference, an input node and an output node, said inverter circuits coupled serially to each other from first to last, an output node of one inverter circuit connected to the input node of the following inverter circuit, an input node of said first inverter circuit connected to said input terminal, an output node of said last inverter circuit connected to said output terminal; and potential difference means (11, 12, 13) connected between at least said first power supply node of said first inverter circuit and said first voltage reference (V cc ); whereby said BiCMOS circuit transmits a signal on said input terminal to said output terminal only if said signal is below a predetermined range of signal values, wherein said potential difference means comprises at least one diode-connected bipolar transistor (11, 12, 13) connected in series between said first inverter circuit and said first voltage reference, characterized by a current source (31, 32) connected to said bipolar transistor for maintaining said bipolar transistor in its on state. The BiCMOS circuit as in claim 1 wherein said plurality of CMOS inverter circuits include one (23, 24) or more inverter circuits between said first (21, 22) and last (25, 26) inverter circuits, wherein the amount of potential difference decreases from said first inverter circuit to said last inverter circuit, said last inverter circuit having no potential difference between said first power supply terminal of said last inverter circuit and said first voltage reference. The BiCMOS circuit as in claim 1 wherein said predetermined range comprises ECL voltage levels. The BiCMOS circuit as in claim 1 wherein said current source comprises a diode-connected MOS transistor (31, 32). The BiCMOS circuit as in claim 1 wherein each of said CMOS inverter circuits comprises a PMOS transistor (21, 23, 25) and an NMOS transistor (22, 24, 26), each transistor having a source electrode, drain electrode and gate electrode, said drain electrodes of both transistors in common forming said inverter output node (42, 43, 44), said gate electrodes of both transistors in common forming said input node, said source electrode of said NMOS transistor forming said second voltage supply node (V EE ), said source electrode of said PMOS transistor forming said first voltage supply, said substrate of said PMOS transistor held at the same voltage as said PMOS transistor source electrode, whereby said PMOS transistor turns on when the voltage at said input node is lower than the sum of said source electrode voltage and PMOS transistor threshold voltage (V T ). The BiCMOS circuit as in claim 5 wherein said potential difference means is such that said PMOS transistor of said first inverter circuit turns on when said input signal is below ECL levels. The BiCMOS circuit as in claim 1 further comprising a signal path (46, 47) connecting said input terminal (41) to a circuit responsive to ECL level signals. The BiCMOS circuit as in claim 1 wherein said potential difference means comprises a first potential difference means comprising two diode-connected bipolar transistors (11, 12) in series and a second potential difference means comprising one diode-connected bipolar transistor (13). The BiCMOS circuit as in claim 8 further comprising first (31) and second (32) current sources connected to said first and second potential difference means for maintaining said diode-connected bipolar transistors in an on state. The BiCMOS circuit as in claim 9 wherein said first and second current sources comprise MOS transistors (31, 32).

Inventors: DEMARIS JAMES E, DEMARIS, JAMES E.
Applicants: NAT SEMICONDUCTOR CORP, NATIONAL SEMICONDUCTOR CORPORATION
Application year: 1991
Main classification: H03K5
IPC codes: G01R31, H03K19