Method of manufacturing a semiconductor device involving a step of planarizing a metal layer

Abstract: A planarization method includes the steps of forming a second layer (4) on a first layer (1) which has an alignment mark (3A) having a heat sink structure, where the second layer is made of a metal, and irradiating a pulse energy beam on the entire exposed surface of the second layer (4) to planarize the second layer. The heat generated in the second layer (4) on the alignment mark (3A) is released via the first layer (1) so that substantially no melting of the second layer occurs on the alignment mark.

Description: BACKGROUND OF THE INVENTION The present invention generally relates to planarization methods, and more particularly to a method of planarizing a metal layer by a pulse energy beam such as a pulse laser beam. The method of the present invention is especially suited for planarizing a metal interconnection layer. When forming a metal interconnection layer during a process of producing an integrated circuit, a conductor layer 4 shown in FIG.1 is formed on an insulator layer 2 which is provided on a semiconductor layer 1 by a vapor deposition, sputtering or the like. However, as a via hole 5 such as a contact hole and a through hole in the insulator layer 2 becomes smaller, the conductor layer 4 does not sufficiently fill the via hole 5 and the step coverage becomes poor. This poor step coverage is caused by the fact that it becomes difficult for the conductor layer 4 to adhere on the sidewall of the via hole 5 due to the shadowing effect. FIG.2 is a cross sectional view for explaining a proposed method of eliminating the poor step coverage described above. According to this proposed method, a laser beam is irradiated on the conductor layer 4 to melt and planarize the conductor layer 4. On the other hand, FIGS.3 and 4 are cross sectional views for explaining a proposed method of forming a plug to eliminate the problem of poor step coverage. According to this proposed method, the conductor layer 4 is formed in a vicinity of the via hole 5 as shown in FIG.3, and a laser beam is irradiated on the conductor layer 4 to form a plug 6 within the via hole 5 by the melted conductor as shown in FIG.4. However, an alignment mark 3 is usually formed on the conductor layer 4 as shown in FIG.5. This alignment mark 3 is used for aligning a mask relative to the conductor layer 4. When the laser beam irradiates the conductor layer 4, the laser beam irradiates the entire surface of the conductor layer 4 because the laser beam irradiation is made with respect to the conductor layer 4 on a wafer, for example, so as to improve the throughput of the device. For this reason, the alignment mark 3 is also planarized by the laser beam irradiation as shown in FIG.6, and there is a problem in that the alignment mark 3 disappears when the planarization using the laser beam is carried out. On the other hand, if the laser beam irradiation is made to avoid the alignment mark 3, it is necessary to irradiate the laser beam on the conductor layer 4 on the wafer in parts, and the throughput of the device becomes poor because of the need to make several laser beam irradiations with respect to the conductor layer 4 on the wafer. The European Patent Application EP-A-0 097 848 discloses a process where a metal layer is sputter deposited over a substrate comprising via holes. The metal is patterned to leave metal only in and in the vicinity of the via holes. The structure is planarized locally in a subsequent heating step. Finally, a futher metal layer is deposited which is patterned to form interconnection lines. SUMMARY OF THE INVENTION Accordingly, it is a general object of the present invention to provide a novel and useful planarization method according to the claims and in which the problem described above is eliminated. Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIGS.1 and 2 are cross sectional views for explaining a proposed method of planarizing a conductor layer; FIGS.3 and 4 are cross sectional views for explaining a proposed method of forming a conductor plug; FIGS.5 and 6 are cross sectional views for explaining unwanted planarization of a alignment mark; FIG. 7 is a cross sectional view for explaining an embodiment of the planarization method according to the present invention; and FIGS. 8 and 9 are cross sectional views for explaining a method of planarization which does not form part of the present invention. A description will be given of an embodiment of the planarization method according to the present invention, by referring to FIG.7. In this embodiment, the insulator layer 2 formed on the semiconductor substrate 1 is made of PSG and has a thickness of 0.6 µm. The insulator layer 2 is patterned to form an alignment mark 3C and a via hole (not shown). The conductor layer 4 is formed on the entire surface of the insulator layer 2 and the exposed surface of the semiconductor substrate 1. For example, the conductor layer 4 is made of Al. Thereafter, the conductor layer 4 is patterned to remove the conductor layer 4 on the alignment mark 3C. Then, a laser laser is irradiated on the conductor layer 4 to melt the Al. The melted Al completely fills the via hole and is planarized. On the other hand, the Al conductor layer 4 does not exist on the alignment mark 3-C, and as a result, the alignment mark 3C will not be planarized by the laser beam irradiation. The planarized conductor layer 4 is then patterned using the alignment mark 3C so as to form an interconnection layer. Next, a description will be given of a planarization method which does not form part of the present invention, by referring to FIGS. 8 and 9. In this example, the insulator layer 2 formed on the semiconductor substrate 1 is made of PSG and has a thickness of 0.6 µm. The insulator layer 2 is patterned to form an alignment mark 3D and a via hole 5. The conductor layer 4 is formed on the entire surface of the insulator layer 2 and the exposed surface of the semiconductor substrate 1. For example, the conductor layer 4 is made of Al. Thereafter, the conductor layer 4 is patterned so that the conductor layer 4 remains only in a vicinity of the via hole 5 as shown in FIG.8. Thereafter, a laser beam is irradiated on the conductor layer 4 to melt the Al. The melted Al (conductor layer 4) in the vicinity of the via hole 5 flows into the via hole 5 and solidifies into a plug 6 as shown in FIG.9. Since the conductor layer 4 does not exist on the alignment mark 3D, the alignment mark 3D will not be planarized. Then, an Al layer (not shown) which connects to the plug 6 is formed and patterned to form an interconnection layer, for example. According to the preferred embodiment, no special process is required to prevent the planarization of the alignment mark 3C and the conductor layer 4 simply needs to be patterned to remove the conductor layer 4 in the vicinity of the alignment mark 3C. Since the patterning of the conductor layer 4 is originally required to leave the conductor layer 4 at least in the vicinity of the via hole 5, the process of removing the conductor layer 4 in the vicinity of the alignment marks 3C may be carried out simultaneously as the patterning to avoid the unnecessary increase of production processes. In the described embodiment, the conductor layer is made of Al. However, the conductor layer is not limited to Al, and any metal may be used. For example, titanium (Ti), copper (Cu), tungsten (W) and molybdenum (Mo) may be used for the conductor layer. In addition, the melting of the conductor may of course be made by an energy beam other than the laser beam. However, it is desirable that the energy beam is a pulse energy beam. Moreover, the semiconductor layer or substrate used in the described embodiment may be used as an active layer in which various semiconductor devices are formed. The illustration of such semiconductor devices will be omitted in this specification so as to simplify the drawings.

Claims: A method of manufacturing a semiconductor device involving a step of planarizing a metal layer, said method comprising in sequence the steps of: providing a semiconductor substrate (1); forming a layer (2) of insulating material on said substrate (1); patterning said layer (2) of insulating material to selectively expose portions of said substrate so as to define an alignment mark (3C) and at least one via hole; forming a metal layer (4) on the entire surface of the insulating layer (2) and on the exposed regions of the semiconductor substrate (1); removing the metal layer (4) from and in the vicinity of the alignment mark; irradiating an energy beam on the metal layer (4) to planarize said metal layer and to fill said at least one via hole; and patterning said planarized metal layer (4) so as to form an interconnection layer. The method according to claim 1 wherein said irradiating step is performed using a pulsed laser beam. A method according to claim 1, characterized in that said metal layer (4) is made of a metal selected from a group consisting of aluminum (Al), titanium (Ti), copper (Cu), tungsten (W) and molybdenum (Mo). A method according to any of claims 1, 2, 3 characterized in that said alignment mark (3C) includes grooves which are formed in the layer of insulating material (2) and extend to the semiconductor substrate (1).

Inventors: MUKAI RYOICHI, MUKAI, RYOICHI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1991
Main classification: H01L21
IPC codes: H01L21, H01L23