Circuit for driving a floating circuit in response to a digital signal

Abstract: A driving circuit for driving a floating circuit (28) responsive to a digital signal (IN) includes two DMOS transistors (10, 12) which are driven in opposite phase on their respective gates starting from the digital signal. The two DMOS transistors are biased by a current source which is formed by a current mirror (16, 18), which mirrors a reference current (I BIAS ), and by an auxiliary circuit (34-44) for injecting an additional current pulse during switching. Two MOS transistors (20, 22) serve as the respective load for the two DMOS transistors. The MOS transistors can be P-channel transistors, in which event the gate of each MOS transistor (20, 22) can be connected to the drain of the other MOS transistor. Two Zener diodes (24, 26) can be employed to limit the voltage between the gate and the source of the respective MOS transistor. The driving output of the floating circuit (28) can be the drain of one of the DMOS transistors.

Description: The present invention relates to a driving circuit for driving a floating circuit in response to a digital signal. In a particular aspect, the invention relates to such a driving circuit which is suitable for implementation in integrated circuit form with BCD technology. The devices used to drive a floating circuit with a digital or logic signal, also known as level shifters, must not lose the logic signal in the variations caused by the charging and discharging of the parasitic input capacitor of the floating circuit while the voltage thereof shifts with respect to the ground. In order that the input node of the floating circuit may assuredly follow the variations of the driving signal which drives the level shifter, the parasitic capacitor must in fact charge and discharge with the same speed as the driving logic signal, and for this purpose the input node of the floating circuit must be connected to a low-impedance point. A simple way of solving the problem consists in causing a current to flow in a resistor which has one terminal at the high floating voltage and the opposite terminal connected to the input of the floating circuit. However, the resistor must have a small value, for example 1 kohm, and the voltage drop required across the resistor in order to produce a logic signal on the floating circuit requires a high current and thus a considerable power absorption. In order to avoid these undesirable continuous consumptions, a solution consists in providing a flip-flop at the input of the floating circuit, with a double pulse drive in two high-value resistors for switching the flip-flop. In this case, current consumption in steady-state conditions is low, but in order to maintain a low impedance even during switching it is necessary to provide current sources for rapidly charging the parasitic capacitor. This entails a certain circuital complexity, besides the fact that in any case the presence of the flip-flop entails the risk of errors on the phases of the logic signal in case of outside noise during rise and fall. US-4,521,703 discloses a high speed sense amplifier having a differential stage combined with a common gate stage to provide increased small signal gain and wherein the components of the two stages are also cross-coupled to provide regenerative feedback. An object of the invention is thus to provide a driving circuit for driving a floating circuit in response to a digital signal which is circuitally simple. Another object of the invention is to provide such a driving circuit which has a low power dissipation in the static phase. A further object of the invention is to provide a driving circuit for driving a floating circuit wherein the driving circuit has a low output impedance and high output fluctuation rate. The invention achieves this aim and other objects and advantages as will become apparent from the following description by means of a driving circuit for driving a floating circuit in response to a digital signal comprising: a digital signal source which produces said digital signal; first, second, third and fourth transistors; a current source; and a voltage source; each of said first and second transistors having a source, a drain and a gate; each of said third and fourth transistors being a MOS transistor having a source, a drain and a gate; said first and third transistors being connected in series between said current source and said voltage source; said second and fourth transistors being connected in series between said current source and said voltage source; said first and second transistors being driven in opposite phase on their respective gates starting from said digital signal; the gate of said third transistor being connected to the connection of said fourth transistor to said second transistor; and the gate of said fourth transistor being connected to the connection of said third transistor to said first transistor; characterized in that said current source comprises a reference source which produces a reference current, and a current mirror which mirrors said reference current from said reference source; said first and second transistors are DMOS transistors; the driving output of said driving circuit is the connection of said second transistor to said fourth transistor, and in that said digital signal comprises at least one pulse signal, said current source further comprising an auxiliary circuit for injecting a high current pulse into said current mirror in response to the leading portion of said pulse signal. The invention is now described in greater detail with reference to a preferred embodiment, which is illustrated in the accompanying drawing, given by way of non-limitative example, wherein the only figure is a schematic diagram of a driving circuit according to a preferred embodiment of the invention. In the device illustrated in the figure, two DMOS transistors 10, 12 are driven in opposite phase by a digital input signal source IN by passing the digital input signal directly from source IN to the gate of DMOS transistor 12 and by passing the digital input signal through an inverter 14 to the gate of the DMOS transistor 10. The sources of the two DMOS transistors are connected to a current mirror which provides a biasing current. The current mirror comprises transistors 16, 18 having their gates connected to each other and to the drain of transistor 16. The sources of transistors 16 and 18 are connected to a reference voltage, e.g. ground. The drain of transistor 18 is connected to the source of each of DMOS transistors 10 and 12, while a reference current source 19 is connected between a high voltage source and the drain of transistor 16. Reference current source 19 provides a reference current I BIAS . The loads on the drains of the two DMOS transistors 10, 12 are constituted by P-channel transistors 20, 22, with the transistors 10 and 20 being connected in series with each other between the current source and a high voltage source V F+ and the transistor 12 and 22 being similarly connected in series with each other between the current source and the high voltage source. The gate of transistor 20 is driven by the drain of transistor 22, and the gate of transistor 22 is driven by the drain of transistor 20. Zener diode 24 is connected between the gate and source of transistor 20, while Zener diode 26 is connected between the gate and source of transistor 22, to limit the voltage drop between the source and the gate of the respective P-channel transistor. The drain of the DMOS transistor 12 is connected to the drive input of a per se known floating circuit 28 powered by the floating voltages V F+ , V F- . When the digital input signal from digital signal source IN is 0, the DMOS transistor 10 is "on" and the DMOS transistor 12 is "off". Consequently, the transistor 20 is "off" and the transistor 22 is "on" as well. When the digital input signal from source IN becomes high, the DMOS transistor 10 switches "off" and the DMOS transistor 12 switches "on", also causing the switching of the transistor 20 to "on", and the switching of the transistor 22 to "off". In static conditions, the conditions of the two transistors 20 and 22 are kept stable by the cross-connections between the gates and the drains of transistors 20 and 22, which make this portion of the circuit similar to a flip-flop. The P-channel transistors 20, 22 are dimensioned so as to be able to rapidly charge the parasitic capacitors indicated by 30, 32, i.e. so as to have a low output resistance, for example approximately 1 kohm. The current flowing through the "on" DMOS transistor, which is normally equal to I BIAS , can be relatively small, for example approximately 280 µA. During the switching operation, one of the DMOS transistors switches "off" while the other one switches "on", and in order to prevent the current, which is absorbed by the DMOS transistor which is "on", from being insufficient to open the P-channel transistor connected thereto, the driving circuit furthermore preferably comprises an auxiliary circuit for generating an additional short duration, high current pulse during the switching operation. The auxiliary circuit comprises a transistor 34 which is source-follower connected to the drain of transistor 16. A resistor 35 is connected between the drain of transistor 34 and voltage source V F+ . The transistor 34 is driven by an XOR circuit 36, which receives the digital signal from digital signal source IN on one input and receives the same signal, delayed by a delay chain on its other input. The delay chain can be formed by a series resistor 38, a parallel capacitor 40 and two cascade inverters 42, 44 connected between the source IN and the other input of the XOR. It can thus be seen that the source follower 34 is driven by a short pulse from the XOR which appears during the period between the arrival at one input of XOR 36 of the leading edge of the digital pulse from digital signal source IN and the arrival at the other input of XOR 36 of the delayed version of the leading edge of the digital pulse. The characteristics of the delay chain can be selected to provide a pulse at the output of XOR 36 which is shorter in duration than the digital input pulse from digital signal source IN. Thus, this auxiliary circuit injects a current pulse in parallel to the reference I BIAS . The added pulse from the auxiliary circuit can have a high value, for example 10 mA, without significantly affecting the average absorption of the driving circuit as a whole. A preferred embodiment of the invention has been described, but it is understood that other modifications and variations can be employed. For example, an equivalent circuit utilizing N-channel transistors as the loads for the DMOS transistors instead of the illustrated P-channel transistors could be employed. Other forms of circuits for producing a reference current and/or an auxiliary pulse current can be utilized. The inverted digital signal can be applied to the gate of DMOS transistors 12 instead of DMOS transistor 10. Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included for the sole purpose of increasing the intelligibility of the claims and accordingly, such reference signs do not have any limiting effect on the scope of each element identified by way of example by such reference signs.

Claims: A driving circuit for driving a floating circuit in response to a digital signal (IN) comprising: a digital signal source which produces said digital signal (IN); first, second, third and fourth transistors (10,12,20,22); a current source (16, 18, 19); and a voltage source (V F +); each of said first and second transistors (10,12) having a source, a drain and a gate; each of said third and fourth transistors (20,22) being a MOS transistor having a source, a drain and a gate; said first and third transistors (10,20) being connected in series between said current source (16,18,19) and said voltage source (V F +); said second and fourth transistors (12,22) being connected in series between said current source (16,18,19) and said voltage source (V F +); said first and second transistors (10,12) being driven in opposite phase on their respective gates starting from said digital signal (IN); the gate of said third transistor (20) being connected to the connection of said fourth transistor (22) to said second transistor (12); and the gate of said fourth transistor (22) being connected to the connection of said third transistor (20) to said first transistor (10); characterized in that said current source comprises a reference source (19) which produces a reference current (I BIAS ), and a current mirror (16, 18) which mirrors said reference current from said reference source; said first and second transistors (10,12) are DMOS transistors; the driving output of said driving circuit is the connection of said second transistor (12) to said fourth transistor (22), and in that said digital signal (IN) comprises at least one pulse signal, said current source (16,18,19) further comprising an auxiliary circuit (34-44) for injecting a high current pulse into said current mirror (16,18) in response to the leading portion of said pulse signal. A driving circuit according to claim 1, wherein one of the source and the drain of the first transistor (10) is connected to said current source (16,18,19), one of the source and the drain of the second transistor (12) is connected to said current source (16,18,19), one of the source and the drain of the third transistor (20) is connected to said voltage source (V F +), and one of the source and the drain of the fourth transistor (22) is connected to said voltage source (V F +). A driving circuit according to claim 1, wherein the source of said first transistor (10) is connected to the source of said second transistor (12), with the sources of the first and second transistors (10,12) being biased by said current source (16,18,19); the drain of said first transistor (10) is connected to the drain of said third transistor (20); the drain of said second transistor (12) is connected to the drain of said fourth transistor (22); the source of said third transistor (20) and the source of said fourth transistor (22) are connected to said voltage source (V F +); the gate of said third transistor is connected to the drain of said fourth transistor; and the gate of said fourth transistor (22) is connected to the drain of said third transistor (20). A driving circuit according to one or more of the preceding claims, wherein the gate of one of said first and second transistors (10,12) is connected directly to said digital signal source (IN) and the gate of the other of said first and second transistors (10,12) is connected to said digital signal source through an inverter (14). A driving circuit according to one or more of the preceding claims, wherein said third and fourth transistors (20,22) are P-channel transistors. A driving circuit according to one or more of the preceding claims, further comprising a first Zener diode (24) connected between the gate of said third transistor (20) and said voltage source (V F +), and a second Zener diode (26) connected between the gate of said fourth transistor (22) and said voltage source (V F +). A driving circuit according to one or more of the preceding claims, wherein said high current pulse is of shorter duration than said pulse signal. A driving circuit according to one or more of the preceding claims, wherein said auxiliary circuit (34-44) comprises a pulse source (36-44) and a fifth transistor (34); said pulse source (36-44) being driven by said digital signal (IN); said fifth transistor (34) being source-follower connected in parallel to said reference source (19). A driving circuit according to one or more of the preceding claims, wherein said pulse source (36-44) comprises a delay circuit (38,40,42,44), an XOR circuit (36) having first and second inputs and an output, the first input of said XOR circuit (36) being connected to said digital signal source, the second input of said XOR circuit (36) being connected through said delay circuit (38,40,42,44) to said digital signal source, and the output of said XOR circuit (36) being connected to the gate of said fifth transistor (34). A driving circuit according to claim 9, wherein said delay circuit (38,40,42,44) is adapted to provide a pulse at the output of said XOR circuit (36) which is shorter in duration than said pulse signal. An integrated circuit comprising a floating circuit connected between a high voltage source and a low voltage source and having a drive input, and a driving circuit according to one or more of the preceding claims, wherein the driving output of said driving circuit is connected to the drive input of said floating circuit.

Inventors: DIAZZI CLAUDIO, MARTIGNONI FABRIZIO, PIDUTTI ALBINO, VIO FABIO, DIAZZI, CLAUDIO, MARTIGNONI, FABRIZIO, PIDUTTI, ALBINO, VIO, FABIO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1991
Main classification: H03K3
IPC codes: H03K19, H03K17, H03K3