Enhanced superconducting field-effect transistor with inverted MISFET structure and method for making the same

Abstract: The present invention relates to an inverted MISFET structure with high-T C superconducting channel (25). This field-effect transistor comprises a gate substrate (22) consisting of a doped compound with perovskite structure, an interfacial layer (23) with one or more elements of the VIII or IB subgroup of the periodic table of elements, an insulating layer (24) consisting of a perovskite or related compound, and a high-T C superconducting channel (25). An electric field, generated by a voltage applied to its gate (20), alters the conductivity of the channel (25). The performance of this device is improved three-fold in comparison to known MISFETs with superconducting channels.

Description: TECHNICAL FIELD The present invention relates to field-effect transistors having a structure similar to an inverted MISFET (Metal-Insulator-Semiconductor Field-Effect Transistor) wherein the current channel consists of a high-T C metal-oxide superconductor and the metal gate electrode is replaced by a conducting compound having a perovskite structure. The inventive field-effect transistor is an n-channel or p-channel depletion or enhancement type. An electric field, generated by a voltage applied to the gate, alters the conductivity of the channel. BACKGROUND OF THE INVENTION Based on the new class of superconductors discovered by Bednorz and Muller and disclosed in their article "Possible High-T C Superconductivity in the Ba-La-Cu-O System", Zeitschrift für Physik B, Condensed Matter, Vol. B64, 1986, p. 189 - 193, different field-effect transistor structures have been developed and published using high-T C superconductors. FET (Field-Effect Transistor) structures with superconducting channels have been described in the following articles: "Superconducting Field-Effect Transistor" by F.F. Fang et al., IBM Technical Disclosure Bulletin, Vol. 19, No. 4, September 1976, pp. 1461 - 1462, and in "Experimental Considerations In the Quest for a Thin-Film Superconducting Field-Effect Transistor" by A.F. Hebard et al., IEEE Trans. on Magnetics, Vol. MAG-23, No. 2, March 1987, pp. 1279 - 1282. In these articles structures are described with a superconducting channel having a thickness of about 10 nm. An electric field generated by applying a voltage between a gate electrode and the superconductor causes a slight change in carrier density in a thin surface layer of the superconductor. This change in carrier density in turn results in a shift in transition temperature T C in the thin layer. By applying signals to the gate, the thin layer can be switched between "superconducting" and "normal conducting" states. This results in a change of the channel resistance. Since the field induced effect does not extend deeply into the channel material, various approaches to enhance the magnitude of the effect have been published by A.T. Fiory and A.F. Hebard in two articles "Field-Effect and Electron Density Modulation of the Superconducting Transition in Composite In/InOx Thin Films", Physica 135B, 1985, pp. 124 - 127, North-Holland, Amsterdam, and "Electric Field Modulation of Low Electron Density Thin-Film Superconductors", Proc. Internat. Workshop on Novel Mechanism of Superconductivity, Berkley, June 1987. Of particular interest is the first cited article of Fiory and Hebard because it relates to the fabrication and measurement of a superconducting MISFET. Another article on this subject, relating to a field effect in strontium titanate, has been published by M. Gurvitch et al. "Field Effect on Superconducting Surface Layers of SrTiO₃", Materials Research Society, 1986, pp. 47-49. The disadvantages of these surface effect devices is that the change in channel resistance is quite small. Even in the switched thin surface layer the change is only from metallic conductivity to superconductivity, and in addition, the bulk section of the channel, not being affected by the applied field, acts as a metal shunt parallel to the thin surface layer. Therefore the output signals are too small to be able to drive FET devices. Another drawback is that the field induced change in T C is rather small, i.e., operating temperature T op requirements are stringent since for proper operation the T C of the thin layer has to be shifted from a value above T op to a value below T op . Another field-effect transistor is described in the European Patent Application EP-A 0 324 044, "A Field-Effect Device with a Superconducting Channel". The channel of this device is about 1 nm thick and consists of a high-T C metal-oxide superconductor. Since the channel is extremely thin, it can be affected by an electric field without leaving a metal shunt. With a few volts applied to the gate, the entire channel is depleted of charge carriers whereby the channel resistance can be switched between "zero" (undepleted, superconducting) and "high" (depleted). This structure points the right direction but some problems remained Studies of such devices have shown that in the suggested configuration the ultrathin superconducting layers readily degrade during deposition of the insulating layer and the top electrode. The European Patent Application EP-A-0494580 (with application number 91810006.6), "Superconducting Field-Effect Transistors with Inverted MISFET Structure and Method for Making the Same", addresses the problem of avoiding degradation during the deposition of insulator and electrode by changing the structure such that the superconducting film is deposited after the insulating layer, and locating the gate electrode underneath the insulator and the superconductor. An exemplary cross-section of this inverted MISFET is shown in Figure 1. The gate electrode 10 consists of a conducting niobium-doped strontium titanate, the insulating layer 11 consists of undoped strontium titanate and the current channel 12, which is grown on top of this layer 11, consists of YBa₂Cu₃O 7-δ . Source and drain contacts 13,14 are situated at the upper surface of the current channel 12 and the gate metalization is fixed at the niobium-doped strontium titanate substrate 10. Measurements with these and similar structures showed lower capacitances between gate and source (C GS ) than theoretically expected. In addition only a few percent resistivity modulation was observed. The fact that the performance of the device, as described in this European Patent Application (91810006.6), is influenced by some degradation at the surface of the doped SrTiO₃ has been published in the article "Electric Field Effect on Superconducting YBa₂Cu₃O 7-δ Films", of J. Mannhart et al., Zeitschrift für Physik B, Condensed Matter 83, pp. 307 - 311, 1991. SUMMARY OF THE INVENTION The main object of this invention is to overcome the described deficiencies of known superconducting FETs by providing an improved structure for an inverted MISFET with high-T C superconducting channel. Another object of the present invention is to provide an inverted MISFET with high-T C superconducting channel having an increased capacitance between gate and source. A further object is to improve the resistivity modulation of the known inverted MISFET. It is another object of this invention to teach a method for making an inverted MISFET with high-T C superconducting channel and enhanced performance. The invention as claimed is intended to meet these objectives and to remedy the remaining deficiencies of known inverted MISFETs with high-T C superconducting channel. The principle -and as far as understood today- by which this is accomplished is by preventing the gate electrode from degradation by depositing an interfacial layer between the gate electrode and the insulating layer. DESCRIPTION OF THE DRAWINGS The invention is described in detail below with reference to the following drawings. FIG. 1 is a cross-section through an inverted MISFET with high-T C superconducting channel (Prior Art). FIG. 2 is a cross-section through an inverted MISFET with high-T C superconducting channel and interfacial layer according to the present invention. FIG. 3 shows resistance vs. temperature curves with gate voltage V G as parameter, of an embodiment of the described inverted MISFET with high-T C superconducting channel and enhanced performance. FIG. 4 shows resistance vs. temperature curves with gate voltage V G as parameter, of an embodiment of the described inverted MISFET with high-T C superconducting channel and enhanced performance. FIG. 5 is a cross-section through another inverted MISFET with superconducting channel and interfacial layer, according to the present invention. FIG. 6 is a cross-section through another inverted MISFET with superconducting channel and interfacial layer, according to the present invention. GENERAL DESCRIPTION Measurements of the resistivity and the capacitance of known inverted MISFETs with high-T C superconducting channel showed some drawbacks of these devices. Both effects seem to be caused by a degradation at the surface of the Nb-doped strontium titanate. Similar effects have been observed and reported by H. Hasegawa et al. in their article "Contact between High-T C Superconductor and Semiconducting Niobium-Doped SrTiO₃", Japanese Journ. of Appl. Phys., Vol. 28, No. 12, December 1989, pp. L2210 - L2212. The authors interpreted their measurement of an Er-Ba-Cu-O thin film superconductor deposited on a Nb-doped SrTiO₃ substrate as an indicator that there are unknown interfacial layers between the high-T C superconductor layer and the substrate. Further investigations and measurements showed that a degradation of the doped SrTiO₃ reduces its conductivity and lowers the dielectric constant of the insulating layer. A low dielectric constant of the insulating layer of a field-effect transistor has a negative influence on several parameters of these devices. For example, the change in drain current, resulting from the applied field, the output admittance, and the transconductance are proportional to the dielectric constant of this insulator. Starting from this interpretation, it seemed advantageous for improving a given high-T C superconducting MISFET to prevent degradation of the gate substrate's surface. To accomplish this, an additional interfacial layer consisting of one or more elements of the VIII subgroup or the IB subgroup of the periodic table of elements has been deposited prior to the deposition of the insulating layer. With the addition of this interfacial layer, the capacitance between gate and source (C GS ) has been improved. A three-fold improvement of the capacitance has been observed. In addition more than one order of magnitude improvement in resistivity modulation has been achieved. Before describing the embodiments of the present invention in greater detail, some aspects of different materials being used and the meaning of hereinafter used expressions are explained. As shown in Figure 2, the inventive MISFET comprises a gate electrode 20 consisting of a contact metallization 21 and a substrate 22. The additional layer 23, in accordance with the present invention, is situated between said gate electrode 20 and an insulating layer 24. A superconducting current channel 25 is formed on top of this insulator 24. The drain and source contacts 26, 27 are placed on the current channel 25. The materials used as substrate 22, insulating layer 24, and superconducting current channel 25, are chosen from the same crystallographic family, that is, all having the same perovskite structure. The lattice constants of the materials chosen should at least approximately match. The layers herein used have a mismatch below 20%. The mismatch m is defined by equation (1): m:=| a 1 -a 0 a 0 |, wherein a₀ is the lattice constant of the "substrate" and a₁ the lattice constant of the following layer. The materials used for the substrate and the insulating layer are taken from the group of perovskites and related compounds. The perovskites form a family of compounds having a crystal structure similar to that of the mineral perovskite, CaTiO₃. Some of these compounds with perovskite structure are listed below. Their lattice constants and the dimensions of the perovskite subcells are given in the following list. Compound Lattice constants Dimensions of subcell a/Å b/Å c/Å a s /Å b s /Å c s /Å CaTiO₃ 5,381 5,443 7,645 3,827 3,827 3,823 KTaO₃ 3,9885 3,9885 LaAlO₃ 5,357 3,791 La₂CuO₄ 5,36 5,41 13,17 3,81 3,81 13,17 LaGaO₃ 5,496 5,524 7,787 3,896 3,896 3,894 NdGaO₃ 5,426 5,502 7,706 3,864 3,864 3,853 PrGaO₃ 5,465 5,495 7,729 3,875 3,875 3,865 Sr₂RuO₄ 3,870 3,870 12,74 3,870 3,870 12,74 SrTiO₃ 3,905 3,905 Many more perovskites and related compounds are listed in the book "Numerical Data and Functional Relationships in Science and Technology", Landolt-Börnstein, Group III: Crystal and Solid State Physics, Volume 4, Part a, Springer-Verlag. To make a substrate consisting of these compounds conductive it has to be doped with appropriate dopants. Strontium titanate (SrTiO₃) , for example, is an insulator. By doping it with niobium (Nb) it becomes electrically conducting. This niobium doped compound with perovskite structure is hereinafter referred to as Nb:SrTiO₃. The surface of this substrate, consisting of a compound with perovskite structure, degrades during the deposition of the insulating layer and the high-T C superconducting channel, because of the oxidizing environment used for these deposition steps. The degraded and insulating surface of the substrate results in a dramatic lowering of the capacitance between gate and source (C GS ) of the inverted MISFET structure. By adding an interfacial layer consisting of elements of the VIII subgroup or the IB subgroup of the periodic table of elements, the performance of the inverted MISFET can be improved. With this additional layer 23 between substrate 22 and insulating layer 24, as illustrated in Figure 2, a three-fold improvement of the capacitance C GS and more than an order of magnitude improvement in resistivity modulation was observed. The chosen material for this interfacial layer 23 has to be highly conductive, resistant to oxidation, its lattice constant and its thermal expansion coefficient close to those of the used substrate 22 and insulating layer 24 compounds with perovskite structure and the high-T C metal-oxide superconductor 25. Besides satisfying these requirements of structural compatibility, it is also desirable to have a chemically compatible material which does for example not react with or otherwise destroy the properties of the insulating or superconducting layers. In addition the compounds with perovskite structure and the one or more elements of the interfacial layer have to be chosen such that epitaxy occurs. One favorable parameter is the lattice constant and the dimensions of the subcells a s , b s , c s as shown in the list of perovskites and related compounds. Examples of materials that satisfy many of these constraints are the elements from the subgroups VIII and IB of the periodic table of elements and their alloys. The utilization of semiconductors replacing these metals or alloys is conceivable. Well suited are Pt, Rh, Pd, Ag, Au and their alloys. By using an alloy of these elements the lattice constant can be varied by controlling the composition of the elements. For example, the lattice constant of Pt-Rh alloys can be varied between 3,804 Å (pure Rh) and 3,924 Å (pure Pt). This ability allows for an even better lattice match to the surrounding layers to be obtained. The appropriate alloy composition yielding roughly the desired lattice constant can be calculated from Vegard's law given below. Vegard's Law: For two components A and B having the same crystal structure and for which a substitutional solid solution exists, the lattice constant a mixture of a mixture containing x atomic % A and (1-x) atomic % B is approximately given by a mixture ≅ x a A + (1-x)a B where a A is the lattice constant of pure A and a B is the lattice constant of pure B. Details of this law are described in an article of L. Vegard published in Zeitschrift für Physik, Vol. 5, 1921, p. 17. Deviations from Vegard's law are investigated in the book "Structure of Metals, Crystallographic Methods, Principles and Data", Third Revised Edition, of C.S. Barrett et al., Pergamon Press 1980. The lattice constants of these elements of the periodic table of elements are listed below: Element Lattice constant a₀/Å Ag 4,086 Au 4,079 Ir 3,839 Pd 3,891 Pt 3,924 Rh 3,804 The binary phase diagrams of the different alloys are published in the book "Binary Alloy Phase Diagrams", Volumes 1 and 2, American Society for Metals, Ohio USA. These diagrams show if an alloy can be produced and if a corresponding substitutional solid solution exists. The first embodiment according to the present invention is described in context with Figure 2. As the compound with perovskite structure, strontium titanate, SrTiO₃, has been chosen, the substrate 22 being employed is doped with niobium (Nb), in particular a single crystal doped with 0,05% Nb and (100) oriented. An interfacial layer 23 of platinum (Pt) is situated on top of said substrate 22. The thickness of this layer is about 4 nm. The insulating layer 24, consisting of undoped SrTiO₃ has a thickness of about 500 nm. This layer 24 is followed by the superconducting channel 25 consisting of YBa₂Cu₃O 7-δ of about 7nm. Gold (Au) contact pads 26 and 27, used as source and drain contacts, are situated on top of the channel 25. The gate contact 21 consists of silver (Ag). Measurements of this device showed an improvement of its performance in comparison to similar devices without Pt-layers. As shown in Figure 3 and 4, the YBa₂Cu₃O 7-δ film is superconducting below ≃ 14 K (T C ≃14K). The resistance vs. temperature is shown in these Figures, with gate voltage V G as a parameter. Figure 4 shows resistance vs. temperature curves with gate voltage as a parameter in the region of the superconducting transition (the temperature range from 13 K to 15 K). Different experiments and measurements have shown that a thin Pt layer improves the surface quality of the substrate 22 considerably. Due to the good lattice match between Pt and SrTiO₃, the Pt layer can be grown epitaxially on the substrate. The mismatch m, as defined in equation (1) is m=| 3,924-3,905 3,905 |≈0,5. The effective dielectric constant ε i of the SrTiO₃ insulating layer 24 has been found to be greater than 100 at 300 K in comparison to ε i ≃40 in a comparable structure without Pt layer 23. As expected, a major increase in device sensitivity is observable. The resistivity modulation for example increased more than an order of magnitude. It was noted, however, that in addition to the beneficial effect of Pt diffusion into the dead surface layer of the Nb doped substrate 22, that Pt diffusion through the undoped SrTiO₃ layer 24 into the YBa₂Cu₃O 7-δ superconducting channel 25 does occur during deposition of the insulator and superconductor. This results in a broadening of the superconducting transition. For this reason, best results are achievable employing thin interfacial layers and thick insulating layers. Interfacial layers with a thickness of 1 up to 100 Å and insulating layers with a thickness of several thousand Ås are well suited. By lowering the processing temperatures after the deposition of the interfacial layer, further improvements in device performance are possible. In the first embodiment it was experimentally demonstrated that the interfacial Pt layer improves the properties of the substrate and the whole device. Pt was chosen for several reasons: it is highly conductive, it is resistant to oxidation during further processing steps in the oxygen ambient, and its lattice mismatch is about 0,5 %. In addition, platinum is chemically compatible with the used compounds with perovskite structure. The fabrication of an inverted MISFET with high-T C superconducting channel and interfacial Pt layer is described in the following section. The processing steps after deposition of said Pt layer are critical because high temperatures stimulate the diffusion of Pt. The gate electrode 20 of the inverted MISFET mainly consists of a conducting n-type (0,05% Nb doped) SrTiO₃ (100) single crystal substrate 22, grown by the float-zone technique. This substrate 22 is heated to about 600 °C and a thin epitaxial layer 23 of platinum is deposited by electron-beam evaporation. The sample is then transferred to a radio frequency (RF) magnetron sputtering chamber and about 500 nm of undoped SrTiO₃ is deposited at a substrate temperature of about 680 °C in a 0,05 Torr argon-oxygen ambient with Ar:O₂=2:1. Without leaving the vacuum environment, the sample is transferred to a direct current (DC) magnetron sputtering chamber where about 80 Å of YBa₂Cu₃O 7-δ is deposited at a substrate temperature of about 750 °C and with a pressure of 0,65 Torr (Ar:O₂=2:1). The sample is then cooled down in a 400 Torr O₂ ambient and removed from the vacuum chamber. Using conventional photolitography and wet etching steps, the sample is patterned and gold contact pads 26, 27 are made to the source and drain contacts. The gate contact 21 (to the back side of the conducting substrate 22) is made using silver paint. This embodiment can be modified by variations of the thickness of the layers and by using other compounds with perovskite structure, interfacial layer and contact materials, and by employing other high-T C metal-oxide superconductors. In addition the arrangement of the contacts can be changed. A second embodiment is illustrated in Figure 5. The substrate 50 consists of a undoped compound with perovskite structure. An interfacial layer 51 is deposited on this substrate 50 according to the invention, and a gate contact 52 is fabricated by a subsequent processing step. On top of this interfacial layer 51, an insulating layer 53 is situated and a high-T C metal-oxide superconductor 54 is deposited thereon. An exemplary arrangement of source and drain contact pads 55, 56 is shown in this figure. This embodiment has the advantage that all three contacts are accessible from the top of the device and that by pattering the interfacial layer 51 the gates of many devices present on the same substrate may be individually controlled. This is advantageous in particular for the packaging of these three-terminal devices. If a high aspect ratio of the gate contact is required, the deposited contact 52 can be used as plating base for the electro-deposition of a thicker contact structure or a recess may be etched into the substrate before the growth of the overlying layers. A third embodiment of the present invention is described below. A cross-section thereof is illustrated in Figure 6. The substrate 60 consists of an undoped compound having a perovskite structure. A doped compound 61 also having a perovskite structure is situated on top of the substrate 60. An interfacial layer 62 is deposited on this doped compound. An insulating layer 63 followed by a high-T C superconducting channel 64 is deposited on top of the interfacial layer 62. Drain and source contact pads 65 and 66 are placed on the channel 64 and a gate contact 67 is fixed at the interfacial layer 62, as shown in Figure 6. This embodiment shows comparable advantageous as the second embodiment and can become important for the integration of multiple devices on one substrate. The three embodiments are examples of how to implement the interfacial layer to improve the performance of inverted MISFETs with high-T C superconducting channels. In addition, MISFETs with heterostructures are conceivable consisting, in accordance with the present invention, of high-T C metal-oxide superconductor/perovskite-related compound multilayers being grown on top of an interfacial layer which is situated on a conducting substrate.

Claims: Field-effect transistor having a gate substrate (22; 50; 60), an insulating layer (24; 53; 63), a high-T C superconducting current channel (25; 54; 64) which is formed on said insulating layer (24; 53; 63), source and drain electrodes (27, 26; 56, 55; 66, 65) connected to the channel (25; 54; 64), and wherein said gate substrate (22; 50; 60) contains a doped compound having a perovskite structure, characterized by an additional layer (23; 51; 62) between said gate substrate (22; 50; 60) and the insulating layer (24; 53; 63) forming an interface between the gate substrate (22; 50; 60) and said insulating layer (24; 53; 63), said additional layer (23; 51; 62) comprising an element of the VIII subgroup or the I-B subgroup of the periodic table of elements. The Field-effect transistor of claim 1, wherein said element is a noble metal. The field-effect transistor of claim 1 or 2, wherein said additional layer (23; 51; 62) comprises a combination of the elements of the respective subgroups. The field-effect transistor of any of the preceding claims, wherein the thickness of said additional layer (23; 51; 62) is less than 100 Å, preferably between 10 and 50 Å. The field-effect transistor of claim 1, wherein said gate substrate (50) is at least partly covered by said additional layer (51). The field-effect transistor of any of the preceding claims, wherein said additional layer (23; 51; 62) consists of a mixture of said elements such that the lattice constant of the additional layer (23; 51: 62) approximately matches to the lattice constants of the adjacent materials. The field-effect transistor of claim 6, wherein said additional layer (23; 51; 62) consists of a mixture of said elements such that epitaxial deposition is possible. The field-effect transistor of any of the preceding claims, wherein said compound having a perovskite structure consists of niobium-doped strontium titanate Nb:SrTiO₃, said additional layer (23; 51; 62) comprises a nobel metal having approximately the same lattice constant as said niobium-doped strontium titanate Nb:SrTiO₃, said insulating layer (24; 53; 63) consists of strontium titanate SrTiO₃, and said superconducting channel (25; 54; 64) consists of YBa₂Cu₃O 7-δ . The field-effect transistor of claim 8, wherein said strontium titanate SrTiO₃ is doped with a doping factor of between 0,01% and 10%, and wherein said noble metal is platinum. Method for the fabrication of a field-effect transistor having a gate substrate (22; 50; 60), an insulating layer (24; 53; 63), a high-T C superconducting current channel (25; 54; 64) which is formed on said insulating layer (24; 53; 63), source and drain electrodes (27, 26; 56, 55; 66, 65) connected to the channel (25; 54; 64), and wherein said gate substrate (22; 50; 60) contains a doped compound with perovskite structure, comprising the following steps: growing a compound having a perovskite structure (22; 50; 60) using the float-zone technique, forming said substrate (22; 50; 60), heating said substrate (22; 50; 60) and epitaxially depositing on said compound having a perovskite structure (22; 50; 60) an additional layer (23; 51; 62), preferably between 10 - 50 Å thick, said additional layer (23; 51; 62) comprising an element of the VIII subgroup or the I-B subgroup of the periodic table of elements, depositing an insulating compound having a perovskite structure forming said insulating layer (24; 53; 63) thereon, depositing a high-T C superconducting metal-oxide layer forming said current channel (25; 54; 64) on said insulating layer (24; 53; 63). The method of claim 10, wherein said compound with perovskite structure is deposited in a radio frequency (RF) magnetron sputtering chamber, and said high-T C superconductor is deposited in a direct current (DC) magnetron sputtering chamber. The method of claim 10 or 11, wherein said substrate (22; 61) is a niobium-doped single crystal strontium titanate Nb:SrTiO₃ with (100) orientation, said additional layer (23; 62) consists of platinum (Pt) deposited at about 600° C, said insulating compound with perovskite structure is undoped strontium titanate SrTiO₃ being sputtered at about 680°C with a pressure of 0,05 Torr in an argon-oxygen ambient, said high-T C superconducting layer (25; 64) consists of YBa₂Cu₃O 7-δ deposited at about 750° C and a pressure of 0,65 Torr in an argon-oxygen ambient.

Inventors: BEDNORZ JOHANNES GEORG DR, MANNHART JOCHEN DR, MUELLER CARL ALEXANDER PROF DR, SCHLOM DARRELL DR, BEDNORZ, JOHANNES GEORG, DR., MANNHART, JOCHEN, DR., MUELLER, CARL ALEXANDER, PROF. DR., SCHLOM, DARRELL, DR., Müller, Carl Alexander, Prof. Dr.
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1991
Main classification: H01L39
IPC codes: H01L39