Liquid crystal display for displaying half-tone images

Abstract: A liquid crystal display comprises picture elements each including a plurality of pixel electrodes (10,12,11,13) of different sizes. Each pixel electrode (10,12,11,13) is connected to a thin film transistor (20,21,22,23). To reduce flicker when displaying a half tone image, each thin film transistor (20,21,22,23) comprises a channel whose width is a function of the size of the corresponding pixel electrode (10,11,12,13). Preferably each thin film transistor (20,21,22,23) comprises a channel whose width is proportional to the size of the corresponding pixel electrode (10,11,12,13).

Description: The present invention relates to an active matrix liquid crystal display having thin film transistor (thereafter referred to as TFT) switching elements, and more particularly, to a liquid crystal display for displaying half tone images by gradation of pixel area. Conventionally, an active matrix liquid crystal display for displaying half tone images comprises picture elements each consisting of a plurality of pixel electrodes of different areas. Each pixel electrode is driven by a different TFT. PUPA no. 62-182717 describes an example of such a liquid crystal display. In operation, different combinations of the pixel electrodes in each picture element are turned on to produce different levels of half tone. For example, a liquid crystal display in which the picture elements include four pixel electrodes of different sizes can produce 16 levels of half tone. In general, the TFTs connected to the pixel electrodes of each picture element have a 1:1 ratio of channel width to channel length. However, there is a pixel capacitance (CLC) associated with each pixel electrode which is a function of the size of the pixel electrode. The pixel capacitance acts as an electrical load on the output of the corresponding TFT. Therefore, each TFT associated with the picture element is effectively connected to a different electrical load. Furthermore, because the same leakage current flows through each TFT, the speed of leakage is higher for a pixel electrode of smaller area than for a pixel of electrode of larger area. Therefore each pixel electrode has a different holding characteristic. Still furthermore, the voltage drop in the gate drive voltage applied to a TFT across the gate-source capacitance (CGS) of the TFT is a function of the size of the associated pixel electrode. This voltage drop is generally referred to as the "punch through" voltage (ΔVcell). Specifically ΔVcell is related to CLC by to the equation: V cell =V G ( 1 1+C LC /C GS ) (where V G , is a gate driving voltage, C LC is a pixel capacitance, and C GS is the gate source capacitance). The optimum gate drive voltage is therefore different for each pixel electrode in the picture element. The differences in the responses of the TFTS associated with driving each picture element cause flicker to be produced on the display. In accordance with the present invention, there is now provided a liquid crystal display comprising: a plurality of picture elements each including a plurality of pixel electrodes of different size, and a plurality of thin film transistors each connected to a corresponding one of the pixel electrodes; characterised in that each of the thin film transistors comprises a channel whose width which is proportional to the size of the corresponding pixel electrode. The present invention advantageously provides a liquid crystal display having a uniform display characteristic that is substantially free from flicker. This is produced by equalizing the "punch-through voltage" for every pixel and by equalizing a writing characteristic and a holding characteristic of each subpixel. In a preferred embodiment of the present invention, there is provided a liquid crystal display in which the channel width of each TFT driving each pixel is changed in proportion to the size of each pixel electrode. Embodiments of the present invention will now be described by way of example only, which reference to the accompanying drawings in which:- FIG.1 is a circuit diagram of a picture element in an example of a liquid crystal display of the invention. FIG.2 shows a structure of a TFT of the picture element shown in FIG1. FIG.3 is a circuit diagram of a picture element in another example of a liquid crystal display of the present invention. FIG.4 is a block diagram illustrating the area gradation method. Referring first to FIG.1, an example of a liquid crystal of the present invention comprises, gate lines 40a and 40b connected to each of the gate electrodes of TFT's 20 and 22 and of TFT's 21 and 23, respectively. FIG.2 shows an example a structure of one of these TFTs. Data lines 30a and 30b are connected to each of the drain electrodes of the TFT's 20 and 21 and of the TFTs 22 and 23, respectively. In this example, picture elements are composed of four pixels. The ratio of pixels 10, 11, 12, and 13 in size is 8:4:2:1 of the Liquid Crystal Display. Therefore, one picture element can display 16 levels of gradation. Pixel electrodes 10, 11, 12, 13, and 14 produce pixel capacitances C LC8 , C LC4 , C LC2 , and C LC1 , respectively. The source electrode of the TFT's 20, 21, 22, and 23 are connected to pixel capacitances C LC8 , C LC4 , C LC2 , and C LC1 , respectively. Because, as aforementioned, the capacitance is proportional to the size of a pixel electrode, the ratio of the subpixel capacitances C LC8 , C LC4 , C LC2 , and C LC1 will be 8:4:2:1. Also, the TFT's 20, 21, 22, and 23 have the gate-source capacitances C GS8 , C GS4 , C GS2 , and C GS1 . In operation, gate signals are sequentially applied to the gate lines 40a and 40b and a gate line 40c from a gate driven (not shown), the TFT's 20, 22, 21, and 23 are driven in this order. Simultaneously, data signals are applied to the data lines 30a, 30b and 30c from a data driver (not shown) Data is thus written into the pixels 10, 11, 12, and 13. For example the data written to pixel 10 is stored in the form of electronic charge on corresponding pixel capacitance CLC8. Preferably, enough charge is stored to maintain pixel 10 in an 'on' state for a frame refresh period after which the charge is refreshed. If the channel width W of the TFT's shown in FIG.2 is changed in proportion to the size of the pixel electrodes, the gate source capacitance C GS of the TFT, and ON resistance R ON and 1/OFF resistance R OFF of the TFT also change in proportion to the channel width W of the TFT. Therefore, a punch-through voltage ( V cell ), writing characteristic, and a holding characteristic of the pixels can be obtained varied according to the following: (1) Punch-through voltage V cell = V G C GS G LC +C GS = V G 1 1+ C LC C GS (where V G is a gate driving voltage of TFT, C LC is a pixel capacitance, and C GS is a capacitance between gate electrode and source electrode of TFT). In the equation (1), C GS changing in proportion to the size of the pixel electrodes, C LC /C GS is constant and the punch-through voltage ( V cell ) is equalized independently of the size of the pixel electrodes so that flicker is not produced. (2) Writing characteristic A write time T ON can be defined as follows: T ON =R ON C LC (where R ON is ON resistance of TFT and C LC is a pixel capacitance.) In the equation (2), if the channel width W of the TFT's is changed in proportion to the size of the pixel electrodes, thereby changing, the pixel capacitance C LC , the time T ON required for writing to the liquid crystal pixel will be constant since the ON resistance R ON is inversely proportional to the channel width W. That is, the write time is the same for all pixel of different size of the pixel electrodes of the picture element and thus a flicker will not be produced. (3) Holding characteristic A hold time T OFF for the liquid crystal pixel based on a leakage current of the TFT can be obtained from the following: T OFF =R OFF C LC (where R OFF is OFF resistance of TFT and C LC is a pixel capacitance.) In the equation (3), if the channel width W of the TFT is changed in proportion to the pixel capacitance C LC , a hold time T OFF will be constant independently of the size of the pixel electrode since the OFF resistance R OFF of the TFT is inversely proportional to the channel width W of the TFT. Accordingly, a data holding characteristic of liquid crystal is equalized for any pixel having the electrodes of different size. Referring now to Figure 3, in another example of a liquid crystal display of the present invention, each TFT in a picture element is provided with a compensation capacitor C s connected in parallel with the pixel capacitance C LC . The compensation capacitor increases the total capacitance of the pixel to C s +C LC , thereby increasing the period for which the pixel can be held in an 'on' state. Therefore, for the example of the present invention shown in Figure 3, C LC in equation 1 is replaced by C LC +C s . Thus, in the examples hereinbefore described of liquid crystal displays of the present invention hereinbefore described, the channel width of each TFT driving each pixel electrode, is changed in proportion to the size of each pixel electrode to equalize the influence of the gate driving voltage (punch-through voltage) on the potential of the pixel electrode. This maintains constant write time, picture element and constant hold time for the liquid crystal picture element, regardless of the size of the pixel electrode (that is, C LC ), and thus to prevents a display screen from flickering. Examples of the present invention have been described with reference to a liquid crystal display panel comprising picture elements each including four pixel electrodes for producing 16 levels of half tone. It will however be appreciated that the present invention is not limited in application to such a liquid crystal display, and is equally applicable to liquid crystal displays with picture elements comprising more or less than four pixel electrodes for producing more or less than 16 levels of half tone.

Claims: A liquid crystal display comprising: a plurality of picture elements each including a plurality of pixel electrodes (10,12,11,13) of different sizes, and a plurality of thin film transistors (20,21,22,23) each connected to a corresponding one of the pixel electrodes (10,12,11,13); characterised in that each of the thin film transistors (20,21,22,23) comprises a channel whose width is a function of the size of the corresponding pixel electrode (10,11,12,13). A liquid crystal display as claimed in claim 1 wherein each of the thin film transistors (20,21,22,23) comprises a channel whose width is proportional to the size of the corresponding pixel electrode (10,11,12,13). A liquid crystal display as claimed in claim 1 or claim 2 wherein each picture element comprises a plurality of compensation capacitors (Cs8,Cs4,Cs2,Cs1) each connected to a corresponding one of the pixel electrodes (10,11,12,13).

Inventors: SUZUKI HIROSHI, YAMAGUCHI HIDEFMI, SUZUKI, HIROSHI, YAMAGUCHI, HIDEFMI
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1991
Main classification: G02F1
IPC codes: G02F1, H01L29, H01L27, H01L21, G09G3