Power supply circuit having reset circuit

Abstract: A power supply circuit includes a power supply stabilizing circuit (C1), a reset circuit (12), and a switching circuit (18). The power supply stabilizing circuit (C1) stabilizes a power supply voltage (Vcc) from a power supply (3) and applying the voltage to a main circuit (10). The reset circuit (12) outputs a reset signal to the main circuit (10) when the power supply voltage rises. The switching circuit (18) is connected to the power supply stabilizing circuit (C11). The switching circuit (18) stops supply of power to the reset circuit (12) when the voltage applied to the main circuit (10) becomes a value not more than a predetermined value after supply of power is interrupted.

Description: The present invention relates to an arrangement of a circuit for resetting an internal state of a main circuit at the rise time of a power supply voltage. A conventional power supply circuit having a reset circuit of this type has an arrangement shown in, e.g., Fig. 4. A reset circuit 2 is connected to an integrated circuit (IC) 1 as a main circuit. A voltage from a battery 3 is stored in a capacitor C1 so as to supply a stable power supply voltage to the IC 1. When a switch S is closed, the reset circuit 2 receives a power supply voltage and supplies a reset signal to the IC 1, thus resetting the internal state thereof. Figs. 5 and 6 show changes in voltage applied to the IC 1 when the switch S is opened and closed. Fig. 5 shows changes in terminal voltage when the switch S is closed. More specifically, when the switch S is closed, and a DC voltage V CC is applied from the battery 3 to the IC 1 and the reset circuit 2 at time t = 0, the voltage of a power supply input terminal 4 of the IC 1 substantially reaches V CC at t = 0, provided that the capacitance of the input terminal 4 is negligibly small, as indicated by a curve 4a in Fig. 5. Assume that a sufficient period of time has elapsed at time t < 0 after the switch S is opened, charges in the capacitor C1 and a capacitor C2 are discharged through resistors R1 and R2, and no charges are left in the capacitor C2. In this case, a voltage is applied to a reset input terminal 5 in accordance with a time constant determined by the resistor R1 and the capacitor C2, as indicated by a curve 5a in Fig. 5. Providing that the resistor R1 has a resistance r 1 (Ω) and the capacitor C2 has a capacitance c 2 (F), a time constant τ 1 is given by τ 1 = r 1 ·c 2 (S). Referring to Fig. 5, reference numeral 6 denotes a GND terminal. If the switch S is closed, and a power supply voltage is applied to the IC 1 in this manner, the voltage V cc is applied to the power supply voltage input terminal 4 when time t is sufficiently close to 0. At the same time, a voltage sufficiently close to 0 V is applied to the reset input terminal 5, and the voltage of the reset input terminal 5 reaches V cc with the lapse of time. Subsequently, the internal state of the IC 1 is reset to 0 V, i.e., "Low" logic level. More specifically, the IC 1 is reset by a reset signal having a voltage close to 0 V, which is applied to the reset input terminal 5. The reset state of the IC 1 is cancelled when the voltage of the reset input terminal 5 is increased after the reset operation. Fig. 6 shows changes in terminal voltages when the switch S is opened. When the switch S is opened (t = t a ), and no power supply voltage is applied to the IC 1, the voltage of the reset input terminal 5 is decreased as indicated by a curve 5b in Fig. 6, provided that the capacitor C1 can be neglected, as indicated by the following equation: time constant τ 2 = (r 1 + r 2 )c 2 [S] (R 2 = r 2 [Ω]) In practice, however, a capacitor having a large capacitance is generally used as the capacitor C1 in order to stabilize a power supply voltage, and hence c 1 >> c 2 is established. If, therefore, the current consumption of the IC 1 is small, the voltage of the reset input terminal 5 exhibits changes indicated by a curve 5c in Fig. 6, due to the following time constant as a dominant factor: time constant τ 3 = r 2 ·c 1 [S] (C1 = c 1 [F]) Note that a portable radio transceiver does not have the switch S, and the reset circuit 2 is operated upon mounting and dismounting of the battery 3. The following problem is posed in the above-described reset circuit 2. When the switch S is opened and is subsequently closed again before the voltage of the reset input terminal 5 is sufficiently decreased, the IC 1 cannot be reset in spite of the fact that the power supply voltage applied to the IC 1 is decreased once. In order to solve such a problem, the time constant τ 2 needs to be made small, and r 2 and c 1 need to be made small to minimize the time constant τ 3 if the current consumption of the IC 1 is small. However, the capacitance c 1 of the capacitor C1 needs to be relatively large to stabilize a power supply voltage and hence cannot be set to be small. In addition, if the resistor R2 (r 2 ) is made small, a current corresponding to the decrease in r 2 undesirably flows constantly. Since a decrease in the time constant τ 3 is limited in this manner, it is difficult to prevent variations in power supply voltage in a decreased state, which are caused upon, e.g., quick switching of power supplies, from influencing a reset operation. In the specification of European patent application number 88111649.5, which was published under number 300440 on January 28, 1989, there was proposed a reset circuit for microprocessors and counters, in which a low-resistance bypass path, consisting of a switching transistor in series with a diode, was connected in parallel with the resistor of an RC reset means, the base of the switching transistor being connected to a voltage divider consisting of a resistor and a Zener diode, and the voltage divider being connected in parallel with the capacitor of a current-limiting RC supply means. A reset circuit, which included an integrating circuit, for converting the curve of the rise of a power supply for a microprocessor to a specific curve, was proposed in the specification of Japanese patent application No. 63-75231, which was published under number 1-246616 on October 2 1989, as mentioned in the Patent Abstracts of Japan Vol. 13, No. 583 (P-981)(393) dated December 22, 1989. The present invention enables a power supply circuit to be provided which has a reset circuit, which can reliably perform a reset operation of a main circuit by minimising the influences of variations in power supply voltage in a decreased state. A power supply circuit will be described below which includes a power supply stabilizing circuit for stabilizing a power supply voltage from a power supply and applying the voltage to a main circuit, a reset circuit for outputting a reset signal to the main circuit when the power supply voltage rises, and reset circuit control means, connected to the power supply stabilizing circuit, for stopping supply of power to the reset circuit when the voltage applied to the main circuit becomes a value not more than a predetermined value after supply of power is interrupted. In the above-described arrangement, when supply of power is interrupted upon, e.g., switching, a voltage applied from the power supply stabilizing circuit, e.g., a capacitor, is decreased in accordance with a predetermined time constant. When the voltage becomes a predetermined value or less, the supply of power to the reset circuit is interrupted by the switching circuit. Therefore, the voltage at the output terminal of the reset circuit is quickly decreased to 0 V regardless of the power supply stabilizing circuit, and a resettable state can be immediately ensured. The following description and drawings disclose a conventional arrangement and, by means of an example, the invention which is characterised in the appended claims, whose terms determine the extent of the protection conferred hereby. In the drawings:- Fig. 1 is a circuit diagram showing a power supply circuit having a reset circuit according to an embodiment of the present invention; Fig. 2 is a graph showing changes in voltage at a power supply voltage input terminal and a reset input terminal upon closing of a switch in the embodiment; Fig. 3 is a graph showing changes in voltage at the power supply voltage input terminal and the reset input terminal upon opening of the switch; Fig. 4 is a circuit diagram showing a conventional power supply circuit having a reset circuit; Fig. 5 is a graph showing changes in voltage at a power supply voltage input terminal and a reset input terminal upon closing of a switch in Fig. 4; and Fig. 6 is a graph showing changes in voltage at the power supply voltage input terminal and the reset input terminal upon opening of the switch in Fig. 4. An embodiment of the present invention will be described below with reference to the accompanying drawings. Fig. 1 shows a power supply circuit having a reset circuit according to the embodiment. A p-channel MOSFET (metal oxide semiconductor field effect transistor) 18 as a switching circuit (reset circuit control means) is incorporated in an integrated circuit (IC) 11 having a main circuit 10. When a switch S is closed, a power supply voltage V CC from a battery 3 is applied to a power supply voltage input terminal 14. A capacitor C11 serves as a power supply stabilizing circuit for stabilizing a power supply voltage, and has a relatively large capacitance c 11 . One terminal of the capacitor C11 is connected to the power supply voltage input terminal 14 of the IC 11. An output terminal 17 of the IC 11 serves as a power supply voltage output terminal with respect to a reset circuit 12, and the gate of the FET 18 is grounded. With this arrangement, when the voltage V CC is applied to the power supply input terminal 14, a gate-source voltage V GS exceeds a threshold value V TH , and the FET 18 is rendered conductive. As a result, the power supply voltage V CC is applied from the power supply voltage output terminal 17 to the reset circuit 12. Note that a terminal 16 is a GND terminal. The reset circuit 12 is constituted by resistors R11 (= r 11 ) and R12 (= r 12 ) and a capacitor C12 (= c 12 ). The reset circuit 12 outputs a reset signal to a reset input terminal 15 of the IC 11. When the power supply voltage V CC is to be applied from the power supply voltage output terminal 17 of the IC 11, since r 11 > r 12 , a voltage V IN of the reset input terminal 15 is given by V IN = (r 11 /(r 11 + r 12 ))V CC ∼ V CC and serves as a "High" logic-level input. As a result, the reset state is canceled. An operation of the embodiment having the above-described arrangement will be described below. When the switch S is closed while the reset input terminal 15 of the IC 11 is set in a state of voltage V IN ≃ 0, i.e., when the switch S is switched from an open state to a closed state (time t = 0), the power supply voltage V CC is applied to the power supply voltage input terminal 14. This voltage is also applied to the FET 18. Fig. 2 shows changes in terminal voltage upon closing of the switch S. The voltage V CC applied to the power supply voltage input terminal 14 exhibits changes indicated by a curve 14a. At the same time, the FET 18 is rendered conductive when the gate-source voltage v GS exceeds the threshold value V TH . As a result, the power supply voltage V CC is output from the power supply voltage output terminal 17 to the reset circuit 12. In this case, the voltage V IN of the reset input terminal 15 is changed as indicated by a curve 15a in Fig. 2 in accordance with a time constant τ 11 ≃ r 12 ·c 12 because r 11 >> r 12 . If time t in Fig. 2 is sufficiently close to 0, the power supply voltage V CC is applied to the FET 18. At the same time, a "Low" logic-level signal having a voltage sufficiently close to 0 V is input to the reset input terminal 15. Therefore, the internal state of the IC 11 is reliably reset immediately after the switch S is closed to apply the power supply voltage. After the reset operation is completed, the reset is canceled. With this operation, initialization of the main circuit 10 of the IC 11 is completed. In other words, initialization of the main circuit 10 (or the IC 11) is completed only after the reset input terminal 15 undergoes a state change from "Low" level to "High" level (reset to reset cancellation) when the switch S is closed, i.e., a new battery is mounted. The reset circuit 12 is required to cause the above-mentioned state change. In contrast to this, when the switch S is opened (t = t b ), a voltage applied to the power supply voltage input terminal 14 is decreased as indicated by a curve 15b in Fig. 3. When the gate-source voltage V GS of the FET 18 becomes lower than the threshold value V TH , the FET 18 is rendered nonconductive. At this time, since no power supply voltage v 1 is applied to the reset circuit 12, the reset input terminal voltage V IN has a time constant τ 12 = r 11 ·c 12 and is quickly decreased, as indicated by a curve 15c. As described above, in this embodiment, when the power supply voltage v 1 becomes equal to or lower than the threshold value |V| of the FET 18, the reset input terminal voltage V IN is changed in accordance with the time constant τ 12 = r 11 ·c 12 regardless of the capacitance of the capacitor C11 and a decreased state of the power supply voltage v 1 . Since c 12 << c 11 , the time constant can be set to be sufficiently smaller than that in a conventional circuit by sufficiently decreasing the product of r 11 and c 12 . In addition, the level of the power supply voltage v 1 at which the reset input terminal voltage V IN begins to quickly drop corresponds to the threshold value |V TH |. Therefore, if the overall IC 11 is constituted by MOSFETs each having substantially the same threshold voltage (absolute value) as that of the FET 18, the minimum operating voltage of the IC 11 becomes nearly equal to the threshold value |V TH |. That is, the instant at which the reset input terminal voltage V IN begins to rise from 0 V when the power supply is turned on corresponds to the instant at which the minimum operating voltage is applied to the IC 11. Therefore, the IC 11 can be reliably reset. In addition, even if the power supply voltage is decreased, when the power supply voltage applied to the IC 11 becomes lower than the minimum operating voltage, the reset input terminal voltage V IN is quickly decreased. Therefore, a reliable reset operation can be ensured even if variations in voltage in a decreased state occur upon opening/closing of the switch S or mounting/dismounting of the battery 3. In the above-described embodiment, an FET is used as a switching circuit. Other types of transistors may be used. In addition, in an apparatus having a detachable power supply, such as a portable radio transceiver, a mounting/dismounting operation of the power supply can substitute for an ON/OFF operation of the above-described switch, as in the prior art. As has been described above, according to the present invention, when supply of power is interrupted by the switching circuit, and a voltage applied to the main circuit becomes equal to or lower than a predetermined value, supply of power to the reset circuit is stopped. Therefore, a resettable state can be easily ensured within a short period of time regardless of a power supply stabilizing circuit. At the same, a reset operation can be reliably performed without being influenced by variations in change state of the power supply voltage.

Claims: A power supply circuit including a power supply stabilizing circuit (Cll) receiving a power supply voltage from a power supply (3) for stabilizing the power supply voltage, a main circuit (10), receiving the power supply voltage without a substantial voltage drop connected in parallel with the power supply stabilizing circuit (C11) and a reset circuit (12) for outputting a reset signal via a potential divider (R 12 , R 11 ) to a reset input terminal (15) of the main circuit (10) when the power supply voltage rises, and there are provided reset circuit control means (18) connected to the power supply stabilizing circuit (C11), for interrupting the supply of power to the reset circuit (12) when the power supply voltage applied to the main circuit (10) decreases to a value not more than a predetermined value, characterized in that a resistance (R11) of the potential divider (R 12 , R 11 ) is connected to a fixed potential and is shunted by a capacitor (C12) of such value compared with the stabilizing circuit (C11) that the voltage falls relatively quickly (15c) at the reset input terminal (15) after interruption of power to the reset circuit (12), but of such value also that the reset voltage rises slowly enough (curve 15a) when the power supply voltage rises for the reset voltage to remain low for a long enough period (15a) for the internal state of the main circuit (10) to be reliably reset. A circuit as claimed in claim 1, wherein the power supply stabilizing circuit (C11) is a capacitor, and the reset circuit control means (18) interrupts the supply of power to the reset circuit (12) when the voltage of the capacitor decreases to a value not more than a predetermined value. A circuit as claimed in claim 1, wherein the reset circuit control means (18) includes a field effect transistor, which is incorporated in the same integrated circuit (IC 11) as that of the main circuit (10) which is connected to receive the power supply voltage and which operates to interrupt the supply of power to the reset circuit (12) when the power supply voltage drops below the predetermined value. A power supply circuit as claimed in claim 2 wherein the main circuit (10) connected to the power supply stabilizing circuit (C11) is initialized in response to a first signal changing from the low- to high-level states, the capacitor of the power supply stabilizing circuit (C11) is connected in parallel with the main circuit (10) between the power supply (3) and ground and receives the power supply voltage, the reset circuit (12) has a first predetermined time constant for outputting the first signal to the main circuit (10) when the stabilised power supply voltage rises, and the reset circuit control means (18), is connected to the power supply stabilizing circuit (C11) for interrupting the supply of power to the reset circuit (12) to produce the low-level state when the stabilized voltage applied to the main circuit (10) decreases to a value not more than a predetermined value after the supply of power is interrupted. A power supply circuit as claimed in claim 4 wherein the reset control means (18) causes the stabilized voltage to the reset circuit to be at the first level when the stabilized voltage applied to the main circuit (10) reaches a predetermined value. A circuit as claimed in either claim 4 or claim 5, wherein the first level is less than the said second level.

Inventors: KUDOH KAZUHIRO, KUDOH, KAZUHIRO, KUDOH, KAZUHIRO, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: H03K17
IPC codes: H03K17