Ferroelectric liquid crystal devices

Abstract: In a method of driving a ferroelectric liquid crystal display, a blanking pulse (41) of width 2t s followed, after a delay of n.t s (where n is an integer), by a writing pulse (43) of width t s and of opposite polarity to the blanking pulse are applied to successive row address lines at intervals of 2t s . Pairs of bipolar data pulses (49,50;52,53) of width t s are applied to column address lines so that the data pulses coincide with the blanking pulse applied to the ith row and the writing pulse applied to row i-(n+1)/2 for odd values of n and to row 1-(n+2)/2 for even values of n. The data pulse amplitude may be varied in order to obtain variable grey levels in the display.

Description: This invention relates to ferroelectric liquid crystal (FLC) devices, and particularly to a method and apparatus for driving the liquid crystal elements of such devices. A ferroelectric liquid crystal has a permanent electric dipole which interacts with the applied electric field. Hence, ferroelectric liquid crystal elements exhibit fast response times, which make them suitable for use in display, switching and information processing applications. In particular, FLC displays will provide important alphagraphic flat panel displays for office applications. The stimulus to which an FLC element responds is a dc field, and its response is a function of the applied voltage (V) and the length of time (t) for which the voltage is applied. The element is switched to one state by the application of a voltage of a given polarity across its electrodes, and is switched to the other state by the application thereto of a voltage of the opposite polarity. it is essential that an overall dc voltage shall not be applied across such an element for an appreciable period, so that the elements remain charge-balanced, thereby avoiding decomposition of the liquid crystal arterial. Pulsed operation of such elements has therefore been effected, with a pulse of one polarity being immediately followed by a pulse of the other polarity, so that there is no resultant dc polarisation. The liquid crystal elements are commonly arranged in matrix formation and are operated selectively by energising relevant row and column lines. Time-division multiplexing is effected by applying pulses cyclically to the row (strobe) lines in sequence and by applying pulses, in synchronism therewith, to the column (data) lines. It is known that the electronic waveforms used to drive a ferroelectric liquid crystal display (FLCD) affect greatly the contrast ratio and the frame time of such a display. Hence, these waveforms will have a great impact on the commercial exploitation of ferroelectric LCDs. Figure 1 of the accompanying drawings illustrates the waveforms occurring in one known FLCD drive scheme. Figure 1 (a) shows the waveform for one row of devices of the display. The waveform 1 comprises a positive pulse 2 of amplitude V s followed immediately by a negative pulse 3 of the same amplitude. After a delay 4, a further negative pulse 5 of amplitude V s is followed immediately by a positive pulse 6 of amplitude V s . Figure 1(b) shows a corresponding section of a "non-select" column waveform 7. That section comprises a positive pulse 8 of amplitude V D immediately followed by a negative pulse 9 and, after a delay 10, a negative pulse 11 immediately followed by a positive pulse 12. The pulses 9, 11 and 12 are all of amplitude V D . The pulses 8, 9, 11 and 12 are of the same width as, and are synchronised with, the pulses 2, 3, 5 and 6. Corresponding column waveform sections for the other rows will occur during the delay period 10. Alternatively, a corresponding section of a "select" column waveform 13 comprises pulses 14-17 of the opposite polarities to the pulses 8, 9, 11 and 12. This scheme uses two sets of bipolar pulses to achieve the desired switching and is, therefore, called a "four-slot" scheme. it is now known that that scheme gives rise to low contrast and long frame times. The frame time is given by the pulse width (t s1 ) x number of slots x number of rows in the display. The frame time can be halved by splitting the column electrodes in half and driving the resulting two sets of row electrodes in parallel. A much reduced frame time can be achieved by using a "two-slot" scheme as disclosed in our British Patent Publication No: 2,208,559A, which scheme is illustrated in Figure 2 of the present drawings. In this case the strobing (row) signal (Figure 2(a)) comprises a positive pulse 20 of amplitude V s , followed by a negative pulse 21 of amplitude V s ′, which is less than V s . This is the only pair of strobe pulses occurring during a frame period. The corresponding data (column) signal section comprises either a positive pulse 22 followed by a negative pulse 23 (Figure 2(b)) or a negative pulse 24 followed by a positive pulse 25 (Figure 2(c)), depending upon the data to be written. The pulses 22-25 are all of amplitude V D (not necessarily equal to V D of Figure 2). The width of each pulse is t s2 . Since the strobe pulses 20 and 21 are of different amplitudes, there would be a residual dc level applied to the addressed liquid crystal elements and, as stated above, this is undesirable. A small dc voltage V G is therefore applied to the strobe line between the end of the pulse 21 and the beginning of the pulse 20 of the next frame period. The required voltage V G is given by V G = V s - V s ′ N where N is the number of rows. Although the known scheme of Figure 2 can have half the frame time of the Figure 1 scheme, the contrast ratio achieved by the Figure 2 scheme is generally similar to that obtained by the Figure 1 scheme and can be low, for example ≦ 5:1. A further known scheme is illustrated in Figure 3 of the drawings. in this case the strobe signal 30 (Figure 3(a)) comprises a negative pulse 31 of amplitude V s and a positive pulse 32 also of amplitude V s . The corresponding "non-select" column signal section 33 (Figure 3(b)) comprises a negative pulse 34 occurring just before the pulse 31, immediately followed by a positive pulse 35 aligned with the pulse 31. A positive pulse 36 is then followed immediately by a negative pulse 37 aligned with the pulse 32. The "select" column signal section 38 (Figure 3(c)) comprises pulses 39-42 aligned with, but of opposite polarity to, the pulses 34-37, respectively. All of the pulses 34-37 and 39 to 42 are of amplitude V D (not necessarily equal to V D of Figure 1 or Figure 2),and each of these pulses, as well as each of the pulses 31 and 32, is of width t s3 . If the schemes of Figures 1, 2 and 3 are compared, it is found that t s1 ≈ t s2 > t s3 . The scheme of Figure 3 therefore operates with short pulse width and has the advantages of short switching times and high contrast ratio, but the disadvantage of being a four-slot scheme, which leads to a long frame time. The known schemes can therefore achieve either a high contrast ratio or a short frame time, but none can achieve both of these desirable features together. It is an object of the present invention to provide an improved method and apparatus for driving ferroelectric liquid crystal devices by which both a relatively high contrast ratio and a relatively short frame time can both be achieved. According to one aspect of the invention there is provided a method of driving, in a time-division multiplex mode, a display comprising a matrix of rows and columns of ferroelectric liquid crystal elements, wherein a blanking voltage pulse of amplitude V B and pulse width 2t s followed, after a delay of n x t s where n is an integer, by a writing voltage pulse of amplitude V W , of width t s and of opposite polarity to the blanking voltage pulse are applied to successive rows at intervals of 2t s ; and pairs of bipolar data pulses of amplitude |V D | selected from a range including zero and such that said data pulses coincide with the blanking pulse for the ith row and the writing pulse applied to row i -(n+1)/2 for odd values of n and to row i -(n+2)/2 for even values of n. According to another aspect of the invention there is provided apparatus for driving, in a time-division multiplex mode, a display comprising a matrix of rows and columns of ferroelectric liquid crystal elements, the apparatus comprising means to apply to successive rows of said elements at intervals of 2t s a blanking voltage pulse of amplitude V B and pulse width 2t s and, after a delay of n x t s where n is an integer, a writing voltage pulse of amplitude V w , of width t s and of opposite polarity to the blanking voltage pulse; and means to apply to column address lines pairs of bipolar data pulses of amplitude |V D | selected from a range including zero and each pulse being of pulse width t s , such that said data pulses coincide with the blanking pulse for the ith row and the writing pulse applied to row i -(n+1)/2 for odd values of n and to row i -(n+2)/2 for even values of n. Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which Figures 1, 2 and 3 illustrate known drive schemes as descrlbed above, Figure 4 illustrates waveforms occurring in a first scheme in accordance with the invention, Figure 5 illustrates waveforms occurring in an alternative scheme in accordance with the invention, Figure 6 illustrates waveforms resulting from the simultaneous application of blanking and data pulses, Figure 7 shows curves of minimum time slot length for proper switching of FLC elements against number of time slots between the blanking and data pulses, and Figure 8 shows a curve of light transmission through an FLC display against the amplitude V D of the pairs of bipolar data pulses. Referring to Figure 4 of the drawings, in a first drive scheme in accordance with the invention a strobe signal 40 (Figure 4 (a)) for an "ith" row comprises a positive blanking pulse 41 of width 2t s and amplitude V B followed by a delay period 42 of t s and then a negative write pulse 43 of width t s and amplitude V w . These pulses are repeated after a frame time given by 2t s x number of rows (N) + (n + 1)t s where n is the number of time slots. In the illustrated case n = 1. The pulses are offset by a dc level V G where V G is given by V G = 2V B - V w N For the "jth" row the strobe signal 44 (Figure 4(b)) comprises a pair of pulses 45, 46 identical to the pulses 41, 43, respectively, but delayed by a period 2t s relative to those pulses. The column "non select" signal 48 (Figure 4(c))for the ith row comprises a negative pulse 49 immediately followed by a positive pulse 50. The pulse 49 occurs in the period 42 between the blanking pulse 41 and the write pulse 43 for the ith row. The pulse 50 is aligned temporally with the write pulse 43. The "select" column signal 51 (Figure 4(d)) comprises pulses 52 and 53 identical in width and timing to, but of opposite polarity to, the pulses 49 and 50. All of the pulses 49, 50, 52 and 53 are preferably of amplitude |V D | and of duration t s ,as shown but,alternatively, the "select" pulses may be of different amplitude from the "non-select" pulses. A zero d.c. level might alternatively be used for either the "select" or the "non-select" signal. The driving signals of the present invention are characterised by a row blanking pulse of amplitude V B and width 2t s ; a writing pulse of width t s ; a spacing of n time slots, i.e. n x t s , where n is an integers ≧ 1, between the blanking pulse and the write pulse; and the write pulse for the ith row overlaps with the blanking pulse of the jth row, where j = i + (n+1)/2 for odd values of n and j = i +(n+2)/2 for even values of n. In the case of the Figure 4 embodiment, n = 1 i. e. the period 42 is t s , as mentioned above. Figure 5 illustrates the corresponding waveforms for n = 9, i.e. there is a delay of 9t s between the blanking pulse 54 and the write pulse 55 of the ith row line drive signal 56. As in Figure 4, the non-select column waveform (Figure 5(c)) comprises a negative pulse 57 followed by a positive pulse 58 temporally aligned with the write pulse 55. The select column waveform 59 (Figure 5(d)) comprises pulses 60, 61 of the opposite polarities to the pulses 57, 58, respectively. The strobe signal 62 (Figure 5(b)) for the (i+1)th row comprises a blanking pulse 63 having its leading edge coincident with the trailing edge of the pulse 54 and a negative write pulse 64 spaced from the pulse 63 by a period 9t s . There is therefore a time delay of 2t s between the pulses 55 and 64. in this embodiment, the frame time is given by (2t s x N) + 10t s . In the strobe signals 40 and 56 of Figures 4 and 5 the waveforms are offset by a dc voltage V G in order to account for the difference in blanking and write pulse amplitudes and widths, so as to avoid an overall dc unbalance, as explained previously. Figure 6 shows the effect of the application of the column "non-select" data pulses 49,50 (Figure 6(b)) for row i on the simultaneously-applied blanking pulse 45 for row j. The resultant waveform 60 is shown in Figure 6(c). Waveforms occurring for the column "select" data pulses 52,53 are shown in Figures 6(d),(e) and (f). It will be seen that the data pulses merely modify the shape of the waveform and do not alter the magnitude of the average voltage and, therefore, do not affect the effective drive voltage of the blanking pulse. Figure 7 shows two curves 67,68 of minimum acceptable pulse width against number of time slots (n) between the row blanking pulse and the write pulse, where n is in a range from 0 to 10 inclusive. The curve 67 relates to even numbers of time slots, whereas the curve 68 relates to odd numbers of time slots. It will be seen that both curves flatten out for increasing numbers of time slots, so that little improvement in pulse width reduction is achieved by increasing n beyond 9. Furthermore, it is found that better performance in terms of pulse width reduction is obtained by using an odd number of time slots rather than an even number. This is considered to be due to a disruptive influence produced by the trailing half of the bipolar data pulse which comes after the writing pulse for even values of n. The optimum values of V B , V W and V D will depend on the ferroelectric liquid crystal material and the cell technology employed. it is preferable that V B , V W and V D should be variable independently of each other. However, if 2V B = V D then V G " 0, i.e. no voltage offset is required. Furthermore, the use of voltage levels such that 4V D = 2V B = V W in a bilevel display with no grey levels can provide acceptable performance and has the significant advantage that only two variables i.e. V D ,V B or V W and t s need to be adjusted to drive the display rather than five variables, i.e. V D , V B , V W , V G and t s . Typical values for V D , V B , V w , t s and n for a 2µm ferroelectric liquid crystal display containing a ferroelectric liquid crystal known as SCE8 supplied by BDH Ltd., Poole, England are 10V, 20V, 40V, 80µs, and 9 respectively. This combination provides a contrast ratio of 8:1 and a frame time of 83.4ms for a display containing 516 lines. if the column electrodes are split and the rows are driven in parallel as two pairs of 256 lines, then the frame time can be reduced to 41.8ms. Similar contrast ratios and values of t s are achieved with the known scheme of Figure 3, but the frame time of the latter scheme is almost twice as long at 165.1ms. If 2V B ≠V W then a dc offset V G , given by V G = (2V B -V W )N, where N = the number of rows, should be applied. Alternatively, the polarities of V B and V W can be reversed at every frame, thereby cancelling any dc affects. The latter is less desirable, because it can lead to reduced contrast ratios, for example when the blanking pulse V B produces a bright state and the pixel is to be 'written' into a dark state. Furthermore,in order to avoid similar problems, it is preferable that the blanking pulse V B always produces a dark state rather than a light state in the instances when 2V B = V W or when an offset voltage V G is employed. Figure 8 shows a graph of light transmission through a written pixel of the FLC display for varying values of |V D |, the amplitude of the bipolar data pulses. The variation in light transmission enables a number of grey levels to be produced in the display. For example, the maximum contrast ratio of 18.8 shown in Figure 8 would allow nine grey levels to be obtained by selecting values of |V D |, where the contrast ratio increases by a factor of √2 from one grey level to the next. The addressing schemes in accordance with the present invention, such as those illustrated in Figures 4 and 5 and described herein, provide high contrast ratios and short slot times. In addition, due to their advantage of being two-slot schemes, they produce short frame times. Each of these factors is advantageous to the commercial exploitation of a ferroelectric liquid crystal display.

Claims: A method of driving, in a time-division multiplex mode, a display comprising a matrix of rows and columns of ferroelectric liquid crystal elements, wherein a blanking voltage pulse (41) of amplitude V B and pulse width 2t s followed, after a delay of n x t s where n is an integer, by a writing voltage pulse (43) of amplitude V W , of width t s and of opposite polarity to the blanking voltage pulse are applied to successive rows at intervals of 2t s ; and pairs of bipolar data pulses (49,50;52,53) of amplitude |V D | selected from a range including zero and each pulse being of pulse width t s are applied to column address lines such that said data pulses coincide with the blanking pulse for the ith row and the writing pulse applied to row i -(n+1)/2 for odd values of n and to row i - (n+2)/2 for even values of n. A method as claimed in Claim 1, wherein n is an odd integer. A method as claimed in Claim 2, wherein n is an odd integer from one to nine. A method as claimed in Claim 1, wherein n is an even integer. A method as claimed in Claim 4, wherein n is an even integer from zero to ten. A method as claimed in any preceding claim, wherein the polarities of the blanking pulse (41) and the writing pulse (43) are reversed for alternate frames of operation of the display. A method as claimed in Claim 1, wherein an offset dc voltage of magnitude V G is applied with said blanking and writing pulses such that V G = (2V B - V W )/N where N is the number of rows A method as claimed in any preceding claim, wherein the amplitudes V D , V B and V W of the data, blanking and writing pulses (49,50; 52,53; 41:43), respectively, are related by 4V D = 2 V B = V W for use in a bilevel display with no grey levels. A method as claimed in any one of Claims 1-7, wherein V D is variable such that various shades of grey are obtained. A ferroelectric liquid crystal display arranged to operate by a method as claimed in any preceding claim. Apparatus for driving, in a time-division multiplex mode, a display comprising a matrix of rows and columns of ferroelectric liquid crystal elements, the apparatus comprising means to apply to successive rows of said elements at intervals of 2t s a blanking voltage pulse (41) of amplitude V B and pulse widths t s and, after a delay of n x t s where n is an integer, a writing voltage pulse (43) of amplitude V W , of width t s and of opposite polarity to the blanking voltage pulse; and means to apply to column address lines pairs of bipolar data pulses (49,50; 52,53) of amplitude |V D | selected from a range including zero and each pulse being of pulse width t s , such that said data pulses coincide with the blanking pulse for the ith row and the writing pulse applied to row i -(n+1)/2 for odd values of n and to row i -(n+2)/2 for even values of n. Apparatus as claimed in Claim 11, comprising means to apply to said ith row with said blanking and writing pulses an offset dc voltage of magnitude V G such that V G = (2V B - V W )/N where N is the number of rows Apparatus as claimed in Claim 11, wherein the means to apply said blanking pulse and said writing pulse is operative to reverse the polarities of said pulses for alternate frames of operation of the display.

Inventors: LISTER STEPHEN JOSEPH SHELFORD, MOSLEY ALAN, YEOH COLIN TECK HOOI, LISTER, STEPHEN JOSEPH SHELFORD, MOSLEY, ALAN, YEOH, COLIN TECK HOOI
Applicants: GEC MARCONI HOLDINGS, GEC-MARCONI (HOLDINGS) LIMITED
Application year: 1991
Main classification: G09G3
IPC codes: G02F1, G09G3