Method for producing a semiconductor device including a bipolar transistor

Abstract: A semiconductor device including a bipolar transistor, has a collector region including a first semiconductor region of the first electroconduction type and a second semiconductor region of the first electroconduction type having higher resistance than the first semiconductor region, a base region including a semiconductor region of the second electroconduction type, and an emitter region including a semiconductor region of the first electroconduction type. The semiconductor device further comprises a metal layer region for connecting the first semiconductor region and the collector electrode on the collector region provided within the second semiconductor region layer of the collector region.

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention generally relates to a method for producing a semiconductor device such as memory, photoelectric converting device, signal processing device to be mounted on various electronic instruments, more particularly to a method for producing a semiconductor device including a bipolar transistor having a specific feature in the formation of its electrode structure. Related Background Art To describe the prior art, as an example, the vertical PNP (hereinafter abbreviated as V-PNP) transistor which is used in recent years as the functional device for highly integrated semiconductor device may be mentioned. For example, one having the structure shown in Fig. 1 has been known. In Fig. 1, the symbol l is a P-type silicon substrate. On the P-type silicon substrate 1 is formed an N + buried layer 2, and on the N + buried layer 2 is formed a collector region 5 comprising a P + buried layer 3 and a P - well layer 4. Within the P - well layer 4 of the collector region 5 is formed an N - well layer 6, and further within the N - well layer 6 are formed a P + layer 7 and an N + layer 8 made apart from each other. Within the P - well layer 4 of the collector region 5 is formed a P + layer 9 apart from the N - well layer 6. And, on the P + layer 7, the N + layer 8 within the N - well layer 6 and the P + layer 9 within the P - well layer 4 are respectively formed an emitter electrode 10, a base electrode 11 and a collector electrode 12. Around the collector region 5 as mentioned above, an N - epitaxial layer 13 is formed. In the V-PNP transistor with such structure, when the transistor actuation enters saturation region (stage), current may be sometimes leaked from the collector region 5 through the N - epitaxial layer 13 into the P-type silicon substrate 1, thereby forming a parasitic PNP transistor. For this reason, as shown in Fig. 2, there has been also known a transistor which has been made to have a constitution having a deep N + layer 14 in contact with the N + layer 2 and surrounding the collector region 5 formed within the N - epitaxial layer 13, and further in which the emitter grounding current amplification β of the parasitic PNP transistor is reduced by biasing to the maximum potential, whereby the leak current to the P-type silicon substrate 1 can be reduced. The guard ring electrode 15 of the transistor is taken out from the N + buried layer 2 through the N + layer 14. However, in the transistor of the type shown in Fig. 1 and Fig. 2, the current from the emitter electrode 10 flows into the P - well layer of the collector region 5 and the P + buried layer 3, wherefrom it is taken out through the P + layer 9 on the transistor surface at the collector electrode 12, and therefore the resistance of the P - well layer 4 becomes larger, thus involving the drawback that the collector series resistance becomes larger as a whole. Further, when the collector series resistance becomes larger, the emitter grounding current amplification β of large current region becomes lower, while when collector region 5 is taken larger, there will occur an inconvenience that the device size becomes larger. In the transistor shown in Fig. 2, because the N + layer 14 is required to be provided within the N - (epitaxial) layer 13 around the collector region 5, the margins of the collector region 5 and the device separation region 16 are required to be taken sufficiently large due to the influence of lateral spreading of the diffusion layer, and therefore the device size become large also in this case, and yet the junction capacity with the N + layer 14 of the collector region 5 will be increased. It has been known to provide a contact hole and a filling metal interconnect between a buried collector semiconductor layer and surface wiring, as a means of reducing collector series resistance. DE-A-2621165 discloses such a process performed by steps of: forming a collector region of a first conductivity type; forming a semiconductor region of a second conductivity type on the collector region for defining a base region; forming a further semiconductor region of a first conductivity type on the base region for defining an emitter region; forming an insulating film on the whole upper surface of the device; forming a groove in the collector region by etching a portion of the insulating film located over the collector region and the underlying portion of the collector region to form a groove having a depth equal to or greater than its width; forming a collector electrode mainly of Al by deposition from a vapor phase so as to fill the groove; forming base and emitter contact holes in the insulating film by etching portions of the insulating film located on the base region and the emitter region, respectively; forming base and emitter electrode layers by deposition of a metal from a vapour phase in the base and emitter contact holes; and forming emitter, base and collector wirings by non-selective deposition on the whole surface of the device, and patterning, of a metallic film. In the aforesaid process, as described in detail, the collector contact hole and a trench isolation moat are filled with aluminium in a common evaporation step. Surplus aluminium metal, on the substrate insulator surface, is then removed prior to subsequent processing. The base and emitter electrode layers and the metallisation layer for forming the emitter, base, and collector wirings are formed in the same evaporation step. The method of the present invention, as defined in claim 1 appended, also has as its object the reduction of collector series resistance. Also since the width of the collector electrode can be made small, by comparison with the equivalent doped semiconductor interconnection diffusion, previously discussed, it is well suited to high density integration. Of particular note, in the method of the present invention, the collector electrode is formed by a selective deposition process i.e. a process in which the electrode material, mainly of aluminium, is deposited selectively on semiconductor and not on insulation material, and, as deposition continues, the electrode material is grown on the electrode material already deposited. Since this deposition is selective, no surplus material is grown on the insulator surface and the step of etch removal, previously necessary as in DE-A-2621165, is obviated. Since, in the present invention, the collector electrode material is grown from semiconductor material exposed at the foot of the collector contact hole, the bottom portion of the contact hole is filled first. The contact hole can thus be filled effectively even for large aspect ratio of hole depth H to hole width W, H/W ≥ 1, especially H/W ≥ 3, which is optimum for high density integration. Where the collector electrode is of aluminium as such the non-selective deposition of aluminium from one of monomethylaluminium hydride and dimethylaluminium hydride, diluted with hydrogen, can be performed so that the aluminium that is deposited and grown is of good quality, in particular is single crystal. It is acknowledged that it has been known to metallize a semiconductor device with conductive material mainly of Al, specifically silicon/aluminium alloy coating material. US 4,328,261 discloses a method in which the surface of a silicon process wafer is exposed to silane and an aluminium alkyl vapour. The various alkyls, which may be employed in this process, include tri-methyl, tri-ethyl or tri-isopropyl aluminium, tri-isobutyl aluminium, di-isobutyl aluminium, or mixtures thereof. These may be used diluted with argon and/or hydrogen. It is also acknowledged that it has been known to form aluminium thin films by photo CVD using dimethylaluminium hydride as a source gas, without any dilution, and a deuterium lamp as light source, see Japanese Journal of Applied Physics, Part 2, vol. 27, no. 8, August 1988, pp. L1392-4. In the accompanying drawings: Fig. 1 is a schematic sectional view showing an example of the bipolar transistor of the prior art. Fig. 2 is a schematic sectional view showing another example of the bipolar transistor of the prior art. Fig. 3 is a schematic sectional view showing a bipolar transistor for explaining the present invention. Figs. 4A to 4I are schematic sectional views for illustration of the preparation method of the semiconductor device according to the present invention. Fig. 5 is a schematic sectional view showing another bipolar transistor for explaining the present invention. Figs. 6, 7 are schematic views showing one example of the film forming apparatus to be used for practicing the method according to the present invention. Fig. 8 is a schematic plan constitutional view of the apparatus shown in Figs. 6 and 7. Fig. 9 is a schematic constitutional view of the movement order of the substrate in Fig. 8 added with arrowheads. Figs. 10A to 10D are schematic views for explaining the method according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following, preferred embodiments of the present invention are described. An electrode structure of a semiconductor device produced by the method of the present invention is an electrode region comprising a metal region mainly of Al with an aspect ratio H/W ≥ 1 buried within the semiconductor substrate. Said electrode structure forms a part of the electrode wiring internally of the semiconductor substrate in the sense of series resistance reduction. Particularly, great effects will be exhibited. Since it is utilized for the collector electrode of a bipolar transistor, above all V-PNP transistor. Fig. 3 is a schematic sectional view showing a V-PNP transistor as an example for explaining the present invention. In Fig. 3, the same symbols are attached to the same constitutional portions as in the V-PNP transistor of the prior art shown in Figs. 9 and 10, and description thereof is omitted. In Fig. 3, the symbol 20 is a first electrode layer comprising a metal as the electroconductive material. Here, W ≤ H, with H/W being 1.0 or higher, preferably 2.0 or higher, optimally 3.0 or higher, whereby the area occupied by the collector electrode can be made smaller. The first electrode layer 20 connects the P + buried layer 3 in the collector region 5 to the collector wiring 12, and is formed here along the direction crossed at right angle as the crosslinking direction relative to the surface of the P-type silicon substrate 1 within the P - well layer 4 of the collector region 5 between the P + buried layer 3 and the collector wiring 12 and the interlayer insulation film 18. The P - well layer 4 has higher resistance than the P + buried layer. In the present transistor, because the first wiring layer is in direct ohmic contact with the P + buried layer 3, no impurity layer corresponding to the P + layer 9 in the transistor of the prior art shown in Figs.1 and 2 is formed. As the electroconductive material for forming such first electrode layer 20, pure aluminum or an aluminum composed mainly of Al, e.g. containing silicon as a metal (Al-Si), is employed. Al is inexpensive, has high electroconductivity, and also can form a dense oxidized film on the surface, thereby having a number of advantages such that the inner portion is chemically protected to be stabilized and has good adhesion with Si, and therefore it can be used when connecting well the P + buried layer 3 to, for example, a collector wiring 12 comprising Al. Thus, when the metal buried electrode is electrically connected to a predetermined portion only at the bottom of the groove, the whole side wall surface should be preferably covered with an insulation film. On the other hand, when the metal buried electrode is insulated from a part of the side wall or the bottom of the groove, only said portion is covered with an insulation film. Next, by referring to Fig. 4A to Fig. 4I, an embodiment of the present invention is described. 1) First, for example, on the surface of a P-type silicon substrate 1 having an impurity concentration of 10 14 to 10 15 /cm 3 , a thermally oxidized film 30 comprising SiO 2 for diffusion mask, etc. is formed with a thickness of, for example, 0.8 to 1.0 mm, and the by patterning of the thermally oxidized film 30, openings 31 with predetermined sizes, shapes are formed. Next, with the thermally oxidized film 30 as the mask, an N-type impurity such as Sb (antimony) or As (arsenic) is introduced according to the ion injection method in the surface of the P-type silicon substrate 1 through the openings 31 of the thermally oxidized film 30, heat treatment is carried out to activate the N-type impurity simultaneously with diffusion thereof internally of the P-type silicon substrate 1. Thus, for example, an N + buried layer 2 with a sheet resistance 40 to 120 Ω/□ is formed (Fig. 4A). 2) Next, after removal of the thermally oxidized film 30 as described above, a thermally oxidized film 32 comprising another SiO 2 , etc. is formed with a thickness of, for example, 10 to 100 nm (100 to 1000) Å). Resist patterning is effected on the thermally oxidized film 32. After incorporation of a P-type impurity of B (boron) into the N + buried layer 2 and the region surrounding outside of the N + buried layer B through the openings of the resist, heat treatment is applied after removal of the resist. By such heat treatment, the impurity as described above is activated simultaneously with diffusion internally of the substrate 1. Thus, P + layers 33, 34 of, for example, 200 to 1000 Ω/□ are formed (Fig. 4B). 3) Next, after removal of all the oxidized films on the silicon substrate 1, an N-type epitaxial layer 13 is grown. The N-type epitaxial layer 13 should desirably have its thickness of about 1 to 5 µm, and a specific resistance of about 1 to 20 Ω/cm. In such epitaxial growth, the impurity is diffused into the N-type epitaxial layer 13 from the P + layers 33, 34. Particularly, from the N + buried layer 2 (P + layer 33), the N-type and P-type impurities are diffused into the N-type epitaxial layer 13. However, since the P-type impurity with greater coefficient of diffusion is diffused at higher diffusion speed, a P + buried layer 3 will be formed on the N + buried layer 2 (Fig. 4C). 4) Next, a thermally oxidized film is formed on the surface of the N-type epitaxial layer as described above, the thermally oxidized film is subjected to patterning to form openings. After introduction of a P-type impurity such as B into the surface of the N-type epitaxial layer 13 according to ion injection through the openings with the thermally oxidized film as the mask, heat treatment is effected to have the impurity diffused internally of the N-type epitaxial layer 13. By such ion injection method and heat treatment, a P - well layer 4 is formed on the P + buried layer 3 (Fig. 4D). The well layer 4 should desirably have a sheet resistance of about 2 to 10 kΩ/□. 5) Next, after removal of the thermally oxidized film from above the N-type epitaxial layer 13, a thermally oxidised film with a thickness of 10 to 100 nm (100 to 1000 Å) and a non-oxidizable film comprising Si 3 N 4 , etc. with a thickness of 100 to 200 nm (1000 to 2000Å) are successively laminated. Next, on the laminated film, patterning is applied to form openings for device separation region as described below. And, according to the selective oxidation by use of the laminated film as the oxidation resistant mask, a field oxidized film region 17 for device separation (thickness 0.8 to 1.0 µm) and a device region for bipolar region are formed, and then the laminate film as described above is removed (Fig. 4E). 6) Next, a thermally oxidized film with a thickness of 20 to 100 nm (200 to 1000 Å) is formed on the N + type epitaxial layer 13 in the device region, the thermally oxidized film is applied with resist patterning to form openings for base formation of the bipolar transistor. Then, after introduction of an N-type impurity through the openings, the thermally oxidized film is removed and then heat treatment is effected. By doing so, a N - well layer (base) 6 is formed within the P - well layer 4. The formation conditions of the base layer 6, which depend on the characteristics of the bipolar transistor to be prepared, should desirably be made to have a sheet resistance of about 0.6 to 3 kΩ/□. (Fig. 4F). 7) Next, on the surface of the device region, a thermally oxidized film is formed, and the thermally oxidized film is applied with resist patterning to form openings at the positions corresponding to the N - well layer (base) 6 of the thermally oxidized film, namely the emitter formation region of the resist and the PN device separation region. Next, after introduction of a P-type impurity such as B, BF 2 etc. through these openings, the thermally oxidized film as the resist is removed. Next, a thermally oxidized film is formed on the surface of the N - well layer (base) 6, the thermally oxidized film is applied with resist patterning to form openings for formation of the N + layer of the base contact. Next, after formation of an N-type impurity such as As, etc. though the openings according to the ion injection method, a thermally oxidized film as the resist is formed.Then, the P-type impurity is activated and diffused by application of heat treatment to form the P + layer 7 and the N + layer 8 separately from each other at the upper portion of the N - well layer (base) 6 (Fig. 4G).The ion injection conditions of the P-type impurity in this step and subsequent heat treatment conditions are determined depending on the characteristics of the bipolar transistor to be prepared. 8) Next, on the whole surface of the device region and the device separation, for example, BPSG (Boro-phospho silicate glass), etc. is deposited to a thickness of about 0.6 to 1.0 µm according to the CVD method, annealing is applied to form an interlayer insulation film 18. 9) Next, a thermally oxidized film is formed on the interlayer insulation film 18, and the thermally oxidized film is applied with resist patterning to form openings for contact hole. Subsequently, through the openings the interlayer insulation film 18 and the P - well layer 4 are applied with etching in two steps to form collector contact holes reaching the surface of the P + buried layer 3, and then the thermally oxidized film as the resist is removed. Then, a first electrode region 20 comprising an Al film or an Al-Si film is formed according to the Al-CVD method as described below (Fig. 4H). 10) Next, on the surface of the device region is formed a thermally oxidized film, which thermally oxidized film is applied with patterning to form resist openings for formation of contact holes for base and emitter. Next, through these openings, etching is applied on the interlayer insulation film 18 to form base contact holes and emitter contact holes, respectively. Subsequently, within these base contact holes and emitter contact holes, electrode layers 21 and 22 comprising an Al film or an Al-Si film are again formed so as to be coplanar with the interlayer insulation film 18 according to the Al-CVD method as described below. Next, an Al film or Al-Si film is formed with a thickness of 0.5 to 1.0 µm on the whole surface of the device region according of a non-selective CVD method or sputtering method, and by application of patterning to the Al film, etc., the respective electrodes of emitter electrode 10, base electrode 11, collector electrode 12 and the wirings accompanying these are formed to prepare desired V-PNP (Fig. 4I). As shown in Fig. 4H, the first electrode region 20 is grown so as to be coplanar with the interlayer insulation film 18 according to the Al-CVD method, but it is also possible to stop once the selective growth at the stage when the first wiring layer 20 has been grown to coplanar with the P - well layer 4, and effect selective growth by initiating again the Al-CVD method after formation of the base and emitter contact holes as described above, thereby making the respective upper surface of the first electrode region 20 and the electrode layers 21, 22 coplanar. In a V-PNP transistor thus constituted, since the first electrode region 20 is provided, the collector series resistance of the P - well layer 4 can be reduced to great extent, and therefore reduction of the emitter grounding current amplitude β of the large current region, namely the present transistor can be ameliorated. Fig. 5 is a schematic sectional view showing another bipolar transistor for explaining the present invention. Also in Fig. 5, the same constituent portions as those of the V-PNP transistor of the prior art showing Figs. 1, 2 are attached with the same symbols, and description there of is omitted. The present invention can be suitably used for the second wiring layer comprising an electroconductive material shown by the symbol 24 in Fig. 5. The second electrode region 24 connects the guard ring electrode 15 on the interlayer insulation film 17 to the N + buried layer 2, and is formed along the direction crossing at right angle to the surface of the P-type silicon substrate 1 so as to extend through the N - epitaxial layer 13 surrounding the collector region 5 and the interlayer insulation film 18. As the electroconductive material forming the second electrode region 24, the same kind as that forming the first electrode material region 20 as described above can be used. And, when forming both of the electrode regions 20, 24, for example, after formation of necessary contact holes according to such steps as resist patterning, etching, etc., the both electrode regions 20, 24 can be formed at the same time according to the Al-CVD method used in the method according to the present invention. In a V-PNP transistor thus constituted, since the second electrode region 24 is provided, even a parasitic PNP transistor may be constituted at the saturation step as the transistor actuation, the emitter grounding current amplification β of the parasitic PNP transistor can be reduced, and also the leak current to the P-type silicon substrate 1 reduced by biasing to the maximum potential. And, in the V-PNP transistor, as different from the structure of the V-PNP transistor of the prior art shown in Fig. 1, the second electrode region 24 is provided comprising e.g. Al instead of the deep N + layer 14, and therefore no diffusion of the dopant from the N + layer 14 is required to be considered. Hence, no great margin of the collector region 5 and the device separation region 16 is required to be taken, whereby the device size can be made smaller and also the junction capacity of the collector region 5 can be made smaller. For the formation of the first electrode layer 20 or the second electrode layer 24 described above, the Al-CVD method as described below is used. According to this Al-CVD method, fine working can be suitably effected not only for an aspect ratio of 1.0 or higher as a matter of course, but also for 2.0 or higher, or 3.0 or higher. Referring now to specific examples, the present invention is described in detail. [Experimental example 1] In the following manner, a V-PVP transistor with the constitution shown in Fig. 3 was prepared. First, on the surface of a P-type silicon substrate having an impurity concentration of 10 14 to 10 15 /cm 3 was formed a thermally oxidized film comprising SiO 2 , etc. for diffusion mask with a thickness of 0.8 to 1.0 µm, and the thermally oxidized film was subjected to patterning to form openings with predetermined sizes, shapes on the thermally oxidized film. Subsequently, after introduction of an N-type impurity such as Sb (antimony) or As (arsenic) into the P-type silicon substrate through the openings 31 according to the ion injection method, heat treatment was effected to activate the N-type impurity simultaneously with diffusion internally of the P-type silicon substrate. Thus, an N + buried layer of 40 to 120 Ω/□ was formed. Next, after removal of the thermal fixed film as described, another thermal oxidized film comprising SiO 2 , etc. was formed with a thickness of about 10 to 1000 nm (100 to 10000 Å). On the thermally fixed film was applied resist patterning, and after introduction of a P-type impurity of B (boron) in the N + buried layer and the region surrounding the outside of the N + buried layer through the openings of the resist, heat treatment was applied after removal of the resist. By such heat treatment, the above-mentioned impurity was activated simultaneously with diffusion internally of the silicon substrate. Thus, a P + layer of 200 to 1000 Ω/□ was formed. As the next step, all of the oxidized films on the silicon substrate were removed, and then an N-type epitaxial layer was grown. The N-type epitaxial layer had a thickness of about 1 to 5 µm and a specific resistance of about 1 to 20 Ω/cm. By such epitaxial growth, a P + -type buried layer was formed on the N + buried layer. Next, on the surface of the N - epitaxial layer, a thermally oxidized film was formed, the thermally oxidized film was subjected to patterning to form openings, and after introduction of a P-type impurity such as B, etc. into the N - epitaxial layer surface with the thermally oxidized film as the mask through its openings according to the ion injection method, heat treatment was effected to have the impurity diffused internally of the N - epitaxial layer. By doing so, a P - well layer was formed on the P + buried layer. The P - well layer had a sheet resistance of 2 to 10 kΩ/□. Next, after removal of the thermally oxidized film from above the N - epitaxial layer, again a thermally oxidized film with a thickness of 100 to 10000 nm (100 to 10000 Å) and a non-oxidizable film comprising Si 3 N 4 , etc. with a thickness of 100 to 200 nm (1000 to 2000 Å) were successively laminated. Then, the laminated film was applied with patterning to form openings for device separation region as described below. And, by the selective oxidation by use of the laminated film as oxidation resistant mask, the field insulation film region for device separation (thickness 0.8 to 1.0 µm) and the device region for bipolar transistor were formed, followed by removal of the laminated film. Subsequently, on the surface of the N - epitaxial layer in the device region, a thermally oxidized film with a thickness of 20 to 1000 nm (200 to 10000 Å) was again formed, which thermally oxidized film was applied with resist patterning to form openings for base formation of bipolar transistor. Then, after introduction of an N-type impurity through the openings according to the ion injection method, the thermally oxidized film as the resist was removed, following by heat treatment. By doing so, an N - well layer (base) was formed within the P - well layer. The base layer had a sheet resistance of about 0.6 to 3 kΩ/□. Next, on the surface of the device region a thermally oxidized film was formed, and the thermally oxidized film was applied with resist patterning to form openings at the positions corresponding to the N - well layer (base), namely the emitter formation region and the PN device separation region. Then, after introduction of a P-type impurity such as B, BF 2 , etc. through these openings according to the ion injection method, the thermally oxidized film as the resist was removed. Subsequently, a thermally oxidized film was formed on the N - well layer (base), and the thermally oxidized film was applied with resist patterning to form openings for formation of the N + layer for base contact. Then, after introduction of an N-type impurity such as As, etc., the thermally oxidized film as the resist was removed. Then, the P-type and N-type impurities were activated, diffused by application of heat treatment to form the P + layer and the N + layer separate from each other on the upper part of the N - well layer (base). As the next step, after growth of BPSG, etc. on the whole surface of the device region and the device region to a thickness of 0.6 to 1.0 µm according to the CVD method, annealing was applied to form an interlayer insulation film. Next, a thermally oxidized film was formed on the interlayer insulation film, and the thermally oxidized film was applied with resist patterning to form openings for collector contact hole. Subsequently, after formation of the interlayer insulation film and the P - well layer through the openings, etching was applied in two steps to form contact holes reaching the P + buried layer surface, followed by removal of the thermally oxidized film as the resist. Next, within the collector contact holes, a first electrode region comprising an Al film was formed by use of dimethylaluminium hydride (DMAH) and hydrogen while maintaining the substrate surface temperature at 270°C. The first electrode region was permitted to grow until its surface became coplanar with the interlayer insulation film surface. Next, a thermally oxidized film was formed on the surface of the device region, and the thermally oxidized film was applied with patterning to form resist openings for formation of contact holes for base and emitter. Subsequently, through these openings, the interlayer insulation film was applied with etching to form base contact holes and emitter contact holes, respectively. Then, within these base contact holes and emitter contact holes, respective electrode regions comprising Al film were formed according to the Al-CVD method. Next, according to the sputtering method, an Al film was formed with a thickness of about 0.5 to 1.0 µm, and the Al film was applied with patterning to form a desired V-PNP transistor having the respective electrodes such as emitter electrode, base electrode, collector electrode, etc. and the wirings accompanied with these formed thereon. In the V-PNP transistor thus prepared, reduction of the emitter grounding current amplification β could be ameliorated. [Second Experimental Example] A V-PNP transistor with the constitution shown in Fig. 5 was prepared. The preparation steps are the same as those in the first Example as described above up to the steps before formation of the first electrode region according to the Al-CVD method. In the present Example, the first electrode region and the second electrode region were formed at the same time according to the Al-CVD method. In the V-PNP transistor thus prepared reduction of the emitter grounding current amplification β could be ameliorated, and further the β of the parasitic transistor could be reduced. As described above, according to the present Example, the collector series resistance of the P - well layer of the collector region can be reduced to great extent by the first electrode region for connecting the surface electrode for collector and the P + buried region of the collector region, whereby reduction of the emitter grounding current amplification β of the bipolar transistor can be ameliorated, and also the frequency characteristic can be improved. Also, in addition to the first electrode region as described above, by the second electrode region connecting the electrode for guard ring on the N - epitaxial layer and the N + buried layer, the β of the parasitic transistor can be reduced, and also the leak current to the substrate can be reduced, even if the maximum potential may be biases without enlargement of the device size. Further, improvement of frequency characteristic can be effected, because the junction capacity of the collector region can be made smaller. The film forming method used in the method of the present invention is to form a deposited film by the surface reaction on an electron-donative substrate by use of a gas of an alkylaluminum hydride selected from monomethylaluminium hydride and dimethylaluminium hydride, and hydrogen (hereinafter called the Al-CVD method). By use of monomethylaluminum hydride (MMAH) as the starting gas or dimethylaluminum hydride (DMAH) as the starting gas, and H 2 gas as the reactive gas, and heating the substrate surface under the mixture of these gases, an Al film of good quality can be deposited. Here, during the selective deposition of Al, it is preferable to maintain the surface temperature at the decomposition temperature of the alkylaluminum hydride or higher and less than 450°C, more preferably 260°C to 440°C. As the method for heating the substrate to the above-mentioned temperature range, there are direct heating and indirect heating. Particularly, by maintaining the substrate at the above-mentioned temperature by direct heating, an Al film of good quality can be formed at high deposition speed. For example, when the substrate surface temperature during Al film formation is made 260 °C to 440 °C which is more preferable temperature range, a film of good quality can be obtained at higher deposition speed of (30 to 500 nm/min) (300Å to 5000Å/min.) which is higher than in the case of resistance heating. As such direct heating method (substrate itself is heated by direct transmission of the energy from the heating means to the substrate), for example, lamp heating by means of halogen lamp, xenon lamp, etc. may be included. As the method for indirect heating, there is resistance heating, by which heating can be performed by use of a heat-generating body, etc. provided at the substrate supporting member for supporting the substrate to form deposited film arranged in the space for formation of the deposited film. By applying the CVD method to the substrate having the electron-donative surface portion and the non-electron donative surface portion co-present thereon, a single crystal of Al can be formed under good selectivity only on the electron-donative substrate surface portion. The Al thus formed will have all of excellent characteristics desirable for the electrode/wiring material. That is, reduction of generation probability of hillock, reduction of generation probability of alloy spike will be accomplished. This may be considered to be due to the fact that substantially no or extremely small formation of alloy spike, etc. on account of the eutectic reaction with the subbing silicon, etc. is seen, because Al of good quality can be formed on the surface comprising a semiconductor or an electroconductive member as the electron-donative surface, and also the Al is excellent in crystallinity. And, when employed for the electrode of a semiconductor device, an effect surpassing the concept of the Al electrode which has been contemplated in the prior art, and could not be even expected in the prior art can be obtained. Having described above about the fact that the Al deposited on an electron-donative surface, for example, within the opening with the semiconductor substrate surface exposed becomes to have a single crystalline structure, according to the Al-CVD method, a metal film composed mainly of Al as described below can be also selectively deposited, and its film quantity also exhibits excellent characteristics. For example, in addition to said gas of an alkylaluminum hydride selected from MMAH and DMAH, and hydrogen, a gas containing Si atoms such as SiH 4 , Si 2 H 6 , Si 3 H 8 , Si(CH 3 ) 4 , SiCl 4 , SiH 2 Cl 2 , SiHCl 3 , or the like, a gas containing Ti atoms such as TiCl 4 , TiBr 4 , Ti(CH 3 ) 4 , etc., a gas containing Cu atoms such as copper bisacetylacetonate Cu(C 5 H 7 O 2 ), copper bisdipivaloylmethanite Cu(C 11 H 19 O 2 ) 2 , copper bishexafluoroacetylacetonate Cu(C 5 HF 6 O 2 ) 2 , etc., may be introduced in a preferable combination to form a gas mixture atmosphere, thereby forming an electrode by selective deposition of an electroconductive material such as Al-Si, Al-Ti, Al-Cu, Al-Si-Ti, Al-Si-Cu. The Al-CVD method as described above is a film forming method excellent in selectivity, and also the surface characteristic of the film formed has good surface characteristic. Hence, by application of a non-selective film forming method to the next deposition step, Al or a metal film composed mainly of Al can be also formed on the Al film selectively deposited as described above and SiO 2 , etc. as the insulating film, whereby a preferable metal film having high useability for general purpose as the wiring of semiconductor device can be obtained. Specific examples of such metal film include the following. There may be included combinations of Al, Al-Si, Al-Ti, Al-Cu, Al-Si-Ti, Al-Si-Cu, deposited selectively with Al, Al-Si, Al-Ti, Al-Cu, Al-Si-Ti, Al-Si-Cu. As the film forming method for non-selective deposition, there are other CVD methods than the Al-CVD method as described above, such as the sputtering method. Next, a preferable film forming apparatus for carrying out the method according to the present invention is described. Fig. 6 to Fig. 8 show schematically a sequential metal film forming apparatus preferable for applying the film forming method as described above. The sequential metal film forming apparatus, as shown in Fig. 6, is constituted of loadlock chamber 311 connected mutually communicated under shielding from outer air through the gate valves 310a to 310f, a CVD reaction chamber 312 as the first film forming chamber, an Rf etching chamber 313, a sputtering chamber 314 as the second film forming chamber and a loadlock chamber 315, and the respective chambers are constituted reducible in pressure by evacuation with the evacuation systems 316a to 316e. Here, the above loadlock chamber 311 is a chamber for replacing the substrate atmosphere before deposition treatment with H 2 atmosphere after evacuation in order to improve the throughput characteristic. The next CVD reaction chamber 312 is a chamber for selective deposition on the substrate according to the Al-CVD method as described above under normal pressure or reduced pressure, in which a substrate holder 318 having a heat-generating member 317 which can heat the substrate to be formed to a range of 200 °C to 450 °C is provided internally, and starting gases such as alkylaluminum hydride bubbled and gasified in the bubbler 319-1 are introduced into the chamber through the starting gas introducing line 319 for CVD, and also hydrogen gas as the reactive gas is introduced through the gasline 319'. The next Rf etching chamber 313 is a chamber for carrying out cleaning of the substrate surface after selective deposition (etching) under Ar atmosphere, and internally thereof are provided at least a substrate holder 320 capable of heating the substrate to a range of 100 °C to 250 °C and an electrode line for Rf etching 321, and also an Ar gas feeding line 322 is connected. The next sputtering chamber 314 is a chamber for depositing non-selectively a metal film by sputtering under Ar atmosphere on the substrate surface, and internally thereof are provided a substrate holder 323 heated within a range of 200 °C to 250 °C and a target electrode 324 for mounting a sputter target material 324a, and also an Ar gas feeding line 325 is connected. The final loadlock chamber 315 is a control chamber before taking out the substrate after completion of the metal film deposition into the outer air, and constituted so that the atmosphere may be replaced with N 2 . Fig. 7 shows another constitutional example of a sequential metal film forming apparatus preferable for applying the film forming method as described above, and the same portions as described above in Fig.6 are made the same symbols. The difference of the apparatus in Fig. 7 from that in Fig. 6 resides in that a halogen lamp 330 is provided as the direct heating means and the substrate surface can be directly heated, and for that purpose, the substrate holder 312 is provided with a nail 331 for holding the substrate under suspended state. By heating directly the substrate surface with such constitution, the deposition speed can be further improved as described above. The sequential metal film forming apparatus with the above constitution, as shown in Fig. 8, is substantially equivalent to one with the structure having the above loadlock chamber 311, the CVD reaction chamber 312, the Rf etching chamber 313, the sputtering chamber 314, the loadlock chamber 315 connected mutually to one another with the conveying chamber 326 as the relay chamber. With this constitution, the loadlock chamber 311 functions also as the loadlock chamber 315. In the above conveying chamber 326, as shown in the Figure, an arm 327 as the conveying means reversibly rotatable in the AA direction and stretchable in the BB direction is provided, and with the arm 327, as shown in the arrowhead in Fig. 9, the substrate can be moved following the steps successively from the loadlock chamber 311 to the CVD chamber 312, the Rf etching chamber 313, the sputtering chamber 314, the loadlock chamber 315 without exposure to outer air. A film forming procedure for explaning the present invention is described in the following. Fig. 10 is a schematic perspective view for illustration of the film forming procedure for explaining the present invention. First, the outline is described. A semiconductor substrate having openings formed on an insulating film is prepared, which substrate is arranged in a film forming chamber, and its surface is maintained at, for example, 260 °C to 450 °C to deposit selectively Al at the portion where the semiconductor is exposed according to the hot CVD method in a mixed atmosphere of DMAH as the alkylaluminum hydride and hydrogen gas. Of course, as described above, a metal film composed mainly of Al such as Al-Si may be also deposited selectively by introducing a gas containing e.g. Si atoms. Next, on the Al selectively deposited by the CVD method and the insulating film, Al or a metal film composed mainly of Al is non-selectively formed. Then, by patterning of the metal film non-selectively deposited to a desired wiring shape, electrodes and wirings can be formed. Referring next to Fig. 7 and Fig. 10, description is made in more detail. First, a substrate is prepared. As the substrate, for example, a single crystalline Si wafer having an insulating film provided with openings with respective apertures provided thereon is prepared. Fig. 10A is a schematic view showing a part of the substrate. Here, 401 is a single crystalline silicon substrate as a conductive substrate, 402 a thermally oxidized silicon film as the insulating film (layer). 403 and 404 are openings (exposed portions), having apertures different from each other. 410 is the groove bottom with Si exposed. The procedure for forming Al film which becomes the electrode as the first wiring layer on the substrate is as follows with Fig. 7. First, the substrate as described above is arranged in the loadlock chamber 311. Hydrogen is introduced into the loadlock chamber 311 to make it under hydrogen atmosphere. And, the reaction chamber 312 is internally evacuated to approximately 1.3x10 -6 Pa (1x10 -8 ) Torr)by the evacuation system 316b. However, Al film can be formed even if the vacuum degree within the reaction chamber 312 may be worse. And, the gas of DMAH bubbled from the gasline 319 is fed. For the carrier gas for the DMAH line, H 2 is employed. The second gasline 319' is for H 2 as the reaction gas, and by flowing H 2 through the second gas line 319' and controlling the opening degree of the slow leak valve not shown to adjust the pressure within the reaction chamber 312 to a predetermined value. A typical pressure in this case is preferably about 200 Pa (1.5 Torr). Through the DMAH line, DMAH is introduced into the reaction tube. The total pressure is made about 200 Pa (1.5 Torr), and the DMAH pressure 6.5x10 -1 Pa (5.0x10 -3 ) Torr. Then, current is passed to the halogen lamp 330 to heat directly the wafer. Thus, Al is selectively deposited. After elapse of a predetermined deposition time, feeding of DMAH is once stopped. The predetermined deposition time of the Al film deposited in this process is the time until the thickness of the Al film on the Si (single crystalline silicon substrate 1) becomes equal to the film thickness of the SiO 2 (thermally oxidized silicon film 2), and can be determined previously by experimentation. The temperature of the substrate surface by direct heating at this time is made about 270 °C. According to the steps up to this state, the Al film 405 is selectively deposited within the openings and the grooves as shown in Fig. 10B. All of the steps as described above are referred to as the first film forming step for formation of electrode within contact hole. After the above first film forming step, the CVD reaction chamber 312 is evacuated until reaching a vacuum degree of 6.5x10 -1 Pa (5x10 -3 Torr) or lower by the evacuation system 316b. At the same time, the Rf etching chamber 313 is evacuated to (6.5x10 -4 Pa) (5x10 -6 Torr) or lower. After confirmation that the both chambers have reached the above vacuum degree, the gate valve 310c is opened, the substrate moved from the CVD reaction chamber 312 to the Rf etching chamber 313 by the conveying means, and the gate valve 310c closed. The substrate is conveyed to the Rf etching chamber 313, and the Rf etching chamber 313 is evacuated by means of the evacuation system 316c until reaching a vacuum degree of 1.3x10 -4 Pa (10 -6 Torr) or lower. Then, argon is fed through the argon feeding line 322 for Rf etching, and the Rf etching chamber 313 maintained under an argon atmosphere of 13 Pa to 1.3x10 -1 (10 -1 to 10 -3 Torr). The substrate holder 320 of Rf etching is maintained at about 200°C, Rf power of 100 W supplied to the electrode for Rf etching 321 for about 60 seconds, and discharging of argon is caused to occur within the Rf etching chamber 313 for about 60 seconds. By doing so, the surface of the substrate can be etched with argon ions to remove unnecessary surface layer of the CVD deposited film. The etching depth in this case is made about 10nm (100Å) in terms of the oxide. Here, surface etching of the CVD deposited film is effected in the Rf etching chamber, but since the surface layer of the CVD film of the substrate conveyed through vacuum contains no oxygen, etc., no Rf etching may be effected. In that case, the Rf etching chamber 313 function as the temperature changing chamber for effecting temperature change within a short time, when the temperatures in the CVD reaction chamber 12 and the sputtering chamber 314 are greatly different. In the RF etching chamber 313, after completion of Rf etching, flowing of argon is stopped, and the argon within the Rf etching chamber 313 is evacuated. After the Rf etching chamber 313 is evacuated to 6.5x10 -4 Pa (5 x 10 -6 Torr) and the sputtering chamber 314 to 6.5x10 -4 Pa (5x10 -6 Torr)or lower, the gate valve 310d is opened. Then, the substrate is moved from the Rf etching chamber 313 to the sputtering chamber 314 by means of a conveying means, fdllowed by closing of the gate valve 310d. After the substrate is conveyed to the sputtering chamber 314, the sputtering chamber 314 is made under an argon atmosphere of 13 to 1.3x10 -1 Pa (10 -1 to 10 -3 Torr) similarly as in the Rf etching chamber 313, and the temperature of the substrate holder 323 for mounting the substrate set to about 200 to 250°C. And discharging of argon is effected at a DC power of 5 to 10 kw to cut a target material such as Al or Al-Si (Si: 0.5%) and effect film formation of a metal such as Al, Al-Si, etc. at a deposition speed of about 10000 nm/min (10000 Å/min.) on the substrate. This step is a non-selective deposition step. This is called the second film forming step for formation of the wiring to be connected to the electrode. After formation of a metal film of about 500 nm (5000Å), flowing of argon and application of DC power are stopped. After evacuation of the loadlock chamber 311 to 6.5x10 -1 Pa (5 x 10 -3 Torr)or lower, the gate valve 310e is opened and the substrate moved. After the gate valve 310e is closed, N 2 gas is permitted to flow into the loadlock chamber 311 until reaching atmospheric pressure, the gate valve 310f opened and the substrate taken out of the apparatus. According to the second Al film deposition step as described above, the Al film 406 can be formed on the SiO 2 film 402 as shown in Fig. 10C And, by patterning the Al film 406 as shown in Fig. 10D, a wiring with a desired shape can be obtained. [Experimental Examples] In the following, how excellent is the above-described Al-CVD method is and how good of the quality the Al film deposited within the openings is are described based on the experimental results. First, as the substrate, a plurality of N-type single crystalline silicon wafers were prepared, which are thermally oxidized on the surface to form SiO 2 of 800nm (8000 Å), and have various openings with various apertures from 0.25 µm c 0.25 µm square to 100 µm x 100 µm square patterned to have the underlying Si single crystal exposed (Sample 1-1). These are subjected to formation of Al films according to the Al-CVD method under the conditions as described below. Under the common conditions by use of DMAH as the starting gas, and hydrogen as the reaction gas, a total pressure of 200 Pa (1.5 Torr), a DMAH partial pressure of 6.5x10 -1 Pa (5.0 x 10 -3 ) Torr, the power amount passed through the halogen lamp is adjusted and the substrate surface temperature set within the range of 200°C to 490°C to form films. The results are shown in Table 1. As can be seen from Table 1, at a substrate surface temperature by direct heating of 260 °C or higher, Al is deposited selectively at a high deposition speed of 300 to 500 nm/min (3000 to 5000 Å/min.) within the openings. When the characteristics of the Al film within the openings at substrate surface temperature range of 260 °C to 440 °C are examined, they are found to be excellent such that no carbon is contained, with resistivity being 2.8 to 3.4 µΩcm, reflectance 90 to 95%, hillock density of 1 µm or higher 0 to 10 and substantially no spike generation (destruction probability of 0.15 µm junction). In contrast, at substrate surface temperatures of 200 °C to 250 °C, the film is found to be considerably good as compared with the prior art although the film quality is slightly worse as compared with the case of 260 °C to 440 °C, but the deposition speed is 100 to 150 mm/min (1000 to 1500Å/min), which can never be said to be sufficiently high. When the substrate surface temperature becomes 450 °C or higher, the characteristics of the Al film with the openings are lowered with the reflectance becoming 60% or less, hillock density of 1 µm or more 10 to 10 4 cm -2 , alloy spike generation 0 to 30%.

Claims: A method for producing a semiconductor device including a bipolar transistor, comprising successive steps of: forming a first semiconductor region (3) of a first conductivity type; forming a second semiconductor region (4) of the first conductivity type on the first region so that the first and second regions form a collector region, the second region (4) having a higher resistivity than that of the first region (3); forming a third semiconductor region (6) of a second conductivity type on the second region (4) for defining a base region; forming a fourth semiconductor region (7) of a first conductivity type on the third region for defining an emitter region; forming an insulating film (18) on the whole upper surface of the device; forming a groove in the second region (4) by etching a portion of the insulating film (18) located on the second region (4) and the underlying portion of the second region (4) to form a groove reaching the surface of the first region (3) and having a depth equal to or greater than its width; forming a collector electrode layer (20) mainly of Al by selective deposition from a vapour phase containing an alkylaluminium hydride selected from monomethylaluminium hydride or dimethylaluminium hydride, and hydrogen so as to fill the groove; forming base and emitter contact holes in the insulating film (18) by etching portions of the insulating film (18) located on the third and fourth regions (6,7) respectively; forming base and emitter electrode layers (22, 21) mainly of Al by selective deposition from a vapour phase containing an alkylaluminium hydride selected from monomethylaluminium hydride or dimethylaluminium hydride, and hydrogen in the base and emitter contact holes; and forming emitter, base, and collector wirings (10-12) by non-selective deposition on the whole surface of the device, and patterning, of a metallic film composed mainly of Al. A method according to claim 1 in which the wirings (10-12) are formed by sputtering. A method according to claim 2 in which the base and emitter electrode layers (21,22) are formed in a first deposition chamber and the wirings (10-12) are formed in a second deposition chamber. A method according to any preceding claim wherein said groove formed by etching and filled by selective deposition has a depth H and a width W satisfying H/W ≥ 3. A method according to any preceding claim wherein, in said step of forming the collector electrode (20), the groove is filled with single crystal Al by the selective deposition.

Inventors: ASABA TETSUO, ICHISE TOSHIHIKO, ISHIZUKA KEIJI, KATAOKA YUZO, ASABA, TETSUO, ICHISE, TOSHIHIKO, ISHIZUKA, KEIJI, KATAOKA, YUZO
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1991
Main classification: H01L29
IPC codes: H01L21, H01L29