Code setting circuit

Abstract: A trimming code setting circuit formed between a first and a second potential source (VDD,GND) includes a transistor (M1;M2;M3), an inverter (IN1;IN2;IN3), a capacitor (C1;C2;C3) and a fusible resistor (R1;R2;R3). The transistor has its source-drain passage connected between the first potential source and an output node (1). The inverter is connected between the output node and a gate of the transistor. The capacitor is connected between the first potential source and the output node. The resistor is connected between the output node and the second potential source. A steady-state current does not flow after the resistor is cut and this allows an increase in current capability of the circuit. There is no possibility for the trimming codes to change with lapse of time.

Description: The present invention relates to a code setting circuit and, more particularly, to a code setting circuit which has a conductive thin film fuse for trimming purposes. With advancement in higher capability of and higher integration in integrated circuit devices in recent years, there has been a development of stronger desires for a higher accuracy in the setting of circuit conditions and lower power consumption. Especially for the setting of values of reference voltages or of circuit currents in such as analog circuits, since the requirements for catalog specifications are very strict, it is necessary to provide a circuit for purposes of adjusting current value to a specified value by trimming methods. The trimming becomes fixed once the setting is effected in the course of a manufacturing process and cannot be readjusted at a later stage of the industrial application of a manufactured product. Such circuit is one which cannot have any changes in its permanent characteristics and which is required to be highly reliable without any fear of malfunction. The conventional circuit for trimming purposes, that is, the trimming code setting circuit has problems in that the trimming codes having been set undergo changes with time over the service life of the circuit, and that since a steady-state current flows in the circuit, it is necessary to restrict the current in order to reduce power consumption. It is an object of the invention to overcome the problems existing in the conventional circuit and to provide an improved trimming code setting circuit. It is another object of the invention to provide a trimming code setting circuit which does not undergo changes with the passage of time during the service life of the circuit. It is a further object of the invention to provide a trimming code setting circuit which is operable at low power consumption. According to the present invention, there is provided a code setting circuit formed between a first and a second potential source, said circuit comprising: a transistor having its source-drain passage connected between said first potential source and an output node; a resistor connected between said output node and said second potential source, characterised by further comprising: an inverter circuit connected between said output node and a gate of said transistor; and a capacitor connected between said first potential source and said output node. The above objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention will be explained by way of example, with reference to the accompanying drawings; in which:- Fig. 1 is a circuit diagram of a conventional trimming code setting circuit; Fig. 2 is a circuit diagram of an embodiment according to the invention; and Fig. 3 is a circuit diagram of another embodiment according to the invention. For the purpose of assisting in the understanding of the invention, first a conventional trimming code setting circuit is explained in detail before the present invention is explained. Fig. 1 schematically shows an example of a conventional code setting circuit wherein three trimming code setting circuits are provided within a range from the highest potential of VDD = +5 V to the lowest potential of GND = 0 V. The circuit operation is explained with an example of a trimming code setting circuit which is formed by a P-channel MOS transistor M6 whose source-drain passage is connected between the highest potential source VDD and an output node 10 and a thin film resistor R5 connected between the output node 10 and the ground GND. Other two trimming code setting circuits, one formed by a P-channel MOS transistor M5 and a thin film resistor R4 and the other formed by a P-channel MOS transistor M7 and a thin film resistor R6, are the same in their circuit configurations and operation as those of the trimming code setting circuit formed by the transistor M6 and the resistor R5. The P-channel MOS transistor M6 is mirror-connected to a P-channel MOS transistor M4 and has a function to allow the flow of a constant current Io which is determined by the constant current source Cs. That is to say that there is formed a ratio circuit by the P-channel MOS transistor M6 together with the thin film resistor R5. Under the state in which the resistor R5 is not cut, since the resistance value of the resistor R5 is smaller than the ON-resistance of the transistor M6, the output node 10 of the ratio circuit, that is, the junction node between the transistor M6 and the resistor R5, is of a value lower than the logical threshold value of an inverter IN8. Thus, the inverter IN8 outputs a high level output to a decoder circuit 20. Next, consideration is given to the state wherein the resistor R5 is cut. Here, due to the transistor M6, the output of the ratio circuit becomes higher when the logical threshold value of the inverter IN8. Therefore, the inverter IN8 outputs a low level output. Thus, it is appreciated whether the trimming code setting is possible or not is decided by whether the thin film resistor R5 is cut or not. Normally, the cutting of the thin film resistor is effected in the following ways. A pad, such as of aluminum, is taken out from the junction between the thin film resistor and the P-channel MOS transistor, and then a voltage is applied through the pad to the particular thin film resistor to be cut during a wafer inspection step with such an instrument as a tester whereby the thin film resistor is fused and cut by the current flowing therein. Other methods of cutting include one by which the subjected thin film resistor is cut thermally by applying a laser beam. As explained above, the trimming code setting is effected by having the subjected thin film resistor cut and such code of trimming circuit is one in which, once the trimming is done, there should be no change therein at any time during the service life of the semiconductor circuit device utilizing such code setting circuit and this requires the highest reliability. It is not possible to effect the complete removal of the thin film resistor which is not completely cut, so that there have been problems when the trimming codes being used have undergone changes with lapse of time and have become defective. Conventionally, since the current flows constantly or steadily if the thin film resistor is not cut, it has been necessary to restrict the current which the constant current source allows to flow due to problems associated with power consumption. For example, if the current which the thin film resistor and the P-channel MOS transistor forming the ratio circuit allow to flow is 10 µA and the current which leaks from the cut portion and which is detected in a test is smaller than 10 µA, the test is passed. Subsequently, a change may develop as time goes by and, if the leak current should exceed 10 µA, the output of the inverter would immediately change and the circuit involved would become defective. Thus, in the conventional trimming code setting circuit, since the tolerance allowed for a possible leakage in an incompletely cut thin field resistor is small, the reliability on the semiconductor integrated device equipped with such trimming code setting circuit has been low. Now, the present invention is explained with reference to the drawings. Fig. 2 is a circuit diagram showing an embodiment according to the present invention. As in the conventional example explained above with reference to Fig. 1, there are provided three trimming code setting circuits formed within a range from the highest potential of VDD = +5 V to the lowest potential of GND = 0 V. Here, a trimming code setting circuit composed of a P-channel MOS transistor M2, a thin film resistor R2, an inverter IN2 and a capacitor C2 is taken up for explanation. Each of the remaining two trimming code setting circuits, one formed by a P-channel MOS transistor M1, a thin film resistor R1, an inverter IN1 and a capacitor C1 and the other formed by a P-channel MOS transistor M3, a thin film resistor R3, an inverter IN3 and a capacitor C3, has the same circuit arrangements as those of the circuit formed by the transistor M2, the resistor R2, the inverter IN2 and the capacitor C2. The capacitance of the capacitor C2 is made sufficiently large as compared with other parasitic capacitance which is associated with an output node 1. Also, an ON-resistance of the transistor M2 is made large for the resistance of the resistor R2. The thin film resistor R2 may be, in addition to such film resistor as that formed in the course of the diffusion process of silicon such as polycrystalline silicon, one which is formed such as with aluminum as long as such thin film is fusible. First, an instance where the resistor R2 stays uncut is considered. Immediately after the power source is turned ON, the potential at the output node 1 is momentarily determined by the division of capacitance of capacitive components against respective potentials. However, since the capacitor C2 which is sufficiently large with respect to the other parasitic capacitance exists between the node 1 and the highest potential source VDD, the potential at the output node 1 rises substantially to the VDD potential. Thus, the inverter IN2 outputs a low level output and the transistor M2 turns ON accordingly. Next, since the resistance of the resistor R2 is smaller then the ON-resistance of the transistor M2, the potential at the output node 1 is caused to be lowered approximately to the ground potential GND. Thus, the inverter IN2 outputs a high level output and the inverter IN5 outputs a high level output to a decoder circuit 2. At the above point in time, the transistor M2 is turned OFF completely and the potential at the output node 1 turns to the ground potential GND. That is, in the circuit according to this embodiment, even when the resistor R2 is not cut, the circuit current does not flow so that, unlike in a conventional circuit, there is no need to lower the current in consideration of power consumption. Next, consideration is given to a case wherein the resistor R2 is cut. Immediately after the power source is turned ON, the potential at the output node 1 rises substantially to the VDD potential as explained above. Thus, the inverter IN2 outputs a low level output and the transistor M2 turns ON accordingly. Here, since the resistor R2 has been cut, the potential at the node 1 maintains its high level whereby the inverter IN5 continues to output the low level output. Thus, the possibility of trimming code setting depends on whether the thin film resistor R5 is cut or uncut. In the circuit according to the present invention, as explained above, the steady-state current does not flow irrespective of whether the thin film resistor is cut or uncut so that, unlike a conventional circuit, there is no need to lower the current which flows through the thin film resistor and the P-channel MOS transistor forming the ratio circuit. . Accordingly, the current to flow in the P-channel MOS transistor can be increased up to in the order of 1 mA which, in the conventional circuit, has been set to in the order of 10 µA in consideration of power consumption. Since there may no case wherein the leak current flowing in the thin film resistor which has been cut becomes larger than 1 mA, there is no fear that the trimming codes change with lapse of time according to the circuit of the invention. In the embodiment explained above, the transistor M2 is a P-channel MOS transistor, however, an N-channel MOS transistor can be used with a two-stage inverter circuit (IN12, IN13) being provided to its gate as shown in Fig. 3. As explained above, according to the present invention, there is no necessity to make the current low in consideration of power consumption since a steady-state current does not flow after the resistor is cut and this allows an increase in currents. Thus, since no leak current of the resistor after it is cut has any influence, there is no possibility for the trimming codes to change with time whereby the reliability of a semiconductor integrated circuit device which requires a trimming code setting is markedly enhanced. While the invention has been described in its preferred embodiments, it is to be understood that the words which have been used are words of description rather than limitation and that changes may be made without departing from the scope of the invention as defined by the claims.

Claims: A code setting circuit formed between a first and a second potential source (VDD, GND), said circuit comprising: a transistor (M1 ; M2; M3) having its source-drain passage connected between said first potential source and an output node (1); a resistor (R1 ; R2; R3) connected between said output node and said second potential source, characterised by further comprising: an inverter circuit (IN1;IN2;IN3;IN10,IN11;IN12,IN13;IN14,IN15) connected between said output node and a gate of said transistor; and a capacitor (C1;C2;C3) connected between said first potential source and said output node. A code setting circuit according to Claim 1, in which said resistor (R1;R2;R3) is a fusible thin film resistor whose resistance value is smaller than ON-resistance of said transistor. A code setting circuit according to Claim 1, in which said transistor (M1;M2;M3) is a P-channel MOS transistor. A code setting circuit according to Claim 1, in which said transistor (M1;M2;M3) is an N-channel MOS transistor and said inverter circuit is a two-stage inverter circuit formed by two inverters connected in series. A code setting circuit according to any one of Claims 1 to 4, in which the capacitance of said capacitor (C1;C2;C3) is larger than the parasitic capacitance associated with said output node.

Inventors: HINOOKA KIYONOBU, HINOOKA, KIYONOBU, Hinooka, Kiyonobu, c/o NEC Corporation
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: G11C17
IPC codes: H01L27, H03M1, G11C17, H01L21