Low-noise amplifier with high input impedance, particularly for microphones

Abstract: The amplifier includes a pair of bipolar input transistors (Q1, Q2), each having a base adapted to receive a differential input signal, a collector and an emitter which is biased by a first fixed current source (M7, M8) of its own and a degeneration resistor (R) which connects the emitters of the two bipolar transistors. The collector of each bipolar transistor is also biased by a second fixed current source (M5, M6) with a smaller current than that of the first source, and the collectors of the two bipolar transistors are furthermore connected to the input terminals of respective MOS amplifier devices (M1, M2, M3, M4, R L ). The amplifier can be made in BCD, BiCMOS or purely CMOS technology, in which case the bipolar transistors are obtained as lateral bipolar transistors.

Description: The present invention relates to a low-noise amplifier with high input impedance, particularly for use as microphone amplifier in the field of telephony, which can be made in CMOS technology or in a mixed technology (BiCMOS, BCD) to be included in mixed analog and digital integrated circuits. The recent evolution of circuit integration methods has allowed to integrate an increasingly large number of analog and digital functions on a single integrated circuit. This is particularly evident in the field of telephony, in which it has recently become possible to combine in a single mixed integrated circuit (BCD, BiCMOS) digital functions in MOS technology and analog functions in bipolar technology. However, as is known, bipolar technology is more expensive than MOS technology, occupies more area and dissipates more power, besides the fact that mixed technology is intrinsically complicated and therefore expensive. On the other hand, the use of analog functions or amplifiers in MOS technology is hindered by the higher noise which is typical of these circuits with respect to bipolar ones. Another hindrance is the low supply voltage which is generally available for said microphone amplifiers (since said voltage is drawn from the telephone line current). The aim of the invention is therefore to provide an amplifier entirely or predominantly in CMOS technology, which has low noise and is thus suitable for being integrated as microphone amplifier in telephone circuits. A further object is to provide said amplifier with high input impedance. Another object is to provide said amplifier so that it can operate even with a low power supply voltage (even less than 3 V). The invention achieves this aim, these objects and other objects and advantages such as will become apparent from the continuation of the description with a differential amplifier comprising a pair of bipolar input transistors each of said bipolar input transistors having a base adapted to receive a differential input signal, a collector, and an emitter which is connected to and biased by a respective first fixed current source of its own; and a degeneration resistor which connects the emitters of said pair of bipolar transistors, the collector of each bipolar transistor being also biased by a respective second fixed current source of its own, the collectors of said pair of bipolar transistors being furthermore coupled to respective MOS amplifier devices, characterized in that each of said MOS amplifier devices includes a first MOS transistor having a drain connected to a respective emitter of said pair of bipolar input transistors and a gate connected to a respective collector of said pair bipolar input transistors, and in that each of said second fixed current sources has a smaller current than that of a respective one of said first fixed source, such that the difference current flows into a respective one of said first MOS transistors. The invention is now described in greater detail with reference to some preferred embodiments, illustrated in the accompanying drawings, which are given by way of non-limitative example and wherein: Fig. 1 is a circuit diagram of a microphone circuit according to the prior art; Fig. 2 is a circuit diagram of a bipolar microphone amplifier according to the prior art; Fig. 3 is a circuit diagram of another bipolar microphone amplifier according to the prior art; and Fig. 4 is a circuit diagram of a microphone amplifier according to a preferred embodiment of the invention. With reference to Fig. 1, which illustrates a typical microphone circuit of the prior art, an electret microphone E with differential output, biased by resistors R1, R2, drives, through capacitors C1, C2 for direct-current insulation, the two inputs of an operational amplifier A, with input resistors R3, R4, a feedback resistor R5 and a bias resistor R6. The amplifier A must have low noise and low distortion. If the amplifier is manufactured in CMOS technology, it must be dimensioned with very large input transistors in order to have a low noise, with an undesirable area expenditure. Furthermore, since R3 and R4 must be much higher than the output impedance of the microphone (which is typically 1 kohm) in order to avoid signal attenuation, and since R5 must in turn be much higher than R3 and R4 (since the amplifier must provide an appreciable gain), this leads to a further considerable area expenditure, also due to the fact that said resistors must have a good linearity since they directly affect the linearity of the circuit. As is known, resistors manufactured with lower-resistivity materials are in fact the most linear; typically, polysilicon resistors, with a specific resistance of 20-30 ohm/per square, are much more linear than those with n-well or p-well diffusion, which have a typical resistance of 1-4 kohm/per square. Another known solution of low-noise amplifier is illustrated in Fig. 2, and comprises a bipolar input amplifier formed by two transistors T1, T2, with collector resistors R L and with an emitter degeneration resistor R. The transistors T1, T2 are biased by fixed current sources I, which can be in either bipolar or CMOS technology. On the basis of the equivalent circuit for small signals, the following ratio can be easily obtained as gain of the amplifier: 2βR L /(2r be + βR ) where β is the current gain of the bipolar transistors and r be is the total base-emitter resistance. For high values of β, the gain is approximately 2R L /R. The input resistance is approximately 2r be + βR: if β is not very large, and if an excessively large R is to be avoided, this value is relatively low. In order to obviate the problem of the low input impedance of the circuit of Fig. 2, it is known to modify the circuit according to the circuit of Fig. 3, in which two input transistors, with associated fixed current sources, have been added so as to form Darlington connections. The input impedance is thus increased, but the larger number of components inserted between the power supply and the ground also requires a higher minimum supply voltage, and the noise increases as well. Other examples of prior art circuits are the article in the IEEE Journal of Solid State Circuits, vol. 24, no. 4, August 1989, IEEE Inc., Piscataway, NJ, US, page 951-961, Tzu-Wang Pan et alt.:"A 50-dB Variable Gain Amplifier Using Parasitic Bipolar Transistors in CMOS, and the Japanese Patent JP-A-63 015 519. Fig. 4 illustrates an amplifier according to the preferred embodiment of the invention. Two CMOS transistors M1, M2 are driven by respective bipolar transistors Q1, Q2. Said bipolar transistors are biased by current sources M5, M6 on their collectors (adjusted by a fixed voltage V B2 ) and by current sources M7, M8 on their emitters (adjusted by a fixed voltage V B1 ) . The current generated by M7 (or M8) is higher than the current generated by M5 (or M6), and the difference current flows in the transistor M1 (or M2). The emitters of Q1 and Q2 are connected by a degeneration resistor R. The current which flow in M1 and M2 are mirrored in respective CMOS transistors M3, M4 and flow in respective load resistors R L . Each of the two pairs of MOS transistors M1, M3 and M2, M4, together with the associated load resistor R L , thus constitutes a MOS amplifier device, and the two devices together form a differential amplifier stage. When a differential signal V i1 , V i2 is applied to the bases of the transistors Q1, Q2, said transistors behave like voltage followers. Therefore, ignoring second-order effects, a voltage equal to the input voltage v i = V i1 - V i2 occurs on the resistor R, with a current V i /R, which flows almost exclusively in M1 and M2, since the currents in Q1 and Q2 are fixed by the sources M5 and M6 and vary to a negligible extent with the input signal. The current variations in Q1 and Q2 are in fact exclusively those required to vary the gate voltages of M1 and M2 (which are high-impedance points) so that these two MOS components absorb the current variation developed in R. It is evident that if the dimensions of M1 and M3 (and of M2 and M4) are identical, the differential voltage gain between the input and the output is very close to 2R L /R even for rather low values of β. This value is the same which was obtained with the known circuit of Fig. 2, in which however β was assumed to be very high. The circuit of Fig. 4 can therefore replace the one of Fig. 2, but with the advantage of a much higher input impedance. In fact, if one considers the circuit of Fig. 2, all of the signal current I R which flows in the resistor R due to the signal V i also flows in the input bipolar transistors: the base current to the signal in said bipolar transistors is therefore equal to I R /β, where β is the current gain of the bipolar transistors. In the circuit according to the invention, instead, only a small fraction of I R reaches the bipolar transistors (as mentioned above), and therefore the base current of said transistors is equal to the same fraction of I R divided by the β of said transistors. The input impedance for small signals is therefore much higher. On the basis of the equivalent circuit for small signals, it can be easily checked that the input resistance R i of the amplifier of Fig. 4 is: R i = r be + [(β + 1) + g m1 r ds5 β ] R/2 and the gain V o /V i is: V o V i = g m3 r ds5 β r be + ( β + 1 ) + g m1 r ds5 β · 2R L R where g m1 and g m3 are the transconductances of the MOS transistors M1 and M3 and r ds5 is the resistance between the drain and the source of the MOS transistor M5. The value of g m3 r ds5 is high (certainly higher than 100, provided that the MOS transistors are dimensioned appropriately), and is furthermore multiplied by β. The input impedance is therefore very high, and the gain is close to 2R L /R. One of the advantages of the circuit according to the invention is that it can operate correctly even for very small power supply voltages, differently from the one of Fig. 3. The minimum voltage which can be used without making the devices leave their correct operation region is in fact lower than 2 volts. Distortion is also very low, since as mentioned the current variation due to the input signal V i in the bipolar input transistors is very small. Due to this reason, said devices operate in a very linear region, and the total distortion is dominated by the linearity of the emitter degeneration resistor. Noise is only slightly higher than in an entirely bipolar circuit, since the dominant noise is that of the input transistors, which are indeed bipolar and therefore produce little noise, whereas the noise increase due to the MOS transistors is limited. As seen above, the circuit according to the invention is made entirely with CMOS transistors and resistors, except for the two input bipolar transistors Q1 and Q2. The circuit can therefore be manufactured in mixed bipolar/CMOS technology, such as the so-called BCD technology, or also, in view of the absence of DMOS power transistors, in the simpler and less expensive BiCMOS technology. If one considers the fact that high performance is not required of the transistors Q1, Q2, said transistors can even be obtained more economically as lateral bipolar transistors within a purely CMOS technology, for example as described in the article "MOS Transistors Operated in the Lateral Bipolar Mode and their Application in CMOS Technology", by Eric A. Vittoz in IEEE Journal of Solid-State Circuits , vol. SC-18, no. 3, June 1983. This possibility is one of the important advantages of the invention. A preferred embodiment of the invention has been described, but it is understood that the expert in the field may devise other modifications and variations comprised within the scope of the inventive concept. Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included for the sole purpose of increasing the intelligibility of the claims and accordingly, such reference signs do not have any limiting effect on the scope of each element identified by way of example by such reference signs.

Claims: Differential amplifier comprising a pair of bipolar input transistors (Q1, Q2) each of said bipolar input transistors (Q1, Q2) having a base adapted to receive a differential input signal, a collector, and an emitter which is connected to and biased by a respective first fixed current source (M7, M8) of its own; and a degeneration resistor (R) which connects the emitters of said pair of bipolar transistors (Q1, Q2), the collector of each bipolar transistor (Q1, Q2) being also biased by a respective second fixed current source (M5, M6) of its own, the collectors of said pair of bipolar transistors (Q1, Q2) being furthermore coupled to respective MOS amplifier devices (M1, M2, M3, M4, RL), characterized in that each of said MOS amplifier devices (M1, M2, M3, M4, RL) includes a first MOS transistor (M1, M2) having a drain connected to a respective emitter of said pair of bipolar input transistors (Q1, Q2) and a gate connected to a respective collector of said pair bipolar input transistors (Q1, Q2), and in that each of said second fixed current sources (M5, M6) has a smaller current than that of a respective one of said first fixed source (M7, M8), such that the difference current flows into a respective one of said first MOS transistors (M1, M2). Differential amplifier according to claim 1, characterized in that each of said MOS amplifier devices (M1, M2, M3, M4, RL) further includes a second MOS transistor (M3, M4) which has a source connected to the ground, a gate connected to a respective gate of one of said first MOS transistors (M1, M2) to act as input terminal, and a drain connected to a respective load resistor (RL) for biassing said drain, said load resistor (RL) being connected to the supply voltage. Differential amplifier according to claims 1 or 2, characterized in that each of said first MOS transistors (M1,M2) has a source connected to the ground. Differential amplifier according to one or more of claims 1-3, characterized in that it is made in BiCMOS technology. Differential amplifier according to one or more of claims 1-3, characterized in that it is made in BCD technology. Differential amplifier according to on or more of claims 1-3, characterized in that it is made in purely CMOS technology, the bipolar transistors (Q1, Q2) being lateral bipolar transistors.

Inventors: PERNICI SERGIO, PERNICI, SERGIO
Applicants: SGS THOMSON MICROELECTRONICS, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1991
Main classification: H03F3
IPC codes: H03F3