Digital colour signal processing with clock signal control for a video camera

Abstract: A video camera in which an output signal from a solid-state image sensor is converted into the corresponding digital signal at the horizontal reading cycle of the output signal, and the digital signal is digital-processed with a first predetermined clock (fs) synchronous with the reading cycle to provide a luminance signal and a color difference signal. This video camera comprises data clock converter means (42) for latching the color difference signals generated on the basis of the first clock with a data latch clock synchronous with a second clock (4 fsc) having the frequency four times as large as that of a color subcarrier (fsc) thereby to convert the clock for the color difference signal; control means (45) for detecting the phase of the changing point of the color difference signal generated on the basis of the first clock (fs) for the second clock (4 fsc) to provide a phase detecting signal and supplying said data latch clock with which the color difference signal is latched synchronously with said second clock (4 fsc) at a stable point after the changing point of the color difference signal generated on the basis of the first clock (fs); phase correction means (43) for receiving the color difference signal after data clock conversion from said data clock converter means, and producing a phase-corrected color difference signal by selecting in accordance with said phase detecting signal from the control means (45) either one of the color difference signal having an intermediate phase obtained by interpolating the signals before and after the changing point of the received color difference signal and said color difference signal after data clock conversion; and modulation means (44) for quadrature-balanced-modulating the color difference signal supplied from said phase correction means (43) to provide a modulated color signal.

Description: BACKGROUND OF THE INVENTION The present invention relates to a video pickup device which is driven by digital-processing a luminance signal and a color difference signal. In recent years, the propagation rate of home video cameras has increased rapidly. The reasons for this are 1) compactness/light weight, 2) low cost, 3) improvement of characteristics such as high image quality, and 4) improvement of usability due to the development of a movie in which a VTR (Video Tape Recorder) unit and a camera unit are integrated. And it could be noted that 1) a solid state image sensor and 2) rationalization of signal processing have greatly contributed to realize these characteristics. Generally, solid state image pick-up devices have many characteristics such as compactness/light weight, high reliability, etc. At the beginning of development, those devices were inferior to camera tubes in their production cost, sensitivity and resolution, etc. With rapid development of semiconductor technology, the solid state video camera has exceeded the camera tubes also in their production cost and performance. At present, almost all home video cameras adopt the solid state video camera. The history of development of video cameras hitherto made is disclosed in Proceedings of The institute of Television Engineers of Japan, Vol. No. 11 (1987), pp. 983 - 990. On the other hand, the signal processing circuit is intended to improve signal processing and also to be designed in an IC for the purpose of realizing its compactness, low cost and high performance. As a result, the improved signal processing circuit coupled with above solid state camera has realized the high quality, drastic compactness/light weight and low cost of the home video cameras. However, the analog signal processing system adopted hitherto has a certain limit in further rationalizing the signal processing. In the future, a digital signal processing system, which has the following features, will become the most favorite signal processing system for reasons as follows: 1) The filter which is a bulky component can be integrated in an IC with high accuracy. 2) Circuits incorporating A/D and D/A converters can be comprised within a single chip. 3) Due to rounding error of calculation, signal processing circuits with high S/N can be easily realized. An example of the signal processing in such a video camera is disclosed in Japanese Patent Publication JP-A-63-45153. Fig. 1 shows a block diagram of a prior art video camera in which the conventional analog signal processing unit is designed in a digital system. In Fig. 1, in response to an input optical signal 11, a sensor 1 produces an analog pixel signal 12, for each horizontal read scanning period, which is synchronous with a read clock frequency (hereinafter referred to as sensor clock) and consisting of repeated alternately different color signals. The operation of the sensor 1 is controlled by the control signal 18 sent from the sensor driving timing generator circuit (hereinafter abbreviated TG). The analog pixel signal 12 is A/D converted by an analog/digital converter (hereinafter abbreviated A/D) to provide a digital pixel signal 13. A digital signal processing circuit 3, when it receives the digital pixel signal 13, a synchronization (sync) signal 20 and a control signal 23 from a synchronization signal generating circuit (hereinafter abbreviated SSG) and the control signal 18 from TG 5, produces a luminance signal 14 and a color difference signal 15 supplemented with the sync signal 20, respectively. These signals 14 and 15 are D/A converted by a digital/analog converter (abbreviated D/A) to provide an analog luminance signal 16 and an analog color signal supplemented with the sync signal, respectively. An explanation will be given of the control signal 18 generated by TG5, and the sync signal 20 and the control signal 23 generated by SSG 8. First, SSG 8 when the signal 60 at a frequency of n·fsc is supplied as a clock from an oscillator 61 with an oscillation frequency of n·fsc (n = an integer; and fsc = the frequency of a color subcarrier), produces a horizontal sync signal (hereinafter referred to as CHD) and a vertical sync signal (hereinafter referred to as VD) which are necessary to generate a sensor driving signal; these two signals 19 are supplied to TG5. In response to the signal CHD and the signal fs from an oscillator 51, TG5 produces a sensor clock signal fs. On the other hand, in response to the clock signal nfsc, SSG 8 produces synchronization (sync) signals 20 such as a composite sync signal (CSYNC), a composite blanking signal (CBLK), a burst flag signal (BF), etc. The digital signal processing circuit 3, in response to the sensor clock nfsc, produces the luminance signal 14 and a color difference signal 15 supplemented with the sync signals 20, wherein the color difference signal 15 is further modulated by the control signal 23. The art related to the system described above is disclosed in Japanese Patent Publication No. 63-45153. Many problems remain to be solved in digitizing the signal processing in the video camera provided with a CCD sensor 1 which is the solid state image pick-up device shown in Fig. 1. One of them is to digitize the encoder for a color signal. The present CCD sensor adopts several values as the number of horizontal pixels. Since the horizontal scanning period is fixed, there are different frequencies of horizontal pixel read clock signals (sensor clock) corresponding to the number of pixels. For example, the sensor clock frequency (fs) in an NTSC color television system includes the values of 9.5 MHz, 12.7 MHz, 14.3 MHz, etc. Generally, the signal processing in the digital camera is desired to be performed in a process which is synchronous with the sensor clock because of its easiness and merit of providing small-sized circuits. Now it should be noted that the signal processing in the encoder must be done with a clock frequency which is n times as large as fsc (n = 3 or 4). Therefore, if in digitizing all the signal processings in a camera the relation fs = n·fsc (n = 3, 4, 6, 8, etc.) is not satisfied (the phase of a high clock is not fixed for), jitter of (n·fs) -1 is generated when signals are transferred to the encoder. Now if n = 4, the jitter in the two color TV systems is: NTSC : (4fsc) -1 = 70 ns, and PAL : (4fsc) -1 = 56 ns. The value of jitter permitted for the color signal is, however, only 35 ns or less so that it is apparent that the above jitter is not permitted. It was found that n must be 8 or greater in order to be within the permitted value. However, actually, the signal processing based on an oscillation at 8 fsc (NTSC = 28.6 MHz, PAL = 35.44 MHz) suffers from the following defects: 1) The oscillation is likely to be unstable to require the strict specifications for an oscillator. 2) The power consumption of the oscillator is doubled. 3) The gate switching speed for an encoder circuit is required to be twice as high as hitherto so that very strict specifications are required for the components. 4) Furtheron, the power consumption for the encoder circuit is increased. For these reasons the signal processing is desired to be actually done with a clock of 4 fsc or less. Incidentally, digitizing the encoder is not referred to in the above Japanese Patent Application JP-A-63-45153. The prior art video camera shown in Fig. 1 has, in addition, the following defect. In converting the signals in the processing system from analog to digital, no consideration on taking synchronization of a luminance signal with a sync signal, when the luminance signal is supplemented with the sync signals, is made although the luminance signal is synchronous with the sensor clock fs and the sync signal such as CSYNC is synchronous with n·fsc. Fig. 2 is a timing chart showing the relationship between the sensor clock fs and CSYNC before it is added to the luminnance signal, and CSYNC after it has been added thereto. As seen from Fig. 2, if the rising edge 104 of the sensor clock 101 coincides with the falling edge 106, CSYNC is latched at the rising edge 104 so that it remains unvaried and, for CSYNC after being added to the luminance signal, the waveform 102 results; on the other hand, when CSYNC is latched not at the rising edge 104 but at the rising edge 105, for CSYNC, after being added to the luminance signal, the waveform 103 results. In this case, the timing difference between the two cases CSYNC 102 and CSYNC 103 in their falling edges is 1/fs (difference between 106 and 107). If, for example, the number of sensor clock pulses in the horizontal period is 550, then there is 1/fs = 1H/550 = 115 ns. Such a large timing difference will produce jitter in the output image which will be visible by the human eye. Further, since the horizontal read clock frequency in the sensor for TG5 is fixed at a certain value, the video camera cannot deal with the sensor fixed at a different clock frequency; thus the video camera does not have sufficient versatility. An object of the present invention, therefore, is to provide an improved video camera wherein all the signal processings are digitized including that in an encoder which avoids within a permitted range (35 ns or less) the jitter generated when 4 fsc is used as the data processing clock in the encoder, and enables low power consumption and small-size/light weight constructions. Another object of the present invention is to provide a video camera comprising a digital signal processing circuit which prevents jitter from being generated on an output image, wherein, for example, a programmable SSG which is controlled by a microcomputer can make the timing of the sync signal variable so that sensors of several different specifications can be implemented. The above and other objects are solved in advantageous manner basically by applying the features laid down in the characterizing portions of the independent apparatus and method claims 1 and 4. Further features and aspects of the invention and enhancements are defined in the associated dependent claims. SUMMARY OF THE INVENTION In order to put the jitter within the permitted value, the video camera according to the present invention comprises an A/D converter for converting the output signal from a CCD sensor into a digital signal synchronously with a sensor clock, a signal processor for processing the digital sensor output from the A/D converter on the basis of a sensor clock to generate a luminance signal and a color difference signal, an encoder for balanced-modulating the color difference signal on the basis of a clock at 4fsc (referred to 4fsc clock), and a D/A converter for converting two digital signals of the luminance signal and the color difference signal after modulation generated by the encoder into analog signals, respectively, and further comprises a data clock converter for latching the color difference signal with the cycle of fs/m (m = 1, 2, 3, 4, ...) generated by the signal processor on the basis of the sensor clock by a latch pulse on the basis of a 4 fsc clock generated by a control circuit described later, thereby producing a converted data clock; a control means for generating the latch pulse to be supplied to the data clock converter on the basis of the 4fsc clock from the phase reference signal (for example, a latch pulse at the final stage of the color difference signal) providing the changing phase of the color difference signal with fs/m cycles outputted from the signal processor based on the sensor clock, and also detecting the relative phase between the phase reference signal and the 4fs clock at the rising and falling edges of the 4 fsc clock to control a phase correction circuit described using the detected signal; and a phase correction means for phase-correcting the color difference signal supplied from the data clock converter on the basis of the phase detected signal supplied from the control means and supplying the color difference signal after correction to the encoder. Further, in order to prevent the jitter from being generated, a sync signal generating circuit (SSG) is provided to comprise an nfsc unit for generating a horizontal sync signal and a vertical sync signal for a sensor using the signal at the frequency of nfsc as a clock and a fs unit for generating the sync signal ' for generating a television signal. Another arrangement comprises a signal switching circuit for alternately supplying the sync signals for the luminance signal and the television to the D/A converter and a clock switching circuit for alternately supplying the clock at the frequency nfsc and the sensor clock fs as a clock for the D/A converter. In the preferred embodiment which is the subject of this application, the control circuit detects the phase relationship between the phase reference signal and the 4 fsc clock with accuracy of (8 fsc) -1 by detecting it at the rising and falling edges of the 4 fsc clock, and the phase correction circuit detects the amount of jitter due to the detected phase relationship to replace the color difference signals having the jitter supplied from the data clock converter by the data interpolated from adjacent data before and after latch, thus making the phase correction for the color difference signals. In this interpolation processing, the ratio of the adjacent data to be added can be changed to create the data in any phase. Therefore, the accuracy of phase correction depends on the detection accuracy so that the amount of jitter remaining after the phase correction is equivalent to the detecting accuracy. Thus, the amount of jitter of the color difference signals after the phase correction is equal to (8 fsc) -1 which is within a permissible range for the color difference signal. In this way, the problem of jitter occurring in the digital encoder can be solved. In another arrangement which is the subject of a divisional application (published as EP-A-0 720 389 on 03 July 1996), when the clock at the frequency of nfsc is supplied, the nfsc unit generates the clock by means of a counter, etc., a horizontal sync signal (CHD) and a vertical sync signal (VD) for the video camera which are supplied to TG. TG generates a sensor clock fs using a signal synchronous with CHD and supplies several kinds of control signals including the sensor clock fs to the digital signal processing circuit and the fs unit in SSG. The digital signal processing circuit performs a signal processing using the sensor clock fs as a clock to generate the luminance signal and the color difference signal. On the other hand, using the sensor clock fs as a clock, the fs unit also generates the sync signals such as a composite sync signal (CSYNC) for TV. Therefore, the luminance signal and the sync signals are synchronous with the sensor clock fs so that the luminance signal is synchronous with the sync signals. Thus, when the digital signal processing circuit supplements the luminance signal with the sync signals, a large timing difference which would cause jitter is not generated. In still another arrangement which is the subject of the above-mentioned divisional application, during a horizontal blanking period and at the time (point A) when the level of the luminance signal is at a predetermined level before the horizontal blanking period and horizontal synchronizing period, the signal switching circuit is switched on the side of the sync signals and also the clock switching circuit is switched on the side of the nfsc so that the sync signals are supplied, using the nfsc clock, to the D/A converter from which analog sync signals are produced. Likewise, during the horizontal blanking period and at the time (point B) when the level of the luminance signal is at a predetermined level after the horizontal blanking period, the signal switching circuit and the clock switching circuit are switched on the sides opposite to the above cases so that an analog luminance signal is produced from the D/A converter circuit. Therefore, even if the luminance signal and the sync signals are not synchronous with each other at the points A and B, because of the level of the luminance signal being fixed, no jitter is generated. If in a further arrangement which is also the subject of the above-mentioned divisional application, the timing data, the control signals such as a sensor clock and a vertical sync signal are supplied from a microcomputer, TG and the nfsc unit, respectively, with the timing data held in a state holding circuit, the fs unit processes the value of a counter using the sensor clock fs as a clock and the timing data held in the state holding circuit thereby to generate a horizontal sync signal and synthesizes the horizontal sync signal and the vertical sync signal supplied from the nfsc unit, thereby generating sync signals. Thus, if the timing data supplied from the microcomputer to the fs unit are set for the specification of a sensor used, the sync signals applied to the sensor can be generated, thereby realizing versatility for plural sensors. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing the basic arrangement of the prior art; Fig. 2 is a timing chart showing the relationship between the sensor clock and the composite sync signal used in Fig. 1; Fig. 3 is a block diagram of a video camera according to a preferred embodiment of the present invention; Fig. 4 is a timing chart showing the waveforms at the respective points of the arrangement of Fig. 3; Fig. 5 is a block diagram showing the details of the data clock converter circuit, the phase correction circuit and the control circuit in Fig. 3; Fig. 6 is a timing chart showing the wave-forms at the respective points in Fig. 5; Fig. 7 is a block diagram showing the details of the digital encoder in Fig. 3; Fig. 8 is a timing chart showing the waveforms at the respective points in Fig. 7; Fig. 9 is a block diagram of a modification of the arrangement of Fig. 3; and Fig. 10 is a timing chart showing the respective points in Fig. 9. DESCRIPTION OF THE PREFERRED EMBODIMENT Now referring to the accompanying drawings, Fig. 3 shows the arrangement of the video camera according to a preferred embodiment of the present invention. In Fig. 3, numeral 1 denotes a solid state camera sensor; numeral 2 denotes an A/D converter; numeral 3 denotes a digital signal processing circuit for generating a luminance signal and a color difference signal; numeral 5 denotes a driving circuit (sensor driving timing generating circuit); numeral 8 denotes a sync signal generating circuit; and numerals 4 and 4' denote a D/A converter, respectively. As described later, the digital signal processing circuit 3 is composed of a data clock converter circuit 42, a phase correction circuit 43, an encoder 44 and a control circuit 45. First, the sync signal circuit 8 generates sync signals (horizontal/vertical sync signals, a subcarrier, clocks, etc.) required for a signal processing circuit 41, the driving circuit 5 and other circuits. The pulses or the like necessary for signal processing in processing circuit 41 and encoder 44 are not shown in Fig. 3 since they are not indispensable to the present explanation. The driving circuit 5 reads signals from the solid-state image sensor 1 at the sensor clock cycle fs in synchronism with the horizontal sync signal and the vertical sync signal supplied from the sync signal generating circuit 8. The sensor output which corresponds to an optical signal 11 is read from the solid-state image sensor 1 and is supplied to the A/D converter 2. The A/D converter 2 converts the sensor output signal for each pixel into a digital signal in synchronism with the sensor clock; this digital signal is supplied to the signal processing circuit 41. The signal processing circuit 41 processes the digital sensor output signal after A/D conversion (which is supplied from the A/D converter 2 through the processing disclosed in Japanese Patent Publication No. JP-A-63-45153) on the basis of the sensor clock thereby producing a luminance signal and color difference signals. The color difference signals (R-Y) and (B-Y) thus produced are supplied to the data clock converter circuit 42. The control circuit 45 detects with an accuracy of (8 fsc) -1 a phase difference between the phase reference signal indicative of the changing point of the color difference signals supplied from the signal processing circuit 41 (e.g. a latch clock of the color difference signal as described above) and the 4 fsc clock supplied from the sync signal generating circuit to send a data latch pulse (clock) to the data clock converter circuit 42 and the phase correction circuit 43, and send a phase detecting signal to the phase correction circuit 43. The data clock converter circuit 42 latches the color difference signals (R - Y) and (B - Y) supplied from the control circuit 45 with the data latch clock so that the color difference signals after latch are sent to the phase correction circuit 43. The phase correction circuit 43 phase-corrects the color difference signals (R - Y) and (B - Y) to be sent to the encoder 44. Meanwhile, the above control circuit 45 latches the supplied phase reference signal at the rising and falling edges of the 4 fsc clock to detect in which period of 'H' and 'L' of the 4 fsc clock the changing points of the color difference signals are located on the basis of the latched two phase reference signals, and supplies the detected signal to the phase correction circuit 43. Now assuming that the 'H' period and the 'L' period are substantially equal, the changing points of the color difference signals can be detected at intervals of 1/2 of (4 fsc) -1 . Since (4 fsc) -1 /2 = (8 fsc) -1 , the changing points can be detected with an accuracy of (8 fsc) -1 . Further, as mentioned above, the control circuit 45 processes the phase reference signal with the 4 fsc clock to generate the latch pulse which will be supplied to the data clock converter circuit 42. It should be noted that this latch pulse can provide a jitter up to (4 fsc) -1 to the above phase reference signal in accordance with the phase relationship between the phase reference signal and the 4 fsc clock. The data clock converter circuit 42 latches the color difference signals (R - Y) and (B - Y) supplied from the signal processing circuit 41 with the latch pulse supplied from the control circuit 45. As a result, the latched color difference signals (R - Y) and (B - Y) can be processed using the signal of the 4 fsc clock. However, as mentioned bove, the latch pulse provides the jitter up to (4 fsc) -1 so that the latched color difference signals also have the jitter up to (4 fsc) -1 . The latched color difference signals are further supplied to the phase correction circuit 43. The phase correction circuit 43 first latches the color difference signals having the jitter up to (4 fsc) -1 supplied from the data clock converter circuit 42 with the above latch pulse and adds these latched color difference signals to the signals before latch supplied from the data clock converter circuit 45 to generate the color difference signals having an intermediate phase. Next, in accordance with the phase detection signal sent from the control circuit 45, the color difference signals having the intermediate phase corresponding to one clock of (4 fsc) -1 are selectively produced only if they are located, at the changing points, on the phase side in which the delay time of the color difference signals is shortened owing to latching by the data clock converter circuit 42 in the 'H' side or 'L' side of the 4 fsc clock; and in the other case, the color difference signals supplied from the data clock converter circuit 45 are produced. Therefore, the signal advancing by (4 fsc) -1 in the case where the maximum jitter is generated can be effectively delayed by 1/2 of (4 fsc) -1 so that the maximum jitter is limited to (4 fsc) -1 /2 = (8 fsc) -1 which is permissible as mentioned above. Fig. 4 shows the waveform charts for explicitly explaining the manner of reducing the jitter on the basis of the above processing. Fig. 4 shows the state where the maximum jitter is provided assuming that the sensor clock is fs ≃ (4 fsc) x (2/3), the data cycle of the color difference signal is fs/2, the phase reference signal 13 has substantially the same phase as the 4 fsc clocks 15 and 16 (the phases A and B are slightly earlier and later from the phase reference signal 13, respectively). In Fig. 4, a waveform 12 denotes a sensor clock fs; a waveform 13 denotes the phase reference signal; a waveform 14 denotes the color difference signals; the waveform 15 denotes the 4 fsc clock when its rising edge is in the phase (A phase) slightly earlier than that of the phase reference signal 13; the waveform 16 denotes the 4 fsc clock in the phase (B phase) slightly later than that of the phase reference signal 13; a waveform 17 denotes the data latch clock corresponding to the phase A, a waveform 18 denotes the data latch clock corresponding to the phase B; a waveform 19 denotes the color difference signals after latch corresponding to the phase A; a waveform 20 denotes the color difference signals after latch corresponding to the phase B; and a waveform 21 denotes the color difference signals phase-corrected corresponding to the phase B. It should be noted that the data latch clocks 17 and 18 are generated by twice latching the phase reference signal with the rising edge of the 4 fsc clock. The reason for this is that generally, if the latched data and the latched clock are completely in phase with each other, the latched data may be unstable so that malfunctioning due to this should be prevented. However, whether or not the jitter occurs owing to latching depends on the first latching. As mentioned above, the phase of the phase reference signal is decided according to which period of 'H' (a in Fig. 4) and 'L' (b in Fig. 4) of the 4 fsc clock its rising edge is located on. Under such an assumption, the data after latch advances by approximately (4 fsc) -1 in the phase B where the rising edge of the phase reference signal 13 is located in the 'L' period of the 4 fsc clock. Therefore, the control circuit 45 detects the phase B and the detected signal is supplied to the phase correction circuit 43. In accordance with the detected signal, the phase correction circuit executes the phase correction only at the phase B to produce the color difference signals after phase correction as shown by the waveform 21. At the phase B, the color difference signals as shown by the waveform 19 are used as they are. As is apparent from the comparison of the waveform 19 with the waveform 20, the above processing provides the jitter of (8 fsc) -1 corresponding to the phase difference between the center points (C A and C B ' in Fig. 4) of N-th data which is substantially half as long as that between the center points (C A and C B in Fig. 4) of the N-th data in the case where the phase correction is not made. In short, the above processing can reduce the jitter from (4 fsc) -1 to (8 fsc) -1 . In this way, when the sensor having any number of pixels is used, the jitter attendant on the data clock conversion of the color difference signals (R - Y) and (B - Y) to be supplied to the encoder 44 can be limited to (8 fsc) -1 or less. The encoder 44 balanced-modulates the supplied color difference signals (R - Y) and (B - Y) using the 4 fsc clock and fsc clock supplied from the sync signal generating circuit 8. The modulated color difference signal generated through the above processing and the luminance signal produced by the signal processing circuit 41 are sent to D/A converter circuits 4' and 4, respectively. The D/A converter circuits 4 and 4' convert the supplied luminance signal and modulated color difference signal into corresponding analog signals, respectively. These D/A converter circuits 4 and 4' are not required if the above luminance signal and modulated color difference signal are further processed in the digital mode. In accordance with this embodiment, the signal processing including an encoder is digitized, and when a sensor with any number of pixels is used, the jitter generated in the encoder can be limited to (8 fsc) -1 , thus preventing the image quality from detoriation. Fig. 5 shows the respective details of the data clock converter circuit 42, the phase correction circuit (here designated 53) and the control circuit 45. Fig. 6 shows the waveforms at the respective points in Fig. 5. As described in connection with Fig. 4, in Fig. 6 also, assuming that the sensor clock is fs ≃ (4 fsc) x (2/3), and the phase reference signal and the edge of the 4 fsc clock are substantially in phase with each other, the state providing the maximum amount of jitter is taken. Further, it is also assumed that the data cycle of the color difference signals (R - Y) and (B - Y) is 1/2 of the sensor clock as in the previous case. In Fig. 5, the data clock converter circuit 42 is composed of latch circuits 422 and 423; the phase correction circuit 53 is composed of latch circuits 530, 531, adder circuits 532, 533, coefficient circuits 534, 535, multiplexers 536, 537, a DFF (D flip-flop) 538, a NOR gate 539 and an AND gate 540; and the control circuit 45 is composed of DFF's 454, 455, 456, 457 and 458 and an inverter 459. Further, in Fig. 6, the same reference numerals refer to the same waveforms in Fig. 4. Namely, the waveform 13 denotes a phase reference signal; the waveform 14 denotes a data train D i resulting from the sum of i-th (R - Y) and (B - Y); the waveform 15 denotes the 4 fsc clock having the phase (A phase) that is slightly earlier than the rising edge of the phase reference signal; and the waveform 16 denotes the 4 fsc clock having the phase (B phase) that is slightly later than the phase reference signal 13. The other waveforms correspond to alike waveforms in Fig. 4. An explanation will be given of the other waveforms in connection with the operation of the corresponding components. First, the phase reference signal 13 and the 4 fsc clock are supplied to the control circuit 45. The control circuit 45 latches the supplied phase reference signal (waveform 13) twice at the rising edge of the 4 fsc clock by DFF's 454 and 455 and twice at the falling edge of the 4 fsc clock by DFF's 456 and 457. As a result, the respective Q outputs of DFF 454 and 456 provide pairs of waveforms 17 (phase A) and 18 (phase B), and 50 (phase A) and 51 (phase B). The Q output from the DFF 454 is supplied to the data clock converter circuit 42 and the phase correction circuit 53 as a data latch clock. On the other hand, the Q output from DFF 456 is further latched by DFF 458 with the Q output from DFF 454. Thus, the Q output from DFF 458 provides the waveform 52 in the phase A and the waveform 53 in the phase B. Therefore, as the Q output from DFF 458 is 'L' or 'H', it is possible to detect in which period of the 'H' (a in Fig. 6) and 'L' (b in Fig. 6) periods of the 4 fsc clock the rising edge of the phase reference signal 13 is located. This operation corresponds to the phase detection described previously. The Q output from DFF 458 is supplied to the phase correction circuit 53 as a phase detection signal. The data clock converter circuit 42 latches the color difference signals (R - Y) and (B - Y) indicated by numeral 14 by the latch circuits 422 and 423 with the data latch clock supplied from the control circuit 45. Each of the latch circuits 422 and 423 may be composed of DFF's corresponding to the number of bits of the color difference signals (R - Y) and (B - Y). The respective outputs of the latch circuits 422 and 423 provide the waveform (phase A) or the waveform (phase B). These output signals are supplied to the phase correction circuit 53. The phase correction circuit 53 latches the color difference signals (R - Y) and (B - Y) supplied from the data clock converter circuit 42 by the latch circuits 530 and 531 with the data latch clock supplied from the control circuit 45. The color difference signals (R - Y) and (B - Y) after latch are added to the color difference signals before latch supplied from the data clock converter circuit 42. The signals thus obtained are multiplied by the coefficient circuits 534 and 535 to provide the color difference signals (D i + D i+1 )/2 in the intermediate phase between D i and D i+1 which are supplied to the multiplexers 536 and 537. The multiplexers 536 and 537 produce the supplied color difference signals in the intermediate phase and the color difference signals supplied from the data clock inverter circuit 42 in accordance with the output signal from the AND gate 540. Now it is assumed that if the output form the AND gate 540 is 'H', the color difference signals in the intermediate phase are produced. On the other hand, the rising edge detecting circuit composed of DFF 538 and NOR gate 539 produces an edge signal which is 'H' during only one cycle of the 4 fsc clock immediately after the supplied data latch clock has changed from 'L' to 'H'. The AND gate 540, in accordance with the phase detection signal supplied from the control circuit 45, supplies the above edge signal to the multiplexers 536 and 537 for the phase B and mask this signal for the phase A. The waveform of the output from the AND gate 540 is shown as the waveforms 54 (phase A) and 55 (phase B) in Fig. 6. As a result, the multiplexers 536 and 537 selectively produce the color difference signals in the intermediate phase only at the edge of the phase B, and produce the color difference signals having the waveform 19 for the phase A and those having the waveform 21 for the phase B. These color difference signals are those with the jitter suppressed. Fig. 7 shows the details of the digital encoder 44 in an NTSC system in Fig. 3. The digital encoder 44 is composed of latch circuits 441, 442, polarity inverter circuits 445, 446, DFF's 443, 444, and an adder 447. With reference to Fig. 8, the operation of the digital encoder 44 will be explained below. First, the color subcarrier fsc having the waveform 66 supplied from the sync signal generating circuit 8 (Fig. 3) is latched by the DFF 443 with the 4 fsc clock having the waveform 65. Thus, a signal having the waveform 67 is obtained. Further, this signal is latched by DFF 444 to provide a signal having the waveform 68. The signals having the waveforms 67 and 68 thus obtained are color subcarrier signals having a phase difference of 90° from each other, which are supplied to the polarity inverter circuits 445 and 446. The polarity inverter circuits 445 and 446, if the signals from DFF's 443 and 444 are 'L', invert the polarities of the color difference signals (waveforms 69 and 70) which have been obtained by latching the color difference signals with the jitter suppressed by the phase correction circuit with the 4 fsc clock, thus producing signals having waveforms 70 and 71. These signals having the waveforms 70 and 71, which are the signals modulated by the subcarriers out of phase by 90° from each other, are added by an adder circuit 447 to provide a color signal subjected to quadrature balanced modulation. Although the explanation hitherto made relates to the case of the NTSC system, in the case of PAL system also, the quadrature balanced modulation can be implemented in the same construction in such a manner that a line ID is inputted to the polarity inverter circuit 445 and the polarity inversion is done for each line when the subcarrier is 'H' or 'L'. Fig. 9 shows another embodiment of the present invention. In Fig. 9, alike reference numerals designate alike components in the previous embodiment. The present embodiment uses both 8 fsc clock and 4 fsc clock to detect the changing points of the color difference signals with an accuracy of (16 fsc) -1 for phase correction. As a result, the jitter generated results in (16 fsc) -1 . The maximum frequency of the clock is twice as large as in the embodiment of Fig. 3 and so the power consumption of the oscillator is increased. But the data processing is performed using the clock up to 4 fsc so that the power consumption in the data processing is substantially equal to that of the previous embodiment. The embodiment shown in Fig. 9 is basically different from the previous embodiment in only its phase correction circuit 43' so that only the phase correction circuit 43' will be explained below referring to Fig. 10. First, the control circuit 45 divides one cycle of the 4 fsc clock into four parts to detect where, i.e. in which range, the changing points of the color difference signals (rising edges of the phase reference signal) do occur. The phase ranges divided into four parts are designated by a, b, c and d in Fig. 10. The cases where the rising edges of the phase reference signal are located in a, b, c and d are referred to as phases A, B, C and D, respectively. Waveforms 72 and 73, waveforms 74 and 75, waveforms 76 and 77 and waveforms 78 and 79 are the 4 fsc clock and the 8 fsc clock in the cases of phases A, B, C and D, respectively. Further, waveforms 80, 81, 82 and 83 are data latch clocks, corresponding to the respective phases, produced by latching the phase reference signal 13 with the rising edge of the 8 fsc clock and thereafter with that of the 4 fsc clock. With respect to these data latch clocks, the phase A, the phase B and the phase C are earlier than the phase D by (16 fsc) -1 , 2·(16 fsc) -1 and 3·(16 fsc) -1 , respectively. Therefore, the color difference signals, latched by the data clock converter circuit 42 with these data latch clocks, have the above phase differences corresponding to the respective phases. The phase correction circuit 43 creates, on the basis of the color difference signal (D i-1 , D i ), the signals having intermediate phases (1/4 D i-1 + 3/4 D i ), (1/2 D i-1 + 1/2 D i ) and (3/4 D i-1 1/4 D i ) and outputs these signals having the intermediate phases corresponding to the phases A, B and C during only one cycle of the 4 fsc clock at the changing points of the color difference signal, thus providing waveforms 84, 85, 86 and 87 the center points of which are out of phase from one another as designated by C A , C B , C C and C D . In short, in accordance with this embodiment, in which the data processing is performed using the 4 fsc clock, the jitter can be corrected with a high accuracy of (16 fsc) -1 , thus further improving the image quality.

Claims: A video camera wherein an image signal from a solid-state image sensor (1) is converted into the corresponding digital signal at the horizontal reading cycle of the image signal, and wherein said digital signal is digitally processed with a first predetermined clock (fs) (12) synchronous with the reading cycle to provide a digital luminance signal (Y) and a digital color difference signal (R-Y, B-Y) (14), characterized by: data clock converter means (42) for latching the color difference signals (14) generated on the basis of said first clock (12) with data latch clock signals (17, 18) which are synchronous with a second clock (4 fsc) (15, 16) having the frequency four times as large as that of a color subcarrier (fsc) thereby converting the clock for said color difference signal; control means (45) for detecting the phase of a voltage level changing point (D N-1 ⇒ D N ) of said color difference signal (14) generated on the basis of said first clock (fs) (12) and providing a phase detecting signal (output of DFF 458) and supplying said data latch clock signal (17, 18) with which the digital color difference signal is synchronously latched at a stable voltage level region (D N ) after said voltage level changing point; phase correction means (43) for receiving the color difference signal after data clock conversion (19, 20) from said data clock converter means (42), said data latch clock signal and said phase detecting signal from said control means (45), and producing at its output (45, 46) a phase-corrected color difference signal by selecting in accordance with said phase detecting signal (54, 55) either one of a phase-corrected color difference signal having an intermediate phase (21) obtained by interpolating the color difference signals before (D N-1 ) and after (D N ) said voltage level changing point and said color difference signal after data clock conversion (19); and encoder means (44) for quadrature-balanced-modulating the color difference signal supplied from the output (45, 46) of said phase correction means (43) to provide a modulated color signal (R-Y, B-Y) (70, 72). The video camera according to claim 1, characterized in that said control means (45) comprises detection means (DFF; 454-458) for detecting said voltage level changing point of the color difference signal (14) using the raising edge and falling edge of said first clock (fs) for each period ((4 fsc) -1 ) of said second clock, and said phase correction means (43) selects, in accordance with the phase detecting signal (54, 55) for each period ((4 fsc) -1 ) of said data latch clock (17, 18), either one of the average value ((D N-1 + D N )/2) of the signals before (D N-1 ) and after (D N ) said voltage level changing point and the related color difference signal after latch (19, 20) to produce at its output (45, 46) the phase-corrected color difference signal (21). The video camera according to claim 1, characterized in that said control means (45) are provided for detecting into which of four phase ranges the said voltage level changing point of the color difference signal (14) belongs, using said second clock (4 fsc) and a third clock at a frequency (8 fsc) twice as large as that of said second clock, said four phase ranges being formed by dividing one cycle of said second clock (4 fsc) into four parts, and said phase correction means (43) forms three signals (84, 85, 86) in intermediate phases on the basis of the color difference signals before (D N-1 ) and after (D N ) said voltage level changing point, and selectively outputs one of said three signals (84, 85, 86) in intermediate phases and the related color difference signal after latch to produce at its output (45, 46) the phase-corrected color difference signal. Method of producing in a video camera phase-corrected digital color difference signals (R-Y, B-Y) with suppressed jitter, characterized by the following steps: supplying digital color difference signals (14) obtained in a predetermined reading cycle from the image sensor (1) of the video camera to a digital signal processing means (41, 42, 43, 45) where they are processed under control of a first clock (fs) pulse waveform (12) which is in synchronism with said reading cycle; generating phase reference signals (13) which are indicative of the voltage level changing points of said digital color difference signals (14) whenever said signals (14) change voltage level after each stable voltage level region (D N-1 ⇒ D N ); generating under control of a second clock (15, 16) having a frequency n-times (e.g. n = 4) larger than the frequency of the color subcarrier (fsc), latch clock signals (17, 18) in synchronism with said second clock (15, 16); detecting the phase in said digital color difference signals (14) at said changing points in relation to said second clock (15, 16); latching the digital color difference signals with said latch clock signals (17, 18) in synchronism with said second clock (15, 16) to the effect that the voltage level changes of the digital color difference signals after latch (19, 20) coincide with the raising edges of the latch clock signals (17, 18); generating from said latch clock signals (17, 18) associated phase detecting signals (54, 55); supplying said digital color difference signals after latch (19, 20) to a first MPX input of a multiplexer MPX (536, 537); interpolating successive data portions (D N-1 , D N ) of said digital color difference signals to form intermediate signal values ((D N-1 + D N )/2) which are supplied to a second MPX input of said multiplexer MPX; and placing said intermediate signal values between the successive portions (D N-1 , D N ) of said digital color difference signals by selective MPX switching under control of said phase detecting signals (54, 55) to connect the said first or the said second MPX input to the MPX output (45, 46) thereby obtaining the phase-corrected digital color difference signals (21).

Inventors: KOSHIO KAZUHIRO, OHTSUBO HIROYASU, KOSHIO, KAZUHIRO, OHTSUBO, HIROYASU, OHTSUBO, HIROYASU, HITACHI CHIGASAKI DOMITORI
Applicants: HITACHI LTD, HITACHI, LTD.
Application year: 1991
Main classification: H04N9
IPC codes: H04N9, H04N5