Memory device

Abstract: A common requirement for a display adapter for multimedia applications is to be able to support two display "layers" simultaneously accessed from display memory. For each displayed pixel the two display layers are merged with various forms of mixing possible. The obvious way of displaying these two layers is to hold each layer in separate VRAMs and use the VRAM serial ports to access the two layers simultaneously. However, with the low resolution displays and small memory sizes required for personal computers it is not possible to keep the two layers in separate VRAMs, and so both data streams must be fetched from a single VRAM, or bank of VRAMs. With conventional VRAMs this cannot be efficiently achieved. By a novel enhancement to a conventional "Split Shift Register" VRAM, the disclosed invention allows both layers to be accessed simply and efficiently from the same memory device(s). The disclosed invention finds application in the field of semiconductor memory devices, in particular VRAMs and other similar memory devices. The disclosed use of memory devices according to the invention finds application in the field of, but not limited to, display memory subsystems.

Description: The present invention relates to a memory device capable of high speed data transfer to a peripheral device such as a raster display. Such memories are commonly known as Video Random Access memories (VRAMs). VRAMs are commonly used as display memories in display systems. A VRAM is essentially a conventional DRAM with the addition of a second port where memory data can be accessed serially. A conventional VRAM comprises a RAM array, a serial access memory array, address/control logic and transfer gates. The RAM array is connected to the primary (RAM) port of the VRAM and behaves in a manner identical to that of a DRAM. The SAM array, sometimes called the Shift Register, is connected to the secondary (SAM or Serial) port of the VRAM and may be accessed serially under the control of an external asynchronous clock, the Serial Clock. An address counter generates an address in the SAM, which increments under the control of the serial clock, from which data is presented at the serial port. The address/control logic supervises the address multiplexing on the RAM port and provides all the control and global timing functions of the VRAM. The transfer gates allow data to pass between the RAM array and the SAM array, under the control of the address/control logic. In modern all-points-addressable display systems, an image to be viewed is stored point-by-point as picture element or pixel data in a display memory. VRAMs are used in such display systems because their two ports can be operated independently and asynchronously, except when data must be transferred between the RAM and SAM arrays. The SAM array usually has the memory capacity of one row of the RAM array, and a full row of memory data is transferred between RAM and SAM in a single data transfer access. The RAM portion of the VRAM is used as the display memory to store pixel data to be displayed and the RAM port is used to update this data. The SAM port provides the pixel data to video generation circuitry which enables it to be passed to and displayed on a raster display device such as a cathode ray tube. The RAM port is generally operated at the frequency of the update hardware which may be, for example, a graphics processor. The SAM port is generally operated at a frequency dictated by the requirements of the display device. Because the data to be rastered onto the display device is obtained from the SAM port, almost all the RAM port bandwidth is available for update of the pixel data in the display memory. In some VRAMs the SAM array is divided into two parts, where one part can be loaded from one half of a row in the RAM array and the other part can be loaded from the other half of that row, or another row. These types of VRAMs are called Split Shift Register VRAMs. Examples of such split shift register VRAMs are described in US patent numbers 4,855,959 and 4,825,411. Transfer cycles to the two parts can be made independently so that one may be loaded while the other is being used to provide serial data at the serial output port. An output status or QSF pin is usually provided to indicate which half of the SAM is being scanned out. A common requirement for a display system for multimedia applications is to be able to support more than one display "layer" simultaneously. The number of display layers is often two, although it can be greater than two. One display layer typically contains "natural image" data, for example live television, and the other display layer typically contains an overlay of text or graphics. The image layer can be made visible through the overlay layer with various forms of mixing. For each pixel the overlay is examined to determine if it is "transparent" allowing the corresponding image pixel to be displayed, or whether it is opaque and so must itself be displayed. As this test is performed for every pixel individually it is generally necessary to fetch both overlay and image data for every pixel i.e. fetch two pictures simultaneously and switch between the pictures as determined for each pixel. A problem which arises in the application of VRAM technology to display systems for multimedia applications is that of how to hold more than one display layer in the display memory and display each layer simultaneously on a display device. One way of doing this would be to hold each layer in a separate VRAM device and use the VRAM serial port of each device to access the layers simultaneously. However, for low resolution screens one large VRAM, eg 4Mbit, would have enough capacity to hold the pixel data for all the display layers. The use of multiple VRAMs would therefore increase the memory cost by a factor of the number of layers. So, it would be advantageous if all the data streams could be fetched from a single VRAM device. With conventional VRAM designs this cannot be efficiently achieved for the following reasons. In order to obtain data for, for example, two layers held in two buffers in separate areas of a conventional VRAM it is necessary to first use a data transfer cycle to load the SAM for the first layer, then read some data for the first layer from the serial output port. Then a data transfer cycle must be used load the SAM for the second layer and data for the second layer is read from the serial output port. This sequence must then be repeated. Each data transfer cycle takes a considerable time compared to the rate at which the pixel data needs to be supplied at the output port and also requires accesses at the RAM port, thus reducing the bandwidth available to update the RAM contents. To minimise the time lost two large buffers, one for each display layer, must be used so that many serial data words can be read for each data transfer Cycle. Data for the two layers can then be taken from the two buffers simultaneously in order to be displayed. These large buffers and the control logic required add to the size and complexity of the display system. In the split shift register VRAM described in EP-A-0398510 two frame buffers are stored, one in each half of the rows in a single VRAM. One frame buffer is scanned out to the screen while the other is being updated by the graphics or image processor. A select control signal controls which half of the serial access memory presents data to the output port for each serial clock signal. This approach is only suitable when the data in each frame buffer has a similar format and so each buffer takes up a similar amount of space in the display memory. In accordance with the present invention, there is provided a memory device comprising: a random access memory portion; more than one serial access memory portion, each serial access memory portion comprising a plurality of storage locations, each storage location corresponding to a unique address; transfer gates connecting the random access memory portion and the serial access memory portions for carrying out data transfer independently therebetween; a serial output port; selection means operable in response to a selection control signal to select one of the serial access memory portions and to present, at the serial output port, the data stored in the storage location therein corresponding to an address, a number of separate address counters, one corresponding to each serial access memory portion, each for generating an address in the corresponding serial access memory portion from which address data is available at the output port via the selection means and for incrementing that address in response to a clock signal, characterised in that said separate address counters are independently clocked from each other thereby to allow differently timed serial operation of the serial access portions. Each display layer is stored in a different part of the RAM portion and transferred to a different one of the serial access memory portions to be clocked out of the serial output port when that serial access portion is selected by the selection means. The selection means can change the selected one of the serial access memory portions, in response to the selection control signal, at the rate of the serial clock. It is then only necessary to buffer a single word from each layer in order to have data from all the layers available simultaneously. In one form of the invention there is a single serial clock input and the selection means directs the serial clock to the address counter corresponding to the selected serial access portion. Thus, in this form of the invention the address counters are only incremented whilst the serial access portions of the memory to which they correspond are selected. Alternatively, a clock input can be provided for each address counter. In a preferred form of the invention the number of serial access memory portions is two. This allows the invention to be implemented as an enhancement of a conventional split shift register VRAM. An extra tap counter is added to allow independent serial operation of the two halves of the SAM. In this case the selection means comprises a means responsive to a selection control signal for switching the serial output between the two halves of the SAM. In this case, the selection control signal is a binary signal, one binary state selecting a first one of the serial access portions and the other binary state selecting the other of the serial access portions. A pin is added to allow the selection control signal to be externally applied, thus allowing external control over which half of the SAM is active at any time, i.e. which tap counter is receiving SCLK and which half of the SAM is providing data for the serial output port. The QSF pin can be converted to perform this function. In an advantageous form of the invention additional transfer gate paths are also added so that either half of the SAM can be loaded from either half of a row in the RAM array, i.e. each half of the SAM can now be loaded from any part of the RAM array. This allows an uneven division of the RAM portion of the memory if for example the image and overlay layers are at different resolutions. A pipeline latch can be included connected between the selection control input and the selection means. This reduces the timing constraints on the SAM Select input since, if the pipeline latch is included, the signal applied at the selection control input need only be valid for the latch setup and hold times rather than for the whole time data is being read from the output. This allows higher speed serial output port operation. The invention finds particular, though not exclusive, application in multi-media display systems. Accordingly, therefore, the invention enables a multi-media display system to be provided comprising the above described memory device. The multi-media display system can be in the form of a plug-in adapter card for use with a conventional data processing system or in the form of a data processing system specially adapted for multi-media applications. The display system can include a display device and video generation circuitry for generating a video signal suitable for output to the display device from the data presented at the serial output port of the memory device. An embodiment of the invention will be described below, by way of example, with reference to the accompanying drawings, wherein: Figure 1 shows a block diagram of the VRAM according to the present invention; Figure 2 shows an alternative arrangement of the clock signals to the tap counters; Figure 3 is a timing diagram showing the data presented at the serial output port and the states of the serial clock and the SAM select line; Figure 4 is a schematic block diagram of a display adapter for use in a multi-media display system in accordance with the invention; Figure 5 is a schematic block diagram of a multi-media display system in accordance with the invention. The embodiment of the invention comprises a conventional split shift register Video Random Access Memory which has been modified in accordance with the invention. Referring to figure 1 the VRAM comprises a random access portion 2 with memory locations arranged in rows and columns. Data stored in the RAM is modified via the primary port 20 and address/control logic 1. In this embodiment the VRAM has a capacity of 4Mb, organised as 256K by 16, with 512 rows by 512 columns by 16 bits. The RAM portion 2 is divided into two halves, an upper half U and a lower half L, each comprising 256 columns. Two serial access memory portions 4, 6, each comprising 256 memory locations and designated the lower and upper half of the SAM respectively, are connected to the RAM portion 2 via transfer gates 8, 10. The transfer gates enable data to be transferred between the RAM and each half of the SAM over paths 9, 11. Each half of the SAM is loadable from the RAM independently under the control of the address/control logic 1 and data from either half of the RAM can be transferred to either half of the SAM. Each half of the SAM has its own address counter means or tap counter 12, 14. The tap counters are loadable with an initial address in the SAM and generate the address of a memory location in the corresponding half of the SAM from which data is presented at the serial output port 30. This address is incremented in the tap counters in response to the serial clock signal SCLK 34. Pipeline latch 36 is connected on a SAM select input 32 and is clocked from serial clock SCLK 34. The outputs from the halves of the SAM are connected via the switch 16 to the serial output port 30. Switch 16 connects the output from one or other of the halves of the SAM to the serial output port depending on the state of the pipelined SAM select line 38. The switch 16 is a two into one multiplexor which operates under the control of the pipelined SAM select line 38. In addition, the pipelined SAM select line 38 is gated with the single serial clock input 34 via AND gates 26 and 28 and invertor 27 to the two tap counters 12, 14, so that the addresses generated by the tap counters are only incremented whilst the output of the half of the SAM to which they correspond is connected by the switch 16 to the serial output port 30. Alternatively each tap counter can have its own external clock signal. This is illustrated in Figure 2 where tap counters 12 and 14 have their own clock inputs SCLKU and SCLKL. Figure 3 is a timing diagram showing the serial data output and the states of the SAM select line 32, the pipelined SAM select line 38 and the serial clock 34. When the pipelined SAM select line is low data from the lower half of the SAM is clocked out of the serial output port. When the pipelined SAM select line is high data from the upper half of the SAM is clocked out of the serial output port. Data from one display layer is loaded into the lower half of the SAM, using one Data Transfer cycle, and data from the other display layer loaded into the upper half of the SAM, using a second Data Transfer cycle. In the example shown in Figure 3 the serial access portion from which data is being presented at the serial output port is being changed at the rate of the serial clock and so data is obtained alternately one word from each layer. In this case only one word of data needs to be buffered externally in order that both the image layer and the overlay layer be available simultaneously. If the pipeline latch were not included the SAM select input 32 would need to be identical to the pipelined SAM select input 38 shown in Figure 3. It is not necessary to switch between the two halves of the SAM on every Serial Clock cycle. An application using this VRAM can switch between the two layers whenever appropriate, for example, if the data rate required is different for the two layers due for example to differing number of bits per pixel in each layer. A VRAM constructed in accordance with the invention could easily be made capable of also working like a conventional Split Shift Register VRAM, by linking together the operation of the two Tap Counters and providing the SAM select signal from the Tap Counter logic. A memory in accordance with the invention can be used as the display memory in a multi-media display system, which can be in the form of a plug-in adapter card for use with a conventional data processing system. Such an adapter is illustrated in figure 4. It comprises display memory 50 in which pixel data for the two layers is stored. The pixel data is updated via input port 48. The serial output port of the memory is connected to a buffer 54 which temporarily stores pixel data from the image layer and then passes it to video generation circuitry 56. Pixel data from the graphics overlay layer is passed directly to the video generation circuitry 56. Buffer 54 buffers one word of the image data so that the image data and the overlay data are available to the video generation circuitry simultaneously. The video generation circuitry determines on a pixel-by-pixel basis whether the image layer or the overlay layer is to be displayed and generates a video signal suitable for output to a display device such as a CRT, enabling a composite image comprised of the image data and the overlay data to be displayed. Figure 5 shows a multi-media display system, including the display adapter 58. The display system is a conventional computer workstation specially adapted for multi-media applications. It comprises a display device 60, a central processing unit 62, a system memory 64, a disk storage device 66 and user input devices 70, such as a keyboard and a mouse. The display system is connected to a host computer system via a communications adaptor 68. So, for example, the image data could be passed to the display system from the host via the communications adapter under the control of appropriate software and stored in the display memory. The overlay layer could be generated in the workstation using appropriate software and stored in the display memory. A composite image comprising the image layer with the graphics overlayed on it can be displayed on the display device.

Claims: A memory device comprising: a random access memory portion (2); more than one serial access memory portion (4,6), each serial access memory portion (4,6) comprising a plurality of storage locations, each storage location corresponding to a unique address; transfer gates (8, 10) connecting the random access memory portion and the serial access memory portions for carrying out data transfer independently therebetween; a serial output port (30); selection means (32, 36, 38, 16) operable in response to a selection control signal to select one of the serial access memory portions and to present, at the serial output port, the data stored in the storage location therein corresponding to an address, a number of separate address counters (12,14), one corresponding to each serial access memory portion (4,6), each for generating an address in the corresponding serial access memory portion from which address data is available at the output port via the selection means and for incrementing that address in response to a clock signal (SCLK); characterized in that said separate address counters (12 ,14) are independently clocked from each other thereby to allow differently timed serial operation of the serial access portions (4,6). A memory device as claimed in claim 1 wherein the selection means (32) directs said clock signal to each address counter means only when the serial access memory portion corresponding thereto is selected. A memory device as claimed in claim 1 wherein each address counter (12, 14) has its own external serial clock input for receiving said clock signal. A memory device as claimed in any preceding claim wherein the number of serial access portions is two and the selection means comprises means (16) operable in response to the selection control signal to switch to the serial output port either the output from one or the other of the serial access memory portions (4,6). A memory device as claimed in claim 4 wherein the selection control signal is a binary signal, one binary state selecting a first one of the serial access portions and the other binary state selecting the other serial access portion. A memory device as claimed in claim 5 wherein the memory device has a selection control input and includes pipeline latch means (36) connected between the selection control input and the selection means. A multi-media display system for displaying an image made up of more than one display layer, the display system comprising a memory device (50) as claimed in any preceding claim, data from each display layer being presented at the serial output port of the memory device from different ones of the serial access memory portions, the display system comprising video generation circuitry (56) for generating, from the data presented at the serial output port of the memory device, a video signal representative of a composite image comprised of the display layers and suitable for output to a display device. A multi-media display system as claimed in claim 7 including a display device (60), for displaying the composite image, arranged to receive the video signal from the video generation circuitry.

Inventors: BUTLER NICHOLAS DAVID, WEST R MICHAEL P, BUTLER, NICHOLAS DAVID, WEST, R. MICHAEL P.
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1991
Main classification: G09G1
IPC codes: G09G5, G06F12, G11C7