Color television image display apparatus

Abstract: A color television image display apparatus wherein an image quality control signal is generated with regard to every field of an input video signal in accordance with sampled data obtained therefrom and then is supplied to an image signal processor to execute automatic adjustment of the image quality. The apparatus is equipped with a delay means having a delay time substantially equal to the time required for generation of the image quality control signal, and the video signal is supplied via such delay means to the video signal processor so that both the image quality control signal and the video signal to be controlled by such image quality control signal are inputted to the video signal processor substantially without a timing difference therebetween.

Description: The present invention relates to a color television image display apparatus equipped with an automatic image quality control means. Description of the Prior Art For the purpose of continuously achieving an optimal image state in television, technical development is recently in rapid progress with regard to a television monitor having a function of automatically controlling the luminance, color saturation and so forth to optimal conditions in every field of a video signal. When the image being displayed in a television monitor changes momentarily among light, dark, colorful and nearly monochromatic states, it is impossible to achieve a desired optimal image condition continuously if the controls for the luminance, color saturation and so on are set at fixed positions. Therefore, a predetermined unitary amount of the video signal is analyzed and then the luminance control and others are adjusted in a manner to attain the best condition. For example, as shown in Fig. 2, a video signal fed via a TV tuner 1 and an IF (intermediate frequency) amplifier 2 is supplied to an image quality control signal generator which comprises an A-D (analog-to-digital) converter 3 and an arithmetic processor 4 consisting of a microcomputer. The arithmetic processor 4 sets, in each field of the video signal, sampling points denoted by S P1 - S Pn in Fig. 3 and supplies sample timing signals to the A-D converter 3. In accordance with such sample timing signals, the A-D converter 3 executes analog-to-digital conversion of the luminance signal for example and then outputs n digital data (voltage value data of the luminance signal) in every field to the arithmetic processor 4. Then the arithmetic processor 4 calculates one field of the luminance data and generates an image control signal S Al of the luminance amplification level in accordance with the result of such calculation (discrimination data determined by the lightness, darkness and so forth of the image). The image control signal S Al thus generated is supplied to a video signal processor 5 where the luminance amplification level is controlled, and the processed signal is outputted to a CRT display unit 6. Since such process is executed with regard to every field, it follows that an optimal image quality is ensured continuously. According to the image quality control signal generator, it is possible to perform simultaneous adjustment of the color saturation, sharpness and so forth in addition to the luminance control by the same constitution, hence achieving enhancement in the overall quality of the image being monitored. However, in the conventional television image display apparatus mentioned above, there occurs a time loss which is required in the A-D converter 3 and the arithmetic processor 4 for generating an image quality control signal S Al to execute automatic image quality adjustment. Suppose now that, in an exemplary case where the arithmetic processor 4 consists of a 4-bit single chip microcomputer, a time of 0.1 second or so is required until an image quality control signal S Al(n) is outputted after sampling the data of one field F n . Then, at the instant the image quality control signal S Al(n) is inputted to the video signal processor 5, the video signal of a field F (n+5) , which is posterior by 6 fields to the relevant field F n sampled for generating the image quality control signal S Al(n) , is inputted to the video signal processor 5. Although it is a slight time delay, such delay causes a failure in adjusting the image quality of the field F n to be adjusted by the image quality control signal S Al(n) . Consequently, there arises a problem that when the image is suddenly changed, the image quality is deteriorated for a moment. EP-A2-0 221 769 discloses an image transition detector in which a transition detection signal is added to a luminance signal. The path for the luminance signal includes a delay so that the transition detection signal (delayed by the detection process) can be added at the correct timing. It is an object of the present invention to provide an improved colour television image display apparatus where both an image quality control signal and a video signal to be controlled by such image quality control signal are inputted to a video signal processor substantially without a timing difference therebetween. According to the present invention, there is provided a colour television image display apparatus comprising: a video signal processing circuit for controlling luminance signal of an input video signal fed thereto prior to display; means for supplying a video control signal to the video signal processing circuit for controlling said luminance signal, and including sampling means for dividing every field of the input video signal and providing a plurality of digital data samples of the video signal level, and an arithmetic processing means supplied with said digital data samples from said sampling means for generating therefrom the video control signal to adjust the luminance signal of the displayed video image, a signal delay means for delaying the video signal for a time substantially equal to the time required for the arithmetic processing means to generate the video control signal, so that the phase of the video signal is substantially coincident with the phase of said video control signal supplied to said video signal processing circuit; characterised by said video signal processing circuit controlling the amplification level of said luminance signal and said signal delay means delaying the input video signal in response to a timing signal from the arithmetic processing means said signal delay means consisting of an analog-to-digital converter receiving the input video signal and producing therefrom digital video data, a field memory for storing said digital video data, a digital-to-analog converter connected in series and a memory controller connected to receive the timing signal from said arithmetic processing means for controlling said field memory to read out said digital video data with an output timing substantially coincident with the output timing of the video control signal. Due to the function of the delay means, both the video signal and the image quality control signal obtained in the image quality control signal generator in accordance with the video signal are inputted to the video signal processor substantially with a timing coincidence. The present invention will be further described by way of example in the following description which will be given with reference to the illustrative accompanying drawings. Fig. 1 is a block diagram of an exemplary colour television signal display apparatus embodying the present invention; Fig. 2 is a block diagram of a conventional example; and Fig. 3 schematically illustrates a sampling operation for automatic image quality control. Hereinafter a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. Fig. 1 is a block diagram of an exemplary color television image display apparatus embodying the present invention where a delay means is composed of an image memory. In this diagram, the same reference numerals and symbols as those used in Fig. 2 denote the same or corresponding components, and both a power supply circuit and an audio circuit are omitted. A rectangular section 10 enclosed with a one-dot chained line denotes a delay means employed in this embodiment. The delay means 10 comprises an A-D (analog-to-digital) converter 11 for converting the supplied video signal into a digital signal, an image memory 12 where the digital video data is stored and read out at a predetermined timing, a D-A (digital-to-analog) converter 13, and an image memory controller 14 for supplying a timing clock signal to both the A-D converter 11 and the D-A converter 13 while supplying a read/write control signal, an operation clock signal and an address data to the image memory 12 so as to control the operation thereof. The storage capacity of the image memory 12 is set in conformity with the time required for the arithmetic processor 4 to generate an image quality control signal S Al . For example, when a time of 0.1 second is required for generation of an image quality control signal S Al , it is desired that the capacity of the image memory be sufficient to store at least six fields of the image data. A video signal fed via a TV tuner 1 and an IF (intermediate frequency) amplifier 2 is supplied to an A-D converter 3 and an arithmetic processor 4 similarly to the aforementioned example of Fig. 2, so that a predetermined arithmetic process is executed with regard to every field of the video signal to thereby generate an image quality control signal S Al . Meanwhile the video signal is supplied also to the A-D converter 11 to become digital data, which is then stored in the image memory 12. The video data stored in the image memory 12 is read out therefrom in synchronism with the output timing of the image quality control signal S Al under control of the image memory controller 14 and is converted into analog video data, which is then inputted to the video signal processor 5. Consequently, in case a time of 0.1 second is required for generation of the image quality control signal S Al , input of the video signal is delayed for 0.1 second. In the video signal processor 5, a predetermined process (such as luminance amplification to a level preset by the image quality control signal S Al for example) is executed for the input video signal in accordance with the image quality control signal S Al , and also the R (red), G (green) and B (blue) signals are demodulated. Thereafter the color signals thus demodulated are outputted to a CRT (cathode-ray tube) display unit 6. The operation mentioned above is performed with regard to every field of the video signal, so that the image of the automatically adjusted quality can be displayed on the CRT display unit 6. In this embodiment where the video signal is delayed by the delay means 10 for a time required for generation of the image quality control signal S Al , the process based practically on the image quality control signal S Al can be executed for the video signal of the field to be controlled by the image quality control signal S Al , thereby averting the disadvantage that the image being controlled is rendered noncoincident by the delay derived from generation of the image quality control signal S Al . When a time of 0.1 second is required for generation of an image quality control signal in such automatic image quality control operation performed with regard to every field as in this embodiment, it is necessary for the image memory 12 to have a sufficient storage capacity of at least 6 fields of the video signal as mentioned to attain a timing coincidence between the video signal and the image quality control signal S Al inputted to the video signal processor 5. However, the desired effect can be achieved to a certain extent even if a complete input timing coincidence is not exactly attained. For example, when the image memory 12 has a storage capacity of merely 3 fields, there occurs an input timing difference of 0.05 second even by setting a maximum delay value. It follows that an image quality adjustment based on the image quality control signal S Al is executed for the field posterior by three fields to the data-sampled field relative to generation of the image quality control signal S Al . However, if the timing difference corresponds merely to three fields or so, any sudden change of the displayed image gives no incongruous visual impression to a television viewer. Therefore it is not exactly necessary for the delay means 10 to have a delay value corresponding to the time required for generation of the image quality control signal S Al . It is a matter of course that the required storage capacity of the image memory 12 can be reduced if the time for generation of the image quality control signal S Al is shortened by the use of a high-speed microcomputer or the like. Although a description has been given with respect to an exemplary case of executing an automatic image quality adjustment for every field of the video signal, a similar adjustment may be executed for every frame or every several fields. Furthermore, it is not exactly necessary to provide an exclusive delay means as the image memory 12, and in any appliance having an image memory to perform other process, such image memory may be utilized for the delay mentioned. It is also to be understood that the delay means is not limited to a type utilizing an image memory. According to the color television image display apparatus of the present invention, as described herein-above, a video signal is delayed by a delay means in conformity with the time required for generation of an image quality control signal, whereby it is rendered possible to eliminate the known disadvantage that an automatic image quality adjustment is delayed from the video output to be adjusted, thereby averting an incongruous visual impression that may otherwise be given to a television viewer due to some sudden change in the image being displayed.

Claims: A colour television image display apparatus comprising: a video signal processing circuit (5) for controlling luminance signal of an input video signal fed thereto prior to display; means (3,4) for supplying a video control signal to the video signal processing circuit (5) for controlling said luminance signal, and including sampling means (3) for dividing every field of the input video signal and providing a plurality of digital data samples of the video signal level, and an arithmetic processing means (4) supplied with said digital data samples from said sampling means (3) for generating therefrom the video control signal to adjust the luminance signal of the displayed video image, a signal delay means (10) for delaying the input video signal for a time substantially equal to the time required for the arithmetic processing means (4) to generate the video control signal, so that the phase of the video signal is substantially coincident with the phase of said video control signal supplied to said video signal processing circuit (5) ; characterised by said video signal processing circuit controlling the amplification level of said luminance signal and said signal delay means delaying the input video signal in response to a timing signal from the arithmetic processing means (4) said signal delay means (10) consisting of an analog-to-digital converter (11) receiving the input video signal and producing therefrom digital video data, a field memory (12) for storing said digital video data, a digital-to-analog converter (13) connected in series and a memory controller (14) connected to receive the timing signal from said arithmetic processing means (4) for controlling said field memory (12) to read out said digital video data with an output timing substantially coincident with the output timing of the video control signal.

Inventors: ODA OSAMU, ODA, OSAMU
Applicants: SONY CORP, SONY CORPORATION
Application year: 1991
Main classification: H04N5
IPC codes: H04N5, H04N17, H04N9