Field-effect transistor having a vertical structure and method of manufacturing the same

Abstract: On a semiconductor substrate (1) are formed a plurality of pedestal regions (3₁ to 3₇) which are of the same conductivity type as the semiconductor substrate. Insulating layers (4) are formed on side surfaces of the pedestal regions. On the insulating layers are formed gate electrodes (5) which are connected together. First and second regions (6a, 6b) are formed within top portions of the pedestal regions and the semiconductor substrate. The first and second regions serve as source/drain regions and are of the opposite conductivity type to the semiconductor substrate. The first regions (6a), the second regions (6b) and the gate electrodes (5) function to form a single transistor because the gate electrodes are connected together.

Description: The present invention relates to a semiconductor device having an insulated gate transistor, e.g., a MOS transistor and, more particularly, to a semiconductor device with improved current drivability. More especially, the present invention relates to a semiconductor device with an insulated gate transistor comprising: a semiconductor substrate, a pedestal region having side walls formed on said semiconductor substrate, said pedestal region and said semiconductor substrate having the same conductivity type, insulating layers formed on said side walls of said pedestal region, a gate electrode formed on said insulating layers, and a first region formed within said semiconductor substrate and adjoining the side walls of said pedestal region and a second region formed within a top portion of said pedestal region, said first region and said second region serving as source and drain regions respectively, said first and second region having a conductivity types opposite to the conductivity type of said semiconductor substrate. Such a semiconductor device is disclosed in International Electron Devices Meeting, December 1988, pages 222-255. A conventional MOS-transistor structure will be described with reference to Figs. 8 and 9. Fig. 9 is a plan view of the conventional MOS transistor and Fig. 8 is a cross-sectional view taken along line 8 - 8 of Fig. 8. In Fig. 8, an isolation region 102 is formed on the major surface of a p-type substrate 101. In regions isolated by the isolation region are formed n-type source/drain regions 103 1 and 103 2 . A gate insulating layer 104 is formed on the channel region between the source/drain regions 103 1 and 103 2 . A gate electrode 105 is formed on the gate insulating layer 104. As shown in Fig. 9, the source/drain regions 103 1 and 103 2 are formed on both sides of the gate electrode 105. The width L of the gate electrode 105 is called the gate length and the width W of each of the source/drain regions 103 1 and 103 2 in the direction normal to the direction of the channel is called the channel width. Under the condition that Vd > V G - V T the current drivability Id of the MOS transistor is expressed by Id = (W/2L) × µCox (V G - V T ) 2 where L stands for the channel length, W stands for the channel width, µ stands for mobility, Cox stands for capacitance of the gate insulating layer, and Vd, V G and V T stand for a drain voltage, a gate voltage and a gate threshold voltage, respectively. To produce a MOS transistor requiring great current drivability Id, the channel width W in expression (1) is currently made large. With such an approach, however, an increase of the channel width W results in an increase of the area of the MOS structure, thus making a fine structure of the device difficult. For this reason, a transistor has been developed in which a pedestal region is provided between source and drain regions to protrude from a semiconductor substrate and a gate electrode is formed on side walls of the pedestal region. This transistor is useful for making the device structure fine, but still it has no sufficient current drivability. Reference is also made to IEEE ED-36, no. 11 pages 2605-2606, "High Speed and Compact CMOS", which discloses a Surrounding Gate Transistor (SGT) consisting of multi-pillar silicon islands, in which the pillar side walls are used as channel regions. This multi-channel structure provide a large channel width, realising high drivability even with a small occupied area. It is therefore an objection of the present invention to provide a semiconductor device which permits its channel width to be increased for increased current drivability and its integration density to be increased. According to the invention there is provide a semiconductor device as defined in the second paragraph of the specification, which device is characterised in that said pedestal region is one of a plurality of such pedestal regions; said pedestal regions are arranged in rows, said pedestal regions in each row being arranged at intervals of LD, said rows being arranged at intervals of LE, and said gate electrodes have a thickness in the direction of said rows of LF, the pedestal regions of each row being arranged with one pitch defined between any two successive centers of the pedestal regions, the centers of the pedestal regions in each row being staggered by a half pitch length relative to the centres of pedestal regions of an adjacent row; the intervals LD and LE and the thickness LF are related such that LD≥2LF≥LE; said first region adjoins the side walls of each pedestal region; and said gate electrodes are connected together. With this construction, a plurality of transistors are formed having gate electrodes on side surfaces of the pedestal regions. The transistors function as a single transistor because their gate electrodes are connected together. Therefore, the channel width of one transistor can be increased, thereby providing high current drivability. In addition, since the gate electrodes are formed on the side surfaces of the pedestal regions, the transistor of the invention permits high-density integratior and moreover the channel width to be increased with a small device area. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figs. 1A, 1B and 1C are plan views, in the order of steps of manufacture, of a MOS transistor with improved current drivability in accordance with a first embodiment of the present invention; Figs. 2A, 2B and 2C are cross-sectional views taken along lines 2A - 2A, 2B - 2B and 2C - 2C of Figs. 1A, 1B and 1C, respectively; Fig. 2D is a sectional view for use in explanation of a relation between the width of a pedestal region an the width of a depletion layer; Fig. 3 is a plan view illustrating an exemplary arrangement of pedestal regions; Figs. 4A, 4B and 4C are plan views, in the order o steps of manufacture, of a MOS transistor with improved current drivability in accordance with a second embodiment of the present invention; Figs. 5A, 5B and 5C are cross-sectional views take along lines 5A - 5A, 5B - 5B and 5C - 5C of Figs. 4A, 4B and 4C, respectively; Figs. 6A, 6B and 6C are plan views, in the order of steps of manufacture, of a MOS transistor with improved current drivability in accordance with a third embodiment of the present invention; Figs. 6D and 6E illustrate steps of manufacture of contact holes of a MOS transistor with improved current drivability of the present invention in accordance with mask alignment; Figs. 7A, 7B and 7C are cross-sectional views taken along lines 7A - 7A, 7B - 7B and 7C - 7C of Figs. 6A, 6B and 6C, respectively; Figs. 7D and 7E are cross-sectional views taken along lines 7D - 7D and 7E - 7E of Figs. 6D and 6E, respectively; Fig. 8 is a cross-sectional view of a conventional MOS transistor; and Fig. 9 is a plan view of the MOS transistor of Fig. 8. The preferred embodiments of the present invention will be described with reference to accompanying drawings. As illustrated in Figs. 1A and 2A, an isolation region 2 is formed on, for example, a p-type substrate 1 by means of, for example, a technique called LOCOS (localized oxidation of silicon). Subsequently, pedestal regions 3 1 to 3 7 protruding from the surface of the substrate 1 are formed in rows on a device region 1 by means of, for example, known selective epitaxial growth (SEG). More specifically, the pedestal regions 3 3 to 3 5 are arranged at regularly spaced intervals along the row of the pedestal regions 3 1 and 3 2 which are also arranged at regularly spaced intervals. The pedestal regions 3 6 and 3 7 are also arranged at regularly spaced intervals along the row of the pedestal regions 3 1 and 3 2 . The rows of pedestal regions have an equal space between adjacent pedestal regions. The space LD between pedestal regions is shorter than the length LA of each pedestal region. The spaced LE between adjacent rows is shorter than the space LD between adjacent pedestal regions. Next, as illustrated in Figs. 1B and 2B, an oxide layer, serving as a gate insulating layer 4, is formed over the surface of the device region 1 1 including surfaces of the pedestal regions 3 1 to 3 7 by means of, for example, thermal oxidation. In subsequent step, a polysilicon layer is deposited over the entire surface of the resultant structure by means of, for example, chemical vapor deposition (CVD). Subsequently, the polysilicon layer is etched by means of, for example, RIE which is known as an anisotropic etching technique so that it may remain only on side surfaces of the pedestal regions 3 1 to 3 7 , thereby forming gate electrodes 5. The gate electrodes 5 formed on side surfaces of the pedestal regions 3 1 to 3 7 are linked together and serve as a single gate electrode in the device region 1 1 . At this point, a description is made of a method of shaping the gate electrodes 5 into such a form as described above. Fig. 3 is a schematic representation of a plan view of the device in the state of Fig. 1B. First, examples of numeric values of the pedestal regions 3 1 to 3 7 will be described. The length LA and width LB of the pedestal regions are about 1.4 µm and 0.5 µm, respectively. The gate insulating layer 4 (not shown in Fig. 3) formed on the surfaces of the pedestal regions has a thickness of about 100 nm and the gate electrode has a thickness LF of about 0.3 µm. Assuming that the space LE between the rows of pedestal regions is filled up with the gate electrode 5, it may be set to two or less times the thickness LF of the gate electrode 5. Since the thickness LF of the gate electrode 5 is 0.3 µm as described above, the space LE may be 0.6 µm or less. In this embodiment, to ensure a sufficient thickness of the gate electrode 5 on the gate insulating layer 4 between pedestal regions, the space LE is set to be, for example, of the order of 0.5 µm taking some allowance into account. To form an opening CH, each side of which having a length of LG, among the four pedestal regions 3 1 , 3 3 , 3 4 and 3 6 , it is required that the space LD between the pedestal regions 3 4 and 3 3 arranged in a row be set to at least twice the thickness LF of the gate electrode 5. Since the thickness LF of the gate electrode 5 is 0.3 µm, if the space LD is 1.0 µm, then the length LG of each side of the opening CH will be LG = 1.0 - (0.3 + 0.3) = 0.4 µm Being very thin, the thickness of the gate insulating layer 4 is neglected here. Since the length LA of each of the pedestal regions 3 1 , 3 3 and 3 4 is 1.4 µm, it is required, to secure the spacing LD of 1.0 µm between the pedestal regions 3 3 and 3 4 , that the length LC of overlap between the pedestal regions 3 1 and 3 3 (3 4 ) be LC = (1.4 - 1.0)/2 = 0.2 µm Since a pedestal region in one row overlaps a pedestal region in another row and the space LE between rows of pedestal regions is set to two or less times that the thickness of the gate electrode 5, the space between each of the pedestal regions and the other can be filled up with the gate electrode 5. Thus, the single gate electrode 5 will suffice for the pedestal regions 3 1 to 3 7 arranged in rows. As illustrated in Fig. 1B, a mask formed of, for example, a photo resist may be provided on the polysilicon layer 5 formed on the isolation region 2 to thereby form a contact hole 5 1 . Subsequently, as illustrated in Figs. 1B and 2B, n-type impurities of, for example, arsenic, which are opposite in conductivity type to the substrate 1, are implanted into the substrate 1 and top portions of the pedestal regions 3 1 to 3 7 using the gate electrode 5 and the isolation region 2 as a mask, whereby source/drain regions 6a and 6b are formed within the substrate and the top portions of the pedestal regions. Subsequently, as illustrated in Figs. 1C and 2C, an oxide layer 7 is formed over the entire surface by means of, for example, CVD. Then, the oxide layer 7 is subjected to anisotropic etching by means of, for example, RIE so that the oxide layer is left on the side walls of the pedestal regions. Thus, the gate electrode 5 is insu-lated from other conductive regions by the oxide layer 7. The removal of the oxide layer 7 to expose the surface of the substrate 1 and the top portions of the pedestal regions 3 1 to 3 7 permits contact holes 8 to be formed on a self-alignment basis. Subsequently, a contact hole (not shown) communicating with the contact area 5 1 of the gate electrode 5 is formed in the oxide layer 7. Next, a conductive layer which is in contact with the source/drain regions 6a and 6b is formed and then patterned in accordance with a predetermined wiring pattern, and the entire surface of the resultant structure is covered with a surface protective film, whereby a MOS transistor with high current drivability is produced. There is a possibility that source connection and drain connection are short-circuited in forming conductive layers for connection not shown. Where the use of one conductive layer is difficult for connection, multi-layer interconnection using two conductive layers may be employed. The channel region of the MOS transistor according to the first embodiment is formed of the inside side walls of the pedestal regions 3 1 to 3 7 . The MOS transistor may operate with the diffusion layers 6a within the semiconductor substrate 1 as source/drain and the diffusion layers 6b of the pedestal regions 3 1 to 3 7 as drain/source or with one of the diffusion layers 6a as source, the other as drain and the diffusion layers 6b of the pedestal regions as a conductive portion for channel-to-channel connection. In Fig. 3, the channel width W of one pedestal region is given by W = 2(LA + LB) In the present embodiment, there are plural pedestal regions in one device region. Assuming the number of the pedestal regions to be n, then the channel width W per device will be W = 2n (LA + LB) Moreover, according to the present embodiment, the minimum spacing LE between rows of the pedestal regions is selected to be two or less times that the thickness LF of the gate electrode 5 and the pedestal regions in the central row overlap the pedestal regions in other rows, thereby permitting a single gate electrode 5 to connect all of the pedestal regions together. As illustrated in Fig. 2D, a depletion layer is produced within the pedestal region by the gate electrode. By relating the width xj of the depletion layer and the width LB of the pedestal region such that LB ≦ 2xj, it becomes possible to prevent the device area from increasing and produce a MOS transistor having high current drivability. The gate bias and impurity concentration of the MOS transistor constructed as described above are, for example, 3V, 1 × 10 16 cm- 3 , respectively. Figs. 4A, 4B and 4C are plan views, in the order of steps of manufacture, of a semiconductor device according to a second embodiment of the present invention and Figs. 5A, 5B and 5C are cross-sectional views of Figs. 1A, 1B and 1C. Like reference characters are used to designate corresponding parts to those in the first embodiment. As illustrated in Figs. 4A and 5A, an isolation region 2 is formed on the major surface of, for example, a p-type substrate 1 by means of, for example, LOCOS. Next, a concavity 9 is formed within the substrate 1 by means of a photoetching method using a photo resist. At this time, the substrate 1 is selectively etched so that pedestal regions 3 8 to 3 14 protruding from the bottom of the concavity 9 are formed. As shown, the pedestal regions 3 10 to 3 12 are arranged at regularly spaced intervals along the pedestal regions 3 8 and 3 9 at regu-larly spaced intervals, and moreover the pedestal regions 3 13 and 3 14 are arranged at regularly spaced intervals along the pedestal regions 3 10 to 3 12 . The pedestal regions 3 8 to 3 14 are arranged in substantially the same relation as in the first embodiment. As illustrated in Figs. 4B and 5B, an oxide layer serving as a gate insulating layer is subsequently formed over the surface of the device region including the surfaces of the pedestal regions by means of, for example, thermal oxidation. Subsequently, onto the entire surface of the resultant structure is deposited by means of, for example, CVD a polysilicon layer which is then subjected to anisotropic etching by means of, for example, RIE to leave it on side walls of the pedestal regions 3 8 to 3 14 and concavity 9, thereby forming gate electrodes 5. In the second embodiment as well, the area between each of the pedestal regions and another is filled up with the gate electrodes 5 as in the first embodiment. The gate electrodes 5 formed on the side walls of the pedestal regions 3 8 to 3 14 and concavity 9 are connected together to serve as a single gate electrode in the device region. As illustrated in Fig. 4B, a mask formed of, for example, a photo resist may be provided on the polysilicon layer 5 formed on the isolation region 2 to thereby form a contact hole 5 1 . Subsequently, n-type impurities of, for example, arsenic, which are opposite in conductivity type to the substrate 1 are implanted into the substrate 1 and the pedestal regions 3 8 to 3 14 using the gate electrode 5 and the isolation region 2 as a mask, whereby source/drain regions 6a and 6b are formed within the substrate portion as the bottom of the concavity, the substrate portion between the isolation region and the concavity and the top portions of the pedestal regions. Subsequently, as illustrated in Figs. 4C and 5C, an oxide layer 7 is formed over the entire surface of the resultant structure by means of, for example, CVD and the resultant oxide layer is subsequently subjected to anisotropic etching by means of, for example, RIE so that the oxide layer is left on the side walls of the pedestal regions 3 8 to 3 14 and the concavity 9. At this time the electrode 5 extending from the substrate 1 to the isolation region 2 is covered with the oxide layer 7 so that it may not exposed. Thus, the gate electrode 5 is insulated from other conductive regions. The removal of the oxide layer 7 to expose the surface of the substrate 1 and the surfaces of the pedestal regions 3 8 to 3 14 permits contact holes 8 to be formed on a self-alignment basis. Subsequently, a contact hole (not shown) communicating with the contact area 5 1 of the gate electrode 5 is formed in the oxide layer 7. Next, a conductive layer which is in contact with the source/drain regions 6a and 6b is formed and then patterned in accordance with a predetermined wiring pattern. Subsequently, the entire surface of the resultant structure is covered with a surface protective film, whereby a MOS transistor according to the second embodiment is produced. As with the first embodiment, the second embodiment can also prevent the device area from increasing and produce a MOS transistor having high current drivability. Figs. 6A, 6B and 6C are plan views, in the order of steps of manufacture, of a semiconductor device according to a third embodiment of the present invention, and Figs. 7A, 7B and 7C are cross-sectional views of Figs. 6A, 6B and 6C. Like reference characters are used to designate corresponding parts to those in the first embodiment. As illustrated in Figs. 6A and 7A, an isolation region 2 is formed on the major surface of, for example, a p-type substrate 1 by means of, for example, LOCOS. Next, a concavity 9 is formed in the substrate 1 by means of a photoetching method using, for example, a photo resist. At this time, the substrate 1 is selectively etched so that pedestal regions 3 15 to 3 27 protruding from the bottom of the concavity 9 are formed. Of the pedestal regions 3 15 to 3 27 the regions 3 15 , 3 16 , 3 17 , 3 20 , 3 22 , 3 25 and 3 27 are integral with the side walls of the substrate 1. As shown, the pedestal regions 3 15 , 3 16 and 3 17 are arranged at regularly spaced intervals. The pedestal regions 3 18 and 3 19 are arranged along the pedestal regions 3 15 to 3 17 . The spacing between the pedestal regions 3 18 and 3 19 is equal to that in the row of the pedestal regions 3 15 to 3 17 . The pedestal regions 3 20 to 3 22 , pedestal regions 3 23 and 3 24 and pedestal regions 3 25 to 3 27 are arranged at regu-larly spaced intervals as with the pedestal regions 3 15 to 3 19 . As illustrated in Figs. 6B and 7B, an oxide layer serving as a gate insulating layer 4 is subsequently formed over the surface of the device region including the surfaces of the pedestal regions 3 15 to 3 27 by means of, for example, thermal oxidation. Subsequently, a polysilicon layer serving as gate electrode 5 is deposited onto the entire surface of the resultant structure by means of, for example, CVD. The polysilicon layer is then subjected to anisotropic etching by means of, for example, RIE so that it is left on side walls of the pedestal regions 3 15 to 3 27 , thereby forming gate electrodes 5. The gate electrodes 5 formed on the side walls of the pedestal regions 3 15 to 3 27 are all connected together to serve as a single gate electrode in the device region. In the third embodiment as well, the area between each of the pedestal regions and another is filled up with the gate electrode 5 as in the first and second embodiments. The gate electrode 5 may be formed in the same manner as the first embodiment. As illustrated in Fig. 6B, the polysilicon layer 5 formed on the isolation region 2 may be masked by, for example, a photo resist to form a contact hole 51. Subsequently, n-type impurities of, for example, arsenic, which are opposite in conductivity type to the substrate 1 are implanted into the substrate 1 and top portions of the pedestal regions 3 18 to 3 24 using the gate electrode 5 and the isolation region 2 as a mask, whereby source/drain regions 6a and 6b are formed within the substrate portion as the bottom of the concavity, the substrate portion between the isolation region 2 and the concavity 9 and the top portions of the pedestal regions 3 18 to 3 24 . Subsequently, an oxide layer 7 is formed over the entire surface of the resultant structure by means of, for example, CVD and the resultant oxide layer is subsequently subjected to anisotropic etching by means of, for example, RIE so that the oxide layer is left on the side walls of the pedestal regions 3 18 to 3 27 as illustrated in Figs. 4C and 5C. At this time electrode 5 extending from the substrate 1 to the isolation region 2 is covered with the oxide layer 7 so that it may not exposed. Thus, the gate electrode 5 is insulated from other conductive regions. If, in this state, the surface of the substrate 1 and the surfaces of the pedestal regions 3 18 to 3 24 are exposed, contact holes 8 can be formed on a self-alignment basis. Subsequently, a contact hole (not shown) communicating with the contact area 5 1 of the gate electrode 5 is formed in the oxide layer 7. Next, conductive layers which are in contact with the source/drain regions 6a and 6b is formed and then patterned in accordance with a predetermined wiring pattern. Subsequently, the entire surface of the resultant structure is covered with a surface protective film, whereby a MOS transistor according to the third embodiment is produced. According to the third embodiment, a MOS transistor with higher current drivability and smaller surface area than those of the second and third embodiments can be produced. In the case of the first, second and third embodiments described above, the contact holes for the source/drain diffusion layers 6a and 6b are formed using a self aligned process. However, the contact holes may be formed by a photoetching method using a photo resist, that is, by a masking process. Hereinafter an example of the masking process for forming the contact holes will be described on the basis of the semiconductor device in accordance with the third embodiment. First, as illustrated in Figs. 6D and 7D, an oxide layer 7 is formed over the entire surface of a device which has been produced in accordance with the same steps as those used for producing the structure shown in Figs. 6B and 7B by means of, for example, CVD. Subsequently, a contact hole 9 communicating with a source/diffusion layer 6a and a contact hole 10 communicating with a source/drain diffusion layer 6b are formed in the oxide layer 7 by means of a photoetching method using a photo resist. The contact holes 9 and 10 are alternately formed in alignment with one another. As can be seen from Fig. 6D, the contact holes 9 are in alignment with one another along a diagonal line and so are the contact holes 10. By arranging the contact holes 9 and 10 in this way, it becomes easy to arrange lines connected to the source/drain diffusion layers. At this point, a contact hole which communicates with the contact area 5 1 of the gate electrode 5 may be formed in the oxide layer 7. Subsequently, as illustrated in Figs. 6E and 7E, aluminum is deposited over the entire surface of the resultant structure by means of, for example, sputtering. Subsequently, the layer of aluminum is patterned with the result that metal lines 11 which contact the source/drain diffusion layers 6a through the contact holes 9 and metal lines 12 which contact the source/drain diffusion layers 6b through the contact holes 10 can be formed. The metal lines can be formed by a single layer of aluminum. In the first through third embodiments, a MOSFET is produced. Alternatively, a MESFET which is formed on a GaAs substrate may be produced. In this case, of course, there is no need for a gate insulating layer. Also, since GaAs itself is semi-insulating, an isolation region which is represented by a field insulating layer need not necessarily be formed.

Claims: A semiconductor device with an insulated gate transistor, comprising: a semiconductor substrate (1); a pedestal region (3 1 to 3 21 ) having side walls formed on said semiconductor substrate (1), said pedestal region and said semiconductor substrate having the same conductivity type; an insulating layer (4) formed on said side walls of said pedestal region; a gate electrode (5) formed on said insulating layer; and a first region (6a) formed within said semiconductor substrate and adjoining the side walls of said pedestal region and a second region (6b) formed within a top portion of said pedestal region, said first region and said second region serving as source and drain regions respectively, said first and second regions having a conductivity type opposite to the conductivity type of said semiconductor substrate; characterised in that said pedestal region (3 1 ) is one of a plurality of such pedestal regions (3 1 to 3 21 ); said pedestal regions are arranged in rows, said pedestal regions in each row being arranged at intervals of LD, said rows being arranged at intervals of LE, and said gate electrodes have a thickness in the direction of said rows of LF, the pedestal regions of each row being arranged with one pitch defined between any two successive centers of the pedestal regions, the centers of the pedestal regions in each row being staggered by a half pitch length relative to the centres of pedestal regions of an adjacent row; the intervals LD and LE and the thickness LF are related such that LD≥2LF≥LE; said first region (6a) adjoins the side walls of each pedestal region; and said gate electrodes (5) are connected together. A device according to claim 1, characterised in that a minimum width of said pedestal regions 3 1 to 3 21 is LB and the width of a depletion region in each of said pedestal regions is xj, and the minimum pedestal region width LB and the depletion region width xj are related such that LB ≤ 2 x j. A device according to claim 1, characterised in that said semiconductor substrate (1) has a concavity (9), and the pedestal regions are in the concavity (9). A device according to claim 3, characterised in that some of said pedestal regions (3 10 , 3 12 ) are each formed on an inner sidewall surface of the concavity (9). A device according to any preceding claim, characterised in that said first regions (6a) are connected together by a first conductive layer (11) and said second regions (6b) are connected together by a second conductive layer (12). A device according to claim 5, characterised in that said first and second conductive layers (11,12) are arranged diagonally with respect to a direction in which said pedestal regions (3 15 to 3 27 ) are arranged.

Inventors: MIZUNO TOMOHISA, MIZUNO, TOMOHISA, MIZUNO, TOMOHISA, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: H01L29
IPC codes: H01L29