Multipurpose analog front-end circuit

Abstract: An analog front-end circuit has a low-group low-pass filter and a low-group high-pass filter connected in series, a high-group low-pass filter and a high-group high-pass filter connected in series, and switching means enabling the low-group high-pass filter and high-group low-pass filter to be connected in series, thus providing three bandpass filters with different passbands.

Description: An analog front end is a circuit that interfaces between an analog signaling system such as an analog telephone line and digital signal-processing circuits such as the modulating and demodulating circuits of a modem. The analog front end of a half-duplex 1200-bit/s modem conforming to CCITT recommendation V.23, for example, has a bandpass filter comprising a low-pass filter (LPF) and a high-pass filter (HPF) connected in series, the LPF having a cutoff frequency of 2300 Hz and the HPF having a cutoff frequency of 1100 Hz. The combined passband is accordingly 1100 to 2300 Hz. The analog front end of a full-duplex modem has two bandpass filters, each comprising an LPF and an HPF connected in series. A typical modem for a personal computer supports CCITT recommendations V.22 and V.22bis for 1200-bit/s and 2400-bit/s data rates: the low-group bandpass filter has a passband of 800 to 1600 Hz, while the high-group bandpass filter has a passband of 2000 to 2800 Hz. The low-group bandpass filter is used for transmitting and the high-group bandpass filter for receiving (or vice versa), permitting communication in both directions at once. A full duplex modem front end circuit is known from FR-A-2618037. In previous modems that supported both half-duplex and full-duplex communications (referred to hereinafter as multi-standard modems), the analog front-end circuits had three bandpass filters, each comprising an LPF and an HPF connected in series as described above. Two of the bandpass filters were used for full-duplex communications and the third bandpass filter was used for half-duplex communications. A problem is that the circuits are complex and expensive to fabricate. Thus a multi-standard modem incorporating three bandpass filters is significantly more costly than a full-duplex modem having only two bandpass filters. Even when the analog front end is integrated onto a single semiconductor chip, with three separate bandpass filters the chip becomes large in size, so fewer chips can be fabricated from a single semiconductor wafer. The result is a rise in the cost per chip, and in the cost of the modem (or other equipment) in which the chip is employed. An object of the present invention is accordingly to simplify the structure of a multipurpose analog front-end circuit. Another object is to reduce the cost of a multipurpose analog front-end circuit. Yet another object is to reduce the size of a multipurpose analog front-end circuit. According to the present invention, there is provided a front end circuit for a full/half duplex modem, including a filter circuit comprising a first low-pass filter, a second low-pass filter, a first high-pass filter, a second high-pass filter and switching means for selectively configuring the filter circuit for full or half duplex communication, wherein, by means of the switching means being in a first configuration, the first low-pass filter and first high-pass filter are connected in series and the second low-pass filter and first high-pass filter are connected in series to form two band-pass filters corresponding respectively to high and low channels for full duplex communication, and, by means of the switching means being in a second configuration, the first low-pass filter and the second high-pass filter are connected in series to form a band-pass filter corresponding to a channel for half duplex communication. Embodiments of the present invention will now be described, by way of example, with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of a novel analog front-end circuit; Fig. 2 is a circuit diagram of the D/A converter in Fig. 1; Fig. 3 is a circuit diagram of the low-group LPF in Fig. 1; Fig. 4 is a circuit diagram of the A/D converter in Fig. 1; Fig. 5 is a block diagram of a modem using the analog front-end circuit of Fig. 1; and Fig. 6 is a block diagram of another novel analog front-end circuit. Novel analog front-end circuits embodying the present invention will be described with reference to Figs. 1 and 6. Circuit diagrams of their major components will be shown in Figs. 2, 3, and 4. Their operation will be explained with reference to a multi-standard modem employing the first novel analog front-end circuit, illustrated in Fig. 5. All of these drawings are exemplary in nature and do not restrict the scope of the invention, which should be determined solely from the appended claims. The novel analog front-end circuit 21 in Fig. 1 comprises a digital-to-analog (D/A) converter 22, switching means 23 and 24, an analog input terminal 25, a low-group bandpass filter 26, a high-group bandpass filter 27, switching means 28, 29, and 30, an analog output terminal 31, and an analog-to-digital (A/D) converter 32. The switching means 23 connects either the D/A converter 22 or the analog input terminal 25 to the low-group bandpass filter 26. The switching means 24 connects either the D/A converter 22 or the analog input terminal 25 to the high-group bandpass filter 27. The switching means 29 connects either the low-group bandpass filter 26 or the high-group bandpass filter 27 to the analog output terminal 31. The switching means 30 connects either the low-group bandpass filter 26 or the high-group bandpass filter 27 to the A/D converter 32. The low-group bandpass filter 26 comprises an LPF 26a that receives input from the switching means 23, and a HPF 26b that feeds output to the switching means 29 and 30. The output of the low-group LPF 26a can be fed as input to the low-group HPF 26b through the switching means 28. The high-group bandpass filter 27 comprises a high-group LPF 27a that receives input from the switching means 24, and a high-group HPF 27b that feeds output to the switching means 29 and 30. The output the high-group LPF 27a is connected directly as input to the high-group HPF 27b, and can also be connected as input to the low-group HPF 26b through the switching means 28. The switching means 28 thus selects the output of either the low-group LPF 26a or the high-group LPF 27a for input to the low-group HPF 26b. Next the structure of the individual elements in Fig. 1 will be described in more detail. With reference to Fig. 2, the D/A converter 22 is a well-known circuit comprising a switching array 22a, a resistor array 22b, an operational amplifier 22c, and a feedback resistor 22d. To briefly describe the operation of this circuit, switching elements in the switching array 22a are controlled by respective bits of a digital input signal. The resistors in the resistor array 22b have resistance values in the ratio of successive powers of two. The operational amplifier 22c adds the currents flowing through those resistors that the switching array 22a connects to the power supply (Vcc) to produce an analog output signal representative of the digital input signal. The switching means 23, 24, 28, 29, and 30 comprise, for example, MOS transistors controlled by control signals applied to their grate electrodes. The invention is not restricted to MOS transistor switching means, however; bipolar transistors or other types of switching elements may be used instead. With reference to Fig. 3, the low-group LPF 26a is a switched-capacitor filter of the dual op-amp type, having: operational amplifiers 26a-1 and 26a-2, input capacitors 26a-3 and 26a-4, hold capacitors 26a-5 and 26a-6, feedback capacitors 26a-7 and 26a-8, and a capacitor 26a-9; switching means 26a-10 to 26a-14 that switch on and off under control of a clock signal ; and switching means 26a-15 to 26a-19 that switch on and off under control of the inverted clock signal  . This circuit is well known, so a detailed description of its interconnections and operation will be omitted. The capacitances of the capacitors 26a-3 to 26a-9 and other circuit parameters are set so that the passband of the low-group LPF 26a is 0 to 1600 Hz. The low-group HPF 26b, the high-group LPF 27a, and the high-group HPF 27b are similar in structure to the low-group LPF 26a, but have different passbands. The passband of the low-group HPF 26b is 800 Hz to infinity. The passband of the high-group LPF 27a is 0 to 2800 Hz. The passband of the high-group HPF 27b is and 2000 Hz to infinity. The passband of the low-group bandpass filter 26 is accordingly 800 to 1600 Hz, while the passband of the high-group bandpass filter 27 is 2000 to 2800 Hz. With reference to Fig. 4, the A/D converter 32 comprises, for example, a comparator 32a, a control circuit 32b, a successive approximations register 32c, and a D/A converter 32d. A detailed description of this well-known circuit will be omitted. Suffice it to say that an analog input signal received from the low-group HPF 26b or the high-group HPF 27b in Fig. 1 is converted to a digital signal output from the successive approximations register 32c in Fig. 4. Fig. 5 shows a modem 41 for interfacing between a data terminal equipment (DTE) 42 such as a personal computer and an analog signal line 43 such as a telephone line. The modem 41 comprises the novel analog front-end circuit 21, which is denoted using the same reference numerals as in Fig. 1, a digital signal-processing section 50, and a network control circuit 60. The digital signal-processing section 50 comprises a DTE interface 51, a modulating circuit 52, a demodulating circuit 53, a control circuit 54, and a clock circuit 55. The output of the modulating circuit 52 is fed to the input of the D/A converter 22 in the analog front-end circuit 21. The output of the A/D converter 32 in the analog front-end circuit 21 is fed to the demodulating circuit 53. The control circuit 54 supplies control signals collectively denoted Sc that control the switching means 23, 24, 28, 29, and 30 of the analog front-end circuit 21. The analog input terminal 25 and analog output terminal 31 of the analog front-end circuit 21 are connected to the network control circuit 60, which is connected to the analog signal line 43. The operation of the analog front-end circuit 21 will now be described with reference to Fig. 5, treating the cases of full-duplex communication and half-duplex communication separately. In full-duplex communication, the switching means 28 connects the output of the low-group LPF 26a to the input of the low-group HPF 26b (the opposite setting to the one shown in the drawing). The other switching means are set according to whether the modem 41 operates in originate mode or answer mode. In originate mode the modem 41 transmits low-group signals and receives high-group signals, so the switching means 23, 24, 29, and 30 are set as follows. The switching means 23 connects the output of the D/A converter 22 to the low-group LPF 26a. The switching means 24 connects the analog input terminal 25 to the high-group LPF 27a. The switching means 29 connects the output of the low-group HPF 26b to the analog output terminal 31. The switching means 30 connects the output of the high-group HPF 27b to the A/D converter 32. In originate mode, transmit data generated by the DTE 42 is fed through the DTE interface 51 to the modulating circuit 52 where it modulates a digital carrier signal. The digitally modulated signal is converted to an analog signal by the D/A converter 22, filtered by the low-group LPF 26a and low-group HPF 26b to remove unwanted frequency components outside the range from 800 to 1600 Hz, sent via the analog output terminal 31 and the network control circuit 60 to the analog signal line 43, and transmitted over the analog signal line 43 to a distant device (not shown in the drawing). Signals received from the distant device are fed from the analog signal line 43 via the network control circuit 60 and the analog input terminal 25 to the switching means 24, filtered by the high-group LPF 27a and the high-group HPF 27b to remove unwanted frequency components outside the range from 2000 to 2800 Hz, then converted to a digital signal by the A/D converter 32. This digital signal is demodulated by the demodulating circuit 53 to recover the receive data, which is sent via the DTE interface 51 to the DTE 42. The transmit and receive signals follow separate paths between the DTE 42 and the network control circuit 60. Data can therefore be transmitted and received simultaneously. When the modem 41 operates in full-duplex answer mode the settings of the switching means 23, 24, 29, and 30 are reversed. The operation is exactly the same as before except that the transmit signal is filtered by the high-group LPF 27a and the high-group HPF 27b, and the receive signal is filtered by the low-group LPF 26a and the low-group HPF 26b. In half-duplex communication, the switching means 28 connects the output of the high-group LPF 27a to the input of the low-group HPF 26b. The modem 41 now operates in either transmit mode or receive mode; it does not transmit and receive simultaneously. In half-duplex transmit mode, the switching means 24 connects the output of the D/A converter 22 to the high-group LPF 27a, and the switching means 29 connects the output of the low-group HPF 26b to the analog output terminal 31, as shown in the drawing. Transmit data generated by the DTE 42 is converted to an analog signal by the modulating circuit 52 and the D/A converter 22 as described in full-duplex communication, filtered by the high-group LPF 27a and the low-group HPF 26b, then sent via the network control circuit 60 to the analog signal line 43. In half-duplex receive mode, the switching means 24 connects the analog input terminal 25 to the high-group LPF 27a, and the switching means 30 connects the low-group HPF 26b to the A/D converter 32. The receive signal from the analog signal line 43 is thus fed via the network control circuit 60 to the switching means 24, filtered by the high-group LPF 27a and the low-group HPF 26b, converted to a digital signal by the A/D converter 32, demodulated by the demodulating circuit 53, and furnished via the DTE interface 51 to the DTE 42. The passband of the bandpass filter used in half-duplex communications, comprising the high-group LPF 27a and the low-group HPF 26b, is 800 Hz to 2800 Hz. This is somewhat wider than the 1100-to-2300-Hz passband usually used for 1200-bit/s half-duplex communications, but if the modem is designed to be capable of 2400-bit/s communications in full-duplex mode, then at the slower rate of 1200 bits/s it is an easy matter to compensate for the signal-to-noise penalty caused by the widened half-duplex passband. Fig. 6 shows another novel analog front-end circuit. This circuit is identical to the one in Fig. 1 except for the manner in which the high-pass and low-pass filters are mutually interconnected and connected to the switching means. Elements common to both Figs. 1 and 6 are denoted by the same reference numerals. In Fig. 6 high-pass filtering is performed before low-pass filtering. Thus the low-group HPF 26b receives input from the switching means 23, feeds output directly to the low-group LPF 26a, and feeds the same output via a switching means 28a to the high-group LPF 27a. The high-group HPF 27b receives input from the switching means 24 and feeds output via the switching means 28a to the high-group LPF 27a. The output of the low-group LPF 26a and the output of the high-group LPF 27a are fed to the switching means 29 and 30. The switching means 28a, which is analogous to the switching means 28 in Fig. 1, thus selects either the output of the low-group HPF 26b or the output of the high-group HPF 27b as input to the high-group LPF 27a. The operation of the analog front-end circuit in Fig. 6 is identical to the operation of the analog front-end circuit in Fig. 1. The passbands of the low-group bandpass filter 26, the high-group bandpass filter 27, and the half-duplex bandpass filter comprising the low-group HPF 26b and the high-group LPF 27a are also the same as in Fig. 1. As is clear from Figs. 1 and 6, the novel analog front-end circuit is hardly at all more complex than a conventional analog front-end circuit for full-duplex communications, the only additional element being the switching means 28 in Fig. 1 or the switching means 28a in Fig. 6; yet the novel analog front-end circuit supports both full-duplex and half-duplex communications. The novel analog front-end circuit thus enables a multi-standard modem to be manufactured at substantially the same cost as a conventional full-duplex modem, and at a substantially lower cost than a conventional multi-standard modem. In particular, the novel analog front-end circuit can be integrated onto a semiconductor chip without increasing the chip size or driving up the per-chip fabrication cost. As will be obvious to one skilled in the art, the embodiments illustrated in Figs. 1 and 6 can be modified in various ways . Further components can be added to the analog front-end circuits in Figs. 1 and 6, such as an automatic gain control (AGC) circuit to adjust the amplitude of the filtered receive signal, or an all-pass filter for group delay equalization, for example. The invention is furthermore not restricted to the use of D/A and A/D converters and filters of the types shown in Figs. 2 to 4. Other types of filters and converters can be employed instead. The passbands of the filters can also be modified as required by the application, and the application need not be a modem as illustrated in Fig. 5: the novel front-end circuit can be applied in various other devices.

Claims: A front end circuit for a full/half duplex modem, including a filter circuit comprising a first low-pass filter (27a), a second low-pass filter (26a), a first high-pass filter (27b), a second high-pass filter (26b) and switching means (28) for selectively configuring the filter circuit for full or half duplex communication, wherein, by means of the switching means (28) being in a first configuration, the first low-pass filter (27a) and first high-pass filter (27b) are connected in series and the second low-pass filter (26a) and first high-pass filter (26b) are connected in series to form two band-pass filters (27,26) corresponding respectively to high and low channels for full duplex communication, and, by means of the switching means (28) being in a second configuration, the first low-pass filter (27a) and the second high-pass filter (26b) are connected in series to form a band-pass filter corresponding to a channel for half duplex communication. A circuit according to claim 1, wherein the cut-off frequency of the first low-pass filter (27a) is higher than that of the first high-pass filter (27b) and the cutoff frequency of the second low-pass filter (26a) is higher than that of the second high-pass filter (26b). A circuit according to claim 1 or 2, wherein the cut-off frequency of the first low-pass filter is substantially 2800Hz, the cut-off frequency of the first high-pass filter is substantially 2000Hz, the cutoff frequency of the second low-pass filter is substantially 1600Hz and the cut-off frequency of the second high-pass filter is substantially 800Hz. A circuit for a full/half duplex modem according to claim 1, 2 or 3, comprising an analogue signal input terminal (25), an analogue signal output terminal (31), a digital-to-analogue converter (22), an analogue-to-digital converter (32), a first route switching means (24) for selectively applying a signal from either the analogue signal input terminal (25) or the digital-to-analogue converter (22) to the first low-pass filter (27a), a second route switching means (23) for selectively applying a signal from either the analogue signal input terminal (25) or the digital-to-analogue converter (22) to the second low-pass filter (26a), a third route switching means (29) for selectively applying the output of either the first high-pass filter (27b) or the second high-pass filter (26b) to the analogue signal output terminal (31), and a fourth route switching means (30) for selectively applying the output of either the first high-pass filter (27b) or the second high-pass filter (26b) to the analogue-to-digital converter (32).

Inventors: FUJII SHOJI, OHTAKE HISAO, OKAMOTO SEIJI, FUJII, SHOJI, OHTAKE, HISAO, OKAMOTO, SEIJI, FUJII, SHOJI, C/O OKI ELECTRIC IND. CO. LTD., OHTAKE, HISAO, C/O OKI ELECTRIC IND. CO. LTD., OKAMOTO, SEIJI, C/O OKI ELECTRIC IND. CO. LTD.
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY CO., LTD.
Application year: 1991
Main classification: H04L5
IPC codes: H03H7, H04L5