Method of and apparatus for inspecting connection pattern on a printed circuit board

Abstract: In order to correctly detect the width of wiring pattern on a printed board, a multiple train operator is applied to image data. The multiple train operator consists of arms each having three unit arms. The binary data obtained by applying the multiple train operator to the image data is converted into a single horizontal arm and a single vertical arm. The combination of the horizontal and vertical arms corresponds to a single cross operator. The conversion into the single cross operator form is conducted through a logical operation on the binary data obtained by the multiple train operator, so that quantization errors are compensated and fine pattern defects can be detected. As a result, the width of the wiring pattern etc. are correctly obtained.

Description: BACKGROUND OF THE INVENTION THE PRESENT INVENTION relates to a method and an apparatus for inspecting a pattern on a printed circuit board. DESCRIPTION OF THE BACKGROUND ART As electronic parts have been reduced in size and in weight as well as having been improved in performance, wiring patterns on printed circuit boards have been also highly refined and integrated. Accordingly, circuit boards having narrow wiring tracks in wiring patterns and small diameters of holes are required. As to such narrowed tracks, inspection and management of widths, disconnection, or short-circuiting etc. thereof are regarded as more important than before. In optical inspection and management of the wiring pattern, a circuit board is photoelectrically scanned to obtain a wiring pattern image of the circuit board. The pattern image is binarized to obtain image data, which in turn is subjected to various types of processing for determining whether the pattern is defective or not. The binarized pattern image has been inspected with a pixel operator, as disclosed in Japanese Patent Application No. 59-74627 (1984), for example. Figures 14 to 18 show a cross operator OP as an example of pixel operators, which operator OP has four arms crossing each other. Figure 14 shows such a case where defects MIS are present in a wiring track pattern L and a vertical arm of the operator OP is located along the track L. The track width is measured with a horizontal arm crossing the track L. In the example shown in Figure 14, the track has a width of 5 pixels. If the track width is below a prescribed threshold value, the defect MIS in the track is detected. However, it may happen that the defect MIS shown in Figure 14 are not actual defects but are quantization errors caused at the edges of the track on binarizing the pattern image. Further, when a short circuit SC is obliquely caused between two vertically running tracks L as shown in Figures 15 to 17, pixels on the horizontal arm will not entirely become "1" whatever position the cross operator OP is located, and it is impossible to detect the short circuit SC. Similarly, it is also impossible to detect oblique disconnection or cut in the track L shown in Figure 18. Thus, in the inspection with the conventional cross operator OP, false information may be obtained as to pattern abnormality in wiring tracks. SUMMARY OF THE INVENTION The present invention is directed to a method of inspecting a wiring pattern formed on a printed circuit board. According to the present invention, the method comprises the steps of: (a) obtaining an image of said wiring pattern; (b) applying an image operator to the image to obtain a first data array, wherein the image operator has a plurality of operator arms each of which is formed of a plurality of pixel trains, and the first data array has a first plurality of data arms each of which is formed of a plurality of sequences of data values; (c) converting the first data array into a second data array having a second plurality of data arms each of which is formed of a single sequence of data values; and (d) inspecting the wiring pattern as a function of the second data array. Steps (a) and (d) are known per se form the prior art. Preferably, the image operator is so defined that the plurality of operator arms cross each other at the center of the image operator. In a prescribed embodiment of the present invention, the plurality of operator arms form a radial pattern. The conversion of the first data array into the second data array may be conducted through the step of applying a logical operation to the plurality of sequences of data values to obtain the single train of data values. In the preferred embodiment of the present invention, a plurality of types of logical operation are previously determined. One of the same is selected as a function of a data value at a center of the first data array which corresponds to the center of the image operator. The selected one is used to convert the plurality of sequences of data values into the single sequence of data values. In the present invention, the first data array obtained by applying the image operator represents not only the pixel data on object pixels but also represents those on the pixels neighbouring the object pixels. This is because each arm in the image operator consists of the plurality of operator arms, and a plurality of pixel sequences on the image can be taken into consideration. The first data array is converted into the second data array, in which the respective pixel data on the object line and the neighbouring lines are synthesized. Even if minor errors are present on the image data, the errors are compensated through the conversion and do not provide false information on the wiring pattern. Thus, it is possible to eliminate false information in pattern abnormality and to improve reliability of pattern inspection. The present invention also provides an apparatus operable to conduct the present method. Accordingly, an object of the present invention is to provide an improvement in pattern inspection of printed boards in which the pattern inspection is conducted at a high reliability without causing false detection as to pattern defects. These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram showing the structure of a DRC circuit; Fig. 1B is a flow chart showing operation flow of the DRC circuit 34; Fig. 2A is a block diagram showing the overall structure of a pattern inspection apparatus according to a preferred embodiment of the present invention; Fig. 2B is a block diagram showing the structure of a pattern inspection circuit 30; Figs. 3A and 3B are conceptual diagrams showing image-reading through photoelectric scanning; Fig. 4 illustrates a signal waveform obtained with an image scan reader shown in Fig. 3A and a wiring pattern obtained from the waveform; Fig. 5 is a block diagram showing the structure of a multiple sequence operator processing part 36; Fig. 6 is a conceptual diagram of the multiple sequence operator MOP; Fig. 7 is a conceptual diagram of the synthesized single cross operator DOP; Fig. 8 is a flow chart for obtaining the operator DOP from the operator MOP; Fig. 9 is a block diagram showing a processing block G in Fig. 5; Figs. 10 to 13 and Fig. 19 illustrate examples of the result of operation according to the preferred embodiment of the present invention; Figs. 14 to 18 illustrate a conventional cross oparator; and Fig. 20 illustrates an operator according to another preferred embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS A. Overall Structure and Schematic Operation Fig. 2A is a block diagram showing the overall structure of a pattern inspection apparatus according to a preferred embodiment of the present invention. A circuit board 11 to be inspected is placed on a stage 10. The circuit board 11 is fed in a carriage direction Y while the image of the circuit board 11 is read with an image reader 20 for each scanning line defined in the direction X. The image reader 20 has a plurality of CCD linear image sensors each having thousands of elements in the line direction X, and is operable to read the pattern of the printed board 11 for each pixel. The image data obtained in the image reader 20 is fed to binarizing circuits 21a and 21b. The binarizing circuit 21a generates a hole image original signal HIS O while the binarizing circuit 21b generates a pattern image original signal PIS O , details of which signals HIS O and PIS O will be described later. Both of the signals HIS O and PIS O are input to a pattern inspection circuit 30. The pattern inspection circuit 30, which has a function as described below, inspects the wiring pattern including pads, and relative positional relation between the same and holes. The result of the inspection is delivered to a central processing unit (MPU) 50. The MPU 50 controls the entire apparatus through a control system 51. The control system 51 generates X-Y addresses for specifying addresses for the image data obtained in the pattern inspection circuit 30 etc. It also supplies the X-Y addresses to a stage driving system 52, to control a carrying mechanism for the stage 10. A CRT receives a command from the MPU 50 and displays various results of operation such as a hole image. A keyboard 70 is used for inputting various instructions to the MPU 50. A defect confirming apparatus 81, a defective removing apparatus 82 and a defective position marking apparatus 83 etc. are arranged in an option part 80. The defect confirming apparatus 81 is adapted to display detected defects on the CRT 60 in the form of an enlarged image. The defective removing apparatus 82 is adapted to carry a circuit board 11 having a defect to a tray for defectives. The defective position marking apparatus 83 is adapted to directly mark a defective portion on the circuit board 11 or mark a point on a sheet corresponding to the portion. These apparatuses are optional. B. Optical Reading System Fig. 3A illustrates an example of optical reading systems which can be employed in the present invention. The optical reading system comprises the stage 10 shown in Fig. 2A and the image reader 20. Referring to Fig. 3A, light from a light source 22 is reflected by a half mirror 23, and applied onto the circuit board 11 on the stage 10. The circuit board 11 is provided with a base plate B serving as an underlayer, a track L, a hole H and a pad R surrounding the hole H. Light reflected from the circuit board 11 passes through the half mirror 23, and is incident upon the CCD 24 in the reader 20 through a lens 25. The CCD 24 reads for each scanning line the reflected light from the base plate B, the track L, the hole H and the pad R on the circuit board 11 which is fed in the carriage direction Y. Fig. 4 illustrates a graph showing a signal waveform obtained along a line A - A' in Fig. 3A and an exemplary pattern obtained by synthesizing respective signal waveforms for a two-dimensional area on the printed board 11. As shown in the signal waveform of Fig. 4, the intensity of the reflected light is relatively weak in the base plate B, and the signal level thereof is between threshold values TH1 and TH2 (TH1 < TH2). Since the wiring pattern P (the track L and the pad R) is made of a metal such as copper, the intensity of the reflected light is large on the wiring pattern, and the signal level thereof exceeds the higher threshold value TH2. From the hole H, substantially no light is reflected and a signal whose level is below the threshold value TH1 is obtained. Edges E are present between the hole H and the pad R as well as between the track L and the base B. Due to irregularities and inclination in the edges E, reflected light levels in these portions vary between the threshold values TH1 and TH2, so that quantization errors are often caused. Signals from the image reader 20 are binarized in the binarizing circuits 21a and 21b shown in Fig. 2A, using the threshold values TH1 and TH2 respectively. The binarizing circuit 21a generates a signal representing a hole image HI corresponding to the hole H, while the binarizing circuit 21b generates another signal representing a pattern image PI corresponding to the wiring pattern P consisting of the track L and the pad R. These signals representing the images HI and PI are subjected to the processing described below. Fig. 3B shows another example of the reading optical system. Similarly to the system shown in Fig. 3A, light from a light source 22a is applied onto the printed board 11 and a reflected light is incident on a CCD 24 in an image reader 20 through a half mirror 23 and a lens 25. In this example, another light source 22b is provided at the rear side of a stage 10, so that light passing through a hole H is also received by the CCD 24. Therefore, the signal obtained in the CCD 24 is at the highest level in the hole H, at an intermediate level in a wiring pattern P consisting of a track L and a pad R, and at relatively low levels in a base plate B and edges E. Alternatively, at least two linear arrays of CCDs 24 may be prepared. In this case, the wiring pattern P consisting of the track L and the pad R is detected by the combination of the light source 22a and one of the two linear arrays of CCDs 24, while the hole H is detected by the combination of the light source 22b and the other of the two linear arrays of CCDs 24. The image signals are delivered to respective binarizing circuits provided in a subsequent stage. C. Pattern Inspection Circuit Fig. 2B is a block diagram showing the internal structure of the pattern inspection circuit 30 shown in Fig. 2A. The primary hole image signal HIS O and the primary pattern image signal PIS O obtained in the binarizing circuits 21a and 21b shown in Fig. 2A are supplied to noise filters 32a and 32b respectively through an interface 31. The noise filters 32a and 32b remove noises through smoothing processing etc., to generate a hole image signal HIS and a pattern image signal PIS respectively. Both of the hole image signal HIS and the pattern image signal PIS are supplied to all of a comparative check circuit 33, a DRC (design rule check) circuit 34, and a hole inspection circuit 35. The comparative check circuit 33 is adapted to compare the hole image signal HIS and the pattern image signal PIS with image signals obtained for a reference circuit board previously prepared, for specifying portions of the signals HIS and PIS which are different from the reference circuit board. The reference circuit board is of the same type as the circuit board 11 to be inspected and has been previously decided as nondefective. The hole inspection circuit 35 is adapted to detect relative positional relation between the pad R and the hole H on the printed board 11 and decide whether or not the same deviates from a value on design, thereby checking whether the circuit board 11 is defective or not. D. DRC Circuit (D-1) Outline Before explaining the structure and the operation of each part of the DRC circuit 34, the outline thereof is now described. Fig. 1A is a block diagram showing the outline of the DRC circuit 34, and Fig. 1B is a flow chart showing the flow of the operation of this circuit 34. A multiple sequence operator processing part 36 is operable to conduct the process steps S100 and S101, in which a multiple sequence operator MOP (Fig. 6) is applied to the pattern image PI and the result of the operation is converted to digital data which is in the form of a single cross operator DOP (Fig. 7). An error decision part 37 is operable to conduct the process step S102, in which the data in the form of the apparent cross operator DOP is received and pattern abnormality is detected. Since the data in the cross operator form DOP has four arms each consisting of a single sequence of binary data, the error decision part 37 may be the same circuit as for the conventional cross operator (Figs. 14-18). (D-2) Processing with Multiple Sequence Operator Fig. 5 shows the structure of the multiple sequence operator processing part 36. The image data represented by the pattern image signal PIS for respective scanning lines are arranged into two-dimensional data array or matrix with a set of one-line shift registers SR and a set of one-pixel shift registers which are represented by square blocks in Fig. 5. Respective outputs of the one-pixel shift registers in the central three columns and in the central three rows are extracted to be delivered to processing blocks G. The set of signals inputted to the processing blocks G are data representing the result of applying the operator MOP to the image data. Fig. 6 shows the pixel arrangement in the operator MOP. The operator MOP consists of a horizontal arm A H and a vertical arm A V crossing each other and forming a radial operator pattern. Each arm is a multiple sequence arm consisting of three sequences or unit arms UA of eleven pixels, and the crossing region is a pixel matrix consists of 3 x 3 = 9 pixels. The unit arm forms a close bundle of pixel arms. The horizontal arm A H is parallel to the X-direction and the vertical arm A V is parallel to the Y-direction. From another point of view, the operator MOP consists of a straight pair of horizontal multiple sequence arms, a straight pair of vertical multiple train arms and the crossing region corresponding to a pixel matrix consisting of 3 x 3 = 9 pixels. The operator MOP is equivalent to a logical operator having a plurality of multiple sequence arms A H and A V . Each of the multiple sequence arms A H and A V consists of a close bundle of unit arms UA. Respective unit cells UC in each unit arm UA is equivalent to a unit operator operable to extract a logical "1" level from the respective pixels in the image data and to provide a logical "0" level for the other pixels. In other words, each unit cell UC is equivalent to an AND circuit whose one input is a pixel image data and the other terminal is fixed to a logical "1" level. Consider a coordinate system having a u axis and a v axis. The u axis is parallel to the X direction and the v axis is parallel to the Y direction. The origin is set at the center 0. The unit of respective axis is the pixel width. Accordingly, each pixel in the operator MOP can be expressed in the form of A(u, v). For example, the pixel which is in a position of (+2) pixels in the X direction and (+1) pixel in the Y direction from the center O is expressed as A(+2, +1). The pixel which is in a position of (-1) pixel in the X direction and (+4) pixels in the Y direction from the center 0 is expressed as A(-1, +4). The center or origin 0 can be expressed as A(0, 0). The processing part 36 is operable to apply the operator MOP to the image data for respective pixels to obtain a multiple cross array of binary data consisting of multiple train arms. The multiple cross array of binary data is converted by the processing blocks G into a single cross array of binary data corresponding to the operator form DOP. The circuit structure of the blocks G will be described later. The operator form DOP can be also expressed in a similar manner as the operator MOP. As shown in Fig. 7, a pixel which is in a position of (-3) pixels from the center O in the X direction is expressed as DA(-3, 0), while a pixel which is in a position of (+3) pixels from the center O in the Y direction is expressed as DA(0, +3). Similarly to the case of the operator MOP, the center DO can also be expressed as DA(0, 0). A technique of converting the result of applying the operator MOP to the image data into the single cross operator form DOP is now described. Fig. 8 shows the step S101 of Fig. 1B in detail. First, it is checked whether a pixel on which the center O of the multiple train operator MOP acts is "0" or "1" (the process step S201). In the case shown in Fig. 10 in which quantization errors MIS are on the line L, the binary image data on the center pixel O is: O ( = A(0,0) ) = 1 Thus, the process is advanced to the process step S202, to check whether or not the following expression (2) holds as to a certain u : A(u,+1) + A(u,0) + A(u,-1) = 1 where the symbol "+" indicates logical summation. If the expression (2) is satisfied, the binary data: DA(u,0) = 1 is given to the pixel on the position u in the apparent cross operator DOP (the process step S203). In the example shown in Fig. 10, the following equation (4) is satisfied for the pixels on the base plate B. A(-4,-1) = A(-4,0) = A(-4,+1) = 0 Accordingly, the binary data: DA(-4,0) = 0 is given to the pixel DA(-4,0). In the vicinity of the center of the line L, the following equation (6) is satisfied and the equation (7) is obtained. A(-1,-1) = A(-1,0) = A(-1,+1) = 1 DA(-1,0) = 1 In the portion where the quantization errors MIS are present, the equations: A(-3,-1) = A(-3,+1) = 1 A(-3,0) = 1 are held, and therefore, the binary data: DA(-3,0) = 1 is given to the pixel DA(-3,0) on the operator form DOP, so that the quantization errors MIS disappear on the operator form DOP. Fig. 12 shows an operator DOP obtained as the result. No quantization errors appear on the operator DOP, and a line L which has a width W and whose elongated direction LD is along the Y direction can be detected without influence of quantization errors, by counting the number of pixels of "1" which are continuously aligned in the direction X. When a short circuit SC is present between two lines L as shown in Fig. 11, the following equation (10) for all values of u and the equation (11) hold in the process steps S204 and S205. DA(u,0) = 1 DA(0, -1) = DA(0,0) = DA(0,+1) = 1 As a result, an operator form DOP of Fig. 13 is obtained as the presence of the short circuit SC and the width thereof can be detected. While such the case that the center O is "1" has been described above, this also applies to the case of that the center O is "0" (the process step S206). If a line L is disconnected or cut and the operator MOP acts on the disconnected portion as shown in Fig. 19, for example, the binary data in the operator form DOP obtained from the operator MOP is given as the following equation (12) for all values of u , so that the disconnected portion is detected. DA(u,0) = 0 Namely, in the preferred embodiment, if at least one of cross-directionally adjacent three pixels of the operator MOP is "1" under the condition that the center O is "1", the corresponding pixel of the apparent cross operator DOP is given the logical value "1". On the other hand, if at least one of cross-directionally adjacent three pixels of the operator MOP is "0" under the condition that the center O is "0", the corresponding pixel of the operator DOP is given the logical value "0". The processing is conducted in the processing blocks G (Fig. 5). Each processing block G is provided with a combination of logic circuits shown in Fig. 9, for example, and its logical operation is as follows: DO I x (M 1 x M 2 x M 3 ) + DO x (M 1 + M 2 + M 3 ) where M 1 , M 2 and M 3 represent the binary data on cross-direcitonally adjacent three pixels obtained through the operator MOP: DO is the binary data on the center pixel O; DO I is the inverse of the binary data D O on the center pixel O; the symbol "x" represents logical product; and; the symbol "+" represents logical summation As to the value of the center DO of the operator DOP, the value of the center 0 of the operator MOP may be directly used without passing through the processing block G. (D-3) Error Decision A method of performing error decision using the data of the operator DOP is now described. First, cases of compensation of quantization errors and short-circuiting are described. It is recognized whether the following expression (14) holds as to all u or all v among the data in the cross operator form DOP: DA(u,v) = 1 If the expression (14) holds as to all u , it is decided that the elongated direction LD of the track L is along the X direction. On the other hand, it is decided that the elongated direction LD of the track L is along the Y direction if the expression (14) holds as to all v . If the expression (14) holds for neither case, it is decided that no detection has been made as the track L. Upon such decision of the elongated or running direction LD of the track L, a direction perpendicular thereto is regarded as the cross direction on the track, and the number of continuous pixels having "1" is counted. Since the elongated direction LD of the track L is along the Y direction ( v direction) as shown in Fig. 12 and seven pixels from DA(-3, O) to DA(+3, 0) are continuously "1" in the X direction ( u direction), it is decided that the width W of the track L is seven pixels. If there is no arithmetic processing using the operator MOP, the width W may be erroneously decided as five due to a quantization error as shown in Fig. 14, while such an erroneous decision can be avoided in this preferred embodiment by the processing as described in the section (D-2). In the case of Fig. 13, it is decided that the elongated direction LD of the track L is along the X direction ( u direction), and the width W of this track L is decided to be three since three pixels from DA(0, -1) to DA(0, +1) are continously "1" in the Y direction ( v direction). A minimum allowable value Wmin for the line width is set at four, for example, to provide such a criterion that a line L having a width smaller than the minimum allowable value Wmin is abnormal. Then, a portion decided as the line L here is regarded as abnormal (short-circuiting SC in this case), whereby the error decision part 37 outputs an error signal ER (Fig. 1A). If there is slight disconnection as shown in Fig. 19, held are the expression (12) and the following expression (15) for the case where the center DO of "0". DA(0,-2) = DA(0,+2) = 1 Thus, the disconnection is recognized and an error signal ER is outputted. E. Modifications (1) The width of respective arms in the operator MOP may be any multiple number of pixels, which is five in the preferred embodiment. When the width of respective arms is relatively wide, the effect of the present invention is enhanced in such a case where the short circuit SC and disconnection are obliquely formed with respect to the X direction and the Y direction. Further, the width of respective arms may be varied depending on the elongated directions of respective arms so as to reflect characters of the wiring pattern P. (2) As shown in Fig. 20, the multiple train operator may have not only the horizontal and vertical arms but also other arms extending in the directions forming angles of 45° and 135° with the directions X and Y. In this case, the track L, the short circuit SC and/or disconnection extending at angles of 45° and 135° with respect to the X direction are easily detected. Similarly to the modification (1), the width of respective arms may be varied depending on the elongated directions of respective arms so as to reflect characters of the wiring pattern P. While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention as defined in the claims.

Claims: A method of inspecting a wiring pattern formed on a printed circuit board, comprising the steps of: (a) obtaining an image of said wiring pattern; (b) applying an image operator (MOP) to said image to obtain a first data array, wherein said image operator being of predetermined geometrical form has a plurality of operator arms each of which is formed of a plurality of pixel sequences, and said first data array has a first plurality of data arms each of which is formed of a plurality of sequences of data values; (c) converting by application of a logical operation said first data array into a second data array (DOP) having a second plurality of data arms each of which is formed of a single sequence of data values; and (d) inspecting said wiring pattern as a function of said second data array by comparison with preselected reference information. The method of claim 1, wherein the step (b) comprises the steps of: (b-1) defining said image operator (MOP) so that said plurality of pixel sequences form a close bundle of parallel pixel sequences; (b-2) serially selecting each pixel on said image; and (b-3) applying said image operator to said image while adjusting the center of said image operator to each pixel of said image. The method of claim 2, wherein the step (b-1) comprises the step of: (b-1-1) defining said image operator (MOP) so that said plurality of operator arms cross each other at said center of said image operator. The method of claim 3, wherein the step (b-1-1) comprises the step of: defining said image operator (MOP) so that said plurality of operator arms form a radial pattern. The method of claim 4, wherein the step (c) comprises the step of: (c-1) applying a logical operation to said plurality of sequences of data values to obtain said single sequence of data values. The method of claim 5, wherein the step (c-1) comprises the steps of: (c-1-1) determining a first type of logical operation and a second type of logical operation; (c-1-2) obtaining a data value of said image data at a center of said first data array which corresponds to said center of said image operator; (c-1-3) selecting one of said first and second types of logical operation as a function of said data value at said center of said first data array; and (c-1-4) applying said one of said first and second types of logical operation to said plurality of sequences of data values to obtain said single sequence of data values. The method of claim 6, wherein the step (c-1-4) comprises the step of: applying said one of said first and second types of logical operation to each group of pixel data values aligning in said plurality of data arms in respective directions traversing said plurality of data arms. The method of claim 3, wherein the step (d) comprises the steps of: (d-1) detecting a number of pixels which are aligned along an elongated direction of each arm in said second plurality of data arms and which have a same logical level; and (d-2) comparing said number of pixels with a threshold number to inspect said wiring pattern. An apparatus for inspecting a wiring pattern formed on a printed circuit board, comprising: (a) means for obtaining an image (20, 21a, 21b) of said wiring pattern; (b) means for applying an image operator (MOP) to said image to obtain a first data array, wherein said image operator being of predetermined geometrical form has a plurality of operator arms each of which is formed of a plurality of pixel sequences, and said first data array has a first plurality of data arms each of which is formed of a plurality of sequences of data values; (c) means for converting (36) said first data array into a second data array (DOP) by application of a logical operation, said second data array having a second plurality of data arms each of which is formed of a single sequence of data values; and (d) means for inspecting (37) said wiring pattern as a function of said second data array by comparison with preselected reference information. The apparatus of claim 9, wherein said means (b) comprises: (b-1) means for implementing said image operator so that said plurality of pixel sequences form a close bundle of parallel pixel sequences; and (b-2) means for serially selecting (SR) each pixel on said image; and (b-3) means for delivering (31, 32a, 32b) said image data to said means (b-1) to apply said image operator to said image while adjusting the center of said image operator to each pixel of said image. The apparatus of claim 10, wherein said means (b-1) comprises: (b-1-1) means for implementing said image operator so that said plurality of operator arms cross each other at said center of said image operator. The apparatus of claim 11, wherein said means (b-1-1) comprises: means for implementing said image operator so that said plurality of operator arms form a radial pattern. The apparatus of claim 12, wherein said means (c) comprises: (c-1) means for applying a logical operation (G) to said plurality of sequences of data values to obtain said single sequence of data values. The apparatus of claim 13, wherein a first type of logical operation and a second type of logical operation are previously determined; and said means (c-1) comprises: (c-1-1) means for obtaining a data value of said image data at the center of said first data array which corresponds to said center of said image operator; (c-1-2) means for selecting one of said first and second types of logical operation as a function of said data value at said center of said first data array; and (c-1-3) means for applying said one of said first and second types of logical operation to said plurality of trains of data values to obtain said single train of data values. The apparatus of claim 14, wherein said means (c-1-3) comprises: means for applying said one of said first and second types of logical operation to each group of pixel data values aligning in said plurality of data arms in respective directions traversing said plurality of data arms. The apparatus of claim 15, wherein said means (d) comprises: (d-1) means for detecting a number of pixels which are aligned along an elongated direction of each arm in said second plurality of data arms and which have a same logical level; and (d-2) means (34) for comparing said number of pixels with a threshold number to inspect said wiring pattern.

Inventors: ATSUTA HITOSHI, KANAI TAKAO, MANDAI ICHIROU, SEZAKI YOSHINORI, ATSUTA, HITOSHI, KANAI, TAKAO, MANDAI, ICHIROU, SEZAKI, YOSHINORI, Atsuta, Hitoshi, c/o Dainippon Screen Mfg. Co.,, Kanai, Takao, c/o Dainippon Screen Mfg. Co., Ltd., Mandai, Ichirou, c/o Dainippon Scr. Mfg. Co., Ltd., Sezaki, Yoshinori, c/o Dainippon S. Mfg. Co., Ltd.
Applicants: DAINIPPON SCREEN MFG, DAINIPPON SCREEN MFG. CO., LTD.
Application year: 1991
Main classification: G06T5
IPC codes: G06T1, G06T7, G01N21, H05K3, G01B11