Dynamic random access memory device with improved refreshing unit

Abstract: A dynamic random access memory device (DRAM) stores data bits in a plurality of memory cell arrays (22-25) associated with a plurality of word line groups (WL11-WL4k) coupled with a plurality of row address decoding units (26-29). The device is periodically subjected to a refresh cycle. A refresh address counter (36) increments the refresh address indicated by a refresh address signal (A0-Am) for sequentially designating all the word lines of the word lines groups. The low-order address bits (A0-A1) of the refresh address are supplied to an address predecoding unit (30) (rather than the high-order address bits) thereby allowing the row address decoding units to respond sequentially to the high-order address bits (A3-A1) of the refresh address (Fig. 5). In this way a refreshing operation of a component word line is carried out after recovery from any undesirable voltage fluctuation occurring in the refreshing operation for the previous word line in the same word line group.

Description: FIELD OF THE INVENTION This invention relates to a dynamic random access memory device and, more particularly, to a refreshing technology for a short refreshing time period. DESCRIPTION OF THE RELATED ART Data bits stored in dynamic random access memory cells need to be periodically refreshed, and the dynamic random access memory device is equipped with a refreshing unit. A typical example of the dynamic random access memory device comprises four memory four cell array units 1, 2, 3 and 4, four word line groups WL11 to WL1k, WL21 to WL2k, WL31 to WL3k and WL41 to WL4k respectively associated with the four memory cell array units 1 to 4, four row address decoding units 5, 6, 7 and 8 respectively coupled with the four word line groups WL11 to WL1k, WL21 to WL2k, WL31 to WL3k and WL41 to WL4k for selectively driving the component word lines WL11 to WL1k, WL21 to WL2k, WL31 to WL3k and WL41 to WL4k, and an address predecoding unit 9, and the address predecoding unit 9 selectively activates the row address decoding units 5 to 8 with predecoded address signals PAD1, PAD2, PAD3 and PAD4. Though not shown in Fig. 1, a multi-bit internal row address signal is distributed to the row address decoding units 5 to 8 and the address predecoding unit 9, and one of the row address decoding units 5 to 8 drives one of the component word lines of the associated word line group WL11 to WL1k, WL21 to WL2k, WL31 to WL3k or WL41 to WL4k upon an access from an external device. Each of the memory cell array units 1 to 4 comprises memory cell arrays consisting of a plurality of memory cells arranged in rows and columns, and the memory cells are of the one-transistor one-capacitor type. In detail, Fig. 2 shows the circuit arrangement of one of the memory cell array units 1 to 4, and bubbles are indicative of the memory cells coupled with the component word lines WL11 to WL1k, WL21 to WL2k, WL31 to WL3k or WL41 to WL4k. A plurality of bit line pairs BLP1 to BLPn are further coupled with the memory cells, and propagate data bits from a row of the memory cells coupled with the component word line driven by the associated address decoding unit 5, 6, 7 or 8 to n-channel enhancement type transfer gate transistors Qn1 to Qn10. Since a control signal TG is supplied to the gate electrodes of the n-channel enhancement type transfer gate transistors Qn1 to Qn10, the n-channel enhancement type transfer gate transistors Qn1 to Qn10 relay the data bits to sense amplifier circuits SA1, SA2, SA3, SA4, SA5, SA6, SA7, SA8, SA9 and SAn, and the sense amplifier circuits SA1 to SAn quickly discriminate the logic level of the data bits through differential amplification with a reference voltage level. While the sense amplification is carried out, the n-channel enhancement type transfer gate transistors Qn1 to Qn10 are turned off, and, thereafter, turn on again for transferring the data bits from the sense amplifier circuits SA1 to SAn to the memory cells. Though not shown in the drawings, the data bits are transferred from the sense amplifier circuits SA1 to SAn to a column selecting unit, and the column selecting unit is responsive to a multi-bit internal column address decoded signal for selectively transferring the data bits to an output buffer circuit (not shown). Thus, the prior art dynamic random access memory device allows the external device to access to a data bit stored in the memory cell array units 1 to 4. However, the data bits are stored in the memory cells in the form of electric charges, and the electric charges are liable to flow out. For this reason, the prior art random access memory device is equipped with a refreshing unit. Turning back to Fig. 1 of the drawings, the prior art random access memory device further comprises a balance signal generating unit 10 for producing a balance signal BL, four AND gates 11, 12, 13 and 14 enabled with the predecoded address signals PAD1 to PAD4 for transferring the balancing signal BL to the associated memory cell array units 1 to 4, and a refresh address counter 15. The balancing signal BL is ANDed with the predecoded address signals PAD1 to PAD4, and the balancing signal BL is transferred to one of the memory cell array units 1 to 4. The balancing signal BL is supplied to the gate electrodes of n-channel enhancement type field effect transistors Qn11, Qn12, Qn13, Qn14 and Qn15 (see Fig. 2) for equalizing the bit line pairs BLP1 to BLPn prior to the selection from the associated word line group WL11 to WL1k, WL21 to WL2k, WL31 to WL3k or WL41 to WL4k. The refresh address counter 15 is implemented by D-type flip flop circuits FF1, FF2, FF3, FFm-2, FFm-1 and FFm coupled in cascade, and a clock signal CL is supplied from an external clock source (not shown) to the flip flop circuit FF1. With the clock signal CL, the refresh address counter 15 increments an refresh address indicated by address bits A0, A1, A2, Am-2, Am-1 and Am. The flip flop circuits FF1 to FFm-2 are coupled in parallel with the row address decoding units 5 to 8, and the address bits A0 to Am-2 are supplied in parallel to the row address decoding units 5 to 8. However, the flip flop circuits FFm-1 and FFm are coupled with the address predecoding unit 9, and, accordingly, the address bits Am-1 and Am are supplied to the address predecoding unit 9. For this reason, the low order address bits A1 to Am-2 are indicative of the word line driven by the associated row address decoding unit, and the highest two address bits Am-1 and Am designate one of the row address decoding units 5 to 8 as shown in Fig. 3. Such arrangement is also disclosed in IBM Technical Disclosure Bulletin, no. 8, vol. 31, January 1989, pages 227-229 "High-Performance DRAM Refresh Mechanism". While the prior art random access memory device is in the standby phase, i.e., out of the read-out and write-in phases, the data bits stored in the memory cell array units 1 to 4 are subjected to refreshing. In the refreshing, the clock signal CL is supplied to the refresh address counter 15, and the refresh address is sequentially incremented. Every refreshing starts with balancing operation of the bit line pairs BLP1 to BLPn in the presence of the balancing signal BL. While one of the word lines WL11 to WL1k, WL21 to WL2k, WL31 to WL3k and WL41 to WL4k is designated by the address predecoding unit 9 and the associated row address decoding unit, the data bits are read out from the memory cells coupled therewith to the associated bit line pairs BLP1 to BLPn, and are relayed from the bit line pairs BLP1 to BLPn through the n-channel enhancement type transfer transistors Qn1 to Qn10 to the sense amplifier circuits SA1 to SAn. Since the data bits are represented by differential voltage levels between voltage levels on the associated bit lines and the reference voltage level, the sense amplifier circuits SA1 to SAn increase the magnitudes of the differential voltage levels indicative of the data bits, and the bit line pairs BLP1 to BLPn backwardly propagate the data bits indicated by the differential voltage levels thus increased in magnitude through the n-channel enhancement type transfer gates Qn1 to Qn10 to the memory cells. Then, the data bits to be refreshed are rewritten into the memory cells again. Since the highest two address bits Am-1 and Am designate one of the memory cell array units 1 to 4, when all of the component word lines WL11 to WL1k, WL21 to WL2k, WL31 to WL3k or WL41 to WL4k are sequentially driven by the associated row address decoding unit 5, 6, 7 or 8, the address predecoding unit 9 changes the designated row address decoding unit, and the refreshing are repeated for all of the data bits stored in the memory cells coupled with all the component word lines WL11 to WL1k, WL21 to WL2k, WL31 to WL3k and WL41 to WL4k. When all of the word line groups WL11 to WL1k, WL21 to WL2k, WL31 to WL3k and WL41 to WL4k are sequentially driven for the refreshing operations, the refreshing cycle is over, and the refresh address counter 15 starts a refreshing cycle again. A problem is encountered in the prior art dynamic random access memory device in that the data bits tend to be destroyed without refreshing upon voltage fluctuation of a positive power voltage source. In detail, all of the component word lines of every word line group WL11 to WL1k, WL21 to WL2k, WL31 to WL3k or WL41 to WL4k are sequentially driven by the associated row address decoding unit, and the refreshing is repeated for all the data bits stored in every memory cell array unit 1 to 4 at relatively short intervals each defined by the single clock pulse CL. Assuming now that the positive power voltage level Vcc fluctuates or is decayed, the n-channel enhancement type field effect transistors Qn1 to Qn10 turn off to isolate the bit line pairs BLP1 to BLPn from the sense amplifier circuits SA1 to SAn, and the data bits represented by a high voltage level are confined in the bit line pairs BLP1 to BLPn, because the high voltage levels make differential voltage levels between the source nodes and the gate electrodes smaller than the threshold level. The high voltage levels thus left on the bit line pairs BLP1 to BLPn are never affected by the voltage fluctuation. If the fluctuation continues over a single refreshing operation, the bit line pairs BLP1 to BLPn are equalized in the next refreshing at a relatively high voltage level in view of a positive power voltage level to be decayed. However, the fluctuation has influence on the active level of the component word line, and data bits are liable to be confined in the memory cells in the next refreshing operation. The data bits thus confined in the memory cells are never subjected to the refreshing, and are destroyed until the next refreshing starts. SUMMARY OF THE INVENTION It is therefore an important object of the present invention to provide a dynamic random access memory device which refreshes data bits regardless of fluctuation of a power voltage level. To accomplish the above described object, the present invention proposes to repeat a refreshing operation on a memory cell array at long time interval so that a power voltage source is allowed to recover from undesirable voltage fluctuation occurred in the refreshing operation on the same memory cell array. In accordance with the present invention, there is provided a dynamic random access memory device fabricated on a single semiconductor chip, comprising: a) a plurality of memory cell arrays each implemented by a plurality of dynamic random access memory cells arranged in rows and columns; b) a plurality of word line groups respectively associated with the plurality of memory cell arrays and each having a plurality of component word lines respectively coupled with the dynamic random access memory cells in the rows for allowing data bits to be selectively read out from the dynamic random access memory cells; c) a plurality of bit line pair groups respectively associated with the plurality of memory cell arrays and each having a plurality of bit line pairs respectively coupled with the dynamic random access memory cells of the columns for propagating the data bits; d) a plurality of transfer gate groups respectively associated with the plurality of bit line pair groups and each having a plurality of transfer gates for transferring the data bits; e) a plurality of sense amplifier groups respectively associated with the plurality of memory cell arrays and each having a plurality of sense amplifier circuits respectively coupled with the transfer gates of the transfer gate groups which are coupled with the bit line pairs of the associated bit line pair group, each of the plurality of sense amplifier circuits being operative to increase the magnitude of a differential voltage level indicative of one of the data bits read out from the dynamic random access memory cells; f) a plurality of row address decoding units respectively coupled with the plurality of word line groups and each responsive to first internal address bits for selectively driving the component word lines of the associated word line group; g) an address predecoding unit responsive to second internal address bits for allowing one of the row address decoding units to respond to the first internal address bits; and h) a refresh address counter responsive to a clock signal for incrementing a refresh address having low-order address bits serving as the second internal address bits and high-order address bits serving as the first internal address bits. BRIEF DESCRIPTION OF THE DRAWINGS The features and advantages of the dynamic random access memory device according to the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which: Fig. 1 is a block diagram showing the arrangement of the prior art dynamic random access memory device; Fig. 2 is a circuit diagram showing the arrangement of each memory cell array block incorporated in the prior art random access memory device; Fig. 3 is a view showing the format of the refresh address signal produced in the prior art random access memory device; Fig. 4 is a block diagram showing the arrangement of a dynamic random access memory device according to the present invention; Fig. 5 is a view showing the format of a refresh address signal produced in the dynamic random access memory device shown in Fig. 4; Fig. 6 is a diagram showing the relation between an refresh address and an activated predecoded signal line in a refresh cycle of the dynamic random access memory device; Fig. 7 is a diagram showing the sequence of a refreshing operation carried out by the dynamic random access memory device shown in Fig. 4; and Fig. 8 is a block diagram showing the arrangement of another dynamic random access memory device according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment Referring to Fig. 4 of the drawings, a dynamic random access memory device embodying the present invention is fabricated on a single semiconductor chip 21. The dynamic random access memory device comprises four memory cell array units 22, 23, 24 and 25, and the memory cell array units 22 to 25 are similar in circuit arrangement to the memory cell array unit shown in fig. 2, and no further description is incorporated hereinbelow for the sake of simplicity. However, if it is necessary to refer to the components of each memory cell array unit 22, 23, 24 or 25, the components are accompanied with references used in Fig. 2 for better understanding. The dynamic random access memory device further comprises row address decoding units 26, 27, 28 and 29 provided in association with the memory cell array units 22 to 25, and word line groups WL11 to WL1k, WL21 to WL2k, WL31 to WL3k and WL41 to WL4k couple the row address decoding units 26 to 29 with rows of the memory cells of the memory cell array units 22 to 25. A row address predecoding unit 30 is provided for the row address decoding units 26 to 29, and is responsive to internal row address bits produced from an external row address signal for selectively activating the row address decoding units 26 to 29 with predecoded signal lines 30a, 30b, 30c and 30d. When one of the row address decoding units 26 to 29 is activated with the predecoded signal lines 30a to 30d, the row address decoding unit becomes responsive to other internal row address bits for selectively driving the component word lines of the associated word line group. The random access memory device further comprises a balance signal generating unit 31, and the balance signal generating unit 31 distributes a one-shot balancing signal BL to AND gates 32, 33, 34 and 35. Since the predecoded signal lines 30a to 30d are respectively coupled with the AND gates 32 to 35, the one-shot balancing signal BL is ANDed with the predecoded signals on the signal lines 30a to 30d, and in turn is supplied through one of balance signal lines 32L, 33L, 34L or 35L to the n-channel enhancement type field effect transistors Qn11 to Qn15 (see Fig. 2) of the associated memory cell array unit. In order to increment a refresh address, the random access memory device is equipped with a refresh counter 36, and the refresh counter 36 is implemented by D-type flip flop circuits FF1, FF2, FF3, FFm-3, FFm-2, FFm-1 and FFm coupled in cascade. In this instance, a clock signal CLK is supplied from the outside thereof to the flip flop circuit FF1, and the refresh address is incremented by the clock signal CLK. In detail, the non-inverted output nodes Q of the flip flop circuit FF1 to FFm are respectively coupled with refresh address lines AL1, AL2, AL3, ALm-3, ALm-2, ALm-1 or ALm, and the non-inverted output nodes Q of the flip flop circuits FF1 to FFm-1 are further coupled with clock nodes of the next flip flop circuits FF2 to FFm. The inverted output nodes CQ of the flip flop circuits FF1 to FFm are respectively coupled with the input data nodes thereof, and refresh address bits A0 to A1 are selectively propagated through the refresh address lines AL1 to ALm to the address predecoding unit 30 and the row address decoding units 26 to 29. Namely, the low-order refresh address bits A0 and A1 are supplied to the address predecoding unit 30, and the high-order refresh address bits A2 to A1 are supplied in parallel to the row address decoding units 26 to 29. Therefore, the refresh address signal is formatted as shown in Fig. 5 of the drawings. If the pulse train of the clock signal CLK is continuously applied to the clock node of the flip flop circuit FF1, the non-inverted output node thereof is changed between high and low levels in synchronism with the clock signal CLK, and a pulse train P1 takes place on the refresh address line AL1. Each of the other refresh address lines AL2 to ALm doubles the pulse with of a pulse train on the previous refresh address line as shown in Fig. 6. However, the low-order refresh address bits A0 and A1 are used for sequential activation of the row address decoding units 26 to 29, and the predecoded signal lines 30a to 30d are repeatedly activated at every four pulses of the clock signal CLK. Description is hereinbelow made on circuit behavior of the dynamic random access memory device focusing upon a refreshing cycle with reference to Fig. 7. A single refreshing cycle is constituted by a plurality of refreshing operations each carried out for a row of the memory cells coupled with a component word line. Assuming now that the refreshing cycle starts from the component word line WL11, the address predecoding unit 30 decodes the low-order refresh address bits A0 and A1, and enables the predecoded signal line 30a coupled with the row address decoding unit 26 at time t1. The predecoded signal line 30a is further operative to allow the AND gate 32 to transfer the one-shot balance signal BL to the associated balance signal line 32L, and the bit line pairs BLP1 to BLPn of the memory cell array unit 22 are equalized in voltage level immediately after time t1. When the row address decoding unit 26 is enabled, the refresh address bits A2 to A1 are decoded, and the component word line WL11 is driven so that data bits are read out from the memory cells coupled therewith to the bit line pairs BLP1 to BLPn. The data bits are propagated through the bit line pairs BLP1 to BLPn to the n-channel enhancement type transfer gate transistors Qn1 to Qn10, and the n-channel enhancement type transfer gate transistors Qn1 to Qn10 relay the data bits to the sense amplifier circuits SA1 to SAn. The n-channel enhancement type transfer gate transistors Qn1 to Qn10 turn off so that the sense amplifier circuits SA1 to SAn are isolated from large parasitic capacitances of the bit line pairs BLP1 to BLPn. The sense amplifier circuits SA1 to SAn increase the magnitudes of differential voltage levels respectively indicative of the data bits at high-speed, and the data bits are refreshed again. The n-channel enhancement type transfer gate transistors Qn1 to Qn10 turn on again, and the data bits thus refreshed are fed back to the memory cells. Then, the data bits are rewritten into the memory cells, and the refreshing operation is completed. Upon completion of the refreshing operation, the low-order refresh address bits A0 and A1 causes the address predecoding unit 30 to enable the row address decoding unit 27 with the predecoded signal line 30b at time t2, and a refreshing operation is carried out for the data bits stored in the memory cells coupled with the component word line WL21. Upon completion of the refreshing operation on the component word line WL21, the low-order refresh address bits A0 and A1 causes the address predecoding unit 30 to enable the row address decoding unit 28 at time t3, and a refreshing operation is carried out for the data bits stored in the memory cells coupled with the component word line WL31. Similarly, the row address decoding unit 29 is enabled at time t4, and a refreshing operation is carried out for the data bits stored in the memory cells coupled with the component word line WL41. Upon completion of the refreshing operation on the component word line WL41, the low-order refresh address bits A0 and A1 allow the address predecoding unit 30 to enable the row address decoding unit 26 again, and a refreshing operation is carried out for the data bits stored in the memory cells coupled with the component word line WL12. Thus, the dynamic random access memory device repeats the refreshing operation, and the data bits stored in the memory cells coupled with the component word line WL4k are finally refreshed. As will be understood from the forgoing description, the individual memory cell array units 26 to 29 are designated at every four refreshing operation. Even if voltage fluctuation takes place in a positive power voltage source, the positive power voltage source usually recovers from the voltage fluctuation within the time period assigned the four refreshing operations, and data bits refreshed in the previous refreshing operation never confine other data bits in the memory cells coupled with the next component word line. Second Embodiment Turning to Fig. 8 of the drawings, another dynamic random access memory device embodying the present invention is illustrated. The dynamic random access memory device shown in Fig. 8 is similar in circuit arrangement to the first embodiment except for a balance signal generating unit 41, and, for this reason, the other components are labeled with the same references designating the corresponding components of the first embodiment without detailed description. Namely, the balancing signal generating unit 31 and the AND gates 32 to 35 are replaced with four one-shot pulse generating circuits 41a, 41b, 41c and 41d respectively associated with the memory cell array units 22 to 25, and each of the one-shot pulse generating circuits 41a to 41d is implemented by a time delay circuit 42, an inverting circuit 43 and a NOR gate 44. The decoded signal lines 30a to 30d are coupled with the time delay circuits 42 as well as with the inverting circuits 43, While the associated predecoded signal line 30a, 30b, 30c or 30d remains low, the inverting circuit 43 deactivates the associated NOR gate 44. If one of the predecoded signal lines 30a to 30d is lifted, the associated inverting circuit 43 enables the NOR gate 44 to produce a balancing signal BL of the active high level. However, when the associated time delay circuit 42 relays the predecoded signal after short interval, the NOR gate 44 shifts the balancing signal BL to an inactive low level. However, the other circuit behavior and the advantages are similar to those of the first embodiment, and no further description is incorporated for the sake of simplicity. Although particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that various changes and modifications may be made without departing from the scope of the present invention as specified in the appended claims. For example, the clock signal CLK may be internally produced, and the number of the memory cell array units may be less than or more than 4.

Claims: A dynamic random access memory device fabricated on a single semiconductor chip (21), comprising: a) a plurality of memory cell arrays (22/23/24/25) each implemented by a plurality of dynamic random access memory cells arranged in rows and columns; b) a plurality of word line groups (WL11 to WL1k/ WL21 to WL2k/ WL31 to WL3k/ WL41 to WL4k) respectively associated with said plurality of memory cell arrays and each having a plurality of component word lines respectively coupled with the dynamic random access memory cells in said rows for allowing data bits to be selectively read out from said dynamic random access memory cells; c) a plurality of bit line pair groups respectively associated with said plurality of memory cell arrays and each having a plurality of bit line pairs (BLP1 to BLPn) respectively coupled with said dynamic random access memory cells of said columns for propagating said data bits; d) a plurality of transfer gate groups respectively associated with said plurality of bit line pair groups and each having a plurality of transfer gates (Qn1 to Qn10) for transferring said data bits; e) a plurality of sense amplifier groups respectively associated with said plurality of memory cell arrays and each having a plurality of sense amplifier circuits (SA1 to SAn) respectively coupled with said transfer gates of said transfer gate groups which are coupled with said bit line pairs of said associated bit line pair group, each of said plurality of sense amplifier circuits being operative to increase the magnitude of a differential voltage level indicative of one of said data bits read out from said dynamic random access memory cells; f) a plurality of row address decoding units (26/ 27/ 28/ 29) respectively coupled with said plurality of word line groups and each responsive to first internal address bits for selectively driving said component word lines of said associated word line group; g) an address predecoding unit (30) responsive to second internal address bits for allowing one of said row address decoding units to respond to said first internal address bits; and h) a refresh address counter (36) responsive to a clock signal (CLK) for incrementing a refresh address, characterized in that said refresh address has low-order address bits (A0/A1) serving as said second internal address bits and high-order address bits (A3 to A1) serving as said first internal address bits. A dynamic random access memory device as set forth in claim 1, in which said refresh address counter comprises a plurality of flip flop circuits (FF1 to FFm) coupled in cascade, said plurality of flip flop circuits having a first flip flop circuit (FF1) supplied with said clock signal for producing the lowest-order address bit (A0) of said refresh address. A dynamic random access memory device as set forth in claim 2, in which said dynamic random access memory device further comprises i) a plurality of balancing units respectively associated with said plurality of bit line pair groups, and each having a plurality of balancing transistors (Qn11 to Qn15) respectively coupled with said plurality of bit line pairs of said associated bit line pair group for equalizing the component bit lines of said plurality of bit line pairs in response to a balancing signal (BL); and j) a balancing signal generating unit (31 to 35; 41)) producing said balancing signal, and selectively distributing said balancing signal to said plurality of balancing units in synchronism with sequential designation of said plurality of row address decoding units carried out by said address predecoding unit. A dynamic random access memory device as set forth in claim 3, in which said balancing signal generating unit comprises j-1) a one-shot pulse generating circuit (31) for producing a one-shot pulse signal, and j-2) a plurality of AND gates (32 to 35) respectively associated with said plurality of balancing units, and each having an output node coupled with gate electrodes of said balancing transistors of said associated balancing unit, a first input node supplied with said one-shot pulse signal, and a second input node supplied with a predecoded signal indicative of designation of said associated row address decoding unit from said address predecoding unit. A dynamic random access memory device as set forth in claim 3, in which said balancing signal generating unit comprises a plurality of balancing signal generating circuits (41a/ 41b/ 41c/ 41d) respectively associated with said plurality of balancing units, and each having a time delay circuit (42) supplied with a predecoded signal indicative of designation of said associated row address decoding unit from said address predecoding unit for producing a delay signal, an inverting circuit (43) supplied with said predecoded signal for producing a complementary predecoded signal, and a NOR gate (44) supplied with said delay signal and said complementary predecoded signal for producing said balancing signal.

Inventors: TAMAKI SATOSHI, TAMAKI, SATOSHI, Tamaki, Satoshi, c/o NEC Corporation
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: G11C11
IPC codes: G11C11, G11C29