TWIN-TUB FABRICATION METHOD

Abstract: A method is disclosed for forming self-aligned twin tubs (8, 9) of opposite conductivity type in a semiconductor substrate (1). The method comprises the steps of implanting an impurity of one conductivity type in the substrate over a region which is to form the twin tubs, masking the substrate to expose a selected portion (4) thereof which is to form one of the tubs, etching the substrate in the exposed portion to remove at least most of the initial implant (7) from the substrate, implanting an impurity (5) of the opposite conductivity type in the exposed region of said substrate, and thermally diffusing the implanted impurities into the substrate (1) to form the twin tubs (8, 9). This process reduces the number of steps needed in the fabrication process and also reduces the number of crystal defects.

Description: TWIN-TUB FABRICATION METHOD This invention relates to a method of forming self-aligned twin tubs in a semiconductor substrate, particularly in the manufacture of CMOS semiconductor devices. CMOS technology has been widely adopted in very large scale integrated circuits, in part due to its low power characteristics, which allow very high component densities to be achieved, especially with two micron technology. In the classic CMOS process, an n channel transistor is formed in a p tub, which is diffused into a moderately doped n-substrate, in which an associated p channel transistor is to be formed. The doping level of the p tub must be approximately an order of magnitude greater than the doping level of the n substrate to provide an adequate degree of control. As the scale of the technology decreases, the doping in the n substrate must be increased to support the voltage in the shorter channel length p channel transistors, and consequently the p tub doping must be raised proportionately. This results in the n channel transistor suffering from excessive source/drain to p tub capacitance. The twin-tub CMOS process was designed to overcome these problems in small scale processes by providing separately optimized tubs and hence a lower capacitance n channel transistor than could be obtained with the classic process. In the conventional twin-tub process (see, for example, L.C. Parillo et. al., Twin-Tub CMOS - A Technology for VSLI Circuits, CHI612-2/80/0000-0752, IEEE) , a pair of tubs of opposite conductivity type, in which the p channel and n channel transistors are ultimately formed, are first formed in the silicon substrate. The silicon substrate is then covered with a thin oxide layer on which is deposited a nitride layer. A photoresist layer is then deposited on the nitride layer, exposed, and developed to mask a portion of the nitride layer over one of the regions that is to form one of the tubs. Through the window in the mask, the exposed nitride layer and underlying oxide layer are etched away to expose the surface of the silicon substrate. A first ion implantation of one conductivity type is performed into the exposed substrate. A thick thermal oxidation layer (in the order of 1 μm) is then formed over the implanted substrate and the remaining photoresist layer stripped away. Next, the remaining nitride is stripped from the thin oxide layer overlying the region that is to form a second tub, and a second implantation is performed through the exposed thin oxide layer into the underlying substrate with the thick oxide layer blocking the initial implant. The implanted impurities are then thermally diffused to the required depth to form the p and n type tubs respectively. A problem with this method is that it is relatively complicated, time-consuming to carry out and furthermore has a tendency to introduce crystal defects into the substrate. An object of the invention is therefore to alleviate the aforementioned disadvantages of the conventional process. According to the present invention there is provided a method of forming self-aligned twin tubs of opposite conductivity type in a semiconductor substrate. The method comprises implanting an impurity of one conductivity type in the substrate over a region in which the twin tubs are to be formed, masking the implanted substrate to expose a selected portion thereof which is to form one of the tubs, etching the substrate in the exposed region to remove at least most of the initial implant from the substrate, implanting an impurity of the opposite conductivity type in the exposed region of said substrate, and thermally diffusing the implanted impurities diffused into the substrate to form twin tubs of said opposite conductivity types. By selectively removing the initial implant from the region that is to form the second tub, the method according to the invention becomes considerably shorter and simpler than the methods according to the prior art, and furthermore it has been found that it leads to significantly fewer crystal defects than were found in the prior art methods. Preferably, the substrate is of silicon and the thin oxide layer is formed on the substrate prior to implanting the impurity of one conductivity type, for example p type. In this case, the p type impurity is implanted through the thin oxide layer. However, if the rapid thermal oxidation method is used to grow very thin initial oxide, the thin oxide layer can be formed after the initial implant of the p type impurity, the latter occurring on the bare silicon. The thin oxide layer may be in the order of 200 Angstroms thick. The mask is applied by conventional techniques. A photoresist layer is first deposited, exposed through a photo mask, and subsequently developed. After developing, windows are formed in the exposed regions of the photomask, through which the etch can subsequently be formed. If the initial oxide is thick enough, the photoresist can be stripped from the substrate prior to performing the second implantation of the other conductivity type. The invention will now be described in more detail, by way of example only, with reference to the accompanying drawings, in which:- Figures 1 to 3 illustrate diagrammatically a conventional process for forming twin tubs; and Figures 4 to 7 show diagrammatically a process for forming twin tubs in accordance with the invention. In the conventional process shown in Figures 1 to 3, a thin silicon dioxide (Siθ2) layer 2 is grown or deposited on silicon substrate 1. A Silicon nitride (Si 3 N4) layer 3 is deposited on the thin oxide layer 2. The layer 3 is then covered with a photoresist layer (not shown) , which is exposed and developed to form a window over surface region 4 of the substrate 1. The exposed layers 2, 3 are then etched away (Figure 1). An n type ion implantation with phosphorus ions is performed into the exposed portion 4 to form an n-type implanted zone 5 underneath the surface of the exposed substrate region 4 and in the silicon nitride layer 3 over the unexposed portion of the substrate 1. A thick thermal oxidation is then carried out on the exposed region 4 to form thermal oxidation layer 6 (in the order of 1 μm) . Subsequently, the residual nitride layer 3 containing implant 5 is stripped from the substrate 1. A p-type ion implantation, for example with boron, is then performed to form p type zone 7 underneath the thin oxide layer 2 and in the thermal oxidation layer 6, which masks the underlying substrate. The implanted impurities are thermally diffused to form the respective p type and n type tubs 8 and 9 with a uniform overlying oxide layer 10. The upper level of the thick oxide layer, which contains the boron 7, is removed, and the filed oxide 10 is grown to a thickness of about lμm. As can be seen, this process requires a substantial number of steps. It also suffers from the disadvantage that it is liable to cause crystal defects in the substrate. In the process according to the invention, a thin oxide layer 2 (in the order of 200 Angstroms) is first thermally grown on the silicon substrate 1. A first p- type implantation with boron ions is performed over the whole of the surface of the substrate through the thin oxide layer 2 to form p type zone 7 under the thin oxide layer 2 (Figure 4) . A photoresist layer 11 is then deposited on the thin oxide layer 2, exposed and developed to form a window region over the part 4 of the substrate that is to become the n tub. The thin oxide layer 2 and the surface region of the substrate containing at least most of the n type implant 5 is then etched away (Figure 5) . A subsequent n type implant with phosphorus ions is then performed to produce n type zone 5 as shown in Figure 6. Finally, the photoresist layer 11 is removed and the two remaining implanted zones are thermally diffused to form p and n tubs 8 and 9 overlaid by thin oxide layer 10 (Figure 6) . Transistors can then be formed in the tubs by conventional techniques during further processing. The described process requires fewer steps than the prior art process while maintaining an accurate self-alignment with two micron technology. If a rapid thermal oxidation process is used to grow the thin oxide layer 2, the first two steps may be reversed. The initial p type implant can be performed on bare silicon, and the thinner oxide layer grown subsequently. If the initial thin oxide layer 2 is made thick enough, the photoresist layer 11 can be stripped prior to the second implantation of the n type conductivity impurity. In this case, the initial thin oxide layer 2 serves as the mask for the second implantation. In order to confirm the effectiveness of the process, polished slices of silicon wafer were processed according to the twin tub method based on Mitel Corporation's CS220A 2 micron process from initial oxidation to p well diffusion, i.e. as shown in Figure 4. The silicon etch depth of the substrate with the initial p-type implant was varied by varying the silicon etch time. The spreading resistance profile and four point probe mapping were used to investigate how much of the initial implant was removed with the silicon etch. The processing was carried out as follows: All silicon slices were 100 mm diameter, SEMI standard prime polished, and oriented as supplied by Wacker Siltronics. The n type slices had a resistivity of 10 to 15 ohm centimeter and the p type had a resistivity 32.34 to 36.74 ohm centimeter. The initial oxidation was carried out under standard CS200 A conditions (approximately 30 minutes at 950°C) to form a thin oxidation layer approximately 200 Angstroms thick. The initial implant was carried out by ion implantation with 1.9 E 12 phosphorus singly charged at 40 kv through the 200 Angstrom initial oxide layer. The mask was formed on the pattern wafers using the DH 18 test structure with positive resist. The silicon etch process was identical to the CS200A process, except the etch time was varied as follows: The p well implant was 1.9 E 12 boron, singly charged at 50 kv (standard Cs200A process) . The p well diffusion was then carried out under standard conditions for the CS200A process (400 minutes in pure oxygen at 1175°C) . The silicon etch step was measured with a DEKTAK (trade mark) surface profilometer at the wafer centre in accordance with CSA200A process requirements. The sheet resistance was mapped with a prometrix four probe system on blank wafers at 49 points per wafer and 6 mm. edge exclusion. The results were as follows: (correlation coefficient) . SHEET RESISTANCE MAPPING Sheet resistance was mapped with a PROMETRIX four point probe system on blank wafers at 49 points per wafer and 6 mm. edge exclusion. On all the actual p well structures, the sheet resistance pattern was characterized by an almost perfectly radial symmetry, with a strong negative radial gradient (i.e. resistance higher at the centre than at the edge) . These observations correlate with an actual etch rate lower at the centre than at the edge. For the actual P well structures: Log(S) = a + bD, where (with the same units as above) a=2.43, b=-7.722E-04 and r= -0.9948 (correlation coefficient) . Extrapolating this curve to S = 1.3% (value for the ideal P well) , a depth of 2750 Angstroms is obtained. This suggests that the LSL for this process is about 2750 Angstroms at the wafer centre. Spreading resistance profiles were measured with at a resolution of 0.05μm. Blank and patterned wafers were measured. The pattern profiled was that of a 600x600μm capacitor. Samples were taken at the edges of the wafers. NET CARRIER PROFILE The above results and observations show that the initial implant was indeed partially removed from the selectively etched silicon areas. The self-aligned twin-tub process based on an n- well technology requires the optimization of the following parameters, which can be determined by experiment in each case: P/P+ epitaxial silicon wafers The Epi layer thickness and resistivity affects latch- up, ESD, electrical parameters; substrate resistivity affects Latch-up, ESD Initial oxide thickness If the oxide layer is too thin, poor substrate protection against photoresist contamination during strip results. Too thick an oxide layer masks too much of the initial implant. The preferred thickness is about 200 Angstroms, but the actual thickness can be determined by experiment in each case. Initial Boron Implant enerσy and dose Too low energy causes poor transmission through the initial oxide, whereas too high energy causes the implant dose to reach too deep in the silicon to be removed efficiently by the silicon etch. N-well phosphorus implant enerσy and dose The implant dose affects the electrical parameters Silicon etch depth An etch depth that is too shallow results in poor removal of the initial boron implant. An etch depth that is too deep results in photo or step coverage problems. Uniformity and repeatability are important: a non-contact step measurement system is desirable for monitoring purposes, for example, commercial apparatus based on a dynamic laser focusing is available. N-well phosphorus implant enerσy & dose: Dose and energy affect electrical parameters. N-well diffusion Cycle temperature, duration and atmosphere affect electrical parameters, substrate boron outdiffusion. If the technology is n-well, the substrate must be p- type, which means that the initial implant should also be p-type. The implanted impurity should therefore normally be boron, which since it is a very light element penetrates deeper into the silicon than heavier elements such as phosphorus (n-type dopant) for the same implant energy. The standard implant energy for Mitel's CS200A process for the boron Pwell implant is 50Kev. Since the shallower the implant, the shallower the silicon etch required to remove it, experiments were performed to determine how low the initial boron implant energy could be before the uniformity of the p- well sheet resistivity was degraded. Also if n-well diffusion is carried out in pure oxygen, as is the case in the CS200A process, a considerable fraction of boron becomes incorporated in the oxide during the diffusion cycle. Two experimental lots were made, each with 6 n- type 10-15 ohm-cm polished slices. The wafers were processed through initial oxidation (200A) , a boron implant at 1.9E12/cm 2 , and a short p-well diffusion for two hundred minutes in pure oxygen at 1175°C. The oxide layer (about 350θA) was stripped and the sheet resistivity mapped as described above. The results were as follows: These results suggest that a 25 KeV boron implant is also . The described method permits self-aligned twin tubs to be fabricated in a manner which requires fewer processing steps than the prior art and which reduces the incidence of crystal defects.

Claims: CLAIMS 1. A method of forming self-aligned twin tubs of opposite conductivity type in a semiconductor substrate, characterized in that an impurity of one conductivity type is implanted in said substrate over a region in which the twin tubs are to be formed, said implanted substrate is masked to expose a selected portion thereof which is to form one of the tubs, said substrate is etched in said exposed region to remove at least most of the initial implant from the substrate, an impurity of the opposite conductivity type is implanted in said exposed region of said substrate, and the implanted impurities are thermally diffused into said substrate to form twin tubs of said opposite conductivity types. 2. A method as claimed in claim 1, characterized in that a thin oxide layer is formed on said substrate prior to implanting said impurity of one conductivity type, and said impurity of one conductivity type is implanted therethrough. 3. A method as claimed in claim 1, characterized in that a thin oxide layer is formed on said substrate subsequent to implanting said impurity of said one conductivity type. 4. A method as claimed in claim 2 or 3, characterized in that said thin oxide has a thickness sufficient to mask said substrate alone during implantation of said impurity of said second conductivity type, and said mask is removed prior to implanting said impurity of said other conductivity type. 5. A method as claimed in claim 1, characterized in that said thin oxide layer is formed by rapid thermal oxidation. 6. A method as claimed in claim 1, characterized in that said method employs a 2μ fabrication process. 7. A method as claimed in claim 1, characterized in that the silicon is etched to a depth of about 1,000 to 2,500 to remove most of the initial impurity implant in the exposed region. 8. A method as claimed in claim 2 or 3, wherein said thin oxide layer is about 200 Angstroms thick.

Inventors: HUET PIERRE, HUET, PIERRE
Applicants: MITEL CORP, MITEL CORPORATION
Application year: 1991
Main classification: H01L21
IPC codes: H01L21, H01L27