Optical modulation element and its manufacturing method

Abstract: An optical modulation element (1'',1''') comprising: a plurality of n common electrodes (Y1-Y4) on the assumption that n denotes an integer of 2 or more; m subelectrodes (Si1-Si3) which are electrically connected to one of the common electrodes (Y1-Y4) by electrical elements (71a-71d) on the assumption that m denotes an integer of 1 or more; and a plurality of segment electrodes (X1-X4) which confront the common electrodes (Y1-Y4) and the subelectrodes (S11-S41); in which when a first one (Si1) of the m subelectrodes (Si1-Si3) is electrically connected to an i-th one (Y i ) of the common electrodes (Y1-Y4) on the assumption that i denotes an integer from 1 to n, an m-th one (Si3) of the m subelectrodes (Si1-Si3) is connected to neither a reference potential nor another row electrode.

Description: The present invention relates to an optical modulation element comprising: first and second substrates which confront each other; a liquid crystal layer which is interposed between the first and second substrates; a plurality of column electrodes which are provided on said first substrate; a plurality of n main row electrodes which are provided on said second substrate; a plurality of n groups of m subelectrodes provided on said second substrate, each group being associated to and placed at one side of a respective main row electrode on the assumption that n denotes an integer equal or greater than 2, and that m denotes an integer equal or greater than 1, wherein each main row electrode is connected to the closest subelectrode of the group associated to it, and each subelectrode within the group to the adjacent one by electrical elements having predetermined impedances; and means adapted to apply line sequential scanning signals to the main row electrodes and signals corresponding to display patterns to the column electrodes. In a known ferroelectric liquid crystal panel, ferroelectric liquid crystal formed into a thin film is interposed between opposed electrodes. At this time, several limited states of the ferroelectric liquid crystal becomes stable as shown in Figs. 10a to 10c. In Figs. 10a to 10c, reference numeral 100 denotes a molecule of the ferroelectric liquid crystal, reference numeral 101 denotes a cone, reference numeral 102 denotes an upper substrate and reference numeral 103 denotes a lower substrate. In Figs. 10a and 10b, orientations of the molecules 100 of the liquid crystal are substantially uniform and spontaneous polarization of the molecules is directed upwardly or downwardly along a normal relative to the upper and lower substrates 102 and 103. In Fig. 10c, the molecules 100 of the liquid crystal are twisted in the direction of the normal relative to the upper and lower substrates 102 and 103. A direction of twist of the molecules 100 of the liquid crystal, which is opposite to that of Fig. 10c, may exist. Stable states of the molecules 100 of the liquid crystal may become different from those of Figs. 10a to 10c according to angle of inclination of the molecules 100 of the liquid crystal relative to the upper and lower substrates 102 and 103 due to kind of the orientation film and according to bending of the liquid crystal layer but can be schematically illustrated by Figs. 10a to 10c basically. Figs. 11a to 11c are top plan views of the liquid crystal of Figs. 10a to 10c observed from above the upper substrate 102, respectively. In Figs. 11a to 11c, reference numeral 110 denotes direction of spontaneous polarization, reference numeral 111 denotes a polarizer, reference numeral 112 denotes an analyzer, reference numeral 113 denotes a molecule of the liquid crystal in the vicinity of the upper substrate 102 and reference numeral 114 denotes a molecule of the liquid crystal in the vicinity of the lower substrate 103. When a liquid crystal panel is interposed between the polarizer 111 and the analyzer 112 intersecting at right angles, Fig. 11a corresponds to a bright state and Fig. 11b corresponds to a dark state. Thus, by using these uniform states in which the molecules 113 and 114 coincide, in position, with each other, the liquid crystal panel can give bright and dark displays. In the state of Fig. 11c in which the molecules 113 and 114 deviate from each other, the liquid crystal panel gives a gray display. The ferroelectric liquid crystal formed into a thin film has such stable states as described above and is unstable in other states. Therefore, if a voltage applied to the liquid crystal panel is increased, changes among these states occur suddenly at specific values of the voltage. Thus, relation between voltage applied to the liquid crystal panel and quantity of light transmitted through the liquid crystal panel exhibits sharp threshold characteristics. In case a voltage not exceeding this threshold voltage is applied to the liquid crystal panel, the liquid crystal is kept stable. Hence, in the liquid crystal panel, display of high contrast and large capacity can be obtained in a simple matrix arrangement of only the electrodes without the need for providing a non-linear element at each pixel as in a thin-film transistor. However, since the ferroelectric liquid crystal can assume a stable state restrictively as shown in Figs. 11a to 11c, it is extremely difficult to achieve a number of gradations. The state of gray display of Fig. 11c is stable only in a narrow voltage region in which the state of Fig. 11a changes to the state of Fig. 11b. Thus, it is difficult to obtain uniform intermediate gradation due to uniformity of the liquid crystal panel, etc. Therefore, a prior art ferroelectric liquid crystal panel usually employs binary display basically so as to obtain gradation through a plurality of pixels and a plurality of scannings as proposed, for example, by T. Leroux, F. Baume et al. in 1988 INTERNATIONAL DISPLAY RESEARCH CONFERENCE, p111-113. In this method, each of a scanning electrode and a signal electrode, which constitute each pixel, is required to be provided with one drive circuit. Several methods are proposed in which display of gradation is performed without increasing the number of the drive circuits. For example, in a method, liquid crystal response threshold is changed by providing a region in which thickness of a liquid crystal layer varies in one pixel as proposed by Y. Iwai et al. in Digest of 13th Liquid Crystal Conference (1987), p138-139. In another method, an intermediate voltage is applied to an subelectrode by dividing a range between a voltage and an earth potential through a resistance element. Especially, regarding the latter method, a concrete example is reported in JP-A- No. 63-316024 in which the main electrode and the subelectrode connected to a power source are connected by a resistance of 500 n and the subelectrode and the earth electrode are connected by a resistance of 500 Ω. However, this method has such drawbacks that power consumption is quite large and stability of liquid crystal on the subelectrode is low. This is partly because in many drive methods, positive or negative potential is applied to the sides of the scanning electrode and the signal electrode substantially at all times and thus, a rather large amount of current flows through the resistances substantially at all times. Furthermore, this may be partly because the subelectrode is grounded by the low resistance, so that drop of stability of liquid crystal on the subelectrode is greatly influenced by nonselected pulses, thereby resulting in unstable memory state. Accordingly, an essential object of the present invention is to provide an optical modulation element which is capable of displaying gradations stably by a single scanning with small power consumption without the need for increasing the number of pixels. In order to accomplish this object of the present invention, an optical modulation element as defined above (preamble of claim 1) is characterized in that, when the m subelectrodes of a group associated to an i-th main row electrode are placed between this and a (i-1)-th one on the assumption that i denotes an integer from 1 to n, a first one of the m subelectrodes is connected to the i-th main row electrode by means of electrical elements having predetermined impedances, whereas all the main row electrodes and all the subelectrodes are coupled to the column electrodes by the internal capacitance of the liquid crystal layer. Preferable embodiments are defined in the dependent claims. By the above described arrangement of the present invention, the voltage apply to the subelectrodes is made lower than that applied to the main row electrodes through voltage division or voltage delay caused by the electrical elements. Thus, by combining response of pixels on the subelectrodes and response of pixels on the main row electrodes, clear and stable display of gradations can be performed. Meanwhile, when the number of the subelectrodes connected to each main row electrode by the electrical elements is increased, more gradations can be displayed. Thus, in the present invention, the subelectrodes are connected to the main row electrodes by the electrical elements. Therefore, the present invention provides an optical modulation element of simple matrix type in which stable display of gradations can be performed by a single scanning with substantially no increase of power consumption without increasing the number of drive circuits. Features of the present invention will become apparent from the following description taken in conjunction with the preferred embodiments thereof with reference to the accompanying drawings, in which: Fig. 1 is a top plan view of an optical modulation element for describing the present invention; Fig. 1A is a fragmentary top plan view of one example of the optical modulation element of Fig. 1; Fig. 2 is a sectional view of the optical modulation element of Fig. 1; Figs. 3a to 3c are diagrams showing drive wave forms applied to common electrodes in the optical modulation element of Fig. 1; Figs. 4a to 4c are diagrams showing drive wave forms applied to segment electrodes in the optical modulation element of Fig. 1; Figs. 5a to 5f are diagrams showing voltage wave forms applied to each pixel in the optical modulation elements as decribed; Fig. 6 is a top plan view of the optical modulation element according for describing the present invention; Fig. 7 is a top plan view of optical modulation elements according to an embodiment of the present invention; Figs. 8a to 8f are voltage wave-form diagrams of the optical modulation element having resistors as electrical elements; Figs. 9a to 9f are voltage wave-form diagrams of the optical modulation element according to an embodiment of the present invention; Figs. 10a to 10c are schematic views showing molecules of ferroelectric liquid crystal (already referred to); and Figs. 11a to 11c are top plan views of the molecules of ferroelectric liquid crystal of Figs. 10a to 10c, respectively (already referred to). Before the description of the present invention proceeds, it is to be noted that like parts are designated by like reference numerals throughout several views of the accompanying drawings. Referring now to the drawings, there is shown in Fig. 1, a liquid crystal panel 1 acting as an optical modulation element. The liquid crystal panel 1 is constituted by an upper substrate 2, a lower substrate 3 and a liquid crystal layer interposed between the upper and lower substrates 2 and 3. Each of the upper and lower substrates 2 and 3 includes an electrically conductive thin film formed with an electrode pattern. Column electrodes X1 to X4 are provided on the upper substrate 2, while main row electrodes Y1 to Y4 and subelectrodes S11 to S41 are provided on the lower substrate 3. The number n of the common electrodes is set to 4, while the number m of the subelectrodes used for each common electrode is set to 1. If the number m is 2 or more, numerals 1, 2, 3, -- are sequentially allotted to the subelectrodes in increasing order of distance from each corresponding main row electrode. For example, in the case where the number m is 3, subelectrodes Si1 to Si3 (1≤i≤n) are connected between neighboring main row electrodes Y i and Y i-1 by resistors 6i1 to 6i3 and 5i as shown in Fig. 1A. Thus, the subelectrode Sil is connected to the main row electrode Y i by the resistor 6i1, while the subelectrode Si3 is connected to the main row electrode Y i-1 by the resistor 5i. Among the resistors 6i1 to 6i3 and 5i between the main row electrodes Y i and Y i-1 , the resistor 5i connecting the subelectrode Si3 and the main row electrode Y i-1 has a maximum impedance. The column electrodes X1 to X4 are connected to a signal voltage circuit by a flexible substrate 7. The main row electrodes Y1 to Y4 are connected to a scanning voltage circuit by the flexible substrate 7. Resistive paste 4 is coated linearly on the main row electrodes Y1 to Y4 and the subelectrodes S11 to S41 so as to be printed. In this case, since only portions between the main row electrodes Y1 to Y4 and the subelectrodes S11 to S41, in which the electrically conductive thin film is not present, act as resistors, these regions are, respectively, regarded as resistors 5b to 5d and 6a to 6d for convenience's sake. Each of the subelectrodes S11 to S41 is electrically connected to opposite neighboring ones of the main row electrodes Y1 to Y4 by the resistors 5b to 5d and 6a to 6d. Fig. 2 shows the liquid crystal panel 1. An overcoat 20 for preventing dielectric breakdown is provided on the column electrodes X1 to X4 on the upper electrode 2. Likewise, an overcoat 21 for preventing dielectric breakdown is provided on the main row electrodes Y1 to Y4 on the lower substrate 3. Furthermore, alignment layers 22 and 23 formed by oblique deposition of SiO are, respectively, provided on the overcoats 20 and 21. Ferroelectric liquid crystal 24 of ester series, which exhibits chiral smetic-C phase, is interposed between the alignment layers 22 and 23. In patterning of the electrodes in this embodiment, a distance of a gap between the main row electrode and the subelectrode for the resistors 5b to 5d and that for the resistors 6a to 6d are set to a ratio of 5 to 1 such that the resistors 5b to 5d and the resistors 6a to 6d have resistances of 10 kΩ and 2 kΩ, respectively. Meanwhile, the coated resistors are printed so as to have a fixed width. Thus, the resistors 5b to 5d having a resistance of 10 kΩ and the resistors 6a to 6d having a resistance of 2 kΩ can be obtained relatively easily. Meanwhile, even if width and thickness of the resistors are partially nonuniform, resistance value at the region changes uniformly, so that the ratio of the resistance values of 5 to 1, which determines divisional ratio of voltage, can be obtained substantially positively, thereby offering no problem for drive of the liquid crystal panel 1. In the case where transfer procedure from a film is employed in place of printing in order to form the resistors, the same excellent effects as those of printing can be achieved. Although not specifically shown, also when a method in which a resistor is coated on a flexible substrate so as to be printed or a method in which a resistor is formed on a circuit board are employed in addition to the substrates of the liquid crystal panel 1, the same effects can be obtained. Meanwhile, the ITO electrically conductive thin film used for the electrodes for the substrates is a resistor itself. Thus, the resistors can be formed by producing an extremely thin pattern of the electrically conductive thin film simultaneously with etching a pattern of the electrodes. At this time, by controlling width and length of the electrically conductive thin film acting as the resistors, proper resistances can be imparted to the resistors and display of gradations can be performed as in the above embodiment. The resistance value of the resistors 6a to 6d is determined by value of capacity of the liquid crystal layer and is based on such a condition that charging and discharging periods of the liquid crystal layer are sufficiently short, namely, the resistance value is sufficiently small. A limit at which influence of charging and discharging periods of the liquid crystal layer is negligible corresponds substantially to a case in which the resistors 6a to 6d assume a resistance value of 10 kΩ. The resistance value of the resistors 6a to 6d is set to 2 kΩ conservatively. Meanwhile, resistance value of the resistors 5b to 5d is determined by the resistance value of the resistors 6a to 6d and a desired divisional ratio of voltage. By adjusting the divisional ratio of voltage, gradations can be displayed properly. In this embodiment, the divisional ratio of voltage of 5 to 1 is optimum. In this embodiment, 4-pulse method having quiescent phase is employed. However, this method is not necessarily essential for the present invention and thus, ordinary 4-pulse method or 2-pulse method may be employed for driving the liquid crystal panel 1 without any problem. Hereinbelow, this 4-pulse method having quiescent phase is described. Figs. 3a to 3c show examples of drive wave form applied to the main row electrodes. When a scanning wave form of Fig. 3a is applied to the main row electrode Y3, writing is performed for liquid crystal on the main row electrode Y3 during a selected period t2. In this case, the wave form of Fig. 3b is applied to the main row electrode Y2 which has been selected during a period tl preceding the selected period t2. A nonselected wave form is applied to the main row electrode Y2 during the period t2. In the case where the above described voltage wave forms are applied to the main row electrodes Y3 and Y2, a wave form obtained by effecting voltage division at a ratio of 5 to 1 between the wave forms of Figs. 3a and 3b, namely the wave form of Fig. 3c is applied to the subelectrode S31. In this case, a selected wave form of a total of 8 pulses is applied to the subelectrode S21 during the periods t1 and t2. In order to drive the subelectrode S31 simultaneously with the main row electrode Y3, the selected pulse during the period t2 should have a value relatively similar to that of the main row electrodes Y2 and Y3. Also for this reason, the resistance value of the resistors 5b to 5d are required to be larger than that of the resistors 6a to 6d. Otherwise, the subelectrode S31 will be driven in dependence upon the main row electrode Y2. However, in this case, since a voltage of the selected pulse, which is low but is higher than a voltage of the nonselected pulse, is applied to the subelectrode S31 immediately after writing on the subelectrode S31, stability of writing on the subelectrode S31 deteriorates slightly. Therefore, it is desirable that the subelectrode S31 be driven in dependence upon the main row electrode Y3. Figs. 4a to 4c show examples of voltage pulse applied to the column electrodes. The voltage pulse are required to be outputted at a number of intermediate levels corresponding to the number of the subelectrodes. Since one subelectrode is provided for each main row electrode, achievable gradations are of 3 values in which (1) both the main row electrode and the subelectrode are in the OFF state, (2) only the main row electrode in the OFF state and (3) both the main row electrode and the subelectrode are in the ON state. Thus, the 3-value signal is applied to the column electrodes. In Figs. 4a to 4c, liquid crystal of the column electrodes X1, X2 and X3 is in the ON state, the gray state and the OFF state, respectively. In Fig. 1, the hatched portions illustrate areas of liquid crystal in the ON state. The signal wave forms shown in Figs. 4a to 4c are, respectively, applied to the column electrodes X1 to X3, respectively. This represents a voltage modulation type drive method in which the gray wave form of Fig. 4b assumes voltage intermediate between the ON wave form of Fig. 4a and the OFF wave form of Fig. 4c. However, this voltage modulation type drive method may be replaced by a pulse width modulation type drive method. When the drive wave forms of Figs. 3 and 4 are applied to the main row electrodes and the column electrodes, wave form applied to each pixel is determined by difference between the wave form of Fig. 3 and the wave form of Fig. 4 as shown in Figs. 5a to 5f. Figs. 5a to 5c show wave forms of voltage pulses applied between the main row electrode Y3 and each of the column electrodes X1 to X3, respectively. On the other hand, Figs. 5d to 5f show voltages applied between the subelectrode S31 and each of the column electrodes X1 to X3, respectively. A 4-pulse method having quiescent phase is employed in which writing pulses are constituted by 4 positive or negative pulses. In the 4 pulses, the first two pulses function to reset pixels have a fixed magnitude regardless of data to be written. Meanwhile, the last two pulses arranged to effect writing of pixels and magnitude of the last two pulses varies according to data to be written. It is well known that response of ferroelectric liquid crystal has sharp threshold characteristics. When magnitude of the last two pulses exceeds this threshold, writing of pixels is performed. In Fig. 5, the response threshold of ferroelectric liquid crystal is indicated by a voltage Vt. When writing pulse voltage exceeds the threshold Vt, the hatched regions in Fig. 1 respond and thus, 3-value display of the ON state, gray state and OFF state can be performed at pixels a, b and c, respectively. Meanwhile, as shown by the periods t1 and t2 in Figs. 5d to 5f, the writing pulse applied to liquid crystal on the subelectrode S31 is constituted by 8 pulses. Thus, as compared with a case in which liquid crystal on the subelectrodes is driven by only 4 pulses, drive margin of liquid crystal on the subelectrodes becomes wider, thereby resulting in its stable drive. However, in the 8 pulses, the first 4 pulses are influenced by the common electrodes of other stripe groups and are not essential for writing. In order to lessen this influence in this embodiment, the common electrodes are disposed, in the scanning direction, downstream of the subelectrodes which are driven in dependence upon the common electrodes, respectively. Since the pulses essential for writing are disposed at the last side of the 8 pulses, influence of the writing data signal at the time when other main row electrodes have been selected can be minimized. Fig. 6 shows another liquid crystal panel 1' in which the resistors 5b to 5d and 6a to 6d of the liquid crystal panel 1 are replaced by capacitors 61a to 61d and 62b to 62d. Since other constructions of the liquid crystal panel 1' are the same as those of the liquid crystal panel 1, description thereof is abbreviated for the sake of brevity. Figs. 2 to 5 apply to also the liquid crystal panel 1'. Also in the liquid crystal panel 1', the divided voltage is applied to the subelectrodes in the same manner as in the liquid crystal panel 1. The capacitors 62b to 62d have a capacity of 1,000 pF, while the capacitors 61a to 61d have a capacity of 5,000 pF. The capacity of the capacitors 61a to 61d is determined by capacity of the liquid crystal layer. If the capacity of the capacitor 61a to 61d is small, influence of a circuit leading to a signal voltage source through the capacitors of the liquid crystal layer is increased and thus, dependence upon patterns is likely to take place. This phenomenon can be prevented on the condition that the capacitors 61a to 61d have a capacity of about 1,000 pF. The capacity of the capacitors 61a to 61d is set to 5,000 pF conservatively. The capacity of the capacitors 62b to 62d is determined by an inverse of the divisional ratio of voltage of 5 to 1 and the capacity of 5,000 pF of the capacitors 61a to 61d so as to assume 1,000 pF. The capacitors are formed by coating dielectric material having high dielectric constant on the overcoats 20 and 21 (Fig. 2) for preventing dielectric breakdown. This method may be replaced by a method in which dielectric material having high dielectric constant is formed on an electrically conductive thin film on a liquid crystal substrate and further dielectric material is formed on the dielectric material, a method in which capacitors are coated on a flexible substrate so as to be printed and a method in which capacitors are formed on a circuit board. Fig. 7 shows a liquid crystal panel 1" according to an embodiment of the present invention. In the liquid crystal panel 1", each subelectrode is connected to one common electrode by each of electrical elements 71a to 71d. Since one subelectrode is driven in dependence upon each common electrode, the electrical elements 71a to 71d are provided. Since other construction details of the liquid crystal panel 1" are the same as those of the liquid crystal panel 1, description thereof is abbreviated for the sake of brevity. Figs. 2 to 4 also apply to the liquid crystal panel 1". In a first version, the electrical elements 71a to 71d are resistors each having a resistance of 10 kΩ. At this time, voltages are applied to pixels as shown in Figs. 8a to 8f. Figs. 8a to 8c show the voltages applied between the common electrode Y3 and each of the segment electrodes X1 to X3, respectively. At this time, the voltages shown in Figs. 8d to 8e are applied between the subelectrode S31 and each of the segment electrodes X1 to X3, respectively. The portion between the segment electrode and the common electrode or the subelectrode functions as a capacitor and charging of the capacitor is performed upon application of the voltage pulse thereto. At this time, charging of the capacitor on the common electrode Y3 is performed rapidly since resistance of the common electrode Y3 is negligible. However, since charging of the capacitor on the subelectrode S31 is performed through the resistor 71c, its wave form is made obtuse by CR time constant and voltage effectively applied to the liquid crystal layer is lessened. At this time, only regions exceeding the response threshold Vt respond. As a result, the hatched portions in Fig. 7 are turned on and 3-value display of the ON state, gray state and OFF state is performed at the pixels a, b and c, respectively. In an embodiment of the invention, the electrical elements 71a and 71d are capacitors each having a capacity of 1,000 pF. When the drive wave forms of Figs. 3 and 4 are applied to the liquid crystal panel 1"', voltages are applied to pixels as shown in Figs. 9a to 9f. Figs. 9a to 9c show the voltages applied between the common electrode Y3 and each of the segment electrodes X1 to X3, while Figs. 9d to 9f show the voltages applied between the subelectrode S31 and each of the segment electrodes X1 to X3. This is because voltage effectively applied to the liquid crystal layer is reduced due to capacity of the liquid crystal layer and voltage division performed by the capacitor connecting the subelectrode S31 and the common electrode Y3. Also in this embodiment, only regions exceeding the response threshold Vt respond, so that only the hatched portions in Fig. 7 respond and thus, clear 3-value display can be performed.

Claims: An optical modulation element (1", 1"') comprising: first and second substrates (2, 3) which confront each other; a liquid crystal layer which is interposed between the first and second substrates (2, 3); a plurality of column electrodes (X1-X4) which are provided on said first substrate (2); a plurality of n main row electrodes (Y1-Y4) which are provided on said second substrate (3); a plurality of n groups of m subelectrodes (S11-S41) provided on said second substrate (3), each group being associated to and placed at one side of a respective main row electrode (Y1-Y4) on the assumption that n denotes an integer equal or greater than 2, and that m denotes an integer equal or greater than 1, wherein each main row electrode is connected to the closest subelectrode of the group associated to it, and each subelectrode within the group to the adjacent one by electrical elements (71a-71d)having predetermined impedances; and means (8, 9) adapted to apply line sequential scanning signals to the main row electrodes (Y1-Y4) and signals corresponding to display patterns to the column electrodes (X1-X4); characterized in that the electrical elements (71a-71d) are capacitors. An optical modulation element (1", 1"') as claimed in claim 1, characterized by a ferroelectric liquid crystal layer (24). A method of manufacturing an optical modulation element (1"') as claimed in claim 1, wherein the electrical elements (71a-71d) are formed by printing. A method of manufacturing an optical modulation element (1"') as claimed in claim 1, wherein the electrical elements (71a-71d) are formed by transfer. An optical modulation element (1", 1"') as claimed in claim 1, wherein the electrical elements (71a-71d) are formed on the second substrate (3) on which the subelectrodes (S11-S41) are formed. An optical modulation element (1", 1"') as claimed in claim 5, wherein the electrical elements (71a-71d) are wholly or partially made of a material identical with that of the subelectrodes (S11-S41). A method of manufacturing an optical modulation element (1", 1"') as claimed in claim 6, wherein the electrical elements (71a-71d) are wholly or partially formed simultaneously with etching of patterns of the subelectrodes (S11-S41). An optical modulation element (1", 1"') as claimed in claim 1, wherein the electrical elements (71a-71d) are formed on a circuit board connected to the second substrate (3) on which the main row electrodes (Y1-Y4) and the subelectrodes (S11-S41) are formed. An optical modulation element (1", 1"') as claimed in claim 1, wherein the electrical elements (71a-71d) are formed on a flexible substrate connected to the second substrate (3) on which the main row electrodes (Y1-Y4) and the subelectrodes (S11-S41) are formed.

Inventors: NAKAO KENJI, WAKITA NAOHIDE, NAKAO, KENJI, WAKITA,NAOHIDE
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1991
Main classification: G02F1
IPC codes: G09G3, G02F1