Field effect transistor signal switching device

Abstract: A field effect transistor signal switching device includes a semiconductor substrate including an active region; an input electrode disposed on the substrate and including a source electrode disposed on the active region and a source pad; first and second output electrodes respectively including first and second drain electrodes disposed on the active region; and first and second control electrodes disposed on the substrate for controlling the selective transmission of an input signal applied to the input electrode to the first and second output electrodes, the first and second control electrodes respectively including first and second gate electrodes disposed on the active region between the source electrode and the first and second drain electrodes, respectively, first and second gate pads, and first and second connecting portions disposed on the substrate respectively electrically connecting the first and second gate electrodes to the first and second gate pads. An input line is connected to the source pad, first and second collinear output lines perpendicular to the input line are connected to the first and second output electrodes, respectively, and first and second control lines are connected to the first and second gate pads, respectively. In one embodiment, the first and second control lines are disposed on opposite sides of the first output line and generally parallel to the input line. In another embodiment, the first and second control lines are disposed on opposite sides of the input line and generally parallel to the first and second output lines.

Description: The present invention relates to a field effect transistor signal switching device for selectively switching an input signal from an input line to a selected one of two output lines occupying a reduced area and including a variety of geometrics for reducing design constraints in producing integrated circuits. A paper "Dual Gate GaAs FET Switches" by James L Vorhaus et al, IEEE Transactions on Electron Devices, volume ED-28, no. 2 (February 1981) pages 204 to 211 mentions P-I-N diodes for use as microwave signal switching devices, but proposes instead the use of "dual-gate field effect transistors" (DGFET) to provide a microwave switch with gain. These switches comprise one or more DGFET's connected in a common source arrangement. A first gate of each transistor receives the input signal, while a second gate receives a switching control signal. The input signal appears inverted and amplified at the drain of the DGFET, subject to the switching control signal. Figures 9 and 10 of the present application show an alternative form of FET switching device which has been considered by the present inventors but which have not been published prior to the present priority date. Figure 9 is a highly schematic plan view of a signal switching device 100 incorporating two field effect transistors (FETs) 17 and 18. The signal switching device of Figure 9 includes an input line 2, first and second output lines 3 and 4, and control lines 5 and 6. For clarity, the input line 2 is labelled I and the first and second output lines 3 and 4 are labelled O 1 and O 2 , respectively. The input, output, and control lines are electrically conducting metallizations or stripes, such as striplines, disposed on the substrate for conducting direct current and relatively high frequency signals. The input, output, and control lines as well as the FETs 17 and 18 are disposed on a semiconductor substrate 20 that is schematically illustrated in Figure 9. Output lines 3 and 4 are disposed at opposed ends of the signal switching device and are perpendicular to the input line 2. In response to a control signal applied to control line 5, FET 17 controls whether an input signal supplied to input line 2 reaches the output of line 3. Likewise, the FET 18 controls, in response to a control signal applied to the control line 6, whether the input signal is transmitted to the output line 4. The structure of the FET 17 is illustrated in detail in the plan view of Figure 10. The FET 18 is symmetrical to the FET 17 and does not need separate illustration for understanding. In Figure 10 and in the other figures, the same elements are given the same reference numbers. An active region 16 is disposed within substrate 20. As well known in the semiconductor arts, if the substrate 20 is a compound semiconductor, for example gallium arsenide, the substrate may be semi-insulating and the relatively low resistivity active region 16 may be formed by the ion implantation or diffusion of dopant impurities into the substrate or by another technique. An input electrode 7 includes a source electrode 7a disposed within the active region 16 on the substrate 20 and a source pad 7b disposed on the substrate 20 outside the active region 16. The source pad 7b is electrically connected to the source electrode 7a through an air bridge structure 12. As well known in the art, air bridge structures include an electrical conductor spaced from the surface of the substrate on which they are disposed that provides an electrical crossover path, i.e., an insulated separation, between two electrical conductors that cross each other. An electrically insulating material may be part of the air bridge structure and interposed between the insulated two electrical conductors but, preferably, in an air bridge structure the two electrical lines are separated by empty space. An output electrode 14 includes a drain electrode 14a disposed on the semiconductor substrate 20 within the active region 16 and a drain pad 14b disposed on the substrate 20 outside the active region 16. A control electrode 15 includes a gate electrode 15a disposed on the substrate 20 within the active region 16, between the source and drain electrodes 7a and 14a, a gate pad 15c, and a connecting portion 15b connecting the gate electrode 15a to the gate pad 15c. The connecting portion 15b passes underneath the air bridge structure 12 and is electrically insulated from the conducting portion of the air bridge that provides an electrical connection between the source electrode 7a and the source pad 7b. As shown in Figure 10, the input line 2 is connected to the source pad 7b, the output line 3 is connected to the drain pad 14b and the control line 5 is connected to the gate pad 15c. The operation of the signal switching device in Figure 9 is described with respect to the structure shown in Figure 10 and a symmetrical structure comprising FET 18, although that symmetrical structure not shown in detail in the figures. When an input signal is applied to input line 2 for transmission to the output line 3, the FET 17 is made conductive, i.e., switched "on", by the application of a voltage, such as 0 volts, to the control electrode 15 of the FET 17 through the control line 5. At the same time, the FET 18 is made non-conductive, i.e., turned "off" by applying a voltage, for example -5 volts, to the control electrode of the FET 18 through the control line 6. The input signal is thereby transmitted to the output line 3 and is not transmitted to the output line 4. Likewise, if the control signals applied to control lines 5 and 6 are interchanged, the FET 17 is turned "off" and the FET 18 is turned "on" so that the input signal applied to input line 2 is transmitted to output line 4. In the signal switching device described, two FETs are needed to switch the input signal between the two output lines. An active region must be formed for each of the two FETs and a relatively large area of the substrate 20 is required for the two FETs. Therefore it is difficult to reduce the area occupied by the signal switching device. In addition, the geometry of the signal switching device, i.e. the positional relationship of the input, output, and control lines, is limited, constraining the placement of components in the design of an integrated circuit including the device. It is an object of the present invention to provide a field effect transistor signal switching device employing only one FET for switching an input signal selectively between two output signal lines. It is another object of the invention to provide a signal switching device with a variety of input, output, and control line geometries for increased flexibility in designing integrating circuits including the signal switching device. The invention provides an integrated circuit including a field effect transistor signal switching device comprising: a semiconductor substrate including an active region; an input electrode disposed on the substrate and including a source electrode disposed on the active region and a source pad; first and second output electrodes respectively including first and second drain electrodes disposed on the active region; and first and second control electrodes disposed on the substrate, the first and second control electrodes respectively including first and second gate electrodes disposed on the active region between the source electrode and the first and second drain electrodes, respectively, first and second gate pads and first and second connecting portions disposed on the substrate respectively electrically connecting the first and second gate electrodes to the first and second gate pads, the integrated circuit further comprising: means for connecting an input signal to said input electrode; and means for applying switching control signals to said first and second control electrodes so as to switch said input signal selectively between the first and second output electrodes. The invention further provides a method of manufacturing an integrated circuit including a field effect transistor signal switching device, the method comprising: providing a switching device having an input electrode, first and second signal output electrodes and first and second control electrodes, providing means for connecting an input signal to the input electrode of said switching device; and providing means for applying switching control signals to the first and second control electrodes of said switching device so as to switch the input signal selectively between the first and second output electrodes, wherein the switching device comprises: a semiconductor substrate including an active region; said input electrode being disposed on the substrate and including a source electrode disposed on the active region and a source pad; said first and second output electrodes respectively including first and second drain electrodes disposed on the active region; and said first and second control electrodes being disposed on the substrate for controlling the selective transmission of the input signal from the input electrode to the first and second output electrodes in response to said switching control signals, the first and second control electrodes respectively including first and second gate electrodes disposed on the active region between the source electrode and the first and second drain electrodes, respectively, first and second gate pads and first and second connecting portions disposed on the substrate respectively electrically connecting the first and second gate electrodes to the first and second gate pads. The invention further comprises the use of such a device as claimed in claims 24 and 25. It is noted that an FET device having the same structure as the above mentioned switching device is disclosed in EP-A-0348998 for use as part of a differential amplifier integrated circuit. In that context, a bias current is supplied to the common source electrode of the device and a differential input signal is applied across the two gate electrodes. The geometry of the device is said to provide a pair of very well matched transistors. Other features and advantages of the invention will become apparent from the detailed description that follows. The detailed description of specific embodiments of the invention are for illustration only, since various additions and modifications within the scope of the invention will be apparent to those skilled in the art from the detailed description. Brief Description of the Drawings Figure 1 is a plan view of a signal switching device in accordance with an embodiment of the invention. Figure 2(a) is a plan view and Figure 2(b) is a cross-sectional view taken along line 2(b) - 2(b) of an FET in accordance with an embodiment of the invention. Figure 3(a) is a plan view and Figure 3(b) is a partial sectional view taken along line 3(b) - 3(b) of Figure 3(a) of a signal switching device in accordance with an embodiment of the invention. Figure 4 is a plan view of a signal switching device in accordance with an embodiment of the invention. Figure 5 is a plan view of a signal switching device in accordance with an embodiment of the invention. Figure 6(a) is a plan view and Figure 6(b) is a cross-sectional view taken along line 6(b) - 6(b) of Figure 6(a) of an FET in accordance with an embodiment of the invention. Figure 7(a) is a plan view and Figure 7(b) is a partial sectional view taken along line 7(b) - 7(b) of Figure 7(a) of a signal switching device in accordance with an embodiment of the invention. Figure 8 is a plan view of a signal switching device in accordance with an embodiment of the invention. Figure 9 is a plan view of an alternative signal switching device, not according to the present invention. Figure 10 is a plan view of an FET employed in the alternative signal switching device of Figure 9. Detailed Description of Preferred Embodiments Figure 1 is a plan view of an field effect transistor signal switching device 1 in accordance with an embodiment of the invention. Switching device 1 includes an FET 101. The other elements of the embodiment of the invention shown in Figure 1 are the same as those identified by corresponding reference numbers in Figure 9. An embodiment of an FET 101 used in the switching device 1 is shown in a plan view in Figure 2(a) and in a sectional view in Figure 2(b). The elements of the FET 101 that are the same as those elements described with respect to Figure 10 are given the same reference numbers. The FET 101 includes an input electrode 7 comprising a source electrode 7a disposed on the active region 16 and a source pad 7b disposed on the substrate 20 outside the active region 16. A first drain electrode 8a and a second drain electrode 9a are disposed within the active region 16 on the substrate 20 on opposite sides of the source electrode 7a. A first control electrode 10 includes a gate electrode 10a, a connection portion 10b, and a gate pad 10c. The gate electrode 10a is disposed on the active region 16 between the source electrode 7a and the first drain electrode 8a. The connecting portion 10b electrically connects the gate electrode 10a to the gate pad 10c on the substrate 20 outside the active region 16. Similarly, a second control electrode 11 includes a gate electrode 11a disposed on the substrate 20 in the active region 16 between the source electrode 7a and the second drain electrode 9a. A connecting portion 11b of the control electrode 11 connects the gate electrode 11a to the gate pad 11c of the control electrode 11. The first and second control lines 5 and 6 are respectively connected to the gate pads 10c and 11c. The input line 2 is connected to the source pad 7b and the output lines 3 and 4 are respectively connected to the first and second drain electrodes 8a and 9a. In the arrangement of Figures 1 and 2(a), the control lines 5 and 6 lie on opposite sides of one of the output lines, namely output line 3, and are generally parallel to the input line 2. The FET structure of Figure 2(a) including two gate electrodes permits selective transfer of an input signal applied to the input line 2 to either of the output lines 3 and 4. The switching is achieved by applying complementary voltages to the gate electrodes 10a and 11a through the gate pads 10c and 11c. For example, a 0 voltage control signal may be applied to gate electrode 10a while a -5 volt control signal is applied to the gate electrode 11a. As a result, the input signal is transferred to the first drain electrode 8a, but not to the second drain electrode 9a. When the control signals are interchanged, the input signal is transferred only to the output line 4 and not to the output line 3. Thus, selective switching of an input signal between two different output lines is achieved with a single FET that includes two gate electrodes and two drain electrodes. The area required for the FET 101 is only about two-thirds as large as the area required for the two FETs 17 and 18 of the prior art structure of Figure 9. Therefore, the area required for a signal switching device in accordance with the invention is reduced. A plurality of the FETs 101 of Figure 2 can be connected in parallel as a single, higher power capacity signal switching device in accordance with the invention. An embodiment of such a construction is shown in Figures 3(a) and 3(b). Figure 3(b) is a partial cross-sectional view of the structure shown in plan view in Figure 3(a) showing details of the air bridge construction described below. In the multiple FET structure of Figures 3(a) and 3(b), the same elements are given the same reference numbers as in Figures 1 and 2(a). The structure of Figure 3(a) includes individual FETs, such as the FET 13, each having a separate active region 16 in the substrate 20. Each individual FET includes first and second drain electrodes 8a and 9a, a centrally disposed source electrode 7a and gate electrodes 10a and 11a respectively disposed between the source electrode 7a and the first and second drain electrodes 8a and 9a. The source electrodes 7a are commonly connected to a source pad 7b through air bridge structures 121. One of the source electrodes 7a, the lowermost source electrode 7a in Figure 3, is directly connected to the source pad 7b without using an air bridge structure 121. Those air bridge structures provide an electrical connection crossing over and insulated from the parallel interconnection of the gate electrodes 10a through the connecting portion 10b to the gate pad 10c. The first drain electrodes 8a of each of the individual FETs are connected together through an air bridge structure 122. That air bridge structure crosses over the gate electrodes 10a and 11a as well as the source electrodes 7a and second drain electrodes 9a without making electrical contact with them. Likewise, an air bridge structure 123 provides parallel interconnection of the second drain electrodes of the FETs. The interrelationship of these air bridge structures is best seen in Figure 3(b). There, for clarity, the air bridge structures are shown as including interconnectors disposed at different heights above the surface of the substrate 20, but those different heights are not essentials and all air bridge conductors may lie in substantially the same plane. Finally, the gate electrodes 11a are electrically connected in parallel through the connecting portion 11b to the gate pad 11c. The structure of Figure 3(a), like the structures of Figures 1 and 2(a) has input and output lines 3 and 4 lying along the same general line and disposed perpendicular to the input line 1. The control lines 5 and 6 are generally perpendicular to the output lines 3 and 4 and generally parallel to the input line 1. The operation of the structure of Figure 3(a) is identical to the operation of the structure of Figure 2(a). Yet another embodiment of a signal switching device according to the invention is shown in plan view in Figure 4. The structure of Figure 4 differs from the structure of Figure 3(a) in two important respects. First, in the structure of Figure 4, only a single, elongate active region 26 is present in the substrate 20 and a plurality of FETs is present in that common active region 26. Because of the use of a common active region 26 in the structure of Figure 4, additional space savings over the structure of Figure 3(a) is achieved although the possibility of signal leakage through an "off" FET is increased. In the structure of Figure 4, the source electrodes, the first and second drain electrodes, and the gate electrodes are arranged in a different sequence from that of Figure 3. Each source electrode 7a is disposed between a first and a second drain electrode 8a and 9a. However, unlike the structure of Figure 3(a), first and second drain electrodes are never directly adjacent to each other. Instead, the structure of Figure 4 includes sequentially disposed repetitive units of a first drain electrode 8a, a first gate electrode 10a, a source electrode 7a, a second gate electrode 11a, a second drain electrode 9a, a second gate electrode 11a, a source electrode 7a, and a first gate electrode 10a, provided with an appropriate drain electrode at one end of a complete structure including a plurality of the units. In other words, in the structure of Figure 4, gate electrodes are sequentially arranged in pairs of gate electrodes 11a and gate electrodes 10a. As in the structure of Figure 3(a), the gate electrodes 10a are all connected to the connecting portion 10b, i.e. in parallel, to the gate pad 10c. Likewise, the gate electrodes 11a are connected in parallel to the gate pad 11c through the connecting portion 11b. The source electrodes 7a are connected to the source pad 7b through the air bridge structures 121. The first drain electrodes 8a and the second drain electrodes 9a are respectively connected together, in parallel, by the air bridge structures 122 and 123, respectively. With this structure and the respective source, first drain, second drain, first gate, second gate electrodes respectively connected parallel, a different operational arrangement from that of Figure 3(a) is achieved. When the first gate electrodes 10a are biased to turn respective FETs "on" and the second gate electrodes 11a are biased to turn respective FETs "off", the input signal flows from two source electrodes 7a to the first drain electrode 8a disposed intermediate those two source electrodes. In other words, a single drain electrode collects current from each of two source electrodes. Likewise, when the control signals applied to the gate electrodes are interchanged, each adjacent second drain electrode 9a collects current from the two source electrodes 7a. Another embodiment of a signal switching device according to the invention is shown in a schematic plan view in Figure 5. The switching device of Figure 5 is geometrically different from that of Figure 1 and includes an FET 103 that is different in structure from the FET 101. In the structure of Figure 5, the control lines 5 and 6 are generally parallel to the first and second output lines 3 and 4 instead of being perpendicular to those lines as in the structure of Figure 1. In addition, the control lines 5 and 6 lie on opposite sides of the input line 2 rather than on the same side of the input line as in the embodiment of Figure 1. An FET structure for use in the signal switching device of Figure 4 is shown in plan and sectional views in Figures 6(a) and 6(b). The FET 103, unlike the FET 101 of Figure 2(a), includes air bridge structures to achieve the geometric arrangement of Figure 5. In addition to the elements of FET 101 of Figure 2(a), the FET 103 of Figure 6(a) includes an auxiliary source electrode 71 disposed at one end of the active region 16. The auxiliary source electrode 71 is connected by an air bridge structure 12b to the source electrode 7a that is disposed between the gate electrodes 10a and 11a. In effect, the auxiliary source electrode 71 supplants the source pad 7b. The first drain electrode 8a is electrically connected to a first drain pad 8b disposed on the substrate 20 outside the active region 16 by an air bridge structure 12a. A second drain electrode 9a is directly connected on the surface of the substrate 20 to a second drain pad 9b lying outside the active region 16. The operation of the FET structure 103 is identical to that of the FET 101 of Figure 2 and thus does not need repeated description. The geometrically complementary structures of Figures 2(a) and 6(a) permit an integrated circuit designer to choose a signal switching device having a geometry meeting the constraints of other circuitry elements. Thereby, the freedom in designing an integrated circuit including a signal switching device is improved. In Figures 7(a) and 7(b) plan and partial sectional views of a structure including a plurality of the FETs 103 of Figure 6(a) connected in parallel is shown. The structure of Figure 7(a) and 7(b) is analogous to the structure of Figures 3(a) and 3(b) in the same way that the structure of Figure 6(a) is analogous to the structure of Figure 2(a). Just as with the embodiment of Figure 3(a), in the embodiment of Figure 7(a), a larger signal handling capacity is achieved because of the parallel interconnection of a plurality of FETs. Otherwise, the operation of the structure of Figure 7(a) is identical to that of Figure 6(a). In the structure of Figure 7(a), each of the FETs has an individual active region 16. Air bridge structures 12c electrically connect the first drain electrode 8a of each of the FETs to drain pad 8b. Air bridge structure 12d electrically connects the second drain electrode 9a of each of the FETs to the drain pad 9b. One second drain pad 9a, the lowermost second drain pad in Figure 7(a), is directly connected to the drain pad 9b without an air bridge structure. The air bridge structures insulate the first and second drain electrodes 8a and 9a from the connecting parts of 10b and 11b of the control electrodes 10 and 11. The gate electrodes 10a and 11a are respectively connected in parallel by the connecting portions 10b and 11b to the gate pads 10c and 11c, respectively. The source electrodes 7a are interconnected in parallel by an air bridge structure 124 that is connected to an auxiliary source pad 81 disposed on the substrate 20 outside the active region 16. The auxiliary source pad 81 replaces the source pad 7b of Figure 3(a). Yet another embodiment of the invention is shown in a plan view in Figure 8. The structure of Figure 8 is analogous to the structure of Figure 4 but those structures differ in the geometric arrangements of the input and output lines. Unlike the structure of Figure 7(a), the structure of Figure 8 includes a single, common active region 26 where the source, drain, and gate electrodes are present. A repetitive unit of the structure of Figure 8 includes a first drain electrode 8a, a first gate electrode 10a, a source electrode 7a, a second gate electrode 11a, a second drain electrode 9a, a second gate electrode 11a, a source electrode 7a, and a first gate electrode 10a. These elements in repetitive units are sequentially disposed on the active region 26. The complete structure includes an appropriate drain electrode added at at least one end of the assembled units. Otherwise, the elements shown in Figure 8 are the same as those identified and described with respect to Figure 7(a) and do not need further description. Like the structure of Figure 7(a), the respective gate electrodes, respective first and second drain electrodes, and the source electrodes in the structure of Figure 8 are respectively electrically connected in parallel. The operation of the structure of Figure 8 is the same as that of the structures of Figure 4. In the structure of Figure 8, the auxiliary source electrode 81 is disposed on the substrate 20 within the active region 26 rather than outside the active regions 16 as in the structure of Figure 7(a). As with the structures of Figures 6(a) and 7(a), in the structure of Figure 8 the control lines are generally parallel to the output lines 3 and 4 and are disposed on opposite sides of the input line 2. In all of the structures described, the signal switching devices are constructed around single FETs including two gate electrodes for selectively controlling the transmission of a signal from an input line to one of two output lines. In some embodiments of the invention, FETs are connected in parallel to increase their signal handling capacity. Embodiments of the invention permit selection between various geometric positions of the control lines relative to the input and output lines, increasing the freedom of the integrated circuit designer. The invention may be constructed using various semiconductor materials and is not limited to a particular material. However, relatively high frequency signal switching devices may be realized using gallium arsenide or indium phosphide with striplines for the input, output, and control lines.

Claims: An integrated circuit including a field effect transistor signal switching device comprising: a semiconductor substrate (20) including an active region (16); an input electrode (7) disposed on the substrate and including a source electrode (7a) disposed on the active region and a source pad (7b); first and second output electrodes respectively including first and second drain electrodes (8a, 9a) disposed on the active region; and first and second control electrodes (10, 11) disposed on the substrate, the first and second control electrodes respectively including first and second gate electrodes (10a, 11a) disposed on the active region between the source electrode and the first and second drain electrodes, respectively, first and second gate pads (10c, 11c) and first and second connecting portions (10b, 11b) disposed on the substrate respectively electrically connecting the first and second gate electrodes to the first and second gate pads, the integrated circuit further comprising: means for connecting an input signal to said input electrode; and means for applying switching control signals to said first and second control electrodes so as to switch said input signal selectively between the first and second output electrodes. The integrated circuit of claim 1, further including an input line (2) disposed on the substrate and electrically connected to the source pad, first and second output lines (3, 4) disposed on the substrate and electrically connected to the first and second output electrodes, respectively, first and second control lines (5, 6) disposed on the substrate and electrically connected to the first and second gate pads, respectively, wherein the first and second output lines are disposed on opposite sides of the switching device and the input line is generally perpendicular to the first and second output lines. The integrated circuit of claim 2 wherein the first and second control lines (5, 6) are disposed on opposite sides of the first output line (3) generally parallel to the input line (2). The integrated circuit of claim 1 wherein the switching devices includes: a plurality of spaced apart active regions (16, Fig 3(a)) serially arranged in the substrate; a source electrode (7a) disposed on the substrate on each active region; first and second drain electrodes (8a, 9a) disposed on each active region on opposite sides of the source electrode of each respective active region; first and second gate electrodes (10a, 11a) disposed on the substrate on each active region between the source electrode and first and second drain electrodes, respectively, of each respective active region, the connecting portions (10b, 11b) of the first and second gate electrodes respectively electrically connecting together the first and second gate electrodes of the plurality of active regions; and a first air bridge structure (121) electrically connecting source electrodes to the source pad, a second air bridge structure (122) electrically connecting together the first drain electrodes, and a third air bridge structure (123) electrically connecting together the second drain electrodes. The integrated circuit of claim 4, further including an input line (2) disposed on the substrate and electrically connected to the source pad; first and second output lines (3, 4) disposed on the substrate and electrically connected to the first and second drain electrodes, respectively; and first and second control lines (5, 6) disposed on the substrate and electrically connected to the first and second gate pads, respectively. The integrated circuit of claim 5 wherein the first and second output lines (3, 4) are disposed on opposite sides of the plurality of active regions, the input line (2) is generally perpendicular to the first and second output lines, and the first and second control lines (5, 6) are generally parallel to the input line. The integrated circuit of claim 1, wherein the switching device includes an elongate active region (26) disposed in the substrate; a plurality of first and second drain electrodes (8a, 9a, Fig 4) alternatingly disposed in the active region; a plurality of source electrodes (7a) disposed on the active region, each source electrode being disposed between a first drain electrode and a second drain electrode; a first gate electrode (10a) disposed on the active region between each adjacent source electrode and first drain electrode and a second gate electrode (11a) disposed on the substrate between each source electrode and each adjacent second drain electrode, the first connecting portion of the first control electrode electrically connecting the first gate electrodes to the first gate pad and the second connecting portion of the second control electrode electrically connecting the second gate electrodes to the second gate pad; and a first air bridge structure (121) electrically connecting source electrodes to the source pad, a second air bridge structure (122) electrically connecting together the first drain electrodes, and a third air bridge structure (123) electrically connecting together the second drain electrodes. The integrated circuit of claim 7 including: an input line (2) disposed on the substrate and electrically connected to the source pad; first and second output lines (3, 4) disposed on the substrate and electrically connected to the first and second drain electrodes, respectively; and first and second control lines (5, 6) disposed on the substrate and electrically connected to the first and second gate pads, respectively. The integrated circuit of claim 8 wherein the first and second output lines (3, 4) are disposed on opposite sides of the elongate active region (26), the input line (2) is generally perpendicular to the first and second output lines and the first and second control lines are generally parallel to the input line. The integrated circuit of claim 1 wherein the first and second drain electrodes (8a, 9a, Fig 6(a)) are disposed on the active region (16) on opposite sides of the source electrode (7a) and first and second drain pads (8b, 9b) are disposed outside the active region, and wherein the switching device further includes a first air bridge structure (126) electrically connecting the source electrode to the source pad and a second air bridge structure (12a) electrically connecting the first drain electrode (8a) to the first drain pad (8b), the second drain electrode being electrically connected to the second drain pad. The integrated circuit of claim 10, further including an input line (2) disposed on the substrate and connected to the source pad, first and second output lines (3, 4) disposed on the substrate and electrically connected to the first and second drain pads (8b, 9b) respectively, first and second control lines (5, 6) disposed on the substrate and electrically connected to the first and second gate pads (10c, 11c), respectively, wherein the first and second output lines are disposed on opposite sides of the switching device and the input line is generally perpendicular to the first and second output lines. The integrated circuit of claim 11 wherein the first and second control lines are disposed on opposite sides of the input line generally parallel to the first and second output lines. The integrated circuit of claim 10, wherein the switching device includes a plurality of spaced apart active regions (16, Fig 7(a)) serially arranged in the substrate; a source electrode (7a) disposed on the substrate on each active region; first and second drain electrodes (8a, 9a) disposed on each active region on opposite sides of the source electrode of each respective active region; first and second gate electrodes (10a, 11a) disposed on the substrate on each active region between the source electrode and first and second drain electrodes, respectively, of each respective active region, the connecting portion (10b) of the first and second gate electrodes respectively electrically connecting together the first and second gate electrodes of the plurality of active regions; and a second air bridge structure (12c) electrically connecting the first drain electrodes to the first drain pad and a third air bridge structure (12d) electrically connecting second drain electrodes to the second drain pad, the first air bridge structure (124) electrically connecting the source electrodes to the source pad. The integrated circuit of claim 13, further including: an input line (2) disposed on the substrate and electrically connected to the source pad; first and second output lines (3, 4) disposed on the substrate and electrically connected to the first and second drain pads, respectively; and first and second control lines (5, 6) disposed on the substrate and electrically connected to the first and second gate pads, respectively. The integrated circuit of claim 14 wherein the first and second output lines are disposed on opposite sides of the plurality of active regions, the input line is generally perpendicular to the first and second output lines, and the first and second control lines are generally parallel to the output line. The integrated circuit of claim 10 wherein the switching device includes: an elongate active region (26, Fig 8) disposed in the substrate; a plurality of first and second drain electrodes alternatingly disposed in the active region; a plurality of source electrodes disposed on the active region, each source electrode being disposed between a first drain electrode and a second drain electrode; a first gate electrode disposed on the active region between each adjacent source electrode and first drain electrode and a second gate electrode disposed on the substrate between each source electrode and each adjacent second drain electrode, the first connecting portion (106) of the control electrode electrically connecting the first gate electrodes (10a) to the first gate pad (10c) and the second connecting portion (11b) of the control electrode electrically connecting the second gate electrodes (11a) to the second gate pad (11c); and a second air bridge structure (12c) electrically connecting the first drain electrodes to the first drain pad and a third air bridge structure (12d) electrically connecting second drain electrodes to the second drain pad, the first air bridge structure (124) electrically connecting the source electrodes to the source pad. The integrated circuit of claim 16, further including an input line (2) disposed on the substrate and connected to the source pad, first and second output lines (3, 4) disposed on the substrate and electrically connected to the first and second drain pads, respectively, first and second control lines (5, 6) disposed on the substrate and electrically connected to the first and second gate pads, respectively, wherein the first and second output lines are disposed on opposite sides of the switching device and the input line is generally perpendicular to the first and second output lines. The integrated circuit of claim 17 wherein the first and second output lines are disposed on opposite sides of the elongate active region, the input line is generally perpendicular to the first and second output lines and the first and second control lines are generally parallel to the first and second output lines. An integrated circuit according to any preceding claim wherein said substrate comprises gallium arsenide or indium phosphide. An integrated circuit according to any of claims 2, 3, 5, 6, 8, 9, 11, 12, 14, 15, 17 and 18, wherein said input line and output lines comprise stripline conductors for high frequency signals, and wherein the semiconductor substrate comprises gallium arsenide or indium phosphide. An integrated circuit according to any of claims 3, 5, 6, 8, 9, 11, 12, 14, 15, 17 and 18, wherein said input line, said output lines and said control lines compromise stripline conductors for high frequency signals, and wherein said substrate comprises gallium arsenide or indium phosphide. A method of manufacturing an integrated circuit including a field effect transistor signal switching device, the method comprising: providing a switching device having an input electrode, first and second signal output electrodes and first and second control electrodes, providing means for connecting an input signal to the input electrode of said switching device; and providing means for applying switching control signals to the first and second control electrodes of said switching device so as to switch the input signal selectively between the first and second output electrodes, wherein the switching device comprises: a semiconductor substrate (20) including an active region (16); said input electrode (7) being disposed on the substrate and including a source electrode (7a) disposed on the active region and a source pad (7b); said first and second output electrodes respectively including first and second drain electrodes (8a, 9a) disposed on the active region; and said first and second control electrodes (10, 11) being disposed on the substrate for controlling the selective transmission of the input signal from the input electrode to the first and second output electrodes in response to said switching control signals, the first and second control electrodes respectively including first and second gate electrodes (10a, 11a) disposed on the active region between the source electrode and the first and second drain electrodes, respectively, first and second gate pads (10c, 11c) and first and second connecting portions (10b, 11b) disposed on the substrate respectively electrically connecting the first and second gate electrodes to the first and second gate pads. A method as claimed in claim 22, wherein the switching device comprises all the switching device technical features of the integrated circuit as claimed in any of claims 2 to 21. A method of switching signals comprising the steps of: providing a field effect transistor signal switching device having an input electrode, first and second signal output electrodes and first and second control electrodes, applying an input signal to the input electrode of said switching device; and applying switching control signals to the first and second control electrodes of said switching device so as to switch the input signal selectively between the first and second output electrodes, wherein the switching device comprises: a semiconductor substrate (20) including an active region (16); said input electrode (7) being disposed on the substrate and including a source electrode (7a) disposed on the active region and a source pad (7b); said first and second output electrodes respectively including first and second drain electrodes (8a, 9a) disposed on the active region; and said first and second control electrodes (10, 11) being disposed on the substrate for controlling the selective transmission of the input signal from the input electrode to the first and second output electrodes in response to said switching control signals, the first and second control electrodes respectively including first and second gate electrodes (10a, 11a) disposed on the active region between the source electrode and the first and second drain electrodes, respectively, first and second gate pads (10c, 11c) and first and second connecting portions (10b, 11b) disposed on the substrate respectively electrically connecting the first and second gate electrodes to the first and second gate pads. A method as claimed in claim 24, wherein the switching device comprises all the switching device technical features of the integrated circuit as claimed in any of claims 2 to 21.

Inventors: ANDOH NAOTO, ANDOH, NAOTO, Andoh, Naoto, c/o Mitsubishi Denki K.K. Optelec.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1991
Main classification: H01L29
IPC codes: H01L27, H03K17, H01L29, H01L21