BATTERY VOLTAGE MEASUREMENT SYSTEM

Abstract: A temperature stable, battery measurement system for measuring discrete voltages of serially connected battery modules making up a battery power supply (10) wherein there would be connected to each junction between cells one terminal of a dual-level voltage responsive switch (SW1-SW17) and wherein the other terminal of each switch is connected to a common terminal (16). The switches are identical, and each would close at a first voltage across it and open at a second, slight higher, voltage. A ramp voltage is generated and connected between the common terminal (16) and the negative terminal (12) of the battery power supply. The ramp voltage and current through each switch circuit are concurrently measured and displayed wherein the difference in voltage between the appearance of any two current pulses through any two switches is illustrative of the battery voltage of the battery module connected between the two switches.

Description: Battery Voltage Measurement System Technical Field This invention relates generally to measurements of battery power supplies, and particularly to a temperature stable system for accurately measuring the voltage of individual battery modules making up a battery power supply. Background Art There are many instances in which battery cells, or battery modules, are serially connected in a bank or banks to provide a higher voltage than otherwise available. Unfortunately, the condition of the bank of cells as a whole is dependent upon the condition of individual cells or modules, and it is well known that in order to detect and locate a deteriorating one of these, individual measurements must be made at the cell or module level. As an example, where there is a bank voltage of 126 volts, it might be in the form of ten 12.6-volt lead acid batteries. In such case, condition measurements would typically require that each individual 12-volt battery be subject to measurement, which would necessitate the wiring harness extending from each battery back to the point of instrumentation making the measurement, and wherein there would be a wire for each terminal, or, in this case, a total of 11 wires. This has been regarded as quite cumbersome. Accordingly, applicant has devised a battery voltage measurement system described in co-pending application Serial No. 07/498,702 having a plurality of bi-level switching circuits each forming a switch that closes at a discrete voltage level and opens at a set, slightly -higher potential. One terminal of each of these switches is connected to a common lead, and the other terminal of these switches is connected to one of the positive-to-negative connections between the discrete battery cells making up the bank of batteries. Thus, each positive-to-negative battery connection is also coupled in parallel to the common lead via the bi-level switches. A ramp voltage is generated and applied between the common lead and the battery bank, sequentially causing the bi-level switches to first close and then open, sequentially generating a current pulse from each battery. The ramp voltage and current pulses through this circuit is concurrently measured and displayed wherein the difference in voltage between the current pulses, with the first pulse utilized as a reference, is illustrative of the battery voltage of the individual battery cells making up the bank of batteries. While this scheme works relatively well, problems have become apparent. Notably, in each of the bi- level switch circuits, a diode passes the current generated by the difference in ramp voltage and battery voltage. This diode has proved to have instabilities related to temperature, which in turn causes inaccurate measurements of battery voltage. Further, the design of the circuitry of the bi-level switches includes a field effect transistor (FET) that is utilized to switch the current, with this FET controlled by a NPN transistor. This transistor and FET are also subject to temperature instabilities and noise, such as noise generated by battery charging equipment, that causes nonlinear responses from the FET and transistor. In accordance with the foregoing, is an object of this invention to provide an improved battery voltage measurement system which is insensitive to temperature gradients between discrete bi-level switches of the invention, has better response than the circuitry of prior art, and is insensitive to noise generated by switching circuitry in battery charging networks. Disclosure of_ Invention In accordance with this invention, one connection of a plurality of voltage responsive switches is coupled to intermediate terminals of a bank of battery modules, one switch per intermediate terminal. The 5 other connection of the switches is coupled to a common terminal. A ramp voltage is applied between the common terminal and the battery module, this ramp voltage being such as to extend from below a voltage of one of the batteries to just in excess of the total 10. voltage of the bank of batteries. As the voltage is ramped up, the switches are sequentially closed and opened, giving rise to current pulses. Both the ramp voltage and instantaneous current through this arrangement are coordinately provided as outputs, 15 wherein the voltage between discrete current pulses are used to determine battery condition. Brief Description of the Drawings Fig. 1 is a block diagram of an embodiment of the invention. 0 Fig. 2 is a schematic diagram of one of the switches employed in the system and provided with integral temperature compensating circuitry. Fig. 3 is an osci llographic display of current versus voltage, particularly illustrating the 5 operation of the system. Best Mode For Carrying Out the Invention Referring to Fig. 1, there is shown a battery assembly 10 consisting of a plurality of six-volt battery modules designated B1-B16, only seven of 0 which are shown, with battery assembly 10 producing a nominal voltage of about 96 volts. The negative terminal of battery module Bl is connected to terminal 12, and the positive terminal of battery module B16 is connected to terminal T16, the intermediate batteries 5 being connected in series by connecting terminals designated T1-T15, only T1-T2 and T13-T15 being shown. Of course, the battery voltage at each of terminals T1-T15 is derived by the number of battery connections below a particular connection, with 6 volts on terminal Tl, 12 volts on terminal T2, and so on to terminal 14, where the entire battery assembly voltage of 96 volts is felt. Two-threshold, or bi-level, switches SW1-SW17 are employed wherein one terminal of each switch is connected to common lead or terminal 16, and the opposite lead of each is connected to one of terminals 12, T1-T16. These switches are identically set to close at a like discrete voltage at their terminals and to open at a slightly higher potential. The first bi-level switch SW1 is coupled between the negative terminal 12 of battery assembly 10 and common terminal 16, and is used as a reference. Ramp voltage generator 18 and current sensing shunt 20 are connected in series between negative terminal 12 and common terminal 16. Ramp voltage generator 18 generates a ramp voltage waveform 22 which commences at zero volts and rises to about 100 volts, approximately 4 volts above the nominal voltage of 96 volts of battery assembly 10. Current shunt 20 provides a voltage representative of current flow through switches SW1-SW17. The ramp voltage from ramp voltage generator 18 is provided to the horizontal input of an oscilloscope 28, with the voltage output from current sensing shunt 20 provided to the vertical input of oscilloscope 28. As the ramp voltage rises on terminal 16, it sequentially rises above the voltage appearing at each terminal T1-T15 and finally just above that on terminal T16, sequentially closing and then opening each of switches SW1-SW17, generating a series of current pulses. The ramp voltage is also applied as an X axis or horizontal sweep voltage tc oscilloscope 28, and the voltage output of current measuring shunt 20 is connected to the Y or vertical axis input of oscilloscope 28. Fig. 2 shows a schematic circuit diagram of one of the switches which is generally labelled a bi-level switch SW (Fig. 1). Switch SW is voltage responsive as described across its terminals to close and pass current when its right terminal is more positive than its left by about 2 volts and to open and block current flow when this voltage difference rises to approximately 2.5 volts. Thus, as the bi-level switches are sequentially opened and closed by the rising ramp voltage, a waveform appears on oscilloscope 28 comprising a series of current peaks, the first peak PI representative of a current pulse through switch SW1, peak P2 representative of current flow through switch SW2, and so forth to peak 17. In the instance where discrete battery cells each contribute a like potential to the total potential, in this example, six volts, each peak will be slightly higher than a preceding peak, with the peaks approximately equally spaced as shown in Fig. 3, the spacing between the peaks corresponding to the difference of potential between discrete battery cells. In the instance where a battery is in marginal condition and is contributing a lower voltage, the particular switch SW associated with the marginal battery closes at a lower potential, displacing the current peak for that battery to the left, as shown by peak P5, conveniently identifying marginal battery B4 for replacement. The correlation between a displaced current pulse and a marginal battery cell may be made by direct observation of an oscilloscope, or in a computerized system, by software disposed for directly indicating the marginal battery. Examining now one of switches SW, illustrated in Fig. 2, the operative current path therethrough for generating one of the current peaks shown in Fig. 3 is through zener diode 30, N-channel, enhancement mode field effect transistor (FET) 32, N-channel, enhancement mode FET 33, and current limiting resistor 34, with these components generally coupled in series to provide a limited current flow of about 10 milliamps through switch SW. FETs 32 and 33 are selected to conduct when the gate terminals thereof are more positive than the drain terminals by about 1.5 volts. Two FETs are used here due to the selection of FETs used in this circuit, which FETs have a slight unidirectional leakage current from source to drain when biased "off." Thus, FET 32, positioned drain-to-source with respect to FET 33, blocks this leakage current and prevents the leakage current from affecting voltage measurements. However, it is possible that FET 32 may be omitted with selection of a different FET for FET 33. The cathode of zener diode 30, which is selected to conduct at about 2.0 volts, is connected to terminal 16 and receives the ramp voltage, with the anode of diode 30 coupled to the source terminal S of FET 32. The drain terminal D of FET 32 is coupled to the drain terminal D of FET 33, in turn having its source terminal S coupled via current limiting resistor 34 to the left-hand terminal of switch SW, which receives a potential from bank 10 determined by the number of battery connections below it. Gate G of FET 33 is coupled as shown via high impedence resistors 40 and 41 of filter circuit 38 to terminal 16 and to the collector of NPN transistor 35. The gate terminal G of FET 32 is coupled directly to terminal 16. Thus, FET 33 is biased "on," with transistor 35 in the "off" state, when the ramp voltage applied via resistors 40 and 41 to gate G of FET 33 rises to about 1.5 volts above the battery voltage applied to the drain of FET 33. Likewise, as the ramp voltage rises about 1.5 volts above the battery potential, FET 32 is also biased "on" by virtue of the battery potential being felt at drain D thereof via resistors 34, 36 and 37 and gate G being coupled directly to the rising ramp voltage applied to terminal 16. As the rising ramp voltage reaches about 2.0 volts, zener diode 30 conducts, permitting current flow through diode 30 and FETs 32 and 33. Thus, in contrast to applicant's prior application, the FETs are biased "on" prior to conduction of diode 30, meaning that any variation in the voltage potential at which the FETs are biased "on" is not passed to current sensing shunt 20 and oscilloscope 29. Further, since diode 30 is a very temperature stable device, temperature differences that may be present between discrete switches SW in a battery bank have no effect upon the two-volt threshold of these switches, allowing reliable voltage and current measurements of each battery cell to be taken. Control of the FETs is effected by a voltage sensing circuit including transistor 35 and resistors 34, 36 and 37, with transistor 35 having an emitter coupled to the left-hand terminal of switch SW, a collector coupled through a filter circuit 38 comprised of high impedence resistors 40, 41 and capacitor 42 to terminal 18 and to the gate input G of FET .33, and a base coupled via resistor 36 to the source terminal S of FET 33 and via resistor 37 to the drain terminal D of FETs 32 and 33. Resistors 34 and 36 form a voltage divider network that proportions the voltage drop across resistor 34 such that about 700 millivolts is applied to the base of transistor 35 when the ramp voltage rises to about 2.5 volts above the battery voltage. Coupled as such, increasing current flow through FETS 32 and 33 due to increasing ramp voltage causes an increasing voltage drop across resistor 34, with this voltage drop proportioned by resistor 36 and applied to the base of transistor 35 via resistor 36. When the voltage applied to the base reaches about 700 millivolts, corresponding to a ramp voltage difference between the battery voltage of about 2.5 volts, transistor 35 is biased "on," with the result that the slightly higher ramp voltage is shunted to the battery potential, equalizing the potential between drain D and gate G of FET 33, biasing FET 33 "off" and blocking further current flow through bi-level switch SW. After transistor 35 is biased "on," it is latched "on" by a small current flow through resistor 37 and resistor 34, which form a second voltage divider network that proportions a 2.5- volt difference between the ramp voltage and the battery voltage to apply about 700 millivolts to the base of transistor 35. This in turn keeps FET 33 off, blocking current flow through switch SW. When the ramp voltage reaches its peak and falls back to about 0 volts, the voltage applied to the base of transistor 35 disappears and transistor 35 reverts back to an "off" state, decoupling gate G from drain D of FET 33 in preparation for the next ramp cycle. A second zener diode 39, selected to conduct at about 10 volts, is coupled between the gate G and source S terminals of FET 33, and serves to protect FET 33 from an overvoltage condition between source and drain terminals occurring when the ramp voltage falls to zero volts. Filter circuit 38 functions to block noise, such as switching noise from charging equipment, when transistor 35 is switched "on." Initially, the operation of switch SW1 (Fig. 1) will be considered, with ramp generator 18 just starting its rise from zero voltage. When the ramp voltage applied to terminal 16 rises to just above approximately 7.5 volts, 1.5 volts above the battery voltage felt at the left-hand terminal of switch SW1, FETs 32 and 33 are biased "on" as described. Further increase of the ramp voltage to about 8.0 volts causes diode 30 to conduct, allowing current to flow through FETS 32 and 33, diode 30 and through resistor 34, generating the leading edge of first peak PI of Fig. 3. As the ramp voltage continues to increase to about 8.5 volts, 2.5 volts above the battery voltage, the voltage drop across resistor 34 increases directly with the ramp voltage to apply an increasing voltage to the base of transistor 35, lowering the resistance of transistor 35 as the ramp voltage increases and shutting "off" FET 33, generating the falling edge of peak PI and latching transistor 35 "on." At about 700 millivolts, transistor 35 is saturated, which equalizes the ramp potential applied to gate G of FET 33 as described, biasing FET 33 completely "off" and blocking current flow through bi-level switch SW for the remainder of the ramp cycle. During the conductive period of switch SW1, there will be no current flow through switches SW2-SW17 as diode 30 of these switches will be blocked by virtue of the battery voltages on terminals T1-T16 being higher than the voltage on common terminal or lead 16. After switch SW1 opens, and as the ramp voltage continues to rise, the switching action just described for SW1 will sequentially repeat in the balance of the switches, that is, switches SW2-SW17, giving rise to the succeeding current pulses shown in Fig. 3. Significantly, if one reads the voltage from Fig. 3 from succeeding on otherwise identical points on the current pulse waveforms, the voltage difference will be indicative of the voltage of the particular battery module between which succeeding switches have been operated to create the current pulses. It is to be noted that the base point for the current pulses gradually rises on the display of Fig. 3, this occurring by virtue of there being increased current flow with increasing ramp voltage as more of diodes 30 of the switches conduct. Where module voltages are simply determined by visual examination of the display, such as shown in Fig. 3, this poses no point of error; whereas, where battery module voltage is determined from amplitude points on the trailing or leading edges of the pulses, appropriate compensation would be provided to comparators making such an examination either by hardware or via software. _ . From the foregoing, it is to be appreciated that applicant's system provides an improved, temperature compensated means of battery module analysis . No contact-type swi tching systems are needed , and wire connections from the environs of the batteries to any remotely located measurement system need only total two wires.

Claims: Claims 1. In combination: a pair of first and second terminals; a battery assembly connected between said terminals comprising a plurality of serially arranged battery modules, each module having a pair of plus and minus battery terminals; a plurality of intermediate terminals, each interconnecting a plus terminal of one said battery module to the negative terminal of an adjacent said battery module; a common electrical lead; ramp voltage generating means for generating a D.C. ramp voltage extending from a voltage below a voltage produced by a discrete one of said battery modules to a voltage slightly exceeding a voltage of said battery assembly, said ramp voltage being connected between said first terminal and said common electrical lead and wherein said battery voltages at said second terminal with respect to said first terminal and said ramp voltage at said common lead with respect to said first terminal are of like polarity; a plurality of voltage responsive switching means, each connected between said common electrical lead and one said terminal for effecting a closed circuit responsive to a first level voltage and an open circuit responsive to a voltage of increased level; and current sensing means in circuit with said common lead and ramp generating means, for providing an output responsive to current flow during discrete closed circuit conditions of each said switching means, whereby voltage between successive current flows through said switching means provides a determination of condition of each said battery module. 2. A combination as set forth in claim 1 including indica means responsive to said ramp generating means and said current sensing means, for indicating current flow verses ramp voltage, whereby a discrete difference in voltage between indications of current flow is indicative of the discrete voltage of a discrete said battery module. 3. A combination as set forth in claim 2 wherein said indicating means comprises display means for displaying an X-Y coordinate presentation, wherein voltage is one of said coordinates and current is the other. 4. A combination as set forth in claim 3 wherein said indicating means comprises an oscilloscope. 5. A combination as set forth in claim 1 wherein said switching means comprises: at least one electronic switch having a control input coupled to said common electrical lead; a voltage responsive switch disposed for closing at a predetermined ramp voltage and coupled between said first electronic switch and said common electrical lead; and a voltage sensing circuit coupled to said control input and disposed for sensing, a selected, higher ramp voltage than said predetermined ramp voltage and providing a disabling signal to said control input, opening said electronic switch at said selected, higher ramp voltage, whereby said electronic switch is closed at a potential lower than said predetermined ramp voltage, and conduction is enabled through said electronic switch upon closing of said voltage responsive switch at said predetermined ramp voltage, and said conduction is interrupted by opening of said electronic switch upon said ramp voltage reaching said selected, higher ramp voltage. 6. A combination as set forth in claim 5 wherein said electronic switch is a field effect transistor and said voltage responsive switch is a zener diode, the field effect transistor and zener diode being coupled in series between said common lead and one of said terminals. 7. A combination as set forth in claim 6 wherein said voltage sensing circuit comprises: a transistor; and a transistor input circuit consisting of a voltage divider comprising first and second impedance elements wherein said first impedance element is connected across an input of said transistor, and said second impedence element is connected between said FET and said first terminal, and wherein switched terminals of said transistor are coupled between said first terminal and said second control input, whereby said voltage divider provides about 700 millivolts to said input of said transistor when said ramp voltage rises to about 2.5 volts above battery potential applied to said first terminal, biasing said transistor "on" and applying said battery potential to said control input, biasing "off" said FET and blocking current flow through said voltage responsive switching means. 8. A combination as set forth in claim 7 comprising a third resistance element coupled between said input of said transistor and said zener diode, for applying at least 700 millivolts of said ramp voltage to said input of said transistor, latching said transistor "on" and maintaining an "off" state of said FET.

Inventors: NOWAK DIETER K, NOWAK, DIETER, K.
Applicants: NOWAK DIETER K, NOWAK, DIETER, K.
Application year: 1991
Main classification: G01N27
IPC codes: G01R31