Circuit for generating an address of a random access memory

Abstract: A write address (WAD) and a read address (RAD) are generated by use of a pointer register (1) and a single register set (2) common to the write and read addresses. The read address is obtained by an addition in an adder (4) or by a subtraction (Fig.7) of a pointer value and a value selected from offset values of the register set, and the write address is obtained by adding one to the read address or subtracting one therefrom.

Description: BACKGROUND OF THE INVENTION The present invention relates to a circuit for generating an address of a random access memory (abbreviated RAM hereinafter), and more particularly to, a circuit for designating write and read addresses of a RAM which functions as a delay circuit in an audio surrounding system. Recent audio surrounding systems which delay digital audio data often use a RAM as a delay circuit, in which the audio data is written at a write address into the RAM, and it is read at a read address therefrom after a predetermined delay time. The write and read addresses are designated by an address generation circuit. One type of a conventional address generation circuit comprises a pointer register, a write offset register set, and a read offset register set. The pointer register indicates a pointer value of each write and read address. The write and read offset register sets respectively include a plurality of offset registers each having a different offset value. The offset value indicates an offset from the pointer. Therefore, the write and read addresses are designated to provide a predetermined delay time, for instance, by the addition of the pointer value and the offset values. Another type of a conventional address generation circuit modifies the former one, so that the write and read offset values are obtained from one common offset register set. For this common-use purpose, this address generation circuit further comprises a pointer register controller which changes a pointer value of the pointer register dependent on a state of a write and read control signal. Still another type of a conventional address generation circuit includes a RAM which is divided into a plurality of storage regions each having a different delay amount. Each item of data is stored in a corresponding storage region based on the required delayed amount. However, the above conventional address generation circuits have the following disadvantages: 1. In the first conventional one, the construction thereof becomes complicated, since this address generation circuit includes two offset register sets each having a plurality of offset registers for different offset values; 2. In the second conventional one, the construction thereof and a control system thereof become complicated due to the inclusion of the pointer register controller; 3. In the third conventional one, it is difficult to effectively utilize all the storage regions, when a required delay time is small as compared to a delay time determined by an address length of a divided storage region. SUMMARY OF THE INVENTION The present invention provides, in a first aspect, a circuit for generating an address of a RAM, comprising: a pointer register for storing a predetermined pointer value; a set of registers for storing offset values, one of the registers being sequentially selected to provide one of the offset values in a predetermined order; and means for calculating write and read addresses by receiving the pointer value and the selected offset value; wherein the calculating means provides a read address in an adding calculation of the pointer value and the selected offset value, and a write address in an adding calculation of the pointer value, the selected offset value and one; and wherein the pointer value is decremented after each cycle of the read and write address generation through the set of offset value registers. The present invention provides, in a second aspect, a circuit for generating an address of a RAM, comprising: a pointer register for storing a predetermined pointer value; a set of registers for storing offset values, one of the registers being sequentially selected to provide one of the offset values in a predetermined order; and means for calculating write and read addresses by receiving the pointer value and the selected offset value; wherein the calculating means provides a read address in a subtracting calculation of the selected offset value from the pointer value, and a write address in a subtracting calculation of the selected offset value and one from the pointer value; and wherein the pointer value is incremented after each cycle of the read and write address generation through the set of offset value registers. Thus, the present invention may advantageously provide a novel and useful circuit fcr generating an address of a RAM in which the disadvantages of the prior art described above are eliminated. The present invention may also advantageously provide a circuit for generating an address of a RAM having a simple construction, requiring a simple control system, and providing an effective use of the RAM. BRIEF DESCRIPTION OF THE DRAWINGS Other objects and further features of the present invention will become apparent from the following description when read in conjunction with the accompanying drawings, wherein: Figs, 1A and 1B are block diagrams showing surrounding circuits, to which a circuit for generating an address of a RAM functioning as a delay circuit is applied; Fig. 2 is a block diagram showing one type of a conventional circuit for generating an address of a RAM; Fig. 3 is an explanatory diagram showing an address map of the RAM in Fig. 2; Fig. 4 is a block diagram showing another type of a conventional circuit for generating an address of a RAM; Fig. 5 is a block diagram showing a circuit for generating an address of a RAM in a first preferred embodiment according to the invention; Fig. 6 is an explanatory diagram showing an address map of the RAM in Fig. 5; Fig. 7 is a block diagram showing a circuit for generating an address of a RAM in a second preferred embodiment according to the invention; and Fig. 8 is an explanatory diagram showing an address map of the RAM in Fig. 8. DESCRIPTION OF THE PREFERRED EMBODIMENTS Before explaining the preferred embodiments of the present invention, a detailed description will now be given of several conventional address generation circuits with reference to Figs. 1 to 4. Figs. 1A and 1B respectively show surrounding circuits which achieve the surrounding function. Numerals 100 A to 100 R denote coefficient multipliers, numerals 200 A to 200 N denote delay circuits, numerals 300 A to 300 P denote adders, and letters DT 1 and DT 0 denote input and output audio data, respectively. The surrounding circuits achieve audio surrounding systems which surround a predetermined point with audio sound. For this purpose, the surrounding circuits utilize the reflection and the delay of audio sound. The surrounding circuit shown in Fig. 1A includes a plurality of feedback circuits, so that the audio sound can be reflected more than twice before it reaches the predetermined point. As a result, a reverberation characteristic is obtained in this circuit. On the other hand, the surrounding circuit shown in Fig. 1B includes no feedback circuits, so that the audio sound is reflected only once before it reaches the predetermined point. Both surrounding circuits include a plurality of delay circuits which delay the audio data which are processed to provide the audio sound. Each delay amount of a corresponding delay circuit is determined by taking the timing of the reflecting of the audio sound into consideration. The delay circuit often comprises a RAM, as mentioned above. Fig. 2 shows a block diagram of the aforementioned first conventional address generation circuit. This address generation circuit comprises a pointer register 1, a write offset register set 7, a read offset register set 8, a multiplexer 3, and an adder 4. The pointer register 1, and the write and read offset register sets 7 and 8 are coupled to a bus 5. The pointer register 1 stores a pointer value which is transferred through the bus 5 from a control unit (not shown) and may be renewed by write and read addresses to be outputted from the adder 4. The write and read offset register sets 7 and 8 respectively have a plurality of offset registers having different offset values corresponding to the required delay amount. The multiplexer 3 selects a register of the write and read offset register sets 7 and 8, respectively, based on a read/ write (abbreviated RD/ WR hereinafter) control signal. The adder 4, coupled to the pointer register 1 and the multiplexer 3, adds the output of the pointer register 1 to that of the multiplexer 3 to generate a write or read address. In operation, it is assumed that the pointer value and the offset value have been already set by the control unit. When the WR control signal (RD/ WR =0) is supplied to the multiplexer 3, the address generation circuit generates the write address. That is, one of the offset registers in the write offset register set 7 is selected to provide one of offset values A, B, C and D stored therein through the multiplexer 3 to the adder 4. The adder 4 adds the selected offset value to the pointer value from the pointer register 1 so as to generate the write address WAD. On the other hand, when the RD control signal (RD/ WR =1) is supplied to the multiplexer 3, the address generation circuit generates the read address. That is, one of the offset registers in the read offset register set 8 is selected to provide one of offset values A, B, C and D stored therein. The adder 4 adds the selected offset value to the pointer value so as to generate the read address RAD. The output of the adder 4 may be fed back to the pointer register 1, so that the pointer value of the pointer register 1 is renewed after the write and/or read addresses are generated. Consequently, an address map representing the write and read addresses WADn and RADn (n=0,1,2,...) is formed as shown in Fig. 3, wherein Dn (n=0,1,2,...) respectively denotes the delay amounts. As shown in Fig. 3, audio data An, Bn, Cn and Dn (n=0,1,2,...) are stored in a RAM 400. For instance, the audio data A 0 which was written into the RAM 400 at an (n+1) preceding time is read therefrom at the designated read address RAD0 after the delay time D 0 equal to the (n+1) write and read clock pulse duration which corresponds to the difference between the write and read addresses WAD0 and RAD0. The aforementioned second conventional address generation circuit, as shown in Fig. 4, comprises a pointer register 1, an offset register set 2, an adder 4, a bus 5, and a pointer register controller 9. As mentioned before, the second conventional address generation circuit differs from the first conventional one as regards the offset register set 2 and the pointer register 9. That is, this address generation circuit combines the write and read offset register sets 7 and 8 shown in Fig. 2 into one common offset register set 2. Because of this structure, the multiplexer 3 shown in Fig. 2 is omitted. Instead, the address generation circuit further comprises the pointer register controller 9. The pointer register controller 9 controls the pointer register 1 to provide one value selected from pointer values corresponding to write and read addresses. This address generation circuit can also form the address map shown in Fig. 3. Next, a description will be given of a circuit for generating an address of a RAM in the first preferred embodiment according to the present invention. This address generation circuit comprises, as shown in Fig. 5, a pointer register 1, an offset register set 2, a multiplexer 3, and an adder 4. The multiplexer 3 selects "0" supplied from a zero generator (not shown), when a pointer register write signal PRW of "1" is supplied thereto, so that a pointer value P is written into the pointer register 1. On the other hand, the multiplexer 3 selects one of offset values A, B, C and D stored in the offset register set 2, when the signal PRW of "0" is supplied thereto. The adder 4 carries out the addition of the value P of the pointer register 1, an output of the multiplexer 3 and "1", when the write control signal WR is supplied thereto, and the addition of the value P of the pointer register 1 and the output of the multiplexer 3, when the read control signal RD is supplied thereto. In operation, the pointer value P is written into the pointer register 1, when the pointer register write signal PRW is "1", so that "0" is selected to be supplied to the adder 4 by the multiplexer 3. As a result, the addition of "P+1" is carried out in the adder 4, when the RD/ WR signal is "0". Thus, the added value is supplied from the adder 4 as a write address WADP, at which audio data An is written into the RAM 400 as shown in Fig. 6. Next, the offset value A is selected to be supplied to the adder 4 by the multiplexer 3, when the PRW signal is changed to be "0". As a result, the read address RAD0 of "P+A" is supplied from the adder 4 as shown in Fig. 6, when the RD/ WR signal is "1". The audio data A 0 which was written at the read address RAD0 into the RAM 40 at an (n+1) preceding time is read therefrom after a delay time D 0 equal to an (n+1) write and read clock pulse duration corresponding to the difference of the addresses WADP and RAD0. Next, the write address WAD0 of "P+A+1" is calculated in the adder 4, when the RD/WR signal is changed back to be "0". Thus, write and read addresses are generated as follows. (1) WRITE CYCLE (RD/ WR = 0) (a) pointer write address WADP = P+1 (b) 0th write address WAD0 = P+A+1 (c) 1st write address WAD1 = P+B+1 (d) 2nd write address WAD2 = P+C+1 (e) 3rd write address WAD3 = P+D+1 (2) READ CYCLE (RD/ WR = 1) (a) 0th read address RAD0 = P+A (b) 1st read address RAD1 = P+B (c) 2nd read address RAD2 = P+C (d) 3rd read address RAD3 = P+D After each cycle of the write and read address generation, a pointer value of the pointer register 1 is decremented by one. As apparent from the above, and from the illustration in Fig. 6, delay times D 0 , D 1 , D 2 and D 4 are obtained for audio data A 0 , B 0 , C 0 and D 0 which are read at the read addresses RAD0, RAD1, RAD2 and RAD3 from the RAM 400. In addition, each write address WADn (n=0,1,2,...) is obtained by the addition of one to each preceding read address RADn (n=0,1,2,...) by use of a single common offset register set 2. Consequently, the utilizing efficiency of the RAM 400 is much improved, and the software by which an address generation operation is controlled is simplified. Fig. 7 shows a circuit for generating an address of a RAM in the second preferred embodiment according to the invention. This address generation circuit comprises a pointer register 1 for storing a pointer value, an offset register set 2 having a plurality of registers for storing offset values A, B, C and D, and a subtracter 6 for subtracting one of the offset values A, B, C and D from the pointer value to provide a read address RAD, and for subtracting one of the offset values A, B, C and D and "1" from the pointer value to provide a write address WAD. The pointer register 1 and the offset register set 2 are connected to a bus 5. In operation, delay times D 0 , D 1 , D 2 , ..... are obtained, when audio data A 0 , B 0 , C 0 , ..... are read from the RAM 400 at addresses RAD 1 , RAD 2 , RAD 3 ..... thereof. In the first and second preferred embodiments, the offset register set 2 may be replaced by a RAM storing offset values. Although the invention has been described with respect to specific embodiment for complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modification and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.

Claims: A circuit for generating an address of a RAM, comprising: a pointer register (1) for storing a predetermined pointer value (P); and a set of registers (2) for storing offset values (A,B,C,D), one of the registers being sequentially selected to provide one of the offset values in a predetermined order; characterised by means (4) for calculating write and read addresses (WAD, RAD) by receiving the pointer value and selected offset value; wherein the calculating means provides a read address by adding the pointer value and the selected offset value, and a write address by adding the pointer value, the selected offset value and one; and wherein the pointer value is decremented after each cycle of the read and write address generation through the set of offset value registers. A circuit for generating an address of a RAM, according to claim 1, further comprising: means for generating zero; and means (3) for selecting a value from the zero and the selected offset value; wherein the selecting means selects the zero, when the predetermined pointer value of the pointer register is decremented. A circuit for generating an address of a RAM, according to claim 2, wherein: the pointer register is decremented when a pointer write address (WADP) is generated. A circuit for generating an address of a RAM, according to any preceding claim, in which the pointer value is decremented by one after each cycle of the read and write address generation through the set of offset value registers. A circuit for generating an address of a RAM, comprising: a pointer register (1) for storing a predetermined pointer value (P); and a set of registers (2) for storing offset values (A,B,C,D), one of the registers being sequentially selected to provide one of the offset values in a predetermined order; characterised by means (6) for calculating write and read addresses (WAD, RAD) by receiving the pointer value and the selected offset value; wherein the calculating means provides a read address by subtracting the selected offset value from the pointer value, and a write address by subtracting the selected offset value and one from the pointer value; and wherein the pointer value is incremented after each cycle of the read and write address generation through the set of offset value registers. A circuit for generating an address of a RAM, according to claim 5, in which the pointer value is incremented by one after each cycle of the read and write address generation through the set of offset value registers.

Inventors: YAZAWA AKIRA, YAZAWA, AKIRA, YAZAWA, AKIRA, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: G06F5
IPC codes: G11C8, G06F12, G06F5, G10K15