Image processing apparatus

Abstract: An image processing apparatus having: memory means for storing encoded image data; converting means for interpreting command data so as to convert it into image data; decoding means for decoding said encoded image data stored in the memory means; synthesizing means for synthesizing the image data converted by the converting means and the image data decoded by the decoding means; and encoding means for encoding the image data synthesized by the synthesizing means.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to an image processing method and apparatus for compressing image data. Related Background Art Hitherto, an image recording apparatus, for example, a thermal printer, an ink jet printer and a laser beam printer, has been used as a terminal of the recording system, that is, a white/black printer having a bit map memory. However, the image recording apparatus has been widely used as an apparatus for precisely recording a full color image with the recent trends of enlargement of the capacity of the semiconductor memory, development of excellent function LSI and advancement of the computer technology. On the other hand, there is the requirement for fetching natural color image data into a computer so as to subject it to a variety of processes and perform picture communication. As an encoding method therefor, there has been a variable length encoding method called the "ADCT" (Adaptive Discrete Cosine Transform) method as disclosed on p.p 398 to 407, Vol. 18, the Journal of the Picture Electronics Society. In a case where an image memory arranged to act in accordance with the ADCT method is employed in the image recording apparatus, the memory capacity required to hold a full color natural image can be reduced to 1/10 to 1/20 of the capacity required to hold it as ordinary source data (non-compressed data). Therefore, a satisfactory effect can be obtained because the overall cost of the recording apparatus can be significantly reduced. On the other hand, in a case where the same is used as a recording apparatus connected to an ordinary computer, it is usual for a standardized PDL (Page Description Language) to beemployed and data compatibility to be established between different recording apparatuses. The reason for the above-described arrangement is that a problem arises in that a specific computer can only be connected to a specific printer by using a common language, which establishes compatibility between the printer and the computer the specifications of which are different depending upon their manufacturers. An example of a language of this type is known as Post Script. In a case where a PDL is used, the following problems arise because the PDL has been developed on the basis of a concept of overwriting by overwriting new data on base data written previously): Additionally (1) A block among the 8 × 8 blocks image is synthesized must be updated to novel code data. (2) Since the variable length encoding method is employed to compress data, the address coincidence cannot be made in a case where another image data item is superposed on a portion in which the base image is present. (3) The overall code length of synthesized novel image data can be changed by the image quality. Therefore, it has been considered that the PDL cannot be used on the compression memory. On the other hand, the page printer has a frame buffer for one page and a page description language interpreter (hereinafter called an "interpreter") develops, on the frame buffer, a code described in a page description language (hereinafter called a "PDL") processed by an application program loaded in the host computer. However the fact that the frame buffer for one page is provided in the apparatus causes a problem in that hardware is enlarged excessively (15 Mbit in a case of 400 dpi in an A4 sheet where 1 bit/pixel). This will cause a critical problem when color data is processed. For example, when a full color (24 bits/pixel) image, in which each of red, green and blue is imaged by 8 bit/pixels, is formed, an excessively large memory capacity of 24 times the above-described capacity is required. A concern of the present invention is to overcome the above-described problems. European Patent Specification No EP-A-0,235,456 discloses image processing apparatus in which original image data is compressed and stored, and the stored data edited. United States Patent specification No 4791680 discloses an image data converter in which input data is compression encoded in a plurality of blocks which can subsequently be scaled. In accordance with the present invention there is provided image processing apparatus as set out in claims 1 and 6. An embodiment of the present invention provides a method of efficiently compressing image data. Other features and advantages of the invention will appear more fully from the following description which is given by way of example and with reference to the accompanying drawings, in which : Figs. 1A and 1B respectively are block diagrams which illustrate an example of an image processing apparatus Fig. 2 is a structural view which illustrates a synthesizer; Fig. 3 is a structural view which illustrates an address controller disposed in the synthesizer; Fig. 4 illustrates a data region which illustrates each block raster on a compression memory; Fig. 5 illustrates data held on the compression memory; Fig. 6 is a structural view which illustrates the address controller for a compression memory; Fig. 7 is a block diagram which illustrates a second embodiment of the present invention; Fig. 8 is a block diagram which illustrates a third embodiment of the present invention; Fig. 9 illustrates a data region which illustrates each block raster on a compression memory; Fig. 10 illustrates data held on the compression memory; Fig. 11 is a structural view which illustrates the address controller for the compression memory; Fig. 12 is a structural view which illustrates a blank buffer region administrative circuit; Fig. 13 is a structural view which illustrates a flag buffer; Fig. 14 is a structural view which illustrates a sorter; Fig. 15 is a structural view which illustrates a flag buffer updating circuit: Fig. 16 is a structural view which illustrates an expansion block address buffer; Fig. 17 is a block diagram which illustrates another example of an image processing apparatus; Fig. 18 is a block diagram which illustrates a further example of an image processing apparatus of the present invention; Fig. 19 is a block diagram which illustrates a still further example of an image processing apparatus; Fig. 20 illustrates an example of an encoding method; Fig. 21 illustrates a quantization matrix; Fig. 22 illustrates a method of zigzag scanning; Fig. 23 illustrates a predictive method between blocks of DC coefficient; Figs. 24 to 29 illustrate Huffman code; Fig. 30 is a flow chart which illustrates a process of adding a marker code; Fig. 31 illustrates a data transfer apparatus according to present invention; Figs. 32 and 33 illustrate a print image; Fig. 34 illustrates a table; Fig. 35 is a flow chart which illustrates a flow of the image processing operation; Fig. 36 is a block diagram which illustrates the structure of yet another example of an image processing apparatus; Fig. 37 is a flow chart of a processing sequence of the PDL interpreter shown in Fig. 36; Fig. 38 is a flow chart of a processing sequence of the PDL interpreter shown in Fig. 1; Fig. 39 illustrates a state where an image region for one page is sectioned into a plurality of small regions Fig. 40 illustrates the contents of a file in the command buffer shown in Fig. 36; Fig. 41 illustrates a page-described developed image; Fig. 42 illustrates a page-described developed image; Fig. 43 illustrates a page-described developed image; Fig. 44 illustrates page-described contents Fig. 45 illustrates page-described contents Fig. 46 illustrates the origin of the coordinate of an image region; Fig. 47 illustrates the contents of an exemplary process of image processing; Fig. 48 is a block diagram which illustrates the structure of a circuit of yet another example of image processing apparatus. According to an example to be described later, the inner sace of the compression memory is sectioned into fixed-length blocks which are sufficiently long in comparison to the average code length for the block raster. Then, each of the block raster is subjected to the reproduction, the changing and the re-coding processes so that the PDL can easily be used on the compression memory. Fig. 1A typically illustrates the characteristics of an image processing apparatus where reference numeral 1 represents a host computer for outputting a command column described in a PDL. Reference numeral 2 represents an interpreter (hereinafter called a "PDL interpreter) for receiving the command column output from the host computer 1 so as to interpret and execute it. Reference numeral 3 represents a synthesizer for synthesizing the base data and image data generated by the PDL interpreter 2. Reference numeral 4 represents a compressor for compressing data in accordance with the ADCT method. Reference numeral 5 represents a compression data memory which is sectioned into blocks, each of which has a sufficient memory quantity, at the time of usage. Reference numeral 6 represents a decoder and 7 represents a multiplexer for switching over the output from the decoder 6 to the synthesizer 3 or an image formation portion of a recording apparatus (omitted from illustration). Reference numeral 8 represents an address controller for a compression memory for controlling read/write of the compressed data. When the PDL interpreter 2 receives the postscript PDL command from the host computer 1, it discriminates the image portion to be changed in accordance with the above-described command so as to control the address controller 8 and the decoder 6 to sequentially read out block raster data including the above-described portion from the compression memory 5 so as to decode and output it. Simultaneously, the PDL interpreter 2 controls the multiplexer 7 so as to cause data decoded by the decoder 6 to be transmitted to the synthesizer 3. Furthermore, the PDL interpreter 2 controls the synthesizer 3 in such a manner that the synthesizer 3 receives decoded data transmitted from the decoder 6 to store it in the buffer. The PDL interpreter 2 overwrites novel data, which has been generated in accordance with the above-described command, in the region which corresponds to the position of the pixel in the block raster which has fetched the decoded data. After data corresponding to the block raster region has been written, the PDL interpreter 2 controls the synthesizer 3, the compressor 4 and the address controller 8 so that the block raster region is again compressed by the compressor 4 and it is re-stored in the subject position in the compression memory 5. The above-described sequence is repeated for all of the block rasters. Fig. 1B illustrates the structure of the overall system including the interface portion shown in Fig. 1A. Referring to Fig. 1B, reference numeral 1 represents a host computer, 201 represents an interface portion shown in Fig. 1A and 202 represents an output controller for controlling the output signal. Reference numeral 203 represents a display for displaying the output image and 204 represents a transmitter for transmitting the output image through, for example, a public line or a local area network. Reference numeral 205 represents a laser beam printer for forming a latent image by applying laser beams to the surface of a photosensitive member so as to form a visible image from the latent image. Reference numeral 206 represents an operation unit for setting the area to which the output so that an image desired by an operator is transmitted. Fig. 2 illustrates an example of the structure of the synthesizer shown in Fig. 1A. Reference numerals 21, 22 and 23 respectively represent buffers each of which is composed of 8 raster buffers, the raster buffer having a capacity capable of holding decoded data of a quantity for one block raster. Reference numeral 24 represents a selector for individually connecting output data 27 transmitted from the PDL interpreter 2 and signal data 28 decoded by the decoder 6 and supplied via the selector 7 to any one of the 8-line buffers 21, 22 and 23 in response to a signal 29 transmitted by a selector controller 26 controlled by the PDL interpreter 2. Reference numeral 25 represents another selector for selectively transmitting an output from any one of the above-described 8-line buffers 21, 22 and 23. The selector controller 26 transmits/receives the timing, at which the buffers 21 to 23 are switched over, to and from the PDL interpreter 2. That is, when the PDL interpreter 2 issues a command signal to write data in a novel buffer, the selector controller 26 switches over the 8-line buffers 21, 22 and 23 in a sequential order as 21 → 22 → 23 → 21 → ... so as to connect them to a signal line group 27. Simultaneously, it switches over the 8-line buffers in the sequential order as 22 → 23 → 21 → 22 → ... so as to connect them to a signal line group 28. As a result, data serving as the base of the block raster which is overwritten by the PDL interpreter 2 is synthesized so as to be stored. Simultaneously, the selector controller 26 controls the selector 25 to switch over the 8-line buffers in the sequential order 23 → 21 → 22 → 23 → ... so as to transmit data, in which overwriting from the PDL interpreter 2 on the base data has been completed, to an encoder 4. Reference numeral 30 represents an address controller which receives a scanning line synchronous signal (HSYNC) and a pixel synchronous signal (PXCLK) transmitted from the decoder, a data output address transmitted from the PDL interpreter, a scanning line synchronous signal and a pixel synchronous signal transmitted from the encoder. The address controller 30 generates the address in the 8-line buffer from which pixel data is output, the address in the 8-line buffer from which pixel data on which data transmitted from the PDL interpreter is overwritten is output and the address in the 8-line buffer from which pixel data transmitted so as to be encoded to the encoder is output, each of the addresses being decoded by the decoder. The generated addresses are then transmitted to any one of the three 8-line buffers in response to a select signal supplied from the selector controller 26. Fig. 3 illustrates an example of the structure of the address controller 30. Reference numeral 31 represents a counter for counting the scanning synchronous signals (HSYNC) supplied from the decoder. Reference numeral 32 represents a counter for counting the pixel synchronous signals (PXCLK) supplied from the decoder. The counter 32 outputs, as its count, the address which corresponds to the position in the main scanning direction in one scanning line. The counter 32 outputs, as its count, the upper bit of the address of the leading pixel in each scanning line in one raster block. The output from the counter 31 is made to be the upper it, while the output from the counter 32 is used as an address signal of the ensuing lower bit. As a result, a storage address on the 8-line buffer for the output data from the decoder is generated. The counter 32 is set in response to the scanning synchronous signal (HSYNC). Similarly, counters 33 and 34 receive the synchronous signals transmitted from the encoders. The counter 33 counts the scanning synchronous signal (HSYNC) transmitted from the encoder, while the counter 34 counts the pixel synchronous signal (PXCLK) transmitted from the encoder. As a result, similarly to the counters 31 and 32, the storage address on the 8-line buffer for data to be transmitted to the encoder is generated. The selector 35 is a selector for transmitting the addresses generated by the counters 31 and 32 to any one of the line buffers 21, 22 and 23 selected in response to the select signal supplied from the selector controller 26 so that data decoded by the decoder is stored. The selector 36 is a selector for transmitting the addresses generated by the counters 33 and 34 to any one of the 8-line buffers 21, 22 and 23 selected in response to a select signal supplied from the selector controller 26 so that held data is transmitted to the encoder. The selector 36 is also arranged to transmit the address signal supplied from the PDL interpreter to any one of the 8-line buffers 21, 22 and 23 in response to the select signal supplied from the selector controller 26 in order to hold the base data to be overwritten. Thus, data overwritten on the base data is again transferred to the encoder 4 so as to be compressed. Compressed data is transmitted from the encoder 4 to the compression memory 5 so as to be stored. Then, the encoding method according to this example will now be described. Fig. 20 illustrates the overall flow of the processes to be performed in when encoding method using the above example. First, the original image is sectioned into block regions each of which is composed of 8 × 8 pixels. As designated by reference numeral 180, data for each of color components R, G and B of the original image is received so that 64-pixel data block for only red of a certain original square image composed of 8 × 8 pixels, 64-pixel data block for only green of the same, 64-pixel data block for only blue of the same are processed. Then, the 8 × 8 pixel block adjacent to the above-described 8 × 8 pixel square block of the original image is subjected to a process performed in such a manner that red data, green data and blue data are sequentially processed. When the subject block raster has been thus-processed, the process of the ensuing block rasters are sequentially performed in units of 8 × 8 pixel block in a direction form left to right. In a process 181, each of the color components of 8 × 8 is processed in accordance with DCT (Discrete Cosine Transform) by a size of 8 × 8. Then, each value of the results (which can be expressed by a matrix the size of which is 8 × 8) of the above-described process is quantized by a quantization portion 182 in each term of 8 × 8 by a quantization step value 183 (64 fixed-value group which corresponds to the matrix 8 × 8) which has been previously stored in a memory comprising a ROM or a RAM. Although it is preferable that a quantization matrix be the most suitable value with which the encoding efficiency can be obtained for the subject color components, it can be arbitrary established basically. Fig. 21 illustrates an example of the quantization step value according to this example. As shown in Fig. 22, a DCT coefficient 184 obtained after the linear quantization thus-performed is displayed on the coordinate in which horizontal directional position i is rightward arranged from 0 to 7 and vertical directional position j is downward arranged from 0 to 7 so as to display the position of each term on coordinate (i, j). In this case, position (0, 0) denotes the DC component in such a manner that i is in proportion to the horizontal directional spatial frequency and j is in proportion to the vertical directional spatial frequency. Each of the term of the DCT coefficient which has been 8 × 8 quantized is encoded in such a manner that the DC component positioned at (0, 0) and the AC component position at the other position are divided from each other. In a one-dimensional predictive portion 185 performs a one-dimensional prediction between the adjacent blocks of the DC component so that a predictive error is generated. That is, value Deltak which is the result of subtraction of DC component DC (0, 0) k-1 of the forward adjacent block from the DC component DC (0, 0) k of the subject block is made to be the predictive error of the subject block (Delta k = DC(0, 0) k - DC(0, 0) k-1 ). The prediction between the blocks is performed as shown in Fig. 23 in such a manner that each of the color components is subjected to it between the subject block and the forward adjacent block. In a Huffman encoding portion 186, the above-described predictive error is encoded in accordance with the correspondence shown in Fig. 24, the value of code SSSS thus-obtained is Huffman-encoded. The value of SSSS denotes the number of bits required to specify the value in the subject group as well as denotes the above-described group of the predictive error. For example, there is a necessity of two bits to identify the member of a group SSSS = 2 which contains four members -3, -2, 2 and 3. After the value of SSSS has been Huffman-encoded, the additional SSSS bits are subsequently added. The Huffman code must be previously set in 188 so as to make the length of the code, which is frequently generated, to be short enough. The AC component is, as shown in Fig. 22, zigzag-scanned from its low frequency component to the high frequency component in the 8 × 8 coefficient matrix. As shown in Fig. 25, coefficients except for 0 are classified into any one of 15 groups depending upon its value. This identification code is made to be SSSS (an integer selected from 1 to 15). On the other hand, the number of 0 interposed by the coefficient which is other than 0 is made to be NNNN. Since the coefficient matrix is composed of 8 × 8 pixels and thereby includes 63 AC coefficients, code R16 shown in Table 6 is repeatedly generated until the residual number is reduced to 15 or less. As a result, NNNN is arranged to be 15 or less. The codes SSSS and NNNN are, as an alternative to a structure in which they are processed individually, Huffman encoded as shown in Fig. 25 as a pair. The Huffman code thus-obtained must be previously set in 188 so as to make the length of the code of the pair of SSSS and NNNN, which is frequently generated, to be short enough. Code EOB (End of Block) is added to the end portion of the code of the block of each of the color components. Figs. 26 to 29 illustrate an example of a Huffman code table according to this embodiment. Since the signals denoting red, green and blue has a length of 8 bits according to this embodiment, the DCT coefficient does not exceed 10 bits. As a result, it is sufficient for SSSS to correspond to 0 to 10 and therefore SSSS of 12 or more (for DC component) and 11 or more (for AC component) are omitted from the table. Then, the control of the compressor 4 and the compression memory 5 performed by the PDL interpreter 2 will now be described with reference to a flow chart shown in Fig. 22. As a result of the following sequential control, the histeresis information to the forward adjacent position of the image data can be reset. Fig. 22 illustrates the operation of the PDL interpreter 2 for processing image data for a certain small region. The PDL interpreter 2 commences its control operation in step S100 to start the compression of image data of the certain small region. In S110, a restart (RST) marker code is written to a memory position at which compressed data given by the address controller 8 must be stored. The address controller 8 is again set in order to prevent the deviation of the memory address by a degree corresponding to the above-described marker code. In S120, the compressor 4 is then started so as to compress/encode data on the synthesizer 3. In S130, the status of the compressor 4 is supervised through its control register so that the completion of the operation of the compressor 4 is confirmed before the process proceeds to S140. In S140, the operation of the compressor 4 is stopped. In S150, the EOI (End Of Image) marker code is added to the code written on the above-described memory. In S160, the operation of compressing the subject small region is completed. The previous value buffer of the compressor 4 is reset whenever the above-described operation for the small region is completed. On the other hand, the decoder 6 has a function capable of detecting the above-described marker code and is arranged in such a manner that, when it detects the above-described restart (RST) marker code, its register holding the hysteresis before the previous value is reset. As a result, the hysteresis before the previous value of each of the small regions can be reset. The decoder 6 has a function of stopping its operation when it detects the EOI (End Of Image) marker code and to transmit a signal for notifying this fact outside. As a result of the signal transmission, the decoder 6 is capable of notifying the fact that decoding of encoding data for small regions by generating the interruption signal in the PD interpreter. Each of the block rasters is subjected to the above-described process until the compression process has been completed. Fig. 4 illustrates the position at which compressed data corresponding to each of the block rasters is stored in the compression memory. For example, an assumption is made that an image the number of pixels of which is less than 4096 × 4096 and one pixel of three colors R, G and B requires 3 bytes (1 byte/color) is processed. The maximum image has a capacity of 48 MBytes. Another assumption is made that the compression ratio which is realized by the encoder 4 is set to 1/12. Each of the blocks of the block raster is constituted in units of 8 × 8 pixels so as to be compressed. As a result, the image of the maximum size is constituted by 512 × 512 blocks. The image of the maximum size is compressed to a capacity of about 4 MByte, causing the average code length per block raster to be 8 KByte. According to this embodiment, a memory capacity of 4 times the average code length is assumed as a sufficiently large capacity per block raster. As shown in Fig. 4, the compression memory has a compression memory region for each block raster at every 32 KByte. That is, the compression memory is sectioned into blocks each of which has a sufficient capacity with respect to the average code length of each of the block rasters. Fig. 5 illustrates a status of data actually held by the compression memory shown in Fig. 4. The blocks shown in Fig. 5 are the same as the data regions of the block rasters shown in Fig. 4. Furthermore, the compression memory regions for the block rasters are formed at every 4 times the average code length. The diagonal line portions are the regions which store the code for each of the block rasters. Fig. 6 illustrates the structure of the address controller 8 shown in Fig. 1, where reference numeral 61 represents a counter for counting the synchronous signals of the block raster so that the block raster to be selected from the compression memory so as to be compressed is designated by the count value. A value corresponding to the block address to be written by the PDL interpreter 62 is set as the initial value of the counter 61 through a signal line 62. Furthermore, a block raster synchronous signal supplied from the encoder 9 is counted. Reference numeral 64 represents a counter for counting the data transference clock for each byte transmitted from the encoder 9 so as to designate the position in the block raster data at which it is stored by its count value. The counter 64 is reset in response to the raster synchronous signal. Reference numeral 66 represents a counter for counting the block raster synchronous signal similarly to the counter 61. The number of the block raster including the pixel position to be overwritten by the PDL interpreter 62 is set as the initial count. Subsequently, the block raster synchronous signal 67 supplied from the decoder is counter so as to indicate, with the count value, the region of the block raster in the compression memory to be accessed. Reference numeral 68 represents a counter for counting the data transferring clock similarly to the counter 64 in such a manner that the position in the block raster data to be read is indicated with the count value. The counter 68 is reset in response to the raster synchronous signal transmitted from the decoder. The counters 61 and 64 are used in such a manner that the count value of the counter 61 is used as the upper address signal and the count value of the counter 64 is used as the lower address signal before they are combined to each other so as to be used as the write data address of the compression memory. Similarly, the counters 66 and 68 are used in such a manner that the count value of the counter 66 is used as the upper address signal and the count value of the counter 68 is used as the lower address signal before they are combined to each other so as to be used as the read data address from the compression memory. Reference numeral 70 represents a read/write control circuit for receiving the above-described write data address, the read data address, a data transfer clock 65 transmitted from the encoder and a data transfer clock 69 transmitted from the decoder so as to control the reading/writing address and timing to and from the above-described compression memory. The encoder and the decoder can easily be constituted by using, for example, an LSI such as CL550 manufactured by C-Cube, U.S.A. in such a manner that a circuit for adjusting the synchronous signal or the like is added if necessary. The sectioning of the above-described block raster is controlled by using the marker code. By using the marker code, the block rasters are individually encoded/decoded. As for the marker code, there has been disclosed in detail in the above-described organ (published from the Image Electronic Society). The PDL interpreter 2 according to the above-described example is arranged in such a manner that it discriminates the image position to be changed in response to a PDL command supplied from the host computer 1. Furthermore, it performs decoding, rewriting and re-encoding. However, another structure may be employed which is arranged in such a manner that an image buffer 71 and a command buffer 72 are, as shown in Fig. 7, used to temporarily hold the PDL command and data supplied from the host computer by a quantity for a plurality of commands. Then, the position to be changed due to each command is discriminated for every set of commands of a certain number so that rewriting of the same block raster is performed collectively. That is, the rewriting which relates to the decoding → the subject block raster may be performed in the sequential order as execution → re-coding. As described above, by subjecting a certain number of commands to the process after they are temporarily held in the buffer, the required number of decoding and encoding processes can be reduced. Therefore, the degree of deterioration in the image quality due to the above-described processes can be prevented. Furthermore, another effect of shortening the required waiting time due to the execution of the commands made with respect to the host computer can be obtained. As described above, according to the above-described example , the image data is published and processed by using the compression memory. As a result, the overall cost can be significantly reduced in a case where a memory having a data capacity which is sufficiently large to hold actual data is used. Furthermore,the apparatus is arranged in such a manner that compressed data is processed for each block raster and the compression memory is sectioned into blocks each of which has a sufficient capacity with respect to the average code length of the block raster. Therefore, an effect can be obtained in that an image can easily be published and processed by using the compression method of the variable-length-coding type. Although the PS (Post Script) is employed as the PDL another PDL can, of course, be employed. The method of the compression is not limited to ADCT. The other perpendicular transformation encoding method, predictive encoding method, a run length encoding method and the like may be employed. The publishing method is not limited to the overwriting method. As an alternative to this, a calculation by using the previous data and posterior data (for example, a multiplication is performed or the AND or the OR is calculated). That is, a process such as overlaying or modulation may be performed. The output signal decoded can be formed into a hard copy by a laser beam printer, an ink jet printer, a thermal printer or the like as well as displaying it by a display means. As described above, the image can be variously processed by using compressed data. Fig. 8 illustrates another image processing apparatus where reference numeral 1 represents a host computer for outputting a command column described in the PDL. Reference numeral 2 represents an interpreter (hereinafter called a "PDL interpreter) for receiving the command column output from the host computer 1 so as to interpret and execute it. Reference numeral 3 represents a synthesizer for synthesizing the base data and image data novely generated by the PDL interpreter 2. Reference numeral 4 represents a compressor for compressing data in accordance with the ADCT method. Reference numeral 5 represents a compression data memory which is sectioned into blocks, each of which has a sufficient memory quantity, at the time of usage. Reference numeral 6 represents a decoder and 7 represents a multiplexer for switching over the output from the decoder 6 to the synthesizer 3 or an image formation portion of a recording apparatus (omitted from illustration). Reference numeral 8 represents an address controller for a compression memory for controlling read/write of the compressed data. Reference numeral 9 represents a blank buffer region administrative circuit which is used by the address controller for the purpose of controlling the blank area in the compressed memory 5. When the PDL interpreter 2 receives the postscript PDL command from the host computer 1, it discriminates the image portion to be changed in accordance with the above-described command so as to control the address controller 8 and the decoder 6 to sequentially read out data of the block raster including the subject position from the compression memory 5 so as to decode and output it. Simultaneously, the PDL interpreter 2 controls the multiplexer 7 so as to cause data decoded by the decoder 6 to be transmitted to the synthesizer 3. Furthermore, the PDL interpreter 2 controls the synthesizer 3 in such a manner that the synthesizer 3 receives decoded data transmitted from the decoder 6 to store it in the buffer. The PDL interpreter 2 overwrites novel data, which has been generated in accordance with the above-described command, in the region which corresponds to the position of the pixel in the block raster which has fetched the decoded data. After data corresponding to the block raster region has been written, the PDL interpreter 2 controls the synthesizer 3, the compressor 4 and the address controller 8 so that the block raster region is again compressed by the compressor 4 and it is re-stored in the subject position in the compression memory 5. The above-described sequence is repeated for all of the black rasters. Fig. 8 which illustrates the structure of the overall system including the interface portion is the same as Fig. 1B. The structure of the synthesizer 3 and that of the address controller 30 shown in Fig. 8 are the same as those shown in Figs. 2 and 3. Fig. 9 illustrates the position at which compressed data corresponding to each of the block rasters is stored in the compression memory. For example, an assumption is made that an image the number of pixels of which is less than 4096 x 4096 and one pixel requires 3 bytes (1 byte/color) is processed. The maximum image has a capacity of 48 MBytes. Another assumption is made that the compression ratio which is realized by the encoder 4 is set to 1/12. Each of the blocks of the block raster is constituted in units of 8 × 8 pixels so as to be compressed. As a result, the image of the maximum size is constituted by 512 × 512 blocks. The image of the maximum size is compressed to a capacity of about 4 MByte, causing the average code length per block raster to be 8 KByte. According to this embodiment, a memory capacity for each block raster is assumed to be a quantity of data of the average code length. Furthermore, as shown in Fig. 9, the compression memory has a compression memory region for each of the block rasters at every 8 KByte. Fig. 10 illustrates a status of data actually held by the compression memory shown in Fig. 9. The blocks shown in Fig. 10 are the same as the data regions of the block rasters shown in Fig. 9. Furthermore, the compression memory regions for the block rasters are formed at every average code length. The diagonal line portions are the regions which store the code for each of the block rasters. Referring to Fig. 10, the second block raster of the original image, the fourth block raster of the same, the seventh block raster, the tenth block raster,..., the 506th block raster and the 510-th block raster are arranged to have a code quantity which is longer than the average code length. It cannot be stored in a single block raster compression memory region set for each data quantity of the average code length. Therefore, data is stored by using a plurality of regions. In particular, since the seventh block raster cannot be stored in the second region, the third region is used to store it. Fig. 11 illustrates the structure of the address controller and the blank buffer region administrative circuit 9 of the address controller 8 shown in Fig. 8. Referring to Fig. 11, reference numeral 61 represents a counter for counting the synchronous signals of the block raster so that the block raster to be selected from the compression memory so as to be compressed is designated by the count value. A value corresponding to the block address to be written by the PDL interpreter 62 is set as the initial value of the counter 61 through a signal line 62. Furthermore, a block raster synchronous signal 63 supplied from the encoder 4 is counted. Reference numeral 64 represents a counter for counting the data transference clock 65 for the block data transmitted from the encoder 4 so as to designate the position in the block raster data at which it is stored by its count value. The counter 64 is reset in response to the block raster synchronous signal. The counter 64 generates a count up (carry signal) 76 in a case where data cannot be stored in the memory region in the compression memory for the subject block raster so as to reset it. In this case, the blank buffer region administrative circuit 9 shown in Fig. 8 is started in response to the count up signal 76 so that position in the block raster memory region in the compression memory in which the residual data must be subsequently stored is obtained. Reference numeral 66 represents a counter for counting the block raster synchronous signal similarly to the counter 61, in which the number of the first block raster in the block raster including the position of the pixel to be overwritten by the PDL interpreter 62 is set after the first counting has been made. Subsequently, the block raster synchronous signals 67 transmitted from the decoder are counted for the purpose of showing the region of the block raster in the compression memory to be accessed. Reference numeral 68 represents a counter for counting data transference clock similarly to the counter 64 in such a manner that it counts the transference clock transmitted from the decoder for each byte so as to show the position in the block raster data to be read with the count value. The counter 68 is reset in response to the raster synchronous signal transmitted from the decoder. The counter 68 generates the count up (carry) signal 73 so as to reset the counter 68 in a case where all of data items in the block raster cannot be read out even if data is read out in the memory region for the block raster in the compression memory. In this case, the bland buffer administrative circuit 9 shown in Fig. 81 is started in response to the count up signal 73. As a result, the position of the block raster memory on the compression memory from which data is subsequently read is obtained. When the blank buffer region administrative control circuit 9 is started in response to the count up (carry) signal 76 transmitted from the counter 64 for counting the transference clock of the block data, it transmits, to a signal line 80, the address of the extension block raster memory region in the block raster image memory which is being written. Simultaneously, a selection switch signal 74 of a selector 78 and a latch timing signal 75 of a latch 79 are transmitted. The position of the expansion region block raster memory portion transmitted to the signal line 80 is selectively transmitted by the selector 78 at the timing of the signal 74. It is then held by the latch 79 at the timing of the signal 75 so as to be used as the upper address of the address at which the ensuing image data items are stored. Similarly, the blank buffer administrative circuit 9 is started in response to the count up (carry) signal transmitted from the counter 68 for counting the clock data transference clock. As a result, the blank buffer administrative circuit 9 transmits the address of the expansion block raster memory region in the image memory of the block raster, which is being read, to a signal line 81. Simultaneously, it transmits a selection switch signal 87 of a selector 83 and a latch timing signal 88 of a latch 84. The position of the expansion region block raster memory transmitted to the signal line 81 is selectively transmitted by the selector 83 at the timing of the signal 87 so as to be held by the latch 84 at the timing of the signal line 88. As a result, it is used as the upper address for the address of reading the ensuing image data. Fig. 12 illustrates the detailed structure of the image memory blanking buffer region administrative circuit 9. A buffer read/write control circuit 90 transmits a signal 102 to a flag buffer 91 when it receives the signal 76. As shown in Fig. 13, the flag buffer 91 is arranged to be a buffer corresponding to the number of the extension blanking region block rasters. Referring to Fig. 13, it is composed of 512 cells each of which is made by 1 bit. The above-described cells correspond to the 0-th expansion (block raster) region of the image memory shown in Fig. 9 to the 511-th expansion (block raster) region. "1" denotes the fact that the corresponding expansion region is blank, while "0" denotes the fact that the same is being used. The buffer 91 transmits held 512-bit information to a signal 98 composed of 98-0 to 98-511 when it receives the signal 102. A sorter 92 is a 512-input/512-output circuit arranged in such a manner that it receives the signal 98 so as to select a signal line which is the least number from 98-0 to 98-511 which is "1" and transmits the above-described signal as "1" and the others as "0". An example of the structure of the sorter 92 is shown in Fig. 14. An output signal 99 from the sorter 92 is subjected to a process by the encoder 93 in such a manner that the sequential order of the signal line, which is "1", is encoded to a 9-bit binary number so as to be transmitted as a signal 80 of 9 bits. The signal 80 transmitted from the encoder 93 denotes the position of the expansion region by a binary expression method, the signal 80 being fetched into an expansion block address buffer 94. The buffer table 94 is structured as shown in Fig. 16 so as to receive the block address before the expansion which has been received in the form of the signal 86 from 90 as the access position of the buffer table 94 from the signal 101. As a result, the contents of the signal 80 is fetched to the subject position. When the buffer read/write control circuit 90 receives the signal 73, the number of the block, which is being read at this time, is received by the signal 82 so as to transmits the block number as the signal 101 to the expansion block address buffer 94. The expansion block address buffer 98 transmits the contents of the position assigned by the signal 101 to the signal line 81. The signal line 81 transmits the number of the block raster buffer which stores the ensuing data of the block raster which is being read and received by the signal 82. The signal 81 is simultaneously also transmitted to a decoder 96. The decoder 96 transmits, as signals 100-0 to 100-511, the signal 81 expressed by a 9-bit binary number to 512 signal lines 100 in such a manner that only the signals of the number which denotes the 9-bit binary number are transmitted as "1" and the other signals are transmitted as "0". A flag buffer updating circuit 95 transmits signals 98, 99 and 100 so as to make the flag of the position of the expansion block to be used for writing to be "0" and the flag of the position of the expansion block to be read to be "1". As a result, the status where the blank buffer region of the image memory is updated as shown in Fig. 15. The latch 79 and the counter 64 is used as a write data address for writing in the compression memory by combining in such a manner that the output from the latch 79 is made to be the upper address signal and the count value of the counter 64 is made to be the lower address signal. Similarly, the latch 84 and the counter 68 is used as a read data address for reading the compression memory by combining in such a manner that the output from the latch 84 is made to be the upper address signal and the count value of the counter 68 is made to be the lower address signal. The read/write control circuit 70 receives the above-described write data address, read data address, the data transference clock 65 transmitted from the encoder and the data transference clock 69 transmitted from the decoder so as to control the address and timing of reading/writing data to and from the compression memory. The encoder and the decoder can easily be constituted by using, for example, an LSI such as CL550 manufactured by C-Cube, U.S.A. in such a manner that a circuit for adjusting the synchronous signal or the like is added if necessary. The sectioning of the above-described block raster is controlled by using the marker code. By using the marker code, the block rasters are individually encoded/decoded. As for the marker code, there has been disclosed in detail in the above-described organ (published from the Image Electronic Society). According to the above-described examples , the PDL interpreter 2 discriminates the image positions to be sequentially changed in response to the corresponding commands when it receive the PDL command so that the subject position is decoded, rewritten and re-encoded. However, as shown in Fig. 17, the image buffer 71 and the command buffer 72 are employed so as to temporarily hold the PDL command and data supplied from the host computer 1 by a quantity of a plurality of commands. Furthermore, a certain number of commands are collected so as to collectively rewrite the portions in the same block raster after the portions to be changed have been determined in accordance with the corresponding commands. That is, a process of decoding → rewriting of the subject block raster may be performed in such a manner that execution → re-encoding. As described above, by subjecting a certain number of commands to the process after they are temporarily held in the buffer, the required number of decoding and encoding processes can be reduced. Therefore, the degree of deterioration in the image quality due to the above-described processes can be prevented. Furthermore, another effect of shortening the required waiting time due to the execution of the commands made with respect to the host computer can be obtained. As described above, the inner portion of the compression memory is sectioned into the fixed length blocks each of which has a a capacity which is about the average code length of the block raster. The reproduction, changing and re-encoding processes are performed in units of the block raster. Furthermore, the structure according to this example comprises means for detecting whether or not the code length exceeds the above-described fixed block length at the time of the encoding process and means for administrating the blank fixed block in the compression memory. Thus, data of the code of the block raster the code quantity of which exceeds the fixed block length is held over a plurality of fixed length blocks. As a result, the PDL can easily be used in the compression memory. That is, by publishing and operating image data by using the compression memory, the overall cost can be significantly reduced in a case where a memory having a data capacity which is sufficiently large to hold actual data is used. In this presently described apparatus, the inner portion of the compression memory is sectioned into the fixed length blocks each of which has a a capacity which is about the average code length of the block raster. The reproduction, changing and re-encoding processes are performed in units of the block raster. Furthermore, the structure comprises means for detecting whether or not the code length exceeds the above-described fixed block length at the time of the encoding process and means for administrating the blank fixed block in the compression memory. Thus, data of the code of the block raster the code quantity of which exceeds the fixed block length is held over a plurality of fixed length blocks. As a result, an image can easily be published and operated by the compression method of the variable-length encoding system. Although the PS (Post Script) is employed as the PDL, PDLs may of course, be employed. The method of the compression is not limited to the ADCT. The other perpendicular transformation encoding method, predictive encoding method, a run length encoding method and the like may be employed. The publishing method is not limited to the overwriting method. As an alternative to this, a calculation by using the previous data and posterior data (for example, a multiplication is performed or the AND or the OR is calculated). That is, a process such as overlaying or modulation may be performed. The output signal decoded can be formed into a hard copy by a laser beam printer, an ink jet printer, a thermal printer or the like as well as displaying it by a display means. Fig. 18 illustrates another example of image processing apparatus, where reference numeral 1 represents a host computer for outputting a command column described in the PDL. Reference numeral 2 represents an interpreter (hereinafter called a "PDL interpreter) for receiving the command column output from the host computer 1 so as to interpret and execute it. Reference numeral 3 represents a synthesizer for synthesizing the base data and image data novely generated by the PDL interpreter 2. Reference numeral 4 represents a compressor for compressing data in accordance with the ADCT method. Reference numeral 5 represents a compression data memory which is sectioned into blocks, each of which has a sufficient memory quantity, at the time of usage. Reference numeral 6 represents a decoder and 7 represents a multiplexer for switching over the output from the decoder 6 to the synthesizer 3 or a selector 11. Reference numeral -8 represents an address controller for a compression memory for controlling read/write of the compressed data. Reference numeral 9 represents a blank buffer region administrative circuit used when the address controller 8 administrates the blank region in the compression memory 5. Reference numeral 10 represents a memory for storing characters and line drawings. Reference numeral 11 represents a selector for switching over a picture output from the decoder 6 made via the selector 7 and a picture output from the character and line drawing memory 10 to be transmitted to an image formation unit of a recording apparatus (omitted from illustration). Reference numeral 12 represents an address controller for controlling read/write of the character and line drawing memory. When the PDL interpreter 2 receives the postscript PDL command from the host computer 1, it discriminates the image portion to be changed in accordance with the above-described command and whether or not the image to be changed is the character and the line drawing. In a case of the character and the line drawing, the subject portion of the character and line drawing memory 10 is overwritten. In the other cases, when the PDL command is supplied from the computer 1, the PDL interpreter 2 controls the address controller 8 and the decoder 6 so as to discriminate the image portion to be changed in response to the above-described command so as to sequentially read out the block raster data including the above-described portion from the compression memory 5 so as to decode and output the result. Simultaneously, the PDL interpreter 2 controls the multiplexer 7 so as to cause data decoded by the decoder 6 to be transmitted to the synthesizer 3. Furthermore, the PDL interpreter 2 controls the synthesizer 3 in such a manner that the synthesizer 3 receives decoded data transmitted from the decoder 6 to store it in the buffer. The PDL interpreter 2 overwrites novel data, which has been generated in accordance with the above-described command, in the region which corresponds to the position of the pixel in the block raster which has fetched the decoded data. After data corresponding to the block raster region has been written, the PDL interpreter 2 controls the synthesizer 3, the compressor 4 and the address controller 8 so that the block raster region is again compressed by the compressor 4 and it is re-stored in the subject position in the compression memory 5. The above-described sequence is repeated for all of the black rasters. Fig. 18 which illustrates the overall structure of the system including the interface is the same as Fig. 1B. The character and line drawing memory 10 has a capacity capable of storing pixel data corresponding to the picture size to be processed. That is, according to this embodiment, it possesses a capacity of one bit for each of 4096 × 4096 = 16,777,216 pixels. Therefore, a memory space having a data capacity of one bit for each address is created in an address space of 16 M. The above-described memory space is a continuous address spaces arranged in such a manner that address spaces are continuously formed in the sequential order from the 0-th to the 4095-th pixels for each scanning line. Furthermore, address spaces for the scanning lines from the 0-th to the 4095-th scanning lines are continuously formed in units of the 4096 addresses. The PDL interpreter 2 accesses a desired address of the character and line drawing memory 10 along the map of the above-described address. In a case where data is black line drawing, "1" is written in the character and line drawing memory. In a case where the other picture is drawn, data is written in the compression memory in accordance with the above-described procedure and as well as "0" is written in the address of the character and line drawing memory at the position of the subject pixel. Data in the character and line drawing memory 10 is read out in synchronization with the timing of image data transmitted from the decoder 6 when the image output is made via the selector 11. The control of reading data from the character and line drawing memory is performed by the character and line drawing memory address control portion 12 in response to a scan synchronization signal and a pixel synchronization signal. Similarly to the counters 31 and 32 in the address controller in the synthesizer 3 shown in Fig. 3, the character and line drawing memory address control portion 12 can be constituted in such a manner that it counts the above-described synchronous signal to generate the memory address to be accessed. The picture signal transmitted from the character and line drawing memory is used as image data about the character and the line drawing. Furthermore, it is used as a selection signal of the selector 11 for selecting character and line drawing data or the image output from the decoder 6. The selector 11 selectively transmits character and line drawing data when character and line drawing data is "1", while the same transmits the output signal from the decoder 6 when it is "0". Since the other structures are same as those according to the third embodiment, their detailed descriptions are omitted here. The encoder and the decoder can easily be constituted by using, for example, an LSI such as CL550 manufactured by C-Cube, U.S.A. in such a manner that a circuit for adjusting the synchronous signal or the like is added if necessary. The sectioning of the above-described block raster is controlled by using the marker code. By using the marker code, the block rasters are individually encoded/decoded. In the above examples, the PDL interpreter 2 discriminates the image positions to be sequentially changed in response to the corresponding commands when it receive the PDL command so that the subject position is decoded, rewritten and re-encoded. However, as shown in Fig. 19, the image buffer 71 and the command buffer 72 are employed so as to temporarily hold the PDL command and data supplied from the host computer 1 by a quantity of a plurality of commands. Furthermore, a certain number of commands are collected so as to collectively rewrite the portions in the same block raster after the portions to be changed have been determined in accordance with the corresponding commands. That is, a process of decoding → rewriting of the subject block raster may be performed in such a manner that execution → re-encoding. Although the character and line drawing memory is formed into the bit map memory according to the above-described examples a structure may be employed which is formed into several bits/pixel of, for example, 4 bits per pixel and which has a bit map for each color cyane, magenta, yellow and black. In this case, the selection signal 11 shown in Fig. 18 may be the logical sum of several bits for the same pixel. Furthermore, the character and line drawing memory may, of course, comprise a compression type memory. In this case, the character and line drawing memory may be arranged similarly to the structure according to the above-described embodiments in which the process is performed by using the image compression memory in the sequential order as decoding → overwriting → re-compressing. As described above, the characters and line drawings which usually have relatively high spatial frequency component and the other images are individually stored in corresponding memory regions so as to be individually published and processed. As a result, the deterioration in the image quality of the characters and line drawings can be prevented. Furthermore, the undesirable rapid and great change of the quantity of the image data code due to the image quality can be prevented. As a result, the PDL can easily be used on the compression memory. That is, the image data is published and processed by using the compression memory. As a result, the overall cost can be significantly reduced in a case where a memory having a data capacity which is sufficiently large to hold actual data is used. As described above, the inner portion of the compression memory is sectioned into the fixed length blocks each of which has a a capacity which is about the average code length of the block raster. The reproduction, changing and re-encoding processes are performed in units of the block raster. Furthermore, the structure according to this embodiment comprises means for detecting whether or not the code length exceeds the above-described fixed block length at the time of the encoding process and means for administrating the blank fixed block in the compression memory. Thus, data of the code of the block raster the code quantity of which exceeds the fixed block length is held over a plurality of fixed length blocks. As a result, the publishing and operation of an image by a compression method in accordance with the variable length encoding method can easily performed. Furthermore, the characters and line drawings which usually have relatively high spatial frequency component and the other images are individually stored in corresponding memory regions so as to be individually published and processed. As a result, the deterioration in the image quality of the characters and line drawings can be prevented. Furthermore, the undesirable rapid and great change of the quantity of the image data code due to the image quality can be prevented. As a result, the PDL can easily be used on the compression memory. Although the PS (Post Script) is employed as the PDL, other PDLs may, of course, be employed. The method of the compression is not limited to the ADCT. The other perpendicular transformation encoding method, predictive encoding method, a run length encoding method and the like may be employed. The publishing method is not limited to the overwriting method. As an alternative to this, a calculation by using the previous data and posterior data (for example, a multiplication is performed or the AND or the OR is calculated). That is, a process such as overlaying or modulation may be performed. The output signal decoded can be formed into a hard copy by a laser beam printer, an ink jet printer, a thermal printer or the like as well as displaying it by a display means. According to an embodiment of the present invention, the capacity of the frame buffer for use when the interpreter develops the source code to image data for each pixel can be reduced to a quantity smaller than 1 page. For example, as shown in Fig. 32, a page 1201 is sectioned into four sections 1202-a to d. Furthermore, the size of the frame buffer is arranged to have the sectioned regions (sub-frames), which are called "sub-frame buffers" hereinafter). The interpreter sequentially performs the development in each region so as to compress the contents of the sub-frame buffer in each region after the above-described development has been completed. The compressed contents are transferred to the compression frame buffer having a capacity of 1 page so as to be stored in the compression frame buffer. When data printing is executed in response to a command issued from the host computer, data in the compression frame buffer is expanded at a transference rate required by the printer engine before the data is transferred to the printer engine. By the actions of the sub-frame buffer and the compression frame buffer, the memory capacity of the system can be reduced. In a case where each of the sectioned regions in the above-described page region is subjected to the development process, the interpreter must store the PDL code by a quantity of 1 page even if the region to be developed at a single process is 1/n of one page. The reason for this lies in that the code of the region to be developed can be described in any portion of the code for the page because the contents to be described within one page may be described in an arbitrary order according to the PDL. However, it is impossible (theorically code can be contained indefinetely) to previously estimate the total quantity of the code for the page. Therefore, the capacity of the PDL code buffer in the interpreter is always able to overflow. If the PDL code buffer is enlarged excessively, the merit obtainable in that the quantity of the memory in the division development process can be reduced will be countervailed. Therefore, the structure must be designed in such a manner that the capacity of the PDL code buffer for one page is predicted statistically. On the other hand, another method may be employed in which all of the PDL codes are transferred from the host computer at each band. However, data of n times must be transferred from the host computer in a case where the one page is sectioned into n portions. The transference efficiency is unsatisfactory, causing the system performance to be deteriorated. Therefore, according to this embodiment of the present invention, a portion of the object to be drawn for one page the overall or a portion of which is included in the divided region is fetched by sorting. Furthermore, the included object is transferred from the host computer to the interpreter at the time of the development. As a result, the capacity of the PDL code buffer in the interpreter before the development can be reduced or eliminated in the above-described method in which the interpreter performs the development in each of the page division regions. Furthermore, the PDL code transference from the host computer to the interpreter can be reduced or made efficient. Then, it will now be described. A ninth embodiment of the present invention is shown in Fig. 31. Reference numeral 1101 represents a host computer for generating the PDL code and 1102 represents a page printer system such as a laser beam printer for forming a latent image on a photosensitive member by laser beams and forming a visible image on a recording medium. Reference numeral 1103 represents a PDL code buffer for storing the PDL code (source code) transferred from the host computer. An interpreter 1104 receives the PDL code from the PDL code buffer 1103 so as to develop it to image data for each pixel. The result of the development is stored in a sub-frame buffer 1105. When the development in the sub-frame has been completed, the contents are transference to a compression frame buffer 1106. The compression frame buffer 1106 compresses and stores the pixel developed data. After the PDL codes for one page has been developed so as to hold it in the compression frame buffer 1106, a printer engine 1107 expands data from the compression frame buffer 1106 so as to read it in a case where printing is executed. The sub-frame buffer 1105 divides one page into a plurality of regions so as to hold the developed data in the above-described regions. Fig. 32 illustrates an example of the above-described process. Reference numeral 1201 represents an example of a picture for one page and 1202-a to d represent divided regions (bands) in one page. The sub-frame buffer 1105 holds developed data for a certain portion of the regions 1202-a to d. Although the frame is divided into four sections according to this embodiment, the present invention is not limited to the number of the sections. Reference numerals 1203 to 1205 represent objects to be drawn. The above-described objects may be described in the PDL code in one page regardless of the describing order. Reference numeral 1206 represents a main scanning direction (X) of the printer engine and 1207 represents a sub-scanning direction (Y). In a case where data is developed in the region 1202a, the PDL code of each of the objects 1203 and 1205 is transferred from the host computer. In this case, the host computer determines whether or not a portion or the overall portion of 1203 and 1205 is included in the region 1202-a. The above-described determination is made in such a manner that the Y-direction maximum and minimum values of each of the objects are detected so as to be subjected to a comparison with the value Y in the boundary portion. It can be performed as shown in table 1 of Fig. 34 in such a manner that a Y-table for recording the maximum and minimum values of Y of each of the objects described in PDL is provided so as to perform sorting made for the purpose of discriminating whether or not the contents of the Y-table are included in the divided region. For example, assumptions are made that the maximum and minimum values of Y of the object 1203 respectively are Y max 1203 and Y min 1203 and the maximum and minimum values of Y of the region 1202-a respectively are Y max 1202-a and Y min 1202-a. In this case, a discrimination must be performed that (Y max 1202a > Y min 1203) and (Y min 1202a < Y max 1203). The other objects and divided regions may be processed similarly. The host computer transfers an object code included in a region developed by the interpreter 1104 from the thus-obtained result. The interpreter 1104 sequentially develops, for example, the regions 1202-a to d. Although a portion of the objects can be drawn over a plurality of regions depending upon the shape and the size of the object, the PDL code is transferred from the host computer to the interpreter whenever each of the regions is developed. For example, the code of the object 1203 is transferred when both of the regions 1202a and 1200b are developed. The transferring order coincides with the sequential order of the original PDL code list. For example, in the case of Table 1, Codes 1203, 1205 and 1204 are transferred in this sequential order, while Codes 1203 and 1205 are transferred when the region 1202a is developed. The sequential order must be 1203 and 1205 in this sequential order. The reason for this lies in that the image becomes different in case where the objects superposed on each other if the sequential order is reversed in the PDL specification in which the posterior image becomes the top image. In order to discriminate whether or not the object is included in the divided region, Y max and Y min must be detected. They may be calculated from the reference point for determining the position of the object denoted by the PDL code (source code) and the Y-directional size of the object. As an alternative to the arrangement in which the discrimination is directly made from the PDL code (source code), it may be made from the intermediate code which further approximates the image data and which has been obtained by conversion. If a strict determination is made that a certain object is included in a divided region, data development for each pixel must be temporarily performed. Therefore, a critical disadvantage will occur in terms of time saving. In a case as shown in Fig. 33 in which character "A" of the object is positioned below a boundary 1304 and its reference point is 303, "A" is not included in a region upper than 304. However, a boundary box 1302 for defining the size of "A" can upward deviate from 1304. In this case, it is difficult to discriminate whether or not "A" is included in the region upper than 1304 if an actual development is not performed. However, large quantity of calculations must be performed for the purpose of performing the development. In this case, an assumption is made that "A" is included in the region in the vertical direction of 1304 before the PDL codes are transferred at the time of the development of each of the regions. That is, in a case where an actual development is performed in accordance with region information (for example, the position at which drawing is started, size and the like) defined by the PDL code, it is transferred if there is a possibility that the object is included in the divided region. As a result, lacking of information taken place in each of the divided regions can be prevented. In a case where the object is a natural image and the pixel is multivalue data, the quantity of data is becomes excessively large. Therefore, when a plurality of number of transferring operation from the host computer are performed, an excessively long time takes to complete the operation, causing the performance (transference efficiency) to deteriorate. An arrangement may be employed to overcome the above-described problem, in which the included portion in each of the regions is sectioned before it is transferred. For example, in a case where the object 1205 shown in Fig. 32 is a natural image, the portion of the object 1205-a is transferred when 1202-a is developed. The portion of the object 1205-b is transferred when 1202-b is developed. The fact that the object is natural image = pixel development data may be detected by a PDL operator of the object. The divided region may be detected by counting the number of data items. According to this embodiment, by transferring the PDL code of the next object from the host computer after the development of each of the objects has been performed in the interpreter, the PDL code buffer can be minimized or eliminated. The quantity of the PDL code to be transferred can be reduced to a value smaller than the number which is n times the sections of the divided page. Therefore, the transferring operation can be performed efficiently. The compression frame buffer 1106 can be eliminated from the structure if the development speed of the interpreter is higher than a required level of the printer engine 1107. The flow of processes including the process of discriminating whether or not the above-described PDL code is included in the divided region is shown in Fig. 35. First, an application software device is set to the host computer and a page printer system capable of performing banding process is assigned as a printer to be connected to the host computer (S1001). Then, the PDL code (source code) included in the first band (divided region) is sorted by using the table 1 shown in Fig. 34 (S1002). The sorted PDL code is transferred to the PDL code buffer 1103 adjacent to the printer (S1003). The transferred PDL code is developed in a sub-frame buffer 1105 by the interpreter 1104 in the transference order (S1004). In this case, "posterior priority" principle, that is, a priority is given to data transferred lately in the superposed portion of the developed image. When all of the PDL codes included in the subject band have been developed, the image data of the subject band is compressed (S1005). The compression is performed in accordance with, for example, ADCT (Adaptive Descrete Cosine Transform) in which a DCT (Descrete Cosine Transform) is performed in each block so as to Huffman-encoding each of the coefficients. However, the compression method is not limited to this. For example, a vector quantization run length encoding method, MH, MH or MMR may be employed. Compressed image data is, in each block, sequentially stored in the compression frame buffer 1106 (S1006). When all of block data about the subject band have been stored, the second band is subjected to the development, compression and storage processes similarly to the first band (S1007). When all of the bands have been subject to the process, printing of one page is performed. The above-described operation is controlled by a printer controlling driver disposed adjacent to the host computer. The driver may be disposed in the page printer system 1102. In this case, commands relating to the system control, for example, the assignment of the printer and a print command and the like are transmitted or received between the driver and the host computer. As described above, according to this embodiment of the present invention, an effect can be obtained in a method arranged in such a manner that the interpreter of a page printer system performs the development process for each of the divided regions of the page, the effect being an effect obtainable in that the capacity of the PDL code buffer before the development process can be reduced or the PDL code buffer can be eliminated from the structure. Furthermore, in a case where the PDL code of the next object is transferred after the development of the object has been completed by the interpreter, the efficiency of transferring the PDL code from the host computer can be improved. As described above, according to this embodiment, the memory capacity of an image processing apparatus can be reduced. Furthermore, the data can be efficiently transferred. In addition, image can be processed efficiently. Fig. 36 illustrates the structure of a circuit of another example of image processing apparatus. Referring to Fig. 36, reference numeral 1 represents a host computer for transmitting Page Description Language (hereinafter called a "PDL"). Reference numeral 302 represents a PDL interpreter for receiving data described in the PDL and developing received data to image data for recording. Reference numeral 303 represents a disk device which is used by the PDL interpreter 302 as a command buffer. Reference numeral 304 represents a small region buffer for holding image data developed into small regions created after the image for one page has been sectioned into a plurality of small regions. Reference numeral 305 represents a compressor (encoder) for transforming image data into compressed image data formed into a code. Reference numeral 306 represents an image compression memory for holding an image for one page in the form of a compressed image data. Reference numeral 307 represents an expander (decoder) for expanding compressed image data to an image data. Reference numeral 308 represents a printer engine for recording expanded and developed image. The host computer 301 transmits page data described in the PDL to the PDL interpreter 302 via the interface 309. Then, the operation of the circuit shown in Fig. 36 will now be described with reference to Fig. 37. When power is supplied to the interpreter 302, it is automatically started. In step S200 shown in Fig. 37, the internal status of the PDL interpreter 302, that is, the counter, the flag and the like required for the operation of the PDL interpreter 302 are reset. Furthermore, the operational mode and the like are initialized to a predetermined default state. The PDL is exemplified by the above-described Post Script (hereinafter called the "PS"). The description will now be made hereinafter that the PDL is PS. In addition, the initialization of the internal state includes the initialization of the graphs. In S201, PS command data for 1 page is fetched by the PDL interpreter 302 via the interface 309 so as to be held in the command buffer 303. The process in step S201 is realized by the PDL interpreter 302 in accordance with detailed sequence shown in Fig. 38. That is, input of a command from the host computer 301 is waited for in step S300 shown in Fig. 38. If the input has been made, the process proceeds to step S301 in which the input command is fetched before the process proceeds to step S302. In step S302, it is determined whether or not the command fetched in step S301 is a copy page command. If it is the copy page command, the process proceeds to step S305. If it is not the copypage command, the process proceeds to step S303. In step S303, it is determined whether or not the command fetched in step S301 is a showpage command. If it is the showpage command, the process proceeds to step S306. If it is not the showpage command, the process proceeds to step S304. As shown in Fig. 5, the PDL interpreter 302 processes and holds two types of files, that is, a current command file 31 and a pre-command file 32 on a command buffer 303. In step S304, a process is performed which is arranged to be performed in a case where the command fetched in step S301 is neither the copypage command nor the showpage command. In step S304, the command fetched in step S301 is added to the current command file 331 before the process returns to step S300. The current command file 331 has been cleared in step S200. In step S305, a process is performed which is arranged to be performed in a case where the command fetched in step S301 is the copypage command. In step S305, the current command file 331 is added to the precommand file 32, the result of this addition being made to be a novel precommand 332. Thus, a determination is made that the sequential processes in step S201 have been completed. Therefore, the process returns from the sequence shown in Fig. 38 to that shown in Fig. 37 before the process proceeds to step S202. In step S306 shown in Fig. 38, a process is performed which is arranged to be performed in a case where the command fetched in step S301 is the showpage command. In step S306, the current command file 331 is copied to the precommand file 332 as it is so that a novel precommand file 332 is created. Thus, a determination is made that the sequential processes in step S201 have been completed. Therefore, the process returns from the sequence shown in Fig. 38 to that shown in Fig. 37 before the process proceeds to step S202. Thus, the sequence in step S201 is completed and the process proceeds to step S202. In step S202, small region pointer i is initialized to 0 before the process proceeds to step S203, the small region pointer i showing the small region which is being processed in a case where the PDL interpreter 302 has divided the image region for one page into a plurality of small regions. Fig. 39 illustrates a stat where the image region for one page is divided into a plurality of small regions. An assumption is made that the image processed by the printer portion is an image composed of less than 6144 pixels in the main scanning direction × less than 8192 pixels in the sub-scanning direction. The image size is able to sufficiently cover an image size (4752 × 6720 pixels) which forms A3-size (297 mm × 420 mm) when a print is made with a pixel density of 400 pixels/(1 inch = 25.4 mm) in both the main scanning direction and the sub-scanning direction. The above-described image size is divided into small regions in each 1024 rasters in the sub-scanning direction. That is, it is considered that the image is divided into small regions composed of 6144 pixels × 1024 rasters. That is, in a case where the orientation of the above-described A3 size image is processed in the lengthwise direction, the image is divided into 7 small regions starting from region 0 to region 6. Similarly, in a case of the A4 lengthwise directional image (3360 × 4752 pixels), the image is divided into 5 small regions starting from region 0 to region 4. The small region buffer is a memory for holding data for pixels in the small region composed of 6144 pixels x 1024 rasters. The above-described buffer has a total × memory capacity of 24 bits composed of 8 bits for each of red, green and blue per pixel. In step S203, the corresponding address on the image compression memory 306 is initialized. That is, a compression memory address pointer (omitted from illustration) is initialized to the leading address for storing the encoding data which corresponds to region 0. Then, the process proceeds to step S204. In step S204, the small region buffer 304 is cleared by the PDL interpreter 302. In step S205, only image data in the small region in the PDL interpreter 302 pointed by the small region pointer is developed and generated in response to a command so as to be stored on the small region buffer 304. The generation of small region i has been completed, the process proceeds to step S206. In step S206, in response to a command supplied from the PDL interpreter 302, data in the small region buffer is compressed via a signal line 310 with respect to the compressor 305. The compressor 305 reads, compresses and encodes data in the small region buffer 304 in response to a command supplied from the PDL interpreter 302. The compressed code data is, by the compressor 305, stored in a portion on the compression memory 306 pointed by the above-described compression memory address pointer. In accordance with this, the compression address pointer is sequentially updated. The compressor 305 transmits a signal denoting the completion (encoding) of all of data items in the small region buffer 304 to the PDL interpreter 302 via the signal line 310. Then, its operation is stopped. The PDL interpreter 302 detects the transmission of the signal, which denotes the completion of the compression operation of the small region buffer 304, from the compressor 305, the detection being made by supervising the signal line 310. Then, the process proceeds to step S207. In step S207, the value of small region point i is increased by one before the process proceeds to step S208. In step S208, it is determined whether or not small region pointer i exceeds 7. If it has exceeded 7, a determination is made that the image development for one page has been completed before the process proceeds to step S209. If it has not exceeded 7, the process returns to step S204 before the similar process is performed for the next small region. In step S209, the decode 307 is started via the signal line 311. The decoder 307 sequentially reads out compression encoded data stored on the image compression memory 306 so as to decode them. Furthermore, the printer engine 308 is started and data decoded are sequentially transmitted in synchronization with the operation of the printer engine 308. The decoder 307 decodes all of data in the image compression memory 306 before it transmits a signal denoting the completion of decoding of data. Then, its operation is stopped. The PDL interpreter 302 detects the completion of decoding by supervising the signal line 311 before the process returns to step S200 in which the process for the next page is commenced. The above-described process is repeated so as to sequentially print the ensuing pages. Then, a process of developing data in i-th small region in step S205 will now be described with reference to Figs. 41 to 45. Figs. 44 and 45 illustrate an example of the page description made in accordance with the PS. Figs. 44 and 45 illustrate the result of the output made in a case where the PDL interpreter 2 is subject to the page description shown in Fig. 44 before the same is subjected to a page description shown in Fig. 45. Fig. 47 illustrates the result of the output made in a case where the PDL interpreter 302 is subjected to the page description shown in Fig. 44. Fig. 43 illustrates the result of the output made in a case where the PDL interpreter 302 is subjected to the page description shown in Fig. 45. As described with reference to Fig. 38, in a case where the sequential page descriptions shown in Fig. 44 have been transmitted from the host computer 301, sequential commands to copypage denoted by W16 shown in Fig. 44 are accommodated in the precommand file 332, the precommand file 332 being used to generate an image for one page. Then, in a case where sequential page descriptions shown in Fig. 45 has been supplied from the host computer 301 subsequently to the sequential page descriptions shown in Fig. 44, page descriptions from W1 to W15 shown in Fig. 44 are added before the sequential page descriptions shown in Fig. 45 are added so that a novel precommand file is processed, the precommand file being used to generate an image for one page. The image shown in Fig. 42 is generated from the description shown in Fig. 44 in the following sequence: referring to Fig. 45, the commands for actually developing image data on the memory are W9 and W15 only. The other commands are used to only change the internal state of the PDL interpreter 302. In response to command W9, an image 710 shown in Fig. 42 is drawn on the memory before an image 720 shown in Fig. 42 is drawn on the memory in response to command W15. Therefore, in the process in step S205, when the commands such as W9 and W15 for actually developing data on the memory is executed by the PDL interpreter 302, the internal state of the PDL interpreter 302 is checked at this time. As a result, only the image portion corresponding to the i-th region may be processed. That is, by checking the graphic state immediately before the execution of command W9 (immediately after command W8 has been executed), the area on the memory in which a graph to be developed on the memory in response to command W9 is drawn is checked. As a result, in response to command W9, only the subject portion is drawn on the small region buffer while checking whether or not the Y-address of each pixel at the time of development of only the portion overlapping the i-th region, is in the i-th region, that is, whether or not it is in (1024 × i to 1024 × (i + 1) - 1) raster. Also command W15 is executed in such a manner that image data is developed while checking the region. Commands except for commands W9 and W15 are not commands for developing data on the memory but respectively are commands for changing the graphic state of the interpreter or defining the operational procedure or the like. All of the above-described operations are the operations for only changing the internal state of the interpreter, the operations being executed whenever the small regions are developed. In the case of the page description shown in Fig. 45, only commands W27 and W33 are commands to be executed while checking the developed pixel positions. The other commands are commands for only changing the internal state. In a case where an image is drawn in response to only the commands shown in Fig. 45, an image can be drawn as shown in Fig. 42. According to the above-described examples, only fill command W27 is the command to be executed while checking the developed region. Furthermore, there are provided various commands, that is, image, imagemask, show, ashow, widthshow, awidthshow, kshow and stroke. Also the above-described commands are executed by performing the development on the memory. The compressor (encoder) 305 and the decoder 307 can easily be realized by using, for example, an LSI CL550 manufactured by C-Cube, U.S.A. in such a manner that a circuit for adjusting the synchronous signal or the like is added if necessary. As a result, the compression can be performed in accordance with the above-described ADCT method suggested by JPEG. Referring to Figs. 41 to 43, the coordinates of each of the apexes of each of the graphs 710, 720, 730 and 740 are expressed by (x, y). According to the PS method, the lower left corner of the image region assumed as shown in Fig. 46 is defined to be (0, 0). Therefore, the position of the graphic image is expressed according to the above-described coordinate system. On the other hand, the raster position on the memory is scanned while making the upper left corner to be the start point. Therefore, in a case of an image of A3 of 400 dpi is processed, it corresponds to (x, y), while it corresponds to the position of the x-th pixel on the (6720 - y)-th scanning line. The address transformation can automatically be executed by the PDL interpreter. In a case where the quantity of page description command data becomes larger than the capacity of the command buffer 303 to be processed and thereby it cannot be processed, the PDL interpreter 302 transmits this fact via the interface 309. The host computer 301 is able to recognize the state of the PDL interpreter by supervising the above-described signal. According to the above-described example, the current command file 331 and the precommand file 332 shown in Fig. 40 file the command received by the PDL interpreter 302. The above-described information may be held as a temporarily encoded intermediate language. Furthermore, by holding, as shown column 2 of Fig. 47, the maximum value and the minimum value of the Y-directional coordinate value of the area which is the subject of the drawing by the commands such as codes W9, W15, W27 and W33 which develop data on the memory in such a manner that the maximum value and the minimum value are added to the intermediate code, a discrimination whether or not the drawing in each of the small regions generates by the execution of the command can easily be made. As a result, the execution speed can be raised. Furthermore, as shown in column 3 of Fig. 47, by adding the fact whether or not each of the data development commands has a drawing region in each of the small regions at the time of the intermediate-coding, the execution speed can further be raised. According to the previous description, a plurality of small region buffers may be used. Fig. 48 illustrates an example of the structure in which two small region buffers are used. In this case, a PDL interpreter 2102 operates a small region buffer 2041 and another small region 2042 by controlling a multiplexer 2120 and a selector 2130. That is, the multiplexer 2120, through a signal line 2113, switches over the output from the PDL interpreter 2102 to be connected to the small region buffer 2041 or the small region buffer 2042. The selector 2130 switches over, via a signal line 2112, the PDL interpreter 2102 to connect the original data buffer, through which a compressor 2105 fetches data, to the small region buffer 2041 or the small region buffer 2042. The PDL interpreter 2102 acts to read data from the small region buffer 2042 to the compressor 2105 when data is being developed to the small region buffer 2041. Furthermore, it acts to read data from the small region 2041 to the compressor 2105 when data is being developed to the small region buffer 2042. The above-described actions are performed via the signal line 2110 while supervising the state of the compressor. The other portions are the same as those according to the above-described embodiments. The compression method (encoding method) is not limited to the ADCT method. It may be any of the vector quantizing, the MH, the MR methods. The number of the rasters in the small region is not limited to 1024. For example, the other number of rasters may, of course, be employed for example, 8 rasters, 256 rasters or the like. As described above, according to this example, image data, which is the result of the processing, modifying and publishing operations performed in accordance with the image position instructed from outside, is generated in units of the small regions before it is compressed. As a result, the number of compression processes required for each of the regions can be reduced. In addition, the development memory can be reduced to correspond to the small region. Therefore, the cost can be significantly reduced in comparison to a case where a memory having a data capacity which is sufficiently large to hold actual data is used.

Claims: An image processing apparatus comprising: supplying means (1, 1101) for supplying a plurality of code data representing an image for a page including a plurality of object images; interpreting means (2, 1104) for generating image data corresponding to said image by interpreting the code data supplied by said supplying means; and output means (2, 1105) for outputting the interpreted image data, characterised in that the apparatus further includes means (1105) for dividing the page of image data into a plurality of bands, with each object image existing in one or more of the bands, at least one of the object image being multi-value image (1205) in which one pixel is represented by multi-value data, and wherein said interpreting means is adapted to interpret and output the image data in each band, said supplying means being adapted to select code data necessary to represent one of the plurality of bands from the plurality of code data, in synchronism with development of each band and supplies the selected code data such that the coordinates for all these objects are supplied which have a portion included in the band being interpreted, and the order or the number of supplying the plurality of code data of the objects by said supplying means is determined according to size or shape of each object image represented by the plurality of code data. Apparatus according to claim 1 or claim 2, wherein the multi-value image is a natural image. Apparatus according to claim 1 or 2, wherein the object image represented by the code data includes a natural image. Apparatus according to any one of claims 1 to 3, wherein said supplying means is adapted to execute the selection on the basis of command data in the form of source code. Apparatus according to any one of claims 1 to 3, wherein said supplying means executes the selection on the basis of command code in the form of intermediate code. An image processing apparatus comprising: supplying means (1, 1101) for supplying a plurality of code data representing an image for a page including a plurality of object images; interpreting means (2, 1104) for generating image data corresponding to said image by interpreting the code data supplied by said supplying means; and output means (2, 1105) for outputting the interpreted image data, characterised in that the apparatus further includes means for compressing the image data generated by said interpreting means, and means (1105) for dividing the page of image data into a plurality of bands, with each object image existing in one or more of the bands, and wherein said interpreting means is adapted to interpret and output the image data in each band, said supplying means being adapted to select code data necessary to represent one of the plurality of bands from the plurality of code data, in synchronism with development of each band and supplies the selected code data such that the coordinates for all these objects are supplied which have a portion included in the band being interpreted, and the order or the number of supplying the plurality of code data of the objects by said supplying means is determined according to size or shape of each object image represented by the plurality of code data. Apparatus according to claim 6, wherein said compression means compresses the interpreted image data for a band each time the code data for a band selected by said supplying means is interpreted by said interpreting means (S1005). Apparatus according to claim 6 or claim 7, wherein said compression means executes a variable length coding. Apparatus according to claim 8, wherein said compression means executes an orthogonal transformation in the image. Apparatus according to any preceding claim, further comprising image forming means for forming an image on a medium on the basis of the image data generated by said interpreting means. Apparatus according to claim 10, wherein said image forming means is a laser beam printer. Apparatus according to any preceding claim, whrein the plurality of code data are described in PDL (page description language). Apparatus according to claims 1 to 12, wherein said supplying means is a host computer.

Inventors: HONMA HIDEO, ISHIDA YOSHIHIRO, KAWAMURA NAOTO, HONMA, HIDEO, ISHIDA, YOSHIHIRO, KAWAMURA, NAOTO, HONMA, HIDEO, CANON KABUSHIKI KAISHA, ISHIDA, YOSHIHIRO, CANON KABUSHIKI KAISHA, KAWAMURA, NAOTO, CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1991
Main classification: G06T9
IPC codes: H04N1, H04N7, G06T9