ECL circuit constituted in semiconductor integrated circuit

Abstract: An ECL circuit is designed such that at the beginning of the falling of the output level, the current flowing to an output terminal (11) is rapidly led in the direction where it will be reduced, the potential of the output terminal (11) at this time is directly detected, and a pull down transistor (15) is controlled through a feedback loop, thus assuring high-speed operation and low power consumption. A control circuit is provided to regulate the collector current of the pull down transistor (15), which is used to drop the level of the potential at the output terminal (11). This control circuit is so designed that the base current of the pull down transistor (15) is controlled by the operation of another, single transistor (12), and no capacitor which will obstruct the circuit integration is employed to drive the pull down transistor (15). The structure of this circuit is therefore advantageous in realizing higher integration.

Description: The present invention relates to an ECL (Emitter Coupled Logic) circuit which requires high-speed operation and low power consumption. In the prior art (Fig. 1), the rising speed of an output waveform is determined by the current flow from the emitter follower of an output transistor. On the other hand, the falling speed is determined by the discharging of charges in a load capacitor C L through a resistor R EF connected to the emitter of the output transistor. To increase the speed, therefore, the value of the resistor R EF has only to be reduced. However, this undesirably increases the current consumption. The prior art cannot therefore increase the falling speed of the output without increasing the power dissipation. According to the structure as disclosed in USPs 4,629,913, 4,539,493, 4,687,953, 4,835,420, the output stage is designed to have a totem pole structure with the upper transistors constituting a conventional emitter follower and the lower transistor forming a differential waveform using the capacitor C, so that operating this lower transistor at the falling time of the output discharges the charges from the load capacitor C L . This arrangement can improve the falling speed of the output by increasing the capacitance of the capacitor C. Increasing the capacitance of the capacitor, however, increases the area of the capacitor, which will hinder circuit integration and thus result in design restriction. It is therefore an object of the present invention to provide an ECL circuit which can realize low power consumption and high-speed operation without any design restriction to obstruct the circuit integration. According to the present invention, there is provided an ECL circuit as set out in claim 1. According to the structure described above, when the output level falls, the fourth transistor instantaneously discharges a load capacitor to be connected to the output terminal. Then, the control circuit regulates the collector current of the fourth transistor for direct discharge from the output terminal. This operation reduces the wasteful power consumption more than needed. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram illustrating the structure of a prior ECL circuit; and Fig. 2 is a circuit diagram illustrating the structure of an ECL circuit according to one embodiment of the present invention. A preferred embodiment of the present invention will now be described referring to the accompanying drawing. Fig. 2 illustrates the circuit structure of the embodiment of the ECL circuit according to the present invention as applied to constitute an inverter circuit. A differential pair of NPN transistors 1 and 2 have their emitters commonly connected to a constant-current supply 3, which is connected to a constant-voltage supply 4. As the potential on the positive side (+) of the voltage supply 4 is connected to a ground voltage V SS , the current from the current supply 3 flows to a negative power supply voltage V EE on the negative side (-). An input terminal 5 is connected to the base of the transistor 1, while the ground voltage V SS is connected to the collector of the transistor 1. Between the collector of the transistor 1 and the ground voltage V SS is located a resistor 6. A constant-voltage supply 7 is connected between the base of the transistor 2 and the ground voltage V SS , and a predetermined reference voltage V ref whose value is between V SS and V EE is applied to the base of the transistor 2. The collector of the transistor 2 is also connected to the ground voltage V SS . Between the collector of the transistor 2 and the ground voltage V SS , resistors 8 and 9 are connected in a series. The collector of the transistor 1 is connected to the base of an output NPN transistor 10. The transistor 10 has its collector connected to the ground voltage V SS , and its emitter connected to an output terminal 11. An NPN transistor 12 has its collector connected to the contact point of the resistors 8 and 9 and its emitter connected to the output terminal 11. A constant-voltage supply 13 is inserted between the base of the transistor 12 and the ground voltage V SS , and a predetermined negative voltage V B whose value is between V SS and V EE is applied to the base of the transistor 12. A diode 14 has its anode connected to the collector of the transistor 2, and its cathode connected to the base of an NPN transistor 15. The collector of this transistor 15 is connected to the output terminal 11. The emitter and the base of the transistor 15 are connected to each other through a resistor 16. A constant-voltage supply 17 is arranged between the emitter of the transistor 15 and the ground voltage V SS , a predetermined negative voltage V TT whose value is between V SS and V EE is supplied to the emitter of the transistor 15. The operation of the circuit with the above structure will now be explained. When a signal at the input terminal 5 falls, the collector potential of the transistor 1 of the differential pair rises. As a result, the base potential of the transistor 10 rises, and the transistor 10 is switched on, sending an "H" level (high level) signal to the output terminal 11. Since the collector potential of the transistor 2 of the differential pair is low at this time, no current, which is large enough to turn of the transistor 15, flows to the diode 14, and the transistor 15 is therefore in an OFF state. Further, as the emitter potential of the transistor 12 has been increased due to the ON state of the transistor 10, the transistor 12 is in an OFF state. When the signal of the input terminal 5 rises, the transistor 1 is switched on, and the collector potential of the transistor 2 rises. The current flows to the diode 14 in accordance with the collector potential, so that the transistor 15 is rendered on, reducing its collector potential. The potential of the output terminal 11, therefore, falls down to an "L" level (low level). The transistor 12, whose emitter is connected to the collector of the transistor 15, is turned on as the emitter potential decreases. Accordingly, the collector potential of the transistor 2 drops, thus decreasing the base potential of the transistor 15. The output terminal 11 is stably kept at the "L" level. With the above circuit arrangement, when the signal at the input terminal 5 rises, a differential pulse is supplied to the base of the transistor 15. It is therefore sufficient to permit a large current to instantaneously, not constantly, flow through the collector of the transistor 15. Therefore, the "L" level current is stably output, and the power consumption can be reduced. A capacitor which interferes with integration is not used to drive the transistor 15 to lower the potential level of the output terminal 11, so that the circuit with the above structure is advantageous in realizing the integration. In other words, this circuit structure is most suitable for higher integration, because the collector current potential of the transistor 15 is used to lower the potential level of the output terminal 11 according to this embodiment, and the control circuit to control the collector current is so designed that the base current of the transistor 15 is controlled by the operation of a single transistor 12. The timings at which the transistor 12 is switched on and off are determined according to the divided resistance of the resistors 8 and 9, and the voltage V B of the voltage supply 13. According to the present invention as described above, at the beginning of the falling of the output level, the current flowing to the output terminal 11 is rapidly led toward the direction where it will be reduced, the potential of the output terminal 11 at this time is directly detected, and the transistor 15 is controlled through a feedback loop. With this structure, high-speed operation and low power consumption are assured.

Claims: An ECL circuit constituted in a semiconductor integrated circuit, comprising: a differential pair including first and second transistors (1, 2) having emitters connected to each other; a third transistor (10) having a base connected to the collector of the said first transistor (1); a fourth transistor (15) having a base connected to the other collector output of said differential pair; a logic output terminal (11) connected to an emitter of said third transistor (10) and a collector of said fourth transistor (15); and a fifth transistor (12) for detecting a potential at said logic output terminal (11) and controlling the output of said second transistor (2) through a feedback loop, and having a collector and an emitter connected between a predetermined potential point, determined by dividing a load resistor element provided at said collector of said second transistor (2), and said logic output terminal (11), the fifth transistor being biased by a predetermined base potential. An ECL circuit according to claim 1 and constituting an inverter circuit, wherein the: first and second transistors (1, 2) each have a collector coupled to a first potential (V SS ) and an emitter coupled to a second potential (V EE ); and the circuit further comprises a constant-current supply (3) inserted between said emitters of said first and second transistors (1, 2) and said second potential (V EE ); an input terminal (5) connected to a base of said first transistor (1); a first resistor element (6) inserted between said collector of said first transistor (1) and said first potential (V SS ); a reference potential (V ref ) connected to a base of said second transistor (2); second and third resistor elements (8, 9) inserted between said collector of said second transistor (2) and said first potential (V SS ) to form the divided load resistor; wherein the base of the third transistor (10) is connected to said collector of said first transistor (1), and the collector of the third transistor is connected to said first potential (V SS ); and wherein the emitter of the fourth transistor (15) is connected to a first predetermined potential (V TT ); the circuit further comprising a fourth resistor element (16) connected between a base and said emitter of said fourth transistor (15); and a diode (14) inserted between said collector of said second transistor (2) and said base of said fourth transistor (15).

Inventors: SUGIMOTO YASUHIRO, SUGOH TAKESHI, SUGIMOTO, YASUHIRO, SUGOH, TAKESHI, SUGIMOTO, YASUHIRO, C/O INTELLECTUAL PROPERTY DIV., SUGOH, TAKESHI, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: H03K19
IPC codes: H03K19