PHASE LOCKING CIRCUIT FOR JITTER REDUCTION IN A DIGITAL MULTIPLEX SYSTEM

Abstract: A phase locking circuit for jitter reduction in a digital multiplex system includes a feed-back operational amplifier (OP). Two antiparallel coupled diodes (D1, D2) are arranged on one input of the amplifier for achieving automatic gain control, the other input of the amplifier being connected to a reference voltage (Ref).

Description: Phase Locking Circuit for Jitter Reduction in a Digital Multiplex System The present invention relates to a phase locking circuit for jitter reduction in a multiplex system, including a feed¬ back operational amplifier. In a digital multiplexer of the digital cross connect (DCC) type, a phase locked circuit or loop (PLL) shall lock on to frequency differences, which requires "large" gain and "large" bandwidth. When the system has been phase locked, the output signal shall have low inherent jitter, in accordance with standards for acceptable jitter level, which requires "low" gain due to digitally generated jitter in the multiplex system. Solutions up to now have comprised the manipulation of gain and bandwidth, with accompanying problems, either with jitter or locking. The object of the present invention is to provide a new solution to the problem of inherent jitter contra phase lock¬ ing in a digital multiplexer of the DCC type in a simple, cheap, voluminously economic and current saving way. This object is achieved with a circuit of the kind de- scribed in the introduction, and with the characterising features stated in claim 1. With the circuit according to the invention low gain in a locked circuit is thus obtained in a very simple way, re¬ sulting in low inherent jitter, and at the same time high gain for a circuit that has not been locked, or has a high input jitter. According to the one embodiment of the circuit according to the invention, an RC circuit is arranged before the diodes on the amplifier input to pass through frequency and phase differences, for the purpose of filtering, but to attenuate the input frequencies and input signals to the phase compara¬ tor. According to another advantageous embodiment of the circuit according to the invention, a series resistance is provided on the amplifier input for dimensioning purposes. This resistance is intended to limit the magnitude of the gain for an unlocked circuit, and in principle it could be included in the resistance of the above-mentioned RC circuit. However, in arranging this gain regulation resistance separa¬ tely the adjustment of the gain is facilitated. According to another advantageous embodiment of the cir¬ cuit according to the invention, the amplifier is of the FET or CMOS type with a high-ohm amplifier input, so that the load from the amplifier will be low. According to a further advantageous embodiment of the circuit according to the invention, the reference voltage for the amplifier is selected such that the operation will take place substantially in the central part of the buffer store. An embodiment of the circuit according to the invention, selected as an example, will now be described more in detail with reference to the accompanying drawing on which Figure 1 illustrates the location of the circuit in a practical app¬ lication, and Figure 2 is a circuit diagram of the circuit. The circuit 2 in accordance with the invention is connec¬ ted between a phase comparator 4 and a voltage controlled oscillator VCO with associated buffer store 6, as illustrated in Figure 1. D in and Cl in respectively denote data and clock inputs, and D out and Cl out respectively denote outputs for data and clock signals. The circuit in accordance with the invention includes an operational amplifier OP, which is fed back by the loop R 2 , C 2 r as will be seen from Figure 2. R 2 is a high-ohm resistan¬ ce, and the capacitor C 2 is dimensioned to give a long time constant (DC separation) . One input on the amplifier OP is connected to the phase comparator via an RC circuit, which is adapted to pass fre- quency diferences and block fundamental frequencies to the phase comparator. There is thus obtained at the point A substantially the phase and frequency difference from the phase comparator and only a low superposed AC level. Two anti-parallel coupled diodes O- and D 2 are connected in series with a resistance R_ between the point A and the input of the amplifier OP. Desired automatic gain control is thus realised in a very simple way. The gain F will be substantially F = S 2 R l + R D12 where R D ι denotes a mean value of the resistance through the diodes. For a locked PLL circuit U uτ is constant, and a small current flows through the diodes O_ and D , which then will be high-ohmic, the gain F decreasing and the jitter being attenuated. For an unlocked PLL circuit, a larger current passes through the diodes D x and D 2 , which then become low- ohmic, and the gain increases, so that the phase and fre- quency differences can be captured. There is thus obtained in a simple way the desired automtaic gain control with a smooth transition between the two states, and which thus switches to low-ohm state between high- and low-ohm states in response to variations in the input voltage U IN . The circuit according to the invention includes two anti¬ parallel coupled diodes D_ and D 2 to be able to operate in both directions. The diodes are suitably ordinary silicon diodes. The resistance R_ is selected so that the gain F will be of a suitable magnitude in the case when the diodes D 2 and D 2 are low-ohmic, i.e. when R D12 ^ s approximately equal to zero. In principle, R_ could be included in the resistance R, but the adjustment of the gain F is facilitated by the arrange¬ ment of a separate resistance R_ for this purpose. The ope- rational amplifier OP is suitably of the FET or CMOS type, with a high-ohm amplifier input, such that it conducts as small a current as possible through the diodes, thus making them high-ohmic. As illustrated in the figure, the circuit may suitably operate at signal levels of 5 V, it then being suitable to choose the reference voltage Ref to the operational ampli¬ fier OP equal to 2.5 V, which will mean that operation will be substantially in the middle of the buffer store 6, cf Figure 1. •

Claims: CLAIMS 1. Phase locking circuit for jitter reduction in a di- gital multiplex system, including a feed-back operational amplifier, characterised in that two anti-parallel coupled diodes (D lf D 2 ) are arranged at one input to the amplifier (OP) for achieving automatic gain control, the other input to the amplifier being connected to a reference voltage. 2. Circuit as claimed in claim 1, characterised in that an RC-circuit is arranged before the diodes on the amplifier input for only letting through phase and frequency differen¬ ces for filtering purposes. 3. Circuit as claimed in claim 1 or 2, characterised in that a further series resistance (R_ ) is provided on the amp¬ lifier input for dimensioning purposes. 4. Circuit as claimed in any one of claims 1-3, charac¬ terised in that the amplifier is of the FET or CMOS type, with high-ohmic amplifier input. 5. Circuit as claimed in any one of claims 1-4, charac¬ terised in that the reference voltage for the amplifier is selected such that operation will be substantially in the middle of a buffer store (6) .

Inventors: BLADH MATS, BLADH, MATS
Applicants: ERICSSON TELEFON AB L M, TELEFONAKTIEBOLAGET L M ERICSSON
Application year: 1991
Main classification: H04J3
IPC codes: H03L7, H04J3