Dynamic type semiconductor memory device

Abstract: This invention discloses a dynamic type semiconductor memory device including a plurality of memory cells (MC), plural pairs of bit lines for supplying data to the plurality of memory cells (MC), a first sense amplifier (9, 10) arranged for each of the plural pairs of bit lines, for amplifying a bit line signal, a pair of data input/output lines consisting of first and second data input/output lines (DQ, DQ ), for extracting data from the plural pairs of bit lines, a second sense amplifier arranged for each of the plural pairs of bit lines and consisting of first and second driver MOS transistors, for extracting charges from the data input/output lines in a data reading operation, and for amplifying a data input/output line signal, first and second column selecting transistors (7, 8) which is inserted between the pair of data input/output lines and the second sense amplifier and gates of which are connected to a column selecting line (CSL), and first and second write transistors (13, 14), the first and second write transistors being turned on in a data writing operation.

Description: The present invention relates a dynamic type semiconductor memory device having a sense amplifier for amplifying and outputting a micro signal on a bit line. The arrangement of a sense amplifier section in a conventional dynamic type semiconductor memory device (to be referred to as a DRAM hereinafter) is shown in Fig. 1, and operational waveforms thereof are illustrated in a timing chart in Fig. 2. That is, when a signal from a word line WL rises, a MOS transistor 1 in a memory cell MC is turned on, and a signal corresponding to data stored in a capacitor 2 is read to a bit line BL, thereby generating a micro potential difference between a pair of bit lines BL and BL . Thereafter, when a signal from a sense amplifier control line SAN for activating an n-channel side sense amplifier consisting of two n-channel MOS transistors 3 and 4 is dropped from 0.5·V CC to V SS , a potential of the low-potential side bit line ( BL in Fig. 2) is decreased sequentially from 0.5·V CC to V SS . Thereafter, when a signal from a sense amplifier line SAP for activating a p-channel side sense amplifier consisting of two p-channel MOS transistors 5 and 6 is raised from 0.5·V CC to V CC' a potential of the high-potential side bit line (BL in Fig. 2) is increased sequentially from 0.5·V CC to V CC . When the potential difference between the bit lines BL and BL is sufficiently large, a signal from a column selecting line CSL is raised, and a pair of column selecting n-channel MOS transistors 7 and 8 are turned on, thereby causing a signal to appear from a pair of input/output lines DQ and DQ precharged to be V CC in advance. In a conventional DRAM, a signal from a pair of bit lines cannot be disadvantageously transmitted to a pair of data input/output lines at a high speed, because a potential of the column selecting line CSL cannot be raised unless the potential difference between a pair of bit lines is sufficiently amplified. If the potential of the column selecting line CSL is raised when the potential difference between the pair of bit lines is small, the potentials of the pair of bit lines become floating state due to an entrance of charges precharged to the pair of data input/output lines, and data may be broken due to unbalance of the potentials of the pair of bit lines. In addition, when an integration density of memory cells in a DRAM is increased, a time required for amplifying the potential difference between the pair of bit lines is further prolonged. Therefore, since a delay time of the sense amplifier section occupies a very large part in an access time, the delay time will be further increased in the future. The preamble of claim 1 contains features known previously, as shown in Figure 1 and reflected also in DE-A-3 904 560. EP-A-0 316 902 shows the possibility of isolating the bit lines from the sense amplifier and the input/output data lines during a read operation. The present invention has been made in consideration of the above description, and has as its object to provide a dynamic type semiconductor memory device in which signal transmission in a data read path from a bit line to a data input/output line is rarely delayed, thereby obtaining a high-speed operation. According to the present invention, there is provided a dynamic type semiconductor memory device as set out in claim 1. Another aspect of the invention is set out in claim 13. In addition to the first sense amplifier for amplifying a bit line signal, the second sense amplifier for amplifying a signal from a pair of data input/output lines in a data reading operation is arranged, and a pair of bit lines are connected to the gates of the two driver MOS transistors constituting the second sense amplifier. Therefore, the signal from the pair of data input/output lines can be amplified without any influence on an amplification operation for the bit line signal in the first sense amplifier. Since the second sense amplifier is arranged, the bit line signal and the data input/output line signal can be started to be almost simultaneously amplified. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a circuit diagram showing a conventional DRAM; Fig. 2 is a timing chart of the conventional DRAM shown in Fig. 1; Fig. 3 is a circuit diagram showing an arrangement of a DRAM according to the first embodiment of the present invention; Figs. 4 and 5 are timing charts showing an operation of the DRAM according to the first embodiment; Fig. 6 is a circuit diagram showing an arrangement of a DRAM according to the second embodiment of the present invention; Figs. 7 and 8 are timing charts showing an operation of the DRAM according to the second embodiment; Fig. 9 is a circuit diagram showing an arrangement of a DRAM according to the third embodiment of the present invention; Fig. 10 is a circuit diagram showing an arrangement of a DRAM according to the fourth embodiment of the present invention; Fig. 11 is a circuit diagram showing an arrangement of a DRAM according to the fifth embodiment of the present invention; Fig. 12 is a circuit diagram showing an arrangement of a DRAM according to the sixth embodiment of the present invention; Fig. 13 is a circuit diagram showing an arrangement of a DRAM according to the seventh embodiment of the present invention; Fig. 14 is a circuit diagram showing an arrangement of a DRAM according to the eighth embodiment of the present invention; Fig. 15 is a circuit diagram showing an arrangement of a DRAM according to the ninth embodiment of the present invention; and Fig. 16 is a circuit diagram showing an arrangement of a DRAM according to the tenth embodiment of the present invention. Embodiments of the present invention will be described below with reference to the accompanying drawings. Fig. 3 is a circuit diagram showing an arrangement of a DRAM according to the first embodiment of the present invention. A plurality of memory cells MC (only one is illustrated) are connected to a word line WL. As shown in Fig. 3, each of the memory cells MC consists of a selecting MOS transistor 1 and a data memory capacitor 2. The gate of the selecting MOS transistor 1 is connected to the word line WL, and the source or drain of the transistor connected to an electrode opposite to an electrode to which a predetermined potential V PL of the capacitor 2 is applied is connected to a corresponding bit line BL or BL (BL side in Fig. 3). An n-channel side sense amplifier 9 consisting of two n-channel MOS transistors 3 and 4 and a p-channel side sense amplifier 10 consisting of two p-channel MOS transistors 5 and 6 are connected between the pair of bit lines BL and BL . The drain and gate of the transistor 3 of the n-channel side sense amplifier 9 are connected to the bit lines BL and BL , respectively, and the drain and gate of the transistor 4 are connected to the bit lines BL and BL, respectively. The sources of both the transistors 3 and 4 are commonly connected to each other. That is, the two transistors 3 and 4 are connected to be operated as a flip-flop, and the common source of the transistors 3 and 4 is connected to a sense amplifier control line SAN for activating the sense amplifier 9. The drain and gate of the transistor 5 of the p-channel sense amplifier 10 are connected to the bit lines BL and BL , respectively, and the drain and gate of the transistor 6 are connected to the bit lines BL and BL, respectively, and the sources of both the transistors 5 and 6 are connected to each other. That is, the two transistors 5 and 6 are connected to be operated as a flip-flop, and the common source of the transistors 5 and 6 is connected to a sense amplifier control line SAP for activating the sense amplifier 10. A bit line sense amplifier for amplifying a potential difference between the pair of bit lines consists of the n-channel side sense amplifier 9 and the p-channel side sense amplifier 10. A column selecting n-channel MOS transistor 7 and a data input/output line signal amplifying n-channel MOS transistor 11 are connected in series between one data input/output line DQ of a pair of data input/output lines and a ground potential V SS , and a column selecting n-channel MOS transistor 8 and a data input/output line signal amplifying n-channel MOS transistor 12 are connected in series between the other data input/output line DQ and the ground potential V SS . The gates of both the column selecting transistors 7 and 8 are connected to the same column selecting line CSL, the gate of the transistor 11 of the two data input/output line signal amplifying transistors is connected to the bit line BL , and the gate of the other transistor 12 is connected to the bit line BL. That is, a data input/output line sense amplifier for amplifying a potential difference between the pair of data input output lines in accordance with signals from the bit lines BL and BL consists of the two transistors 11 and 12, and both the transistors 11 and 12 serve as driver transistors. A data write n-channel MOS transistor 13 is connected between a common connection node A of the transistors 7 and 11 and the bit line BL, a data write n-channel MOS transistor 14 is connected between a common connection node B of the transistors 8 and 12 and the bit line BL . The gates of both the data write transistors 13 and 14 are connected to a data write control line WRT and simultaneously ON/OFF-controlled by a signal from the signal line WRT. An operation of the DRAM with the above arrangement will be described below with reference to timing charts in Figs. 4 and 5. Fig. 4 is a timing chart in a data reading state. A signal from the word line WL rises first. Substantially at the same time, a signal of the column selecting line rises. When a signal from the word line WL rises, the MOS transistor 1 in the memory cell MC is turned on, and a signal corresponding to data stored in the capacitor 2 is read out on the bit line BL side. In this case, since potentials of the bit lines BL and BL are precharged to a potential 0.5·V CC which is equal to half the power source potential V CC in advance by a means (not shown), the transistors 11 and 12 are simultaneously turned on. Therefore, when the transistors 7 and 8 are turned on in response to a signal from the column selecting line CSL, charges in the data input/output line DQ are extracted through the transistors 7 and 11 connected in series, and charges of the data input/output line DQ are extracted through the transistors 8 and 12 connected in series. That is, potentials of the pair of data input/output lines having a parasitic capacitances larger than those of the pair of bit lines are decreased. When a signal from the word line WL completely reaches "H" level (level generally obtained by bootstrapping the power source potential V CC' , e.g., 1.5·V CC ), a signal from the sense amplifier control line SAN for activating the n-channel side sense amplifier 9 is dropped from 0.5·V CC to the ground potential V SS . Thus, a low-potential bit line (in this case, the bit line BL ) of the pair of bit lines is sequentially dropped to the V SS side. In this case, a speed of decreasing the potential of the bit line BL is low because the number of memory cells connected to one word line is very large, for example, a word line has 1,024 memory cells in a 4-Mbit DRAM. Therefore, since the number of n-channel side sense amplifiers is equal to the number of memory cells, a large amount of charges must be extracted through the common signal line SAN , and a speed of extracting charges is to be low by an influence of a line resistance present on the signal line SAN . This tendency will be more conspicuous as an integration density of memory cells is increased, e.g., from a 16-Mbit DRAM to a 64-Mbit DRAM. The signal of the sense amplifier control line SAN is dropped, and after a short time, the signal from the sense amplifier control line SAP for activating the p-channel side sense amplifier 10 rises from 0.5·V CC to V CC . Therefore, the high-potential side bit line (in this case, the bit line BL) sequentially rises to V CC . In this case, a speed of increasing the potential is very low because of the same reason as described above. When a potential difference is generated between the pair of bit lines, the conductances of the transistors 11 and 12 the gates of which receive the signals of both the bit lines are different from each other. In this case, the transistor 12 the gate of which receives the signal from the high-potential bit line BL has a conductance higher than that of the transis-tor 11 the gate of which receives the signal from the low-potential bit line BL . Therefore, the speeds of extracting charges from the pair of data input/output lines DQ and DQ are different from each other, and the potential of the data input/output line DQ is decreased earlier than that of the data input/output line DQ. When the potential of the data input/output line DQ is further decreased and has a voltage lower than a threshold voltage V TH of the n-channel MOS transis-tor 11, the transistor 11 is set in a cutoff state, and the decrease in potential of the data input/output line DQ is stopped. Thus, data read out to the pair of bit lines is transmitted to the pair of data input/output lines. In a data reading operation, since a column selecting line CSL can be activated earlier than the signals SAN and SAP for respectively activating the n-channel side sense amplifier 9 and the p-channel side sense amplifier 10, the signals from the pair of bit lines and the signals from the pair of data input/output lines can be almost simultaneously amplified. Since signal transmission from the pair of bit lines to the pair of data input/output lines through a data reading path is rarely delayed, the data can be read out at a high speed. Fig. 5 is a timing chart in a data reading state, a signal of the word line WL rises first, and the same data reading operation as described in Fig. 4 is performed. When this reading operation is completed, a signal from the data writing control line WRT rises as a pulse. At the same time, the potentials of the pair of data input/output lines DQ and DQ are set by a write circuit (not shown). Fig. 5 shows a case wherein data having a level opposite to the read data is written, and the potentials of the pair of data input/output lines DQ and DQ are reversed to each other. At this time, since the signal from the signal line WRT is set to be "H" level, the data write transistors 13 and 14 are turned on. Therefore, the signal potential of the bit line BL set at "H" level is decreased to "L" level through the transistors 7 and 11, and the signal potential of the bit line BL set at "L" level is increased to "H" level through the transistors 8 and 12. The n-channel side sense amplifier 9 and the p-channel side sense amplifier 10 latch new written data. At this time, the transistor 11 is turned on, and the transistor 12 is turned off, thereby completing the data writing operation. Even when driving of the pair of data input/output lines DQ and DQ by a write circuit is stopped, the potential of the data input/output line DQ is decreased to "L" level, and the potential of the data input/output line DQ is held to be "H" level. Thus, the data writing operation is completed. In the data writing operation shown in the timing chart in Fig. 5, although data is written after a data reading operation is completed, a timing of the writing operation may be advanced, and the writing operation may be started before the data reading operation is completed. That is, only the writing operation is stated after the bit line sense amplifier is activated. In this embodiment, although data is read out while the data input/output line is precharged to V CC , the potential is not limited to the potential V CC , and the potential can be precharged to, e.g., 0.5·V CC . Fig. 6 is a circuit diagram showing an arrangement of a DRAM according to the second embodiment of the present invention. In the DRAM according to the first embodiment in Fig. 1, the column selecting MOS transistors 7 and 8, the data input/output line signal amplifying MOS transistors 11 and 12, and the data writing MOS transistors 13 and 14 are n-channel transistors, and one terminal of each of the data input/output line signal amplifying MOS transistors 11 and 12 is connected to the ground potential V SS. However, in a DRAM according to the second embodiment, p-channel MOS transistors are used in place of the above n-channel MOS transistors. That is, a column selecting p-channel MOS transistor 15 and a data input/output line signal amplifying p-channel MOS transistor 16 are connected in series between one data input/output line DQ of a pair of data input/output lines and a potential V CC , and a column selecting p-channel MOS transistor 17 and a data input/output line signal amplifying p-channel MOS transistor 18 are connected in series between the other data input/output line DQ and the power source potential V CC. The gates of both the column selecting transistors 15 and 17 are commonly connected to a column selecting line CSL which receives an "L"-level signal in an active state. The gate of the transistor 16 of the data input/output line signal amplifying transistors is connected to the bit line BL , and the gate of the transistor 18 is connected to the bit line BL. That is, a data input/output sense amplifier for amplifying a potential difference between the pair of data input/output lines in accordance with the signals from the bit lines B1 and BL consists of both the transistors 16 and 18. In this case, both the transistors 16 and 18 are driver transistors. A data writing p-channel MOS transistor 19 is connected between a common connection node A of the transistors 15 and 16 and the bit line BL, and a data write p-channel MOS transistor 20 is connected between a common connection node B of the transistors 17 and 18 and the bit line BL . The gates of both the data writing transistors 19 and 20 are connected to a data write control line WRT receiving an "L"-level signal in an active state and simultaneously ON/OFF-controlled by a signal from the signal line WRT . An operation of the DRAM with the above arrangement will be described with reference to the timing charts in Figs. 7 and 8. Fig. 7 is a timing chart in a data reading operation. A signal from a word line WL rises first, and a signal corresponding to data is read out to the pair of bit lines. Thereafter, a signal from a sense amplifier control line SAN for activating the n-channel side sense amplifier 9 and a signal from a sense amplifier control line SAP for activating the p-channel side sense amplifier 10 are sequentially activated, and a potential difference between the pair of bit lines is amplified by both the sense amplifiers. The potential from a signal of the column selecting line CSL is precharged to a potential V CC in advance, and the potential is decreased to a ground potential V SS after the signal from the word line WL rises. Therefore, charges are supplied from the power source potential VCC to the pair of data input/output lines which are precharged to the ground potential V SS by a means (not shown) through the series-connected transistors 15 and 17 and the series-connected transistors 16 and 18, respectively. The signals from the pair of bit lines are amplified by the bit line sense amplifiers. At the same time, the pair of data input/output lines have a potential difference due to a conductance difference between the transistors 16 and 18. Thus, the data read from the pair of bit lines are transmitted to the pair of data input/output lines. In this embodiment, since the column selecting line CSL can be activated earlier than the signals SAN and SAP for respectively activating the n-channel side sense amplifier 9 and the p-channel side sense amplifier 10 during a data reading operation, the signals from the pair of bit lines and the signals from the pair of data input/output lines can be almost simultaneously amplified. In this case, since signal transmission from the pair of bit lines to the pair of data input/output lines through a data reading path is rarely delayed, the data can be read at a high speed. Fig. 8 is a timing chart in a data writing operation. A signal from the word line WL rises first, and the same data reading operation as described in Fig. 7 is performed. When this reading operation is completed, a signal from the data writing control line WRT rises as a pulse, and at the same time, the potentials of the pair of data input/output lines DQ and DQ are set by a write circuit (not shown). In Fig. 8, data having a level opposite to that of the read data is written, and the potentials of the pair of data input/output lines DQ and DQ are reversed to each other. At this time, since the signal from the signal line WRT is set to be "L" Level, the data writing transistors 19 and 20 are tuned on, and the data of the of data input/output lines are transmitted to the pair of bit lines. The n-channel side sense amplifier 9 and the p-channel side sense amplifier 10 latch new written data. At this time, the transistor 18 is turned on, and the transistor 16 is turned off, thereby completing the data writing operation. Even when driving of the pair of data input/output lines DQ and DQ by the write circuit is stopped, the potential of the data input/output line DQ is decreased to "L" level, and the potential of the data input/output line is held to be "H" level. Thus, the data writing operation is completed. Fig. 9 is a circuit diagram showing an arrangement of a DRAM according to the third embodiment of the present invention. In the DRAM according to this embodiment, a load p-channel MOS transistor 21 is inserted between the node A and the power source potential V CC of the DRAM of the embodiment in Fig. 3, and the gate of the MOS transistor 21 is connected to the gate of the data input/output line signal amplifying n-channel MOS transistor 11, thereby constituting a CMOS inverter 22. In addition, a load p-channel MOS transistor 23 is inserted between the node B and the power source potential V CC , and the gate of the MOS transistor 23 is connected to the gate of the data input/output line signal amplifying n-channel MOS transistor 12, thereby constituting a CMOS inverter 24. In the DRAM according to the third embodiment, although the number of elements is increased by an increase in the load p-channel MOS transistors 21 and 23 compared with that of the embodiment in Fig. 3, the amplification of the pair of data input/output lines is advantageously increased. Fig. 10 is a circuit diagram showing an arrangement of a DRAM according to the fourth embodiment of the present invention. In the DRAM of this embodiment, in place of connecting one terminal of each of the n-channel transistors 11 and 12 to the ground potential V SS in the DRAM according to the third embodiment in Fig. 9, a through current control n-channel MOS transistor 25 is inserted between both the transistors 11 and 12 and the ground potential V SS and the gate of the transistor 25 is connected to a column selecting line CSL. In the DRAM according to this embodiment, when column selecting transistors 7 and 8 are turned on in response to a signal from the column selecting line CSL, the through current control transistor 25 on only the selected column is turned on, and through current control transistors 25 on non-selected columns are turned off. For this reason, the large number of non-selected data input/output line sense amplifiers can be prevented from a through current flow, and low power consumption can be achieved. Fig. 11 is a circuit diagram showing an arrangement of a DRAM according to the fifth embodiment of the present invention. In the DRAM of this embodiment, a load p-channel MOS transistor 26 is inserted between the node A and the power source potential V CC , and a load p-channel MOS transistor 27 is inserted between the node B and the power source potential V CC , in the first embodiment in Fig. 3. In addition, the gates of both the transistors 26 and 27 are commonly connected to the node B so as to add p-channel current mirror loads to the data input/output signal amplifying n-channel MOS transistors 11 and 12. In the DRAM according to this embodiment, although the number of elements is increased by an increase in the load p-channel MOS transistors 26 and 27 compared with the first embodiment in Fig. 3, the amplification of the pair of data input/output lines is advantageously increased. Fig. 12 is a circuit diagram showing an arrangement of a DRAM according to the sixth embodiment of the present invention. In the DRAM of this embodiment, in place of directly connecting one terminal of each of the channel MOS transistors 11 and 12 to the ground potential V SS in the DRAM according to fifth embodiment in Fig. 11, a through current control n-channel MOS transistor 25 is inserted between both the transistors 11 and 12 and the ground potential V SS , and the gate of the transistor 25 is connected to a column selecting line CSL. As in the fourth embodiment in Fig. 10, a large number of non-selected data input/output line sense amplifiers can be prevented from a through current flow. Fig. 13 is a circuit diagram showing an arrangement of a DRAM according to the seventh embodiment of the present invention. In the above embodiment in Fig. 11, the column selecting MOS transistors 7 and 8, the data input/output line signal amplifying MOS transistors 11 and 12, and the data write MOS transistors 13 and 14 are n-channel transistors, the current mirror loads of the MOS transistors 11 and 12 consist of the p-channel MOS transistors 26 and 27, and one terminal of each of the MOS transistors 11 and 12 is connected to the ground potential V SS . In the DRAM of the seventh embodiment, however opposite channel MOS transistors are used as the MOS transistors described in the fifth embodiment, respectively. That is, a column selecting p-channel MOS transistor 15 and a data input/output line signal amplifying p-channel MOS transistor 16 are connected in series between one data input/output line DQ and a power source potential V CC , and a column selecting p-channel MOS transistor 17 and a data input/output line signal amplifying p-channel MOS transistor 18 are connected in series between the other data input/output line DQ and the power source potential V CC . The gates of both the column selecting transistors 15 and 17 are connected to a column line CSL receiving a signal which is set to be "L" level in an active state, and the gate of the data input/output line signal amplifying transistor 16 is connected to the bit line BL , and the gate of the data input/output line signal amplifying transistor 18 is connected to the bit line BL. A load n-channel MOS transistor 28 is inserted between a node A and the ground potential V SS , and a load n-channel MOS transistor 29 is inserted between the node B and the ground potential V SS . The gates of both the transistors 28 and 29 are commonly connected to a node B. That is, a data input/output line sense amplifier for amplifying a potential difference between the pair of data input/ output lines in accordance with signals from the bit lines BL and BL consists of the p-channel MOS transistor 16 and 18 and the n-channel MOS transistors 28 and 29. A data write p-channel MOS transistor 19 is connected between the node A and the bit line BL, and a data write p-channel MOS transistor 20 is connected between the node B and the bit line BL . The gates of both the data write transistors 19 and 20 are connected to a data write control line WRT receiving a signal which is set to be "L" level in an active state. Fig. 14 is a circuit diagram showing an arrangement of a DRAM according to the eighth embodiment of the present invention. In the DRAM of this embodiment, in place of connecting one terminal of each of the p-channel MOS transistors 16 and 18 to the power source potential V CC in the DRAM of the above embodiment in Fig. 13, a through current control p-channel MOS transistor 30 is inserted between both the transistors 16 and 18 and the power source potential V CC , and the gate of the through current control p-channel MOS transistor 30 is connected to a column selecting line CSL . Therefore, as in the DRAM of the above embodiment in Fig. 10, a large number of non-selected data input/output line sense amplifiers can be prevented from a through current flow. In the DRAM of the above embodiments, although the signals from the pair of data input/output lines are amplified immediately when the signal from the sense amplifying the signals from the pair of bit lines. When a data input/output line sense amplifier (for example, consisting of the n-channel MOS transistors 11 and 12 in the embodiment in Fig. 3, consisting of the p-channel MOS transistors 16 and 18 in the embodiment in Fig. 6, and consisting of the two CMOS inverters 22 and 24 in the embodiment in Fig. 9, respectively) has a high sensitivity, the signals from the pair of data input/output lines can be started to be amplified before the signals from the pair of bit lines are amplified. That is, when a signal from a word line WL rises and a micro signal from a memory cell is transmitted to the pair of bit lines, the pair of data input/output lines may be immediately started to be operated so as to quickly amplify the signal output to the pair of data input/output lines. In this case, thereafter, the bit line sense amplifier relatively slowly amplifies the potential difference between the pair of bit lines. Fig. 15 is a circuit diagram showing an arrangement of a DRAM according to the ninth embodiment of the present invention. In the DRAMs of the above embodiments, although one data input/output line sense amplifier is arranged for each pair of bit lines, one data input/output line sense amplifier may be arranged in units of plural pairs of bit lines. In the DRAM of this embodiment, one data input/output line sense amplifier is arranged for every four pairs of bit lines. Referring to Fig. 15, four CMOS-S/A 41 correspond to the bit line sense amplifiers each of which consists of, e.g., the two n-channel transistors 3 and 4 and the p-channel MOS transistors 5 and 6 described in Fig. 3. A DQ S/A 42 in Fig. 15 corresponds to the bit line sense amplifier which consists of, e.g., the two n-channel MOS transistors 11 and 12 described in Fig. 3, and the DQ S/A 42 includes the data write n-channel MOS transistors 13 and 14. The four bit line sense amplifiers (CMOS S/A) 41 are connected between a pair of bit lines BL0 and BL0 to a pair of bit lines BL3 and BL3 , respectively, so as to be activated in accordance with signals from the sense amplifier control lines SAN and SAP. The four pairs of bit lines BL0 and BL0 to BL3 and BL3 are connected to the DQ S/A 42 through n-channel transistors 43 on the BL side and through n-channel transistors 44 on the BL side. The gates of the transistors 43 and 44 are commonly connected to each pair of bit lines, and four column selecting lines CSL0 to CSL3 are connected to the common gates. In addition, the output from an OR gate 45 receiving signals from the four column selecting lines CSL0 to CSL3 is supplied to the gates of the two column selecting n-channel MOS transistors 7 and 8 connected between the DQ S/A 42 and one of the pair of data input/output lines and between the DQ S/A 42 and the other of the pair of data input/output lines. In the DRAM with the above arrangement, any one of the signals from the four column selecting lines CSL0 to CSL3 is set to be "H" level, any one of the four pairs of transistors 43 and 44 is turned on, and any one of the four CMOS S/As 41 is selectively connected to the DQ S/A 42. At this time, the output of the OR gate 45 goes to "H" level so as to activate the DQ S/A 42. The DRAM of this embodiment is effectively used, when the area of the data input/output line sense amplifiers on a silicon chip is too large to arrange a data input/output line sense amplifier to each pair of bit lines, when a data input/output line sense amplifier is arranged for each pair of bit lines such that a chip area is increased exceeding an allowable range, or the like. Fig. 16 is a circuit diagram showing an arrangement of a DRAM according to the tenth embodiment of the present invention. In this embodiment, one data input/output line sense amplifier is arranged for each of plural pairs of bit lines. Referring to Fig. 16, four bit line sense amplifiers 41 are connected between a pair of bit lines BL0 and BL0 to a pair of bit lines BL3 and BL3 , respectively and activated in accordance with signals from sense amplifier control lines SAN and SAP. In addition, the four pairs of bit lines BL0 and BL0 to BL3 and BL3 are connected to the DQ S/A 42 through n-channel MOS transistors 46 on the BL side and through n-channel MOS transistors 47 on the BL side. The gates of the transistors 46 and 47 are commonly connected to each pair of bit lines, and four decode signal lines X0 to X3 are connected to the common gates, respectively. A column selecting line CSL is connected to the gates of two column selecting n-channel MOS transistors 7 and 8 respectively connected between the DQ S/A 42 and data input/output line DQ and between the DQ S/A 42 and data input/output line DQ . In the DRAM with the above arrangement, any one of signals from the four decode signal lines X0 to X3 goes to "H" level, any one of four pairs of transistors 46 and 47 are turned on such that any one of the four CMOS S/A 41 is selectively connected to the DQ S/A 42. In this case, the DQ S/A 42 is activated in accordance with a signal from the column CSL. As in the embodiment in Fig. 15, the DRAM of this embodiment is used, effectively when an area of the data input/output line sense amplifiers is too large to arrange a data input/output line sense amplifier for each pair of bit lines, when a data input/output line sense amplifier is arranged to each pair of bit lines such that a chip area is increased exceeding an allowable range. In embodiments in Figs. 15 and 16, one data input/output line sense amplifier is arranged to each of four pairs of bit lines. However, one data input/output line sense amplifier may be arranged in units of two, four, eight, or sixteen pairs of bit lines. In general, one data input/output sense amplifier can be arranged in units of 2 n (n is a natural number) pairs of bit lines. The present invention is not limited to the above described embodiments, and various modifications can be made. For example, in the above embodiments in Figs. 9 and 10, p-channel MOS transistors can be used as the column selecting transistors 7 and 8 and the data write transistors 13 and 14. Similarly, in the embodiments in Figs. 11 and 12, p-channel MOS transistors can be used as the column selecting transistors 7 and 8 and the data write transistors 13 and 14. In addition, in the embodiments in Figs. 11 and 12, the n-channel MOS transistors 11 and 12 are used as driver transistors of the data input/output line sense amplifiers, and the p-channel MOS transistors 26 and 27 are used as current mirror load transistors. However, in this case, p-channel MOS transistors may be used as the driver transistors, and n-channel MOS transistors may be used as the current mirror load transistors. As described above, according to the present invention, a dynamic type semiconductor memory device in which signal transmission on a data write path from a bit line to a data input/output line is rarely delayed, thereby obtaining a high-speed operation. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A dynamic type semiconductor memory device comprising: a plurality of memory cells (MC) each consisting of a MOS transistor (1) and a capacitor (2); plural pairs of bit lines each pair of which consist of first and second bit lines (BL, /BL) for supplying data to said plurality of memory cells (MC); a first sense amplifier (9, 10) arranged for each of said plural pairs of bit lines, for amplifying a bit line signal; a pair of data input/output lines consisting of first and second data input/output lines (DQ /DQ), for extracting data from said plural pairs of bit lines; a second sense amplifier arranged for each of said plural pairs of bit lines and consisting of first and second driver MOS transistors (11, 12) gates of which are connected to be cross-coupled to said first and second bit lines (BL, /BL), for extracting charges from said data input/output lines in a data reading operation and for amplifying data from the bit lines and transferring the amplified data to the data input/output lines; and first and second column selecting transistors (7, 8) which are inserted between said pair of data input/output lines and said second sense amplifier and gates of which are connected to a column selecting line (CSL); characterized by a first write transistor (13) one current path of which is connected to said first bit line (BL) and the other current path of which is connected to one output terminal of said second sense amplifier (11, 12), said first write transistor being turned on in a data writing operation; and a second write transistor (14) one current path of which is connected to said second bit line (/BL) and the other current path of which is connected to the other output terminal of said second sense amplifier (11, 12), said second write transistor being turned on in a data writing operation; wherein the write transistors are off in a read mode, and there is no direct connection between the bit lines and the outputs of the second sense amplifier in the read mode. The memory device according to claim 1, characterized in that said first sense amplifier (9, 10) for amplifying a bit line signal is a CMOS sense amplifier including a first flip-flop consisting of two n-channel MOS transistors (3, 4) and a second flip-flop consisting of two p-channel MOS transistors (5, 6), said first and second driver MOS transistors (11, 12) of said second sense amplifier for amplifying a data input/output line signal are n-channel MOS transistors, said first and second column selecting transistors (7, 8) are n-channel MOS transistors, and said first and second write transistors (13, 14) are n-channel MOS transistors. The memory device according to claim 1, characterized in that said first sense amplifier (9, 10) for amplifying a bit line signal is a CMOS sense amplifier including a first flip-flop consisting of two n-channel MOS transistors and a second flip-flop consisting of two p-channel MOS transistors, first and second driver MOS transistors of the second sense amplifier for amplifying a data input/output signal are p-channel MOS transistors, said column selecting transistor is a p-channel MOS transistor, and said first and second write transistors are p-channel MOS transistors. The dynamic type semiconductor memory device according to claim 1, wherein said second sense amplifier further comprises first and second load MOS transistors (21, 23). The memory device according to claim 4, characterized in that said first driver MOS transistor (11) and said first load MOS transistor (21) constitute a first CMOS inverter, and said second driver MOS transistor (12) and said second load MOS transistor (23) constitute a second CMOS inverter. The memory device according to claim 4, characterized in that a third MOS transistor (25) is arranged between said one current path of said first and second driver MOS transistors (11, 12) of said second sense amplifier for amplifying a data signal and a power source terminal. The memory device according to claim 1, characterized in that a first load MOS transistor (26) one current path of which is connected to one output terminal of said second sense amplifier and a gate of which is connected to the other output terminal of said second sense amplifier, and a second load MOS transistor (27) a gate and one current path of which are connected to the other output terminal of said second sense amplifier constitute a current mirror load. The memory device according to claim 7, characterized in that a third MOS transistor (25) is arranged between one current path of said first and second driver MOS transistors (11, 12) of said second sense amplifier for amplifying a data signal and a power source terminal. The memory device according to claim 7, characterized in that said first and second driver MOS transistors (11, 12) of said second sense amplifier for amplifying a data input/output line signal are n-channel MOS transistors, said first and second column selecting transistors (7, 8) are n-channel MOS transistors, said first and second write transistors (13, 14) are n-channel MOS transistors, and said first and second load MOS transistors (26, 27) are p-channel MOS transistors. The memory device according to claim 8, characterized in that said first and second driver MOS transistors (11, 12) of said second sense amplifier for amplifying a data input/output line signal are n-channel MOS transistors, said first and second column selecting transistors (7, 8) are n-channel MOS transistors, said first and second write transistors (13, 14) are n-channel MOS transistors, said first and second load MOS transistors (26, 27) are p-channel MOS transistors, and said third MOS transistor (25) is n-channel MOS transistor. The memory device according to claim 7, characterized in that said first and second driver MOS transistors (11, 12) of said second sense amplifier for amplifying a data input/output line signal are p-channel MOS transistors, said first and second column selecting transistors (7, 8) are p-channel MOS transistors, said first and second write transistors (13, 14) are p-channel MOS transistors, and said first and second load MOS transistors (26, 27) are n-channel MOS transistors. The memory device according to claim 8, characterized in that said first and second driver MOS transistors (11, 12) of said second sense amplifier for amplifying a data input/output line signal are p-channel MOS transistors, said first and second column selecting transistors (7, 8) are p-channel MOS transistors, said first and second write transistors (13, 14) are p-channel MOS transistors, said first and second load MOS transistors (26, 27) are n-channel MOS transistors, and said third MOS transistor (30) is p-channel MOS transistor. A dynamic type semiconductor memory device comprising: a plurality of memory cells (MC) each consisting of a MOS transistor (1) and a capacitor (2); plural pairs of bit lines each pair of which consist of first and second bit lines (BL, /BL) for supplying data to said plurality of memory cells (MC); a first sense amplifier (9, 10, 41) arranged for each of said plural pairs of bit lines, for amplifying a bit line signal; a pair of data input/output lines consisting of first and second data input/output lines (DQ, /DQ), for extracting data from said plural pairs of bit lines; a second sense amplifier arranged for each of said plural pairs of bit lines and consisting of first and second driver MOS transistors (11, 12, 42) gates of which are connected to be cross-coupled to said first and second bit lines (BL, /BL), for extracting charges from said data input/output lines in a data reading operation and for amplifying data from the bit lines and transferring the amplified data to the data input/output lines; and first and second column selecting transistors (7, 8) which are inserted between said pair of data input/output lines and said second sense amplifier; characterized by further comprising a gate circuit for forming an OR signal of signals of column selecting lines (CSL); gates of said first and second column selecting transistors being connected to an output of said gate circuit; a first write transistor (13) one current path of which is connected to said first bit line (BL) and the other current path of which is connected to one output terminal of said second sense amplifier (11, 12, 42), said first write transistor being turned on in a data writing operation; a second write transistor (14) one current path of which is connected to said second bit line (/BL) and the other current path of which is connected to the other output terminal of said second sense amplifier (11, 12, 42), said second write transistor being turned on in a data writing operation; and bit line pair selecting means (43, 44) which are inserted between said first sense amplifier (9, 10, 41) and said second sense amplifier (11, 12, 42), wherein the write transistors are off in a read mode, and there is no direct connection between the bit lines and the outputs of the second sense amplifier in the read mode. The memory device according to claim 1, wherein bit line selecting means (46, 47) are inserted between said first sense amplifier (9, 10, 41) and said second sense amplifier (11, 12, 42).

Inventors: OHSAWA TAKASHI, OHSAWA, TAKASHI, OHSAWA, TAKASHI, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: G11C11
IPC codes: G11C11