Semiconductor device having a high-frequency bipolar transistor

Abstract: In a high-frequency transistor a base electrode extends (16a) from at lease two portions of a transistor region (19) toward the outside, and the extension portions are connected to each other. Thus, a margin of a current density of a base electrode is not decreased. Moreover, the base electrode extends from at lease two portions of the transistor region, and at least one of the two extension portions extends on a resistor layer (18) connected to an emitter electrode (17a, 17b) and is connected to the other extension portion. For this reason, a collector electrode (14a), the emitter electrode (17a, 17b), and the base electrode (16a) can be formed at the same time, and a pattern for the base electrode (16) can be easily obtained.

Description: The present invention relates to a high-frequency semiconductor device, i.e., a high-frequency transistor, in which collector, emitter, and base electrodes are formed on a major surface of a substrate and, more particularly, to a high-frequency semiconductor device incorporated in an IC chip and used in a wide-band amplifier. Conventionally, a high-frequency transistor in which collector, emitter, and base electrodes are formed on a major surface of a substrate has a schematic two-dimensional pattern shown in Fig. 1. Fig. 2 is a sectional view showing the high-frequency transistor along a line II -II in Fig. 1. Referring to Fig. 2, reference numeral 1 denotes a p-type semiconductor substrate; 2, an n⁺-type buried collector layer; 3, an n-type collector layer; 4, an n⁺-type collector extraction layer; 4a, a collector electrode; 5, a p-type base layer; 6, a p⁺-type base layer; 6a, a base electrode; 7, an n⁺-type emitter layer; 7a, an emitter electrode; 8, a thin film resistor; and 9, a transistor region. The n⁺-type buried collector layer 2 is formed in the transistor region 9. The n⁺-type collector extraction layer 4 (continuous layer) reaching the major surface of the substrate is formed at both the ends of the n⁺-type buried collector layer 2. The p-type base layer 5 is formed in a surface region of the n-type collector layer 3 defined by the n⁺-type buried collector layer 2 and the n⁺-type collector extraction layer 4, and the p⁺-type base layers 6 and the n⁺-type emitter layers 7 are alternately formed one by one in the surface region of the base layer 5. The collector electrode (continuous layer) 4a is formed on the n⁺-type collector extraction layer 4. The base electrode (continuous layer) 6a is formed on the p⁺-type base layer 6. The emitter electrode (continuous layer) 7a is formed on the n⁺-type emitter layer 7. The emitter electrode 7a is connected to an external emitter electrode 7b through the emitter resistor 8 consisting of a thin film resistor. The base electrode 6a extends from only one end of the transistor region 9 in relation of a pattern of an electrode layer and a wiring layer. The collector electrode 4a extends from both the ends of the transistor region 9. In the pattern of the base electrode 6a extending from only one end of the transistor region 9, when the collector current is increased to increase a transition frequency, i.e., improve high-frequency characteristics, the base resistance is increased, and the operation is poor stable. That is, in order to increase the transition frequency, a pitch between the p⁺-type base layer 6 and the n⁺-type emitter layer 7 must be decreased. When the pitch between the p⁺-type base layer 6 and the n⁺-type emitter layer 7 is decreased, a capacity therebetween is decreased, thereby improving high-frequency characteristics. However, since electrode widths of the base electrode 6a and the emitter electrode 7a are also decreased, a current density of a current flowing through these electrodes is increased. As a result, a collector current is increased, and a base resistance is increased. Therefore, a circuit operation becomes unstable. In order to solve the above problem, a decrease in high-frequency output and in high-frequency gain must be considered. As described above, in the conventional semiconductor device, since a base electrode extends from only one end of a transistor region, as a collector current is increased, a base resistance is increased, and an operation becomes unstable. In order to solve the above problem, a high-frequency output and a high-frequency gain is necessarily decreased. It is, therefore, an object of the present invention to provide a semiconductor device capable of increasing a high-frequency gain and increasing a margin of a current density of a base electrode such that a base of a transistor region is stably driven. FR-A-2 011 431 furthermore discloses a semiconductor device comprising a transistor region in a semiconductor substrate, a collector region and a base region formed in said transistor region, a plurality of emitter regions, a base electrode which is formed on said base region and extends from at least two portions of said transistor region, the extension portions being connected to each other. According to the present invention, there is provided a semiconductor device having a high-frequency bipolar transistor comprising: a transistor region located in a semiconductor substrate; a collector region located in said transistor region; a base region located in said collector region; a plurality of elongated emitter regions and a plurality of elongated highly doped base contact regions, the base contact and emitter regions being alternately located parallel to each other in said base region in a direction perpendicular to the length direction of said emitter and base contact regions; a collector electrode, a part thereof being in physical contact with said collector region; an emitter electrode, a part thereof being in physical contact with said plurality of emitter regions; and a base electrode comprising elongated portions in physical contact with said plurality of highly doped base contact regions and a connecting portion located outside said transistor region on a first side of said transistor region and connecting said elongated portions together, and extensions departing from at least two of said elongated portions, extending outside said transistor region on a second side of said transistor region opposite to said first side, and being all connected together outside said transistor region on said second side of said transistor region. Preferably said collector electrode comprises at least two extensions departing from the part of said collector physically contacting said collector region and a connecting portion connecting said extensions together outside said transistor region on said first side; and said emitter electrode is a continuous layer and extends outside said transistor region on said second side of said transistor region. According to a particular aspect the present invention, said collector electrode comprises at least two extensions departing from the part of said collector physically contacting said collector region and a connecting portion connecting said extensions together outside said transistor region on said first side; and said emitter electrode includes a first emitter electrode portion in physical contact with several emitter regions of said plurality of emitter regions, said first emitter electrode portion being a continuous layer and extending outside said transistor region on said second side of said transistor region, and a second emitter electrode portion in physical contact with the emitter regions of said plurality of emitter regions not contacted by said first emitter electrode portion, said second emitter electrode portion being a continuous layer and extending outside said transistor region on said second side of said transistor region, wherein the extensions of said first and second emitter electrode portions are connected together outside said transistor region. According to another aspect of the present invention, said collector electrode comprises at least two extensions departing from the part of said collector physically contacting said collector region and a connecting portion connecting said extensions together outside said transistor region on said first side; and said emitter electrode includes a plurality of separate electrode portions, each of which being in physical contact with a single emitter region of said plurality of emitter regions and extending outside said transistor region on said second side of said transistor region, wherein the extensions of said separate electrode portions are all connected together outside said transistor region. According to the above arrangement, a base electrode extends from at least two sides of a transistor region, and the extension portions are connected to each other. A margin of a current density of a base electrode is not decreased. In addition, one of said extensions of said base electrode extends outside said transistor region above a resistor layer connected to said emitter electrode. For this reason, a collector electrode, the emitter electrode, and the base electrode can be formed at the same time, and a pattern for the base electrode can be easily obtained. Preferably said extensions of said base electrode depart from opposite ends of said transistor region, or depart from opposite ends and from the middle of said transistor region. Said resistor layer may consist of a polysilicon layer located on said substrate or of a diffusion doped layer located in said substrate. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a schematic plan view showing a pattern of a conventional semiconductor device; Fig. 2 is a sectional view showing the semiconductor device along a line II - II in Fig. 1; Fig. 3 is a plan view showing a pattern of a semiconductor device according to the first embodiment of the present invention; Fig. 4 is a sectional view showing the semiconductor device along a line IV - IV in Fig. 3; Figs. 5 and 6 are sectional views showing the semiconductor device along a line V - V in Fig. 3; Fig. 7 is a plan view showing a pattern of a semiconductor device according to the second embodiment of the present invention; Fig. 8 is a sectional view showing a sectional view showing the semiconductor device along a line VIII - VIII in Fig. 7; Fig. 9 is a plan view showing a pattern of a semiconductor device according to the third embodiment of the present invention; and Fig. 10 is a plan view showing a pattern of a semiconductor device according to the fourth embodiment of the present invention. An embodiment of the present invention will be described below with reference to the accompanying drawings. In this description, common reference numerals denote common parts throughout all the drawings, and descriptive repetitions will be omitted. Fig. 3 shows a schematic two-dimensional pattern of a semiconductor device according to the first embodiment of the present invention. Fig. 4 is a sectional view showing the semiconductor device along a line IV - IV in Fig. 3. Referring to Figs. 3 and 4, reference numeral 11 denotes a p-type semiconductor substrate; 12, an n⁺-type buried collector layer; 13, an n-type collector layer; 14, an n⁺-type collector extraction layer; 14a, a collector electrode; 15, a p-type base layer; 16, a p⁺-type base layer; 16a, a base electrode; 17, an n⁺-type emitter layer; 17a, an emitter electrode; 17b, an external emitter electrode; 18, a resistor layer for forming an emitter; and 19, a transistor region. The n⁺-type buried collector layer 12 is formed in the transistor region 19 on the semiconductor substrate 11. The n⁺-type collector extraction layer (continuous layer) 14 reaching the substrate major surface is formed at both the ends of the n⁺-type collector layer 12. The n-type collector layer 13 is formed in a region defined by the n⁺-type buried collector layer 12 and the n⁺-type collector extraction layer 14. The p-type base layer (base region) 15 is formed in the surface region of the n-type collector layer 13. A plurality of p⁺-type base layers (high-concentration base region) 16 and a plurality of n⁺-type emitter layers (emitter region) 17 are alternately formed one by one in the surface region of the p-type base layer 15. The collector electrode 14a, the base electrode 16a, and the emitter electrode 17a are formed on the n⁺-type collector extraction layer 14, the p⁺-type base layer 16, and n⁺-type emitter layer 17, respectively. The collector electrode 14a is formed on the n⁺-type collector extraction layer 14 and extends from both the ends of the transistor region 19 on one side of the transistor region. The extension portions are connected to each other. The collector electrode 14a forms a U-shaped pattern as a whole. The emitter electrode 17a is formed on the plurality of n⁺-type emitter layers 17 and extends from the corresponding emitter layers 17 to the direction opposite to the extending direction of the collector electrode 14a, i.e., on a side opposite to the side of the transistor region. The extension portions of the emitter electrode 17a are connected to each other. The emitter electrode 17a forms a comb-shaped pattern as a whole. The emitter electrodes 17a are connected to the external emitter electrode 17b through the emitter resistor layer 18. The base electrode 16a is formed on the plurality of p⁺-type base layers 16 and connected to each other on the side of the transistor region. The base electrode 16a extends from both the ends of the transistor region 19 on the opposite side, and these extension portions are connected to each other. That is, the base electrode 16a extending from the end of the transistor region 19 extends on the resistor layer 18, reaches the base electrode 16a extending from the other end of the transistor region 19, and is connected to the base electrode 16a extending from the other end. Figs. 5 and 6 are sectional views showing the semi-conductor device along a line V - V in Fig. 3. Fig. 5 shows the emitter resistor layer 18 consisting of a polysilicon layer. When a polysilicon layer is used as a resistor, for example, arsenic-doped polysilicon having a low sheet resistance is preferably used. In this case, a length X (Fig. 3) of the emitter resistor layer 18 can be sufficiently increased, and an interval between the emitter electrodes can be obtained such that the base electrode 16a extends on the emitter resistor layer 18 to be separated from the emitter electrodes 17a and 17b having a sufficient distance. Fig. 6 shows the emitter resistor layer 18 consisting of an impurity diffusion layer. In this case, when the resistance of the resistor layer 18 is decreased, the length X of the emitter resistor layer 18 can be sufficiently increased. A method of manufacturing the semiconductor device will be described below with reference to Figs. 3 and 4. By using a known method, the n⁺-type buried collector layer 12, the n⁺-type collector layer 13, an n⁺-type collector extraction layer 14, the p-type base layer 15, a p⁺-type base layer 16, and the n⁺-type emitter layer 17 are formed in the transistor region 19 on the semi-conductor substrate 11. Thereafter, a first insulating film is formed on the entire surface of the resultant structure. A pure polysilicon layer is formed on the first insulating film by a CVD (chemical vapor deposition) method to have a thickness of 500 nm (5,000 Å). Phosphorus (P) ions are implanted in the polysilicon layer at a dose of about 3.5 × 10¹⁵ [atoms/cm²] and an acceleration voltage of 40 [keV] to change the polysilicon layer into a conductive polysilicon layer having a sheet resistance of about 100 [Ω/□]. The polysilicon layer is selectively photoetched to leave a polysilicon layer serving as the emitter resistor layer 18 in a stripe shape on the first insulating film on the side of the extension portion side of the emitter electrode in the transistor region. Thereafter, a second insulating film is formed on the entire surface of the resultant structure to have a thickness of about 800 nm (8,000 Å). The first and second insulating films are selectively photoetched to form contact holes reaching the remaining polysilicon layer, the n⁺-type collector extraction layer 14, the p⁺-type base layer 16, and the n⁺-type emitter layer 17 are opened, respectively. An aluminum layer is formed on the entire surface by a CVD method and patterned to form an electrode layer and a wiring layer. At this time, the patterning for the aluminum layer is performed such that the extension portions of the base electrode 16a are connected to each other on the extension side of the collector electrode 14a from the transistor region 19 and that the extension portions extend from both the ends of the transistor region 19 on the opposite side. This patterning is performed such that extension portion of the base electrode 16a extending from the end of the transistor region 19 extends above the resistor layer 18 between the emitter electrodes 17a and 17b and is connected to the other extension portion of the base electrode 16a extending from the other end of the transistor region 19. In this case, a length X of the emitter resistor layer 18 is set to be sufficiently long, and the extension portion of the base electrode 16a can easily extend between the emitter electrodes 17a and 17b without contacting these emitter electrodes. In this case, a resistance of the emitter resistor layer 18 can be adjusted by increasing a width Y of the emitter resistor layer 18. More specifically, the length X of the resistor layer 18 consisting of the polysilicon layer must be 10 µm or more such that the base electrode 16a on the resistor layer 18 can easily extend. A resistance of the emitter resistor layer 18 is preferably about 20 Ω. For this reason, the length X of the resistor layer 18 consisting of, e.g., a polysilicon layer is set to be about 20 µm, and the width Y (Fig. 3) of the resistor layer 18 is set to be 100 µm. When the resistance of the emitter resistor layer 18 must be set to be 10 Ω or less, an arsenic-doped silicon layer is used as a resistor member. In this case, the sheet resistance is to be about 30 [Ω/□], and the demand can be satisfied. With the above arrangement according to this embodiment, the base electrode 16a extends from both the ends of the transistor region 19. Even when a pitch between the p⁺-type base layer 16 and the n⁺-type emitter layer 17 is decreased to achieve an increase in high-frequency output and in high-frequency gain, a margin of a current density of the base electrode is not decreased. More specifically, conventionally, when the high-frequency output and the high-frequency gain are sufficiently increased, the base current density is to be 6 x 10⁴ to 8 x 10⁴ [A/cm²]. According to the present invention, the base current density is decreased to be 3 x 10⁴ to 4 X 10⁴ [A/cm²], and a decrease in margin of the current density can be prevented. In the transistor, when the decrease in margin of the current density is prevented to stably drive the base, a concentration of the collector current can be avoided. Therefore, breakdown of the transistor by Joule heat can be reduced. Fig. 7 shows a schematic two-dimensional pattern of a semiconductor device according to the second embodiment of the present invention. Fig. 8 is a sectional view showing the semiconductor device along a line VIII - VIII in Fig. 7. An n⁺-type buried collector layer 12 is formed in a transistor region 19 on a semiconductor substrate 11. An N⁺-type collector extraction layer (continuous layer) 14 reaching the substrate major surface at the center and both the ends of the n⁺-type buried collector layer 12. N-type collector layers 13 are formed in regions respectively defined by the n⁺-type buried collector layer 12 and the n⁺-type collector extraction layer 14 located at the center and both the ends of the collector layer 12. A p-type base layer (base region) 15 is formed in the surface region of each of the n-type collector layers 13. A plurality of p⁺-type base layers (high-frequency base region) 16 and a plurality of n⁺-type emitter layers (emitter region) 17 are alternately formed one by one. A collector electrode 14a, a base electrode 16a, and emitter electrode 17a are formed on the n⁺-type collector extraction layer 14, the p⁺-type base layer 16, and the n⁺-type emitter layer 17, respectively. The collector electrode 14a is formed on the n⁺-type collector extraction layer 14 located at the center and both the ends of the transistor region 19, and the collector electrode 14a extends from the center and both the ends of the transistor region 19 on one side of the transistor region. These extension portions are connected to each other. The collector electrode 14a has an E-shaped pattern as a whole. The emitter electrodes 17a on the emitter layers 17 in each of the n-type collector layers 13 are formed on the n⁺-type emitter layers 17 and extend in a direction opposite to the extension direction of the collector electrode 14a, i.e., a side opposite to the side of the transistor region. The extension portions are connected to each other. The extension portions of the emitter electrode extending from the emitter layers 17 in the n-type collector layers 13 are commonly connected to the external emitter electrode 17b through the corresponding emitter layers 18. The base electrode 16a is formed on the plurality of p⁺-type base layers 16, and the extension portions of the base electrode 16a are connected to each other on the side of the transistor region and extend from the center and both the ends of the transistor region 19 to the other side. The extension portions are connected to each other. That is, the base electrode 16a extending from the end of the transistor 19 extends above the two emitter resistor layers 18 and is connected to the extension portions of the base electrode 16a extending from the center and the other end of the transistor region 19. According to the arrangement of the embodiment, the base electrode 16a extends from at least three portions of the transistor region 19, i.e., the center and both the ends of the transistor region 19. The extension portion of the base electrode 16a extending from one end of the transistor region 19 extends on the emitter resistor layer 18 and is connected to extension portions of the base electrode 16a extending from the center and the other end of the transistor 19. Therefore, the same effect as described in the first embodiment (Figs. 3 and 4) can be obtained. Fig. 9 shows a schematic two-dimensional pattern of a semiconductor device according to the third embodiment of the present invention. According to this embodiment, a plurality of emitter resistor layers 18 are formed in correspondence with a plurality of n⁺-type emitter layers 17, and a plurality of emitter electrodes 17a formed on the plurality of n⁺-type emitter layers 17 are commonly connected to an external emitter electrode 17b through the corresponding emitter resistor layers 18. In this case, an extension portion of base electrode 16a extending from one end of a transistor 19 extends on all the emitter resistor layers 18 and is connected to an extension of base electrode 16a extending from the other end of the transistor 19. Therefore, the same effect as described in the first embodiment (Figs. 3 and 4) can be obtained. Note that, in this embodiment, since all the emitter electrodes 17a are commonly connected to the external emitter electrode 17b, no emitter electrode 17a extends on one side of the transistor region, and emitter electrodes 17a are not connected to each other on this side. The remaining description of the third embodiment is substantially the same as that of the first embodiment, and a description thereof will be omitted. Fig. 10 shows a schematic two-dimensional pattern of a semiconductor device according to the fourth embodiment of the present invention. In this embodiment, a plurality of transistors used in the first embodiment (Figs. 3 and 4) are formed in parallel with each other. The same effect as described in the first embodiment (Figs. 3 and 4) can be obtained, as a matter of course. As described above, according to the semiconductor device of the present invention, the following effect can be performed. A base electrode formed on a plurality of p⁺-type base layers extends from at least two portions of a transistor region, and the extension portions are connected to each other. For this reason, even when a collector current is increased, the base resistance of the base electrode is not increased, a stable operation can be performed. Therefore, the base of the transistor region can be stably driven, and a high-frequency output and a high-frequency gain can be increased. In addition, an increase in margin of a current density of the base electrode can be achieved.

Claims: A semiconductor device having a high-frequency bipolar transistor comprising: a transistor region (19) located in a semiconductor substrate (11); a collector region (12, 13, 14) located in said transistor region; a base region (15) located in said collector region; a plurality of elongated emitter regions (17) and a plurality of elongated highly doped base contact regions (16), the base contact and emitter regions being alternately located parallel to each other in said base region in a direction perpendicular to the length direction of said emitter and base contact regions; a collector electrode (14a), a part thereof being in physical contact with said collector region; an emitter electrode (17a), a part thereof being in physical contact with said plurality of emitter regions; and a base electrode (16a) comprising elongated portions in physical contact with said plurality of highly doped base contact regions (16) and a connecting portion located outside said transistor region on a first side of said transistor region and connecting said elongated portions together, and extensions departing from at least two of said elongated portions, extending outside said transistor region on a second side of said transistor region opposite to said first side, and being all connected together outside said transistor region on said second side of said transistor region. A semiconductor device according to claim 1, characterized in that said collector electrode (14a) comprises at least two extensions departing from the part of said collector physically contacting said collector region and a connecting portion connecting said extensions together outside said transistor region on said first side; and in that said emitter electrode (17a) is a continuous layer and extends outside said transistor region on said second side of said transistor region. A semiconductor device according to claim 2, characterized in that one of said extensions of said base electrode (16a) extends outside said transistor region above a resistor layer (18) connected to said emitter electrode. A semiconductor device according to claim 1, characterized in that said extensions of said base electrode (16a) depart from opposite ends of said transistor region. A semiconductor device according to claim 1, characterized in that said extensions of said base electrode (16a) depart from opposite ends and from the middle of said transistor region. A semiconductor device according to claim 3, characterized in that said resistor layer (18) consists of a polysilicon layer located on said substrate (11). A semiconductor device according to claim 3, characterized in that said resistor layer (18) consists of a diffusion doped layer located in said substrate (11). A semiconductor device according to claim 1, characterized in that said collector electrode (14a) comprises at least two extensions departing from the part of said collector physically contacting said collector region and a connecting portion connecting said extensions together outside said transistor region on said first side; and in that said emitter electrode (17a) includes a first emitter electrode portion in physical contact with several emitter regions of said plurality of emitter regions, said first emitter electrode portion being a continuous layer and extending outside said transistor region on said second side of said transistor region, and a second emitter electrode portion in physical contact with the emitter regions of said plurality of emitter regions not contacted by said first emitter electrode portion, said second emitter electrode portion being a continuous layer and extending outside said transistor region on said second side of said transistor region, wherein the extensions of said first and second emitter electrode portions are connected together outside said transistor region. A semiconductor device according to claim 1, characterized in that said collector electrode (14a) comprises at least two extensions departing from the part of said collector physically contacting said collector region and a connecting portion connecting said extensions together outside said transistor region on said first side; and in that said emitter electrode (17a) includes a plurality of separate electrode portions, each of which being in physical contact with a single emitter region of said plurality of emitter regions and extending outside said transistor region on said second side of said transistor region, wherein the extensions of said separate electrode portions are all connected together outside said transistor region.

Inventors: NODA NOBURO, NODA, NOBURO, NODA, NOBURO, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: H01L29
IPC codes: H01L29, H01L21