Three-phase PWM signal generating device for inverters

Abstract: In an inverter in which six switching elements (13u-13z) of an inverter main circuit (10) is controlled to be turned on and off under a switching pattern in which a voltage space vector composed of adjacent two of six fundamental voltage vectors out of phase from one another by an electrical angle of π/3 and a zero vector figures a circular locus so that a three-phase substantially sinusoidal voltage is obtained, a three-phase PWM signal generating device includes a circuit (33) in which two switching patterns of the same kind are formed before and after the formation of the switching pattern corresponding to the zero vector, respectively, and a circuit (30) in which when the magnitude of the command voltage vector exceeds the region of a circular locus figured by the fundamental voltage vector, the command voltage vector is converted to a new command voltage vector so as to correspond to the region.

Description: This invention relates generally to an inverter device having a plurality of switching elements turned on and off so that a dc voltage is converted to a three-phase ac voltage, and more particularly to a pulse width modulation (PWM) signal generating device for the inverter device provided for controlling on and off operations of each switching element in accordance with a time ratio so that a substantially sinusoidal output voltage is obtained. One conventional pulse width modulation (PWM) signal generating circuit in an inverter device will be described. FIG. 8 schematically illustrates an arrangement of an inverter main circuit 10 of the inverter device. Six switching elements 13u, 13v, 13w, 13x, 13y and 13z are bridge-connected between main circuit bus lines 11 and 12 as well known in the art. Since either of the upper and the lower switching elements of each of the three arms is turned on, these three switches turned on are referred to as reference symbols Sa, Sb and Sc respectively. The number of switching patterns is thus obtained as 2 3 =8. Each phase voltage is ±V/2 with respect to a virtual neutral point. Where voltage space vectors correspond to three-phase instantaneous voltages in consideration of phase differences among the phases, each of the switching elements Sa, Sb, Sc is represented as "1" when the positive switching element 13u, 13v or 13w in each phase is turned on. Each of the switching elements Sa, Sb, Sc is represented as "0" when the negative switching elements 13x, 13y or 13z in each phase is turned on. Accordingly, each switching pattern can be represented by substituting "1" or "0" for each of Sa, Sb, Sc. As shown by solid lines in FIG. 9, these switching patterns can be represented as six fundamental voltage vectors out of phase from one another by an electrical angle of 2π/6 and two zero vectors (0, 0, 0) and (1, 1, 1). FIG. 10 illustrates the three-phase PWM signal generating device for on-off control of the switching elements in the above-described inverter device. Phase command value classification means 14 classifies a phase command value * into unit regions obtained by dividing an electrical angle of 2π/6 into twelve equal parts, for example and calculates an lead angle in the unit region into which the phase command value is classified. The result of classification and the calculated lead angle are produced as 4-bit information. Switching pattern determining means 15 is provided for determining the switching patterns corresponding to two kinds of fundamental voltage vectors (voltage space vectors) nearest to the unit region to which the phase command value * classified by the phase command value classification means 14 belongs and the switching pattern corresponding to the zero vector. The fundamental voltage vectors are out of phase from each other by an electrical angle of π/3. The switching pattern determining means 15 further determines a sequence that these determined switching patterns are delivered to the base terminals of the switching elements 13u-13z. Generally, two kinds of fundamental voltage vectors of the phases nearest to the phase command value * as exemplified in FIG. 9 and the vectors (1, 0, 0), (1, 1, 0) and the zero vector are specified as the switching patterns in the example of FIG. 9. One of two kinds of zero vectors (1, 1, 1) and (0, 0, 0) is selected so that the number of the switching operations becomes the smallest in consideration of the previous switching patterns. The voltage space vectors which can be outputted must lie inside a hexagon formed by linking the points of six fundamental voltage vectors in FIG. 9 where the voltage space vectors each having a predetermined magnitude and phase are outputted by controlling the fundamental voltage vectors out of phase from each other by an electrical angle of 2π/6 and the zero vector in accordance with the time ratio. Accordingly, the region of the modulation to the sinusoidal waves performed by the above-mentioned control of the fundamental voltage vectors and zero vector is limited to the inside of an inscribed circle of the hexagon. Consequently, polar coordinates can be employed to realize optional voltage space vectors in the limit region and the region of an electrical angle of π/6 can be described in consideration of the symmetry. FIG. 11 shows enlarged fundamental voltage vectors (1, 0, 0), (1, 1, 0) and the zero vector. In order that the voltage space vector corresponding to a command voltage vector including the phase command value * and voltage command value V* is outputted, it is obvious that the following expression needs to be satisfied by the geometric analysis shown in FIG. 21: Vsin(π/6-) : Vsin(π/6+) : 1-V{sin(π/6-)+sin(π/6+)} =t 1 : t 2 : t 0 where t 1 , t 2 and t 0 are output times of the fundamental voltage vectors (1, 0, 0), (1, 1, 0) and the zero vector and  is a lead angle of the phase command value * in the unit region to which the phase command value * belongs. Holding time calculating means 16 is provided for obtaining the output times t 1 , t 2 as shown in FIG. 10. More specifically, data of the lead angle  is supplied to ROM tables 17 and 18 from the phase command classification means 14 so that the value of sin(π/6+) corresponding to the supplied lead angle is obtained. The holding time t 1 of the switching pattern corresponding to the fundamental voltage vector (1, 0, 0) is obtained by multiplying one control period T SW by the voltage command value V* and further by the value of sin(π/6-) . In the same way, the holding time t 2 of the switching pattern corresponding to the fundamental voltage vector (1, 1, 0) is obtained by multiplying one control period T SW by the voltage command value V* and further by the value of sin(π/6+) . The holding time t 0 of the switching pattern corresponding to the zero vector is obtained by subtracting these holding periods t 1 and t 2 from the one control period T SW . One control period refers to a period in which the switching patterns corresponding to the two kinds of fundamental voltage vectors and the zero vector respectively are sequentially produced once. Timing means 19 comprises a presettable counter 20, a switch 21 and a D-type flip flop 22. The presettable counter 20 has a data input terminal DATA to which data of each of the holding times t 0 , t 1 , t 2 is inputted in accordance with the switching of the switch 21. The presettable counter 20 also has a clock terminal CK to which clock signals fck are inputted. The switch 21 is switched to an output terminal of the holding time corresponding to the switching pattern determined by the switching pattern determining means 15 when timing of each of the holding times supplied to the presettable counter 20 is completed and then, the subsequent holding time data is inputted to the data input terminal DATA. The flip flop 22 holds the formation state of the corresponding switching pattern until the timing of each holding time is completed, whereby the switching elements 13u-13z of the inverter device are desirably controlled to be turned on and off. FIG. 12 illustrates a locus of a vector ψ representative of a magnetic flux induced in a three-phase induction motor M as a three-phase load when an output of the inverter main circuit 10 controlled by the above-described PWM signal generating device is supplied to the motor M. Reference symbol ψ' designates a mean locus and figures a circular orbit. The magnetic flux vector ψ is represented as the time integral of the voltage space vector. Since each fundamental voltage vector has a predetermined value, the direction of the magnetic flux vector ψ is the same as that of each fundamental voltage vector and the magnitude of the vector ψ is proportional to the holding time of each fundamental voltage vector. A manner of determining the output sequence of the switching patterns by the switching pattern determining means 15 will now be described. The output holding times t 1 , t 2 of the switching pattern corresponding to the two fundamental voltage vectors determined by the switching pattern determining means 15 are calculated by the holding time calculating circuit 16. The output sequence of the switching patterns is so determined that the zero vector is interposed between longer vectors, that is, the zero vector is positioned at the start or the end of the vector with the longer holding time in one control period T SW . Generally, since the holding time of the fundamental voltage vector with the phase nearest to the phase command value * becomes longer because of the method of calculating the holding time, the switching pattern corresponding to the fundamental voltage vector with the longer holding time can be determined at the stage of the classification by the phase command value classification means 14. FIG. 12 shows the case where the phase command value * is in the condition shown in FIG. 11. The phase command value * when t 1 <t 2 is nearest to the fundamental voltage vector (1, 1, 0) where the holding times of the switching patterns corresponding to the fundamental voltage vectors (1, 0, 0), (1, 1, 0) and the zero vector are represented as t 1 , t 2 , t 0 , respectively. Accordingly, the switch 21 is switched so that the sequence of ...t 1 , t 2 , t 0 , t 0 , t 2 , t 1 ... is repeated. The above example will be described in more detail. When the switching pattern corresponding to the fundamental voltage vector (1, 0, 0) is held for the time t 1 in the previous control period, the switching pattern corresponding to the fundamental voltage vector (1, 0, 0) is held for the time t 1 in the following control period and then, the switching pattern corresponding to the fundamental voltage vector (1, 1, 0) is held for the time t 2 and last, the switching pattern corresponding to the zero vector (1, 1, 1) is held for the time t 0 . In the above-described inverter device, the waveform distortion of output voltage of the inverter device to which the voltage command value V* is supplied is increased since the magnitude of the inverter output voltage is √3/2 times larger than the maximum PWM controllable voltage. More specifically, the principle in this control system is that a carrier voltage signal Va and a sinusoidal wave voltage signal Vb are compared and a PWM signal is obtained in accordance with the magnitude of each signal as shown in FIG. 13. When the amplitude of the sinusoidal wave voltage signal is excessively increased in this control system, the amplitude in the vicinity of its peak cannot be accurately converted to its corresponding time length, resulting in an increase in the waveform distortion. Therefore, an object of the present invention is to provide a PWM signal generating device for an inverter device wherein the distortion of the inverter output voltage waveform near its peak can be improved when the voltage command value is excessively large. The present invention provides a three-phase PWM signal generating device for an inverter device comprising an inverter main circuit including six bridge-connected switching elements which can be turned on and off in predetermined patterns so that a dc voltage supplied from an external source is converted to a three-phase ac approximately sinusoidal voltage, the three-phase PWM signal generating device connected to the inverter main circuit for generating switching pattern signals for turning on and off the switching elements in order to provide six kinds of switching patterns corresponding to six fundamental voltage vectors out of phase from one another by an electrical angle of 2π/6, respectively, and switching patterns corresponding to a zero vector corresponding to an "on" or "off" state of substantially all the switching elements so that the inverter main circuit generates an approximately sinusoidal output voltage waveform, the three-phase PWM signal generating device comprising switching pattern determining means for determining a holding time of each of the six kinds of switching patterns and an output sequence of the switching patterns, based on a command voltage vector including a supplied voltage command value and a supplied phase command value, characterized by command voltage vector substituting means for supplying to the switching pattern determining means a first command voltage vector, instead of a command voltage vector received from an external source, when the command voltage value of the received command voltage vector exceeds a PWM control region where the fundamental voltage vector is a radius, the first command voltage vector being nearest to the limit of the PWM control region. In accordance with the above-described arrangement, even when an excessively large voltage command value is supplied, it can be replaced by a new command voltage vector with the maximum PWM controlled voltage. Since the switching pattern signals are generated in accordance with the replaced voltage vector, the waveform distortion near the peak of the ac voltage can be prevented. The invention will be described, merely by way of example, with reference to the accompanying drawings, in which: FIG. 1 is a block diagram of the three-phase PWM signal generating device of a first embodiment of the invention; FIG. 2 is a flowchart for explaining the operation of command voltage vector replacing means in the first embodiment; FIG. 3 shows the unit regions for explaining the determination of the region by the command voltage vector replacing means; FIG. 4 is a vector diagram for explaining the operation of the three-phase PWM signal generating device; FIG. 5 is a connection diagram of the command voltage vector replacing means in a second embodiment of the present invention; FIG. 6 is a waveform chart showing three-phase approximate sinusoidal waveforms in the prior art; FIG. 7 is a waveform chart showing three-phase approximate sinusoidal waveforms in the first embodiment of the present invention; FIG. 8 is a connection diagram of a three-phase inverter main circuit; FIG. 9 is a diagram of fundamental voltage vectors for explaining the operation of generating the three-phase PWM signals; FIG. 10 is a block diagram of a conventional three-phase PWM signal generating device; FIG. 11 is a vector diagram for explaining the sinusoidal waveform approximating operation of the three-phase PWM signal generating device in FIG. 10; FIG. 12 shows a locus of the magnetic flux vector obtained from the sinusoidal waveform approximation by the conventional device; and FIG. 13 is a voltage waveform chart for explaining the principle of the PWM signal generation. A first embodiment of the present invention will be described with reference to FIGS. 1 to 4. The arrangement of the PWM signal generating device shown in FIG. 1 is substantially the same as that shown in FIG. 10 except for addition of command voltage vector substitution means 30 provided between the signal delivering portion for the switching pattern holding times t 1 , t 2 and t 0 and the switch 21 for distributing the switching pattern holding times. Further, these holding times t 1 , t 2 , t 0 are calculated using the equation (1). When supplied with the switching pattern holding times t 1 , t 2 , t 0 , the command voltage vector substitution means 30 performs a calculation in accordance with a program which will be described later so that actual holding times t 11 , t 22 and t 00 are supplied to the timing means 19. The calculation is performed in accordance with a substitution program by the command voltage vector substitution means 30 when a particularly high voltage command value V* is supplied and the holding time t 0 of the zero vector takes a negative value. The operation of the above-described arrangement will be described. Referring to FIG. 3, the command voltage vector V* can belong to one of the region R 1 or regular hexagonal PWM controlled region as shown in FIG. 9, the regions R 2 perpendicular to respective sides of the regular hexagon outside the region R 1 , and the regions R 3 which are the other region outside the region R 1 . Referring to FIG. 11, the PWM signal generating device operates as follows when the command voltage vector V corresponding to the phase command value * and the voltage command value V* belongs to the region R 1 or the PWM controlled region. The phase command value classification means 14 classifies the unit region in accordance with the phase command value * at that time. The phase command value classification means 14 delivers the result of classification to the switching pattern determining means 15 and further delivers data of the lead angle  to the holding time calculating circuit 16. The holding time calculating circuit 16 calculates the time ratio represented by the equation (1) in the manner as described above and supplies the command voltage vector substitution means 30 with the holding times t 1 , t 2 , t 0 of the switching patterns corresponding to the fundamental voltage vectors and zero vector. Upon receipt of the holding times, the command voltage vector substitution means 30 starts the program shown in FIG. 2. First, the holding time t 0 of the switching pattern corresponding to the zero vector whose data is supplied thereto from the holding time calculating circuit 16 is divided by 2 and stores data of the obtained value as a comparison value A (step S1). The command voltage vector substitution means 30 determines whether the obtained comparison value A is zero or above zero (step S2). In this case the command voltage vector V is within the PWM controlled region as described above, so that the holding time t 0 is a positive value. Accordingly, the command voltage vector substitution means 30 determines that the comparison value A is zero or above zero. Actual holding times t 11 , t 22 , t 00 are determined at step S3. The value obtained by doubling the comparison value A, that is, the value equal to t 0 is substituted for the holding time t 00 . The holding times t 1 , t 2 are substituted for the actual holding times t 11 , t 22 respectively. In this case, consequently, the holding times from the holding time calculating circuit 16 are delivered as the actual holding times without any change. The PWM signal generating device operates as follows when the command voltage vector V is in the region R 2 , that is, outside the PWM controlled region. When the holding time calculating circuit 16 calculates the holding times t 0 , t 1 , t 2 in accordance with the equation (1) in the same manner as described above, the holding time t 0 of the switching pattern corresponding to the zero vector takes a negative value. The broken line ℓ in FIG. 4 shows a locus of the command voltage vector V in this case. FIG. 4 shows the case where the command voltage vector V has been determined to be in the region of the phase of π/6 containing the fundamental voltage vector (1, 0, 0). As obvious from comparison of FIGS. 4 and 11, the holding time t 0 takes a negative value when it is calculated in accordance with the time ratio shown by the equation (1). When supplied with the negative holding time t 0 , the command voltage vector substitution means 30 determines at step S2 that the comparison value A is not zero nor above zero and further that the comparison value A belongs to either the region R 2 or R 3 , advancing to step S4. The command voltage vector substitution means 30 adds the comparison value A to the holding time t 2 supplied from the holding time calculating circuit 16 to obtain a comparison value B. The comparison value B is smaller than the holding time t 2 since the comparison value A is negative. The command voltage vector substitution means 30 determines whether or not the comparison value B is zero or above zero at step S5. Since the comparison value is positive, the substitution means 30 determines that the comparison value B is zero or above zero, advancing to step S6. Consequently, based on the comparison value B, it is determined at step S5 that the command voltage vector V is in the region R 2 (FIG. 3). At step S6, the comparison value B is substituted for the actual holding time t 22 , the addition of t 1 and the comparison value A is substituted for the holding time t 11 and zero is substituted for the holding time t 00 . Consequently, the command voltage vector V is replaced by a compensated command voltage vector V' (FIG. 4). In the physical phase of the above-described process, the value t 0 /2 is subtracted from each of the holding times t 1 , t 2 such that the command voltage vector V is transferred to the point P intersecting a perpendicular on the side m defining the limit of the PWM controlled region, whereby the command voltage vector V is replaced by the command voltage vector V' nearest to the maximum PWM controlled value. When it is determined at step S5 that the comparison value B is not zero nor above zero or when the command voltage vector V is in the region R 3 , the control period T SW is substituted for the holding time t 22 and zero is substituted for both holding times t 11 and t 00 at step S7. Consequently, the command voltage vector V is replaced by the nearest command voltage vector V' (not shown) by the substitution of all the fundamental vectors when the command voltage vector is in the region R 3 . Consequently, when the command voltage vector V shown in FIG. 4 is given, it is replaced by the command voltage vector V' nearest to the limit of the PWM controlled region, which is delivered to the inverter device so that the output voltage with the minimum waveform distortion near the sinusoidal waveform peak can be obtained. FIG. 5 illustrates a second embodiment of the present invention. The command voltage vector substitution means in this embodiment is composed of a logic circuit so as to perform a part of the function of the holding time calculating circuit 16 and the function of the command voltage vector substitution means 30 in the first embodiment as shown in FIG. 1. Each input data is processed as parallel 10-bit digital data. Referring to FIG. 5, an adder 31 adds the holding times t 1 and t 2 and supplies the obtained value to a subtracter 32 as a subtraction value. The subtracter 32 subtracts the subtraction value from the adder 31 from the control period T SW and delivers the obtained value to one input terminals of AND circuits 33 and 34 respectively. The subtracter 32 has a code determination terminal CY1 from which terminal a level "H" determination signal is delivered when the result of subtraction takes a negative value. The determination signal is supplied to the other input terminal of the AND circuit 33 and the other input terminal of the AND circuit 33 via an inverting circuit 35. An output of the AND circuit 33 is an actual holding time t 00 of the switching pattern corresponding to the zero vector. A subtracter 36 is supplied with the output of the AND circuit 33 and with the subtraction value via a divider 37 dividing the output of the AND circuit 33 into two equal parts. The subtracter 36 delivers the result of subtraction to an adder 38. The adder 38 adds the output of the subtracter 36 and the holding time t 1 and delivers the result of addition. An adder 39 adds the output of the divider 37 and the holding time t 2 and delivers the result of addition to an AND circuit 40. The adder 39 has a code determination terminal CY2 and delivers a level "L" determination signal to the other input terminal of the AND circuit 40 via an inverting circuit 41 when the result of addition takes a negative value. The output of the AND circuit 40 is an actual holding time t 22 . A change-over switch 42 is provided so that the output of the adder 38 is usually utilized for the actual holding time t 11 and the control period T SW is utilized for the holding time t 11 when the level "L" determination signal is produced from the adder 39. In operation, when the command voltage vector V is in the region R 1 , the subtracter 32 operates to subtract the result of addition (t 1 +t 2 ) from the adder 31 from the control period T SW . The determination signal is at the level "L" since the result of subtraction t 0 (=T SW -t 1 -t 2 ) is not negative. As a result, the output of the AND circuit 34, that is, the result of subtraction t 0 by the subtracter 32 is delivered as the holding time t 00 . In this case the output of the AND circuit 33 is cut off since the determination signal generated by the subtracter 32 is at the level "L" and accordingly, the input to the adders 38, 39 is zero. The output t 2 (t 2 >0) of the adder 39 is delivered as the holding time t 22 via the AND circuit 40. Further, the output t 1 of the AND circuit 38 is delivered to the change-over switch 32. Since the determination signal from the AND circuit 39 is at the level "L," the output t 1 is delivered as the holding time t 11 from the change-over switch 42. When the command voltage vector V is in the region R 2 , the result of subtraction by the subtracter 32 takes a negative value. Consequently, the output of the AND circuit 34 is cut off and the holding time t 00 of the switching pattern corresponding to the zero vector is zero. The negative result of subtraction (t 0 ) is delivered from the AND circuit 33. As a result, the adder 38 delivers the result of addition of t 1 and t 0 /2 and the adder 39 delivers the result of addition of t 2 and t 0 /2. Since the output of the adder 39 is not negative, it is delivered as the holding time t 22 . The output of the adder 38 is delivered as the holding time t 11 via the change-over switch 42. When the command voltage vector V is in the region R 3 , the result of addition by the adder 39 takes a negative value. The output of the AND circuit 40 is cut off. The determination signal is at the level "L" and the change-over switch 42 is switched. Consequently, the control period T SW is rendered the holding time t 11 and the holding times t 00 and t 22 are rendered zero. Thus, the same effect can be achieved in the second embodiment as in the first embodiment. FIGS. 6 and 7 show waveforms of the outputs of the inverter devices obtained by the first and second embodiments by way of simulation. FIGS. 6 and 7 also show phase currents for comparison in the case where the same load torque is applied to the three-phase induction motor. FIG. 6 illustrates the prior art and FIG. 7 the embodiments of the present invention. As obvious from comparison, the current peak value and the current effect value are smaller in the present invention than in the prior art. This shows that torque is produced by a lesser amount of current since the fundamental wave output voltage is high, whereby high torque effect is achieved. Although the present invention has been applied to the inverters of the open loop control type in the foregoing embodiments, the invention may be applied to the inverters of the current control type, in which case high current follow-up performance can be achieved.

Claims: A three-phase PWM signal generating device for an inverter device comprising an inverter main circuit (10) including six bridge-connected switching elements (13u-13z) which can be turned on and off in predetermined patterns so that a dc voltage supplied from an external source is converted to a three-phase ac approximately sinusoidal voltage, the three-phase PWM signal generating device connected to the inverter main circuit (10) for generating switching pattern signals for turning on and off the switching elements (13u-13z) in order to provide six kinds of switching patterns corresponding to six fundamental voltage vectors out of phase from one another by an electrical angle of 2π/6, respectively, and switching patterns corresponding to a zero vector corresponding to an "on" or "off" state of substantially all the switching elements (13u-13z) are provided so that the inverter main circuit (10) generates an approximately sinusoidal output voltage waveform, the three-phase PWM signal generating device comprising switching pattern determining means (15) for determining a holding time of each of the six kinds of switching patterns and an output sequence of the switching patterns, based on a command voltage vector including a supplied voltage command value (V*) and a supplied phase command value (*), characterized by command voltage vector substituting means (30) for supplying to the switching pattern determining means (15) a first command voltage vector, instead of a command voltage vector received from an external source, when the command voltage value of the received command voltage vector exceeds a PWM control region where the fundamental voltage vector is a radius, the first command voltage vector being nearest to the limit of the PWM control region. A three-phase PWM signal generating device according to claim 1, characterized in that when the received command voltage vector exceeds the PWM control region and the phase command value of the received command voltage vector approximates the fundamental voltage vector, the first command voltage vector is substituted for a vector having the magnitude of the fundamental voltage vector. A three-phase PWM signal generating device for an inverter device comprising an inverter main circuit (10) including six bridge-connected switching elements (13u-13z) which can be turned on and off in predetermined patterns so that a dc voltage supplied from an external source is converted to a three-phase ac approximately sinusoidal voltage, the three-phase PWM signal generating device connected to the inverter main circuit (10) for generating switching pattern signals for turning on and off the switching elements (13u-13z) in order to provide six kinds of switching patterns corresponding to six fundamental voltage vectors out of phase from one another by an electrical angle of 2π/6, respectively, and switching patterns corresponding to a zero vector corresponding to an "on" or "off" state of substantially all the switching elements (13u-13z) are provided so that the inverter main circuit (10) generates an approximately sinusoidal output voltage waveform, the three-phase PWM signal generating device comprising switching pattern determining means (15) for determining a holding time of each of the six kinds of switching patterns and an output sequence of the switching patterns, based on a command voltage vector including a supplied voltage command value (V*) and a supplied phase command value (*), characterized by command voltage vector substituting means (30) for supplying to the switching pattern determining means (15) a first command voltage vector received from an external source, the command voltage vector substituting means (30) comprising determining means for determining to which one of first, second and third regions the received voltage command vector (V*) belongs, the first region being defined by the six kinds of fundamental voltage vectors into an orthohexagonal configuration, the second region extending from the first region vertically relative to each side of the first region, the third region extending in the direction of each fundamental voltage vector, and means for converting the received voltage command vector (V*) to a first command voltage vector nearest to a PWM control region when it is determined by the determining means that the received voltage command vector (V*) belongs to the second region, said means converting the received voltage command vector (V*) to the magnitude of the fundamental voltage vector when it is determined by the determining means that the received voltage command vector belongs to the third region, said means holding the received voltage command vector when it is determined by the determining means that the received voltage command vector belongs to the first region.

Inventors: HIROSE TATSUYA, HORIGUCHI TAKI, MOCHIKAWA HIROSHI, HIROSE, TATSUYA, HORIGUCHI, TAKI, MOCHIKAWA, HIROSHI, Hirose, Tatsuya, Mie Works, K. K. Toshiba, Horiguchi, Taki, Mie Works, K. K. Toshiba, Mochikawa, Hiroshi, Mie Works, K. K. Toshiba
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: H02M7
IPC codes: H02M7