Method for manufacturing memories with thin film transistors

Abstract: A method for manufacturing a TFT type memory providing steps of (i) depositing a first insulating layer over a semiconductor substrate having a polysilicon gate formed by a first polysilicon film, and then opening a first contact hole so as to form a first insulating film, (ii) depositing a second polysilicon layer over the semiconductor substrate including the first contact hole, and then patterning the same so as to form a second polysilicon film, (iii) depositing a second insulating film over the semiconductor substrate including the second polysilicon film, and then opening a second contact hole so as to form a second insulating film, (iv) depositing a third polysilicon layer over the semiconductor substrate including the second contact hole, and then patterning the same so as to form a third polysilicon film as a capacitor bottom electrode, (v) implanting ions in the second polysilicon film in a region other than a capacitor formation region so as to form a source/drain region, (vi) depositing a third insulating layer over the whole surface, and then opening a contact window so as to form a third insulating film as a capacitor insulating film, and (vii) depositing a fourth polysilicon layer over the semiconductor substrate including the contact window, and then patterning the same so as to make a fourth polysilicon film remain as a capacitor top electrode in only the capacitor formation region.

Description: The present invention relates to a method for manufacturing a semiconductor memory, and more particularly to a process of manufacturing TFT type Static Random Access Memories (SRAMs) in which resistance to α rays can be improved by applying capacitors to cell nodes. By way of background art, reference is made to International Electron Devices Meeting, 11-14 December 1988, San Francisco, Ca, USA, pp. 48-51: "A 25µm² New Poly-Si PMOS Load (PPL) SRAM Cell Having Excellent Soft Error Immunity", T. Yamanaka et al and IEEE J. Solid-State Circuits, Vol. SC-25, No. 1, February 1990, pages 55-60. Conventional SRAMs have relied on the use of an N-type substrate and P-well structure to create a barrier for reducing charge collection from an impinging α-particle. The use of a buried P⁺ barrier layer in a P-well has been proposed to reduce the collection charge and soft-error rate. When the memory cell size is reduced, however, the cell node capacitance becomes smaller and it is hard to store enough charge to compensate the discharge generated by the α-particle. In Fig. 5(b), the memory cell parasitic node capacitance is plotted against line width. In Fig. 5(a), the memory cell parasitic node capacitance is indicated at Cn. As shown in Figs. 6(a), (b) and (c), the memory cell parasitic node capacitance Cn is composed of the gate oxide capacitance C G of a cell transistor and diffusion capacitance C DB . When the α-particle hits a storage junction node, carriers are generated along a particle track, and there is induced a noise current which discharges the stored charge. SER (Soft-Error Rate) is characterized by defining the critical charge Qcrit. This is the minimum charge that should be collected from the impinging α-particle to cause data upset. To increase the SRAM cell tolerance of SER to the increase of the memory cell parasitic node capacitance has been recognized, and the use of polysilicon interconnection layers has been proposed. This invention provides a method of manufacturing a semiconductor memory having a cross-coupling capacitor formed between cell nodes provided by polysilicon thin film transistors, the method comprising the steps of: (i) depositing a first insulating layer over a semiconductor substrate having a polysilicon gate formed by a first polysilicon film, and then opening a first contact hole so as to form a first insulating film; (ii) depositing a second polysilicon layer over the semiconductor substrate including the first contact hole, and then patterning the same so as to form a second polysilicon film as body of the polysilicon thin film transistors; (iii) depositing a second insulating layer over the semiconductor substrate including the second polysilicon film, and then opening a second contact hole so as to form a second insulating film; (iv) depositing a third polysilicon layer over the semiconductor substrate including the second contact hole, and then patterning the same so as to form a third polysilicon film as a capacitor bottom electrode of said capacitor as well as a top gate of the polysilicon thin film transistors; (v) implanting ions in the second polysilicon film in a region other than a capacitor formation region so as to form a source/drain region of the polysilicon thin film transistors; (vi) depositing a third insulating layer over the whole surface, and then opening a contact window so as to form a third insulating film as a capacitor insulating film of said capacitor; and (vii) depositing a fourth polysilicon layer over the semiconductor substrate including the contact window, and then patterning the same so as to make a fourth polysilicon film remain as a capacitor top electrode of said capacitor in only the capacitor formation region. In an SRAM Cell with Cross-Coupled Stacked Capacitor, α-ray induced Soft-Error Resistance and Qcrit are improved by: 1. combined action of TFT load current and cross-coupled capacitor, and 2. a memory cell structure and a fabrication process flow which are provided to realize the SRAM cell with Stacked Cross-Coupled Capacitor. Figure 1 (a) - (p) is a view showing manufacturing steps according to an embodiment of the present invention; Figs. 1 (a) and (b) are views showing the same process seen in the different directions. Fig. 1 (b) is a view for explaining manufacturing steps seen in the perpendicular direction to Fig. 1 (a). Figs. 1 (c) and (d) and Figs. (e) to (p) are similar. Figure 2 (a) is an equivalent circuit diagram of a device according to the embodiment of the present invention; Figure 2 (b) is a view for explaining the structure of the device according to the embodiment of the present invention; Figure 2 (c) is a view seen in the direction of the line X - X shown in Figure 2 (b); Figure 3 is a schematic equivalent circuit diagram showing the principles of the device according to the embodiment of the present invention; Figure 4 is a characteristic chart showing the relationship between time and a memory cell flip-flop node voltage of the device according to the embodiment of the present invention; Figure 5 (a) is an equivalent circuit diagram according to the prior art; Figure 5 (b) is a characteristic chart showing the relationship between a line width and SRAM cell node capacitance according to the prior art; Figure 6 (a) is a view showing MOS transistor capacitance according to the prior art; Figure 6 (b) is a view for explaining the operation of a MOS transistor; and Figure 6 (c) is an equivalent circuit diagram showing the memory cell capacitance of the MOS transistor. In order to analyze an SRAM cell circuit and its structure, a simple electrical model can be used for estimating the effect of hitting α rays as shown in Fig. 3. Using this circuit, a critical charge Qcrit for data upset is calculated to be: Qcrit = V H (Cn + 2Cc) / (1 - I L / I α ) where: V H : Signal level at the moment of α rays hitting; Cn : Memory cell parasitic node capacitance; Cc : Memory cell cross-coupling capacitance between cell nodes; I L : Memory cell load device current; I α : Current induced by α-particle. As seen from the formula (1), Cc is twice more effective than Cn in increasing Qcrit. The effect of the cross-coupling capacitor is illustrated in the simulation results of Figs. 4 (a), (b) and (c), where memory cell flip-flop node voltages are shown versus the time after hitting of an α-particle. In Figs. 4 (a), (b) and (c), a node V1 initially stores a level "1". As shown in Fig. 4 (a), Cc = 0 (fF) and Cn = 5 (fF) are not enough to prevent data upset. As shown in Fig. 4 (b), Cc = 1 (fF) is marginally sufficient to prevent data upset. According to the present embodiment, Cc = 5 (fF) is adequate to protect the stored data as shown in Fig. 4 (c). Initially, both nodes move together owing to capacitive coupling. Then, a load transistor supplies a current to restore node voltages. To reduce Soft-Error Rate degradation, Qcrit must be increased. To solve these problems, the claimed method of manufacturing a semiconductor memory is proposed. The present invention provides (1) fabricating a cross-coupled capacitor between memory cell flip-flop storage nodes, and (2) the use of active load devices (PMOSTFT) to (i) reduce the recovery time of the voltage at the node storing a "1" at high speed operation, and (ii) improve the ratio of load currents to α-particle induced currents. According to the present invention, resistance to a rays can be improved by applying capacitors to cell nodes in a TFT type SRAM. The method of the present invention results in a structure in which the conventional memory cells have new capacitor insulating films and electrode polysilicon layers. A preferred embodiment of the present invention will be described in more detail with reference to the drawings. The present invention is not limited to the following embodiment. The new memory cell structure incorporating a cross-coupled capacitor is shown in Figs. 2 (a), (b) and (c). It comprises bulk access transistors Q1 and Q2 which are connected to bit lines BL and to drains D of bulk transistors Q3 and Q4. The bit line BL is indicated at 24 in Fig. 2 (b). The bulk transistors Q3 and Q4 constitute the pull-down devices of a memory cell. As shown in Figs. 2 (b) and (c), the gate of the bulk transistor is formed by a first deposited polysilicon layer 5. As shown in Fig. 2 (c), polysilicon MOS transistors Q5 and Q6 are isolated from the bulk transistors by a first CVD oxide layer 6. As shown in Fig. 2 (c), a second polysilicon layer 8 constitutes a power supply line and a polysilicon MOS transistor body. A second CVD oxide layer 9 shown in Fig. 2 (c) is deposited over the second polysilicon layer 8 [see Fig. 2 (b)]. Consequently, a polysilicon MOS transistor gate insulating film is formed. According to the present embodiment, a gate insulating film 9 is a top gate oxide film for a TFT which is composed of a HTO film as shown in Fig. 2 (c). A top gate electrode 11 for a polysilicon PMOS device is formed on the gate insulating film 9 [see Figs. 2 (b) and (c)]. The polysilicon film of the top gate electrode is a bottom electrode 11 of a cross-coupled capacitor as described below. The transistors Q3, Q4, Q5 and Q6 are connected to one another so as to form a memory cell flip-flop. As shown in Fig. 2 (c), a cross-coupled capacitor C is composed of the capacitor top gate electrode 11 (top gate electrode 11 of a polysilicon PMOS FET), a capacitor insulating film 15 and a capacitor top electrode (second electrode) 17. The capacitor bottom electrode 11 constitutes one of electrodes. The capacitor insulating film 15 is deposited over the polysilicon TFT top gate electrode 11. The capacitor top electrode 17 is formed by a fourth polysilicon layer. After the polysilicon PMOS transistor is formed, a third insulating layer 15 is deposited to form a cross-coupled capacitor insulating layer 15. As shown in Figs. 1 (m) and (n), a contact window 16 is opened. Then, the fourth polysilicon layer 17 is deposited and patterned to form a cross-coupled capacitor electrode. As shown in Figs. 1. (o) and (p), insulating layers 18 and 22 and interconnection metal layers 20 and 24 form ground lines and bit lines. The ground lines are connected to the sources of the bulk transistors Q3 and Q4. Thus, an element is produced. There will be described a manufacturing method. A novel SRAM cell is produced in a MOS forming process as follows. As shown in Figs. 1 (a) and (b), a bulk N-channel polysilicon gate transistor T is formed on a silicon substrate 1 by using the well-known MOS forming process. The bulk N-channel polysilicon gate transistor T comprises a polysilicon gate (first polysilicon film) 5 including a SiO₂ LOCOS oxide film 2, an N⁺ diffusion layer 3 and a SiO₂ side wall 4. Then, a SiO₂ CVD oxide film layer is deposited over the whole surface to form a polysilicon MOS transistor bottom gate insulating film (polysilicon MOS transistor bottom gate dielectric: referred to as a first insulating film) 6. Thereafter, a first contact hole 7 is opened on the insulating film 6 by photoetching techniques [see Figs. 1 (c) and (d)]. The first contact hole 7 has a length d1 of about 0.6 µm and a width d2 of about 0.6 µm. Subsequently, a polysilicon layer (second polysilicon film) 8 is deposited over the silicon substrate 1 including the contact hole 7, and then is patterned by photoetching techniques so as to form a polysilicon transistor body H [see Figs. 1 (e) and (f)]. Then, a HTO film is deposited as a CVD oxide layer over the silicon substrate 1 including the second polysilicon film 8 which is patterned. Consequently, a polysilicon transistor top gate insulating film (polysilicon transistor top gate dielectric : referred to as a second insulating film) 9 is formed. Thereafter, a second contact hole 10 is opened on the insulating film 9 by the photoetching techniques [see Figs. 1 (g) and (h)]. The second contact hole 10 has a length D1 of about 0.6 µm and a width D2 of about 0.6 µm. A polysilicon layer (third polysilicon film) 11 is deposited over the silicon substrate 1 including the contact hole 10 so as to form a polysilicon transistor top gate electrode (a top gate electrode), i.e., the bottom electrode of a stacked cross-coupled capacitor [see Figs. 1 (i) and (j)]. Then, the third polysilicon layer 11 is removed in a predetermined region by using a photoresist 12 as a mask. Thereafter, boron ions (¹¹B⁺) 13, which are P-type impurities, are implanted in the removing region through the HTO film 9 so as to form a source/drain region 14 of the TFT polysilicon transistor [see Figs. 1 (k) and (l)]. Subsequently, a third insulating film is deposited over the silicon substrate 1 including the HTO film 9 and the residual third polysilicon film 11 so as to form a cross-coupled capacitor insulating film 15. Then, a contact window 16 is opened by the photoetching techniques. Thereafter, a fourth polysilicon layer is deposited over the silicon substrate 1 including the contact window 16, and then is patterned to form a top electrode 17 of the stacked capacitor [see Figs. 1 (m) and (n)]. Finally, a second layer insulation film 22, a second contact portion 23 and a second metal film 24 are formed over the whole surface through an intermediate coupling layer 21 by using the well-known method. The second contact portion 23 is opened on the second layer insulation film 22. The second metal film 24 is formed by patterning. The intermediate coupling layer 21 is composed of a first layer insulation film 18, a first contact portion 19 and a first metal film 20. The first contact portion 19 is opened on the first layer insulation film 18. The first metal film 20 is formed by patterning. Thus, a device is completed [see Figs. 1 (o) and (p)]. According to the present invention, the SRAM cell capacitance and critical stored charge Qcrit can be increased by the stacked cross-coupled capacitor. The cross-coupled capacitor can be stacked on the memory cell, so that there is no increase in cell area. Furthermore, the transistor characteristics of the Double-Gated MOS Polysilicon Thin Film Transistors can be improved. In addition, the high drive current of the Double-Gated TFT, combined with the higher cell capacitance owing to the cross-coupled capacitor, results in improved soft-error resistance.

Claims: A method of manufacturing a semiconductor memory having a cross-coupling capacitor (Cc) formed between cell nodes provided by polysilicon thin film transistors (Q5,Q6), the method comprising the steps of: (i) depositing a first insulating layer over a semiconductor substrate (1) having a polysilicon gate formed by a first polysilicon film (5), and then opening a first contact hole (7) so as to form a first insulating film (6); (ii) depositing a second polysilicon layer over the semiconductor substrate including the first contact hole (7), and then patterning the same so as to form a second polysilicon film (8) as body (H) of the polysilicon thin film transistors (Q5,Q6); (iii) depositing a second insulating layer over the semiconductor substrate including the second polysilicon film (8), and then opening a second contact hole (10) so as to form a second insulating film (9); (iv) depositing a third polysilicon layer over the semiconductor substrate including the second contact hole (10), and then patterning the same so as to form a third polysilicon film (11) as a capacitor bottom electrode of said capacitor as well as a top gate of the polysilicon thin film transistors (Q5,Q6); (v) implanting ions (13) in the second polysilicon film (8) in a region other than a capacitor formation region so as to form a source/drain region (14) of the polysilicon thin film transistors (Q5,Q6); (vi) depositing a third insulating layer over the whole surface, and then opening a contact window (16) so as to form a third insulating film (15) as a capacitor insulating film of said capacitor; and (vii) depositing a fourth polysilicon layer over the semiconductor substrate including the contact window (16), and then patterning the same so as to make a fourth polysilicon film (17) remain as a capacitor top electrode of said capacitor in only the capacitor formation region.

Inventors: ADAN ALBERTO OSCAR, ADAN, ALBERTO OSCAR
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1991
Main classification: H01L21
IPC codes: H01L27, H01L21, H01L29