Method for fabricating an optical semiconductor device

Abstract: A method for fabricating an optical semiconductor device includes the steps of forming at least two stripes of dielectric parallel to each other with a predetermined interval on a semiconductor substrate, growing a crystal selectively between the two stripes, and forming a multi-layer structure which is required to have a width determined by the crystal grown between the two stripes. In such a method, the width of the multi-layer structure including an active layer or a waveguide is controlled precisely, because there is no step of etching a semiconductor layer, so that the characteristics of the device may improve and the yield may increase.

Description: This invention relates to a method for fabricating an optical semiconductor device, and more particularly, to a method for fabricating an optical semiconductor device such as a single semiconductor laser, a combination of a semiconductor laser and a semiconductor optical modulator or a waveguide integrated in a common semiconductor substrate used in an optical communication system, an optical information processing system, etc. An optical semiconductor device such as a semiconductor laser used in an optical communication system or an optical information processing system has been required to have higher performances as well as to be fabricated at low cost for public use, so that it is necessary to fabricate such an optical semiconductor device from a large size semiconductor wafer with high yield. In order to meet these requirements, the optical semiconductor device is fabricated by a process in which crystal growth is carried out by vapor phase epitaxy such as metalorganic vapor phase epitaxy (MOVPE) by which epitaxial growth is realized in a large area with high uniformity. Such a vapor phase epitaxy allows to fabricate a semiconductor laser of quantum well structure having characteristics such as low threshold and high efficiency operation or narrow spectrum operation. In a first conventional method for fabricating an optical semiconductor device, a double-hetero (DH) structure consisting of an n-InP clad layer, an InGaAsP active layer and a p-InP clad layer is formed on an n-InP substrate. Then, an SiO 2 layer is formed on the p-InP clad layer, and patterned to stripes each of which having a width of 2 µm. Then, the DH structure is mesa-etched, except for the area which is masked by the SiO 2 layer, until the surface of the n-InP substrate is exposed. The width of the remaining active layer thus subjected to mesa-etching becomes 1.5 µm, which enables the fundamental transverse mode to be kept stable. Then, p-InP and n-InP buried layers are deposited in this order on the exposed surface of the n-InP substrate to stuff the grooves formed by the mesa-etching on both sides of the remaining double-hetero structure. Finally, after removing the SiO 2 layer, a p-InP layer and a p + -InGaAs cap layer are deposited in this order to cover the fabricated surface of the n-InP substrate. In a second conventional method for fabricating an optical semiconductor device, a DH structure consisting of a first clad layer, an active layer and a second clad layer is formed on a substrate. Then, an SiO 2 layer is formed and patterned to stripes each having a predetermined width. Then, the DH structure is mesa-etched, except for the area which is masked by the SiO 2 layer, until the surface of the n-InP substrate is exposed. Then, after removing the SiO 2 layer, a third clad layer and a cap layer are deposited in this order to cover the fabricated surface of the n-InP substrate including the DR structure. Finally, a high resistance region is formed on both sides of the DH structure by implanting protons to confine a current flowing within the DH structure. On the other hand, there is a great demand for an integrated optical semiconductor device such as one including a distributed feedback (DFB) semiconductor laser and a semiconductor optical modulator with narrow spectrum at high speed modulation or one including a distributed Bragg reflection (DBR) semiconductor laser with variable wavelength. In a third conventional method for fabricating an optical semiconductor device, a grating is formed only within the DBR region on the surface of an n-InP substrate. Then, an n-InGaAsP guide layer, an active layer and a p-InP clad layer are deposited in this order. Then, the p-InP clad layer and the InGaAsP active layer in all of the regions but the active region are removed using an SiO 2 layer as a mask. Then, an InGaAsP waveguide layer and a p-InP clad layer are grown selectively on a predetermined region. Then, the fabricated surface of the n-InP substrate, except for the areas forming the elements, is mesa-etched using an SiO 2 layer as a mask. Then, an Fe-doped high resistance InP layer and an n-InP layer are grown to be buried. Then, after removing the SiO 2 layer, a p-InP layer and a p + -InGaAs cap layer are grown. Then, grooves for insulation are formed between the laser and waveguide regions, and between the adjacent semiconductor lasers. Then, an SiO 2 layer is deposited throughout the fabricated surface of the n-InP substrate. Then, after forming openings in the SiO 2 above the waveguide areas of the modulator, DBR, phase adjusting and active regions, p-electrodes are formed to connect the waveguide areas thereof through the openings, while an n-electrode is formed on the back surface of the substrate. According to the first to third conventional methods for fabricating an optical semiconductor device, however, there is a disadvantage in that it is difficult to control the width of waveguides or active layers precisely, because the conventional methods include the steps of semiconductor etching using an SiO 2 layer as a mask. In semiconductor etching such as mesa-etching, the thickness of the semiconductor can be controlled precisely, however, the width thereof varies because of variation of the mesa structure or occurrence of side etching. Variation of width of the active layer or waveguide may affect the characteristics of the device such as the threshold current, oscillation wavelength or beam pattern. Consequently, such a variation of the width thereof may cause yield reduction or outranging of designed operation. Furthermore, in fabrication, it is required to match the location of the active layer with that of the waveguide, so that the steps of etching and growth of buried layers become complex and have problems in uniformity and reproducibility which affect the characteristics of the device and the yield in fabrication. JP-A-62-144 385 discloses a method for fabricating an optical semiconductor device with a mask with a striped opening formed on a substrate; semiconductor layers are grown on the substrate through a MOCVD method. Accordingly, it is an object of the invention to provide a method for fabricating an optical semiconductor device in which the width of an active layer or a waveguide is controlled precisely. This object is solved with the features of the claims. The invention will be explained in more detail in conjunction with the appended drawings wherein: Figs. 1A to 1E are cross-sectional views illustrating a semiconductor laser during various stages of fabrication according to a first conventional method for fabricating an optical semiconductor device; Figs. 2A to 2E are cross-sectional views illustrating a semiconductor laser during various stages of fabrication according to a second conventional method for fabricating an optical semiconductor device; Fig. 3 is a perspective view illustrating an integrated optical waveguide device fabricated by a third conventional method for fabricating an optical semiconductor device; Figs. 4A and 4B are perspective views of a structure of a crystal growth substrate and a growth crystal explaining a basic principle of the invention; Fig. 5 is a graph showing the relation between SiO 2 stripe width and growth rate; Fig. 6 is a graph showing the relation between SiO 2 stripe width and composition ratio of In in the crystal; Fig. 7 is a graph showing the relation between SiO 2 stripe width and emission wavelength; Figs. 8A to 8F are cross-sectional views illustrating a semiconductor laser during various stages of fabrication according to a method for fabricating an optical semiconductor device in a first preferred embodiment according to the invention; Figs. 9A to 9F are cross-sectional views illustrating an integrated optical device during various stages of fabrication according to a method for fabricating an optical semiconductor device in a second preferred embodiment according to the invention; and Fig. 10 is a perspective view illustrating a semiconductor laser fabricated by a method for fabricating an optical semiconductor device in a third preferred embodiment according to the invention. Before describing a method for fabricating an optical semiconductor device in the preferred embodiments according to the invention, the conventional methods for fabricating an optical semiconductor device described before will be explained. First, the first conventional method for fabricating an optical semiconductor device by MOVPE will be explained in conjunction with Figs. 1A to 1B. In the first conventional method for fabricating an optical semiconductor device, a double-hetero (DH) structure consisting of an n-InP clad layer 2, an InGaAsP active layer 3 and a p-InP clad layer 4 is formed on an n-InP substrate 1, as shown in Fig. 1A. Then, an SiO 2 layer 21 is formed on the p-InP clad layer 4, and patterned to stripes each having a width of 2 µm, as shown in Fig. 1B. Then, the DH structure is mesa-etched, except for the area which is masked by the SiO 2 layer 21, until the surface of the n-InP substrate 1 is exposed, as shown in Fig. 1C. The width of the remaining active layer 3 thus subjected to the mesa-etching becomes 1.5 µm, which enables the fundamental transverse mode to be kept stable. Then, p-InP and n-InP buried layers 14 and 15 are deposited in this order on the exposed surface of the n-InP substrate 1 to stuff the grooves formed by the mesa-etching on both sides of the remaining double-hetero structure, as shown in Fig. 1D. Finally, after removing the SiO 2 layer 21, a p-InP layer 5 and a p + -InGaAs cap layer 7 are deposited in this order selectively to cover the fabricated surface of the n-InP substrate 1, as shown in Fig. 1E. Next, the second conventional method for fabricating an optical semiconductor device will be explained in conjunction with Figs. 2A to 2E. In the second conventional method for fabricating an optical semiconductor device, a DH structure consisting of a first clad layer 8, an active layer 3 and a second clad layer 4 is formed on a substrate 1, as shown in Fig. 2A. Then, an SiO 2 layer 21 is formed and patterned to stripes each having a predetermined width, as shown in Fig. 2B. Then, the DH structure is mesa-etched, except for the area which is masked by the SiO 2 layer 21 until the surface of the n-InP substrate 1 is exposed, as shown in Fig. 2C. Then, after removing the SiO 2 layer 21, a third clad layer 5 and a cap layer 7 are deposited in this order to cover the fabricated surface of the n-InP substrate 1 including the DH structure, as shown in Fig. 2D. Finally, a high resistance region 31 is formed on both sides of the DH structure by implanting protons to confine a current flowing within the DH structure, as shown in Fig. 2E. Next, the third conventional method for fabricating an optical semiconductor device will be explained in conjunction with Fig. 3. The integrated optical waveguide device includes four wavelength variable semiconductor lasers, four semiconductor optical modulators and two optical waveguides having four terminals connected with the four modulators to provide four parallel lasing and modulating structures. Each of the four wavelength variable semiconductor laser is a three-electrode DBR laser including an active region, a phase adjusting region and a DBR region. An active layer 3 is formed only in the active region, while a waveguide layer 10 is formed commonly in the phase adjusting region, the DBR region, the modulator region and the waveguide region. The active layer 3 and the waveguide layer 10 are connected with each other at a joint 12. The active layer 3 and the waveguide layer 10 are both mesa-etched to a stripe having a width of approximately 1.5 µm. A high resistance InP layer 13 is formed to be buried between adjacent two of the four parallel structures for confinement of a current flowing within each of the structures and isolation therebetween. In the third conventional method for fabricating an optical semiconductor device, a grating 11 is formed only within the DBR region on the surface of an n-InP substrate 1. Then, an n-InGaAsP guide layer 8, an active layer 3, a p-InP clad layer 4 are deposited in this order. Then, the p-InP clad layer 4 and the InGaAsP active layer 3 in all of the regions, except for the active region are removed using an SiO 2 layer as a mask. Then, the InGaAsP waveguide layer 10 and a p-InP clad layer 4 are grown selectively on the predetermined region. Then, the fabricated surface of the n-InP substrate 1, except for the areas forming the elements are mesa-etched using an SiO 2 layer as a mask. Then, an Fe-doped high resistance InP layer 13 and an n-InP layer 5 are grown to be buried. Then, after removing the SiO 2 layer, a p-InP layer 6 and a p + -InGaAs cap layer 7 are grown. Then, grooves for insulation are formed between the laser and waveguide regions, and between the adjacent semiconductor lasers. Then, an SiO 2 layer 21 is deposited on the entire fabricated surface of the substrate 1. Then, after forming openings in the SiO 2 above the waveguide areas of the modulator, DBR, phase adjusting and active regions, p-electrodes 32 are formed to connect the waveguide areas thereof through the openings, while an n-electrodes 33 is formed on the back surface of the n-InP substrate 1. The growth operations are carried out by metalorganic vapor phase epitaxy (MOVPE). Next, the basic principle of the invention will be explained in conjunction with Figs. 4A and 4B. In Fig. 4A, a thin film 21 for selective growth is formed on a (100) surface of a semiconductor substrate 1. Then, the thin film 21 is selectively removed to form stripes having side walls 21a parallel to [0 1 1] or [011] direction. Then, a DH structure consisting of a first clad layer 2, an active layer 3 and a second clad layer 4 are formed by MOVPE, as shown in Fig. 4B. In such a case, the DH structure has facets of a (111)A surface in a [0 1 1] direction and a (111)B surface in a [011] direction. Additionally, all of the layers composing the DH structure have very flat top surfaces of (100). The mixed crystal compositions of the layers are uniform within each surface so far as the stripe width of the thin film 21 is not too large, so that such a layer thus formed can be used as an active layer or a waveguide layer. As explained above, each of the layers has facets of (111), so that the width of the layers can be controlled precisely so far as patterning of an SiO 2 layer as a mask is carried out precisely. In the selective growth, it is possible to cover the facets of the active layer with an upper clad layer during the growth thereof, so that it is possible to fabricate a semiconductor laser having superior characteristics of little interface recombination composition, controllability and reproducibility. In this method for fabricating an optical semiconductor device, a p-InP clad layer and a p + -InGaAs cap layer are formed by selective growth, and the method does not include etching of semiconductor layers which causes several troubles, though it includes patterning of dielectric thin films such as an SiO 2 layer and selective growth. Therefore, optical semiconductor devices are fabricated from a large size semiconductor wafer by a batch growth process having superior performance such as uniformity or reproducibility due to selective growth of an active layer. Next, the relation between the width of the SiO 2 stripe-shaped layer as a mask and the growth rate of semiconductor layers will be explained. In this MOVPE selective growth, the growth rate becomes large as the width of the SiO 2 stripe becomes large, and the composition of III-group element such as In depends on the width thereof if the semiconductor layer to be grown is a mixed crystal semiconductor. Such an analysis has been reported by Y. D. Galeuchet et al. on pages 147 to 150 of Journal of Crystal Growth 107 (1991) and by J. Finders et al. on pages 151 to 155 thereof. Fig. 5 shows the relation between SiO 2 stripe width and a growth rate in case of InP and InGaAs, while Fig. 6 shows the relation between SiO 2 stripe width and composition ratio of In in the mixed crystal of In x Ga 1-x As and In x Ga 1-x As 0.6 P 0.4 in which a light having a wavelength of 1.3 µm is emitted. The growth rate of the semiconductor layer becomes large as the width of the SiO 2 stripe becomes large, because the growth source materials which are diffused in lateral direction along the SiO 2 , layer to reach the semiconductor surface becomes large in amount as the width thereof becomes large. The In ratio in the composition of the mixed crystal becomes large as the width thereof becomes large, because the source material of In diffuses in lateral direction easier than that of Ga. Therefore, in the selective growth of a quantum well structure using InGaAs or InGaAsP as a well, the thickness of the well becomes large and the lattice distortion (compressive stress) is applied to the well so that the amount of In in the composition of the mixed crystal composing the well increases by widening the SiO 2 , stripe. Consequently, the transition energy of the quantum well structure becomes small. Fig. 7 shows the relation between SiO 2 stripe width and emission wavelength of the selectively grown layer in case of multi-quantum well (MQW) structure including In x Ga 1-x As well and In x Ga 1-x As y P 1-y barrier selectively grown. The wavelength becomes long as the width of the SiO 2 stripe becomes large. In practice, the wavelengths become approximately 1.4 µm, and 1.55 µm when the widths are approximately 4 µm and 10 µm, respectively. Therefore, a semiconductor laser emitting a light having a wavelength of 1.55 µm and a waveguide layer transmitting a light having a wavelength of 1.3 µm can be fabricated simultaneously by the same process by determining the widths of the semiconductor laser and the waveguide layer so as to have a predetermined ratio. In other words, a laser oscillating region in the direction parallel to a waveguide and a waveguide region which is transparent against the light can be fabricated by use of crystal growth. Next, a method for fabricating an optical semiconductor device in a first preferred embodiment according to the invention will be explained in conjunction with Figs. 8A to 8F. First, an SiO 2 layer 21 having a thickness of approximately 0.2µm (2000 Å) is deposited on a (100) surface of an n-InP substrate 1 by chemical vapor deposition (CVD). Then, the SiO 2 layer 21 is patterned by photolithography to form two stripes each having a width of 10 µm with an interval of 1.8 µm, as shown in Fig. 8A. Then, an Si-doped n-InP clad layer 2 having a thickness of 0.1µm (1000Å) and a carrier concentration of 1 × 10 18 cm -3 , an InGaAsP active layer 3 having a thickness of 0.08µm (800Å) and a composition corresponding to a wavelength of 1.55 µm, and a Zn-doped p-InP clad layer 4 having a thickness of 0.05µm (500 Å) and a carrier concentration of 5 × 10 17 cm -3 are selectively grown in this order to form a DH structure on the surface of the n-InP substrate 1 along the SiO 2 layer 21 and between the adjacent SiO 2 layers 21, as shown in Fig. 8B. The thicknesses of the layers shown above are measured at the area between the two SiO 2 stripes 21 corresponding to an active region, and the thicknesses thereof are uniform in the active region. Then, the SiO 2 layers 21 are removed as wide as 10 µm setting the removing center line at the center line of the active region, as shown in Fig. 8C. Then, a p-InP clad layer 6 having a thickness of 1.5 µm and a carrier concentration of 5 × 10 17 cm -3 and a p + -InGaAs cap layer 7 having a thickness of 0.3 µm and a carrier concentration of 1 × 10 19 cm -3 are selectively grown in this order in the area between the two remaining SiO 2 layers 21. Then, after removing the SiO 2 layers 21, a second SiO 2 layer 22 is formed on the entire fabricated surface of the n-InF substrate 1, and the second SiO 2 layer 22 is etched to have a stripe opening above the active region, as shown in Fig. 8E. Finally, a p-electrode 32 is formed to connect with the active region through the stripe opening, while an n-electrode 33 is formed on the back surface of the n-InP substrate 1, as shown in Fig. 8F. An investigation of characteristics of the semiconductor laser thus fabricated was carried out in case of a cavity length of 300 µm to obtain results of an average threshold current of 10.2 mA with standard deviation of 0.2 mA and an average slope efficiency of 0.23 W/A with standard deviation of 0.04 W/A. The average width of the active layer is 1.52 µm with standard deviation of 0.12 µm. Such a result shows that the semiconductor laser fabricated by the first preferred embodiment has almost the same characteristics as those of the semiconductor laser fabricated by the conventional fabrication method as shown in Fig. 1 or 2, and the distribution of values of the characteristics becomes narrow. In this preferred embodiment, a bulk layer of InGaAsP is used for the active layer, however, an MQW structure may be used instead of the bulk layer to improve the characteristics thereof considerably. A p-type substrate may be used instead of an n-type substrate used in the embodiment. In this case, the conduction type of each of layers becomes reversed one as compared with that in the embodiment. Next, a method for fabricating an optical semiconductor device in a second preferred embodiment according to the invention will be explained in conjunction with Figs. 9A to 9F. First, a grating (diffraction lattice) 11 in the direction of [011] is formed only within a laser region on a (100) surface of an n-InP substrate 1, as shown in Fig. 9A. Then, an n-InGaAsP guide layer 8 having the composition corresponding to a wavelength of 1.3 µm, a carrier concentration of 1 × 10 18 cm -3 and a thickness of 0.1µm (1000 Å) and an n-InP spacer layer 9 having a carrier concentration of 1 × 10 18 cm -3 and a thickness of 0.05µm (500 Å) are grown in this order on the n-InP substrate 1, as shown in Fig. 9B. Then, an SiO 2 layer 21 is formed on the n-InP spacer layer 9, and the SiO 2 layer 21 is patterned to be a pair of stripes parallel each other with an interval of 2 µm and each having a width of 10 µm in the laser region and 6 µm in the modulator region, as shown in Fig. 9C. Each of the stripes has a transition width of 20 µm. Then, an n-InP clad layer 2 having a carrier concentration of 1 × 10 18 cm -3 and a thickness of 0.05µm (500 Å), an MQW active layer 3, and a p-InP clad layer 4 having a carrier concentration of 5 × 10 17 cm -3 and a thickness of 0.05µm (500 Å) are selectively grown in this order using the stripes of the SiO 2 layer 21 as masks to form a waveguide region, as shown in Fig. 9D. The MQW active layer 3 has an MQW structure including a well of InGaAs and a barrier of InGaAsP and having a well number of 4. It is to be noted that the growth conditions of the layers are set so that the well and the barrier are both lattice matched with the n-InP substrate 1 in the active region and thicknesses of the well and the barrier become respectively 7.5nm (75Å) and 15nm (150 Å). As a result, the emission wavelength becomes 1.56 µm in the active region and 1.48 µm in the modulator region. Then, the SiO 2 layers 21 are removed on both sides of the waveguide region to have stripe shaped openings having a width of 2 µm, as shown in Fig. 9E. Then, a p-InP clad layer 6 having a carrier concentration of 5 × 10 17 cm -3 and a thickness of 1.5 µm and a p + -InGaAs cap layer 7 having a thickness of 0.3 µm and a carrier concentration of 1 × 10 19 cm -3 are selectively grown in this order, as shown in Fig. 9F. Then, an SiO 2 layer is formed all over the fabricated surface of the n-InP substrate 1, and the SiO 2 layer is removed to form a stripe shaped opening having a width of 20 µm above the laser region and the modulator region. Then, the p + -InGaAs cap layer 7 is removed in the area between the laser and modulator regions by etching to make isolation therebetween. Finally, pad-shaped p-electrodes are formed on the fabricated surface to connect with the laser and modulator regions through the openings, while an n-electrode is formed on the back surface of the n-InP substrate 1. The laser region length having a cleavage surface is 500 µm and the modulator region length is 200 µm. An investigation of characteristics of the integrated optical device thus fabricated was carried out. In a typical one of the integrated optical devices, the oscillation threshold current is 20 mA and the maximum CW optical output from the modulator is 30 mW. The oscillation wavelength is 1.55 µm, and the extinction ratio is 20 dB when the modulator region is applied with a voltage of -3V. The coupling efficiency estimated by the extinction characteristic was found to be as large as 98 %. The isolation resistance between the laser and modulator regions is 50 kΩ. Any of 20 samples random-selected from the fabricated devices has an extinction ratio not smaller than 15 dB on condition of being applied with -5V. Next, a method for fabricating an optical semiconductor device in a third preferred embodiment according to the invention will be explained in conjunction with Fig. 10. First, a grating 11 is formed only within a DBR region on an n-InP substrate 1. Then, an n-InGaAsP guide layer 8 having a composition corresponding to a wavelength of 1.3 µm, a carrier concentration of 1 × 10 18 cm -3 and a thickness of approximately 0.1µm (1000 Å), and an n-InP spacer layer 9 having a carrier concentration of 1 × 10 18 cm -3 and a thickness of approximately 0.05µm (500 Å) are grown in this order. Then, an SiO 2 layer is formed on the n-InP spacer layer 9, and the SiO 2 layer is patterned to a pair of stripes parallel to each other with an interval of 2 µm and each having a width of 10 µm in the active region and 4 µm in both the phase adjusting region and the DBR region. Each of the stripes has a transition width of 20 µm. Then, an n-InP clad layer 2 having a carrier concentration of 1 × 10 18 cm -3 and a thickness of 0.05µm (500 Å), an MQW active layer 3, and a p-InP clad layer 4 having a carrier concentration of 5 × 10 17 cm -3 and a thickness of 0.05µm (500 Å) are selectively grown in this order using the stripes of the SiO 2 layer as masks to form a waveguide region. The MQW active layer 3 has an MQW structure including a well of InGaAs and a barrier of InGaAsP and having a well number of 4. It is to be noted that the growth conditions of the layers are set so that the well and the barrier are both lattice matched with the n-InP substrate 1 in the active region and thicknesses of the well and the barrier become respectively 7.5nm (75 Å) and 15nm (150 Å). As a result, the emission wavelength becomes 1.56 µm in the active region and approximately 1.4 µm in both the phase adjusting region and the DBR region. Then, the SiO 2 layers are removed on both sides of the waveguide region to have stripe shaped openings having a width of 2 µm. Then, a p-InP clad layer 6 having a carrier concentration of 5 × 10 17 cm -3 and a thickness of 1.5 µm and a p + -InGaAs cap layer 7 having a thickness of 0.3 µm and a carrier concentration of 1 × 10 19 cm -3 are selectively grown in this order. Then, an SiO 2 layer is formed all over the fabricated surface of the n-InP substrate 1, and the SiO 2 layer is removed to form a stripe shaped opening having a width of 20 µm. Then, the p + -InGaAs cap layer 7 is removed in the area between the regions by etching to make isolation therebetween. Finally, pad-shaped p-electrodes 32 are formed on the fabricated surface, while an n-electrode 33 is formed on the back surface of the n-InP substrate 1. The active region length having a cleavage surface is 500 µm, the phase adjusting region length is 150 µm and the DBR region length is 300 µm. The distance between the waveguides is 600 µm, and an irradiation facet of the DBR region is coated with an anti-reflection film. An investigation of characteristics of the DBR semiconductor array thus fabricated was carried out after being cut into respective structures of 4 channels. In a typical one of the 4-channel DBR semiconductor arrays, the oscillation threshold current is 18 mA. The oscillation wavelength of the 4 channels is 1.553 µm ± 0.003 µm when a current is injected into only the active region. It was confirmed that the DBR semiconductor array operates in a single mode until the optical output becomes as large as 30 mW. It is possible to obtain a wide range of the wavelength variable not narrower than 5 nm in each channel with keeping the optical output at 5 mW by injecting a current into the phase adjusting and DBR regions. In the second and third preferred embodiments, the current confinement structure may be replaced by one using a proton implantation method instead of the selective growth. Although the invention has been described with respect to specific embodiments for complete and clear disclosure, the appended claims are not to thus limited and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.

Claims: A method for fabricating an optical III-V semiconductor device, comprising the steps of: forming first and second regions on a semiconductor crystal substrate, said first region having a surface having a diffraction grating (II) and said second region having a flat surface; forming a first multi-layer semiconductor structure including a semiconductor guide layer (8) on the surface of said first and second region of said semiconductor crystal substrate; forming at least two stripes of a dielectric layer (21) on said first multi-layer semiconductor structure such that they define between them an optical waveguide region in said first multi-layer semiconductor structure, said stripes being parallel to each other with a predetermined interval between them and each of said stripes having a width which is wider in said first region and is narrower in said second region; forming a second multi-layer semiconductor structure including an active layer (3) by selective MOVPE growth on a surface of said first multi-layer semiconductor structure including said optical waveguide region, whereby the bandgap of the active layer (3) over said first and second regions is varied according to the dielectric layer stripe width; and forming a semiconductor laser and a semiconductor optical modulator over said first and second regions, respectively. A method for fabricating an optical III-V semiconductor device, comprising the steps of: forming first to third regions on a semiconductor crystal substrate (I), each of said first and second regions having a flat surface and said third region having a surface having a diffraction grating (II); forming a first multi-layer semiconductor structure including a semiconductor guide layer (8) on the surface of said first to third region of said semiconductor crystal substrate; forming at least two stripes of a dielectric layer (21) on said first multi-layer semiconductor structure such that they define between them an optical waveguide region in said first multi-layer semiconductor structure, said stripes being parallel to each other with a predetermined interval and each of said stripes having a width which is wider in said first region and is narrower in said second and third regions, whereby the stripe width in said second and third region is the same; forming a second multi-layer semiconductor layer including an active layer (3) by selective MOVPE growth on a surface of said first multi-layer semiconductor structure including said optical waveguide region, whereby the bandgap of the active layer (3) over the first to third regions is varied according to the dielectric layer stripe width; and forming a light emission unit, a phase control unit and a wavelength variable bragg reflector over said first to third regions, respectively. A method according to claim 1 or 2 further comprising the steps of: etching said two stripes of said dielectric layer in part facing each other to expose a surface of said semiconductor substrate after said step of forming the second multi-layer semiconductor structure; and growing a crystal selectively to be a clad layer over said second multilayer semiconductor structure at least including the area between said two stripes of said dielectric layer after said step of etching said two stripes of said dielectric.

Inventors: KATOH TOMOAKI, MITO IKUO, SASAKI TATSUYA, KATOH, TOMOAKI, MITO, IKUO, SASAKI, TATSUYA, KATOH, TOMOAKI, C/O NEC CORPORATION, MITO, IKUO, C/O NEC CORPORATION, SASAKI, TATSUYA, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: H01L33
IPC codes: H01L33, H01S5