A circuit for gradationally driving a flat display device

Abstract: A driving circuit for a flat display panel formed of a plurality of cells arranged in lines and each having a memory function is adapted to produce a desired gradation of visual brightness in an image displayed on the display panel during a frame time period, the frame time period being divided into a series of subframes, and each subframe comprising an address period and a display period subsequent to the address period. The driving circuit comprises means for selecting pixels to be activated in respective subframes of the frame time period and means for activating the selected pixels during the address period of a subframe and for lighting the activated pixels in the display period of the respective subframe. The activating means is adapted to apply sustain pulses to all the pixels of the display during the display periods of the subframes and thereby illuminate activated pixels. The selecting means is adapted to select pixels for activation in subframes of a frame such that the cumulative number of sustain pulses applied to each pixel produces the desired gradation of brightness of the image displayed during the frame time period. The activation means is adapted to address selected pixels in the plurality of lines during an address period of a subframe, which is common to said plurality of lines.

Description: BACKGROUND OF THE INVENTION Field of the invention This invention relates to a circuit for driving a flat display panel having a memory function, such as an AC-type PDP (plasma display panel), etc., to allow gradation, i.e. a gray scale, of its visual brightness for each cell. The present invention is divided from European patent application 91 403 217.2 which is directed to a method for driving a flat display panel having a memory function. Description of the Related Arts Flat display apparatus, allowing a thin depth as well as a large picture display size, have been popularly employed, resulting in a rapid increase in its application area. Accordingly, there has been required further improvements of the picture quality, such as a gradation as high as 256 grades, so as to achieve the high-definition television, etc. There have been proposed some methods for providing a gradation of the display brightness, such as in Japanese Unexamined Patent Publication Sho51-32051 or Hei2-291597, where a single frame period of a picture to be displayed is divided with time into plural subframes each of which has a specific time length for lighting a cell so that the visual brightness of the cell is weighted. A typical prior art method to provide the gradation of visual brightness is schematically illustrated in Fig. 1, where after cells on a single horizontal line (simply referred to hereinafter as a line) Y 1 are selectively written, i.e. addressed, cells on the next line Y 2 are then written. The structure of each subframe on each scanned line, employed in an opposed-discharge type PDP panel, is shown in Fig. 2, where are drawn voltage waveforms applied across the cells on horizontal lines Y 1 , Y 2 ... Y n , respectively. Each subframe is provided with a write period CYw during which a write pulse Pw, an erase pulse Pf and sustain pulses Ps are sequentially applied to the cells on each Y-electrode, and a sustain period CYm during which only sustain pulses are applied. The write pulse generates a wall charge in the cells on each line; and the erase pulse Pf erases the wall charge. However, for a cell to be lit a cancel pulse Pc is selectively applied to the cell's X-electrode X i concurrently to the erase pulse application so as to cancel the erase pulse Pf. Accordingly, the wall charge remains only in the cell applied with the cancel pulse Pc, that is, where the cell is written. Sustain pulses Ps are concurrently applied to all the cells; however, only the cells having the wall charge are lit. Gradation of visual brightness, i.e. a gray scale, is proportional to the number of sustain pulses that light the cells during a frame. Therefore, different time lengths of sustain periods CYm are allocated to the subframes in a single frame, so that the gradation is determined by an accumulation of sustain pulses in the selectively operated subframes each having different number of sustain pulses. A problem in the prior art methods is in that the second subframe must await the completion of the first subframe for all the lines. Therefore, if the number of the lines m = 400 and 60 frames per second to achieve 16 grades (n = 4), the time length T SF allowed to a single subframe period becomes as short as about 10 µs as an average. ( because T SF x 60 x 400 x 4 = 1 sec.) For executing the write period and the sustain period in such a short period, the driving pulses must be of a very high frequency. For example, in the case where the numbers of sustain pulses are 1, 2, 4 and 8 pairs in the respective subframes to achieve 16 grades, the driving pulses must be as high as 360 kHz as derived from: freq. = (1+2+4+8) x 60 x400 = 360 x 10 3 Hz. The higher frequency drive circuit consumes the higher power, and allows less margin in its operational voltage due to the storage time of the wall charge, particularly in an AC type PDP. Moreover, the high frequency operation, such as 360 kHz, may cause a durability problem of the cell. Therefore, the operation frequency cannot be easily increased, resulting in a difficulty in achieving the gradation. Furthermore, in the above prior art method, a write period CYw of a line must be executed concurrently to a sustain period CYm of another line. This fact causes another problem in that the brightness control, for example, the gradation control to meet gamma characteristics of human eye, cannot be desirably achieved. Further US-A-3 906 290 discloses a similar driving scheme and circuit for a flat matrix display with memory function. SUMMARY OF THE INVENTION It is a general object of the invention to provide a driving circuit which allows a high degree of gradation of visual brightness of a flat display panel by requiring less time for addressing cells to be lit. The present invention provides a driving circuit for providing a gradation of visual brightness of an image displayed on a matrix flat display panel during a frame time period, said matrix flat panel display being formed of a plurality of pixels at crossed points of the matrix, said pixels being arranged in a plurality of lines and each having a memory function, the visual brightness of a lit pixel in the displayed image depending upon a cumulative number of sustain pulses applied to said pixel during said frame time period, said frame time period being sub-divided into a plurality of subframes each comprising an address period and a display period subsequent to said address period, predetermined numbers of sustain pulses being allocated to the subframes of the frame such that any desired one of a plurality of gradations of visual brightness of a lit pixel can be obtained by activation of said pixel in a selection of the subframes, the driving circuit comprising: means for outputting data indicating, for each subframe of the frame time period, which pixels are to be activated in said sub-frame; and activating means for activating, during the address period within each subframe, the memory function of the pixels in response to said output data within respective subframes, and for lighting the activated pixels, during the display period of the respective subframes, by application of the predetermined number of sustain pulses allocated to that subframe to all the pixels; characterized in that the activating means is adapted to address said indicated pixels in said plurality of lines during an address period of a subframe, the address period of each subframe being common to the plurality of lines in the display. Features and advantages of the present invention will be more fully described hereinafter, with references being made to the accompanying drawings which form a part hereof, wherein like reference numerals refer to like parts throughout. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 schematically illustrates a prior art structure of a frame to drive each line of a matrix display panel; Figure 2 schematically illustrates waveforms in the prior art frames; Figure 3 illustrates a structure of a frame in a driving method implemented by the circuit of the present invention; Figure 4 illustrates waveforms of cell voltages applied across a cell on each line in a subframe; Figure 5 illustrates voltage waveforms applied to Y-electrodes and X-electrodes according to a first preferred embodiment of the present invention; Figure 6 schematically illustrates the structure of a flat display panel of an opposed-discharge type with which the first preferred embodiment of the invention may be used; Figure 7 illustrates voltage waveforms applied to Y-electrodes and X-electrodes according to a second preferred embodiment; Figure 8 schematically illustrates the structure of a flat display panel of a surface discharge type with which the second preferred embodiment of the invention may be used; and Figure 9 schematically illustrates a block diagram of a driving circuit configuration according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENT Figure 3 schematically illustrates a frame structure in a driving method implemented by a first preferred embodiment of the present invention. A frame FM to drive a single picture on a flat display panel, such as a PDP or an electroluminescent panel, is formed of a plurality of, for example, eight subframes SF1 to SF8. Each subframe is formed of an address period CYa and one of display periods CYi1 ... CYi8 subsequent to each address period CYa1 ... CYa8. In each address period CYa the cells to be lit are addressed by being written selectively from all the cells of the panel. Practical operation in the address period CYa, according to the present invention, will be described later in detail. Each display period CYi1 to CYi8 has different time length essentially having a ratio 1:2:4:8:16:32:64:128 so that different numbers of sustain pulses of same frequency are included in approximately proportional to this ratio in the display periods of the respective subframes. Visual brightness, i.e. the gradation of the brightness, of a lit cell is determined by the number of the sustain pulses accumulated for the single frame period. Thus, the gradation of 256 grades that is composed of the 8 bits can be determined for each cell by selectively operating one or a plurality of the eight subframes. Fig. 4 shows voltage waveforms applied across the cells of an opposed-discharge type PDP, where a discharge takes place between matrix electrodes coated with insulating layers on respective two glass panels facing each other. Layout of the matrix electrodes are schematically shown in Fig. 6, where for the present explanation of the invention the X-electrodes X i , X i+1 , X i+2 ... are data electrodes and the Y-electrodes Y j , Y j+1 , Y j+2 ... are scan electrodes. Cells C are formed at crossed points of the X-electrodes and the Y-electrodes. Operation of the address period CYa is hereinafter described in detail. Voltage waveforms applied to each of X-electrodes and the Y-electrodes to compose the cell voltages of Fig. 4 are shown in Fig. 5. A sustain pulse Ps1 is applied to all the Y-electrodes in the same polarity as the subsequent write pulse, in other words, the prior sequence of sustain pulses ends at a sustain pulse having the polarity of the write pulse. Sustain pulses are typically 95 volt high and 5 µs long. Next, approximately 2 µs later a write pulse Pw is applied to all the cells by applying a pulse Pw concurrently to all the Y-electrodes while the X-electrodes are kept at 0 volt, where the write pulse Pw is typically 150 volt high and 5 µs long adequate for igniting a discharge as well a forming a wall charge, as a memory medium, in all the cells. Immediately subsequent to the write pulse Pw, a second sustain pulse Ps2 having the polarity opposite to that of the write pulse Pw is applied to all the cells by applying the sustain pulse voltage Psx to all the X-electrodes while the Y-electrodes are kept at 0 volt, in order to invert the wall charge by which the subsequent erase pulse Pf can be effective. Next, an erase pulse Pf of typically 95 volt and 0.7 to 1 µs is applied sequentially to each of the Y-electrodes, which, in other words, are now scanned. Concurrently to the erase pulse application, a cancel pulse Pc having substantially the same level and the same width as the erase pulse Pf is selectively applied to an X-electrode connected to a cell to be lit, in order to cancel the function of the erase pulse Pf. Though a cell to which no cancel pulse is applied is lit once by the front edge of the erase pulse Pf; the pulse width is not so long as to accumulate an adequate wall charge to provide the memory function. That is, the wall charge is erased so that the cell is addressed not to be lit later. Now the writing operation, which has addressed the cells to be lit by canceling the function of the erase pulse, is completed throughout the panel. Thus, the address period is approximately 621 µs long for a 400-line picture. If sustain pulse Ps1 is not applied, in other words, if the display period ends at the sustain pulse having the polarity to the write pulse, the change in the cell voltage on application of the write pulse is as large as the sum of the voltage levels of the sustain pulse and the write pulse. This large change in the cell voltage may cause a deterioration of insulation layers of the cell. Thus, the sustain pulse Ps1 is preferably introduced into the address period, although this is not absolutely necessary. In address cycles, all the cell are lit three times by the sustain pulse Psy, the write pulse Pw and the erase pulse Pf; however, these lightings are negligible compared with larger number of the lightings in the display cycles. A first display period CYi1 provided subsequently to the first address period CYa1 is approximately 46 µs long. The sustain pulses are typically 5 µs wide having typically a 2 µs interval therebetween; therefore, three pairs of the sustain pulses of frequency 71.4 kHz are included in the first display period CYi1. The sustain pulses are applied to all the cells by applying the sustain pulse voltage Psy to all the Y-electrodes, and on the next phase by applying the sustain pulse voltage Psx to all the X-electrodes. Then, the cells having been addressed, i.e. having the wall charged, in the first address period CYa1 are lit at the by the sustain pulses in the subsequent subframe CYi1. The first subframe SF1 is now completed. In the second address period CYa2 of the second subframe SF2 subsequent to the first display period CYi1, the cells to be lit during the second display period CYi2 are addressed in the same way as the first address period. The second display period CYi2 subsequent to the second address period CYa2 is approximately 91 µs long to contain 6 pairs of sustain pulses. In the further subsequent subframes SF3 ... SF8, the operations are the same as those of the first and second subframes SF1 and SF2; however, the time length and the number of the sustain pulses contained therein are varied as calculated below: a frame period of 60 frames per second: 16.666 ms; address period as described above: 621 µs; total time length occupied by address periods of 8 subframes: 621 x 8 = 4,968 µs; time length allowed for 8 display periods: 16,666 - 4,968 = 11,698 µs; time length to be allocated to a minimum unit of 256 grades (represented by 8 bits): 11,698 / 256 = 45.67 µs; time length TL of each display period of other subframes: TL = 45.67 x 2, 4, 8, 16, 32, 64 and 128 µs, respectively; accordingly, display period time length: number of sustain pulse pairs: 1 st SF approx. 45 µs approx. 3 2 nd " 91 6 3 rd " 182 13 4 th " 365 26 5 th " 730 52 6 th " 1,461 104 7 th " 2,924 209 8 th " 5,845 418 total 831 frequency of sustain pulses having a 14 µs period: 1 / 14 µs = 71.4 kHz Accordingly, total number of sustain pulse pairs in a second is 831 x 60 = 49,860, which is sufficient to provide the brightness of the maximum gradation. Though in the above driving method implemented by the preferred embodiment the durations of the display periods are different to provide different numbers of sustain pulses, the display period may be allocated constantly to each subframe, for example, 11,698 µs / 8 = 1,462 µs during which different numbers of the sustain pulses are contained, respectively. For varying the sustain pulse numbers, the frequency may be varied for each subframe, such as 0.75, 1.5, 3, 6, 12, 24, 48 and 96 kHz, where the number of sustain pulse pairs are 1, 2, 4, 8, 17, n35, 70 and 140, respectively. In the constant time length 1,462 µs of the display periods, sustain pulses may be of a constant frequency, such as 96 kHz where unnecessary pulses are killed so as to leave necessary number of sustain pulses in each display periods. The operation of a second preferred embodiment of the present invention, applied to a surface discharge type PDP, is hereinafter described. The surface discharge type PDP is widely known , for example from Japanese Unexamined Patent Publication Tokukai Sho57-78751 and 61-39341, or schematically illustrated in Fig. 8. A plurality of X-electrodes X, each of which is parallel to and close to each of a plurality of Y-electrodes Y j , Y j+1 , Y j+2 , and address electrodes An, An+1, An+2 ... orthogonal to the X and Y electrodes are arranged on a surface of a panel. Electrodes crossing each other are insulated with an insulating layer. An address cell Ca is formed at each of the crossed points of the Y-electrodes Y j , Y j+1 , Y j+2 and the address electrodes An, An+1 , An+2 ... . Display cells Cd are formed between the Y-electrode and the adjacent X-electrode, close to the corresponding address cells Ca, respectively. Voltage waveforms applied to X-electrodes X, Y-electrodes Y j , Y j+1 , Y j+2 and address electrode An are shown in Fig. 7. An address period CYa is performed concurrently on all the Y-electrodes. In address periods, a write pulse Pw typically 5 µs long and 90 volt high is applied to all the X-electrodes while a first sustain pulse Psy1 that is opposite to the write pulse Pw, typically 5 µs long and 150 volt high, is applied to all the Y-electrodes, and the address electrodes are kept at 0 volt. Accordingly, all the display cells Cd are discharged by the summed cell voltage 240 V = 90 v + 150 V. Next, immediately subsequent to the write pulse a second sustain pulse Psx typically 5 µs long and 150 volt opposite to the write pulse Pw is applied to all the X-electrodes, so that a wall charge is generated in each display cell Cd and a part of the associated address cell Ca. Next, an erase pulse Pf typically 150 volt high and 3 µs long is applied sequentially to each of the Y-electrodes in the same manner as the first preferred embodiment. Concurrently to the erase pulse application, an address pulse Pa typically 90 volt high and 3 µs long is selectively applied to an address-electrode of a display cell Cd not to be lit later in the subsequent display period CYi1 in the same way as that of the first preferred embodiment, whereby the wall charge is erased. At a cell to which no address pulse is applied, the wall charge is maintained. Thus, the cells to be lit later are addressed throughout the panel by maintaining the wall charge in the selected cells. In a first display period CYi1 subsequent to the first address period CYa1 sustain pulses typically 150 volts high and 5 µs long are applied to all the cells by applying sustain pulses Psy to all the Y-electrodes and sustain pulses Psx alternately to all the X-electrodes. The cells having been addressed to have the wall charge are lit by the sustain pulsed. In the subsequent subframes the same operations are repeated as those of the first subframe except the time lengths of the display periods are different in each subframe, as the same way as that of the first preferred embodiment. The time length allocated to each subframe is identical to that of the first preferred embodiment. Accordingly, the same advantageous effects can be accomplished in the second embodiment, as well. Though in the above preferred embodiments the time length allocation is such a manner that the first subframe has the shortest display period and the last subframe has the longest display period, it is apparent that the order of the time length allocation is arbitrarily chosen. Fig. 9 shows a block diagram of a driving circuit of the present invention for providing gradation of the visual brightness of a flat matrix panel. An analog input signal S1 of a picture data to be displayed is converted by an A/D converter 11 to a digital signal D2. A frame memory 12 stores the digital signal D2 of a single frame FM output from A/D converter 11. A subframe generator 13 divides a single frame of picture data D2 stored in the frame memory 12 into plural subframes SF1, SF2 ... according to the required gradation level, so as to output respective subframe data D3. A scanning circuit 14 scans a Y-electrode driver 31 and an X-electrode driver 32 of the display panel 4. The scanning circuit 14 comprises a cancel pulse generator 21 to generate the cancel pulses Pc of the first preferred embodiment as well as the address pulses Pa of the second preferred embodiment; a write pulse generator 22 to generate the write pulses Pw; a sustain pulse generator 23 to generate the sustain pulses Ps; and a composer circuit 24 to compose these signals. A timing controller 15 outputs several kinds of timing signals for, such as process timing of subframe generator 13, output timing of cancel pulse generator, and termination timing of display period in each subframe. Operation of the gradation drive circuit is hereinafter described. The waveforms applied to the panel are the same as those already described above. In the case where the picture data each of whose pixels has n bit picture data is stored in frame memory 12 so that the picture is to be displayed by a 2 n gradation, subframe processor 13 sequentially outputs an n kinds of binary data D3, i.e. a pixel position data, of a picture to be exclusively formed of the respective bit of the gradation in the order of the least significant to the most significant. Depending on this picture data D3 the cancel pulse generator 21 outputs cancel pulses Pc, at the moment when a line is selected, to X-electrodes connected to the cells to be addressed to light on this selected Y-electrode. Timing controller 15 outputs a timing control signal so that the time length of each display period of subframes become a predetermined length in accordance with picture data D3 for the pixel position data output from subframe processor 13. Composer circuit 24 outputs the scan voltages shown in Fig. 5 by combining the pulse signals output from each pulse generator 21, 22 and 23 so that the address period CYa and the display period CYi can be executed in each subframe SF. The second means 14 specified in the claim is formed with cancel pulse generator 21, write pulse generator 22, sustain pulse generator 23 and composer circuit 24. In the first and second preferred embodiments, the erase/cancel pulses as short as 1 µs require only 600 µs for addressing the cells to be lit on the 400 lines after the concurrent application of the write pulse to all the cells. Thus, the time length required for the addressing operation is drastically decreased compared with the Fig. 1 prior art method where the write pulses Pw that is as long as 5 µs occupy about 2.2 ms for individually addressing the 400 lines. As a result, the time length allowed to the display periods may be as large as 11.7 ms, which is enough to provide a 256-grade gradation. Accordingly, the driving frequency can be lowered in accomplishing the same gradation level. The lower driving frequency lowers the power consumption in the driving circuit, in addition to allowing longer pulse width which provides more margin in the operation reliability. Moreover, the present invention solves the prior art problem where the driving circuit configuration was complicated because the write period CYw of a line had to be executed concurrently to the sustain period CYm of the other lines, whereby, the pulses had to be of very high frequency. Furthermore, in the present invention the number of sustain pulses in each subframe can be easily chosen because the display period CYi is completely independent from the address period CYa, where the cycle of the sustain pulses does not need to synchronize with the cycle of the address cycle. Owing to the above-described advantages, in the driving circuit of the present invention, the gradation can be easily controlled; the ratio of the time lengths of the display periods in the subframes can be arbitrarily and easily chosen so that the gradation can meet the gamma characteristics of the human eye; accordingly, the present invention is advantageous in the freedom in designing the circuit, the production cost, and the product reliability, as well. Though in the address period of the above preferred embodiments the addressing operation is carried out by canceling the once-written cells, it is apparent that the addressing method may be of other conventional methods where the writing operation is carried out only on the cells to be lit, without "writing-all" and "erasing-some-of-them". Even in this case, the same advantageous effect can be achieved as those of the above preferred embodiments. Though only a single example of the circuit configuration is disclosed above as a preferred embodiment, it is apparent that any other circuit configuration may be employed. Though only two examples of the driving waveforms are disclosed above in the preferred embodiments, it is apparent that other waveforms may be employed. Though only two examples of the electrode configuration of the display panel are disclosed above in connection with the preferred embodiments, it is apparent that other electrode configurations may be employed. Though in the above discussion of the preferred embodiments an AC-type PDP is referred to where the memory medium is formed of a wall charge, it is apparent that the present invention may be embodied in other flat panels such as: those where the memory medium is formed of a space charge (e.g. a DC-type PDP); an EL (electroluminescent) display device; or a liquid crystal device.

Claims: A driving circuit for providing a gradation of visual brightness of an image displayed on a matrix flat display panel (4) during a frame time period, said matrix flat panel display being formed of a plurality of pixels (C) at crossed points of the matrix, said pixels being arranged in a plurality of lines and each having a memory function, the visual brightness of a lit pixel in the displayed image depending upon a cumulative number of sustain pulses applied to said pixel during said frame time period, said frame time period (FM) being sub-divided into a plurality of subframes (SF) each comprising an address period and a display period subsequent to said address period, predetermined numbers of sustain pulses being allocated to the subframes of the frame such that any desired one of a plurality of gradations of visual brightness of a lit pixel can be obtained by activation of said pixel in a selection of the subframes, the driving circuit comprising: means (13) for outputting data indicating, for each sub-frame of the frame time period, which pixels are to be activated in said sub-frame; and activating means (14) for activating, during the address period within each subframe, the memory function of the pixels in response to said output data within respective subframes, and for lighting the activated pixels, during the display period of the respective subframes, by application of the predetermined number of sustain pulses allocated to that subframe to all the pixels; characterized in that the activating means is adapted to address said indicated pixels in said plurality of lines during an address period of a subframe, the address period of each subframe being common to the plurality of lines in the display. A driving circuit as recited in claim 1, wherein the activating means comprises means for generating sustain pulses at constant frequency during said display periods of subframes, the number of sustain pulses applied in a respective subframe being determined by the time length of said subframe. A driving circuit as recited in claim 1, wherein the activating means comprises means for generating sustain pulses at variable frequency during said display periods of subframes, the number of sustain pulses applied in a respective subframe being determined by the frequency of the sustain pulses applied during said subframe.

Inventors: SHINODA TSUTAE, SHINODA, TSUTAE, SHINODA, TSUTAE, C/O FUJITSU LTD.
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1991
Main classification: G09G3
IPC codes: G09G3