DRAM using barrier layer

Abstract: A memory cell comprising a MOSFET formed on a principle surface of a semiconductor substrate and an information storage capacitor having a storage electrode formed in or on the substrate so as to contact with a drain region of the MOSFET, and a capacitor electrode formed adjacent to the storage electrode with a capacitor insulator film being sandwiched between the storage electrode and the capacitor electrode. The storage electrode is connected to the drain region of the MOSFET through a thin barrier layer which is formed between the drain region and the storage electrode region so as to prevent impurities in the storage electrode from being diffused into the drain region.

Description: The present invention relates to a one-transistor type memory cell for use in DRAMs (dynamic random access memory), and more specifically to such a one-transistor type memory cell having an associated information storage capacitor. In the prior art, a one-transistor type memory cell having an associated information storage capacitor such as a stacked capacitor has been known, which includes a MOSFET (metal-oxide-semiconductor field effect transistor) formed in a device formation zone confined by a field oxide on a principle surface of a semiconductor substrate. The MOSFET includes a pair of diffusion regions which are formed in the principle surface of the semiconductor substrate, separately from each other so as to form a channel between the pair of diffusion regions. The pair of diffusion regions constitute a source region and a drain region of the MOSFET. An oxide layer is formed to cover the principle surface of the semiconductor substrate within the device formation zone, and a word line is formed on the oxide layer so as to pass above the channel formed between the source region and the drain region. Therefore, a portion of the word line passing above the channel formed between the source region and the drain region functions as a gate electrode, and a portion of the oxide layer between the gate electrode and the channel functions as a gate oxide. The gate electrode and the oxide layer which is not covered with the gate electrode, are covered with a lower interlayer insulator layer. An opening is formed in the lower interlayer insulator layer at a position of the drain region, and a storage electrode is formed to extend over the lower interlayer insulator layer and to contact with the drain region in the opening formed in the lower interlayer insulator layer. A capacitor electrode is formed over the storage electrode with a capacitor insulator film being sandwiched between the storage electrode and the capacitor electrode. Thus, a stacked capacitor is formed of the storage electrode, the capacitor insulator and the capacitor electrode. In addition, an upper interlayer insulator layer is formed to cover the stacked capacitor, and a bit line is formed on the upper interlayer insulator layer. This bit line is connected to the source region through a contact hole formed in the upper and lower interlayer insulator layer above the source region. Thus, the one-transistor type memory cell connected to the word line and the bit line is formed. In this one-transistor type memory cell, the storage electrode is ordinarily formed of a polysilicon. In order to cause the storage electrode to have sufficient conductivity, the polysilicon of the storage electrode has been diffused with impurities. In this diffusion process, the impurities diffuse not only into the storage electrode but also into the semiconductor substrate. As a result, another diffusion region has been inevitably formed within the drain region in the semiconductor substrate. This second diffusion region has a depth larger than that of the drain region. In other words, the second diffusion region extends into the semiconductor substrate beyond a bottom of the drain region. Formation of the above mentioned second diffusion region has given significant adverse affects. First, the impurities diffused into the semiconductor substrate will lower a threshold voltage of a parasitic transistor formed in proximity of the field oxide, so that a device isolation function is deteriorated. In addition, a threshold of a transistor connected to the word line is also decreased. This influence becomes further remarkable if a memory capacity is increased and a cell size is reduced. Therefore, the formation of the second diffusion region is inconvenient to microminiaturization of semiconductor memories. In view of the above problems, concentration of the impurities diffused to the storage electrode of the stacked capacitor has been restrained to a low level in the prior art. A MOS semiconductor device having a stacked capacitor is disclosed in US-A-48 97 709. In this device a barrier layer of titanium nitride is provided between a storage electrode of the capacitor and the substrate preventing diffusion of impurities from the capacitor electrode to the substrate. It is an object of the invention to provide a one-transistor type memory cell having an associated information storage capacitor of the trench type, in which diffusion of impurities from the storage electrode of the associated information storage capacitor to a source/drain diffusion region of the transistor is effectively suppressed or prevented. This object is achieved by a memory cell as defined in claim 1; the dependent claims are related to further developments of the invention. Preferably, the thin barrier layer is formed of silicon nitride, silicon oxide, or titanium nitride. In this case, the thin barrier layer is made to have a sufficiently thin thickness to ensure electric connection between the first diffusion region of the MOSFET and the storage electrode region of the associated capacitor. The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention with reference to the accompanying drawings. Figure 1 is a diagrammatic sectional view of a memory cell including a stacked capacitor; and Figure 2 is a diagrammatic sectional view of an embodiment of the memory cell in accordance with the present invention, including a trench capacitor. Referring to Figure 1, there is shown a diagrammatic sectional view of a memory cell. The shown memory cell is of a one-transistor type including a stacked capacitor. The shown memory cell includes a P-type silicon substrate 10 having a principal surface 12, which is an upper surface in the drawing. The principle surface 12 of the semiconductor substrate 10 is divided into a number of device formation zones confined by a field oxide 14, which is formed in a LOCOS (local oxidation of silicon) method. Only one of the device formation zones is shown in Figure 1 for simplification of the drawing, and is generally designated by Reference Numeral 16. Within the device formation zone 16, a pair of N-type diffusion regions 18 and 20 are formed in the principle surface 12 of the semiconductor substrate, separately from each other so as to form a channel 22 between the pair of diffusion regions 18 and 20. An oxide layer 24 is formed to cover the principle surface of a semiconductor substrate within the device formation zone 16, and a word line 26 formed of polysilicon is located on the oxide layer 24 to pass above the channel 22. Thus, the pair of diffusion regions 18 and 20 constitute a drain region and a source region of a MOSFET, respectively. A portion of the word line 26 passing above the channel 22 functions as a gate electrode of the MOSFET, and a portion of the oxide layer 24 above the channel 22 functions as a gate oxide. Preferably, the pair of N-type diffusion regions 18 and 20 are formed in self-alignment with the gate electrode 26, for example by an ion implantation using the gate electrode 26 as a mask. The gate electrode 26 and the oxide layer 24 which is not covered with the gate electrode 26, are covered with a lower interlayer insulator layer 28. An opening 30 is formed to pierce through the lower interlayer insulator layer 28 and the oxide layer 24 at a position of the drain region 18, and a barrier layer 32 is formed on an exposed upper surface of the drain region 18 within the opening 30. A storage electrode 34 formed of a polysilicon layer having a thickness of 200 nm (2000Å) is deposited over the lower interlayer insulator layer 28 to extend to a position directly above the gate oxide 26 on the one hand and to a position above the field oxide 28 on the other hand. This storage electrode 34 is in contact with the barrier layer 32 in the opening 30 formed in the lower interlayer insulator layer 28. In addition, a capacitor insulator film 36 is formed to completely cover the storage electrode 34, and a capacitor electrode 38 formed of a polysilicon layer is deposited to completely cover the capacitor insulator film 36, so that the capacitor insulator film 36 is sandwiched between the storage electrode 34 and the capacitor electrode 38. Thus, a stacked capacitor is formed of the storage electrode 34, the capacitor insulator 36 and the capacitor electrode 38. In addition, an upper interlayer insulator layer 40 is formed to completely cover the stacked capacitor and the lower interlayer insulator layer 28, and a bit line 42 formed of for example tungsten silicide is located on the upper interlayer insulator layer 40. This bit line 42 is connected to the source region 20 through a contact hole 44 which is formed to pierce through the upper and lower interlayer insulator layers 40 and 28 above the source region 20. Thus, the one-transistor type memory cell connected to the word line and the bit line is formed. The barrier layer 32 is formed of, for example, a silicon nitride layer having a thickness of 4 nm (40Å), which can be formed by a thermal nitridation in which the substrate is heated in an atmosphere of NH₃ after the opening 30 is formed to pierce through the lower interlayer insulator layer 28 and the oxide layer 24 so as to expose an upper surface of the drain region 18 within the opening 30. Interposition of the barrier layer 32 between the drain region 18 and the storage electrode 34 prevents diffusion of impurities into the P-type silicon substrate 10, even if impurity, for example, phosphorus is sufficiently diffused into the storage electrode 34 until the storage electrode 34 has a sheet resistance of 20Ω/□. On the other hand, the thickness of 4 nm (40Å) in the silicon nitride barrier layer 32 ensures sufficient electrical connection between the drain region 18 and the storage electrode 34. The barrier layer 32 can be formed of not only silicon nitride but also a material, such as silicon oxide or titanium nitride, that not only functions as a barrier against impurity diffusion but also ensures electrical connection between the drain region 18 and the storage electrode 34. Referring to Figure 2, there is shown a diagrammatic sectional view of an embodiment of the memory cell in accordance with the present invention. The shown memory cell is of a one-transistor type including including a trench capacitor. In Figure 2, elements corresponding or similar to those shown in Figure 1 are given the same Reference Numerals, and explanation thereof will be omitted for simplification of explanation. As seen from Figure 2, a vertical trench 50 is formed between the field oxide 14 and the drain region 18 of the MOSFET. Inner side and bottom surfaces of the trench 50 are covered with an insulating layer 52. A side surface of the insulating layer 52 is covered with a polysilicon storage electrode 54. In addition, a bottom surface of the insulating layer 52 and an inner side surface and a top surface of the polysilicon storage electrode 54 are completely coated with a capacitor insulator film 56, and an inner space defined by the capacitor insulator film 56 is filled with a polysilicon capacitor electrode 58, which further extends over a top portion of the capacitor insulator film 56 and the field oxide 14. Thus, a capacitor formed of the storage electrode 54, the capacitor insulator film 56 and the capacitor electrode 58, is formed in the vertical trench 50. In the capacitor thus formed in the vertical trench 50, the insulating layer 52 formed on the inner side and bottom surfaces of the trench 50 functions to prevent electric charges accumulated in the storage electrode 54 from escaping into the substrate 10. In addition, a barrier layer 60 is formed to extend around and along an upper edge portion of the trench 50, so that the polysilicon storage electrode 54 is connected through the barrier layer 60 to the drain region 18 and the semiconductor substrate under the field oxide 14 is isolated from the polysilicon storage electrode 54 by the barrier layer 60. This barrier layer 60 serves to prevent impurities included in the storage electrode 54 from being diffused into the semiconductor substrate 10 under the field oxide 14. Therefore, adjacent storage electrodes are prevented from being short-circuited to each other by impurities diffused from the adjacent storage electrodes. This means that it is possible to diffuse a sufficient concentration of impurities into the storage electrodes, and therefore, it is possible to further microminiaturize the memory cell. As seen from the above description of the embodiment with reference to the accompanying drawings, formation of the barrier layer between the diffusion region of the MOSFET and the storage electrode of the capacitor prevents diffusion of impurities from the storage electrode into the semiconductor substrate and/or the diffusion region of the MOSFET. Therefore, it is possible to sufficiently diffuse impurities into the storage electrode of the capacitor, without lowering a threshold voltage of a parasitic transistor formed in proximity of the field oxide, and without lowering the threshold of the transistor connected to the word line. As a result, distance between the field oxide, the storage electrode of the capacitor and the transistor can be reduced. Accordingly, this is very effective for microminiaturization of the memory cell for the speed-up and the increase of integration density of the semiconductor memory.

Claims: A memory cell comprising: a semiconductor substrate (10); a MOSFET including first and second diffusion regions (18, 20) which are formed in a principle surface of said semiconductor substrate, separately from each other so as to form a channel (22) between said first and second diffusion regions, said MOSFET also including an oxide layer (24) formed to cover said principle surface of said semiconductor substrate above said channel (22), and a gate electrode (26) formed on said oxide layer above said channel; and a capacitor having a storage electrode (54) formed to contact said first diffusion region (18), and a capacitor electrode (58) formed adjacent to said storage electrode with a capacitor insulator film (56) being sandwiched between said storage electrode and said capacitor electrode, said storage electrode being electrically connected to said first diffusion region (18) through a thin barrier layer (60) which is formed between said first diffusion region (18) and said storage electrode (54) so as to prevent impurities in said storage electrode from being diffused into said semiconductor substrate, a vertical trench (50) formed between field oxide (14) and said first diffusion region (18) of said MOSFET, said vertical trench (50) having inner side and bottom surfaces covered with an insulating layer (52), and wherein said storage electrode (54) is formed to cover a side surface of said insulating layer in said trench, and a bottom surface of said insulating layer and an inner side surface and a top surface of said storage electrode are completely coated with said capacitor insulator film (56), an inner space defined by said capacitor insulator film being filled with said capacitor electrode (58), so that a capacitor formed of said storage electrode (54), said capacitor insulator film (56) and said capacitor electrode (58) is formed in said vertical trench (50), and said barrier layer (60) is formed to extend around and along an upper edge portion of said trench, so that said storage electrode (54) is electrically connected through said barrier layer (60) to said first diffusion region (18) and said semiconductor substrate (10) under said field oxide is isolated from said storage electrode by said barrier layer. A memory cell claimed in Claim 1 wherein said barrier layer (60) is formed of silicon nitride, silicon oxide, or titanium nitride. A memory cell claimed in Claim 1 wherein said barrier layer is formed of a silicon nitride layer having a thickness of 4 nm (40 Å), and said storage electrode is formed of polysilicon doped with impurities.

Inventors: NARITA KAORU C O NEC CORPORATI, NARITA, KAORU, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: H01L27
IPC codes: H01L27, H01L21