Multi-level logic input circuit

Abstract: A multi-level logic input circuit is composed of a first (R1) and a second resistor (R2), a first polarity current mirror circuit (Q1, Q3, Q5) whose input is connected to the first resistor and which has a plurality of output nodes, and a second polarity current mirror circuit (Q2, Q4, Q6) whose input is connected to the second resistor and which has a plurality of output nodes. The output nodes of the first polarity current mirror circuit are connected correspondingly with the output nodes of the second polarity current mirror circuit. The output nodes are led out as a plurality of output terminals. At least one of the output nodes of each of the current mirror circuits has a current ratio different from that in all the remaining output nodes thereof. The multi-level logic input circuit is simple in its configuration, and it enables to realize multi-level inputs with small current consumption.

Description: BACKGROUND OF THE INVENTION (1) Field of the Invention The present invention relates to a logic circuit and, more particularly, to a logic circuit to which a digital value of multi-level logic data is inputted and from which a digital value of two-valued logic data is outputted. (2) Description of the Prior Art Only the input part is often made to have a multi-level logic input configuration and this is done for enabling to input data of as many different states as possible within the limited number of chip pins of an LSI (Large-scale integrated circuit). For example, where there are provided two input pins for receiving the input signals of three levels including an intermediate level (M) in addition to a low level (L) and a high level (H), it is possible to have them deal with nine different combinations of inputs (3 × 3 = 9), which combinations are larger than twice as compared to those in an ordinary two-level (or two-valued) input configuration (2 × 2 = 4). Conventionally, as shown in Fig. 1A, the inputs V I and each of the threshold values V 1 , V 2 are compared by a comparator 1 and a comparator 2 which have different threshold values with each other and the results are outputted to output terminals V 01 and V 02 as two-valued logic data. Fig. 1B is a truth table for such inputs and outputs. As such comparators 1 and 2, there have often been used a pair of differential amplifiers or a pair of inverters having different threshold values with each other. In such arrangement, in order to be able to achieve three different level inputs, that is, to have the input connected to ground (L), allowed to be in an open state (M), and connected to a power source (H), a bias voltage corresponding to the potential of intermediate level (M) is applied by resistors R 1 and R 2 . Generally, in the case of the comparator using a differential amplifier, it is necessary that the constant current be always supplied to the comparators and this results in such disadvantages that power is always consumed accordingly and also that such circuitry as a load circuit becomes complex in order to secure an appropriate dynamic range in the outputs. In the case of the inverters having different threshold values, power is not consumed in the CMOS inverters when the input level applied thereto is "L" or "H". However, there is a defect that, when the input level applied thereto is at the intermediate level (M), an N-channel transistor and a P-channel transistor constituting the inverter are caused to be turned on at the same time thereby allowing a large current to flow therein as the so-called "through current". Moreover, a three state to binary converter having an input connected to a string of resistors and two outputs connected to an inverter circuit is disclosed in JP 5 481 736. SUMMARY OF THE INVENTION Therefore, the present invention aims at providing a multi-level logic input circuit which is simpler in its construction and which can operate under low power consumption as compared with the conventional ones. In summary, the multi-level logic input circuit according to the present invention adopts two current mirror circuits whereby the desired multi-level logic input is made possible. According to one aspect of the invention, there is provided a multi-level logic input circuit which comprises: a first resistor whose one end is connected to an input terminal; a second resistor whose one end is connected to the input terminal; a first polarity current mirror circuit whose input is connected to the other end of the first resistor and which has a plurality of first output nodes; and a second polarity current mirror circuit whose input is connected to the other end of the second resistor and which has a plurality of second output nodes, the first output nodes of the first polarity current mirror circuit being connected correspondingly with the second output nodes of the second polarity current mirror circuit, all of the output nodes being led out as a plurality of output terminals, and at least one of the output nodes of each of the current mirror circuits having a current ratio different from that in all the remaining output nodes thereof. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will be apparent from the following description of preferred embodiments of the invention explained with reference to the accompanying drawings, in which: Fig. 1A is a circuit diagram showing a conventional multi-level logic input circuit; Fig. 1B is a truth table of inputs and outputs in the conventional circuit shown in Fig. 1A; and Fig. 2 is a circuit diagram of a multi-level logic input circuit of a first embodiment according to the invention; Fig. 3 is a circuit diagram of a multi-level logic input circuit of a second embodiment according to the invention; and Fig. 4 is a circuit diagram of a multi-level logic input circuit of a third embodiment according to the invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Throughout the following explanation, the same reference symbols or numerals as those of the conventional circuit shown in Fig. 1A refer to the same or similar elements of the multi-level logic input circuits according to the invention. Fig. 2 shows a multi-level logic input circuit of a first embodiment according to the invention. An input terminal V I is connected to a junction node of serially connected resistors R 1 and R 2 which are respectively connected to transistors Q 1 and Q 2 each constituting an input stage of the current mirror circuit concerned. When the input terminal V I is at its open state, a bias current is flowing through a route from the power source V CC to the transistor Q 1 , the resistors R 1 , R 2 and the transistor Q 3 . It is assumed that the current ratios of the current mirror circuits (or the ratios of sizes of the transistors or the ratios of conductance gm thereof) are as follows: Q 1 : Q 3 : Q 5 = 1 : 1 : 2, Q 2 : Q 4 : Q 6 = 1 : 2 : 1. When the input terminal V I is at its open state, since the current-sink capability of the transistor Q 4 is larger than that of the transistor Q 3 , the transistor Q 3 causes the same current as in the transistor Q 1 to flow at a pentode characteristic region and the transistor Q 4 causes the same current as in the transistor Q 3 to flow at a triode characteristic region whereby the transistor Q 4 turns to a small drain-source voltage state and, consequently, an output terminal V 02 becomes "L". Likewise, the terminal V 01 becomes "H". Here, the current consumption may be given by the following formula: 3 × V CC - V GS1 - V GS2 R 1 + R 2 wherein V GS1 and V GS2 represent gate-source voltages of the transistors Q 1 and Q 2 , respectively. Each of such voltages is roughly in the order of 1 V. Next, assuming that the input terminal V I is at low potential (L) or is grounded, the current which flows in the current mirror circuit formed by the transistors Q 2 , Q 4 and Q 6 becomes substantially 0 (zero). On the other hand, the current which flows in the transistor Q 1 is given by the following formula: V CC - V GS1 R 1 This current is substantially twice as large as that in the state wherein the input terminal V I is at the open state, and this current causes the transistors Q 3 , Q 5 to turn on. However, since no current flows to the transistors Q 4 , Q 6 , no current flows to these transistors Q 3 , Q 5 , either, so that both the output terminal V 01 and the output terminal V 02 become "H". Likewise, if the input V I is "H", the transistors Q 1 , Q 3 and Q 5 turn off and the transistors Q 2 , Q 4 and Q 6 turn on, so that both the output terminal V 01 and the output terminal V 02 become "L". The consumption current at this time may be obtained by the following formula: V CC - V GS2 R 2 In the above respective cases, if the amount of current which flows to the resistor R 1 or R 2 is excluded (this current is also flowing in the conventional circuit shown in Fig. 1A), the current of consumption when the input terminal V I is at "L" or "H" is substantially zero and that when the input terminal V I is at the intermediate level (M) is about three times thereof (in the order of 3/2 times of the current which flows to the resistor under the low level "L" or the high level "H"). This value is a value sufficiently small as compared with the through current with the CMOS inverters. Fig. 3 shows an arrangement wherein the N-channel MOS transistors shown in Fig. 2 are respectively replaced by NPN transistors, and the P-channel MOS transistors by PNP transistors. This circuit formed by the bipolar transistors operates and functions basically the same as in the circuit formed by the MOS field effect transistors shown in Fig. 2. Since there is a possibility that the transistors Q 3 , Q 5 or the transistors Q 4 , Q 6 enter into a saturated state (triode characteristic region) at the same time, it is desirable that a series resistor be provided to each of the bases of the transistors concerned in order to lessen the influence from the current hogging phenomenon. Fig. 4 shows an example of 5-level logic input circuit wherein the output nodes of the P-channel type current mirror circuit and the output nodes of the N-channel type current mirror circuit shown in Fig. 2 respectively increased in their numbers are correspondingly connected together, which lead to the respective output terminals as output terminals V 01 , V 02 , V 03 and V 04 . Here, it is assumed that the current ratios are, as example, as follows: Q 1 : Q 3 : Q 5 : Q 7 : Q 9 = 1 : 1/2 : 1 : 2 : 5 Q 2 : Q 4 : Q 6 : Q 8 : Q 10 = 1 : 5 : 2 : 1 : 1/2. When the input is "H", the transistors Q 2 , Q 4 , Q 6 , Q 8 and Q 10 all turn off, so that the outputs V 01 , V 02 , V 03 and V 04 all turn to "H". Likewise, when the input terminal V I is at "H", the output terminals V 01 , V 02 , V 03 , and V 04 all turn to "L". Further, it can be readily understood that, when the input terminal V I is at the open state, the output terminals V 01 and V 02 turn to "H" but the output terminals V 03 and V 04 turn to "L". Next, when a bias is applied to the input terminal V I in such a way that the input terminal V I receives a voltage slightly lower than the voltage (normally this is selected to be nearly V CC /2) under the open state thereof and yet the transistors Q 2 , Q 4 , Q 6 and Q 10 do not turn off, the current-sink capability of the transistors Q 6 , Q 8 and Q 10 is evidently smaller than the current-force capability of the transistors Q 5 , Q 7 and Q 9 , so that the output terminals V 01 , V 02 and V 03 relating thereto become "H". A current is flowing in the transistor Q 2 although the amount thereof is small and the current-sink capability of the transistor Q 4 can be up to five times the current of the transistor Q 2 . As long as this value is larger than the current-force capability of the transistor Q 3 , the output terminal V 04 can be maintained at "L" level. It should be noted that the input level of "slightly low" can be decoded. Likewise, it is possible to decode the input level of "slightly high" by the transistors Q 9 and Q 10 and to output the decoded result at the output terminal V 01 . In this way, the circuit of this third embodiment can deal with the input of five levels applied to the input terminal V I , namely, a low level (GND), a slightly low level, an intermediate value (open state), a slightly high level, and a high level (V CC ). As explained above, in the circuit according to the present invention (without the bias circuit portion being taken into consideration), a 3-level logic input circuit can be realized by only six transistors wherein the consumption of current is zero at the low level (L) input or the high level (H) input, and it can be in the order of the amount corresponding to the consumption current flowing in the above mentioned bias circuit portion at the intermediate level (M) input. Also, there is no possibility for a large through current to flow unlike in a conventional arrangement using an inverter. Further, unlike in a conventional arrangement using a differential amplifier, there is no need for the bias current to be constantly supplied to such differential circuit whether under the low level input state or under the high level input state.

Claims: A multi-level logic input circuit comprising: a first (R1) resistor whose one end is connected to an input terminal (V I ); a second (R2) resistor whose one end is connected to said input terminal; characterized by comprising: a first polarity current mirror circuit (Q1, Q3, Q5) whose input is connected to the other end of said first resistor and which has an n number of first output nodes; and a second polarity current mirror circuit (Q2, Q4, Q6) whose input is connected to the other end of said second resistor and which has an n number of second output nodes in common with that of said first output nodes; said first output nodes of the first polarity current mirror circuit being connected correspondingly with said second output nodes of the second polarity current mirror circuit, all of said output nodes being led out as a plurality of output terminals (V 01 , V 02 , V 03 , V 04 ), and at least one of said output nodes of each of said current mirror circuits having a current ratio different from that in all the remaining output nodes thereof. A multi-level logic input circuit according to claim 1 in which said first polarity current mirror circuit comprises P-channel MOS transistors and said second polarity current mirror circuit comprises N-channel MOS transistors. A multi-level logic input circuit according to claim 1 in which said first polarity current mirror circuit comprises PNP transistors and said second polarity current mirror circuit comprises NPN transistors. A multi-level logic input circuit according to claim 1 in which said n number of said first output nodes and said second output nodes is two. A multi-level logic input circuit according to claim 1 in which said n number of said first output nodes and said second output nodes is four.

Inventors: MITSUTOSHI SUGAWARA, MITSUTOSHI, SUGAWARA
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: H03M5
IPC codes: H03M5, H03K19