Processor element for calculating accumulation of data, processing unit, and processor

Abstract: A processor element having a shifter, input data selectors, an adder/subtractor, and output registers computes the cumulative absolute difference between two series of inputs, or computes a term in Booth's multiplication algorithm. A processing unit having N of these processor elements connected in parallel computes an inner product, or computes N cumulative absolute differences simultaneously. A processing unit having M of these processing units connected in parallel multiplies M x M matrices, or computes M x N cumulative absolute differences simultaneously. (M and N are integers greater than one.)

Description: The present invention relates to digital signal processing, more particularly to a processor element, processing unit, and processor adapted for efficient execution of operations such as finding a cumulative absolute difference. Arithmetic digital signal processing circuits are well known and as examples of related prior art, reference is directed to JP-A-58132861, DE-A-1524163 and EP-A-0180340. Since digital signal processing is multiplication-intensive, the prior art abounds in processor elements that combine a hardware multiplier with other arithmetic and logic facilities such as an adder. Such processor elements (PEs) have often been assembled into array processors in which the individual PEs can operate in parallel for high-speed vector and matrix arithmetic, or can be pipelined to carry out more complex operations that a single PE cannot perform alone. An example is a prior art array processor developed for use in telephone apparatus that transmits compressed video images. The processor is configured as a four-by-four array of PEs, each comprising a multiplier and an adder. Operating concurrently and independently, the sixteen PEs perform 4 x 4 matrix operations. In addition, the four PEs in a row of the array can be interconnected to operate as a pipeline. One operation for which the PEs must be pipelined is that of finding the cumulative absolute difference between two series of inputs, an operation necessary in image compression by the motion compensation method. In each pipeline the first PE finds the difference between two inputs, the second PE takes the absolute value of the difference, and the third PE adds the absolute value to the cumulative total. The fourth PE has no function. One problem with this prior art array processor is that only four pipelines can operate in parallel. In the standard motion-compensation method, detection of a single motion vector requires the determination of a large number of cumulative absolute differences, so it would be useful if cumulative absolute difference operations could be performed more than four at a time. Another problem is that since each PE has its own hardware multiplier, the PEs are large in size. This limits the number of PEs that can be included in an array, especially when the array is implemented on a single semiconductor ship (as in the example above). A further problem is that an array processor of the above type performs efficiently only in computations such as matrix multiplication that benefit from parallel multiply-add operations. In the cumulative absolute difference operation no use is made of the multiplier in each PE, even though the multiplier accounts for a large part of the PE's circuitry. Still another problem is that pipelining itself tends to be inefficient. In the example above, one PE in each pipeline was left idle. With a view to overcoming these problems, the invention provides a processor element for calculating cumulative absolute difference comprising: arithmetic means coupled to receive a first signal and a second signal; a first selector for selecting between a first input signal and a first result signal fed back from the arithmetic means to provide said first signal; a second selector for selecting between a second input signal and a second result signal fed back from the arithmetic means to provide said second signal; and control means for applying control signals to the selectors to control their selection of inputs, and to the arithmetic means to control whether it performs addition or subtraction, the control means being operable so that during a first cycle of a cumulative absolute difference phase : the first selector provides the first input signal as said first signal, the second selector provides the second input signal as said second signal, and the arithmetic means subtracts the first signal from the second signal to produce a first result signal, and during a second cycle of said cumulative absolute difference phase: the first selector outputs said first result signal as said first signal, the second selector outputs the second result signal as said second signal, said second result signal being the cumulative absolute difference obtained in the previous cumulative absolute difference phase, and if the first result signal is negative then the arithmetic means subtracts the first signal from the second signal to produce a new second result signal, else the arithmetic means adds the first signal and the second signal to produce a new second result signal. The invention also includes a processing unit that includes a plurality of the inventive processing elements. The invention also extends to a processor for M x M matrices (where M is an integer > 1), comprising an input bus group; an output bus group; and M of the processing units coupled between the input bus group and the output bus group. In order that the invention may be more fully understood an embodiment thereof will now be described by way of example with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of a processor element in accordance with the invention; Fig. 2 is a timing chart showing how the processor element shown in Fig. 1 calculates a cumulative absolute difference; Fig. 3 is a timing chart of the cumulative absolute difference operation; Fig. 4 is a block diagram of a processing unit according to the invention; Fig. 5 is a block diagram of the last-stage accumulator in Fig.4 Fig. 6 is a timing chart of the first part of a multiplication operation performed by the processing unit, Fig. 7 is a shifting chart for the second part of the multiplication operation; Fig. 8 is a timing chart of the second part of the multiplication operation; Fig. 9 is a block diagram of processor according to the invention; Fig. 10 shows how the novel processor carries out matrix multiplication; Fig. 11 is a block diagram of a processor element adapted for performing two series of addition operations rapidly; and Fig. 12 is a timing chart of the two addition operations. A processor element, processing unit, and processor according to the invention will be described below with reference to the drawings. The novel devices perform cumulative absolute difference, inner product (cumulative multiply-add), and matrix multiplication operations. The drawings are intended to illustrate the invention but not to limit its scope, which should be determined from the appended claims. A description will first be given of a processor element (PE) that can calculate and accumulate absolute differences, perform operations useful in Booth's multiplication algorithm, and can execute various other arithmetic and logic operations. With reference to Fig. 1, a PE 100 has a control circuit 110 that receives a mode signal MD, a clock signal CK, three bits of input data X 2k+1 , X 2k , X 2k-1 , and a carry output signal CO, and generates therefrom six control signals S0, S1, S2, S3, S4, and S5. The mode signal and clock signal are supplied from external sources. The carry output CO is generated from within the PE 100 as described later. The three bits X 2k+1 , X 2k , and X 2k-1 are part of third input data X supplied from an input bus not shown in Fig. 1. The superscripts 2k+1, 2k, and 2k-1 denote bit positions in X, rather than exponents. The control circuit 110 comprises, for example, logic circuits and a read-only memory (ROM). Structural details will be omitted, since those skilled in the art will readily understand how the control circuit 110 can be constructed from the description of the operation of the PE given later. Some of the signal lines may comprise more than one physical line: for example, the control signal S0 has at least three states, so its signal line may comprise two physical lines or more; the mode signal line may also comprise several lines, enabling the PE to operate in various modes for different purposes. The PE also comprises a shifter 120, a first data selector 130, and a second data selector 140. The shifter 120 receives first input data Y and the control signal S0 and produces as output either the value zero or the first input data Y shifted by a certain number of bits, controlled by the control signal S0. In particular, the shifter 120 can perform a zero-bit shift, thereby reproducing the input data Y, and a one-bit left shift, thereby multiplying the input data Y by two. The first and second data selectors 130 and 140 are two-to-one multiplexers. The first data selector 130 receives the output of the shifter 120, first result data R1, and the control signal S1, selects the first result data R1 or the output of the shifter 120 according to the control signal S1, and produces the selected data as output. The second data selector 140 receives second input data M, second result data R2, and the control signal S2, selects either the second input data M or second result data R2 according to the control signal S2, and produces the selected data as output. The outputs of the first and second data selectors 130 and 140 are fed to an arithmetic means 150 comprising a bit inverter 151 and an adder 152. The bit inverter 151 and the adder 152 both receive the control signal S3. The control signal S3 has two values, which can conveniently be considered to be zero and one. When S3 is zero, the arithmetic means 150 adds the outputs of the first data selector 130 and the second data selector 140 as follows: the bit inverter 151 passes the output of the first data selector 130 without alteration to the adder 152; the adder 152 adds the output of the bit inverter 151 to the output of the second data selector 140 and the value (zero) of the control signal S3. When the control signal S3 is one, the arithmetic means 150 subtracts the output of the first data selector 130 from the output of the second data selector 140 as follows: the bit inverter 151 inverts all bits in the output of the first data selector 130 and passes the inverted result to the adder 152; the adder 152 adds the output of the bit inverter 151 to the output of the second data selector 140 and the value (one) of the control signal S3. The control signal S3 thus functions as a carry input CI to the adder 152. The adder 152 also generates the carry output CO furnished to the control circuit 110. The carry output CO is the sign bit of the result produced by the adder 152, taking the value one when the result is negative and the value zero when the result is positive or zero. The output of the adder 152 is fed to a first register 160 and a second register 170 and stored therein under control of the signals S4 and S5, respectively. The value stored in the first register 160 is provided as the first result data R1 to the first data selector 130. The value stored in the second register 170 is supplied as the second result data R2 to the second data selector 140, and is also supplied to the outside as the output of the PE 100. The second register 170 thus functions as an output register. Next the operation of the PE 100 in various modes will be described. In a first mode, the PE 100 receives a series of first and second input data Y i and M i and calculates the cumulative absolute difference D between them, which can be expressed mathematically as: This operation is used, for example, in block matching in image processing, to find the block that most nearly matches a given block. In this first mode the control signal S0 always causes the shifter 120 to reproduce the first input data Y i without alteration. The other control signals alternate between two stages. In the first stage, the first data selector 130 selects the first input data Y i as received from the shifter 120, the second data selector 140 selects the second data M i , and the control signal S3 is in the zero state. At the end of the first stage, the control signal S4 causes the first register 160 to store the sum produced by the adder 152. In the second stage the first data selector 130 selects the first result data R1, the second data selector 140 selects the second result data R2, and the control signal S3 has the same value as the carry output CO in the preceding first stage. At the end of the second stage, the control signal S5 causes the second register 170 to store the result produced by the adder 152. The calculation of a cumulative absolute difference is illustrated in Fig. 2. The operation is divided into machine cycles MC1, MC2, ..., each corresponding to one period of the clock signal CK. At the beginning of the operation the second register 170 is initialized to zero as shown at the bottom of Fig. 2. In the first machine cycle MC1 the PE 100 executes first-stage operations. Control signals S1 and S2 are low, causing the first and second data selectors 130 and 140 to select input data Y 1 and M 1 . Control signal S3 (not shown) is one, causing the bit inverter 151 and the adder 152 to execute the operation M 1 - Y 1 . At the end of MC1 the first register 160 latches the value M 1 - Y 1 on the rising edge of the control signal S4. In the second machine cycle MC2 the PE 100 executes second-stage operations. Control signals S1 and S2 are high, causing the first and second data selectors 130 and 140 to select the first and second register outputs M 1 - Y 1 and zero. If M 1 - Y 1 is negative then the carry output in the preceding first stage was one, so the control signal S3 is one and the bit inverter 151 and the adder 152 execute the operation 0 - (M 1 - Y 1 ). If M 1 - Y 1 is positive or zero then the carry output in the preceding first stage was zero, so the control signal S3 is zero and the bit inverter 151 and the adder 152 execute the operation 0 + (M 1 - Y 1 ). In either case the bit inverter 151 and the adder 152 execute the operation 0 + |M 1 - Y 1 |, the result of which is denoted Σ 1 in the drawing. At the end of the second machine cycle MC2 this result Σ 1 is stored in the second register 170 on the rising edge of the control signal S5. In the third machine cycle MC3 the PE 100 receives new input data Y 2 and M 2 and executes stage-one operations, storing the difference M 2 - Y 2 in the first register 160. In the fourth machine cycle MC4 the PE 100 executes stage-two operations, adding the absolute value of M 2 - Y 2 to the contents Σ 1 of the second register 170 and storing the result Σ 2 = Σ 1 + |M 2 - Y 2 | = |M 1 - Y 1 | + |M 2 - Y 2 | in the second register 170. Operation continues in this way, producing at the end of the sixth machine cycle MC6 the cumulative absolute difference of three pairs of first and second input data Σ 3 = |M 1 - Y 1 | + |M 2 - Y 2 | + |M 3 - Y 3 |. In this way an operation that employed a pipeline of three comparatively large processor elements in the prior art is carried out by a single novel processor element of much smaller size. In Fig. 2 each stage of operation occupied one full clock period, so data could be input only in every other clock period. An alternative and preferable scheme, illustrated in Fig. 3, is to have the PE 100 switch between the first-stage and the second-stage operations at every half-period of the clock signal, the first stage being executed when the clock signal CK is low and the second stage when CK is high. Due to its simple structure the PE 100 can easily operate at this higher speed, and data can be input in every clock cycle, which is more convenient. Next a second mode of operation, useful in computing an inner product by Booth's multiplication algorithm, will be described. In this mode the PE 100 receives first (multiplicand) data Y and three bits of third (multiplier) data X, manipulates Y according to the X bits, and accumulates the results. The control signals S0 and S3 are controlled according to X. The control signals S1 and S2 are held constant, causing the first data selector 130 always to select the output of the shifter 120 and the second data selector 140 always to select the second result data R2. The result data produced by the adder 152 are always stored in the second register 170, which initially holds the value zero. The control signals S0 and S3 are arranged so that the output of the adder 152 is equal to: R2 + (-2X 2k+1 + X 2k + X 2k-1 ) · Y Table 1 summarizes the outputs of the shifter 120 as controlled by S0, the values of S3, and the resulting output of the adder 152. X 2k+1 X 2k X 2k-1 Shifter output S3 Adder output 0 0 0 0 0 R2 0 0 1 Y 0 R2+Y 0 1 0 Y 0 R2+Y 0 1 1 2Y 0 R2 + 2Y 1 0 0 2Y 1 R2 - 2Y 1 0 1 Y 1 R2 - Y 1 1 0 Y 1 R2 - Y 1 1 1 0 1 R2 In addition to the two modes described above, the PE 100 can operate in various other modes too obvious to need detailed description. For example, it can produce the sum or difference of first and second input data by having the first and second data selectors always select Y and M and setting the control signal S3 to zero for M + Y, or to one for M - Y. Other possible arithmetic and logic operations include, but are not limited to, Σ Y i (cumulative sum of first input data), Σ M i (cumulative sum of second input data), |Y| (absolute value of first input data), |M| (absolute value of second input data), NOT Y (logical negation of first input data), and NOT M (logical negation of second input data). If necessary, circuits for executing AND and OR logic operations can be added to the arithmetic means 150, or the arithmetic means 150 can be replaced by a simple integer arithmetic and logic unit of the type commonly employed in digital signal processors and microprocessors. If the usage of the PE 100 is restricted, its structure can be further simplified. For example, if the only purpose is to calculate a cumulative absolute difference, the shifter 120 can be eliminated. If only a single absolute difference is required, the second register 170 can be eliminated and the contents of the first register 160 provided as external output. Next a processing unit (PU) will be described that comprises a plurality of the novel processor elements. This processing unit can use its processor elements in a coordinated manner to perform multiplication. Just as easily, it can compute an inner product for vector and matrix operations. The processor elements can also operate in parallel to perform a variety of arithmetic and logic operations concurrently. With reference to Fig. 4 the PU comprises eight PEs 100-0 to 100-7 of the type shown in Fig. 1, a last-stage accumulator 200, an input bus group 300, and an output bus group 400. The input bus group 300 supplies first data Y, second data M, and third data X to the PEs 100-0 to 100-7. As can be seen in the drawing, the k-th PE 100-k receives the three bits X 2k+1 , X 2k , and X 2k-1 . The bit X -1 is always zero which level is a ground level. The outputs produced by the PEs 100-0 to 100-7 are supplied to the output bus group 400, from which they can be supplied to the outside, or to the last-stage accumulator 200. Referring to Fig. 5, the last-stage accumulator 200 comprises a control circuit 210, a shifter 220, an adder 230, and a register 240. The control circuit 210 receives a mode signal MD and a clock signal CK from the outside, and generates control signals S10 and S11. The shifter 220 receives data from the output bus group 400 and shifts the data zero, two, four, six, eight, ten, twelve, or fourteen bits to the left according to the control signal S10. The adder 230 adds the output of the shifter 220 to the output of the register 240 and produces the resulting sum. The register 240 latches this sum on the control signal S11 and supplies it to the adder 230 and the output bus group 400. Operating independently, the PEs 100-0 to 100-7 in Fig. 4 can perform, for example, eight of the cumulative absolute difference operations illustrated in Fig. 2 or Fig. 3 concurrently. In a typical block matching application, each PE receives the same first data Y, but different second data M. Other arithmetic and logic operations involving addition, subtraction, absolute values, and logical negation can also be performed in parallel, eight at a time, by provision of appropriate mode signals to the PEs. Details will be omitted. Next the use of the PU in Fig. 4 to calculate an inner product of the form (X 1 Y 1 + X 2 Y 2 + ... + X m Y m ) will be described. For brevity, this inner product will be denoted Σ XY. The multiplications will be performed by the well-known Booth algorithm, which for a sixteen-bit multiplier X can be expressed by the formula: or XY = (-2X 15 + X 14 + X 13 ) · Y · 2 14 + (-2X 13 + X 12 + X 11 ) · Y · 2 12 + (-2X 11 + X 10 + X 9 ) · Y · 2 10 + (-2X 9 + X 8 + X 7 ) · Y · 2 8 + (-2X 7 + X 6 + X 5 ) · Y · 2 6 + (-2X 5 + X 4 + X 3 ) · Y · 2 4 + (-2X 3 + X 2 + X 1 ) · Y · 2 2 + (-2X 1 + X 0 ) · Y · 2 0 The inner product Σ XY can be expressed as in equation (4). Σ XY = Σ (-2X 15 + X 14 + X 13 ) · Y · 2 14 + Σ (-2X 13 + X 12 + X 11 ) · Y · 2 12 + Σ (-2X 11 + X 10 + X 9 ) · Y · 2 10 + Σ (-2X 9 + X 8 + X 7 ) · Y · 2 8 + Σ (-2X 7 + X 6 + X 5 ) · Y · 2 6 + Σ (-2X 5 + X 4 + X 3 ) · Y · 2 4 + Σ (-2X 3 + X 2 + X 1 ) · Y · 2 2 + Σ (-2X 1 + X 0 ) · Y · 2 0 Using the notation, Φ k = Σ(-2X 2k+1 + X 2k + X 2k-1 ) the equation (4) can be written as equation (6): Σ XY = Φ 0 · 2 0 + Φ 1 · 2 2 + Φ 2 · 2 4 + Φ 3 · 2 6 + Φ 4 · 2 8 + Φ 5 · 2 10 + Φ 6 · 2 12 + Φ 7 · 2 14 The term Φ k is computed by the k-th PE 100-k in Fig. 4, Φ 0 to Φ 7 being computed concurrently. Then Φ 0 to Φ 7 are added with appropriate shifts by the last-stage accumulator 200. This will be illustrated with reference to Figs. 6 to 8 for the four-term inner product: X 1 Y 1 + X 2 Y 2 + X 3 Y 3 + X 4 Y 4 Referring to Fig. 6, at the beginning of the inner-product operation the second registers 170 in all the PEs 100-0 to 100-7 are initialized to zero. In the first machine cycle MC1, the first and the third data Y 1 and X 1 are supplied to the PU and the mode signal MD sets the PEs 100-0 to 100-7 to their second mode of operation. Operating according to Table 1, the shifter 120 in each PE 100-k generates an output value equal to Y 1 , 2Y 1 , or zero depending on the values of X 2k+1 , X 2k , and X 2k-1 , this output value being denoted (X 1 , Y 1 ) in the drawing, and the arithmetic means 150 adds or subtracts (X 1 , Y 1 ) to or from the zero value stored in the second register 170, producing the result denoted Σ 1 in the drawing. At the end of the first machine cycle MC-1 this result Σ 1 is stored in the second register 170 on the rising edge of the control signal S5. From Fig. 6 and Table 1 it is apparent that: Σ 1 = (-2X 1 2k+1 + X 1 2k + X 1 2k-1 ) · Y 1 In the second machine cycle MC-2 the PU receives new first and third data Y 2 and X 2 . Operating in the same way as in the first machine cycle, each PE 100-k calculates a value (X 2 , Y 2 ) and adds or subtracts (X 2 , Y 2 ) to or from the Σ 1 stored in the second register 170, thereby producing a value Σ 2 = Σ1 + (-2X 2 2k+1 + X 2 2k + X 2 2k-1 ) · Y 2 . At the end of the second machine cycle Σ 2 is placed in the second register 170. Proceeding in similar fashion, each PE 100-k produces a value Σ 3 in the third machine cycle MC-3 and a value Σ 4 in the fourth machine cycle. Σ 4 is equal to Φ 4 as defined above: Σ 4 = (-2X 1 2k+1 + X 1 2k + X 1 2k-1 ) · Y 1 + (-2X 2 2k+1 + X 2 2k + X 2 2k-1 ) · Y 2 + (-2X 3 2k+1 + X 3 2k + X 3 2k-1 ) · Y 3 + (-2X 4 2k+1 + X 4 2k + X 4 2k-1 ) · Y 4 = Φ 4 The values Φ k (k = 0 to 7) are output from the PEs 100-0 to 100-7 starting in the fifth machine cycle MC-5. These values now become available on the output bus group 400 in Fig. 4. To carry out the computation shown in equation (6) it is necessary next to add up the Φ k (k = 0 to 7) with appropriate left shifts as illustrated in Fig. 7. This is accomplished in eight additional machine cycles by the last-stage accumulator 200. Referring to Fig. 8, the register 240 in the last-stage accumulator 200 is initialized to zero. In a first machine cycle MC1 (which follows the fourth machine cycle MC-4 in Fig. 6), the shifter 220 in the last-stage accumulator 200 inputs Φ 0 from the output bus group 400 and shifts it left by zero bits, thereby multiplying it by 2 0 . The adder 230 adds the result Φ 0 2 0 to the zero value in the register 240, and the result Σ 1 is stored in the register 240 on the rising edge of the control signal S11. In a second machine cycle MC2 the shifter 220 inputs Φ 1 and shifts it two bits left, and the adder 230 adds the result to the value Σ 1 in the register 240 to produce Σ 2 = Σ 1 + Φ 1 · 2 2 = Φ 0 · 2 0 + Φ 1 · 2 2 Proceeding in this fashion, after an eighth machine cycle MC8 the last-stage accumulator 200 has produced Σ 2XY as given in equation (6). In a ninth machine cycle MC9 the last-stage accumulator 200 places this Σ 2XY on the output bus group 400 for external output, completing the inner product operation. Compared with the prior art in which each PE had its own hardware multiplier, the novel PU requires a few extra machine cycles (MC1 to MC8 in Fig. 6) to compute an inner product, but the simple structure of the novel PEs enables them to operate faster than in the prior art, so speed is not necessarily lost. Moreover, the novel PU makes much more efficient use of its computing resources, because the same hardware that computes an inner product can perform up to eight operations not requiring multiplication, such as eight cumulative absolute difference operations, concurrently. In place of a the last-stage accumulator 200, the PU can employ another PE having the structure shown in Fig. 1. In this case the shifter 120 must be capable of performing left shifts of two, four, ..., fourteen bits as well as zero and one bits. This modification can also be made in the PEs 100-0 to 100-7 so that all nine PEs have the same design. A PU of this type can perform nine cumulative absolute difference operations concurrently. During the machine cycles in Fig. 8, the control signals S1 and S2 in the ninth PE should be held constant in states that cause the first data selector 130 to select the output of the shifter 120, and the second data selector 140 to select the output of the second register 170. The control signal S3 should be held constant in the zero state. Instead of the inner product operation described above, it will be obvious that the novel PU can perform a single multiplication operation, by omitting machine cycles MC-2, MC-3, and MC-4 in Fig. 6 for example. The bit length of the input data is not limited to sixteen bits; other bit lengths can be accommodated by changing the number of PEs. If the number of PEs is N, the novel PU can multiply 2N-bit numbers, or can simultaneously compute N cumulative absolute differences. When the third input data X is a constant coefficient, part of the control circuit 110 of the PE in Fig. 1 can be replaced with a read-only memory circuit in which the expansion of X according to Booth's algorithm is stored in advance, thereby simplifying the operation and consequently increasing the speed of the operation. Fig. 9 illustrates a novel processor comprising four PUs 500-0, 500-1, 500-2, and 500-3 of the type shown in Fig. 4, connected in parallel between an input bus group 600 and an output bus group 700 which are coupled to the input and output bus groups in Fig. 4. Receiving input data Y and X and mode and clock signals MD and CK, the four PUs 500-0 to 500-3 can concurrently compute four inner products, or their 4 x 8 = 32 constituent PEs can concurrently compute thirty-two cumulative absolute differences. The novel processor in Fig. 9 is particularly suited for multiplying 4 x 4 matrices. As illustrated in Fig. 10, the multiplication is performed in four steps. In the first step, the four PUs concurrently compute the following inner products: PU 500-0: Z 00 = X 00 Y 00 + X 01 Y 10 + X 02 Y 20 + X 03 Y 30 PU 500-1: Z 01 = X 00 Y 01 + X 01 Y 11 + X 02 Y 21 + X 03 Y 31 PU 500-2: Z 02 = X 00 Y 02 + X 01 Y 12 + X 02 Y 22 + X 03 Y 32 PU 500-3: Z 03 = X 00 Y 03 + X 01 Y 13 + X 02 Y 23 + X 03 Y 33 In the second step, the four PUs concurrently compute: PU 500-0: Z 10 = X 10 Y 00 + X 11 Y 10 + X 12 Y 20 + X 13 Y 30 PU 500-1: Z 11 = X 10 Y 01 + X 11 Y 11 + X 12 Y 21 + X 13 Y 31 PU 500-2: Z 12 = X 10 Y 02 + X 11 Y 12 + X 12 Y 22 + X 13 Y 32 PU 500-3: Z 13 = X 10 Y 03 + X 11 Y 13 + X 12 Y 23 + X 13 Y 33 Similarly, Z 20 , Z 21 , Z 22 , and Z 23 are computed in the third step, and Z 30 , Z 31 , Z 32 , and Z 33 in the fourth step, completing the matrix multiplication. Since each processing unit must receive the same Y data four times, once in each step, the novel processor may include a cache memory for temporarily storing data, and bus control means for routing the data to the appropriate processing units. Such facilities are well known in the prior art; descriptions will be omitted. The novel processor can perform 4 x 4 matrix operations other than multiplication. For example, it can multiply a matrix by a vector in a single step. Using sixteen of its thirty-two PEs in parallel, the novel processor can also add and subtract 4 x 4 matrices efficiently, the PEs operating in a simple add or subtract mode, each PE adding or subtracting a corresponding pair of elements in two matrices. The invention is not limited to 4 x 4 matrices; M x M matrices of arbitrary size M can be accommodated by connecting M identical PUs in parallel. If each PU comprises N processor elements, the processor can also perform M x N simultaneous additions or subtractions, or compute M x N cumulative absolute differences simultaneously. Fig. 11 shows a simple processor element that receives input data A, B, and C and uses this timing scheme to perform two operations: A + C and B + C. This processor element comprises a data selector 830 that selects the first or second input data A or B, an adder that adds the selected input data to the third input data C, and first and second registers 860 and 870 that store the results. The data selector 830 is controlled by a selector control signal CS. The first and second registers 860 and 870 are controlled by first and second register control signals CR1 and CR2, respectively. With reference to Fig. 12, the control signals CS, CR1, and CR2 have the same frequency as the clock (not shown), so that one machine cycle consists of one period of these control signals. The control signals CS and CR2 are identical. The control signal CR1 is opposite to the control signal CR2 in phase. Three data values A i , B i , and C i are input in each machine cycle. In the first half of each machine cycle, the data selector 830 selects the data value A i and the adder 852 computes A i + C i . This result is stored in the first register 860 at the end of the first half of the machine cycle, on the rising edge of the first register control signal CR1. In the second half of the machine cycle, the data selector 830 selects the data value B i and the adder 852 computes B i + C i . This result is stored in the second register 870 at the end of the second half of the machine cycle, on the rising edge of the second register control signal CR2. Operating in this way, the processor element in Fig. 11 produces two results per machine cycle. It will be apparent that the processing element in Fig. 11 can be combined with that in Fig. 1 by the simple addition of another external input to the first data selector 130 in Fig. 1 and an external output from the first register 160 in Fig. 1. In general, the concept shown in Figs. 11 and 12 can be applied to any processor element of sufficiently simple structure that its circuits are capable of operating at twice the data input rate.

Claims: A processor element for calculating cumulative absolute difference comprising: arithmetic means (150) coupled to receive a first signal and a second signal; a first selector (130) for selecting between a first input signal and a first result signal fed back from the arithmetic means to provide said first signal; a second selector (140) for selecting between a second input signal and a second result signal fed back from the arithmetic means to provide said second signal; and control means (110) for applying control signals (S0, S1, S3, S4) to the selectors to control their selection of inputs, and to the arithmetic means to control whether it performs addition or subtraction, the control means being operable so that during a first cycle of a cumulative absolute difference phase: the first selector provides the first input signal as said first signal, the second selector provides the second input signal as said second signal, and the arithmetic means subtracts the first signal from the second signal to produce a first result signal, and during a second cycle of said cumulative absolute difference phase: the first selector outputs said first result signal as said first signal, the second selector outputs the second result signal as said second signal, said second result signal being the cumulative absolute difference obtained in the previous cumulative absolute difference phase, and if the first result signal is negative then the arithmetic means subtracts the first signal from the second signal to produce a new second result signal, else the arithmetic means adds the first signal and the second signal to produce a new second result signal. A processor element according to claim 1, including a shift register (120) for providing the first input signal to the first selector, wherein the control means is operable so as to be responsive to an input multi-bit signal and a clock signal, to control the shift register and cause the second selector to select continuously the first result signal for calculating a Booth's algorithm inner product from the first input signal and the multi-bit signal. A processor element according to claim 1 or 2 wherein the arithmetic means comprises an adder (152) and a bit inverting means (151), the bit inverting means being between the first selector and a first input of the adder and being responsive to a control signal (S2) so to invert the bits of the output of the first selector when subtraction is performed by the arithmetic means. A processor element according to any preceding claim including a first register (160) for latching said first result data output by the arithmetic means in dependence on a control signal (S4) and a second register (170) for latching said second result data output by the arithmetic means in dependence on a control signal (S5). A processor element according to claim 1 wherein the control means is responsive to an input signal being at a first logic level to output the control signals in a state for effecting said first phase and to the input signal being at a second logic state to output the control signals in a state for effecting said second phase. A processing unit including a plurality of processing elements according to claim 1. A processing unit according to claim 6 including first, second and third data input bus groups (300), an output bus group (400) and an accumulator means (200) coupled to the output bus group for shifting and accumulating the data output by said plurality of processing elements. A processing unit according to claim 7 wherein the accumulating means (200) comprises a shift register (220) for receiving date from the output bus group, an adder (230) arranged to receive the output of the shift register and a signal fed back from the output of the accumulating means, and a register (240) arranged to receive and latch the output of the adder and provide the output of the accumulating means. A processor for M matrices by M matrices, M being an integer greater than 1, comprising: an input bus group; an output bus group; and M processing units according to any one of claims 6, 7 and 8 coupled between the input bus group and the output bus group.

Inventors: MASAKI HIRSOHI, MATSUBISHI NORITSUGU, TOKUNO YOSHIO, YAMAZAKI MASATO, MASAKI, HIRSOHI, MATSUBISHI, NORITSUGU, TOKUNO, YOSHIO, YAMAZAKI, MASATO, Masaki, Hirsohi, c/o OKI ELECTRIC IND. CO. LTD., Matsubishi, Noritsugu, c/o OKI ELECTRIC IND.CO.LTD, Tokuno, Yoshio, c/o OKI ELECTRIC IND. CO. LTD., Yamazaki, Masato, c/o OKI ELECTRIC IND. CO. LTD.
Applicants: OKI ELECTRIC IND CO LTD, OKI ELECTRIC INDUSTRY CO., LTD.
Application year: 1991
Main classification: G06F7
IPC codes: G06F15, G06F7, G06F17