Semiconductor memory device

Abstract: A semiconductor memory device comprises a memory cell group (2) comprising a plurality of memory cells arranged in matrix; a specification circuit (3) for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for enterring them in an active state; a data input/output (I/O) circuit (4) for performing a data read-out/write-in operation (data I/O operation) for the consecutive memory cells specified by the specification circuit (3) under a control based on a read-out/write-in signal provided from an external section; a counter circuit (5) for counting the number of cycles of a basic clock signal provided from an external section; and a controller for receiving at least one or more specification signals provided from an external section, for outputting a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, and for instructing the counter circuit to count the number of counts of the basic clock signal based on the control signal, and for controlling a specification operation executed by the specification circuit (3) and the data I/O operation of the data I/O circuit (4), so that the memory access operations for the memory cell group (2) are controlled.

Description: The present invention relates to a semiconductor memory device comprising a plurality of easily-controllable memory cells which can be accessed at high speed. A conventional, standard, general-purpose DRAM has a page mode for access at a high speed cycle time. As is commonly known, in this page mode it is possible to access specified memory cells in a row of a memory cell array selected by means of a row address, by arbitrarily changing a column address in a string of simultaneously sensed memory cells. High speed access is possible with this type of mode for the following reasons. Considerable time is required for sense amplification of the cell data in a DRAM, but once the data has been sensed, the read-out of this data proceeds very quickly. Once a column address has been changed in the page mode operation, the access to the sense amplifier which has sensed that cell is commenced and the data is output when a CAS signal is switched to "L". Accordingly, the page mode is a random access mode. Recently, the capacity of memory chips has been increasing, year after year. Accordingly, the number of chips used in a system has been more reduced. Therefore, when large volume chips are used in the prior art, namely when many chips are used in the system, these chips are divided into a number of groups which are interleaved, making it possible to construct and utilize a memory system in which the apparent cycle time is short, but this method cannot be used to a system having small volume chips. On the other hand, the speed of an MPU has been increasing year after year, and even in a small scale system there is a strong necessity to achieve high speeds. For these reasons, it has become necessary for a memory to operate at even higher cycle speeds. Also, from these requirements it is not absolutely necessary for the access operation to be random; there are many cases in which all that is required is the ability to read or write a string of data at high speed. A method for providing a high speed operation for RAM including SRAM and the like has been reported in --Chikai Ohno, "Self-Timed RAM: STRAM', FUJITSU Sci. Tech. J., 24, 4, pp293-300, December 1988.--, according to which a RAM (STRAM) operates in synchronization with a system clock, namely in the RAM, an address signal and R/W signals for a read-out or for write-in are received in synchronization with the clock signal at a timing, then at the next timing a content of the memory cell addressed by the address signal is output. However, in this method the address signal must be provided every cycle of the system clock. Therefore there is a disadvantage that the access operation to a memory cell in the RAM cannot be followed to the period of the system clock when the period becomes high. When a conventional page mode is used an address change is absolutely necessary. Therefore, it is impossible to operate with a higher access cycle time which is more than the time determined by the address control of the system. Speed increases for the memory access operation are therefore limited. Control signals such as RAS signals and CAS signals must be supplied to the memory chip. These control signals are produced by the system. Accordingly, the control for supplying the control signals to the memory chip is an obstacle to providing a high speed operation with a memory system which includes an access means. In this case, the operation control of the system becomes so complex that it is difficult to use the control of the system. From EP 0 211 565 A3 a random access memory with a plurality of memory cells is known. In order to address the memory cells in a conventional manner or in a high speed sequential mode a column decoder, a row decoder, a plurality of shift registers and a multiplexer are provided. In the sequential mode alternate cells from each of two sets of cells are addressed. The content of the alternate cells is accessible at system clock rate on a data offline or data can be fed to the alternate cells on a data input line also at system clock rate which is much faster than in the conventional mode. From US 4,819,213 a semiconductor memory for serially reading data out of memory cells is known. The memory cells are connected to a selected one word line pace on the clock signal. During writing the write data are serially input to a latch circuit based on a clock signal wherein the horizontal blanking time of a CRT monitor is taken advantage of. From EP 0 315 194 A2 a micro computer is known comprising a memory chip which can be accessed by a micro processor for a short time. The memory chip includes a memory for storing various processing data, a bus interface for designating an address information of the memory to be accessed for a data transfer, and an address latch for temporarily holding the address information from the bus interface and so as to supply the address information to the memory. Furthermore, there is provided an automatically updated data pointer whose initial value is set with the address information supplied from the bus interface. In case of individually designating an address for each item of data to be transferred, the address latch is used to supply the address information to the memory so that an address is given to the address latch by the bus interface for each data transfer of one unitary data. In case of continuously designating an address for each item of data to be transferred so that the data pointer is used to supply the address information to the memory so that an address for the data transfer of a pursed unitary data to be transferred is given to the data pointer and then the data pointer is automatically updated for each of the second and succeeding data transfers. An object of the present invention is to provide, with due consideration to the drawbacks of such conventional devices, a semiconductor memory device provided with an easily-controllable dynamic memory which can be accessed at high speed. This object is solved by the features of the claim 1. According to the invention, access by the semiconductor device commences with an internal operation synchronized with a basic clock signal which is input at an almost continuous, fixed frequency. After the address is obtained, the operation which determines "read-out" or "write-in", begins after a certain cycle number of fixed cycles which are basic clock cycles, input at an almost fixed frequency. The operation is controlled by a specifying signal for specifying a cycle which acts as the starting point for counting these cycles. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a semiconductor memory device as a first embodiment according to the present invention; FIG. 2 is a timing chart showing an I/O operation of the semiconductor memory device shown in FIG. 1; FIGs. 3 to 5 are timing charts showing I/O operations based on various I/O control methods for the semiconductor memory device shown in FIG. 1; FIG. 6 is a block diagram of a semiconductor memory device as a second embodiment according to the present invention; FIG. 7 is a diagram showing an arrangement of a cell array mat of memory cell groups as a part in the semiconductor memory device shown in FIG. 6; FIG. 8 is a circuit diagram of a column decoder incorporated into the semiconductor device shown in FIG. 6; FIG. 9 is a timing chart showing an I/O operation of the semiconductor memory device shown in FIG. 6; FIGs. 10 to 14 are configuration diagrams showing circuits which produce various types of cycles of clock signals; FIG. 15 is a configuration diagram showing a counter circuit for use in serial access; FIG. 16 is a block diagram of a semiconductor memory device as a third embodiment according to the present invention; FIG. 17 is a timing chart showing an I/O operation of the semiconductor memory device shown in FIG. 16; FIG. 18 is a block diagram of a semiconductor memory device as a fourth embodiment according to the present invention; FIG. 19 is a timing chart showing an I/O operation of the semiconductor memory device shown in FIG. 18; and FIG. 20 is a block diagram of a semiconductor memory device as a fifth embodiment according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Other features of this invention will become apparent in the course of the following description of exemplary embodiments which are given for illustration of the invention and are not intended to be limiting thereof. FIG.1 is a configuration drawing showing the essential parts of a first embodiment of the semiconductor memory device of the present invention. The memory device illustrated in the drawing uses a dynamic memory cell, a static memory cell, or a non-volatile memory cell. In this memory device, the control of internal circuit operations is based on the number of cycles of a continuous external clock signal, to perform the memory access operation. As shown in FIG.1, a memory device 1 comprises a memory cell group 2 provided with a normal memory device, a specification section 3, and a data I/O section 4, to which are added a counting section 5 and a control section 6, which are the main structural element for performing the operation which is the special feature of the present invention. The dynamic memory cells, the static memory cells, or the non-volatile memory cells of the memory cell group 2 are arranged in the form of a matrix. The data which is written in and read out is stored in this memory cell. The specification section 3 allots consecutive addresses in the memory cell group 2 according to a series of externally-provided address signals, and designates, in order, the memory cells which are to be accessed. The specification section 3, for example, fetches a row address signal, then fetches a series of column address signals for a string of memory cells designated by the row address signal. The specification section 3 designates a series of memory cells consecutively by means of the column address signal. The data I/O section 4 performs a read or write operation on a memory cell designated by the specification section 3 based on a read/write signal obtained externally. The read-out data is output to an external destination through the data I/O section 4. The data to be stored is provided to the designated memory cell from an external source through the data I/O section 4 by the specification section 3. The counting section 5 is a counter for counting the number of cycles of a basic clock signal CLK continuously input at an almost fixed frequency from an external source. The counter 5 is capable of counting a fixed number of clock cycles of the basic signal CLK and discriminating some clock cycles from other cycles. A circuit essentially having the function can be considered as the counter 5. Therefore a circuit having the function described above can be used instead of the counter 5 when there is the circuit in the semiconductor memory device. The external basic clock signal CLK used in this embodiment is a clock signal with a cycle time of, for example, less than the 30 ns access time of the memory device. The counting section 5 provides the control section 6 with the count of the number of cycles of the clock signal CLK. The control section 6 receives a specification signal which is provided from an external source and stipulates the conditions for the memory device, for example, a /CE (chip enable) signal or an /OE (output enable) signal. The control section 6 designates a particular cycle of the clock signal CLK by means of a level transition of the signal /CE, and initiates the count of the clock signals in the counting section 5. The control section 6, based on the number of cycles of the clock signal CLK counted by the counting section 5, controls the fetching of the address signal in the specification section 3. Further, the control section 6 controls the internal I/O operation of the data in the data I/O section 4, by a transition level of the signal /OE. Next, the operation of the device shown in FIG.1 will be explained using timing charts shown in FIG.2 to FIG.5. FIG.2 is a diagram showing one example of the timing chart of an operation I/O signal for the memory device shown in FIG.1. In FIG.2, a signal CLK is a clock signal with a cycle time of 30 ns or less for continuous input and output, which is provided into the counting section 5. A signal CE is a signal which indicates the active period of the memory device 1. The operation of the memory device 1 is controlled by means of the value of the signal CLK during the period when a signal CE is at the "L" level. In FIG.2, the signal CE enters the "L" level, and the value of an address signal Add is fetched as a row address R to the specification section 3 at the rise of the initial clock signal CLK (CYCLE 1). Following this, the value of the address signal Add at the rise of the clock signal CLK of the fifth CLK cycle (CYCLE 5) is fetched to the specification section 3 as a column address CN. The data of the column address CN is output to the data I/O section 4 from the eighth active clock cycle (CYCLE 8) which is the third clock signal after the column address CN has been fetched. According to the progress of the clock signals 9, 10, 11, .... , the data from a previously decided order of addresses CN+1, CN+2, CN+3, ...., is output serially to the data I/O section 4. When the CE signal is switched to the "H" level, a fixed number of clock cycles is ignored after the signal CE enters the "H" cycle on the rise of the clock signal CLK, and the memory enters the inactive state. In FIG.2, the rise of the clock signal CE occurs following the 14th clock cycle (CYCLE 14). Several variations have been considered in a control method for this type of memory, therefore examples of these variations will be illustrated. From FIG.3 to FIG.5, specific examples of timing waveforms are shown. In addition, representative values of stipulated timing times are also shown simultaneously in FIG.3 to FIG.5. A CE/RL signal in FIG.3 to FIG.5 corresponds to the CE signal in FIG.2. However, the CE signal is based on the negative logic and the CE/RL signal on the positive logic. The logic of the CE signal differ from the logic of the CE/RL signal. An R/W signal provides instructions as to whether or not the memory operates for a read-out or for a write-in. A0 to A9 (shown in FIGs. 3 and 4) and A0 to A19 (shown in Fig. 5) are address signals. A signal CM indicates that the memory does not receive a clock signal while the CM signal is "H". D OUT/IN indicates data read out of an accessed memory cell or data written into that memory cell. An OE signal is a control signal. When the OE signal is "L", data is output in D OUT/IN , and when "H", the memory output related to D OUT/IN is in a high impedance state. FIG.3 is a diagram showing the specific fetch timing of an R/W signal for a read out instruction, in addition to the case in FIG.2. In FIG. 3, the column address is fetched to the specification section 3 at the clock signal designated by the CLK 3 ○ , and the memory cell data begins to be output to the data I/O section 4 at the clock signal denoted by the CLK 6 ○ . FIG.4 is a timing chart in the case where a clock cycle in which the column address is fetched can be indicated by a clock signal independent of the timing for fetching the row address. In FIG.4, after the row address is fetched to the specification section 3, if a CL signal enters the "H" level when the clock signal rises, the column address is fetched to the specification section 3 during that clock cycle, and access to the cell commences. During this fetch cycle, the data following the column addresses CN, CN+1, CN+2, CN+3, CN+4 from the clock cycle (CLK 3) shown in FIG.4, which is a fixed number of cycles, is output in serial order. FIG. 5 is a timing chart of I/O operations for the memory device in which the R/W signal is controlled based on level change of a RWL signal. This figure shows the timing chart in the case where the clock signal which fetches the address can be independently and freely set. This is the case where the address is fetched without being divided into row and column parts (specifically, the address is not multiplexed). In FIG.5, if the RWL signal is at the "H" level at the rise of the clock signal CLK, the R/W signal, which determines whether there is a read out or a write in from the clock cycle, is fetched. The output of data starts at the CLK 3 which follows the above-mentioned cycle by a fixed number of cycles. Read-outs are shown in the above three timing examples in FIG.3 to FIG.5, but it is also possible to perform a write operation by setting the R/W signal. In such a case, external data is input to the memory from D OUT/IN . In addition, many combinations of control operation methods are also possible in the above examples. For example, it is possible to combine the RWL signal and the CL signal as one signal. It is also possible to fetch the column address and the R/W signal simultaneously, fetch the row address, column address, and the R/W signal independently, and to commence the read/write operation at the cycle following a fixed number of clock signals which has become the final fetch cycle. In addition, instead of the method mentioned above, it is possible to fetch the external signals such as the R/W signal and the like during a fixed period between cycles, for example between the M-th cycle and the N-th cycle. It goes without saying that the same data read/write operation can be continued during a fixed period between cycles also. In FIG.6, the control method in the first embodiment described above is applied to an interleaved type of memory device according to a second embodiment of the present invention. This diagram shows the main configuration of a memory device for which the above-mentioned control method functions effectively. In FIG.6, a memory device 10 comprises a memory cell group 11, a selection section 12, a specification section 13, and a control section 4. The functions of components in FIG.6 which bear the same reference numbers as components in FIG.1 have the same functions as those components. Further explanation is therefore omitted here. In the memory cell group 11, for example, a dynamic type memory cell is formed as a block and arranged in matrix form. This memory cell also includes a column decoder. An example of a specific configuration of the memory cell group 11 will be later described. The selection section 12 is based on one part of an external basic clock signal and an address signal. The respective blocks of the memory cell in the memory cell group 11 are interleaved, and consecutive selection is activated. The selection section 12 provides a series of selection activation signals Φ A, Φ B, Φ C, and Φ D to the memory cell group 11. The specification section 13 specifies the row address based on an address signal, and specifies the column address of the selectively activated block, based on a signal which is one part of the address signal and one part of selection activation signals. Specific examples of the configuration of the selection section 12 and the specification section 13 will be later described. The control section 14 controls the operations of the selection section 12 and the specification section 13 based on the number of cycles of an external basic clock signal. FIG.7 is a diagram showing the arrangement of a memory cell array mat (a memory cell array) of the memory cell group 11. In FIG.7, the memory cell comprises a total of 16 memory cell array mats. A plurality of column decoders takes up eight columns, each column decoder being interposed between two memory cell array mats. This memory system performs four separate operations. When a certain row address is selected, for example, the cell array mats 1, 2, 9, and 10 enclosed in the heavy lines in FIG.7 are activated. Specifically, one fourth of the memory cell group 11 corresponding to row addresses are activated. In FIG.7 there are four combinations of parts of the memory cell array mats, (1, 2, 9, 10) (3, 4, 11, 12) (5, 6, 13, 14) and (7, 8, 15, 16). FIG.7 shows the conditions under which the first combination (1, 2, 9, 10) is activated. Part of the memory cells which are activated simultaneously, as shown in the example in FIG.7, are divided into equal part cell array blocks, and serial access is carried out in the order predetermined for this array. The example of FIG.7 is divided into four cell blocks, and this selection is performed by means of the selection activation signals Φ A, Φ B, Φ C, Φ D. In the example shown in Fig. 7, the cell array mat corresponds to the cell array block with one to one. In addition, the column direction access is serial. Accordingly, the input to the column decoder is the output from the serial counter. Because the memory arrays 1, 2, 9, 10 are interleaved in serial order and accessed, the counter output from the serial counter, which is input to the column decoders 1 and 5, is also interleaved. This interleaving operation will be later explained. FIG.8 shows a specific example of one configuration of a column decoder used in the semiconductor memory device shown in Fig. 6. The configuration of the column decoder shown in FIG.8, shows parts of the column decoders 1, 5 from FIG.7 combined. In addition, the D OUT/IN shown in FIG.2 to FIG.5 is assumed to be an I/O of four bits, and the data transmission routes linked to this input/output circuit are shown as I/O1 to I/O4. In addition, a bit line constructed from a complementary signal pair, and the above-mentioned I/O line are shown as one line for simplicity. In FIG.8, a column decoder C/Dn formed from a NAND gate is selected by means of serial counter output. Subsequently, when the decoder output is at "L" level and the signal Φ A rises, the bit lines B1 to B4 are connected to the I/O lines, and data access begins. This is a latch circuit so this selection state is maintained even when the signal Φ A enters the "L" level and is maintained until the signal Φ A next rises. Next, when the signal Φ B rises, the bit lines B1' to B4' are connected to the I/O lines I/O1' to I/O4'. In this manner, data items are transmitted consecutively from the memory arrays 1, 2, 9, 10 by the consecutive rising of the signals Φ A, Φ B, Φ C, Φ D. In addition, the data can be written in through the I/O lines in the reverse manner. Accordingly, if the signals Φ A, Φ B, Φ C, Φ D are interleaved, the clock signal can utilize three cycles from the initiation of access until the output of the data, as illustrated in the lower portion of the timing waveforms of FIG.9. Accordingly, the data can be output at three times the speed set by the circuit operation. In addition, because three cycles elapse until the same memory cell array can be accessed once again, the data received from an external source can be transmitted at a high speed cycle for a write-in, in the same manner as for a read-out. FIG.9 shows the timing chart for the internal signals with interleaving operation, illustrating the case where interleaving based on four phases of the clock signals is adopted. In FIG.9, an external clock signal CLK is divided into four times the number of cycles, and the internal basic clock signals Φ 1, Φ 2, Φ 3, Φ 4 which are out of phase with the external clock signal by one cycle are generated by the selection section 12. These clock signals are suitably selected and the signals Φ A, Φ B, Φ C, Φ D are generated. The method of selection will be later explained. A signal CNT1 and a signal CNT2 show the output from the serial counter which is input to the column decoders 1 and 5 shown in FIG. 7. CNT1 is carried out first by a count up operation using a four cycle clock signal. A two-cycle delay signal CNT2 is then counted up in the same manner. This state is indicated in FIG.9 by numbers attached to the waveforms of the signal CNT1 and the signal CNT2. Next, the method of selecting the array will be explained in chronological order. In FIG.9, in a certain cycle of the clock signal 1, for example CLK 1, the output of the signal CNT1 changes, and the C/Dn of the column decoder 1 is selected. In a next cycle CLK 2, the memory cell array 1 side shown in FIG. 7 is connected to the I/O line from the rise of the signal Φ A. With a next cycle CLK 3, the memory cell array 2 side is connected to the I/O' line from the rise of the signal Φ B. In this cycle, the output of the signal CNT2 simultaneously changes, and becomes the same as the output of the signal CNT1. As a result, the C/Dn of the column decoder 5 is selected. In the following cycle CLK 4, the selection state of the memory cell array 1 is latched by the latch circuit at the drop in the signal Φ A. This state is maintained even if the state of the column decoder C/Dn changes. Also, the memory cell array 9 side is connected to the I/O line at the rise of the signal Φ C. This I/O line is, of course, a different line than that to which the column decoder 1 is connected. The signal Φ B drops in the next cycle CLK 5, the signal Φ D rises, and the count-up state of the output of the signal CNT1 is changed. As a result, the C/Dn of the column decoder 1 is in the non-selected state. However, the signal Φ A drops and the signal Φ B also drops so that no change occurs in the connection states of the I/O line and the I/O' line of the memory cell arrays 1, 2. Also, the memory array 10 side is connected to the I/O' line at the rise of the signal Φ D. This I/O' line is, of course, a different line than that to which the column decoder 1 is connected. Then, in this cycle, the data transmitted to the I/O line of the column decoder 1 is output from the memory through the data I/O section 4. In the next cycle CLK 6, once again the signal Φ A rises and the signal Φ C drops. The bit lines B1 to B4 are disconnected from the I/O lines on the rise of the signal Φ A. This is because the output of the column decoder C/Dn is at the "H" level and the transmission transistors of the bit lines and the I/O lines enter the OFF state. Simultaneously, the output of the C/D of the other column decoders enters the "L" level. The bit lines on the memory cell array 1 side belonging to the column decoder C/D are connected to the I/O lines. In this cycle, the data transmitted to the I/O' line of the column decoder system 1 is output from the memory through the data I/O section 4. Further, the operation produced consecutively by the column decoder system 1 is also carried out in the column decoder system 5 by the fall of the signal Φ C. An explanation is therefore omitted. Next, the reasons why the system connecting the internal basic clock signals Φ 1 to Φ 4 with the clock signals Φ A to Φ D which actually drive the memory device cannot be a fixed connection will be explained, as will the connection logic. Because the time at which the memory is activated is optional, the state of the internal basic clock signal is not fixed each time access is commenced. On the other hand, in the selection of the respective bit lines and of the column decoder C/D, it is necessary for the signals CNT1, CNT2, and the signals Φ A, Φ B, Φ C, Φ D to be fixed signals. Accordingly, when the column address has been set and access started, the connection state of the basic clock signals and the signals Φ A, Φ B, Φ C, Φ D must be determined according to the state of the basic clock signals Φ 1 to Φ 4 and the address, and the signals Φ A, Φ B, Φ C, Φ D must start from the correct state. Specifically, it is necessary that the operation normally be carried out with a fixed inner operation phase relationship. In the section on the right side of FIG.9, a connection which differs from the section on the left side is shown. In FIG.9, the left side connection, as shown in the drawing, is Φ 4 - Φ A, Φ 1 - Φ B, Φ 2 - Φ C, Φ 3 - Φ D; on the right side Φ 2 - Φ A, Φ 3 - Φ B, Φ 4 - Φ C, Φ 1 - Φ D; and connection relationships exist for another two routes. In addtion, in FIG. 9, there are consecutive rising in the signal Φ A, but consecutive risings are also acceptable in those signals Φ B, Φ C, Φ D. These connection states are determined according to the states of the basic clock signals Φ 1 to Φ 4 at the clock cycle which starts the access to the column address. Next an explanation will be given for specific configurations of the circuits which produce the above-described clock signals and the like. FIG.10 is a configuration diagram showing a circuit which produces a double cycle of a clock signal  2 from the external basic clock signal CLK. In FIG.10, a pair of clock inverters 20, 21 are illustrated. The clock inverter 21, for example, functions as an inverter when the clock signal is at the "H" level, and a high impedance output occurs at the "L" level. With the circuit configuration shown in FIG.10, the state of the signal  2 can be changed by switching the clock signal twice between "H" and "L". FIG.11 is a configuration diagram showing a circuit which produces the basic clock signals Φ 1, Φ 2, Φ 3, Φ 4. The operation of the circuit shown in FIG.11 is basically the same as that of the circuit shown in FIG. 10. However, in this circuit, the signal  2 and the inverted signal  2 are used in place of the clock signal and the inverted clock signal. Therefore, seen from the clock signals, a four-cycle clock signal is produced. The phase relationship of the signals Φ 1, Φ 2, Φ 3, Φ 4 is clear from the circuit configuration. FIG. 12(a) is a configuration diagram showing a circuit which produces the actual circuit control clock signals Φ 1, Φ 2, Φ 3, Φ 4 from the internal basic clock signals. In FIG.12(a), the manner how to connect the four signals Φ 1, Φ 2, Φ 3, Φ 4 to the signals Φ A, Φ B, Φ C, Φ D is shown according to the values of a plurality of selection signals, X1 to X4. In this circuit, four output Ys actually exist, depending on the signals Φ A, Φ B, Φ C, Φ D. FIG.12(b) shows the relationship between the selection signals A, B, C, D, which are the signals X1 to X4, and the signals Φ A, Φ B, Φ C, Φ D which are the outputs Y. For example, when Y = Φ A , the circuits correspond to X1 =A , X2 =B , X3 = C , and X4 = D . If the signal A is at the "H" level an the signals B to D are at the "L" level it can be understood from the combinations shown in FIG.12(b) and the circuit configuration that the corresponding relationships become Φ 1 - Φ A, Φ 2 - Φ B, Φ 3 - Φ C, Φ 4 - Φ D. FIG.13(a) is a circuit which produces the signals A, B, C, D from the state of the basic clock signal Φ 1, Φ 2, Φ 3, Φ 4. As can be understood from FIG.9, the signal Φ 3 is the inverted phase of the signal Φ 1, and the signal Φ 4 is the inverted phase of the signal Φ 2. Therefore, the input of the circuit shown in FIG. 13(a) becomes the signals Φ 1, Φ 2, the invert signal Φ 1, and the invert signal Φ 2. All the staes of the basic clock signal are determined by four combinations of the states of the signals Φ 1,Φ 2. Four such circuits actually exist with the output Xi depending on the signal A, B, C, and D. FIG.13(b) shows the relationship between the selection signals α, β, γ, δ determined from the access head addresses which are the signals x1 to x4, and the signals A, B, C, and D which are the output Xi. For example, the output Xi = A corresponds to the circuits for which x1 =α , x2 = β x3 = γ , and x4 = δ . From the state of the head addresses, when β is "H", α, γ, and δ are "L". If the state of the basic clock signal at this time is such that the signal Φ 1 is at the "H" level and the signal Φ 2 is at the "L" level, only the signal A becomes "H", from the combinations and circuit configuration show in FIG.13(b). FIG.14 shows a circuit configuration which produces the signals α, β, γ, δ from the two lower order bits A0c and A1c of the head address. In FIG.14 the two lower order bits correspond to the memory array which is accessed consecutively in a serial manner in FIG.7, specifically, to the signals Φ A, Φ B, Φ C, Φ D. The memory cell array from which the serial access is commenced and the state of the basic clock signals at that time determine the method of connecting the signals Φ A, Φ B, Φ C, Φ D and the basic clock signals Φ 1, Φ 2, Φ 3, Φ 4. Accordingly, the circuit which produces the selection signals in FIG.14 from the head addresses is essential. This has been discussed previously. In the circuit shown in FIG.14, when the address signal for the head address is fetched, a control signal S is temporarily at the "H" level, and, according to the state of the address, one of the signals α, β, γ, δ temporarily enters the "H" level. Any of the signals A to D can enter the "H" level, depending on this signal. From the circuit configuration shown in FIG.13(a), the reason for the latching of the output Xi is because the signals α, β, γ, δ corresponding to the signals x1 to x4, only enter the "H" level temporarily, so even when this cycle has elapsed the state of the signals A to D is maintained. As explained above, if the signals Φ A, Φ B, Φ C, Φ D are produced from the basic clock signals, the phase relationship of the internal control becomes fixed without any relation to the head address. Next, an example of the configuration of a counter circuit included in the specification section 13 for use in serial access, is shown in FIG.15 The counter of FIG.15 comprises a half-adder circuit 21 and a latch circuit 22. In addition to these components, a control circuit 23 for setting the head address in the counter, and a latch circuit 24 for the signal CNT2 which is the input to the column decoder 5 shown in FIG.7 are also provided. The half-adder circuit 21 and the latch circuits 22, 24 contain only the number of its required for the column address. The address which hold the output of the half-adder circuit 21 in the form of bits is the input address (the address holding IAis in the form of bits ) + 1. This is apparent from the fact that the carry input T -1 for the lowest order bit i = 0 is at "H" level for V DD . The latch circuit 22 and the control circuit 23 latch and output this incremented output in a suitable time period. When the signal D rises, the output from the half adder circuit 21 is output to the latch circuit 22 as IAis, which is the address bit of the signal CNT1. Next, the address remains latched in this state until the signal D rises once again. The control circuit 23 controls so that the column address is output from the latch circuit 22 as the signal CNT1 without the signal D being transmitted to the latch circuit 22 when the head address is set in the counter. The address bit IAis of the signal CNT1 is delayed and is output to the latch circuit 24 as the address bit of the signal CNT2 at the rise of the signal Φ B. The address remains latched in this state until the signal Φ B rises once gain. The signals CNT1, CNT2 shown in FIG.9, are obtained with this type of circuit configuration. Next, a semiconductor memory device as a third embodiment of the present invention will be explained. The semiconductor memory device is a package transfer type memory device which is capable of transferring data into or from a fixed number of memory cells at a time by using a serial register. Fig. 16 shows a block diagram of the semiconductor memory device of the package transfer type as the third embodiment to which the memory I/O operation control method according to the present invention is applied. Between memory cell groups 162 and a data I/O (input/output) section 164, a serial register section 167 comprising a plurality of serial registers (the number of the serial registers is eight in the memory device shown in FIG. 16) is incorporated in a memory device 161. A data transfer operation between the memory cell groups 162 and the data I/O section 164 is performed through the eight serial registers at a time. A data transfer operation between the serial register section 167 and the data I/O section 164 is performed per serial register based on the period of the external basic clock signal. A data transfer control section 168 controls two types of the data transfer operations mentioned above. In the configuration of the memory device 161 shown in FIG. 16, eight bit data is transferred at once between the memory cell groups 162 and the serial register section 167. The eight bit data is serially transferred by one bit between the data I/O section 164 and the serial register section 167. FIG. 17 is a timing chart showing an operation of the semiconductor memory device of the package transfer type shown in FIG. 16. In the same diagram, after the CE signal becomes L level, the counting operation of the basic clock signal CLK starts from a particular cycle which is determined by a control signal provided from an external section. In this embodiment, the particular cycle is designated by the CLK 1 at which a row address is fetched, then a column address is fetched at the CLK 3, CLK 11, and CLK 19. The column address means a head address of the target memory cells of 8 bits as a package memory cell to be fetched at once. The difference between the prescribed interleave type memory device and the memory device of this embodiment is explained followings: In the latter, the setting of head addresses in target package memory cells to be fetched, each of which comprises a fixed number of memory cells to be fetched at once, cannot be determined freely and a head cycle in clock cycles required for transferring all bits in one package memory cell to be transferred at once is determined previously in the cycles at intervals of cycles determined by the number of bits in one package memory cell. Further, in the latter, in order to continue the serial access operation, a next column address must be provided after the number of clock cycles required for transferring the bits as the package data is passed. This next column head address may be generated by a counter in chip automatically to continue the serial access operation. In FIG. 17 Dout designates a serial access operation for data output. In this case, the data output operation starts at the CLK 8. On the other hand, Din denotes the serial access operation for data input to the memory cell groups 162. In this case, the data input operation starts at the CLK 1. Namely, in this embodiment, a memory cell group to be stored data can be determined during the data input operation to the serial register section 167, then all data in the serial register section 167 can be transferred as a packaged data to the memory cell group at once. FIG. 18 is a block diagram of a construction circuit of a memory device as a fourth embodiment according to the present invention, which is required to perform a consecutive serial access operation by counting the number of cycles of the basic clock signal through a serial register section comprising a predetermined number of bits. In the same diagram, a specification section, for specifying a memory cell group 182, comprises a row specification section 183 and a column specification section 181. A plurality of columns are selected at once as a package memory cell section by the column specification section 181. For example, each character 1 ○ , 2 ○ , or 3 ○ in the memory cell group 182 designates a memory cell section comprising a constant number of memory cells having a consecutive address. All of the contents of memory cells in each memory cell section 1 ○ , 2 ○ or 3 ○ are transferred at a time to the serial register sections 187 or 188. The reason why there are two register sections 187 and 188 as the serial register section is that as shown in FIG. 17, a serial access operation for bit data having the number of bits more than that of bit data for the package transfer operation. In this case, when the read-out operation is performed, cell data according to a column address CA which is read out at the CLK 3 under the control of a counting section 185 and a control section 186, for example a package data comprising all of the cell data stored in the memory cell section 1 ○ is transferred at a time to the serial register section 187. A column address is fetched, and then, for example a package data corresponding this column address comprising all of the cell data stored in the memory cell section 3 ○ is transferred to the serial register section 188 during the package data of the memory cell section 1 ○ is accessed. Next, output of the last data in the serial register section 187 is completed, data in the serial register section 188 is accessed serially. Thus, the control section 186 controls the data I/O operations between the memory cell group 182 and the serial register sections 187, 188, and the serial register section 187 ,188 and the data I/O section 184. By repeating the operations described above, the serial access operation can be carried out. On the other hand, in the case of the write-in operation, for example, sequential data is written into the serial register section 187 in accordance with the basic clock signal. In the case of the clock timing shown in FIG. 17, first the counting of the number of the clock signal CLK1 and the data write-in operation start. The head address CA in the memory cells in the memory cell section to be stored is fetched during the data is provided into the serial register section 187 (at CLK 3). After the cycle of the clock signal CLK of the number of the registers constituting the serial register section 187 has elapsed, data is fetched into the serial register section 188, then the package data in the serial register section 187 is transferred into the memory cell section 1 ○ , which is addressed by the column address CA, in the memory cell group 182. Next, the package data in the serial register section 188 is also transferred into the memory cell section. Thereby, the consecutive serial operation progresses. As shown by the character Din in FIG. 17, there is a case that the data in one serial register section must be transferred into one memory cell section before data transfer operation for all of the registers in the serial register section is completed. In addition, as shown in FIG. 19, there is also a case that data must not transferred in one register on a serial register section under the control of an input enable signal. As shown in a timing chart of FIG. 19, data cannot be transferred into a register in the clock signal CLK when WE is in H-level. In these case, the content of the register is indefinite. When a package data including the indefinite data is transferred into a memory cell section, a data transfer operation cannot be completed correctly. This problem is solved by a circuit of a serial register section in the semiconductor memory device as a fifth embodiment according to the present invention shown in FIG. 20. FIG. 20 is a block diagram showing a construction of the serial register section in a semiconductor memory device of the fifth embodiment according to the present invention. As shown in FIG. 20, a register gate section 205 is incorporated between a serial register section 206 and a data bus 201. The register gate section 205 comprises many gates which are corresponding to the registers in the serial register section 206 with one-to-one. The register gate section 205 is activated when a write signal 209 is applied, then each register gate in the register gate section 205 enter ON state by a write enable signal 207 provided from the control section 203. Each register gate in ON state is corresponding to the serial register having an effective data to be transferred into a memory cell in a memory cell group. Thereby, a data transfer path between the serial register having the effective data and the data bus 201 is open. On the other hand, a data transfer path between a serial register having uneffective data and the data bus 201 is closed. The write enable signal is, for example, produced based on a state of the WE signal by a control section 203 Thus, the content of a memory cell can be kept correctly because disabling the transfer of the data in a register having uneffective data the memory cell can be protected by a register gate when a package transfer operation is performed. On the other hand, in the read-out operation, a package data stored in a memory cell section is transferred to a serial register section 206 through the data bus 202. In this case, the register gate section 205 is not activated. With a control system of this type and memory device with this configuration, access can be made without the necessity for critical timing and without using a large number of control signals by using the high speed mode state. Because of this fact, it can be clearly understood that all operations can be controlled with a high speed serial clock signal CLK, and this controls easily performed. In addition, because interleaving can be carried out with any of these clock signals in the internal operation, the internal operations can be perform by doubling the number of high speed access cycles. No special circuit technology is required to convert to high speed. In addition, the phase of the access of the internal circuit section operation is fixed without depending on accessing the head address. Accordingly, restrictions relating to the head address disappear. Furthermore, no special circuit is required to convert high speed because by the present invention the package transfer method, by which an internal operation in a semiconductor memory device can be performed every plural cycles of a clock signal, can be applied to the semiconductor memory device. Various modification will become possible for those skilled in the art after receiving the teachings of the present disclosure without departing from the scope thereof as defined in the appended claims. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: Semiconductor memory device (1, 10, 161) comprising: a) a memory cell group (2, 11, 162, 182) comprising a plurality of memory cells arranged in a matrix, b) specification means (3, 12, 13, 163, 181, 183) being adapted to receive an address signal and to specify in the memory cell group a plurality of memory cells addressed by consecutive addresses for activation of said memory cells, c) data input/output means (4, 164, 184) being adapted to perform a data write-in/read-out operation regarding the memory cells specified by the specification means (3, 12, 13, 163, 181, 183), controlled on the basis of a write-in/read-out signal provided from an external section, d) count means (5, 165, 185) being adapted to count the number of cycles of a basic clock signal (CLK) provided continuously from an external section, and e) control means (6, 14, 166, 186) being connected to said count means (5, 165, 185) and being adapted e.1) to receive a specification signal (CE, CL, RWL) provided from an external section for specifying a cycle of said basic clock signal (CLK), e.2) to output to said count means (5, 165, 185) a control signal in response to the specification signal (CE, CL, RWL), whereupon said count means (5, 165, 185) counts the number of clock cycles of said basic clock signal (CLK), starting with said specified cycle, e.3) to receive from said count means (5, 165, 185) the count of the number of cycles of said basic clock signal (CLK), and e.4) to control a specification operation of said specification means (3, 12, 13, 163, 181, 183) and the data write-in/read-out operation of said data input/output means (4, 164, 184) in accordance with the number of cycles of said basic clock signal (CLK) counted by said count means (5, 165, 185). Semiconductor memory device according to claim 1, wherein said write-in/read-out signal provides instructions as to whether said semiconductor memory device (1) operates for a read-out or for a write-in operation. Semiconductor memory device according to one of the claims 1 - 2, wherein the memory cells have an access time of 30 ns. Semiconductor memory device according to one of the claims 1 - 3, wherein the specification means (3) fetches a row address signal (RAS) and then fetches a series of column address signals (CAS) for a string of memory cells specified by the row address signal. Semiconductor memory device according to claim 4, wherein the specification means (3) specifies a series of memory cells consecutively by means of the column address signal. Semiconductor memory device according to one of the claims 1 - 5, wherein the basic clock signal (CLK) is continuously inputted to said count means (5) at an substantially fixed frequency. Semiconductor memory device according to claim 6, wherein the cycle time of the basic clock signal (CLK) is less than the access time of the memory cells. Semiconductor memory device according to one of the claims 1 - 7, wherein said specification operation of said specification means (3) comprises the fetching of the address signal in the specification means (3) and the internal I/O operation of the data in the data I/O section 4. Semiconductor memory device according to one of the claims 1 - 8, wherein by the control means (6) an address and data of a memory cell first accessed after at least two or more cycles of the basic clock signal counted from the particular cycle. Semiconductor memory device according to one of the claims 1 - 9, wherein the specification signal comprises a first signal (CE) which indicates the active period of the memory device (1). Semiconductor memory device according to claim 10, wherein said semiconductor memory device (1) enters an inactive state after said first signal (CE) enters a high level (H). Semiconductor memory device according to one of the claims 9 - 11, wherein the specification operation of said specification means (3) and the data write-in/read-out operation of said data input/output means (4) are controlled in accordance with the specified fixed number of cycles during the period when the first signal (CE) is at a low level (L). Semiconductor memory device according to one of the claims 9 - 12, wherein the first signal (CE) is based on negative logic. Semiconductor memory device according to one of the claims 9 - 12, wherein said first signal (CE/RL) is based on positive logic. Semiconductor memory device according to one of the claims 1 - 14, wherein the control means (6) controls that a row address of the memory cell group (2) is determined after a fixed number of cycles counted from a particular cycle of the basic clock signal obtained by a first specification signal in the specification signals, and a column address of the memory cell is determined after a fixed number of cycles counted from a particular cycle of the basic clock signal obtained by a second specification signal in the specification signals in order to obtain a content of a memory cell addressed by the row address and the column address. Semiconductor memory device according to claim 15, wherein the value of an address signal (Add) is fetched as a row address (R) by said specification means (3) at the rise of the initial clock cycle (CYCLE 1) of said specified fixed number of clock cycles. Semiconductor memory device according to one of the claims 15 - 16, wherein the value of an address signal (Add) is fetched as a column address (CN) by said specification means (3) at the rise of the fifth CLK cycle (CYCLE 5) of said specified fixed number of clock cycles. Semiconductor memory device according to one of the claims 15 - 17, wherein the data of the column address (CN) is output to said data input/output means (4) at the rise of the eighth clock cycle (CYCLE 8) of said specified fixed number of clock cycles which is equivalent to the third clock cycle after the column address (CN) has been fetched. Semiconductor memory device according to one of the claims 15 - 18, wherein according to the progress of the clock cycles (CYCLE 9, 10, 11, ...) the data from a previously decided order of addresses (CN+1, CN+2, CN+3, ...) is output serially to the data input/output means (4). Semiconductor memory device according to one of the claims 15 - 19, wherein the data of the column address is fetched at the rise of the third clock cycle (CYCLE 3) of said specified fixed number of clock cycles. Semiconductor memory device according to claim 20, wherein the memory cell data begins to be output to said data input/output means (4) at the rise of the sixth clock cycle (CYCLE 6) of said specified fixed number of clock cycles. Semiconductor memory device according to one of the claims 15 - 21, wherein a clock cycle in which the column address is fetched can be indicated by the basic clock signal (CLK) independent of the timing for fetching the row address. Semiconductor memory device according to claim 22, wherein after the row address is fetched to the specification means (3), if a second signal (CL) enters the high level (H) when the basic clock signal (CLK) rises, the column address is fetched to the specification means (3) during that clock cycle. Semiconductor memory device according t0 claim 23, wherein during said fetch cycle a fixed number of clock cycles is specified and wherein the data following the column addresses (CN, CN+1, CN+2, CN+3, CN+4)from the third clock cycle (CLK 3) of the fixed number of clock cycles is output in serial order. Semiconductor memory device according to one of the claims 1 - 9, wherein the write-in/read-out signal is controlled based on level change of a third signal (RWL) such that the basic clock signal which fetches the address can be independently and freely set in order to fetch the address without being divided into row and column parts. Semiconductor memory device according to claim 25, wherein if the third signal (RWL) is at a high level (H) at the rise of the clock signal (CLK), said write-in/read-out signal is fetched. Semiconductor memory device according to claim 26, wherein the output of data starts at the rise of the third clock cycle (CYCLE 3) of said specified fixed number of clock cycles. Semiconductor memory device according to one of the claims 23 - 27, wherein the control of said specification operation is based on a fourth signal being a combination of the second signal (CL) and the third signal (RWL). Semiconductor memory device according to one of the claims 1 - 28, wherein the column address and the write-in/read-out signal are fetched simultaneously. Semiconductor memory device according to one of the claims 1 - 28, wherein the row address and the column address and the write-in/read-out signal are fetched independently. Semiconductor memory device according to one of the claims 1 - 30, wherein said data write-in/read-out operation of said data input/output means (4) commences at the cycle following said fixed number of clock cycles which has become the final fetch cycle. Semiconductor memory device according to one of the claims 1 - 31, wherein the signals of said external section are fetched during a fixed period between cycles. Semiconductor memory device according to one of the claims 1 - 32, wherein said data write-in/read-out operation of said data input/output means (4) is continued during a fixed period between cycles. Semiconductor memory device according to claim 1, wherein the semiconductor memory device (10) is an interleaved type of memory within consecutive selection is activated. Semiconductor memory device according to claim 34, wherein a selection means (12) for outputting a selection signal provided is based on a basic clock signal provided consecutively from an external section and an address signal for specifying an address of the cell block in order to select and activate the cell block by interleaving consecutively the memory cell blocks. Semiconductor memory device according to one of the claims 34 - 35, wherein said specification means (13) specifies sequentially and activates the memory cells addressed by consecutive addresses in the memory cell block in accordance with the address signal and the selection signal for activating and entering the cell block in an active state by the selection means (12). Semiconductor memory device according to claim 36, wherein under the control of the control means (14) a fetch operation for data in y-th memory cell block ( x = i - m (mod n), modulus n) is started before m cycles from a cycle of the basic clock signal counted from a starting cycle to access the i-th memory cell block and outputs the content of the x-th memory cell block when consecutive data are fetched from the n (n ≥ 2) memory cell blocks. Semiconductor memory device according to one of the claims 36 - 37, wherein the memory cell group (11) consists of small groups of n memory cell blocks, the k (n > k) memory cell blocks make up of a large memory cell block, the N (n > k > N) large memory cell blocks make up of the small memory cell group ( n = k x N ), a column decoder is provided every large memory cell block, the k memory cell blocks in each large memory cell block are controlled by the same column decoder, each column decoder is activated every n-th cycle of the basic clock signal for specifying consecutively the memory cells in the k memory cell blocks under the control of the specification means (13), and each of the N column decoders can keep a specification for the large memory cell block specified during at least 2k cycles of the basic clock signal. Semiconductor memory device according to one of the claims 36 - 38, wherein the selection means provides a plurality of internal basic clock signals, which are only different in phase, from the basic clock signal, the plurality of the memory cell blocks are selected and activated by interleaving consecutively them in a fixed order by using the internal basic clock signals and a part of an address signal for specifying a head memory cell block to be accessed, in spite of the state of the internal basic clock signal at which the memory cell block is accessed first by the internal basic clock signal. Semiconductor memory device according to one of the claims 36 - 39, wherein said semiconductor memory device (10) comprises a selection means (12) providing a series of selection activation signals (Φ A , Φ B , Φ C , Φ D ) to the memory cell group (11) for selecting the cell blocks based on one part of an external basic clock signal and an address signal. Semiconductor memory device according to one of the claims 36 - 40, wherein the column direction access is serial. Semiconductor memory device according to one of the claims 36 - 41, wherein said specification means (13) specifies the row address based on said address signal and specifies the column address of the selectively activated block based on one part of said address signal and one part of said selection activation signals. Semiconductor memory device according to one of the claims 36 - 42, wherein said control section (14) controls the operation of the selection means (12) and the specification means (13) based on the number of cycles of an external basic clock signal (CLK). Semiconductor memory device according to claim 1 wherein the memory cell group consists of a package memory cell further comprising: specification means (12) for specifying and activating at once a fixed number of the memory cells, addressed by consecutive addresses in the memory cells in accordance with a basic clock signal and an address signal provided from an external section, and store means (167) for storing temporarily data from or to the fixed number of the memory cells specified at the same time by the specification means (163). Semiconductor memory device according to claim 44, wherein said control means (166) carry out at once a data transfer operation between the fixed number of the memory cells specified by the specification means (163) and the store means (167) in accordance with the basic clock signal and the specification signal, said data input/output (I/O) means (164, 168) executes sequentially a data read-out/write-in operation (data I/O operation) for the store means in accordance with the basic clock signal, and said count means (165) counts the number of cycles of a basic clock signal. Semiconductor memory device according to one of the claims 44 - 45, wherein the control means (166) receives at least one or more specification signals provided from an external section, outputs a control signal per specification signal for specifying a particular cycle as a starting cycle to count the number of the cycles of the basic clock signal, instructs the count means (165) to count the number of counts of the basic clock signal based on the control signal, controls a specification operation executed by the specification means (163) and the data I/O operation of the data I/O means (164, 168) based on the number of the cycles including the number of the cycles at least two or more counted from the particular cycle by the count means (165), so that the control means (166) controls the memory access operations for the memory cell group (162). Semiconductor memory device according to one of the claims 44 - 46, wherein the store means comprises a plurality of parts (187, 188) each having same construction and stores data in the fixed number of the memory cells, and the control means (186) operates such that during data is transferred between one part (187 or 188) in the store means and an external section in accordance with the basic clock signal, data is transferred between the memory cell group (182) and the other part (187 or 188) in the store means. Semiconductor memory device according to one of the claims 44 - 47, wherein the store means (206) comprises a plurality of registers and a plurality of gates (205), the number of gates (205) is equal to the number of the registers, the registers (206) store all data in the fixed number of the memory cells, and each gate is capable of switching whether or not data in the register is transferred to the memory cell when all data in the store means (206) are transferred at once into the memory cell group. Semiconductor memory device according to one of the claims 44 - 48, wherein the semiconductor memory device (161) comprises serial register means (167) with a plurality of serial registers. Semiconductor memory device according to claim 49, wherein a data transfer operation between said memory cell group (162) and the data input/output means (164) is performed through the serial register means (167) at a time. Semiconductor memory device according to one of the claims 49 - 50, wherein a data transfer operation between said serial register means (167) and data input/output means (164) is performed per serial register based on the period of the external basic clock signal (CLK). Semiconductor memory device according to one of the claims 44 - 51, wherein said control means (166) controls the data transfer between the memory cell group (162) and the serial register means (167) such that the data currently stored in the serial register means (167) are transferred at once. Semiconductor memory device according to one of the claims 44 - 52, wherein said control means (166) controls the data transfer between the data input/output means (164) and the serial register section (167) such that the data are transferred sequentially. Semiconductor memory device according to claim 1, wherein said semiconductor memory device performs a consecutive serial access operation by counting the number of cycles of the basic clock signal (CLK) through a serial register means (187,188) comprising a predetermined number of bits. Semiconductor memory device according to claim 54, wherein said specification means is adapted for specifying a memory cell group (182), comprising a row specification section (183) and a column specification section (181). Semiconductor memory device according to claim 55, wherein a plurality of column are selected at once as a package memory cell section by the column specification section (181). Semiconductor memory device according to claim 56, wherein said serial register means consists of a section (187) and (188) in order to perform a serial access operation for bit data having the number of bits more than that of bit data for the package transfer operation. Semiconductor memory device according to claim 57, wherein package data comprising all of the cell data stored in one cell section of the memory cell group (182) is transferred at one time to the serial register section (187) in the case when a readout operation is performed. Semiconductor memory device according to one of the claims 54 - 58, wherein said control means (186) controls said data write-in/read-out operation between the memory cell group (182) and the serial register sections (187, 188) and the serial register means (187, 188) and said data input/output means (184). Semiconductor memory device according to claim 59, wherein cell data corresponding to a column address (CA) are read out at the rise of the third clock cycle (CLK 3) under control of said count means (185) and said control means (186).

Inventors: SAITO SHOZO, TODA HARUKI, TOKUSHIGE KAORU, SAITO, SHOZO, TODA, HARUKI, TOKUSHIGE, KAORU
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: G11C7
IPC codes: G11C7, G11C8, G11C11, H01L27