Read head arrangement comprising 2n read heads of the MR type, and reproduction arrangement comprising the read head arrangement

Abstract: The read head arrangement comprises n first read heads (h a.1 , ..., h a.n ) and n second read heads (h b.1 , ..., h b.n ) of the magnetoresistance type, n transistors (Tr₁, ..., Tr n ) and switching means (S), where n is an integer greater than two. The first main electrode (collector) of a transistor (Tr i ) is coupled to an i-th output (U i ) of the arrangement. The second main electrode (emitter) of the transistor (Tr i ) is coupled to a first terminal (t₁) of a first read head (h a.i ) and a second read head (h b.i ). The second terminal (t₂) of the first read head (h a.1 ) is coupled to a first terminal (a) of the switching means (S). The second terminal (t₂) of the second read head (h b.i ) is coupled to a second terminal (b) of the switching means (S), of which a third terminal (c) is coupled to a point of constant potential (earth), while i ranges from 1 to n.

Description: FIELD OF THE INVENTION The invention relates to a read head arrangement comprising a plurality of n first read heads and a plurality of n second read heads, all of the magnetoresistance type, the n first read heads being arranged for reading a signal, for example, a digital audio signal, from n first tracks running parallel to each other and in the longitudinal direction of a magnetic record carrier on this record carrier, the n second read heads being arranged for reading a signal, for example, a digital audio signal, from n tracks running parallel to each other and in longitudinal direction of the record carrier on this record carrier, the n second tracks running parallel to the n first tracks on the record carrier, the read head arrangement comprising output terminals for supplying to these output terminals the signals read from the n tracks by the n first and second read heads, where n is greater than 2. The invention particularly relates to the application of such a type of read head arrangement in autoreverse cassette recorders. BACKGROUND OF THE INVENTION A read head arrangement as defined above is known from the book 'The art of digital audio' by J. Watkinson, see § 9.20 titled 'SDAT consumer digital cassette', p 345-349, Focal Press, London, 1988. In autoreverse cassette recorders of this type, when side A of a cassette is reproduced, the direction of transport of the tape is reversed at the moment when the end of the tape is reached so as to enable reproduction of side B of the cassette. In some autoreverse cassette recorders the read heads reading the signals from the tracks of side A are then moved at the same time so that they are positioned above the tracks of side B and are capable of reading the signals from the tracks of side B. In other autoreverse cassette recorders the read head arrangement has a stationary position and comprises as many heads as there are tracks on the A and B sides of the magnetic record carrier. During the interval in which the direction of transport is changed, a change is also made from reading side A, by means of the n first read heads, to reading side B by means of n second read heads. The read head arrangement is intended to be used in such an autoreverse cassette recorder. For reading a signal, for example a digital signal, from n adjacent tracks on the record carrier, read heads of the magnetoresistance type usually manufactured in thin-film technology are used, especially where n is much greater than 2. Thin-film heads of this type are realised on a chip. It is customary nowadays with multi-track thin-film heads to lead the electrical outputs of the heads individually from the chip to the exterior so that then at least 2n+1 outputs on the chip are necessary. SUMMARY OF THE INVENTION It is an object of the invention to propose a read head arrangement in which the read heads select in a special manner so that fewer outputs on the chip may suffice. For this purpose, the read head arrangement is characterised in that the read head arrangement has n output terminals and n amplifier stages, each amplifier stage having an input with a low-dynamic input resistance and an output, in that the output of the i-th amplifier stage is coupled to the i-th output terminal, the input of the i-th amplifier stage being coupled to a first terminal of both the i-th first read head and the i-th second read head, a second terminal of the i-th first read head being coupled to a first terminal of a switching means, the second terminal of the i-th second read head being coupled to a second terminal of this switching means, a third terminal of the switching means being coupled to a point of constant potential, and in that the switching means is arranged for connecting the first or the second terminal to the third terminal, and in that i ranges from 1 to n. Preferably, the second terminals of the n first read heads are coupled each to the first terminal of the switching means and the second terminals of the n second read heads are coupled each to the second terminal of the switching means. The invention is based on the understanding that in the prior-art read head arrangement it may sometimes be impossible to realise the 2n+1 outputs. This in view of the limited amount of space available on the chip for the connections. According to the invention use is made of the feature that a thin-film read head of the magnetoresistance type is capable of reading a signal from a track only if the read head is conveying current. The selection may thus be realised by allowing the appropriate read heads to current conducting. According to the invention first terminals of corresponding read heads, that is to say, the i-th first read head and the i-th second read head, are electrically interconnected on the chip and connected to the input of the associated amplifier stage. Since the inputs of the amplifier stages have a low-dynamic input resistance, a low a.c. current resistance is obtained at the common terminal of the read heads to be selected, so that crosstalk between the current-carrying read heads as a result of the electrical connection via the read heads not carrying current can be minimized. The n amplifier stages are each in the form of a transistor having a base earthed for a.c. current, a first main electrode of the i-th transistor constituting the output of the i-th amplifier stage and a second main electrode of the i-th transistor constituting the input of the i-th amplifier stage. With amplifier stages in the form of a transistor one may think of an amplifier stage consisting of only a single transistor, but also amplifier stages consisting of more than one transistor, for example, a Darlington pair. In this respect it should be observed that the selection of read heads of the magnetoresistance type is known per se from United States Patent 4,020,364 (PHN 7728), in the name of the Applicants. BRIEF DESCRIPTION OF THE DRAWING(S) The invention will be further explained with reference to an exemplary embodiment, in which Fig. 1 shows an exemplary embodiment of the read head arrangement, and Fig. 2 shows the magnetic record carrier having the 2n tracks. DESCRIPTION OF EMBODIMENTS Fig. 1 shows the read head arrangement comprising a plurality of n first read heads h a.1 , h a.2 , h a.3 , ..., h a.n-1 , h a.n and a plurality of n second read heads h b.1 , h b.2 , h b.3 , ..., h b.n-1 , h b.n , all of the magnetoresistance type. The read heads h a.1 to h a.n read out signals contained in the n tracks T a.1 to T a.n on the A side of a record carrier 20. This is represented in Fig. 2. The direction of transport of the record carrier 20 when the tracks T a.1 to T a.n are read out is denoted in these tracks by means of the arrows. The read heads h b.1 to h b.n read out signals contained in n tracks T b.1 to T b.n respectively, on the B side of the record carrier 20, cf. Fig. 2. n is an integer greater than two. In Fig. 1 only the electrical equivalent of the MR heads, that is to say the resistors, is shown. The arrangement further includes n amplifier stages having each an input with a low-dynamic input resistance and an output. The exemplary embodiment of Fig. 1 shows amplifier stages in the form of a transistor T r1 to T rn respectively, having a base earthed for a.c. current. The emitters of the transistors T r1 to T rn form the inputs of the amplifier stages and the collectors form the outputs of the amplifier stages. The amplifier stages may consist of a single transistor. However, it is altenatively possible to manufacture the amplifier stages of more than one transistor. Darlington pairs may be considered for an amplifier stage. The transistors may be bipolar transistors, but also different types of transistors such as MOS transistors are possible. Fig. 1 shows an exemplary embodiment comprising npn transistors. The first main electrodes (collectors) of the transistors are coupled each to a first point 1 of constant potential (V cc ) by means of an impedance in the form of a resistor. Furthermore, the first main electrode (collector) of the i-th transistor Tr i is coupled to an i-th output terminal u i of n output terminals u₁ to u n . The first terminal t₁ of the i-th first read head h a.i is coupled to the first terminal t₁ of the i-th second read head h b.i . Both first connecting points are additionally coupled to the second main electrode (emitter) of the transistor Tr i . The second connecting point t₂ of the first read head h a.i is coupled to a first terminal a of a switching means, in the form of a single switch S. The second connecting point of the second read head h b.1 is coupled to a second terminal b of the switching means S. This holds for any value of i, where i ranges from 1 to n. A third terminal c of the switching means S is coupled to a second point 2 of constant potential (earth). The control electrodes (bases) of the transistors are mutually coupled. The voltages on these control electrodes are produced by the voltage divider constituted by the resistors R₁ and R₂ and the capacitance C p , inserted between the first and second points of constant potential. With the switching means S in the state in which terminal c is connected to terminal a, the return line l₁ is allowed to convey current. In this fashion the read heads h a.1 to h a.n are selected and the signals read by these read heads from the tracks T a.1 to T a.n can be presented at the output terminals u₁ to u n respectively, by means of the transistors Tr₁ to Tr n . With the switching means S in the state in which terminal c is connected to terminal b, the return line l₂ is allowed to convey current. Through this line the read heads h b.1 to h b.n are selected and the signals read from the tracks T b.1 to T b.n by these read heads can be presented at the output terminals u₁ to u n by means of the transistors Tr₁ to Tr n . The reading of a signal by a head, for example, the head h a.1 , means that the signals recorded in the tracks realise a resistance variation in the head resistance. Due to the power flowing through the head this might lead to voltage variations over the head, and thus to voltage variations on the emitter of the transistor Tr₁. By means of the non-activated heads h b.1 and h b.2 and the return line l₂ these voltage variations might cause cross-talk on the emitter of the transistor Tr₂, which is undesirable. Because the input of all amplifier stages for a.c. current has a low input impedance, it is avoided (in the best way possible) that voltage variations occur across the head h a.1 , so that (practically) no cross-talk to another input can take place. In the present example the low-dynamic input impedance is realised by means of a transistor having a base earthed for a.c. current. Self-evidently, the switch S can be realised electronically. The read head arrangement as discussed hereinbefore can be applied to an arrangement for reading a digital signal from n tracks on a record carrier, as is described in EP-A 436 991 or EP-A 448 160 or EP-A 455 293 which are assumed to be incorporated in this application where necessary. It should be observed in this respect that the invention is not restricted solely to the exemplary embodiment shown. The various modifications of the described exemplary embodiment are conceivable without leaving the scope of the invention as defined in the claims.

Claims: Read head arrangement comprising a plurality of n first read heads and a plurality of n second read heads, all of the magnetoresistance type, the n first read heads (h a.1 to h a.n ) being arranged for reading a signal, for example, a digital audio signal, from n first tracks (T a.1 to T a.n ) running parallel to each other and in the longitudinal direction of a magnetic record carrier (20) on this record carrier, the n second read heads being arranged for reading a signal, for example, a digital audio signal, from n second tracks (T b.1 to T b.n ) running parallel to each other and in longitudinal direction of the record carrier on this record carrier, the n second tracks running parallel to the n first tracks on the record carrier, the read head arrangement comprising output terminals for supplying to these output terminals the signals read from the n tracks by the n first and second read heads, where n is greater than 2, characterized in that the read head arrangement has n output terminals (u₁ to u n ) and n amplifier stages (Tr₁ to Tr n ), each amplifier stage having an input with a low-dynamic input resistance and an output, in that the output of the i-th amplifier stage is coupled to the i-th output terminal, the input of the i-th amplifier stage (Tr i ) being coupled to a first terminal of both the i-th first read head (h a.i ) and the i-th second read head (h b.i ), a second terminal of the i-th first read head being coupled to a first terminal (a) of a switching means (S), the second terminal of the i-th second read head being coupled to a second terminal (b) of this switching means (S), a third terminal (c) of the switching means being coupled to a point of constant potential (2), and in that the switching means is arranged for connecting the first or the second terminal to the third terminal, and in that i ranges from 1 to n. Read head arrangement as claimed in Claim 1, characterised in that the second terminals of the n first read heads (h a.1 to h a.n ) are coupled each to the first terminal (a) of the switching means and in that the second terminals of the n second read heads (h b.1 to h b.n ) are coupled each to the second terminal (b) of the switching means (S) Read head arrangement as claimed in Claim 1 or 2, characterised in that the n amplifier stages are each in the form of a transistor having a base which is earthed for a.c. current, a first main electrode of the i-th transistor (Tr i ) constituting the output of the i-th amplifier stage and a second main electrode of the i-th transistor constituting the input of the i-th amplifier stage. Read head arrangement as claimed in Claim 3, characterised in that the first main electrode of the transistor is the collector and the second main electrode is the emitter. Reproduction arrangement for reproducing a digital signal, for example a digital audio signal, from n tracks running in parallel and in the longitudinal direction of a magnetic record carrier (20) on this record carrier, comprising a read head arrangement as claimed in one of the preceding claims.

Inventors: SOMERS GERARDUS HENRICUS JOHAN, SOMERS, GERARDUS HENRICUS JOHANNUS
Applicants: PHILIPS ELECTRONICS NV, PHILIPS ELECTRONICS N.V.
Application year: 1991
Main classification: G11B5
IPC codes: G11B15, G11B5