Semiconductor integrated circuit

Abstract: In a semiconductor integrated circuit, a digital circuit section (33) and an analog circuit section (34) are formed on a substrate. A pair of first power source lines (11, 18) connects a circuit element in the digital circuit section (33) to a power source, while a pair of second power source lines (12, 19) connects a substrate region in the digital circuit section (33) to the power source. The pair of second power source lines (12, 19) is formed separately from the pair of first power source lines (11, 18) in the digital circuit section (33). The substrate region in the digital circuit section (33) is surrounded by a guard ring well (31), to which one (19) of the pair of second power source lines is connected.

Description: This invention relates to a semiconductor integrated circuit comprising a substrate; a digital circuit section including a circuit element formed on a region of said substrate; an analog circuit section formed on another region of said substrate to be spaced from said digital circuit section; power source means; a pair of first power source lines connecting said power source means to said circuit element included in said digital circuit section; and a pair of second power source lines arranged to be spaced from said pair of first power source lines, and connecting said power source means to said analog circuit section, said pair of second power source lines both connecting said region of said substrate included in said digital circuit section such that said digital circuit section shares said pair of second power source lines with said analog circuit section. Such a circuit is described in EP-A-0 255 125. Fig. 5 shows a conventional pattern of power source lines for a digital circuit section 40 in a large-scale integrated circuit containing analog circuit sections and digital circuit sections. Here, numeral 41 indicates a V cc line; 42 a contact portion of the V cc line with an n + region 43 in an n-type semiconductor substrate; 44 a p-channel MOS transistor region formed in the n-type semiconductor substrate; 45 a p-well formed in the n-type semiconductor substrate; 46 an n-channel MOS transistor region formed in the p-well, 47 a V ss line (the ground potential); and 48 a contact portion of the V ss line with a p + region 49 in the p-well 45. That is, in the digital circuit section 40, the power source lines 41 and 47 are formed so as to connect to both a circuit element and the substrate (the n-type semiconductor substrate or p-well 45). In LSIs containing both analog and digital circuit sections, electric noise (e.g. noise due to high-speed switching) generated at the digital circuit section 40 often travels along the power source lines 41 and 47, and reaches the substrate via the contact portions 42 and 48 of the lines 41 and 47 with the substrate. It then spreads over the substrate and is absorbed by an analog circuit section (not shown). Such absorption gives an adverse effect on the analog circuit section. As described above, in conventional semiconductor integrated circuits containing both analog circuit sections and digital circuit sections, the leakage of noises occurring at a digital circuit section into the substrate via the digital circuit power source lines often adversely affects the analog circuit sections. IBM Technical Disclosure Bulletin, Vol. 27, No. 6, Nov. 1984, P. 3344 shows a CMOS circuit with an I/O section and an array in the centre of the chip. A single wire is provided to bias the substrate of the I/O section, to improve latch-up characteristics. It is an object of the present invention to provide a semiconductor integrated circuit that minimizes noise generated at a digital circuit section from leaking from the power source lines to the substrate, so that such noise does not adversely affect other circuit sections, such as analog circuit sections, thereby ensuring their stable characteristics. According to the present invention, there is provided a semiconductor integrated circuit as set out in claim 1. It is preferable to connect the pair of first power source lines and the pair of second power source lines to separate power source pads, respectively. The digital circuit section may share the pair of second power source lines with the other circuit sections. In an embodiment, the substrate region in the digital circuit section is surrounded by a guard ring well, to which one of the pair of second power source lines is connected. With this invention, even if noise occurring at the digital circuit section travel along the first power source lines, the separate formation of the second power source lines from the first power source lines at least in the digital circuit section prevents such noise from leaking into the substrate via the contact portion of the second power source lines with the substrate. As a result of this, the other circuit sections are not adversely affected, providing the stable characteristic of the other circuit sections. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is an explanatory diagram for a power source line layout of a digital circuit section in a semiconductor integrated circuit; Fig. 2 is an explanatory diagram for a layout of a semiconductor integrated circuit not covered by the present invention; Fig. 3 is an explanatory diagram for a layout of another semiconductor integrated circuit not covered by the present invention; Fig. 4 is an explanatory diagram for a layout of a semiconductor integrated circuit according to an embodiment of the present invention; and Fig. 5 is an explanatory diagram for a layout of a conventional semiconductor integrated circuit. Fig. 1 shows a wiring pattern from the power source 5 to a digital circuit section 10 in an LSI where the digital circuit section 10 is packed together with an analog circuit section. Here, a CMOS inverter is used as the digital circuit section 10, for example. In the figure, numeral 11 indicates a first V cc line connected to a circuit element in the digital circuit section 10; 12 a second V cc line connected to a substrate (an n-type semiconductor substrate) in the digital circuit section 10; and 13 a contact portion of the second V cc line with an n + region 14 in the n-type semiconductor substrate. Numeral 15 represents a p-channel MOS transistor region formed in the n-type semiconductor substrate; 16 a p-well formed in the n-type semiconductor substrate; and 17 an n-channel MOS transistor region formed in the p-well 16. Numeral 18 indicates a first V ss line (the ground potential) connected to the circuit element in the digital circuit section 10; 19 a second V ss line (the ground potential) connected to the substrate (the p-well 16) in the digital circuit section 10, and 20 the contact portion of the second V ss line 19 with a p + region 21 in the p-well 16. Numeral 22 represents a source contact portion of the p-channel transistor; 23 a gate electrode of the MOS transistor; 24 a drain contact portion of the p-channel transistor; 25 a drain contact portion of the n-channel transistor; 26 a drain wiring between the p-channel transistor and n-channel transistor; and 27 a source contact portion of the n-channel transistor. At least in the digital circuit section, the first power source lines 11 and 18 connected to the circuit element in the digital circuit section 10 is formed separately from the second power source lines 12 and 19 connected to the substrate (the n-type semiconductor substrate or p-well 16) in the same section 10. Outside the digital circuit section, the first lines 11 and 18 and the second lines 12 and 19 are preferably kept separated from each other on the semiconductor chip and connected to power source pads 28a through 28d, respectively. In this region, they may be formed integrally so as to meet each other near the power source pads (not shown) on the semiconductor chip. With the LSI of Fig. 1, even if noises occurring at the digital circuit section 10 travel along the first lines 11 and 18 in the same section 10, the separate formation of the first lines 11 and 18 from the second lines 12 and 19 at least in the digital circuit section prevents the noises from leaking into the substrate via the contact portions 13 and 20 of the second lines 12 and 19 with the substrate. Thus, other circuit sections, such as analog circuit sections, (not shown) are not adversely affected, leading to the stable characteristics of the other circuit sections. Fig. 2 illustrates the layout of a semiconductor integrated circuit not covered by the present invention. This circuit contains a plurality of digital circuit sections 30 and 32. The same parts in Fig. 2 and Fig. 1 are indicated by the same reference characters. In this circuit, a first digital circuit section 30 (particularly, a digital circuit section that tends to generate large amounts of noise, such as a high-power output buffer or a high-frequency digital circuit section) and the other digital circuit section 32 each have the construction as shown in Fig. 1. That is, the first digital circuit section 30 contains the first power source lines 11 and 18 and the second power source lines 12 and 19, while the other digital circuit section 32 contains the first power source lines 11' and 18' and the second power source lines 12 and 19 that are shared by the first digital circuit section 30. The substrate region (e.g., the n-type semiconductor substrate) in the first digital circuit section 30 is surrounded by a guard ring well (e.g., a p-well) 31. To this guard ring well 31, one of the second lines 12 and 19 is connected. (In this embodiment, the second V ss line 19 is connected.) With the LSI of Fig. 2, which assures the similar results to those described in Fig. 1, use of the guard ring 31 prevents noises from leaking from the digital circuit section 30 that causes a large amount of noise to other circuit sections, such as the other digital circuit section 32 and, in some cases, an analog circuit section (not shown) on the same substrate. Fig. 3 shows another layout for a semiconductor integrated circuit not covered by the present invention. This circuit contains a digital circuit section 33 and an analog circuit section 34. The same parts in Figs. 3, 2, and 1 are indicated by the same reference characters. In this embodiment, the digital circuit section 33 contains the first power source lines 11 and 18 and the second power source lines 12 and 19, while the analog circuit section 34 contains a V cc line 35 and a V ss line 36. The entire substrate (e.g., the n-type semiconductor substrate) region in the digital circuit section 33 is surrounded by a guard ring well (e.g., a p-well) 31, to which one of the second lines 12 and 19 is connected. (In this circuit, the second V ss line 19 is connected.) With the LSI of Fig. 3, which ensures the similar results as those in Fig. 1, use of the guard ring 31 prevents noises from leaking from the digital circuit section 33 that causes especially large amounts of noise to the analog circuit 34. Fig. 4 shows the layout for a semiconductor integrated circuit according to an embodiment of the present invention. This circuit includes the digital circuit section 33 and the analog circuit section 34. The same parts in Figs. 4, 3, 2, and 1 are indicated by the same reference characters. In this embodiment, the second power lines 12 and 19 are shared by the digital circuit section 33 and the analog circuit section 34. While in each embodiment described above, an LSI whose p-well is formed in the n-type semiconductor substrate is used, an LSI whose n well is formed in the p-type semiconductor substrate may be used, providing the similar results as described above.

Claims: A semiconductor integrated circuit comprising: a substrate; a digital circuit section (33) including a circuit element formed on a region of said substrate; an analog circuit section (34) formed on another region of said substrate to be spaced from said digital circuit section; power source means; a pair of first power source lines (11, 18) connecting said power source means to said circuit element included in said digital circuit section (33); and a pair of second power source lines (12, 19) arranged to be spaced from said pair of first power source lines, and connecting said power source means to said analog circuit section, said pair of second power source lines both connecting said region of said substrate included in said digital circuit section (33) such that said digital circuit section (33) shares said pair of second power source lines (12, 19) with said analog circuit section (34); characterized in that: said region of said substrate included in said digital circuit section (33) has a first part of a first conductivity type and a second part of a second conductivity type formed of a well (16) in said substrate; said circuit element included in said digital circuit section (33) has first and second MOS transistors (15,17) having second and first conductivity channel types, respectively, and arranged in said first and second parts, respectively, with their drains (24,25) connected to each other; said pair of first power source lines (11,18) are connected to the sources (22,27) of said first and second MOS transistors (15,17), respectively; and said pair of second power source lines (12,19) are connected to said first and second parts, respectively. A semiconductor integrated circuit according to claim 1, wherein said region of said substrate included in said digital circuit section (33) is surrounded by a guard ring well (31), to which one (19) of said pair of second power source lines is connected. A semiconductor integrated circuit according to claim 1 or 2, wherein said pair of first power source lines and said pair of second power source lines are connected to separate power source pads.

Inventors: ISHIKAWA KAZUO, TERASHIMA KAORU, ISHIKAWA, KAZUO, TERASHIMA, KAORU, Ishikawa, Kazuo, c/o Intellectual Property Div., Terashima, Kaoru, c/o Intellectual Property Div.
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1991
Main classification: H01L27
IPC codes: H01L27, H01L21