Vector calculation apparatus capable of rapidly carrying out vector calculation of two input vectors

Abstract: In a vector calculation apparatus, a vector adder (21) produces an adder output signal (E) by calculating a three-term sum of a first, a second, and a third adder input signal which are produced in accordance with the adder output signal, a predetermined value ("0"), a first vector (A), and a second vector (B) under control of a control circuit (29). A first selecting circuit (26) selects, as a first selected signal, one of the adder output signal and the first vector. A second selecting circuit (27) selects, as a second selected signal, one of the adder output signal and the second vector. A zeroth selecting circuit (24) selects, as a zeroth selected signal, one of the adder output signal and the predetermined value. The vector adder is supplied with the first selected signal as the first adder input signal, with the second selected signal as the second adder input signal, and with the zeroth selected signal as the third adder input signal.

Description: This invention relates to a vector calculation apparatus for carrying out vector calculation on a plurality of vectors. It is to be noted throughout the instant specification that each of the vectors is composed of a plurality of vector components or elements. These are in the form of electrical signals for electrical processing, although a specific description will not be made hereinafter. A recent requirement for an electronic digital computer is to process a vector calculation at a high speed. The vector calculation is, for example, vector addition of calculating a sum of a pair of vectors. During the vector addition, addition of components of the respective vectors must be repeated a great number of times. This is because each of the vectors is usually composed of many components. Various conventional vector calculation apparatus are used in the electronic digital computer. One conventional vector calculation apparatus includes a two-input vector adder for carrying out addition of two adder input signals. Supplied with the vectors as the adder input signals, the two-input vector adder carries out the addition to produce an adder output signal representative of the sum of vectors. This vector calculation apparatus requires a relatively long time as will later be described in detail. A different conventional vector calculation apparatus includes a three-input vector adder and a selecting circuit. The three-input vector adder is for carrying out addition of three adder input signals to produce an adder output signal. The selecting circuit is for selecting, as a selected signal, a selected one of the adder output signal and a predetermined value, such as zero. Supplied with the vectors and the selected signal as the adder input signals, the three-input vector adder carries out the addition to produce the adder output signal. As will later be described in detail, this other vector calculation apparatus has a disadvantage in that a very long time is necessary to calculate the sum in the case where the vectors are composed of an enormous number of components. EP-A-0 214 775 discloses a multi-precision fixed/floating-point processor with a three-port ALU, four storage registers, a constant store circuit, and an output data register. Each of the registers is provided with three output ports and corresponding pass gates for selectively transferring data from the registers to the three inputs of the ALU. The constant store is also coupled to one of the input ports of the ALU by means of a pass gate. Results of the ALU are provided to the data output register for further processing. It is therefore an object of this invention to provide a vector calculation apparatus which can carry out a vector calculation of two vectors at a high speed. It is another object of this invention to provide a vector calculation apparatus of the type described, which can quickly calculate a total sum of two vectors. It is still another object of this invention to provide a vector calculation apparatus of the type described, which is convenient for processing vectors composed of an enormous number of components. These objects are achieved with the features of independent claim 1. Fig. 1 is a block diagram of a conventional vector calculation apparatus for use in carrying out vector addition; Fig. 2 is a time chart for use in describing operation of the vector calculation apparatus illustrated in Fig. 1; Fig. 3 is a block diagram of another conventional vector calculation apparatus; Fig. 4 is a time chart for use in describing the operation of the vector calculation apparatus illustrated in Fig. 3; Fig. 5 is a block diagram of a vector calculation apparatus according to an embodiment of this invention; and Figs. 6(A) and 6(B) show, when Fig. 6(B) is connected to Fig. 6(A), a time chart for use in describing the operation of the vector calculation apparatus illustrated in Fig. 5. Referring to Fig. 1, a conventional vector calculation apparatus will first be described for a better understanding of this invention. The conventional vector calculation apparatus is for use in carrying out vector addition of two vectors. The illustrated vector calculation apparatus comprises a two-input vector adder 11 which is connected to first and second input lines 16 and 17. The vectors are supplied as a first and a second adder input signal to the vector adder 11 through the first and the second input lines 16 and 17, respectively, and may be called first and second input vectors A and B (such vectors being denoted herein by capital letters rather than either by thick letters or by the capital letters with horizontal arrows over them). It will be assumed that the first input vector A is composed of a sequence of first-set components or elements (a 1 , a 2 , ..., a n ) which may be called first through n-th components of the first input vector A, respectively. Likewise, the second input vector B is composed of a sequence of second-set components (b 1 , b 2 , ..., b n ) which may be referred to as first through n-th components of the second input vector B. It is assumed in this manner in the illustrated example that the first input vector A has the same number of components as the second input vector B. The vector addition of the first and the second input vectors A and B is for calculating an output vector O composed of a sequence of output components (o 1 , o 2 , ..., o n ) which may be called first through n-th output components. Specifically, the vector adder 11 successively sums up the first-set and the second-set components (a 1 , a 2 , ..., a n ) and (b 1 , b 2 , ..., b n ) to produce the first through the n-th output components (o 1 , o 2 , ..., o n ) which appear on an adder output line 18. Each output component o i is given by: o i = a i + b i , where i is variable between 1 and n, both inclusive. Referring to Fig. 2 in addition to Fig. 1, the description will be made as regards calculation of a total sum of 2 k components of the first and the second input vectors A and B, where k represents a predetermined number, 2 k being not greater than n. A calculation time will be assumed to be equal to mT, where m is an integer and T is representative of a clock cycle which is determined by a sequence of clock pulses. The clock cycle is illustrated along a first or top row labelled CLK. The first-set components are depicted along a second row labelled A. The second-set components are illustrated along a third row labelled B. The adder output signal is shown along a fourth or bottom row labelled O. The 2 k components are divided at first into the first-set and the second-set components. The first-set components are 2 k-1 in number. The second-set components are also 2 k-1 in number. First ones a 1 and b 1 of the components of the first and the second input vectors A and B are supplied through the first and the second input lines 16 and 17 to the vector adder 11 in timed relation to a zeroth one of the clock pulses. Subsequently, second through 2 k-1 -th components of the first and the second input vectors A and B are successively supplied to the vector adder 11 in synchronism with first through (2 k-1 - 1)-th clock pulses, respectively. In Fig. 2, a simplified symbol r is substituted for 2 k-1 merely for simplification of illustration. A simplified symbol s is substituted for 2 k-2 merely for simplification of illustration. The simplified symbols will be used also in the following. In the manner depicted in Fig. 2, first through r-th components o 1 to o r appear as local sum components on the output line 18 in synchronism with m-th through (r + m - 1)-th clock pulses, respectively. A calculation time of (2 k-1 + m - 1)T is required to calculate the 2 k-1 local sum components. Therefore, a total calculation time TCT is given by: When it is assumed that m is equal to 9 and that k is equal to 8, the total calculation time TCT is as follows: TCT = {2 k - 1 + k(m - 1)}T = {2 8 - 1 + 8(9 - 1)}T = (2 8 + 63)T. Referring to Fig. 3, the description will be directed to a different conventional vector calculation apparatus. The different conventional vector calculation apparatus comprises similar parts designated by like reference numerals. In Fig. 3, the vector calculation apparatus comprises a three-input vector adder 21 which is for carrying out vector addition of three vectors. The vector adder 21 is connected to a third input line 23 in addition to the first and the second input lines 16 and 17. Two of the vectors are supplied as the first and the second input vectors A and B to the vector adder 21 through the first and the second input lines 16 and 17. The remaining one of the three vectors is supplied as a third adder input signal to the vector adder 21 through the third input line 23 and may be called a third vector C (such a vector being also denoted herein by capital letters rather than by thick letters). As will later be described in detail, the third vector C is composed of a sequence of third-set components and is assumed to have the same number of components as each of the first and the second vectors A and B. Supplied with the first through the third vectors A, B, and C, the vector adder 21 carries out the vector addition to produce an output vector D as an adder output signal representative of a result of the vector addition. The output vector D is composed of a sequence of output components (d 1 , d 2 , ..., d n ) which may be called first through n-th output components. Specifically, the vector adder 21 successively sums up the first-set, the second-set, and the third-set components to produce the first through the n-th output components (d 1 , d 2 , ..., d n ) which appear on the output line 18. Each output component d i is given by: d i = a i + b i + c i . The vector calculation apparatus further comprises a selecting circuit 24 which is connected to the output and the third input lines 18 and 23 and to an additional input line 25. The selecting circuit 24 is for selecting, as a selected signal, one of the adder output signal and a predetermined value which may be "0" and is supplied through the additional input line 25. The selected signal is supplied as the third vector C to the vector adder 21 through the third input line 23. Therefore, the third vector C is composed of one of the predetermined value and the first through the n-th output components (d 1 , d 2 , ..., d n ). Referring to Fig. 4 in addition to Fig. 3, the description will be made as regards operation of the vector calculation apparatus. The first-set components are depicted along a first or top row labelled A. The second-set components are illustrated along a second row labelled B. The third-set components are illustrated along a third row labeled C. The adder output signal is shown along a fourth row labelled D. The operation of the vector calculation apparatus is controlled in accordance with each of successive timing cycles which comprises zeroth, first through (m - 1)-th, m-th, (m + 1)-th through (n - 1)-th, and n-th through (n + m - 1)-th cycle times 0, 1 to (m - 1), m, (m + 1) to (n - 1), n to (n + m - 1). During the zeroth through the (m - 1)-th cycle times 0 to (m - 1), the selecting circuit 24 selects in each of the timing cycles the predetermined value "0" as the selected signal. Therefore, the vector adder 21 carries out the vector addition as follows: d i = a i + b i + 0. At the m-th cycle time m, the selecting circuit 24 selects the first output component d 1 as the selected signal in the manner indicated by an upwardly directed arrow drawn from a fourth of bottom row labelled D to the third row C. The first output component d 1 is supplied to the vector adder 21. In this manner, the second through (n - m)-th output components d 2 through d n-m are supplied to the vector adder 21 during the (m + 1)-th through (n - 1)-th cycle times (m + 1) to (n - 1). Therefore, the vector adder 21 carries out the vector addition as follows: d i = a i + b i + d i-m . As a result, the vector adder 21 produces first local addition results m times, when i varies from (2 k-1 - m + 1) to 2 k-1 through (2 k-1 - m + 2), ..., and so forth. The first local addition results are divided into a first and a second group. The operation of the vector calculation apparatus is carried out again with the first and the second groups supplied to the vector adder 21 as the first and the second input vectors A and B. As a result, the vector adder 21 produces second local addition results for use as the first and the second input vectors A and B. In this manner, the second local addition results are repeatedly obtained to result in the total sum of 2 k components. The calculation time of (2 k-1 + m - 1)T is required in order to obtain the first local addition results. The calculation time of {2 p - 1 + p(m - 1)}T is required to obtain the second local addition results m times, where p represents a predetermined number, and m being as follows: 2 p > m > 2 p-1 . Accordingly, the total calculation time TCT is given by: TCT = [(2 k-1 + m - 1) + {2 p - 1 + p(m - 1)}]T = {2 k-1 + 2 p - 1 + (p + 1)(m - 1)}T. When it is assumed that m is equal to 9, that k is equal to 8, and that p is equal to 4, the total calculation time TCT is as follows: TCT = {2 k-1 + 2 p - 1 + (p + 1)(m - 1)}T = {2 8-1 + 2 4 - 1 + (4 + 1)(9 - 1)}T = (2 8-1 + 55)T. Namely, the vector calculation apparatus has a disadvantage in that a very long time is necessary to calculate the total calculation time in case where m is relatively great. Referring to Fig. 5, the description will be directed to a vector calculation apparatus according to an embodiment of this invention. The vector calculation apparatus comprises similar parts designated by like reference numerals. Herein, the selecting circuit 24 is referred to as a zeroth selecting arrangement. In Fig. 5, the vector calculation apparatus comprises first and second selecting circuits 26 and 27. In the manner which will presently be described more in detail, the first selecting circuit 26 is connected to the first input line 16 and the three-input vector adder 21 and is for selecting, as a first selected signal, a selected one of the first-set components of a first vector supplied through input line 16 and the vector adder 21 output signal E. The second selecting circuit 27 is connected to the second input line 17, the vector adder 21, and a supplementary input line 28 and is for selecting, as a second selected signal, a selected one of the second-set components of a second vector supplied through input line 17, the vector adder 21 output signal E, and the predetermined value that is supplied through the supplementary input line 28. Furthermore, the vector calculation apparatus according to an embodiment of this invention comprises zero selecting circuit 24 connected to the vector adder 21 and to a supplementary input line 25 and it is for selecting as zero-th selected signal a selected one of the vector adder 21 output signal E and the predetermined value that is supplied through the supplementary input line 25. The vector calculation apparatus further comprises a control circuit 29, a first register 31, a second register 32, and a third register 33. The control circuit 29 is connected to the vector adder 21 and the first through the third registers 31 to 33 and to the zeroth, the first, and the second selecting circuits 24, 26, and 27 through the first through the third registers 31 to 33 and is for controlling the vector adder 21, the first through the third registers 31 to 33 and the zeroth, the first, and the second selecting circuits 24, 27, and 28 as will later be described in detail. It will shortly be described that the first register 31 is connected to the vector adder 21 and the first selecting circuit 26 and is for memorizing the first selected signal as a first memorized signal to supply the first memorized signal as the first adder input signal to the vector adder 21 under control of the control circuit 29. The second register 32 is connected to the vector adder 21 and the second selecting circuit 27 and is for memorizing the second selected signal as a second memorized signal to supply the second memorized signal as the second adder input signal to the vector adder 21 under control of the control circuit 29. The third register 33 is connected to the vector adder 21 and the zeroth selecting circuit 24 and is for memorizing the zeroth selected signal as a zeroth memorized signal to supply the zeroth memorized signal as the third adder input signal to the vector adder 21 under control of the control circuit 29. A combination of the first through the third registers 31 to 33 is referred to as a supplying arrangement. Referring to Figs. 6(A) and 6(B) in addition to Fig. 5, the description will be made as regards operation of the vector calculation apparatus. The clock cycle is illustrated along a first or top row labelled CLK. The first-set components of the first vector are depicted along a second row labelled A. The second-set components of the second vector are illustrated along a third row labelled B. The first memorized signal is shown along a fourth row labelled 31. The second memorized signal is depicted along a fifth row labelled 32. The zeroth memorized signal is illustrated along a sixth row labelled 33. The adder output signal is shown along a seventh or bottom row labelled E. As will presently be described in detail, the operation of the vector calculation apparatus is controlled in accordance with each of successive timing cycles which comprise zeroth, first through ninth, tenth through seventeenth, eighteenth through twenty-sixth, twenty-seventh through n-th, (n + 1)-th, (n + 2)-th, (n + 3)-th through (n + 8)-th, (n + 9)-th through (n + 11)-th, (n + 12)-th through (n + 14)-th, (n + 15)-th through (n + 17)-th, and (n + 18)-th through (n + 26)-th cycle times 0, 1 to 9, 10 to 17, 18 to 26, 27 to 35, 36 to (n - 1), n, (n + 1), (n + 2), (n + 3) to (n + 8), (n + 9) to (n + 11), (n + 12) to (n + 14), (n + 15) to (n + 17), and (n + 18) to (n + 26). During the zeroth through the (n - 1)-th cycle times 0 to n - 1, the first selecting circuit 26 selects the first-set components of the first vector (a 1 , a 2 , ..., a n ) as the first selected signal, one component in each of the timing cycles. The second selecting circuit 27 selects the second-set components of the second vector (b 1 , b 2 , ..., b n ) as the second selected signal. The control circuit 29 makes the zeroth selecting circuit 24 select the predetermined value as the zeroth selected signal although illustration is not made in Fig. 6. The first-set components of the first vector (a 1 , a 2 , ..., a n ) and the second-set components of the second vector (b 1 , b 2 , ..., b n ) are memorized as the first and the second memorized signals in the first and the second registers 31 and 32, respectively, during the first through the n-th cycle times 1 to n. The predetermined value is memorized as the zeroth memorized signal in the third register 33 at the first through the ninth cycle times 1 to 9. The first, the second, and the zeroth memorized signals are supplied as the first, the second, and the third adder input signals to the vector adder 21. The vector adder 21 carries out addition of the first, the second, and the third adder input signals at each of the first through the ninth cycle times 1 to 9 and produces first through ninth output components (e 1 , e 2 , ..., e 9 ) as the adder output signal at the ninth through the seventeenth cycle times 9 to 17. During the tenth through the eighteenth cycle times 10 to 18, the zeroth selecting circuit 24 selects the adder output signal, namely, the first through the ninth output components (e 1 , e 2 , ..., e 9 ), one component in each of the timing cycles. The first through the ninth output components (e 1 , e 2 , ..., e 9 ) are memorized as the zeroth memorized signal in the third register 33. The first, the second, and the zeroth memorized signals are supplied as the first, the second, and the third adder input signals to the vector adder 21. The vector adder 21 carries out the addition of the first, the second, and the third adder input signals at each of the tenth through the eighteenth cycle times 10 to 18 and produces tenth through eighteenth output components (e 10 , e 11 , ..., e 18 ) as the adder output signal at the eighteenth through the twenty-sixth cycle times 18 to 26. The tenth through the eighteenth output components (e 10 , e 11 , ..., e 18 ) are memorized as the zeroth memorized signal in the third register 33. In this manner, nineteenth through n-th output components (e 19 , e 20 , ..., e n ) are produced in the vector adder 21 at the twenty-seventh through the (n + 8)-th cycle times 27 to n + 8 and are memorized in the third register 33. Thus, the vector adder 21 repeatedly carries out the addition to produce the first through the n-th output components (e 1 , e 2 , ..., e n ) as the adder output signal at the ninth through the (n + 8)-th cycle times 9 to n + 8. In this event, the control circuit 29 makes the zeroth selecting circuit 24 select the adder output signal as the selected signal to store the first through the n-th output components (e 1 , e 2 , ..., e n ) in the third register 33. At the (n + 1)-th cycle time n + 1, the first selecting circuit 26 selects (n - 8)-th output component e n-8 to store the (n - 8)-th output component e n-8 in the first register 31. The second selecting circuit 27 selects the predetermined value to store the predetermined value in the second register 32. The zeroth selecting circuit 24 selects the predetermined value to store the predetermined value in the third register 33. At the (n + 2)-th cycle time n + 2, the control circuit 29 controls the first register 31 to make the first register 31 hold the (n - 8)-th output component e n-8 . The second selecting circuit 27 selects (n - 7)-th output component e n-7 to store the (n - 7)-th output component e n-7 in the second register 32. The zeroth selecting circuit 24 selects the predetermined value to store the predetermined value in the third register 33. At the (n + 3)-th cycle time n + 3, the control circuit 29 controls the first and the second registers 31 and 32 to hold the (n - 8)-th and the (n - 7)-th output components e n-8 and e n-7 in the first and the second registers 31 and 32. The zeroth selecting circuit 24 selects (n - 6)-th output component e n-6 to store the (n - 6)-th output component e n-6 in the third register 33. The (n - 8)-th, the (n - 7)-th, and the (n - 6)-th output components e n-8 , e n-7 , and e n-6 are supplied to the vector adder 21 and summed up in the vector adder 21 to produce (n + 3)-th output components e n+3 at the (n + 11)-th cycle time n + 11 under control of the control circuit 29. In this manner, (n + 6)-th and (n + 9)-th output components e n+6 and e n+9 are produced from the vector adder 21 at the (n + 14)-th and (n + 17)-th cycle times n + 14 and n + 17 under control of the control circuit 29. In this event, the control circuit 29 makes the first, the second, and the zeroth selecting circuits 26, 27, and 24 select the adder output signal as each of the first, the second, and the zeroth selected signals in predetermined order. At the (n + 12)-th cycle time n + 12, the first selecting circuit 26 selects the (n + 3)-th output component e n+3 to store the (n + 3)-th output component e n+3 in the first register 31. The second selecting circuit 27 selects the predetermined value to store the predetermined value in the second register 32. The zeroth selecting circuit 24 selects the predetermined value to store the predetermined value in the third register 33. During the (n + 12)-th through the (n + 26)-th cycle times n + 12 to n + 26, the control circuit 29 controls the first register 31 to make the first register 31 hold the (n + 3)-th output component e n+3 . During the (n + 12)-th through the (n + 14)-th cycle times n + 12 to n + 14, the control circuit 29 controls the second and the third registers 32 and 33 to make the second and the third registers 32 and 33 hold the predetermined value. At the (n + 15)-th cycle time n + 15, the second selecting circuit 27 selects the (n + 6)-th output component e n+6 to store the (n + 6)-th output component e n+6 in the second register 32. The zeroth selecting circuit 24 selects again the predetermined value to store the predetermined value in the third register 33. During the (n + 15)-th through the (n + 26)-th cycle times n + 15 to n + 26, the control circuit 29 controls the second register 32 to make the second register 32 hold the (n + 6)-th output component e n+6 . At the (n + 18)-th cycle time n + 18, the zeroth selecting circuit 24 selects the (n + 9)-th output component e n+9 to store the (n + 9)-th output component e n+9 in the third register 33. During the (n + 18)-th through the (n + 26)-th cycle times n + 18 to n + 26, the control circuit 29 controls the third register 33 to make the third register 33 hold the (n + 9)-th output component e n+9 . The (n + 3)-th, the (n + 6)-th, and the (n + 9)-th output components e n+3 , e n+6 , and e n+9 are supplied to the vector adder 21 and summed up in the vector adder 21 to produce (n + 18)-th output components e n+18 at the (n + 26)-th cycle time n + 26 under control of the control circuit 29. Accordingly, the total calculation time TCT is given by: TCT = (2 k-1 + 26)T. When it is assumed that k is equal to 8, the total calculation time TCT is as follows: TCT = (2 k-1 + 26)T = (2 7 + 26)T. Namely, the vector calculation apparatus can carry out a vector calculation of two vectors at a high speed. While the present invention has thus far been described in connection with only one preferred embodiment thereof, it will now be readily possible for those skilled in the art to put this invention into practice in various other manners. For example, the control circuit 29 may be designed in such a manner that the vector adder 21 produces the adder output signal when less or more than eight cycle times lapse after the vector adder 21 is supplied with the first and the second adder input signals.

Claims: An apparatus for calculating a result of vector calculation involving addition of a first vector composed of a plurality of first-set components and a second vector composed of a plurality of second-set components, said apparatus including: a vector adder (21), said vector adder (21) including three inputs and one output for carrying out addition of a first, a second, and a third adder input signal supplied to said vector adder (21) through said three inputs to produce an adder output signal (E) at said vector adder (21) output as said result; control means (29); zeroth selecting means (24) connected to said vector adder (21) and said control means (29) for selecting, as a zeroth selected signal, a selected one of said adder output signal (E) and a predetermined value supplied through supplementary input line (25); first selecting means (26) connected to said vector adder (21) and said control means (29) for selecting, as a first selected signal, a selected one of said first-set components of said first vector and said adder output signal (E); second selecting means (27) connected to said vector adder (21) and said control means (29) for selecting, as a second selected signal, a selected one of said second-set components of said second vector and said predetermined value supplied through supplementary input line (28), and said adder output signal (E); register means (31, 32, 33) connected to said first, said second, and said zeroth selecting means, said control means (29) and said vector adder (21), for temporarily memorizing said first selected signal, said second selected signal and said zeroth selected signal, and for supplying to said vector adder (21) said first selected signal as said first adder input signal, said second selected signal as said second adder input signal, and said zeroth selected signal as said third adder input signal; and wherein said first selected signal, second selected signal and zeroth selected signal have been previously selected by said first (26), second (27) and zeroth (24) selecting means according to the operation of said first, second and zeroth selecting means as determined by said control means (29); wherein said control means (29) are connected to said vector adder (21), said first, said second, and said zeroth selecting means, and said register means for controlling said vector adder (21), said first, said second, and said zeroth selecting means (26, 27, 24), and said register means (31, 32, 33); wherein said register means (31, 32, 33) comprise: first register means (31) connected to said vector adder (21), said first selecting means (26) and said control means (29) further comprising means for temporarily memorizing said first selected signal as a first memorized signal and means to supply said first memorized signal as said first adder input signal to said vector adder (21) under control of said control means (29); second register means (32) connected to said vector adder (21), said second selecting means (27), and said control means (29) further comprising means for temporarily memorizing said second selected signal as a second memorized signal and means to supply said second memorized signal as said second adder input signal to said vector adder (21) under control of said control means (29) ; and third register means (33) connected to said vector adder (21), said zeroth selecting means (24), and said control means (29) further comprising means for temporarily memorizing said zeroth selected signal as a zeroth memorized signal and means to supply said zeroth memorized signal as said third adder input signal to said vector adder (21) under control of said control means (29); wherein said control means (29) further comprise means to control said second selecting means (27) and said zeroth selecting means (24) in such a way that at the same time said second selecting means (27) and said zeroth selecting means (24) select as said zeroth selected signal and as said second selected signal said predetermined value supplied through said supplementary input line (25) and said supplementary input line (28), respectively. An apparatus as claimed in claim 1, wherein said control means comprises: controlling means (29) connected to said first selecting means (26), said second selecting means (27) and said zeroth selecting means (24) to control said first selecting means, said second selecting means and said zeroth selecting means in such a way to supply the following selections of signals to said first (31), second (32) and third (33) register means by operating said first, second and zeroth selecting means accordingly: a first selection wherein a selected one of said first-set components of said first vector is supplied as first selected signal to said first register means (31), a selected one of said second-set components of said second vector is supplied as second selected signal to said second register means (32) and said predetermined value is supplied as zeroth selected signal to said third register means (33); a second selection wherein a selected one of said first-set components of said first vector is supplied as first selected signal to said first register means (31), a selected one of said second-set components of said second vector is supplied as second selected signal to said second register means (32) and said vector adder (21) output signal (E) is supplied as zeroth selected signal to said third register means (33); a third selection wherein said vector adder (21) output signal (E) is supplied as first selected signal to said first register means (31), said predetermined value is supplied as second selected signal to said second register means (32) and said predetermined value is supplied as zeroth selected signal to said third register means (33); said control means (29) further comprising means to select either said first selection or said second selection or said third selection and to operate said first, second and zeroth selecting means accordingly, following a predetermined order of operations. An apparatus as claimed in claim 2, wherein said control means comprises: controlling means (29) connected to said first selecting means (26), said second selecting means (27) and said zeroth selecting means (24) to control said first selecting means, said second selecting means and said zeroth selecting means in such a way to supply the following selections of signals to said first (31), second (32) and third (33) register means by operating said first, second and zeroth selecting means accordingly: a fourth selection wherein no signal is supplied as first selected signal to said first register means (31), said vector adder (21) output (E) is supplied as second selected signal to said second register means (32) and said predetermined value is supplied as zeroth selected signal to said third register means (33); a fifth selection wherein no signal is supplied as first selected signal to said first register means (31), no signal is supplied as second selected signal to said second register means (32) and said vector adder (21) output signal (E) is supplied as zeroth selected signal to said third register means (33); said control means (29) further comprising means to select either said first selection or said second selection or said third selection or said fourth selection or said fifth selection and to operate said first (26), second (27) and zeroth (24) selecting means accordingly, following a predetermined order of operations.

Inventors: OOTA SHINGO, OOTA, SHINGO, Oota, Shingo, c/o NEC Koufu, Ltd.
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: G06F17
IPC codes: G06F17