Direct microcircuit decoupling

Abstract: Decoupling apparatus 10 for a microcircuit 12 provides for a custom capacitor 20 to be placed directly on the passivated upper surface 11 of the integrated circuit or alternatively to be placed directly under the integrated circuit. In another alternative, multiple standard chip capacitors are placed directly on the passivated upper surface and connected by wire bonds to metal bars also resting on the upper surface.

Description: The invention disclosed herein relates generally to decoupling capacitors for use with integrated circuits. In the past decoupling capacitors for integrated circuits have sometimes been separate devices mounted on a printed wiring board and wired across the power supply and return connection to the dual in-line or other type integrated circuit package. Inductance is dependent on the loop area through which current flows and the magnetic flux through the loop. Voltage drop due to inductance is equal to L di / dt. In the past approach of a separate capacitor on the circuit board the length of the path that the current must flow through from the capacitor to reach the chip contributes to the voltage drop due to L di / dt. Another past approach has been to mount a decoupling capacitor on the chip package to reduce the lead length between the capacitor and the chip. While past methods provide adequate decoupling for many applications, there are other applications that require improved decoupling. An example of such an application is the need for certain integrated circuit devices to be insensitive to being bombarded by ionizing radiation. A basic effect of the ionizing radiation is to generate electron-hole pairs in the semiconductor material. In an integrated circuit having a power supply voltage reference and a ground reference, the effect of being irradiated is to create a high current flow in the chip between the voltage reference and the ground reference. The further effect is for current flowing from the power supply to encounter inductance in the connecting leads from the power supply. The result is that the on-chip voltage essentially collapses. A solution is to place a capacitor across the integrated circuit as close as possible to the integrated circuit so that the capacitor is charged to the chip power supply voltage. Then when a transient due to radiation or any cause occurs, the board capacitor is available to supply current instantaneously to the integrated circuit. Thus a need exists for a decoupling device that can be placed as close as possible to the integrated circuit. GB-A-2091035 describes a decoupling apparatus for a microchip. The chip has a first planar surface, a power supply connection means, and a power return connection means (P). The decoupling apparatus comprises further planar capacitor means (C) having a first termination means and a second termination means, said planar capacitor means located on said planar surface, means for securing said planar capacitor means (C) directly to said first surface with no intermediate insulating layer, means for electrically connecting said first termination means to said power supply connection means (P), and means for electrically connecting said second termination means to said power return connection means. FR-A-2584865 describes a decoupling apparatus, in which a capacitor is disposed directly on the upper surface of an electronic component. The capacitor is connected by wire bonds between contact pads on the component and contact terminations on the capacitor. SUMMARY OF THE INVENTION According to the invention, there is provided a microchip having a planar first surface, a power supply connection means and a power return connection means, including planar decoupling capacitor means having a first termination means and a second termination means, said planar capacitor means being secured directly to said first surface with no intermediate insulating layer; and characterised by the power supply connection means and power return connection means being connected to a respective elongate metal bar on said planar first surface to which a plurality of wire bonds from first termination means and second termination means respectively are connected. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a plan view of an illustrative decoupling device. Figure 2 is a side elevation view of the decoupling device of Figure 1 according to section line 2-2. Figure 3 is a plan view of an alternative illustrative design of decoupling device. Figure 4 is a side elevation view of the decoupling device of Figure 3 according to section line 4-4. Figure 5 is a plan view of a decoupling device in accordance with applicant's invention. Figure 6 is a side elevation view of the decoupling device in Figure 5 according to section line 6-6. DESCRIPTION OF THE PREFERRED EMBODIMENT In Figures 1-6, reference numeral 10 identifies a decoupling apparatus. As shown in Figure 1 microchip 12 has an upper surface 11 and lower surface 13. Power supply connection 14 and a power return connection 16 in the form of bonding pads are located on microchip surface 11. A combination of a power supply V dd , and an adjacent power return V ss , forms a V dd -V ss pair. V dd -V ss pairs are designated 30 and are shown in Figure 1 located near or along side edges 15 and 17 of surface 11. Microchip 12 also includes bonding pads 18 for signal connections. As shown in Figures 1 and 2, custom capacitor 20 is located directly on passivated surface 11. Custom capacitor 20 may be physically attached to surface 11 by any of a variety of bonding agents. Instead of having only a terminal at each end, custom capacitor 20 is designed with pairs of terminal 23 which are made up of individual terminals 22 and 24 which are of the bonding pad type. Wire bond 26 connects power supply connection 14 to capacitor terminal 22 and wire bond 28 connects power return connection 28 to capacitor terminal 24. Capacitor terminals 22 and 24 form a pair of terminals 23. As shown in the drawings, custom capacitor 20 is designed with terminal pairs 23 opposite V dd -V ss pairs 30. In an alternate design approach as shown in Figures 3 and 4, microchip 12' has an upper surface 11'; lower surface 13'; power supply connection 14' and power return connection 16'. Power supply connection 14' and power return connection 16' are in the form of bonding pads located on microchip upper surface 11'. A combination of a power supply 14' or V dd and a power return 16' or V ss form a V dd -V ss pair which is designated 30'. V dd -V ss pairs are located near or along side edges 15' and 17' of surface 11'. Microchip 12' also includes bonding pads 18' for signal connections. As shown in Figures 3 and 4 custom capacitor 20' is located below microchip 12' and is secured by a bonding agent directly against surface 13'. Custom capacitor 20' is designed with pairs of terminals 23' which are made up of individual terminals 22' and 24' which are of the bonding pad type. A design according to the present invention which utilizes standard chip capacitors is shown in Figures 5 and 6 for decoupling apparatus 10. In Figures 5 and 6 microchip 12" has its upper level metallization designed to bring the power supply connection and power return connections to surface 11" at locations which accommodate standard capacitor sizes. For example, in Figure 6 power supply connections may be brought to 40 and power return connections brought to 42 and 44. The design allows standard chip capacitors 46 and 48 to be used. For example, capacitor 46 is a standard chip capacitor which rests directly on surface 11" of microchip 12". Capacitor 46 has terminals 50 and 52 which preferably are gold plated. Metal bars of which 58, 60 and 62 are typical are gold plated and are located directly on surface 11" and electrically connected to power supply 40 and power return 42 by solder bump connections at 42, 40 and 44. Electrical connections from metal bars 58 and 60 to capacitor 46 are made by wire bonds 64 and 66 respectively. Electrical connections from metal bars 60 and 62 to capacitor 48 are made by wire bonds 68 and 70 respectively. Metal bars of which 60 is typical provide a large area contact with passivated surface 11". This area of contact provides for pressure distribution during the wire bonding operation. Therefore the cap attach wire bonds can be made over active circuitry without damage to the microcircuit and without chip area impact. Now that the basic construction of the present invention has been set forth, certain features can be set forth and appreciated. The present invention provides for placing a capacitor on the chip or die rather than placing the die on the capacitor. An advantage of this feature is that the decoupling capacitor can be used as an option and not added until after package test. With this approach, capacitors are not wasted on die which fail the package testing. An additional advantage of placing the capacitor on the die occurs in multichip modules. Because the die size determines the spacing between die there is no need to increase die spacing to accommodate capacitors which are larger than the die. In accordance with the foregoing description, applicant has developed a simple microcircuit decoupling apparatus that may be easily incorporated into the design of integrated circuits when required by the application.

Claims: A microchip (12") having a planar first surface (11"), a power supply connection means (40) and a power return connection means (42, 44), including planar decoupling capacitor means (46, 48) having a first termination means (50) and a second termination means (52), said planar capacitor means (46, 48) being secured directly to said first surface (11") with no intermediate insulating layer; and characterised by the power supply connection means (40) and power return connection means (42, 44) being connected to a respective elongate metal bar (58, 60, 62) on said planar first surface (11") to which a plurality of wire bonds (64, 66, 68, 70) from first termination means (50) and second termination means (52) respectively are connected. A microchip according to claim 1 characterised in that said power supply connection means (40), said power return connection means (42, 44), said first termination means (50) and said second termination (52) means comprise bond pads (14, 16, 22, 24). A microchip according to claim 1 or claim 2 characterised in that said power supply connection means is located adjacent said power return connection means to form a pair of connection means (30) located alongside an edge of said planar surface, and said planar capacitor has a perimeter with said first termination means located adjacent to said second termination means to form a pair of termination means located alongside said perimeter and opposite said pair of connection means. A microchip according to any preceding claim characterised in that said planar first surface is an upper surface. A microchip according to any of claims 1 to 3 characterised in that said planar first surface is a lower surface. A microchip according to any preceding claim characterised in that said planar capacitor means is a plurality of individual capacitors. A microchip according to any preceding claim characterised in that said planar capacitor means comprises one or more individual capacitors with each individual capacitor having an end and an opposite end, said ends being gold plated to form said first and second conductive terminations. A microchip according to claim 7 comprising a first metallic bar (60) electrically connected to said power supply connection means and having a longitudinal axis parallel to said one end or ends, and a second metallic bar (58) electrically connected to said power return connection means and having a longitudinal axis parallel to said opposite end or ends; and wire bonds (66, 64) extending from said first metallic bar to said first conductive termination and from second metallic bar to said second conductive termination. A microchip according to claim 8 characterised in that said metallic bars are gold plated.

Inventors: DUNAWAY THOMAS J, HEINKS MICHAEL W, SPIELBERGER RICHARD, DUNAWAY, THOMAS J., HEINKS, MICHAEL W., SPIELBERGER, RICHARD
Applicants: SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO., LTD.
Application year: 1991
Main classification: H01L23
IPC codes: H01L23, H01L27, H01L21