Clock generating apparatus and data receiving/transmitting apparatus

Abstract: In a data transmitting/receiving apparatus, a master clock signal and a slave clock signal different in phase are produced according to a basic clock signal. Serial data (Q) are input according to the produced master or slave clock signal, a protocol process is applied to the input serial data, and the serial data (W) that have been subjected to the protocol process are output according to the master or slave clock signal. A start delimiter detecting signal (S) is generated when a start delimiter (11) indicating the first frame is detected in the input serial data (Q). Phases are exchanged between the master and slave clock signals when there arises a shift on a bit boundary of the serial data at the point in time when the start delimiter detecting signal (S) is generated, and the serial data are output according to the master or slave clock signal having the phases exchanged each other. Thus, the serial data are transmitted without delay despite a shift arising on the bit boundary of the serial data.

Description: BACKGROUND OF THE INVENTION Field of the Invention This invention relates to a clock generating apparatus and a data transmitting/receiving apparatus comprising the same. The invention is particularly concerned with a clock generating apparatus, for generating a non-overlap 2-phase clock signal according to a basic clock signal, and a transmitting/receiving apparatus for transmitting and receiving data according to the 2-phase clock signal. Description of the Prior Art In a typical local area network such as an IEEE 802.5 token ring LAN, digital information is transmitted in the form of serial data. A data transmitting/receiving apparatus comprises means for generating a basic clock signal in synchronism with the serial data and the apparatus transmits and receives data on the basis of the basic clock signal. Documents which deal with the generation of the basic clock signal are JP-A-57-116459, JP-A-56-132043, and EP-A-0 153 107. When the serial data is encoded by the Manchester code, each data bit is encoded by two individual bits (called half bits or 0.5 bits in the following) which are received or transmitted in accordance with the basic clock signal. In this case, for transmitting and receiving the serial data, employed hitherto is a method wherein a non-overlap 2-phase clock signal is generated from the basic clock signal, a master clock signal and a slave clock signal are generated from the 2-phase clock signal, a serial data with the phase lagging 0.5 bits from the serial data inputted is further generated other than the inputted serial data, and each serial data is transmitted according to the master clock signal or the slave clock signal. Further, for transmitting the serial data, the serial data is transmitted in half-bits with data of a start delimiter constructed of an 8-bit long bit pattern placed ahead of a frame. Then, the serial data is received only at the time when each communication station detects the start delimiter in transmitted data. Whether or not the transmitted data indicates the start delimiter is detected from a configuration of the bit pattern. Thus, according to the method whereby the bit pattern (pattern of combinations of 2 half bits) is detected in the transmitted data of half-bits, there may be a case where a data is read with the combinations of half bits shifted by 0.5 bits according to how the data is inputted. In such case, a shift of 0.5 bits may arise on a bit boundary of the serial data. Now, therefore, a method for preventing a data error from resulting by correcting a phase of the serial data according to a master clock signal and a slave clock signal is employed when a shift occurs on the bit boundary of the serial data. That is, in case a shift arises on the bit boundary when transmitting a basic serial data according to the master clock signal, a serial data with the phase lagging 0.5 bits from the basic serial data is transmitted according to the slave clock signal, thereby preventing an error from arising on the data transmission. In the aforementioned prior art, since a serial data is selected for transmission according to the master clock signal and the slave clock signal, when the serial data with the the phase lagging 0.5 bits from a basic serial data is selected as data to be transmitted, a data transmission delays, and such delay in the data transmission becomes serious particularly in the system for which a high throughput is required for data transmission. SUMMARY OF THE INVENTION It is an object of the invention to provide an apparatus for generating master and slave clock signals which can be synchronised without delay. This object is solved by the apparatus set forth in claim 1. The subclaims are directed to preferred embodiments of the invention. A data receiving/transmitting apparatus comprising a clock generating apparatus according to the invention is set forth in claim 5. A first embodiment of the invention comprises a data transmitting/receiving apparatus having 2-phase clock signal generating means for generating 2-phase clock signals different in phase according to an incoming signal and a basic clock signal, master clock signal generating means for generating a master clock signal on a logical product of one signal of the 2-phase clock signals and the basic clock signal, slave clock signal generating means for generating a slave clock signal on a logical product of another signal of the 2-phase clock signals and the basic clock signal, period initializing signal generating means for generating a period initializing signal upon detection of a specific bit pattern of a serial data inputted through a data transmission line, logical means for generating, from a logical sum of the period initializing signal and one signal of the 2-phase clock signals, an incoming signal to the 2-phase clock signal generating means, data input means for inputting a serial data according to the master clock signal or the slave clock signal, protocol processing means for applying a protocol process to the serial data inputted by the data input means, and data output means for outputting the serial data processed by the protocol processing means in sequence to the data transmission line according to the master clock signal or the slave clock signal. A second embodiment comprises a data transmitting/receiving apparatus having 2-phase clock signal generating means for generating 2-phase clock signals different in phase according to an incoming signal and a basic clock signal, master clock signal generating means for generating a master clock signal on a logical product of one signal of the 2-phase clock signals and the basic clock signal, slave clock signal generating means for generating a slave clock signal on a logical product of another signal of the 2-phase clock signals and the basic clock signal, period turnover signal generating means for generating a period turnover signal upon detection of a specific bit pattern of serial data inputted through a data transmission line, logical means for generating, from an exclusive OR of the period turnover signal and one signal of the 2-phase clock signals, an incoming signal to the 2-phase clock signal generating means, data input means for inputting a serial data according to the master clock signal or the slave clock signal, protocol processing means for applying a protocol process to the serial data inputted by the data input means, and data output means for outputting the serial data processed by the protocol processing means in sequence to the data transmission line according to the master clock signal or the slave clock signal. A third embodiment comprises a local area network communication transmitting/receiving apparatus operating as a data transmitting/receiving apparatus of a communication station disposed in a data transmission line, having 2-phase clock signal generating means for 0 generating 2-phase clock signals different in phase according to an incoming signal and a basic clock signal, master clock signal generating means for generating a master clock signal on a logical product of one signal of the 2-phase clock signals and the basic clock signal, slave clock signal 5 generating means for generating a slave clock signal on a logical product of another signal of the 2-phase clock signals and the basic clock signal, period initializing signal generating means for generating a period initializing signal upon detection of a specific bit pattern of a serial data inputted through a data transmission line, logical means for generating, from a logical sum of the period initializing signal and one signal of the 2-phase clock signals, an incoming signal to the 2-phase clock signal generating means, data input means for inputting a serial data according to the master clock signal or the slave clock signal, protocol processing means for applying a protocol process to the serial data inputted by the data input means, and data output means for outputting the serial data processed by the protocol processing means in sequence to the data transmission line according to the master clock signal or the slave clock signal. Still further, a fouth embodiment comprises a local area network communication transmitting/ receiving apparatus operating as a data transmitting/receiving apparatus of a communication station disposed in a data transmission line, having 2-phase clock signal generating means for generating 2-phase clock signals different in phase according to an incoming signal and a basic clock signal, master clock signal generating means for generating a master clock signal on a logical product of one signal of the 2-phase clock signals and the basic clock signal, slave clock signal generating means for generating a slave clock signal on a logical product of another signal of the 2-phase clock signals and the basic clock signal, period turnover signal generating means for generating a period turnover signal upon detection of a specific bit pattern of a serial data inputted through a data transmission line, logical means for generating, from an exclusive OR of the period turnover signal and one signal of the 2-phase clock signals, an incoming signal to the 2-phase clock signal generating means, data input means for inputting a serial data according to the master clock signal or the slave clock signal, protocol processing means for applying a protocol process to the serial data inputted by the data input means, and data output means for outputting the serial data processed by the protocol processing means in sequence to the data transmission line according to the master clock signal or the slave clock signal. A fifth embodiment comprises a clock generating apparatus having 2-phase clock signal generating means for generating 2-phase clock signals different in phase according to an incoming signal and a basic clock signal, master clock signal generating means for generating a master clock signal on a logical product of one signal of the 2-phase clock signals and the basic clock signal, slave clock signal generating means for generating a slave clock signal on a logical product of another signal of the 2-phase clock signals and the basic clock signal, and logical means for generating, from a logical sum of a period initializing signal synchronized with the basic clock signal and one signal of the 2-phase clock signals, an incoming signal to the 2-phase clock signal generating means. A sixth embodiment comprises a clock generating apparatus having 2-phase clock signal generating means for generating 2-phase clock signals different in phase according to an incoming signal and a basic clock signal, master clock signal generating means for generating a master clock signal on a logical product of one signal of the 2-phase clock signals and the basic clock signal, slave clock signal generating means for generating a slave clock signal on a logical product of another signal of the 2-phase clock signals and the basic clock signal, and logical means for generating, from an exclusive OR of a period turnover signal synchronized with the basic clock signal and one signal of the 2-phase clock signals, an incoming signal to the 2-phase clock signal generating means. A seventh embodiment comprises a clock generating apparatus having 2-phase clock signal generating means for generating 2-phase clock signals different in phase according to an incoming signal and a basic clock signal, master clock signal generating means for generating a master clock signal on a logical product of one signal of the 2-phase clock signals and the basic clock signal, slave clock signal generating means for generating a slave clock signal on a logical product of another signal of the 2-phase clock signals and the basic clock signal, period initializing signal generating means for generating a period initializing signal synchronized with the basic clock signal upon detection of a specific bit pattern of a serial data inputted through a data transmission line, and logical means for generating, from a logical sum of the period initializing signal and one signal of the 2-phase clock signals, an incoming signal to the 2-phase clock signal generating means. Further, an eighth embodiment comprises a clock generating apparatus having 2-phase clock signal generating means for generating 2-phase clock signals different in phase according to an incoming signal and a basic clock signal, master clock signal generating means for generating a master clock signal on a logical product of one signal of the 2-phase clock signals and the basic clock signal, slave clock signal generating means for generating a slave clock signal on a logical product of another signal of the 2-phase clock signals and the basic clock signal, period turnover signal generating means for generating a period turnover signal synchronized with the basic clock signal upon detection of a specific bit pattern of a serial data inputted through a data transmission line, and logical means for generating, from an exclusive OR of one signal of the 2-phase clock signals and the period turnover signal, an incoming signal to the 2-phase clock signal generating means. Another embodiment of the invention involves employing a data transmitting/receiving method wherein 2-phase clock signals different in phase are generated according to a basic clock signal, a master clock signal is produced subject to a logical product of one signal of the 2-phase clock signals and the basic clock signal, a slave clock signal is produced subject to a logical product of another signal of the 2-phase clock signals and the basic clock signal, a serial data is inputted according to the master clock signal or the slave clock signal, and when a shift occurs on a bit boundary of the serial data for outputting according to the master clock signal or the slave clock signal after a protocol process has been applied to the inputted serial data, phases of the master clock signal and the slave clock signal are exchanged, then the serial data is transmitted and received according to a specified clock signal of the master clock signal and the slave clock signal having the phases exchanged. When a shift occurs on a bit boundary of the serial data for transmitting the serial data according to the master clock signal or the slave clock signal, phases of the master clock signal and the slave clock signal are exchanged, and the serial data is transmitted according to a specified clock signal of the master clock signal and the slave clock signal having the phases exchanged, therefore the serial data can be transmitted without delay, and thus a throughput in the data transmission can be kept from deteriorating. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a clock generating apparatus; FIG. 2 is a time chart for illustrating an operation when a bit boundary is not shifted from using the apparatus shown in FIG. 1; FIG. 3 is a time chart for illustrating an operation when the bit boundary is shifted from using the apparatus shown in FIG. 1; FIG. 4 is a block diagram showing another embodiment of the clock generating apparatus; FIG. 5 is a time chart for illustrating an operation of the apparatus shown in FIG. 4; FIG. 6 is a block diagram representing one embodiment of a data transmitting/receiving apparatus; FIG. 7 is a time chart for illustrating an operation of the apparatus shown in FIG. 6; FIG. 8 is a block diagram showing another embodiment of the data transmitting/receiving apparatus; FIG. 9 is a block diagram showing an operative example when the data transmitting/receiving apparatus is applied to a token ring LAN system. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS One preferred embodiment of the invention will now be described with reference to the accompanying drawings. In FIG. 1, a clock generating apparatus comprises frequency dividing flip-flops 1, 2, an inverter 3, AND gates 4, 5 and an OR gate 6, a period initializing signal from a period initializing signal generating apparatus for generating the period initializing signal is inputted to one input terminal of the OR gate 6, and a basic clock signal is inputted to the flip-flops 1, 2 and the AND gates 4, 5. The period initializing signal generating apparatus loads in a serial data transmitted in half-bits, and when detecting that a data relating to a start delimiter indicating a start of data transmission (or a data by an 8-bit long bit pattern) is included in the serial data, it generates the period initializing signal synchronized with the basic clock signal. The flip-flops 1, 2 are constructed of an edge trigger type D-flip-flop answering to a pulse rise, and when the basic clock signal shown in FIG. 2 is inputted to a clock terminal of the flip-flop 1, a signal shown in FIG. 2 (D) is generated from a Q terminal of the flip-flop 1. Then, when the basic clock signal is inputted to a clock terminal of the flip-flop 2 through the inverter 3, a signal shown in FIG. 2 (E) is generated from a Q terminal of the flip-flop 2, and a turnover signal is generated from the Q terminal. That is, the flip-flops 1, 2 and the inverter 3 are constructed as 2-phase clock signal generating means. Then, an output of the Q terminal of the flip-flop 2 is fed back to another input terminal of the OR gate 6 and also inputted to the AND gate 5, and an output of the Q terminal is inputted to the AND gate 4. When an outgoing signal of the flip-flop 2 is inputted to the AND gates 4, 5 each, the master clock signal is generated from the AND gate 4 as a clock signal different in phase according to the basic clock signal as shown in FIG. 2 (G), (H), and the slave clock signal is generated from the AND gate 5. That is, the AND gate 4 is constructed as master clock signal generating means, and the AND gate 5 is constructed as slave clock signal generating means. On the other hand, an outgoing signal of the flip-flop 2 and a period initializing signal are inputted to the OR gate 6, and the same signal as an outgoing signal of the Q terminal of the flip-flop 2 is generated normally from the OR gate 6, as shown in FIG. 2 (F). Then, a period is initialized when the period initializing signal synchronized with the basic clock signal is inputted to the OR gate 6. If there arises no shift on a bit boundary of the serial data, then a phase of the period initializing signal coincides with a pulse generated from the Q terminal of the flip-flop 2, and a pulse same in phase as the pulse generated from the Q terminal of the flip-flop 2 is outputted in sequence from the OR gate 6. Thus, phases are not exchanged between the master clock signal and the slave clock signal in this case, and the master clock signal and the slave clock signal are generated alternately in the existing timing. Next, as shown in FIG. 3, when the period initializing signal is generated from a shift arising on a bit boundary of the serial data, the period initializing signal is inputted to the OR gate 6 in a phase different from the pulse outputted from the Q terminal of the flip-flop 2. Thus, an output level of the OR gate 6 is kept high for the term of 0.5 bits, and an output level of the flip-flop 1 is also kept high for the term of 0.5 bits without being inverted to low level. Thus, a level of the Q terminal is kept high despite coming to a low level or low despite coming to a high level, the period of high level and low level being inverted consequently. Now, therefore, the period is initialized between the master clock signal and the slave clock signal which are outgoing signals of the AND gates 4, 5. The initialization is effected only after one period from the period initializing signal being inputted to the basic clock signal being inputted. Phases are exchanged between the master clock signal and the slave clock signal by the initialization effected as above. Then the serial data will be transmitted according to the master clock signal or the slave clock signal having the phases exchanged. Accordingly, irrespective of a shift arising on a bit boundary of the serial data, the serial data can be transmitted without delay simply by exchanging phases of the master clock signal and the slave clock signal. Next, as shown in FIG. 4, an Ex-OR gate 7 is provided as logical means instead of the OR gate 6 of FIG. 1, thus when a specific bit pattern of the serial data inputted through a data transmission line, or, for example, a bit pattern for indicating a command to execute forcedly a phase exchange between the master clock signal and the slave clock signal, or a bit pattern for indicating a shift arising on the bit boundary is detected, simply from inputting a period turnover signal from period turnover signal generating means for generating the period turnover signal to one input terminal of the Ex-OR gate 7, the phases of the master clock signal and the slave clock signal can be exchanged forcedly according to the period turnover signal. In this embodiment, as shown in FIG. 5, while the master clock signal and the slave clock signal different in phase each other are outputted from the AND gates 4, 5 respectively according to the basic clock signal, if the period turnover signal is inputted to the gate 7, an output level of the gate 7 is kept high for the term of 0.5 bits without being inverted to a low level. In this case, an output level of the flip-flop 1 is kept also high longer for the term of 0.5 bits. Thus, the Q terminal of the flip-flop 2 is kept low in level for the term of 0.5 bits, and phases are exchanged between the master clock signal and the slave clock signal. That is, the period is inverted forcedly by the period turnover signal between the master clock signal and the slave clock signal. In this case, when the period turnover signal is inputted, the period of the master clock signal and the slave clock signal is inverted necessarily regardless of a logical value of the Q terminal of the flip-flop 2. Thus, when a shift occurs on a bit boundary of the serial data, the period turnover signal is inputted to the gate 7 to invert periods of both the block signals mutually, and from transmitting the serial data according to the master clock signal or the slave clock signal having the periods inverted, the serial data can be transmitted without delay, even if there arises a shift on the bit boundary of the serial data. According to this embodiment, since the periods of both clock signals can be inverted forcedly from inputting the period turnover signal, a circuit for controlling a timing whereat the period turnover signal is generated may be simplified as compared with the embodiment given in FIG. 1. That is, when the period turnover signal is generated 0.5 bits shifted from the timing shown in FIG. 5, the periods are turned over in response to a rise of the slave clock signal. Next, a data transmitting/receiving apparatus for which the clock generating apparatus is employed is shown in FIG. 6. A data transmitting/receiving apparatus 10 constructs a repeating installation for realizing IEEE802·5 token ring LAN, comprising a start delimiter detecting circuit 11, a clock generating circuit 12, a receiving circuit 13, a protocol processing circuit 14, and a transmitting circuit 18. Then, a serial data through a transmission line 15 and a basic clock signal through a transmission line 16 are inputted to the data transmitting/receiving apparatus 10, and a transmitting serial data is sent therefrom through a transmission line 17. A received serial data Q propagating on the transmission line 15 is modulated according to a system called differential Manchester code. A data frame according to the code comprises a start delimiter SD, an access control AC, a destination address SA, a source address DA, information I, a frame check sequence FCS, an end delimiter ED and so forth, and the start delimiter SD which is a data indicating the first of token and frame comprises an 8-bit long bit pattern represented as differential Manchester code: JK0JK000:. The pattern is encoded as a 17 half-bit long bit pattern :00011011100101010: or 11100100011010101:. The pattern has the other bits than the first 0 or 1 construct patterns J, K, 0, 1 by 2 half bits. Then, when the start delimiter of the serial data is inputted to the start delimiter detecting circuit 11, the detecting circuit 11 is constructed, as shown in FIG. 7, as period initializing signal generating means for generating a 1 half-bit time start delimiter detecting signal S at the point in time when the 17th half-bit of the start delimiter data is detected. The clock generating circuit 12 comprises the flip-flops 1, 2, the inverter 3, the AND gates 4, 5, and the OR gate 6 shown in FIG. 1, and when a start delimiter detecting signal S is inputted to the 2-phase clock generating circuit 12, the master clock signal and the slave clock signal are initialized. In case then a shift arises on a bit boundary between the transmitted data and the received serial data Q, phases are exchanged by initialization. Then the serial data Q is inputted to the receiving circuit 13 according to the master clock signal or the slave clock signal having the phases exchanged each other. The serial data Q inputted to the receiving circuit 13 is transferred to the protocol processing circuit 14 as a demodulated serial data V. Then, a protocol process based on the communication convention of IEEE802·5 token ring LAN is applied to the data, which is outputted to the transmission line 17 through the transmitting circuit 18 as a transmitted serial data W. According to this embodiment, when a bit boundary of the transmitted data is shifted, phases are exchanged between the master clock signal and the slave clock signal, and then the serial data is transmitted according to the master clock signal or the slave clock signal having the phases exchanged, therefore the serial data can be transmitted without delay. In this case, a 1 half-bit long truncated data is generated as the demodulated serial data V at the time of phase exchange between the master clock signal and the slave clock signal, however, the protocol processing circuit 14 interprets only the demodulated serial data V after initialization, therefore the data transmission will be free from trouble. Then, as shown in FIG. 8, an AND gate 19 is provided, a bit boundary shift detecting circuit 20 for detecting a shift of the bit boundary is provided, and an outgoing signal of the start delimiter detecting circuit 11 and an outgoing signal of the bit boundary shift detecting circuit 20 are inputted to the AND gate 19 in construction, then the start delimiter detecting signal S can be transferred to the clock generating circuit 12 only at the time when the start delimiter is detected and a shift arises on the bit boundary. In this case, phases of both the clock signals can be exchanged forcedly according to the start delimiter detecting signal S inputted to the clock generating circuit 12. Meanwhile, the clock generating apparatus may comprise the start delimiter detecting circuit 11 and the clock generating circuit 12, or the clock generating circuit 12 and the bit boundary shift detecting circuit 20. Next, in case, as shown in FIG. 9, where a token ring 30 is constructed of stations 32, 33, 34, the data transmitting/ receiving apparatus 10 shown in FIG. 6 and a serial interface 31 are provided as a communication system of each station, then the data transmitting/receiving apparatus 10 may be applied to the token ring LAN system. In this embodiment, where a shift arises on a bit boundary of a received serial data when exchanging the serial data between each station, phases of the master clock signal and the slave clock signal are initialized by the data transmitting/ receiving apparatus 10 of each station, and the serial data is transmitted according to the master clock signal or the slave clock signal having the phases initialized as above, then the serial data can be transmitted late only by the time necessary for internal processing at each station. That is, when transmitting the received serial data as a serial data to transmit, the data transmission is delayed by the time least necessary for the internal processing, but the data can be transmitted without delay due to a shift arising on the bit boundary. Thus, according to this embodiment, since a delay in transmitting the serial data can be suppressed at each station, a deterioration of throuput can be prevented from the communication system point of view as a whole. For example, in the communication system comprising 200 stations, when exchanging data at 4Mbps in transmission rate, if a phase lags 0.5 bits at each station as in the case of prior art system, then the data delays about 12.8 µS as the whole system, and thus the data for 50 bits will come to a standstill. Now, in the embodiment, while the.data transmission delays by the time (several nS) least necessary for internal processing at each station, such time is not so serious for the system as a whole, and a trouble will not result for the data transmission. As described above, according to this invention, even in case a bit boundary of the transmitted data is shifted, since phases are exchanged between the master clock signal and the slave signal, and the data is transmitted according to the master clock signal or the slave clock signal having the phases exchanged, the data can be transmitted without delay, and a deterioration of throughput at the time of data transmission can be prevented.

Claims: An apparatus for generating master and slave clock signals having different phases, comprising: a two-phase clock signal generating means (1, 2) for receiving a basic clock signal and generating therefrom two two-phase clock signals different in phase, master clock signal generating means (4) for generating a master clock signal from a logical product of one of the two-phase clock signals and the basic clock signal, slave clock signal generating means (5) for generating a slave clock signal from a logical product of the other one of the two-phase clock signals and the basic clock signal, and logical means (6, 7) supplied with a two-phase clock signal and an external synchronising signal, for exchanging the phase of the master clock signal with that of the slave clock signal depending on a logic relationship between said supplied two-phase clock signal and said external synchronising signal. An apparatus according to claim 1, wherein said external synchronising signal is an initialising signal and said logical means comprises means (6) for forming the logical sum of said initialising signal with said supplied two-phase clock signal. An apparatus according to claim 1, wherein the external synchronising signal is a phase turnover signal and the logical means comprises means (7) for forming an exclusive OR of said phase turnover signal with said supplied two-phase clock signal. An apparatus according to any of claims 1 to 3, comprising means (11) for receiving serial data from a transmission line (15) and for generating said external synchronising signal in synchronism with the basic clock signal upon detection of a specific bit pattern in said serial data. A data receiving/transmitting apparatus comprising a clock generating apparatus according to any of claims 1 to 4 and means (13, 18) for receiving or transmitting pairs of data bits in the form of serial data from or to a data transmission line (15, 17) in accordance with the master and slave clock signals.

Inventors: INADA SHUNJI, KAMADA SEIJI, KATAYAMA TOSHIYUKI, SUGIMOTO NORIHIKO, INADA, SHUNJI, KAMADA, SEIJI, KATAYAMA, TOSHIYUKI, SUGIMOTO, NORIHIKO
Applicants: HITACHI ENG CO LTD, HITACHI LTD, HITACHI ENGINEERING CO., LTD., HITACHI, LTD.
Application year: 1991
Main classification: H04L7
IPC codes: H04L7, H03L7