Operational amplifier

Abstract: An operational amplifier (10) is provided which includes a differential input stage (18) for receiving differential signals. A differential loop (30, 64), (86) amplifies said differential signals. The amplified differential signals are output on a pair differential output terminals (80, 84). A common mode loop (54), (30, 64) maintains the mean voltage of the amplified differential signals at a preselected value.

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates in general to analog circuitry and more particularly to an operational amplifier and method of amplification. BACKGROUND OF THE INVENTION Oversampling conversion techniques allow for a reduction in the amount of analog circuitry required in analog-to-digital and digital-to-analog converters by shifting most of the digital processing functions into the digital domain. Despite the use of oversampling conversion techniques, however, the need for analog circuitry is no! completely eliminated. Those analog elements still necessary for the implementation of oversampling conversion, such as operational amplifiers, must meet stringent performance requirements, especially in light of the high sampling frequency required. In addition to meeting the stringent performance requirements necessary for oversampling conversion, these analog elements must be compatible with the technology used to fabricate the associated digital integrated circuits such that both the analog and digital functions can be integrated into a single high-density chip. For example, if complementary metal oxide semiconductor (CMOS) digital circuitry is being used, the associated analog circuit elements must be fabricated using CMOS technology or CMOS compatible technology. Complementary metal oxide semiconductor (CMOS) over-sampled converters typically include continuous parts, such as RC anti-aliasing and smoothing filters, directly connected to switched capacitors being sampled at high-frequency, typically in the range of 1-10 MHz. Currently available CMOS converters implement CMOS operational amplifiers for switched capacitor filters which are generally based on single-stage transconductance amplifier structures. While single-stage transconductance operational amplifier structures have speed characteristics suitable for oversampled converters, these structures present a very high output impedance such that they are not well adapted to driving resistive loads. Further, the output stages of currently available CMOS amplifiers typically consist of several transistors connected in series, a structure which limits the available output voltage swing. A consequence of reduced output voltage swing is decreased output linearity and signal-to-noise ratio performance. Finally, available amplifiers generally using continuous RC filters are not suited for use with highfrequency sampled switched capacitor circuits. IEE JOURNAL OF SOLID STATE CIRCUITS, vol. 24, n°3, June 1989, NEW YORK, US pages 690-697, M. Ferro et al "A Floating CMOS Band-gap Voltage Reference for Differential Applications" discloses an operational amplifier having differential inputs and outputs. This amplifier requires two common mode control loops. EP-A-0 325 299 discloses an amplifier with differential inputs and single ended outputs. EP-A-3 725 323 discloses an amplifier having differential inputs and outputs with a very complex structure. Thus, a need has arisen for a CMOS operational amplifier adapted to the performance required for oversampled converters. Specifically, the need has arisen for a high-speed operational amplifier having high output linearity, improved signal to noise ration performance at the output, and having a reduced output impedance capable of driving resistive loads. SUMMARY OF THE INVENTION According to the invention, an improved operational amplifier as defined in the appended independent claim 1 is provided. According to other aspects of the present invention, the differential path comprises a first gain stage coupled to the input stage, a second gain stage coupled the first gain stage and circuitry coupled to the output terminals and the second gain stage for dynamically controlling the output bias current from the second gain stage. According to further aspects of the invention, the common mode loop includes the first gain stage, the second gain stage and a common mode input stage coupling the output terminals and the first gain stage. The present invention has significant advantages over prior art of CMOS operational amplifiers. The present invention has the speed necessary for use in oversampled analog to digital and digital to analog converters. Further, the reduced output impedance allows the operational amplifier of the present invention to drive both resistive and capacitive loads. Additionally, the operational amplifier of the present invention avoids the slew rate mode during switching transients. Finally, the present invention provides both a switchable power down mode and an unlockable common mode control loop at power up. BRIEF DESCRIPTION OF THE DRAWINGS Other aspects of the invention and their advantages will be discerned when one refers to the following detailed description as taken in conjunction with the drawings, in which: FIGURE 1 is a functional block diagram of an operational amplifier according to the present invention; FIGURE 2 is an electrical schematic diagram of the differential path portion of the operational amplifier according to the present invention; FIGURE 3 is an electrical schematic diagram of the common mode path portion of the operational amplifier according to the present invention; and FIGURE 4 is an electrical schematic diagram of the operational amplifier according to the present invention. DETAILED DESCRIPTION OF THE INVENTION FIGURE 1 is a block diagram of a high performance operational amplifier 10 according to the present invention. Operational amplifier 10 includes a noninverting input 12 and an inverting input 14. Noninverting input 12 is coupled to the noninverting input 16 of first (input) stage 18 and the first plate 20 of capacitor 22. Inverting input 14 is coupled to the inverting input 24 of first (input) stage circuitry 18 and the first plate 26 of capacitor 28. The second stage of operational amplifier 10 (the first amplifying stage) is a cascode amplifier and is shown generally by dotted lines at 30. Second stage 30 includes an upper section 32 and a lower section 34. The noninverting input 36 of upper section 32 is coupled to the inverting output 38 of input stage 18. Noninverting input 36 is also coupled to second plate 40 of capacitor 28. The inverting input 42 of section 32 is coupled to the inverting input 44 of lower section 34. The noninverting input 46 of lower section 34 is coupled to the noninverting output of input stage 18 and second plate 50 of capacitor 22. Inverting input 42 of upper stage 32 and inverting input 44 of lower stage 34 are each connected to output 52 of third stage 54. The noninverting input of third stage 54 is coupled to a reference voltage V cmref at node 58. The noninverting input of third stage 54 is coupled to feedback node 62. Third stage 54 operates as the input stage of a common mode loop which sets the operating point of amplifier 10 by maintaining the mean output voltage of amplifier 10 at a preselected common mode voltage. The fourth stage (the second amplifying stage) is shown by dotted lines generally at 64 and includes an upper section 66 and a lower section 68. The output 70 of upper section 32 of second stage 30 is coupled to inverting input 72 of upper section 66 of fourth stage 64. The output 74 of lower section 34 of second stage 30 is coupled to inverting input 76 of lower section 68 of fourth section 64. The output 78 of upper section 66 is coupled to noninverting output 80 of amplifier 10 while the output 82 of lower section 68 is coupled to inverting output 84 of amplifier 10. Output current is dynamically controlled with a loop including fifth stage 86 (the auxiliary stage). Output 70 of upper section 32 of second stage 30 is coupled to noninverting input 88 of fifth stage 86. Output 74 of lower section 34 of second stage 30 is coupled to inverting input 94 of fifth stage 86. Output signals appearing on output terminals 80 and 84 are also fed back to a fifth stage 86. Noninverting output terminal 80 is coupled to noninverting input 88 of fifth stage 86 through a capacitor 90 and resistor 92. Similarly, inverting output terminal 84 is coupled to inverting input 94 of fifth stage 86 through a capacitor 96 and a resistor 98. Fifth stage 86 includes a noninverting output 100 and an inverting output 102. Noninverting output 100 is coupled to an input 104 of upper stage 66 of fourth stage 64. A capacitor 106 couples noninverting output 100 to noninverting input 88 of fifth stage 86. Noninverting output 102 is coupled to an input 108 of lower section 68 of fourth stage 64. A feedback capacitor 110 coupled inverting output 102 of fifth stage 86 to inverting input 94. In the preferred embodiment, noninverting output 80 of amplifier 10 is coupled to node 62 and the input 60 of third stage 54 by a parallel combination of capacitor 112 and resistor 114. Similarly, noninverting output terminal 84 is coupled through node 62 and input 60 of third stage 54 by the parallel combination of capacitor 116 and resistor 118. In the preferred embodiment, input stage 18 comprises a differential amplifier at inputs 16 and 24 of input stage 18 such that the receipt of unbalanced differential signals result in similarly unbalanced output signals appearing on inverting output 38 and noninverting output 48. The amplified differential signals output from each output of input stage 18 are then fed to the respective noninverting inputs 36 and 46 of amplification stages 32 and 34. In the preferredembodiment, amplification stages 32 and 34 comprise cascode amplification stages whose outputs are driven from first and second voltage rails. The respective differential signals are then further amplified through second stage amplification sections 66 and 68. In the preferred embodiment, amplification section 66 and 68 comprise common source amplifiers whose outputs are also driven from the first and second voltage rails. Amplifier section 66 and 68 invert the polarities of the differential signals, which had been previously inverted by the differential amplifier of input stage 18, such that the outputs at 80 and 84 directly correspond in polarity to the inputs at input terminals 12 and 14. The double amplification stage provides increased output drive allowing a greater voltage swing across the load coupled between output terminals 80 and 84. Auxiliary section 86 controls the bias currents at the outputs of second stage amplification sections 66 and 68. In the preferred embodiment, auxiliary stage 86 includes current mirrors coupled at inputs 104 and 108 of respective amplification sections 66 and 68. Functionally, the current mirrors mirror the current through the common source amplifier output transistors. Auxiliary section 86 also includes a differential amplifier which drives the current mirrors received from the outputs 70 and 74 of the first amplification sections 32 and 34. When the outputs 70 and 74 of amplification sections are unbalanced the signal provided to inputs 88 and 94 of the differential amplifier of auxiliary stage 86 causes unbalanced drive to the current mirrors. The resulting unbalanced current through the current mirrors is in turn reflected in an unbalanced current output from common source amplification section 66 and 68. The resulting modulation of the output current allows the circuit to adapt to the current required by the output load, thereby increasing the threshold beyond which the amplifier goes into the slew rate mode. The operating point of amplifier 10 is set by maintaining the mean voltage value between output terminals 80 and 84 at the common mode voltage. In the preferred embodiment, the mean of the output voltages is taken at node 62 which coupled to noninverting output terminal 80 through an impedance comprising capacitor 112 and resistor 114 and to inverting output 84 through the impedance comprising capacitor 116 and resistor 118. The mean voltage appearing at node 62 is then fed back to the inverting input of common mode stage 54, the noninverting input 56 of which is tied to a reference voltage V cmref . In the preferred embodiment, common mode stage 54 comprises a differential amplifier with inputs 56 and 60 being its respective differential inputs. The reference voltage controls the balancing of the differential amplifier in essence comparing the reference voltage with the mean output voltage. The output of common mode section 54 then provides feedback at the inverting inputs 42 and 44 of first stage amplifying sections 32 and 34 such that the cascode amplifiers making up stages 32 and 34 are biased to set the common mode voltage of outputs 80 and 84. Referring next to FIGURE 2, a schematic diagram depicts the differential path of operational amplifier 10. The differential path includes first stage (the input stage) 18, second (the first gain stage) 30, fourth stage (the second gain stage) 64 and stage five 86 which dynamically controls the bias current of fourth stage 64. First stage 18 is composed of a pair differential p channel transistors 120 and 122, and a current source made up of transistors 124 and 126. Noninverting input terminal 12 of amplifier 10 is coupled to the gate of transistor 120, which is noninverting input 16 for input stage 18. Inverting terminal 14 is similarly tied to the gate of transistor 122 which is the noninverting input 24 of input stage 18. One source/drain of transistor 120 is coupled to a first source/drain of current p channel source transistor 124. The second source/drain of p channel transistor 124 is coupled to first voltage rail 128 while the gate of transistor 124 is coupled to a bias voltage V bias1 . Similarly, a first one of the source/drain of transistor 122 is coupled to the first source/drain of transistor 126. The second source/drain region of transistor 126 is coupled to voltage rail 128 while the gate of transistor 126 is coupled to bias voltage V bias1 . The first source/drains of differential transistors 120 and 122, and current source transistors 124 and 126 are tied together at node 129. The second stage 30 (the first gain stage) includes a cascode amplifier made up of n channel transistors 130, 132, 134 and 136, and p channel transistors 138 and 140. The current flowing out of p channel transistor 120 of the first stage 16 modulates the current flowing through the cascode stage consisting of n channel transistors 130 and 134 and the p channel cascode load transistor 138. The second source/drain of p channel transistor 120 is coupled to respective first source/drains of n channel transistors 130 and 134 at node 133. The second source/drain of transistor 130 is coupled to the first source/drain of p channel transistor 138. The gate of transistor 130 is tied to bias voltage V bias2 . The second source/drain of n channel transistor 134 is tied to the second voltage rail 131. The gate of transistor 134 is tied to bias voltage V bias3 . The second source/drain of p channel transistor 138 is coupled to first voltage rail 128 while the gate of transistor 138 is coupled to bias voltage V bias4 . The current through p channel transistor 122 modulates the current flowing through the cascode stage including n channel transistors 132 and 136 and p channel load transistor 140. The second source/drain of transistor 122 is coupled to the first source/drains of n channel transistors 132 and 136, respectively at node 135. The second source/drain of transistor 132 is coupled to the first source/drain of transistor 140 while the gate of transistor 132 is coupled to bias voltage V bias2 . The second source/drain of p channel transistor 136 is tied to the second voltage rail 131 while the gate of transistor 136 is coupled to bias voltage V bias3 . Finally, the second source/drain of p channel transistor 140 is tied to first voltage rail 128 and the gate of transistor 140 coupled to bias voltage V bias4 . It is important to note that the structure used for the circuitry of second stage 30 allows for the selection of large sized transistors 134 and 136 which reduces their contributions to noise and offset without reducing the performance of the amplifier. The upper section 66 of fourth stage 64 (the second gain stage) is composed of p channel transistor 144 and n channel transistor 146. The first source/drain regions of transistors 144 and 146 are tied together and to noninverting output 80. The second source/drain of p channel transistor 144 is coupled to first voltage rail 128. The gate of transistor 144 is coupled to the second source/drain of transistor 130 ,forming part second stage 30, at node 70. The second source/drain of n channel 146 is coupled to second voltage rail 131. The lower section 68 of fourth stage 64 includes p channel transistor 148 and n channel transistor 150. The respective first source/drains of transistors 148 and 150 are coupled together and coupled to inverting output 84 of amplifier 10. The second source/drain of transistor 148 is coupled to first voltage rail 128 while the gate of transistor 148 is coupled to the second source/drain of transistor 132, forming part of second stage 30, at node 72. The second source/drain of transistor 150 is coupled to second voltage rail 131. The biasing current of the fourth stage 64 is controlled by fifth (auxiliary) stage 86 which allows dynamic adaptation of the current to the differential signal output on terminals 80 and 84. A first current mirror is formed by coupling the gate of transistor 146 to the gate and first source/drain of n channel transistor 152. The second source/drain of transistor 152 is coupled to the second voltage rail 131. A second current mirror is formed by coupling the gate of n channel transistor 150 to the gate and first source/drain of n channel transistor 154. The second source/drain of n channel transistor is coupled to second voltage rail 131. The current biasing for the first and second current mirrors is provided by p channel transistors 156 and 158. P channel transistors 156 and 158 are further coupled to p channel differential pair transistors 160 and 162, which along with transistors 152 and 154, complete the auxiliary differential amplifier. The first source/drain of n channel transistor 152 is coupled to a first source/drain of transistor 162. The second source/drain of transistor 162 is coupled to the first source/drains of p channel transistors 156 and 158. The second source/drains of p channel transistors 156 and 158 are coupled to first voltage rail 128 while the gates of transistors 156 and 158 are tied to bias voltage V bias1 . In a similar fashion, the first source/drain of n channel transistor 154 is coupled to a first source/drain of p channel transistor 160. The second source/drain of p channel transistor 160 is also coupled both to the first source/drains of p channel transistors 156 and 158. A pair of voltage followers are forced by transistors 164 and 166, 168 and 170. The first source/drains of transistors 164 and 166 are coupled together and to the gate of p channel transistor 160. The second source/drain of n channel transistor 164 is coupled to the first voltage rail 128 while the second source/drain of transistor 166 is tied to second voltage rail 131. The gate of transistor 164 is coupled to node 70 and the gate of n channel transistor 166 is tied to bias voltage V bias3 . Similarly, the first source/drains of n channel transistors 168 and 170 are coupled together and to the gate of p channel transistor 162. The second source/drain of transistor 168 is tied to first voltage rail 128 while the second source/drain of transistor 170 is tied to second voltage rail 131. The gate of transistor 168 is tied to node 72 while the gate of transistor 170 is tied to bias voltage V bias3 . Noninverting output terminal 80 is coupled to node 70 through capacitor 90 and resistor 92. Inverting output 84 is coupled to node 72 through capacitor 96 and resistor 98. When no differential signal appears between the gates of transistors 160 and 162, the currents flowing through transistors 152 and 154 are equal. Since the currents flowing through transistors 146 and 150 are respective images of the currents flowing in transistors 152 and 154, the biasing currents at the output terminals 80 and 84 are equal. When a differential signal is applied between the gates of transistors 160 and 162, however, a voltage difference is created at nodes 70 and 72 of second stage 30. The voltage difference appearing at nodes 70 and 72 drive the gates of differential transistors 160 and 162 through the voltage followers formed by transistors 164 and 166 and 168 and 170, respectively. Transistors 160 and 162 drive transistor 152 and 154 differentially (unbalanced) such that the output currents through transistors 146 and 150 are unequal. This modulation of output current provides for the adaptation of the currents at output terminals 80 and 84 to the associated loads. This increases the threshold beyond which the amplifier goes into the slew rate mode and consequently reduces the non-linearities resulting due to the slew rate phenomenon during transients. Referring next to FIGURE 3, the common mode path for operational amplifier 10 is depicted. For the sake of brevity and clarity, interconnections previously described in conjunction with the differential path shown in FIGURE 2 will not be repeated here. The input stage for the common mode path includes a current source consisting of n channel transistors 172 and 174, a differential pair formed by n channel transistors 176 and 178, and loads consisting of p channel transistors 180 and 182. The first source/drains of transistors 172 and 174 are tied to second voltage rail 131 while the gates of transistors 172 and 174 are coupled to bias voltage V bias3 . The second source/drain of transistor 172 is coupled to a first source/drain of transistor 176 while the second source/drain of transistor 174 is tied to a first source/drain of transistor 178. The gate of transistor 176 is tied to a reference common mode voltage V cmref . The gate of transistor 178 is coupled to a signal V cmin , which is equal to the mean value of the two output voltages appearing at output terminals 80 and 84. This mean value can be generated either in a time continuous fashion using resistors 114 and 118, as depicted in FIGURE 1, or in a sampled way by replacing resistors 114 and 118 with switched capacitors. The second source/drain of transistor 176 is coupled to the gate and first source/drain of transistor 180 at node 177. The second source/drain of transistor 180 is in turn tied to first voltage rail 128. The second source/drain of transistor 178 is coupled at node 179 to the gate and first source/drain of p channel transistor 182, the second source/drain of which is tied to voltage rail 128. An additional pair of p channel current source transistors 186 and 188 are provided. P channel transistor 186 has a first source/drain tied to first voltage rail 128 and a second source/drain coupled to second source/drain of n channel transistor 176. P channel transistor 188 has a first source/drain tied to first voltage rail 128 and a second source/drain coupled to the second source/drain of n channel transistor 178. The gates of transistors 186 and 188 are each tied to bias voltage V bias1 . As previously discussed, the common mode path sets the common mode voltage and thereby the operating point of operational amplifier 10. The structure of the common mode path is also designed to avoid any locking state and ensure the proper biasing at start-up of the circuit independent of the initial conditions. FIGURE 4 is a schematic diagram of the complete circuitry of operational amplifier 10, including the compensation loops, as well as the differential and common mode paths depicted in FIGURES 2 and 3. Overall loop stability is achieved by compensation networks, one of which is the main network used for the compensation of both the differential and common mode paths. The main compensation network uses the pole-splitting technique and includes the RC networks formed by capacitor 90 and resistor 92, and capacitor 96 and resistor 98, respectively. The main pole location depends on the output conductance of transistors 138 and 140, on the values of capacitors 90 and 96, and on the gain of the output stages formed transistors 144, 146, 148 and 150. Since all the elements required to set the main pole location are shared by both the differential and common mode paths, the same compensation network ensures the stability of the two loops. Since, in essence, the only difference between the differential path and common mode loop is their input stages, an adjustment in the gain of the input stage for the common mode loop is made so that the frequency characteristics of the differential and common mode loops are similar and such that the same values for the discrete elements of the compensation network will compensate both loops. This adjustment is done by selecting the size of transistors 186 and 188 which sets the transconductance of the input differential pair transistors 176 and 178 of the common mode amplifier. Feed forward type secondary compensation is also provided. Capacitors 22 and 28 allow compensation of the pole due to the parasitic capacitance on the cascode nodes 133 and 135 when the transconductance ratio of transistors 120 and 130 and 122 and 132 are properly selected. Capacitors 106 and 110 are used as feed-forward elements for the fifth stage 54. The power-down state is set by opening all the paths allowing current flow between supply rails 128 and 130. This is achieved by turning off most of the active devices and setting values of the internal nodes to a known voltage. This function is implemented using p channel transistors 190, 192, 194 and 196, and n channel transistors 198 and 200. The gates of p channel transistors 190, 192, 194, and 196 are each tied to a signal DOWNF. First ones of the source/drains of p channel transistors 190, 192, 194, 196 are each tied to first voltage rail 128. The second source/drain of transistor 190 is coupled to node 70 while the second source/drain of transistor 192 is connected to node 72. In a similar fashion, the second source/drain of p channel transistor 194 is tied to node 177 while the second source/drain of transistor 196 is tied to node 179. The gates of n channel transistors 198 and 200 are each tied to signal DOWN. First ones of the source/drains of transistors 198 and 200 are coupled to second voltage rail 131. The second one of the source/drains of transistor 198 is coupled to the first source/drain of p channel transistor 160 while the second source/drain of n channel transistor 200 is coupled to the first source/drain of transistor 162. During power down, bias voltage V bias1 is set to the high supply voltage and bias voltage V bias3 to the low voltage supply. This turns off p channel current source transistors 124, 126, 186, and 188 and n channel current source transistors 134, 136, 172, 174, 166 and 170. The signal DOWNF is set to the low supply voltage and switches on p channel transistors 190, 192, 194 and 196 thereby forcing nodes 70, 72, 177 and 179 to the high voltage supply and turning off p channel output devices 148 and 144. At the same time, the signal DOWN is set to the high supply voltage and switches on transistors 198 and 200 and turns off output current source transistors 146 and 150. In the preferred embodiment, the voltages supplied to the rails 128 and 130 are selected to be on the order of +5 volts and -0 volts, respectively for compatibility with the associated digital circuitry. The bias voltages V bias and the voltages of signals DOWNF and DOWN are then selected accordingly. The operational amplifier present invention will provide typically unity gain bandwidth greater than 30 MHz, low frequency gain greater than 70dB and an output dynamic range of 8 volts peak to peak with linearity greater than 80dB. Moreover, the operational amplifier of the present invention will drive both resistive loads (typically 20K ohms) and capacitive loads (typically 5pF). Further, the slew rate mode is avoided during switching transients. Finally, the present invention provides a switchable power-down mode and an unlockable common mode control loop at power up.

Claims: An operational amplifier comprising : a differential circuitry (18) receiving a differential input signal (IN+, IN-) and generating first and second differential signals ; first and second intermediate gain stages (32,34) having that inputs coupled to the outputs fo the differential input circuitry (18) for respectively amplifying the first and second differential signals, and to the output of a common mode circuitry (54) amplifying a common mode signal ; first and second output gain stages (66,68) respectively coupled to the outputs of the first and second intermediate gain stages (32,34) for further amplifying both the differential and common mode signals ; a common mode feedback means (112-118) providing the input of the common mode circuitry with the common mode signal which is constituted of the mean value of the output of the first and second output gain stages (66,68), and closing the common mode loops which comprise the intermediate and output gain stages, and the feedback means. The operational amplifier of claim 1, wherein the differential amplifying path comprises : the said differential input circuitry (18) ; the said intermediate gain stages (32,34) ; the said output gain stages (66,68) ; a circuitry (86) coupling the said intermediate gain stages (32,34) to the said output gain stage (66,68) for dynamically controlling the bias current of the said output gain stages. The operational amplifier of claim 1 or 2, wherein the said common mode loops comprise : said common mode feedback means and common mode circuitry ; the said intermediate gain stages (32,34); the said output gain stages (66,68) ; means to adjust the gain of the common mode loop (54,30,64) independently of the gain of the differential path. The operational of claim 2 or 3 and further comprising a pole splitting compensation network (90,92, 96,98) coupling output terminals of the output gain stages (66,68) and output terminals of the intermediate gain stages (32,34), said pole splitting network being operable to provide both differential and common mode compensation. An operational amplifier as claimed in any preceding claim and wherein the common mode circuitry includes a differential amplifier (54). An operational amplifier as claimed in claim 2 and wherein the circuitry controlling the dynamic biasing of the output stage includes a first and second source follower stage coupling the outputs of the said first and second intermediate gain stages (66,68) to an auxiliary differential amplifier. An operational amplifier as claimed in claim 1 and wherein the first and second intermediate gain stages (32,34) comprise first and second cascode amplifiers. An operational amplifier as claimed in claim 1 wherein the first and second output gain stages (66,68) comprises first and second common source amplifiers. An operational amplifier as claimed in claim 6 and wherein the circuitry controlling the dynamic biasing of the output gain stage comprises a first and a second current mirror coupling the said auxiliary differential amplifier (86) to the said first and second output gain stages (66,68). An operational amplifier as claimed in claim 1 or claim 2 wherein said differential input circuitry (18) includes a differential pair and a feed forward capacitor network (22,28) coupling each input of the differential pair to the opposite output of the said differential pair. An analog to digital converter including an operational amplifier as claimed in any of claims 1 to 10. A digital to analog converter including an operational amplifier as claimed in any of claims 1 to 10.

Inventors: CARBOU PIERRE, CARBOU,PIERRE
Applicants: TEXAS INSTRUMENTS FRANCE, TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1991
Main classification: H03F3
IPC codes: H03F3