Master-slave type flip-flop circuit

Abstract: The master-slave type flip-flop circuit of the present invention comprises first and second transmission gates (G₁,G₂) for receiving an input pulse signal (Si) and an inverted input pulse signal at a data input terminal (D₁) and an inverted data input terminal (D₂), respectively, and for receiving a clock signal (S c1 ) at a common clock input terminal (CLK₁), a first data holding section (Dr₁) including first and second invertors (INV₁,INV₂) and first and second resistors (R₁,R₂) cross connected between input and output terminals of said first and second invertors for receiving outputs of said first and second transmission gates at the input terminals of said first and second invertors, respectively, third and fourth transmission gates (G₃,G₄) for receiving outputs of said first and second invertors, respectively, of said first data holding section and for receiving an inverted clock signal (S c2 ) at a common inverted clock input terminal (CLK₂), and a second data holding section (D r2 ) including third and fourth invertors (INV₁,INV₄) and third and fourth resistors (R₃,R₄) cross connected between input and output terminals of said third and fourth invertors for receiving outputs of said third and fourth transmission gates at the input terminals of said third and fourth invertors, respectively. The flip-flop circuit is reduced in total number of invertors and hence in power consumption and further reduced in number of invertors on a signal transmission line to permit a high speed operation. Where first to fourth capacitors (C₁ to C₄) are connected in parallel to the first to fourth resistors, respectively, the speed of charging and discharging of gate capacities of the transmission gates can be raised to assure a higher maximum operating frequency.

Description: FIELD OF THE INVENTION The present invention relates to a master-slave type flip-flop circuit, in accordance with the precharacterizing part of claim 1. Such a master-slave type flip-flop circuit is known from Patent Abstracts of Japan, volume 14, No. 182 (E-91), 12 April 1990 and JP-A-20034018. DESCRIPTION OF THE PRIOR ART A master-slave type flip-flop circuit is conventionally known which is constituted, for example, from a compound semiconduction (GaAs) IC (integrated circuit) wherein a GaAs MES FET (GaAs metal semiconductor field effect transistor) is employed as a logic gate element as disclosed, for example, in Japanese Patent Laid-Open Application No. 63-280509. Referring to Fig. 1, there is shown in circuit diagram an exemplary one of such conventional master-slave type flip-flop circuits. The flip-flop circuit shown includes first to eighth NOR circuits NOR 1 to NOR 8 . The third and fourth NOR circuits NOR 3 and NOR 4 and the seventh and eighth NOR circuits NOR 7 and NOR 8 constitute each a flip-flop circuit. The first and second NOR circuits NOR 1 and NOR 2 are connected to receive an input pulse signal and an inverted input pulse signal by way of a data input terminal D 1 and an inverted data input terminal D 2 , respectively, and to receive a clock signal by way of a clock input terminal CLK 1 . The fifth and sixth NOR circuits NOR 5 and NOR 6 are connected to receive outputs of the third and fourth NOR circuits NOR 3 and NOR 4 , respectively, and to receive an inverted clock signal by way of an inverted clock input terminal CLK 2 . Outputs of the seventh and eighth NOR circuits NOR 7 and NOR 8 are connected to an output terminal OUT 1 and an inverted output terminal OUT 2 respectively, of the master-slave type flip-flop circuit. It is to be noted that each of the NOR circuits NOR 1 to NOR 8 is constituted from a logic gate formed from, for example, a GaAs MES FET. The master-slave type flip-flop circuit of Fig. 1 has a drawback that a high speed operation cannot be anticipated because the first NOR circuit NOR 1 , third NOR circuit NOR 3 , fifth NOR circuit NOR 5 and seventh NOR circuit NOR 7 (or the second NOR circuit NOR 2 , fourth NOR circuit NOR 4 , sixth NOR circuit NOR 6 and eighth NOR circuit NOR 8 ) are present on a signal transmission line and, if the gate delay time by one NOR circuit is, for example, 30 ps where each gate is formed from a GaAs MES FET, then the total delay time is 120 ps. Document D 1 differs from the subject matter of the present invention in that the former includes transfer gates as feed back elements for feeding back the inverse output signals of the first and second data holding section, said transfer gates being controlled by the inverted clock signal and the non-inverted clock signal, respectively. SUMMARY OF THE INVENTION It is an object of the present invention to provide a master-slave type flip-flop circuit which involves reduced delay time and low power consumption and therefore, achieves high operating speed and can be applied for optical communication systems. The above object is, according to the invention, solved by the features specified in claim 1. Depending claims 2 and 3 are each specifying advantageous developments thereof. According to an essential aspect of the present invention, a master-slave type flip-flop circuit, comprising first and second transmission gates for receiving an input pulse signal and an inverted input pulse signal at a data input terminal and an inverted data input terminal, respectively, and for receiving a clock signal at a common clock input terminal, a first data holding section (D r1 ) including first and second invertors having their input terminals coupled to the outputs of said first and second transmission gates, respectively, third and fourth transmission gates for receiving outputs of said first and second invertors, respectively, of said first data holding section and for receiving an inverted clock signal at a common inverted clock input terminal (CLK 2 ), and a second data holding section including third and fourth invertors having their input terminals coupled to the outputs of said third and fourth transmission gates, respectively, is characterized by first and second resistors cross connected between input and output terminal of said first and second invertors, and third and fourth resistors cross-connected between input and output terminals of said third and fourth invertors and further first to fourth capacitors connected in parallel to said first to fourth resistors, respectively, to raise the maximum operation frequency and to eliminate deterioration caused by said first to fourth resistors, wherein each of said first to fourth transmission gates and said first to fourth invertors is formed from a GaAs field effect transistor. With the master-slave type flip-flop circuit, the number of invertors on a signal transmission line is reduced so that a high speed operation twice that of a conventional master-slave type flip-flop circuit can be achieved. Further, as capacities between the gates and sourced of GaAs FETs of the first to fourth transmission gates are charged and discharged by way of the first and fourth capacitors connected in parallel to the first to fourth resistors, respectively, a high maximum operating frequency can be assured. The above and other objects, features and advantages of the present invention will become apparent from the following description and the appended claims, taken in conjunction with the accompanying drawings in which like parts or elements are denoted by like reference characters. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram showing an exemplary one of conventional master-slave type flip-flop circuits: Fig. 2 is a circuit diagram showing a master-slave type flip-flop circuit having cross-connected resistors in the first and second data holding sections; Fig. 3 is a circuit diagram showing details of a data holding section of the master-slave type flip-flop circuit of Fig. 2: Fig. 4 is a timing chart illustrating operation of the master-slave type flip-flop circuit of Fig. 2: Fig. 5 is a circuit diagram of a data identifying circuit of an optical communication system to which a master-slave type flip-flop circuit is incorporated: and Fig. 6 is a circuit diagram showing a master-slave type flip-flop circuit according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring first to Fig. 2, there is shown in circuit diagram a master-slave type flip-flop circuit. The master-slave type flip-flop circuit shown has a data input terminal D 1 and an inverted data input terminal D 2 and includes first to fourth transmission gates G 1 to G 4 each formed from a GaAs FET such as GaAs MES FET, a GaAs JFET (junction type field effect transistor) or a GaAs HEMT (high electron mobility transistor), and first to fourth invertors INV 1 to INV 4 . A clock signal S c1 is supplied to the first and second gates G 1 and G 2 by way of a clock input terminal CLK 1 while an inverted clock signal S c2 is supplied to the third and fourth gates G 3 and G 4 by way of an inverted clock input terminal CLK 2 . The master-slave type flip-flop circuit further has an output terminal OUT 1 and an inverted output terminal OUT 2 . The master-slave type flip-flop circuit further includes a first resistor R 1 connected between an input terminal P 1 of the first inverter INV 1 and an output terminal P 2 of the second inverter INV 2 . A second resistor R 2 is connected between an input terminal P 3 of the second invertor INV 2 and an output terminal P 4 of the first inverter INV 1 . A third resistor R 3 is connected between an input terminal of the third inverter INV 3 and the inverted output terminal OUT 2 of the fourth invertor INV 4 . A fourth resistor R 4 is connected between an input terminal of the fourth invertor INV 4 and the output terminal OUT 1 of the third invertor INV 3 . The master-slave type flip-flop circuit further includes a first data holding section D r1 composed of the first and second invertors INV 1 and INV 2 and the first and second resistors R 1 and R 2 , and a second data holding section D r2 composed of the third and fourth invertors INV 3 and INV 4 and the third and fourth resistors R 3 and R 4 . Each of the first to fourth invertors INV 1 to INV 4 employs, as seen from Fig. 3 which shows a data holding section of a master-slave type flip-flop circuit of the present invention, a pair of GaAs FETs Q 1 and Q 2 such as, for example, GaAs MES FETs, GaAs JFETs or GaAs HEMTs as logic gate elements. It is to be noted that, while only the first data holding section D r1 is shown in Fig. 3, also the second data holding section D r2 has a substantially similar construction. In Fig. 3, reference characters RL 1 and RL 2 denote each a load resistor formed from a depletion type GaAs MES FET or the like, and V cc a power source terminal. Subsequently, operation of the master-slave type flip-flop circuit will be described with reference to Fig. 4. When such an input pulse signal S i as seen from a waveform curve A shown in Fig. 4 is supplied to the data input terminal D 1 at a time t ⊘ and simultaneously another input signal similar to but inverted in phase from the input pulse signal S 1 is supplied to the inverted data input terminal D 2 , the first data holding section D r1 is set at another time t 1 of a rising edge of a clock signal S c1 shown by a wave form curve B in Fig. 4 which is supplied to the first and second transmission gates G 1 and G 2 by way of the clock input terminal CLK 1 . The first data holding section D r1 is reset at a further time t 3 after then. Consequently, such an output pulse signal S o1 as shown by a wave form curve D in Fig. 4 appears at the output terminal P 2 of the second invertor INV 2 . Then, the second data holding section D r2 is set at a different time t 2 of a rising edge of an inverted clock signal S c2 shown by a waveform curve C in Fig. 4 which is supplied to the inverted clock input terminal CLK 2 , and is then reset at another time t 4 . Consequently, such an output pulse signal S o2 as shown by a waveform curve E in Fig. 4 appears at the output terminal OUT 2 of the fourth invertor INV 4 . When the second transmission gate G 2 is turned on at the time t 1 , an output voltage of the second gate G 2 prevails over a feedback voltage supplied thereto from the output terminal P 4 of the first invertor INV 1 by way of the second resistor R 2 thereby to invert the second invertor INV 2 from a reset state into a set state. Then, a holding current is supplied to the second invertor INV 2 by way of the second resistor R 2 in order to hold the set state of the second invertor INV 2 . On the other hand, when the fourth transmission gate G 4 is turned on at the time t 2 , an output voltage of the fourth gate G 4 prevails over a feedback voltage supplied thereto from the output terminal OUT 1 of the third invertor INV 3 by way of the fourth resistor R 4 thereby to invert the fourth invertor INV 4 from a reset state into a set state. Then, a holding current is supplied to the fourth invertor INV 4 by way of the fourth resistor R 4 in order to hold the set state of the fourth invertor INV 4 . In this instance, if the delay time of each of the second and fourth invertors INV 2 and INV 4 is 30 ps and the delay time of each of the second and fourth transmission gates G 2 and G 4 is 5 ps, then the operating time of the master-slave type flip-flop circuit is 70 ps, which is about one half that of such conventional master-slave type flip-flop circuit as described hereinabove. Subsequently, an exemplary application of a master-slave type flip-flop circuit will be described with reference to Fig. 5 which shows a data identifying circuit of an optical communication system. The data identifying circuit shown in Fig. 5 includes an input amplifier A 1 which receives a data signal of an operating speed of, for example, 2.4 Gb/s and supplies an input pulse signal S i to a data input terminal D 1 and also supplies to another inverted data input terminal D 2 an inverted input pulse signal similar to but inverted in phase to the input pulse signal S i . Another input amplifier A 2 receives a clock signal having a higher frequency than the data signal and supplies a clock signal and an inverted clock signal to a clock input terminal CLK 1 and an inverted clock input terminal CLK 2 , respectively. Then, whether data supplied to the input amplifier A 1 is a mark (high level) or a space (low level) is detected in synchronism with the inverted clock signal at the inverted clock input terminal CLK 2 , and a result of such detection is held in the fourth invertor INV 4 . The data identifying circuit further includes a pair of output amplifiers A 3 and A 4 . Also with the data identifying circuit shown in Fig. 5. similar effects to those of the master-slave type flip-flop circuit shown in Fig. 2 can be anticipated. Referring now to Fig. 6, there is shown in circuit diagram a master-slave type flip-flop circuit according to the present invention. The master-slave type flip-flop circuit has a substantially similar construction to that of the master-slave type flip-flop circuit of Fig. 2 but additionally includes first to fourth capacitors C 1 to C 4 connected in parallel to the first to fourth resistors R 1 to R 4 , respectively. Further, each of the first to fourth transmission gates G 1 to G 4 is formed from a GaAs FET. In the master-slave type flip-flop circuit of Fig. 6, charging and discharging of capacities C gs1 to C gs4 between the gates and sources of GaAs FETs forming the first to fourth transmission gates G 1 to G 4 take place by way of the first to fourth capacitors C 1 to C 4 , respectively. Accordingly, possible deterioration of the first to fourth resistors R 1 to R 4 and the first to fourth capacitors by time constants is eliminated and the maximum operating frequency can be raised. As apparent from the foregoing description, with a master-slave type flip-flop circuit of the present invention, as the number of invertors on a signal transmission line is reduced, a high speed operation twice that of a conventional master-slave type flip-flop circuit can be achieved. Further, as capacities between the gates and sources of GaAs FETs of first to fourth transmission gates are charged and discharged by way of first and fourth capacitors connected in parallel to first to fourth resistors, respectively, there is an advantage that the maximum operating frequency can be raised. Having now fully described the invention, it will be apparent to one of ordinary skill in the art that many changes and modifications can be made thereto.

Claims: A master-slave type flip-flop circuit, comprising first and second transmission gates (G 1 ,G 2 ) for receiving an input pulse signal (S i ) and an inverted input pulse signal at a data input terminal (D 1 ) and an inverted data input terminal (D 2 ), respectively, and for receiving a clock signal (S c1 ) at a common clock input terminal (CLK 1 ), a first data holding section (D r1 ) including first and second invertors (INV 1 , INV 2 ) having their input terminals coupled to the outputs of said first and second transmission gates, respectively, third and fourth transmission gates for receiving outputs of said first and second invertors, respectively, of said first data holding section and for receiving an inverted clock signal (S c2 ) at a common inverted clock input terminal (CLK 2 ), and a second data holding section (D r2 ) including third and fourth invertors (INV 3 ,INV 4 ) having their input terminals coupled to the outputs of said third and fourth transmission gates, respectively, characterized by first and second resistors (RT 1 ,RT 2 ) cross-connected between input and output terminal of said first and second invertors, and third and fourth resistors cross-connected between input and output terminals of said third and fourth invertors, and further first to fourth capacitors (C 1 to C 4 ) connected in parallel to said first to fourth resistors, respectively, to raise the maximum operation frequency and to eliminate deterioration caused by said first to fourth resistors, wherein each of said first to fourth transmission gates (G 1 -G 4 ) and said first to fourth invertors (INV 1 -INV 4 ) is formed from a GaAs field effect transistor. A master-slave type flip-flop circuit according to claim 1, wherein each of said first to fourth transmission gates and said first to fourth invertors is formed from a GaAs metal semiconductor field effect transistor. A master-slave type flip-flop circuit according to claim 1, wherein each of said first to fourth transmission gates and said first to fourth invertors is formed from a GaAs junction type field effect transistor.

Inventors: TAKANO CHIAKI, TAKANO, CHIAKI
Applicants: SONY CORP, SONY CORPORATION
Application year: 1991
Main classification: H03K3
IPC codes: H03K3