Integrated structure of a bipolar power transistor and a low voltage bipolar transistor in the emitter switching or semibridge configurations and associated manufacturing processes

Abstract: In the version with unisolated components the components of the structure are totally or partially superimposed on each other, partly in a first epitaxial layer and partly in a second epitaxial layer; the low voltage bipolar transistor is indeed situated above the emitter region of the bipolar power transistor which is thus a completely buried active structure. In the version with isolated components, in an n- epitaxial layer there are two p+ regions, i.e. the first, constituting the power transistor base, encloses the n+ emitter region of said transistor while the second encloses two n+ regions and one p+ region constituting the collector, emitter and base regions respectively of the low voltage transistor. A metallization on the front of the chip provides connection between the collector contact of the low voltage transistor and the emitter contact of the power transistor.

Description: The object of the present invention is an integrated structure of a bipolar power transistor and a low voltage bipolar transistor in the emitter switching or semibridge configurations and associated manufacturing processes. Emitter switching is a circuit configuration in which a low voltage transistor of the MOS or bipolar type interrupts the emitter current of a high voltage power transistor, typically a bipolar transistor. With low voltage transistors of the bipolar type this configuration was heretofore provided with discrete components while with low voltage transistors of the MOS type it was also provided with components integrated in the same chip of semiconductor material. An example of an integrated structure in the emitter switching configuration with low voltage transistor of the MOS type is illustrated in EP-A-322041. An example of vertical bipolar transistors of different conductivity type realized one at the side of the other in a same semiconductor substrate is described in EP-A-347550. In addition to the advantages which an integrated circuit generally has compared with an analog circuit provided with discrete components, an integrated form of an emitter switching circuit configuration also allows: increased ruggendness of the bipolar power transistor as concerns the possibility of occurrence of reverse secondary breakdown phenomena (Es/B); joining to the voltage and current capabilities of the driven transistor the performance of speed of the low voltage transistor; direct driving of the system with linear logic circuits through the base of the low voltage transistor. The integrated structure of a bipolar power transistor and a low voltage bipolar transistor in the emitter switching or semibridge configurations in accordance with the present invention thus allows the above advantages. In addition, as compared with the integrated structure with low voltage transistor of the MOS type described in the above-mentioned EP-A-322041, it has the further advantage of being made by means of simpler and more economical manufacturing processes. The structure and processes which in accordance with the present invention allow the aforesaid advantages are set forth in the claims below. The invention will be further clarified by the description given below and the annexed drawings of nonlimiting examDles of embodiments of the invention, in which: FIG.1 shows schematically the eauivalent electrical circuit of the integrated circuit in accordance with the present invention in the 5-terminal version, FIGS. 2-7 show schematically a structure in accordance with the present invention during the various steDs of the manufacturing process, FIG.8 shows schematically the structure at the end of the process indicated in the above FIGS. 2-7, FIG.8A shows schematically the structure at the end of the process indicated in the above FIGS. 2-7 with the addition of the sinker region and the overlying contact Cp, FIG.9 shows schematically the profile of the concentrations of the various types of dopant along a section of the structure of FIG. 7. FIG. 1 shows the electrical circuit equivalent of the integrated structure which the present invention intends to provide in the 5-terminal version. Said circuit consists of a bipolar power transistor Tp connected through its own emitter to the collector of a low voltage bipolar transistor Ts. The electrode Cp for connection of the buried collector of the low voltage transistor Ts and the emitter of Tp is unnecessary for the emitter switching configuration while it is essential for operation of the circuit in semibridge configuration. In this latter case a current flows in the node Cp in one direction or the opposite direction depending on the conduction state of the transistorS Tp and Ts. which, in order to avoid shorting to ground. cannot be in conduction at the same time. The manufacturing process for the integrated structure in a version with superimposed components not isolated from each other as shown in FIG. 8, is hereinafter described. On a silicon substrate 1 of type n+ (FIG.2) there is grown a first epitaxial layer 2 with n- conductivity and high resistivity. On said layer 2 is then obtained by an ion implantation and subsequent diffusion process a type p+ region 3 (FIG.3). By a similar process there is then provided an n+ region 4 (FIG.4). There follows growth of a second epitaxial layer 5 of type n (FIG.5) and, by known oxidation, photomasking, implantation and diffusion processes, definition of the p+ regions 8 which extend from the surface 9 of the chip until they reach the region 3 (as illustrated in FIG.6) so as to enclose therein the collector region (5) of Ts. FIG.7 represents the structure after a subsequent step. i.e. after the growth (again using known techniques) on the surface layer 18 of thermal oxide SiO 2 , and the defining of p+ region 6 and n+ region 7 which make up the base and emitter respectively of the npn transistor indicated by Ts in the equivalent circuit of FIG. 1. In said FIG. 7 the emitter of the transistor Tp consists of the n+ region 4 completely buried. The collector of the low voltage transistor is thereby connected directly to the emitter 4 of the power transistor. There follow the metallizations 10, 11, 13 and 14 designed to ensure ohmic contact with the regions 6, 7, 8 and the substrate 1 and to constitute the terminals B', E, B and C, which have the same meaning as the homologous terminals of FIG. 1. The final structure resulting from the process described above is shown in FIG. 8. If said structure of FIG. 8 is to be used in the semibridge configuration it must be integrated with the regions which allow access through an added terminal Cp to the buried emitter region 4 of the power transistor. For this purpose the manufacturing process described above must be changed as follows. After the steps which lead to the structure of FIG. 6 known photomasking, implantation and diffusion processes are used to provide the n+ sinker regions (the regions 16 of FIG. 8a) which extend from the surface of the chip until they reach the buried region 4. The definition of the p+ region 6 and of the n+ regions indicated by reference numbers 7 and 17 in FIG. 8a, is then carried out, the regions 17 being sinker enriched regions aimed at improving the contacts and reducing the electrical resistance of the sinker. After the last steps of metallization and provision of the electrodes, the structure appears as shown in FIG. 8a. The profile of the concentration (Co) of the various types of dopant in the different regions of the structure, along plane of cut A-A of FIG. 7, is illustrated in FIG. 9 where on the axis X is shown the distance from the upper surface of the chip. It is noted that the terminal Cp can be necessary also in the emitter switching configuration in order to detect the voltage present on the collector of Ts, prevent full saturation of Ts through control of its base current (anti saturation circuit) and thus speed up its switching. The first epitaxial growth on the substrate could be unnecessary if a substrate with characteristics equivalent to those of the substrate mentioned above (substrate 1 of FIG. 2) is adopted after growth of the first epitaxial layer. In addition, although the present invention is illustrated for a structure with npn transistors, it also applies, with variations apparent to those skilled in the art, to structures with pnp transistor provided, in this case, starting from a type p substrate. The processes described lend themselves naturally to simultaneous embodiment on the same chip of several pairs of bipolar transistors Tp and Ts. This finds application, for examDle, in semibridge structures for control of direct current or step motors (for which two pairs are sufficient) and for control of 3-phase current motors (for which three pairs are needed). In these cases all the transistors Tp are provided on the same substrate and therefore have a common collector terminal while the electrodes of each pair provided on the front of the chip can be connected together and to the external circuitry depending on design requirements.

Claims: Structure comprising a bipolar power transistor, hereinafter called Tp, and a low voltage bipolar transistor, hereinafter called Ts, in the emitter switching configuration integrated in a same chip of semiconductor material, characterized by the presence in combination of: a semiconductor substrate (1,2) with a first type of conductivity constituting the collector of Tp, a first region (3) with a second type of conductivity opposite said first type of conductivity, provided in the substrate (1,2) and constituting the base region of Tp, a second region (4) with the first type of conductivity provided in said first region (3), constituting the emitter of Tp and at the same time the collector of Ts, an epitaxial layer ( 5 ) with the first type of conductivity disposed on the entire surface of the chip, third regions (8) with the second type of conductivity, formed in said epitaxial layer ( 5 ) and connected to said first region (3) so as to enclose therein a fourth region, constituting the collector region (5) of Ts, a fifth region (6) with the second type of conductivity constituting the base of Ts, defined in a portion of said fourth region (5), a sixth region (7) with the first type of conductivity, provided in said fifth region (6) and constituting the emitter region of Ts, metallizations on the front of the chip constituting the emitter electrodes (E) of Ts, base electrodes (B') of Ts, and base electrodes (B) of Tp, a metallization on the entire back surface of the chip constituting the collector electrode (C) of Tp. Structure in accordance with claim 1 characterized in that the substrate (1,2) comprises a further epitaxial layer (2) in which is provided said first region (3). Structure comprising a bipolar power transistor thereinafter called Tp, and a low voltage bipolar transistor, hereinafter called Ts, in the semibridge configuration integrated in a same chip of semiconductor material, characterized by the presence in combination of: a semiconductor substrate (1/2) with a first type of conductivity constituting the collector of Tp, a first region (3) with a second type of conductivity opposite said first type of conductivity, provided in the substrate (1,2) and constituting the base region of Tp, a second region (4) with the first type of conductivity provided in said first region (3), constituting the emitter of Tp and at the same time the collector of Ts, an epitaxial layer ( 5 ) with the first type of conductivity disposed on the entire surface of the chip, third regions (8) with the second type of conductivity, formed in said epitaxial layer ( 5 ) and connected to said first region (3) so as to enclose therein a fourth region, constituting the collector region (5) of Ts, a fifth region (6) with the second type of conductivity constituting the base of Ts, defined in a portion of said fourth region (5), a sixth region (7) with the first type of conductivity, provided in said fifth region (6) and constituting the emitter region of Ts, metallizations on the front of the chip constituting the emitter electrodes (E) of Ts, base electrodes (B') of Ts, and base electrodes (B) of Tp, a metallization on the entire back surface of the chip constituting the collector electrode (C) of Tp. at least one sinker region (16,17) with the first conductivity type formed in said fourth region (5) designed to carry said second region to the surface of the chip, at least one metallization (15) on the front of the chip constituting an electrode (Cp) for connection to said sinker region (16,17). Structure in accordance with claim 3 characterized in that the substrate (1,2) comprises a further epitaxial layer (2) in which is provided said first region (3). Structure in accordance with claim 3 characterized in that said sinker region (16,17) connects to the entire contour of said second region (4) so as to completely enclose said fifth region (6). Structure in accordance with claim 5 characterized in that said sinker region (16,17) has a higher percentage of dopant in a part (17) near the surface of the chip. Process for manufacturing a circuit structure integrated in a chip of semiconductor material, comprising a bipolar power transistor and a low voltage bipolar transistor in the emitter switching configuration, which comprises: creating, in a silicon substrate (1,2) of a first type of conductivity, a first region (3), having a second type of conductivity which is opposite said first type of conductivity, by deposition or ion implantation of dopant and subsequent diffusion process, providing a second region (4) having the first type of conductivity, inside said first region (3), by deposition or ion implantation of dopant and subsequent diffusion process growing an epitaxial layer ( 5 ) of the first type of conductivity, defining third regions (8), of the second type of conductivity, inside said epitaxial layer ( 5 ), by known oxidation, photomasking, deposition or implantation of dopant and diffusion processes, said third regions extending from the surface (9) of the chip to said first region (3), so as to define and enclose therein a fourth region (5) of the first type of conductivity, growing a layer (18) of thermal oxide SiO 2 on the surface of said epitaxial layer ( 5 ), defining a fifth region (6) of the second type of conductivity, inside said fourth region (5), defining a sixth region (7) of the first type of conductivity, inside said fifth region (6), realizing ohmic contacts with said third, fifth, sixth regions and with the back of the substrate by metallization. Process for manufacturing a circuit structure in accordance with claim 7 characterized in that, before creating said first region (3) another epitaxial layer (2) of the first type of conductivity is grown on said substrate (1,2). Process for manufacturing a circuit structure integrated in a chip of semiconductor material, comprising a bipolar power transistor and a low voltage bipolar transistor in the semibridge configuration, which comprises: creating, in a silicon substrate (1,2) of a first type of conductivity, a first region (3), having a second type of conductivity which is opposite said first type of conductivity, by deposition or ion implantation of dopant and subsequent diffusion process, providing a second region (4) having the first type of conductivity, inside said first region (3), by deposition or ion implantation of dopant and subsequent diffusion process growing an epitaxial layer ( 5 ) of the first type of conductivity, defining third regions (8), of the second type of conductivity, inside said epitaxial layer ( 5 ), by known oxidation, photomasking, deposition or implantation of dopant and diffusion processes, said third regions ex-tending from the surface (9) of the chip to said first region (3), so as to define and enclose therein a fourth region (5) of the first type of conductivity, realizing seventh regions (16) of the first type of conductivity inside said fourth region ( 5 ), extending from the surface (9) of the chip to said second region (4), growing a layer (18) of thermal oxide SiO 2 on the surface of said epitaxial layer ( 5 ), defining a fifth region (6) of the second type of conductivity, inside said fourth region (5), defining a sixth region (7) of the first type of conductivity, inside said fifth region (6), realizing ohmic contacts with said third, fifth, sixth, and seventh regions and with the back of the substrate by metallization. Process for manufacturing a circuit structure in accordance with claim 9 characterized in that, before creating said first region (3) another epitaxial layer (2) of the first type of conductivity is grown on said substrate (1,2).

Inventors: PAPARO MARIO, PUZZOLO SANTO, ZAMBRANO RAFFAELE, PAPARO, MARIO, PUZZOLO, SANTO, ZAMBRANO, RAFFAELE
Applicants: CONS RIC MICROELETTRONICA, SGS THOMSON MICROELECTRONICS, CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1991
Main classification: H01L27
IPC codes: H01L27, H01L29, H01L21