Information processing system

Abstract: An information processing system having a memory for storing a plurality of programs executed in a parallel processing manner, an instruction interpretation section for interpreting instructions in the programs, and an instruction execution section for executing the interpreted instructions. Cues for registering the numbers of the steps of the programs to be executed, wherein the numbers of the steps to be executed next are registered in the cues, the number of each step registered in the cues is read out, the processing to be performed in accordance with the step corresponding to the step number read out is interpreted, and instructions are given to the instruction interpretation section according to the content of the step interpreted. The step numbers of other steps to be executed are registered in the cues, and the plurality of programs are executed in parallel based on the order of the cues.

Description: This invention relates to an information processing system in which instructions stored in a memory are successively read out to execute instructed processing and, more particularly, to an information processing system for executing a plurality of programs virtually in parallel. A plurality of programs can be executed with one CPU in a virtually parallel manner by changing the CPU at certain time intervals (not always constant) to successively execute the programs little by little. Determining the procedure of changing the CPU for this purpose is called scheduling, and a program for scheduling the CPU is called a monitor. There are conventional CPU scheduling methods: a) one in which programs are executed in order of arrival of execution requests at the monitor irrespective of the kind and size of the programs, and in which the CPU is not changed over until one program is completed (FCFS method); b) one in which if during execution of a program the monitor receives a request for execution of another program which can be executed in a shorter length of time in comparison with the program presently being executed, the program of the shorter execution time being executed immediately (SPT method); and c) one in which the CPU is assigned to each program for a predetermined constant length of time (quantum) irrespective of the size and the kind of the programs, and in which if the processing of one program is not completed in one quantum, it is suspended to be started again in the next cycle of the program rotation and the CPU is assigned to the next program (RR method). The FCFS method entails a drawback such that when a program having a long processing time is executed, services to other programs are insufficient. In the case of the SPT method, it is difficult to previously know the processing time for each program, and the load on the monitor is increased by the operation of detecting the processing time. In the case of the RR method, the same problem as that of the FCFS method is encountered with respect to a long-processing-time program, if the quantum is excessively long. If the quantum is short, the CPU is frequently changed over and the overhead of the monitor is large. It is therefore necessary to optimize the quantum by considering these conditions, but it is difficult to determine an optimal quantum. EP-A-0113516 discloses an information processing system for executing a plurality of programs wherein the programs are stored and are executed concurrently. The programs are available to a processor as a sequence of processes. The processor executes the first process until it is instructed to stop for the time being and then the processor moves on to execute the next process. This is repeated cyclically throughout the process to be executed. According to one aspect, the present invention provides an information processing system for executing a plurality of programs, the system comprising: first storage means for storing the plurality of programs, each comprising a plurality of instructions; processing means for reading and concurrently executing the plurality of stored programs; characterised by: said programs being identified by program numbers and each program comprising a program sequence of numbered steps, each step containing at least one instruction and information identifying the next step to be executed in the program sequence; second storage means having a plurality of memory locations for sequentially storing numbers of steps and corresponding program numbers for said plurality of programs in an execution sequence; read control means for reading from said second storage means the program number and step number of the step to be executed next in the execution sequence, from which the step number and program number of the step to be executed next is read out; said processing means reading and executing the or each instruction in each step of the stored programs identified by the read program number and step number; and write control means for writing the step number and corresponding program number identified as the next step in the program sequence for the step executed by said processing means into the next available memory location in the execution sequence of said second storage means, including second pointer means for identifying the next available memory location in said execution sequence at which the step number and program number of the step to be executed next in the program sequence is to be written. According to another aspect the present invention provides a method of processing information by executing a plurality of programs each program comprising a plurality of instructions, the method comprising the steps of: reading the instructions of the stored programs, and concurrently executing the plurality of programs, characterised by: said programs being identified by program numbers and each program comprises a program sequence of numbered steps, each step containing at least one instruction and information identifying the next step to be executed in the program sequence; the storing step of storing numbers of steps and corresponding program numbers for the first steps of said plurality of programs in first positions in an execution sequence; the read identifying step of identifying, using a first pointer, a position in the execution sequence from which the program number and step number of the step to be executed next in the execution sequence is read out; the reading step of reading out the program number and step number of the step to be executed next; the step of executing of the plurality of program comprising executing the or each instruction in each step of the stored programs identified by the read program number and step number; the write identifying step of identifying using a second pointer the next available memory location in the execution sequence at which the step number and program number of the step identified as the next step in the program sequence for the executed step is to be written; the writing step of writing the step number and program number of the step to be executed next in the program sequence into the identified next available memory location in the execution sequence; and repeating the read identification step, the reading step, the execution step, the write identifying step and the writing step until the steps of said plurality of programs have been executed. Embodiments of the present invention will now be described with reference to the accompanying drawings, in which: Fig. 1 is a diagram of execution wait queues for determining the CPU scheduling of a virtual parallel processing system in accordance with one embodiment of the present invention; Fig. 2 is a block diagram of the information processing apparatus; Fig. 3 is a diagram of the form of instructions executed by the information processing system; Fig. 4 is a flow chart of a process of virtual parallel processing; and Figs. 5(a) and 5(b) are a program block diagram and a diagram of samples of execution wait queues. Fig. 1 is a diagram of execution wait queues for determining scheduling of a CPU of a virtual parallel processing system in accordance with one embodiment of the present invention. Each of the programs executed by this system is expressed as a set of steps which are minimum division units of processing. In a program number registration section 10, program numbers pertaining to steps in a wait state at a certain time are registered. In a step number registration section 11, step numbers of the steps in the wait state at the corresponding time are registered. A read queue pointer 12 indicates a step executed at the corresponding time. A write queue pointer 13 indicates the place of the step number to be registered next. Fig. 2 is a block diagram of the virtual parallel processing system in accordance with one embodiment of the present invention The system has a register 20 in which data or the result of calculation is temporarily stored, and a memory 21 in which programs or data are stored. The programs include user programs such as those shown in Fig. 5(a) and a monitor such as that shown in Fig. 4. Each program stored in the memory 21 is sent to an instruction decoder 22 through a bus 24 to be interpreted. The result of interpretation is sent to an instruction execution section 23 to execute the program. A block 25 corresponds to the registration section shown in Fig. 1. A CPU 26 has a decoder 22 and an execution section 23. Each step is provided in the form shown in Fig. 3. In the process of the monitor, an OP code section 30 of each step is referred to and the kinds of instructions to be executed are discriminated. Information on details of the instructions to be executed is obtained by referring to an operand section 31, operations to be performed by the CPU are determined along with the kinds of the instructions to be executed, and a corresponding instruction set is given to the CPU. After the CPU has completed the execution of the given instruction set, the number of the step to be executed next is obtained by referring to a termination section 32 of the step. On the other hand, the step numbers of steps in the execution wait state are registered in the execution wait queues in the registration section 11 shown in Fig. 1. The read queue pointer 12 indicates a step which is being executed. The read queue pointer 12 is incremented by 1 when the execution of this step is completed. The numbers of the programs to which the steps registered in the execution wait queues pertain are registered in the program number registration section 10, while the numbers of the steps registered in the execution wait queues are registered in the step number registration section 11. The monitor can therefore recognize the step to be executed and the program to which the step pertains by referring to both the program number registration section 10 and the step number registration section 11 at the position of the execution wait queue indicated by the read queue pointer 12. The above-described operations will be described below with reference to Fig. 4 showing a flow chart of virtual parallel processing. It is assumed here that a step has already been registered in one execution wait queue (in a state where the positions indicated by the read queue pointer 12 and the write queue pointer 13 do not coincide with each other). In step 40, the CPU 26 checks whether there is any step in the execution wait state. If there is a step in the execution wait state, the CPU 26 refers to, in step 41, the program number and the step number registered at the position indicated by the read queue pointer 12. In step 42, the CPU 26 executes the step designated by the CPU 26. When the execution of the step is completed, the CPU refers to the termination section 32 of the executed step, finds the step number of the step to be executed subsequently to the present step in the corresponding program, and writes the step number at the position indicated by the write queue pointer 13. In step 44, the CPU increments the write queue pointer 13 by 1. If at this time the write queue pointer 13 exceeds the end stage of the execution wait queues, the top address of the execution wait queues is substituted in the write queue pointer 13 so that the write queue pointer 13 is returned to the top execution wait queue. In step 45, the CPU increments the read queue pointer 12 by 1. If at this time the read queue pointer 12 exceeds the end stage of the execution wait queues, the top address of the execution wait queues is substituted in the read queue pointer 12 so that the read queue pointer 12 is returned to the top execution wait queue. The process returns to step 40, and the CPU checks whether or not there is any step in the execution wait state. If there is a step in the execution wait state, the above-described procedure is repeated. If there is no step in the execution wait state, the process is terminated in step 46. The process will be further described with respect to examples of the programs and queues shown in Figs. 5(a) and 5(b). It is assumed here that programs 1 and 2 shown in Fig. 5(a) are in a state of being executed in parallel, a program 1 step 1 and a program 2 step 1 are registered in the execution wait queues of the registration section, and a read queue pointer 57 indicates the program 1 step 1, as shown in Fig. 5(b). It is also assumed that a program 1 step 2 (51) and a program 1 step 3 (52) shown in Fig. 1 are executed in parallel with each other. First, the place indicated by the read queue pointer 57 is referred to and it is thereby recognized that the step to be executed in step 1 by the CPU is the program 1 step 1 (50). The OP code section and the operand section of the program 1 step 1 are read out and a correspondinq instruction set is given to the CPU (not shown). When the CPU (not shown) has completed the execution of the given instruction set, the termination section (not shown) of the program 1 step 1 (50) is read out to find the step to be executed subsequently to the step 1 (50) in the program 1. Since information is written in the termination section of the program 1 step 1 (50) to indicate that the program 1 step 2 (51) and the program 1 step 3 (52) are steps to be executed next, the program number and the step number of the program 1 step 2 (51) are written in the place of the execution wait queue indicated by a write queue pointer 58 in Fig. 5(b). The write queue pointer 58 is then incremented by 1. If the write queue pointer 58 exceeds the end stage of the execution waitqueues, the top address of the execution wait queues is substituted in the write queue pointer 58 so that the write queue pointer 58 is returned to the top execution wait queue. Since in this case there is another step to be executed, the monitor writes the program number and the step number of the program 1 step 3 (52) of the place of the execution wait queue indicated by the write queue pointer 58 in Fig. 5(b), and increments the write queue pointer 58 by 1. The monitor then increments the read queue pointer 57 by 1, since the execution of the program number 1 step 1 (50) has been completed. If the read queue pointer 57 exceeds the end staqe of the execution wait cues, the top address of the execution wait queues is substituted in the read queue pointer 57 so that the read queue pointer 57 is returned to the top execution wait queue. The process then proceeds to execute the next step. The read queue pointer 57 presently indicates the program 2 step 1, and, by reference to the execution queue of Fig. 5(b), it is recognized that the program 2 step 1 (54) is to be executed, the OP code section and the operand section of the program 1 step 2 (54) are read out, and a corresponding instruction set is given to the CPU. When the CPU completes the instructed operation, the termination section of the program 2 step 1 (54) is read out and the program number and the step number of the step to be executed subsequently to the step 1 in the program 2 (program 2 step 2 in this case) are written at the position indicated by the write queue pointer 58. Then the write queue pointer 58 and the read queue pointer 57 are respectively incremented by 1. If a queue pointer exceeds the end stage of the execution wait queues, the top address of the execution wait queues is substituted so that the queue pointer is returned to the top execution wait queue. Next, since the read queue pointer 57 is indicating the program 1 step 2 (51), the execution of the program 1 step 2 (51) is started. Subsequently, the same procedure is repeated until the execution queue shown in Fig. 5(b) become empty. In the above-described embodiment, the programs are formed of steps which are minimum division units of processing. However, this is not essential to the present invention, and the present invention can easily be applied to programs having a hierarchic structure such that a set of steps constitutes a sub program and a set of sub programs constitutes a program. The above-described embodiment has an interpreter form such that steps having a structure such as that shown in Fig. 3 are interpreted and executed by a monitor, but this also is not essential to the present invention. Even in the case of a compiler form such as programs expressed by codes which can be directly interpreted by the CPU, it is easy to register, in an execution wait queue, a step to be executed subsequently to a certain step when this preceding step is executed, which effect is realized by inserting in each step information on the step to be executed subsequently. An arrangement may be such that when an execution wait queue with higher priority becomes empty, a step registered in the queue of the next priority rank is executed, thereby making it easy to control a system in which a plurality of programs differing in priority coexist. Thus, each program is formed of steps defined as minimum execution units, the numbers of steps to be executed are registered in queues, and the CPU is changed over according to the queues, thereby efficiently executing parallel processing in a plurality of programs or one program in a virtual parallel manner. The possibility of insufficiency of services to a particular program is thereby reduced, and the overhead of the monitor is reduced since the CPU is changed over in an optimal quantum. Also, each queue has a simple structure formed of a program number registration section and a step number registration section, and registration in each queue and reading of the content of each queue are therefore easy and the load on the monitor is reduced. While the present invention has been described with respect to what presently are considered to be the preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiment.

Claims: An information processing system for executing a plurality of programs, the system comprising: first storage means (21) for storing the plurality of programs, each comprising a plurality of instructions; processing means (26) for reading and concurrently executing the plurality of stored programs; characterised by: said programs being identified by program numbers and each program comprising a program sequence of numbered steps, each step containing at least one instruction and information identifying the next step to be executed in the program sequence; second storage means (10,11) having a plurality of memory locations for sequentially storing step designating numbers and corresponding program numbers for said plurality of programs in an execution sequence; read control means (12) for reading from said second storage means (10,11) the program number and step number of the step to be executed next in the execution sequence, including first pointer means for identifying a position in said execution sequence, from which the step number and program number of the step to be executed next is read out; said processing means (26) reading and executing the or each instruction in each step of the stored programs identified by the read program number and step number; and write control means (13) for writing the step number and corresponding program number identified as the next step in the program sequence for the step executed by said processing means (26) into the next available memory location in the execution sequence of said second storage means (10,11), including second pointer means for identifying the next available memory location in said execution sequence at which the step number and program number of the step to be executed next in the program sequence is to be written. A system as claimed in claim 1 wherein said processing means (26) comprises instruction interpretation means (22) for interpreting instructions in each of said programs corresponding to the steps whose numbers are read by said read control means (12); and instruction execution means (23) for executing interpreted instructions interpreted by said instruction interpretation means (22). A system as claimed in claim 1 or claim 2 wherein each step of each program includes a termination section (32) identifying the next program step, said processing means (26) being programmed to execute the or each instruction for each step of said program, to determine the identification of the next step in said program sequence from said termination section, to control said write control means (13) to write the number of the next step in said program sequence at the position identified by said second pointer means to increment said second pointer means to identify the next position in said execution sequence, and to increment said first pointer means to identify the next step in said execution sequence to be executed. A system as claimed in any preceding claim, wherein said second storage means (10,11) has a first area (11) for storing the number of each step and a second area (10) for storing the number of the corresponding program for each step. A system as claimed in any preceding claim further comprising means for determining whether or not a number of any step to be executed next is stored in said second storage means (10,11). A system as claimed in any preceding claim further comprising a plurality of execution sequences, said execution sequences being defined to have a priority order; wherein said storage means (10,11) is arranged to store said plurality of execution sequences in a plurality of memory sequences, each memory sequence having a plurality of memory locations for sequentially storing numbers of steps in a said execution sequence; and said processing means (26) is programmed to execute the steps in said execution sequences in priority order. A method of processing information by executing a plurality of programs each program comprising a plurality of instructions, the method comprising the steps of: reading the instructions of the stored programs, and concurrently executing the plurality of programs, characterised by: said programs being identified by program numbers and each program comprises a program sequence of numbered steps, each step containing at least one instruction and information identifying the next step to be executed in the program sequence; the storing step of storing step designating numbers of steps and corresponding program numbers for the first steps of said plurality of programs in first positions in an execution sequence; the read identifying step of identifying, using a first pointer, a position in the execution sequence from which the program number and step number of the step to be executed next in the execution sequence is read out; the reading step of reading out the program number and step number of the step to be executed next; the step of executing the plurality of programs comprising executing the or each instruction in each step of the stored programs identified by the read program number and step number; the write identifying step of identifying using a second pointer the next available memory location in the execution sequence at which the step number and program number of the step identified as the next step in the program sequence for the executed step is to be written; the writing step of writing the step number and program number of the step to be executed next in the program sequence into the identified next available memory location in the execution sequence; and repeating the read identification step, the reading step, the execution step, the write identifying step and the writing step until the steps of said plurality of programs have been executed. A method as claimed in claim 7 wherein said step of executing the or each instruction comprises the steps of interpreting instructions in each of said program corresponding to the steps whose numbers are read; and executing the interpreted instructions. A method as claimed in claim 7 or claim 8 wherein each step of each program includes a termination section identifying the next step, the method including the steps of identifying the next step in said program sequence from said termination section, storing the number of the next step in said program sequence at the position identified in said execution sequence, incrementing said second pointer to identify the next position in said execution sequence, and incrementing said first pointer to identify the next step in said execution sequence to be executed. A method as claimed in any one of claims 7 to 9 including the step of determining whether or not a number of any step to be executed next is stored. A method as claimed in any one of claims 7 to 10 wherein a plurality of execution sequences are stored, said execution sequence being defined to have a priority order, the method including the step of executing the steps in said execution sequences in priority order.

Inventors: KADOSAWA TSUNEAKI, KOGA EIJI, NAKAMURA TAKASHI, OZAWA KUNITAKA, WATANABE HITOSHI, KADOSAWA, TSUNEAKI, KOGA, EIJI, NAKAMURA, TAKASHI, OZAWA, KUNITAKA, WATANABE, HITOSHI
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1991
Main classification: G06F9
IPC codes: G06F9