Method for producing a semiconductor device with a high density wiring structure

Abstract: A semiconductor device with a high-density wiring structure, and a producing method for such device are provided. The semiconductor device has a substrate such as silicon, an insulation layer laminated on the substrate and having a groove or a hole, and a wiring of a conductive material formed in the groove or hole in the insulation layer. The wiring is formed by depositing a conductive material such as aluminum or an aluminum alloy in the groove or hole of the insulation layer by a CVD method utilizing alkylaluminum hydride gas and hydrogen. The groove or hole can be formed by an ordinary patterning method combined with etching.

Description: The present invention relates to a method for producing a semiconductor device having a multi-layer wiring or screened co-axial wiring structure, as also a semiconductor device having a screened co-axial wiring structure produced thereby. At first there will be explained the producing method of a conventional example of the semiconductor device, with reference to Figs. 1B and 1A, which are respectively a plan view of the semiconductor device and a cross-sectional view along a line A-A' in Fig. 1B. On a semiconductor substrate 55 already bearing functional elements thereon, BPSG (boron phospho silicate glass) or PSG (phosphosilicate glass) is deposited with a thickness of 600 - 800 nm (6000 - 8000 Å) for example by CVD to form a first insulation layer 53. Then contact holes 56, for connecting the semiconductor substrate 55 with first wirings 51, are opened by patterning. The etching in this operation is usually conducted with a mixture of fluorine gas and chlorinated gas, anisotropically in the direction of depth. Then Al (or an Al alloy) is deposited with a thickness of 0.6 - 1 µm over the entire surface for example by magnetron sputtering, and an etching operation with Cl-containing etching gas is conducted to form the first Al wiring layer 51 into desired patterns. Subsequently PSG, or a silicon nitride film by plasma CVD, is deposited over the entire surface, thereby obtaining an insulation layer 54 of a thickness of 5000 - 8000 Å. Subsequently through-holes 57 are opened by patterning of photoresist and etching with a fluorine/chlorine-containing gaseous mixture. Then aluminium is deposited with a thickness of ca. 0.8 - 1.2 µm over the entire surface again with the magnetron sputtering apparatus, and second wirings 52 are formed with desired pattern to obtain the semiconductor device as shown in Figs. 1A and 1B. It is generally difficult to position the through-hole 57 strictly above the contact hole 56, as shown in Fig. 1A because the surface shows significant steps in the vicinity of the contact hole due to the stepped structure therein, so that the through-hole 57 positioned above may not be opened completely or the upper second wiring 52 cannot sufficiently cover the significant step and may become disconnected. Also the wiring pattern has to be made with a size showing a certain margin to the periphery of the contact hole 56, in order that said contact hole 56 is securely covered by the first wiring 51. If said margin is not enough, the aluminium in the contact hole may also be etched in the aluminium etching operation, whereby serious troubles may arise in the contact resistance and in the surface insulation characteristic. A similar situation applies also to the relation between the pattern of the through-hole 57 and the second wiring 52. Because of the above-mentioned reasons, the wiring area can only be reduced to a certain limit, and the chip size cannot be reduced significantly, with the surface steps therein, despite of the miniaturization of the constituent elements. Now, there will be explained the method of forming contact between a semiconductor electrode and a silicon substrate, and forming a through-hole in a multi-layered wiring structure in the conventional semiconductor devices, with reference to Figs. 2 to 5. Fig. 2 is a cross-sectional view of a structure in which a through-hole 101 is formed, above a field oxide film 104, in order to connect a first aluminium layer 101 and a second aluminium layer 102. 103 indicates a silicon substrate, and 104 and 105 are SiO 2 films. In such case, the through-holes can be formed with a minimum size, but such structure is an obstacle to the high level of integration as the first aluminium layer 101 has to be connected to above a field oxide film 106. Fig. 3 is a cross-sectional view of a through-hole TH102 formed in a relatively thin oxide film 107, instead of the field oxide film. 108 indicates a SiO 2 film. As indicated by dimensions L1, L2, L3, L4, L5 and L6 respectively of 0.4, 0.8, 0.8, 1.6, 0.8 and 4.2 µm, the through-hole has to be sized larger for ensuring a proper aperture in the photolithography because of the height relationship different from that in the through-hole in the field oxide film. Also the connection to the first aluminium layer has to be established as in the structure shown in Fig. 3. Figs. 4 and 5 are cross-sectional views of a through-hole formed on a contact by a first Al layer 101 to the silicon substrate, wherein 109 and 110 indicate SiO 2 films. In Fig.5 , dimensions L7, L8, L9, L10, Lll and L12 are respectively 0.4, 0.8, 0.8, 0.8, 0.4 and 3.2 µm. In Fig. 4 the through-hole TH103 is larger than the contact hole CH103, while in Fig. 5, the through-hole TH104 is smaller than the contact hole CH104. In either case a proper hole opening has to be secured by employing different sizes for the contact and through holes, thereby utilizing a relatively flat area for forming the through-hole. Figs. 6A and 6B show a coaxial wiring achieved by a conventional three-layer Al wiring technology, wherein Fig. 6A is a schematic cross-sectional view of said coaxial wiring structure, while Fig. 6B is a plan view thereof. A second aluminium layer 202 is used as a signal line, while a first aluminium layer 201 and a third aluminium layer 203 are used as shield wires and are mutually connected through first through-holes 209, second aluminium layers 202 and second through-holes 210. 204 indicates a SiO 2 substrate. The first aluminium layer 201 and the third aluminium layer 203 are connected to an electrically stable potential (ground potential). In Fig. 6A, dimensions L1, L2, L3 and L4 are respectively 3.2 or 4.2, 1.0, 1.5 and 6.7 or 7.7 µm. A multi-layered wiring structure as shown in Figs. 1A and 1B, obtained by a conventional multi-layered wiring technology, has the associated following drawbacks to be resolved. The multi-layered wiring structure, intended for increasing the wiring density, has been obtained by laminating an insulation layer (a silicon oxide film) on a first wiring layer, then forming a second wiring layer, and repeating the above-mentioned operations for third and subsequent wiring layers. Thus the structure of wiring is defined by the disconnection or migration of the wirings resulting from the surface steps and the form of contact and through holes required for connection through the insulation layer, so that the increase in wiring density has been limited. For example the contact hole and the first through-hole, or the first through-hole and the second through-hole have to be mutually displaced, and a sufficient line/space width has to be provided against wiring disconnection or migration resulting from the surface steps. In the conventional semiconductor devices as shown in Figs. 2 to 5, there are required very large areas for contact between the semiconductor electrode and the silicon substrate and for the through-hole for connecting the first and second aluminum layers, in order to obtain a sufficiently large flat area, so that a high level of integration has been difficult to achieve. Also wirings with three or more layers have been difficult to realize as the flattening of the entire layer has not be achieved. Also in the conventional coaxial wiring structure as shown in Figs. 6A and 6B, in which the shield is composed of the first Al layer 201, first through-hole 209, second Al layer 202, second through-hole 210 and third Al layer 203, the first through hole 209 and the second through-hole 210 have to be formed in the pattern of the second Al layer 202 as shown in Fig. 7B and have to be mutually displaced. Also the first Al layer 201, first through-hole 209, second Al layer 202, second through-hole 210 and third Al layer 203 have to be so constructed, as shown in Fig. 7, to satisfy a relationship [diameter of first through-hole 209] < [diameter of second through-hole 210]. As will be understood from Figs. 6A, 6B and 8, in the conventional coaxial wiring structure, as the form of the second Al layer 202 is determined by the shapes of the first and second through-holes 209,210, the density of the signal lines is governed by the shield lines composed of the second Al layer 202. Other approaches in the prior art will be mentioned below:- European Patent Application EP-A-0 333 132 describes a semiconductor device having a multilayered wiring structure with a small parasitic capacitance. The structure shown includes a wiring metallisation layer, insulation films and embedded wiring, a further wiring metallisation layer and a connecting member connecting the metallisation layers. The metallisation layers are of aluminium or aluminium containing silicon or the like. Metal is formed in contact hole by electroless plating or a low temperature CVD process. No information is given as to the metal used for the connecting member nor is any information given regarding the CVD process used for this. European Patent Application EP-A-0 288 767 describes a VLSI coaxial wiring structure. In particular the device shown comprises: a substrate, a first insulation layer on the surface of said substrate, a first metal layer on said first insulation layer, a second insulation layer on said first metal layer, plural metal conductors on said second insulation layer, a third insulation layer on said plural metal conductors and the adjacent surface of said second insulation layer,a second metal layer on said third insulation layer, and a plurality of conductive walls spaced from and located in-between adjacent ones of said plural metal conductors connecting said first and second metal layers. The connection walls of the structure are produced in two or more stages. The lower part of the wall may be produced at the same time as the conductor metallisation is deposited as in figure 8 described above. Alternatively, the lower part of the wall may be produced in a separate stage of manufacture to the deposition of conductor metallisation. In the latter case aluminium can be used for the conductor metallisation and another metal such as tungsten can be used for the lower part of the wall. In each case however a portion of the conductor metallisation is retained on the lower portion of the wall and the wall structure is not confined to a single apparatus but intrudes metallisation level. For the reasons given with reference to figure 7, this limits integration density. Japanese Journal of Applied Physics Extended Abstracts of 21st Conference Solid State Devices and Materials (1989), Tokyo Japan, pages 29-32 Sekigachi et al "Epitaxial Growth of Al(100) on Si(100) by Gas-Temperature Controlled Chemical Vapour Deposition" describes a process in which monocrystalline aluminium is grown on a silicon wafer using tri-isobutylaluminium (TIBA) as source vapour. It is suggested that epitaxial aluminium grown using this technique might have application to the production of IC interconnects. In order to resolve the technical drawbacks mentioned above, the object of the present invention is to provide a semiconductor device with an increase wiring density, a semiconductor device enabling aluminium wirings of three or more layers by reducing the area required in the multi-layered aluminium wirings and flattening the surface of each layer, a semiconductor device enabling a coaxial wiring structure of an increased level of integration, and a method for producing such semiconductor devices. Methods for producing semiconductor devices having a multi-level wiring structure or a screened co-axial wiring structure in accordance with the present invention are set out in claims 1 and 2, respectively, of the claims appended. Attention is drawn to the article "Aluminium coatings by the decomposition of alkyls" by H.0. Parson in THIN SOLID FILMS, Vol.45, pages 257-263 (1977) which discusses the coating of steel with aluminium by chemical vapour deposition. EP 0420594, not published at the priority date of the present application, describes the deposition of aluminium from a gas containing alkyl aluminium hydride and hydrogen. The present invention can reduce the area required for multi-layered wirings, by forming a through-hole through plural laminated layers and filling said hole with mono-crystalline aluminium grown by a CVD method utilizing alkylaluminium hydride and hydrogen. Furthermore, the present invention allows use of the second Al layer solely for the signal lines, by employing the Al-CVD method for the shield wirings, thereby forming the signal lines with an increased density and enabling a higher integration level in case of forming a coaxial wiring on the chip. In the accompanying drawings:- Figs. 1A and 1B are schematic views of conventional semiconductor devices; Figs. 2 to 5 are schematic cross-sectional views of conventional two-layered aluminium wiring structures; Figs. 6A, 6B and 7 are schematic views of conventional semiconductor devices; Figs. 8 to 11 are schematic views of continuous metal film forming apparatus adapted for use in the film forming method of the present invention; Figs. 12A to 12D are schematic perspective views showing a film forming procedure of the present invention; Figs. 13A and 13 B are views showing the basic concept of the present invention; Figs. 14A and 14 B are schematic views of a third embodiment of the present invention; Figs. 15A to 15F are views showing the steps for producing the semiconductor device shown in Figs. 14A and 14B; Figs. 16A and 16B are schematic views of a fourth embodiment of the present invention; and Figs. 17A to 17H are views showing the steps for producing the semiconductor device shown in Figs. 17A and 16B. To facilitate a better understanding of the invention, embodiments thereof will be described below. The following description is given by way of example only. In the following there will be given a detailed explanation on the Al-CVD method. There will be principally explained a process of depositing a metal in the apertures by the Al-CVD method and then depositing a metal on the entire surface by sputtering. The following description will be helpful in understanding the excellent selectivity of the Al-CVD method, and the satisfactory quality of interconnecting electrodes produced thereby. (Film forming method) In the following there will be explained a film forming method adapted for use in the formation of electrodes according to the present invention. Said method is adapted for filling an aperture with a conductive material, for forming an interconnecting electrode. Said film forming method consists of forming a deposited film by a surface reaction on an electron donating substrate, utilizing alkylaluminium hydride gas and hydrogen gas (said method being hereinafter called Al-CVD method). An aluminium film of satisfactory quality can be deposited by heating the surface of the substrate in the presence of a gaseous mixture particularly consisting of monomethylaluminium hydride (MMAH) or dimethylaluminium hydride (DMAH) as the raw material gas and hydrogen as the reaction gas. At the selective Al deposition, the substrate surface is preferably maintained at a temperature at least equal to the decomposition temperature of alkylaluminium hydride but lower than 450°C, more preferably between 260°C and 440°C, by direct or indirect heating. The heating of the substrate in the above-mentioned temperature range may be achieved by direct or indirect heating, but formation of an Al film of satisfactory quality can be achieved with a high deposition speed, particularly by direct heating. For example, with the more preferred temperature range of 260° - 440°C, a satisfactory film can be obtained with a deposition speed of 30-500nm/min (300-5000 Å/min) which is higher than in the resistance heating. Such direct heating (substrate being heated by direct transmission of energy from the heating means) can be achieved by heating with a lamp such as a halogen lamp or a xenon lamp. Also indirect heating may be achieved for example by resistance heating, conducted by a heat generating member provided in a substrate support member, for supporting the substrate to be subjected to film deposition, provided in a film depositing space. This method, if applied to a substrate having both an electron donating surface area and an electron non-donating surface area, allows to form single crystal of aluminium with satisfactory selectivity solely on the electron donating surface area. Such aluminium is excellent in all the properties required for the electrode material, including a low hillock frequency and a low alloy spike frequency. This is presumably because the semiconductive or conductive surface constituting the electron donating surface can selectively develop an aluminium film of satisfactory quality and excellent crystalline character of said Al film excludes or significantly reduces the alloy spike formation etc. resulting from an eutectic reaction with the underlying silicon. Such Al film, when employed as an electrode of a semiconductor device, provides advantages far exceeding the concept of the conventional Al electrode and not anticipated in the prior technology. As explained above, the Al deposited in an aperture with an electron donating surface, for example an aperture formed in an insulating film and exposing the surface of a semiconductor substrate therein, has a monocrystalline structure. Besides said Al-CVD method can achieve selective deposition of metal principally composed of aluminum, with likewise satisfactory quality. For example, the electrode may be formed by selective deposition of various conductive materials such as Al-Si, Al-Ti, Al-Cu, Al-Si-Ti or Al-Si-Cu by the use of a mixed gaseous atmosphere employing, in addition to alkylaluminium hydride gas and hydrogen, a suitable combination of: Si-containing gas such as SiH 4 , Si 2 H 6 , Si 3 H 8 , Si(CH 3 ) 4 , SiCl 4 , SiH 2 Cl 2 or SiHCl 3 ; Ti-containing gas such as TiCl 4 , TiBr 4 or Ti(CH 3 ) 4 ; and/or Cu-containing gas such as copper bisacetylacetonate Cu(C 5 H 7 O 2 ) 2 , copper bisdipyvaloylmethanite Cu(C 11 H 19 O 2 ) 2 or copper bishexafluoroacetylacetonate Cu(C 5 HF 6 O 2 ) 2 . Examples of such metal films include combinations of selectively deposited Al, Al-Si, Al-Ti, Al-Cu, Al-Si-Ti or Al-Si-Cu and non-selectively deposited Al, Al-Si, Al-Ti, Al-Cu, Al-Si-Ti or Al-Si-Cu. Said non-selective film deposition may be achieved by CVD other than the aforementioned Al-CVD, or by sputtering. (Film forming apparatus) In the following there will be explained a film forming apparatus suitable for the electrode formation according to the present invention. Figs. 8 to 10 schematically illustrate a continuous metal film forming apparatus suitable for executing the film forming method explained above. As shown in Fig. 8, said apparatus is composed of a loading chamber 311, a CVD reaction chamber (first film forming chamber) 312, an Rf etching chamber 313, a sputtering chamber (second film forming chamber) 314 and an unloading chamber 315, which are rendered sealable from the external atmosphere and mutually communicatable by means of gate valves 310a - 310f and can be respectively made vacuum or reduced in pressure by vacuum systems 316a - 316e. The loading chamber 311 is used for eliminating the atmosphere of substrate and replacing it with H 2 prior to the deposition, in order to improve the throughput. The next CVD reaction chamber 312, for selective deposition onto the substrate under normal or reduced pressure, is provided therein with a substrate holder 318 with a resistance heater 317 for heating the substrate surface subjected to film formation at least within a temperature range of 200° - 450°C, and receives the raw material gas such as of alkylaluminum hydride, which is gasified by bubbling with hydrogen in a bubbler 319-1, through a raw material gas supply line 319, and hydrogen as the reaction gas through a gas line 319'. The Rf etching chamber 313, for cleaning (etching) of the substrate surface in Ar atmosphere after the selective deposition, is provided therein with a substrate holder 320 capable of heating the substrate at least within a range of 100° - 250°C and an Rf etching electrode line 321, and is connected to an Ar gas supply line 322. The sputtering chamber 314, for non-selective deposition of a metal film by sputtering in Ar atmosphere, is provided therein with a substrate holder 323 to be heated at least within a range of 200° - 250°C and a target electrode 324 for mounting a sputtering target 324a, and is connected to an Ar gas supply line 325. The final unloading chamber 315, for adjustment of the substrate after metal film deposition and prior to the exposure to the external atmosphere, is designed to be capable of replacing the atmosphere with N 2 . Fig. 9 shows another example of the continuous metal film forming apparatus, wherein same components as those in Fig. 2 are represented by same numbers. The apparatus in Fig. 9 is different from that in Fig. 8 in that the substrate surface is directly heated by halogen lamps 330, and, for this purpose, the substrate holder 312 is provided with projections 331 for supporting the substrate in a floating state. Direct heating of the substrate surface with such structure further increases the deposition speed as explained before. The continuous metal film forming apparatus of the above-explained structure is equivalent, in practice, to a structure shown in Fig. 10, in which the loading chamber 311, CVD reaction chamber 312, Rf etching chamber 313, sputtering chamber 314 and unloading chamber 315 are mutually combined by a transport chamber 326. In this structure, the loading chamber 311 serves also as the chamber 315. In said transport chamber 326, there is provided an arm 327 constituting transport means, rotatable in both directions A-A and extendable and retractable in direction B-B, whereby the substrate can be transferred in succession from the loading chamber 311 to the CVD reaction chamber 312, Rf etching chamber 313, sputtering chamber 314, and finally to the unloading chamber 315 without exposure to the external atmosphere, as indicated by arrows in Fig. 4. (Film forming process) Now there will be explained the film forming process for forming interconnecting electrodes according to the present invention. To simplify explanation reference will be made to a single insulation film, it being understood that in this invention each aperture is through plural insulation films. Figs. 12A to 12D illustrating the film forming procedure for forming the electrodes and wirings according to the present invention, in schematic perspective views. At first the outline of the procedure will be described. A semiconductor substrate with an insulating film having apertures therein is placed in the film forming chamber, and the surface thereof is maintained for example at 260° - 450°C. Thermal CVD conducted in a mixed atmosphere of DMAH gas as alkylaluminum hydride and hydrogen gas causes selective deposition of Al on the semiconductor exposed in the apertures. There may naturally be conducted selective deposition of a metal film principally composed of Al, for example Al-Si, by introduction for example of Si-containing gas, as explained before. Then a metal film composed solely or principally of Al is non-selectively formed by sputtering, on the selectively deposited Al and on the insulation film. Subsequently the non-selectively deposited metal film is patterned into the shape of desired wirings, thereby obtaining the electrodes and the wirings. This procedure will be explained in greater details with reference to Figs. 9 and 12A to 12D. At first prepared is a substrate, consisting for example of a monocrystalline silicon wafer bearing thereon an insulation film, in which apertures of different sizes are formed. Fig. 12A schematically shows a part of said substrate, wherein shown are a monocrystalline silicon substrate 401 constituting a conductive substrate; a thermal silicon oxide film 402 constituting an insulation film; and apertures 403, 404 of different sizes. The formation of Al film, constituting a wiring layer, on the substrate is conducted in the following manner, with the apparatus shown in Fig. 9. At first the above-explained substrate is placed in the load lock chamber 311, in which a hydrogen atmosphere is established by introduction of hydrogen as explained before. Then the reaction chamber 312 is evacuated by the vacuum system 316b approximately to 1 x 10 -6 Pa (1 x 10 -8 Torr), though Al film formation is still possible with a higher pressure. Then DMAH gas obtained by bubbling is supplied from the gas line 319, utilizing H 2 as the carrier gas. Also hydrogen as the reaction gas is introduced from the second gas line 319', and the interior of the reaction chamber 312 is maintained at a predetermined pressure, by the adjustment of an unrepresented slow leak valve. A typical pressure is about 2.0 x 10 2 Pa (1.5 Torr). DMAH is introduced into the reaction chamber from the DMAH line, with a total pressure of about 2.0 x 10 2 Pa (1.5 Torr) and a DMAH partial pressure of about 0.67 Pa (5.0 x 10 -3 Torr). Then the halogen lamps 330 are energized to directly heat the wafer, thereby causing selective Al deposition. After a predetermined deposition time, the DMAH supply is interrupted. Said deposition time is so selected that the Al film on Si (mono-crystalline silicon substrate 1) becomes equally thick as SiO 2 (thermal silicon oxide film 2), and can be experimentally determined in advance. In this process, the substrate surface is heated to ca. 270°C by direct heating, and the procedure explained above causes selective deposition of an Al film 405 in the aperture, as shown in Fig. 14B. The foregoing is called a first film forming step for forming an electrode in an aperture. After said first film forming step, the CVD reaction chamber 312 is evacuated, by the vacuum system 316b, to a pressure not exceeding 0.67 Pa (5 x 10 -3 Torr). Simultaneously the Rf etching chamber 313 is evacuated to a pressure not exceeding 6.7 x 10 -4 Pa (5 x 10 -6 Torr). After confirmation of said evacuations of the chambers, the gate valve 310c is opened, then the substrate is moved from the CVD reaction chamber 312 to the Rf etching chamber 313 by the transport means, and said gate valve is closed. The Rf etching chamber 313 is evacuated to a pressure not exceeding 10 -4 Pa (10 -6 Torr), and is then maintained in argon atmosphere of 10-10 -1 Pa (10 -1 - 10 -3 Torr) by argon supply from the supply line 322. The substrate holder 320 is maintained at ca. 200°C, and an Rf power of 100 W is supplied to the Rf etching electrode 321 for about 60 seconds to generate an argon discharge in said chamber 313, whereby the substrate surface is etched with argon ions and the unnecessary surfacial layer of the CVD deposition film can be eliminated. The etch depth in this case is about 10nm (100 Å), corresponding to the oxide film. Said surface etching, of the CVD deposition film, conducted in the Rf etching chamber, may be dispensed with since said surfacial layer is free from oxygen etc. as the substrate is transported in vacuum. In such case, the Rf etching chamber 313 may serve for varying the temperature within a short time if the temperature is significantly different between the CVD reaction chamber 312 and the sputtering chamber 314. After said Rf etching, the argon supply is terminated, and the Rf etching chamber 313 is evacuated to 5 x 10 -4 pa (5 x 10 -6 Torr). Then the sputtering chamber is also evacuated to 5 x 10 -4 Pa (5 x 10 -6 Torr) or lower, and the gate valve 310d is opened. The substrate is transferred from the Rf etching chamber 313 to the sputtering chamber 314 by the transport means, and said gate valve 310d is closed. Subsequently the sputtering chamber is maintained at argon atmosphere of 10-10 -1 Pa (10 -1 - 10 -3 Torr) as in the Rf etching chamber 313, and the substrate holder 323 is maintained at 200° - 250°C. Argon discharge is induced by a DC power of 5 - 10 kW to scrape the target of Al or Al-Si (Si: 0.5%) with argon ions, thereby depositing Al or Al-Si onto the substrate with a deposition speed of ca. 1000nm/min (10000 Å/min). This is a non-selective deposition step, and is called a second film forming step for forming wirings connected to the electrodes. After the formation of the metal film of about 500nm (5000 Å) on the substrate, the argon supply and the DC power application are terminated. The load lock chamber 311 is evacuated to a pressure of 5 x 10 -1 Pa (5 x 10 -3 Torr) or lower, then the gate valve 310e is opened and the substrate is moved. After the gate valve 310e is closed, the load lock chamber 311 is supplied with nitrogen gas to the atmospheric pressure. Subsequently the gate valve 310f is opened and the substrate is taken out. The second Al film deposition step explained above forms an Al film 406 on the SiO 2 film 402, as shown in Fig. 12C. Subsequently said Al film 406 is patterned as shown in Fig. 12D to obtain the wirings of desired shape. (Experimental examples) In the following there will be shown experimental results indicating the superiority of the above-explained Al-CVD method and the satisfactory quality of the Al film deposited by said method in the apertures. There were prepared plural substrates, each consisting of an N-type monocrystalline silicon wafer, provided thereon with a thermally oxidized SiO 2 film of a thickness of 800nm (8000 Å), in which apertures of different sizes from 0.25 x 0.25 µm to 100 x 100 µm were formed by patterning to expose the underlying monocrystalline silicon (samples 1-1). These samples were subjected to the Al film formation by the Al-CVD method, employing DMAH as the raw material gas and hydrogen as the reaction gas, with a total pressure of 2.0x10 -2 Pa (1.5 Torr) and a DMAH partial pressure of 6.7 x 10 -1 Pa (5.0 x 10 -3 Torr), and with the substrate surface temperatures selected in a range of 200° - 490°C by direct heating under the regulation of electric power supplied to the halogen lamps. The obtained results are summarized in Table 1. As will be apparent from Table 1, aluminium was deposited in the apertures with a deposition speed as high as 300-500nm/min (3000 - 5000 Å/min) at the substrate surface temperature of 260°C or higher obtained by direct heating. The Al film in the apertures, obtained in a substrate surface temperature range of 260° - 440°C, showed satisfactory characteristics, with no carbon content, a resistivity of 2.8 - 3.4 µΩcm, a reflectance of 90 - 95 %, a hillock (≧ 1 µm) density of 0 - 10 cm -2 , and an almost zero spike formation (frequency of destruction of 0.15 µm junction). On the other hand, though the film quality obtained in a surface temperature range of 200° - 250°C was somewhat inferior to that obtained in the temperature range of 260° - 440°C, it is considerably better than that obtainable with the conventional technology, but the deposition speed could not exceed 100-150nm/min (1000 - 1500 Å/min) and the throughput was in a relatively low range of 7 - 10 wafer/hr. At the substrate surface temperature equal to or higher than 450°C, the quality of the Al film in the apertures were deteriorated, with a reflectance of 60 % or lower, a hillock (≧ 1 µm) density of 10 - 10 4 cm -2 and an alloy spike formation of 0 - 30 %. In the following there will be explained how the above-explained method can be advantageously applied to the apertures such as contact holes or through-holes. Said method can be advantageously applied to the contact holes or through-holes composed of the materials explained in the following. The Al film formation was conducted on the following substrates (samples) under the same conditions as in the Al film formation on the above-mentioned samples 1-1. Samples 1-2 were prepared by forming, on monocrystalline silicon constituting a first substrate surface material, a silicon oxide film constituting a second substrate surface material by means of CVD method, and forming apertures by a photolithographic process to locally expose the surface of monocrystalline silicon. The SiO 2 film was 800nm (8000 Å) thick, and the apertures were sized from 0.25 x 0.25 µm to 100 x 100 µm. (Such sample will hereinafter be represented as "CVD SiO 2 (or simply SiO 2 )/monocrystalline silicon".) There were also prepared: a sample 1-3 of boron-doped oxide film formed by normal pressure CVD (hereinafter written as BSG)/monocrystalline silicon; a sample 1-4 of phosphorus-doped oxide film formed by normal pressure CVD (PSG)/monocrystalline silicon; a sample 1-5 of boron- and phosphorus-doped oxide film formed by normal pressure CVD (BSPG)/monocrystalline silicon; a sample 1-6 of nitride film formed by plasma CVD (P-SiN)/monocrystalline silicon; a sample 1-7 of thermal nitride film (T-Sin)/ monocrystalline silicon; a sample 1-8 of nitride film formed by low pressure CVD (LP-SiN)/monocrystalline silicon; and a sample 1-9 of nitride film formed by ECD (ECR-SiN)/monocrystalline silicon. Further, samples 1-11 to 1-179 were prepared by taking all the combinations of the first surface materials of 18 kinds and the second surface materials of 9 kinds shown in the following. (It is to be noted that the sample numbers 1-10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 110, 120, 130, 140, 150, 160 and 170 are lacking.) The first surface materials employed were monocrystalline silicon (mono-Si), polycrystalline silicon (poly-Si), amorphous silicon (a-Si), tungsten (W), molybdenum (Mo), tantalum (Ta), tungsten silicide (WSi), titanium silicide (TiSi), aluminium (Al), aluminium silicon (Al-Si), titanium aluminium (Al-Ti), titanium nitride (Ti-N), copper (Cu), aluminium silicon copper (Al-Si-Cu), aluminium palladium (Al-Pd), titanium (Ti), molybdenum silicide (Mo-Si), and tantalum silicide (Ta-Si). The second substrate surface materials employed were T-SiO 2 , SiO 2 , BSG, PSG, BPSG, P-SiN, T-SiN, LP-SiN and ECR-SiN. In all these samples, there could be obtained satisfactory Al films comparable to those in the aforementioned samples 1-1. Subsequently, the Al was non-selectively deposited by sputtering on the substrates subjected to the selective Al deposition as explained above, and was then patterned. The Al film obtained by sputtering and the selectively deposited Al film in the apertures showed electrically and mechanically satisfactory contact, because of the improved surface state of the Al film in the apertures. Fig. 13A is a schematic plan view of a multi-layered wiring structure adapted for use in a semiconductor device and constituting a preferred embodiment of the present invention, and Fig. 13B is a schematic cross-sectional view along a line A-A' in Fig. 13A. On a semiconductor substrate 261 for example of silicon, there are formed plural insulation films such as a first insulation film 257 of SiO 2 and a second insulation film 255 of SiO 2 , and there is also formed a through-hole TH of a size determined according to the thickness of said insulation films. In said through-hole TH, SiO 2 is removed down to the surface of the crystalline substrate 261. Then the Al-CVD method is executed to grow monocrystalline aluminium 262 on said substrate at the bottom, thereby completely filling the interior of the hole TH and forming a metal film constituting a connecting member, for connecting the substrate surface and a second wiring layer (not shown) to be formed above. Also in the area with plural laminated insulation layers as explained above, it is rendered possible to fill a fine and deep hole with an aspect ratio not only of 1.0 but also of 1.5 - 2.0 or even larger, which is difficult to fill in the prior art, by forming a hole penetrating said insulation layers and applying the aforementioned Al-CVD method. Thus the production yield can be significantly improved for a device of which desired performance is achievable with an aspect ratio of 1.5 or larger. Also the obtained connection is free from lateral projection as in the prior art shown in Fig. 4, since, in a three-layered wiring structure, the penetrating hole can be filled by a single deposition process. Thus the connection of the present embodiment reduces the parasitic capacitance resulting from the connecting member for connecting the upper and lower wiring layers, and does not generate surface steps around the connecting area. Furthermore the diameter of hole can be unified to a necessary minimum one, and the formation of the connecting member can be achieved with a deposition and patterning process, with reduced concern for alignment error, in contrast to the prior process requiring two processes of deposition and patterning. Also in a multi-layered wiring structure with three or more wiring layers, obtained by repeating the above-explained procedure, the surface step does not increase cumulatively because the film surface developed in the aperture is substantially flat. The substrate surface mentioned above thus includes an aluminium film or a metal film principally composed of aluminium, constituting a wiring layer. Fig. 14A is a schematic plan view of a semiconductor device constituting another embodiment of the present invention, and Fig. 14B is a cross-sectional view along a line A-A' in Fig. 14A. The producing method for said device will be outlined in the following. At first an aperture CH is formed in a first insulation film, a first wiring layer thereon and a second insulation film thereon, all formed on a substrate surface, in the same manner as shown in Figs. 13A and 13B, then said aperture CH is completely filled by the growth of monocrystalline aluminum 262, and an Aluminium wiring, similar to the second aluminium wiring shown in Figs. 2 - 5, was formed on the second insulation film 255. This method eliminates the necessity of forming, on the SiO 2 film exposed in the aperture, the first Al layer 101 which is inevitable in the prior art as a base for making contact with the second Al layer 102, as shown in Figs. 2 to 5. Also even in case the entire peripheral area of the SiO 2 257 is covered by a first Al layer 251 as shown in Fig. 14A, a connector 262 can be formed to the substrate 261 at the bottom as long as a space for the aperture only is available. The dimensions L13, L14 and L15 in Fig. 17B are respectively 0.6, 0.8 and 2.0 µm, whereas the dimensions L6 in Fig. 4 and L12 in Fig.5 are respectively 4.2 and 3.2 µm. Thus the present embodiment can reduce the area required for wirings, in comparison with the prior art. The present embodiment will be explained further in the following, with reference to Figs. 14A, 14B and 18A to 18F, in which Figs. 15A and 15B illustrate steps of an example of the producing method for said semiconductor device. After the formation of a diffusion layer on a crystalline silicon substrate 801, a first insulation layer 802 of silicon oxide is deposited with a thickness of 800nm (8000 Å) (Fig. 18A). In the present embodiment, said first insulation layer 802 is composed of silicon oxide containing phosphorus and boron, deposited by a normal pressure CVD process. It may however be replaced by silicon oxide containing phosphorus or silicon oxide without impurity. Then, on said first insulation layer 802, an aluminum layer 803 is deposited with a thickness of 800nm (8000 Å) and formed into a predetermined pattern by an ordinary photolithographic process (Fig. 18B). More specifically, aluminium-silicon is deposited by sputtering, and the patterning is conducted by dry etching with Cl 2 -BCl 3 -He. Then a second insulation layer 804 of silicon oxide, doped with phosphorus, is deposited with a thickness of 600nm (6000 Å) by normal pressure CVD (Fig. 18C). Subsequently a contact hole CH 801 of an aspect ratio of 1.0 or larger is opened through the second insulation layer 804 and the first insulation layer 802 (Fig. 15D). In the present embodiment, a photoresist pattern is prepared by a reduction projection exposure apparatus, and dry etching is conducted with CHF 3 -C 2 F 6 . Then the aforementioned Al-CVD method is employed to deposit monocrystalline aluminium in the contact hole CH 801 (Fig. 15E ). In the present embodiment, aluminium-silicon is deposited instead of pure aluminium. There is employed the film forming apparatus shown in Fig. 8, and the film forming conditions were same as explained before, with a film deposition time of ca. 28 minutes. Hereinafter the sample worked up to the state shown in Fig. 15D will be called substrate. Then, on the second insulation layer 804 and the Al-Si film 805, a second aluminium layer 806 is non-selectively deposited by sputtering, and was formed into a desired pattern by an ordinary photolithographic process (Fig. 15F ). In the present embodiment, said patterning was conducted by dry etching with Cl 2 -BCl 3 -He, as in the case of the first aluminium layer 803. A semiconductor device as shown in Fig. 15F could be obtained through the process explained above. The foregoing description has been limited to a semiconductor device employing a mono-crystalline silicon substrate, but a film of satisfactory quality can be obtained also in a device utilizing a substrate of other electron donating materials, such as GaP. Figs. 16A and 16B are respectively a cross-sectional view and a plan view of a coaxial wiring structure of the present invention. On a semiconductor substrate 507 of silicon, there are laminated, in succession, an insulation layer 504 and a first aluminium layer 501 constituting a shield conductive layer. A second aluminium layer 502, used as a signal line, is covered by a third aluminium layer 503, the first aluminium layer 501 and aluminium members 508 deposited selectively in apertures of a high aspect ratio penetrating concentrically insulation layers 505, 506, all these components serving as a shield line. The crosstalk between the signal lines, for example the second aluminium lines 502 and 502A, can be suppressed by the above-explained structure in which each signal line is surrounded by other aluminium components which are connected to a fixed potential such as ground potential. Insulation layers 505, 506 may be composed of an inorganic material such as silicon oxide or silicon nitride, or an organic material, but in particular the insulation layer 506 is preferably composed of silicon oxide formed from tetraethylorthosilicate (TEOS-SiO 2 ). The conductive member 508, capable of connecting the upper and lower wirings through plural insulation layers, can reduce the occupied area and the parasitic capacitance. In addition, because of its substantially flat lateral face, it does not require additional wiring space as shown in Figs. 6A and 7 in the plural insulation layers and reduces the surface step. The occupied area can be particularly reduced, even for a large depth, by selecting an aspect ratio at least equal to 1.0, preferably 1.5 and most preferably 2.0. Figs. 17A to 17H illustrate an example of the producing method of a semiconductor device involving the coaxial wiring structure of the present invention. On a silicon substrate 601 in which diffusion layers etc. already have been formed by an ordinary process for semiconductor device preparation, an interlayer insulation film 602 is deposited to a thickness of 500nm (5000 Å) (Fig. 17A). Said interlayer insulation film 602 is, composed, in the present embodiment, of silicon oxide doped with boron and phosphorous, but it may also be replaced by silicon oxide doped with phosphorus or by undoped silicon oxide. Then, on said insulation layer 602, there is deposited a first aluminium layer 603 for constituting the bottom shield line, with a thickness of 300 nm (3000 Å) (Fig. 17B1). In the present embodiment, said aluminium deposition is conducted by sputtering, but it may also be conducted by electron beam evaporation or by CVD. Then, in thus deposited aluminium layer 603, there is; opened a hole H601 larger than the contact hole, in a position where contact is made between the signal line and the element on the substrate (Fig. 17B2). Figs. 17B2, 17C2 and 17D2 illustrate the aluminium patterning steps in a contact area, achieved by ordinary photolithography employing photoresist and chlorine-based dry etching. Then an interlayer insulation film 604, for separating the aluminium layer 603 constituting the bottom shield line and the signal line, is deposited with a thickness of 600nm (6000 Å) (Fig. 20C1). Said insulation film 604 is composed of phosphorus-doped silicon oxide in the present embodiment, but it may be replaced by undoped silicon oxide. After said deposition, a contact hole CH601 is opened in a position where contact is to be made between the signal line and the element on the substrate (Fig. 17C2), by means of ordinary photolithography employing photoresist and dry etching. The structure up to the states shown in Figs. 17C1 and 17C2 can be obtained by a known technology for semiconductor device manufacture. Subsequently an aluminium-silicon layer 605 is deposited as the signal line. Said deposition may be achieved by sputtering or electron beam evaporation if the contact hole has a certain large size, but, in the present embodiment, selective Al-CVD method and sputtering are employed since the contact hole is as small as 1 x 1 µm. The deposition of aluminium-silicon is conducted with the apparatus shown in Fig. 8 and with the depositing conditions explained before. The deposition of aluminium-silicon up to a thickness of 1100nm (110000 Å) which is equal to the sum of thicknesses of the insulation layers 602, 604, required about 22 minutes. In this operation the substrate surface temperature was maintained at 270°C by direct heating. In this deposition step, the aluminium-silicon was deposited solely in the contact hole CH 601, as shown in Figs. 17D1 and 17D2. Then aluminium-silicon film 605 was deposited and then formed into a predetermined wiring pattern (Fig. 17E ), by ordinary photolithography employing photoresist and chlorine-based dry etching. Subsequently an interlayer insulation film 606, for insulating the signal line 605 from the upper shield line, was deposited with a thickness of 600nm (6000 Å) (Fig. 17F). Said insulation film 606 in the present embodiment was composed of phosphorus-doped silicon oxide formed by CVD utilizing O 3 -TEOS (tetraethyl orthosilicate), and the phosphorus doping was achieved by introducing TMP (tetramethyl phosphorus). The substrate temperature was maintained at 400°C, and the phosphorus content in the insulation film 606 was about 6%. However ordinary CVD based on SH 4 O 2 -PH 3 may also be used for forming the insulation film 606. Then narrow grooves were opened in areas where the lateral faces of the signal line 605 are to be shielded (Fig. 17G ), by ordinary photolithography and dry etching. In the present embodiment, said grooves were formed by forming a photoresist pattern of a width of 0.8 µm by a reduction projection exposure apparatus, and conducting dry etching employing C 2 F 2 -CHF 3 . Finally an aluminium layer 607 was deposited on the upper and lateral faces of the signal line 605, thereby completing the shield (Fig. 17H ). Since said aluminium deposition was of an aspect ratio over 1.0, with a width of 0.8 µm and a depth of 1.2 µm, it could not be achieved for example by sputtering or electron beam evaporation. Consequently the groove filling relied on the selective Al-CVD method. In the present embodiment the lateral and upper faces 607 of the shield line were formed by the Al-CVD method and sputtering, as in the aluminium deposition for the signal line 605. The difference in the formations of the signal line 605 and the shield line 607 lies in a fact that the shield line 607 was composed of pure aluminium without the addition of trimethyl phosphorus during the Al-CVD process and the deposited depth was 1200 nm (12000 Å). After said aluminium deposition, the unnecessary parts of the shield line were removed by ordinary photolithography employing photoresist and chlorine-based dry etching. Effect of the Invention The present invention, based on wiring formation by the Al-CVD technology, makes it possible to obtain flattened surfaces and a higher density in the wirings, thereby reducing the surface area of the semiconductor device required for connection and also reducing the production cost thereof. The present invention reduces the area required for a multi-layered wiring structure and can provide a flatter surface on the semiconductor device, by forming a penetrating hole through plural laminated insulating layers and completely filling said hole by growing monocrystalline aluminium therein by the Al-CVD method, whereby there can be obtained a semiconductor device extremely suitable for achieving a high level of integration. Furthermore application of the present invention allows an increase in the density of signal lines in a coaxial wiring structure, thereby achieving a higher level of integration in forming such coaxial wirings on a chip.

Claims: A method for producing a semiconductor device having a multi-layered wiring structure provided with a first insulation film (257;802) provided on the surface of a substrate (261;801), a first, patterned, wiring layer (251;803) provided on said first insulation film (257;802), a second insulation film (255;804) provided so as to cover said first wiring layer (251;803), and a second wiring layer (252;806) provided on said second insulation film (255;804) comprising the steps of: forming an aperture (CH;CH801) penetrating said first and second insulation films at a point at which the first wiring layer (251;803) is absent, thereby exposing the surface of said substrate (261;801); depositing selectively aluminium or a metal principally composed of aluminium in said aperture (CH;CH801) by a CVD method utilizing alkylaluminium hydride gas and hydrogen, with the substrate maintained at a temperature higher than the decomposition temperature of the alkylaluminium gas but below 450°C, thereby selectively forming a connection member (262;805) for connecting the surface of said substrate (261;801) and said second wiring layer (252;806); and depositing non-selectively a metal film (252;806) on said aluminium or metal connection member (262;805) and said second insulating film (255;804), and then patterning said metal film (252;806), thereby forming said second wiring layer (252;806). A method for producing a semiconductor device comprising the steps of: depositing a first insulation layer (504;602) on a substrate (507;601); depositing a first metal layer (501;603) on said first insulation layer (504;602); depositing a second insulation layer (505;604) on said first metal layer (501;603); depositing a second metal layer (502;605) on said second insulation layer (505;604); patterning said second metal layer (502;605) into a predetermined form (502;502A;605); depositing a third insulation layer (506;606) on said second insulation layer (505;604) and said second metal layer (502;605); opening in said second and third insulation layers (505,506) holes spaced from said second metal layer (502;605) by a predetermined distance and reaching said first metal layer (501;603); depositing selectively aluminium or a metal (508;607) principally composed of aluminium by a CVD method utilizing alkylaluminium hydride and hydrogen with the substrate maintained at a temperature higher than the decomposition temperature of the alkylaluminium gas, but below 450°C. to fill said holes; depositing non-selectively a metal (503) on said third insulation film (506;606) and said aluminium or metal principally composed of aluminium (508; 607); and patterning the metal (503;607). A method according to claims 1 or 2 wherein the selective deposition of the aluminium or metal is performed within a first chamber, and then, without exposing to an atmosphere, said substrate is moved into a second chamber, and the non-selective deposition of the metal is performed within the second chamber. A method for producing a semiconductor device according to any one of claims 1 to 3 wherein said aperture has an aspect ratio of 1.5 or larger. A method according to any one of claims 1 to 4 wherein the selectively deposited metal is selected from Al-Si, Al-Ti, Al-Cu, Al-Si-Ti, and Al-Si-Cu. A method according to any one of claims 1 to 5 wherein the non-selectively deposited metal is selected from Al, Al-Si, Al-Ti, Al-Cu, Al-Si-Ti, and Al-Si-Cu.

Inventors: ASABA TETSUO, ICHISE TOSHIHIKO, IKEDA OSAMU, INOUE SHUNSUKE, MATSUMOTO SHIGEYUKI, MUROOKA FUMIO, SAKASHITA YUKIHIKO, ASABA, TETSUO, ICHISE, TOSHIHIKO, IKEDA, OSAMU, INOUE, SHUNSUKE, MATSUMOTO, SHIGEYUKI, MUROOKA, FUMIO, SAKASHITA, YUKIHIKO, ASABA, TETSUO, CANON KABUSHIKI KAISHA, ICHISE, TOSHIHIKO, CANON KABUSHIKI KAISHA, IKEDA, OSAMU, CANON KABUSHIKI KAISHA, INOUE, SHUNSUKE, CANON KABUSHIKI KAISHA, MATSUMOTO, SHIGEYUKI, CANON KABUSHIKI KAISHA, MUROOKA, FUMIO, CANON KABUSHIKI KAISHA, SAKASHITA, YUKIHIKO, CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1991
Main classification: H01L21
IPC codes: H01L21, H01L23