A monolithic semiconductor device and associated manufacturing process

Abstract: By using a diffused insulation region placed around the body region and with deeper junction and hence longer curvature radius than the typical body/drain junction values, in combination with an appropriate layout of the buried drain region underneath the power stage, breakdown voltage is maximized without compromising the Ron series resistance of the power stage and the reliability of the device.

Description: Field of the Invention The object of the present invention is the termination of the power stage of a monolithic semiconductor device including an integrated control circuit and one or more vertical current flow MOS power transistors integrated in the same chip and the associated manufacturing process. Background of the Invention Association in the same chip of vertical current flow MOS power transistors and an integrated control circuit provides a very compact and efficient device which is advantageous compared with separate components. A recurring problem in providing such a device is maximization of the breakdown voltage, which is a decreasing function of the dopant concentration in the power stage drain region and an increasing function of the curvature radius of the body/drain junction thereof. At present the problem is solved by appropriate terminations of the junction, such as dielectric and/or metallic field plates, floating rings, low dopant concentration regions, etc. A review of these techniques can be found in "Physics of semiconductor devices" by A. Blicher, Rep. Prog. Phys., Vol. 45, 1982, pages 446-450. The limits of these solutions are essentially that a) the termination region extends for distances even greater than 100 microns and this involves considerable waste of area, b) other manufacturing phases are added to the process and the cost of the device is thus increased, and c) the surface electric field is equal to, if not greater than, the electric field at the junction and, consequently, the reliability of the structure is poor (the process of passivation and/or encapsulation of the device can further reduce breakdown voltage). Objects of the Invention The termination of the power stage in accordance with the present invention overcomes the above shortcomings and in articular maximizes the breakdown voltage without compromising the Ron series resistance of the power stage and the reliability of the device. Summary of the Invention A monolithic semiconductor device according to the present invention is defined in claim 1. A manufacturing process of a monolithic semiconductor device is defined in claim 2. Brief Description of the Drawings The invention will be further clarified by the description given below and the annexed drawings of an example of the known art and nonlimiting examples of embodiments of the invention in which: FIG.1 shows an example of the structure of a semiconductor device in accordance with the known art, FIGS.2-4 show phases of a process in accordance with the invention, FIG.5 shows the semiconductor device resulting from the process of FIGS. 2-4, and FIGS.6-7 show structures of other examples of embodiments of the power stage in accordance with the invention. Specific Description FIG.1 shows a possible structure of a known semiconductor device including a control circuit and one or more vertical current flow MOS transistors integrated in a monolithic manner in the same chip. For the sake of simplicity a single component of the integrated control circuit (a low voltage npn transistor) and a single MOS power transistor are shown. In said figure the meanings of the various parts are as follows: 20,35: drain and source electrodes of the MOS transistor; 34: gate polycrystalline silicon; 24,28: insulation regions; 31,32,33: collector, base and emitter of the control circuit transistor. In said device the breakdown voltage is limited by the minimum values which the curvature radius of the body/drain junction takes on along the periphery thereof, values which are typically on the order of 3-4 microns. An example of a possible embodiment of a power stage termination in accordance with the present invention is illustrated in FIG. 5. Said FIG. shows that to the body region 15 of the power stage is "welded" a diffused insulation region 9 with the same type of conductivity but with deeper junction and hence greater curvature radius Xj than the body junction would have at the edges without said region 9. The increase in breakdown voltage which results is particularly sensitive (by a factor greater than or equal to 2 if we go for example from Xj = 3 microns to Xj = 12 microns). The same FIG. shows that the minimum distance d1 between the buried drain region 6 and the region 9 is not less than the minimum distance d2 of said buried region 6 from the overlying junction 10 between body and drain. This condition must be respected if it is desired that the breakdown voltage be determined by d2 and not by d1. There is now described with reference to FIGS. 2, 3 and 4 an example of a manufacturing process for the structure of FIG. 5. On a substrate 1 of n+ type monocrystalline silicon is implanted opposite the region 2 of FIG. 2 high diffusivity coefficient dopant with the same type of conductivity as the substrate. Then follow epitaxial growth of the n type layer 3 and formation, by diffusion of the dopant previously implanted, of n+ type region 2 designed to constitute a first buried drain region with high dopant concentration, necessary to reduce the Ron of the power stage. By known art there is then created a type p+ region 4 extending inside the layer 3 and designed to constitute the horizontal insulation region of the control circuit (FIG. 2). At this point there are provided, by implantation and diffusion processes, two n+ type regions 5 and 6, the first of which, a buried collector region, is located in the region 4 and is necessary to reduce the collector series resistance of the control circuit transistors, and the second of which (also useful for reducing the Ron of the power stage and designed to constitute a second buried drain region with high dopant concentration) over the region 2, as illustrated in FIG. 3. Then there is grown a second n type epitaxial layer 7 and subsequently, again by known art, type p+ regions 8 and 9 are provided. The regions 8 are used to insulate the components of the control circuit from each other and from the power stage while the regions 9 define the perimeter of the power stage (FIG. 4). At this point follow, by known techniques, the realisation of the control circuit components (bipolar and/or MOS) and of the power stage components (MOS), and in particular the realisation of the regions 12 (collector sink), 13 (base) and 14 (emitter) of the low voltage npn transistor as well as the realisation of the regions 15 (body) and 16 (source), the deposition of polycrystalline silicon to create the region 17 (gate) and finally opening of the contacts, of which only the source contact IS is shown in FIG. 5. In the creation of the body region 15, the body/drain junction 10 (see FIG. 5) of the MCS power transistor must be made to connect with the region 9 described above so as to obtain the structure of FIG. 5. The process described does not cause any added cost over the process used for the manufacture of a device in accordance with the known art of FIG. 1. Indeed, it suffices to simply arrange a different layout of the insulation photomasking because the implantation and diffusion are not changed from the standard process nor are other phases added. The length of the termination provided by the region 9 is equal to the sum of the side diffusion of the insulation region, its photcmasking opening, and the misalignment tolerance, hence less than 2C microns total. It is noted that, differently from known structures, the structure in accordance with the present invention allows optimization of the operating voltage without changing the power stage Ron. It is clear that numerous variants and/or modifications can be made in the process in accordance with the invention without thereby going beyond the scope thereof. For example, the region 2 can be formed using the techniques described in European Patent Application No.91200853.9 published as EP-A-0 453 026, falling under Art 54(3) EPC, or formation of the region 6 can be omitted if the device is to operate at medium or high voltage as exemplified in FIG. 6. Extending the basic concept of the present invention the horizontal insulation region 19 can be used in addition to the insulation regions 9 to further increase the junction curvature radius up to values greater than 20-25 microns (see FIG. 7) to allow operation of the device at voltages higher than several hundred volts without recourse to other structures for the termination. In this case also the added cost of the process is null because it suffices to adjust the horizontal insulation photomasking layout. It is noted that the peripheral insulation region 9 of FIGS. 5 and 6 and the insulation regions 9 and 19 of FIG. 7 are to be understood as contour regions of the entire MOS power transistor, which is generally made up of numerous elementary cells. Therefore only those elementary cells at the edges of the area occupied by the MOS have body regions joining with the insulation region 9; for the sake of simplicity, only the elementary cells at the edge of the MOS transistor are shown in FIGS. 5, 6 and 7.

Claims: A monolithic semiconductor device including an integrated control circuit and at least a vertical current flow MOS power transistor integrated in the same chip as well as a buried drain region which is buried in a drain region and has a relatively high dopant concentration with respect to the drain region, the MOS transistor being made up of numerous elementary cells occupying an area of the chip, and the buried drain region being positioned underneath the body regions of said elementary cells, wherein the body region (15) of each elementary cell placed at the edges of said area joins with a peripheral insulation region (9) surrounding said area and has the same type of conductivity as the peripheral insulation region; the junction of the peripheral insulation region is deeper than the junction of the body region of every elementary cell; the minimum distance (d2) of the body/drain junction (10) of every elementary cell from the underlying buried drain region (6) is less than or equal to the minimum distance (d1) of the buried drain region (6) from the peripheral insulation region (9). Manufacturing process of a monolithic semiconductor device according to claim 1 comprising the steps: forming in a first epitaxial layer (3) deposited on the substrate (1) of the chip a first region (4) with conductivity of a type opposed to that of the substrate and designed to constitute the horizontal insulation region of the control circuit, and depositing a second epitaxial layer (7), realising in the seconds epitaxial layer (7) a second region and a peripheral insulation region (8,9) with conductivity of a type opposed to that of the substrate, the second region (8) joining with the horizontal insulationn region (4) of the control circuit and peripheral insulation the region (9) being allocated and formed in such a manner as to constitute a peripheral insulation region surrounding said area, and realizing, in the second epitaxial layer (7), the components of the control circuit and said elementary cells of the MOS transistor in such a manner that: the body region (15) of each elementary cell placed at the edges of said area joins with said peripheral insulation region (9); the junction of the peripheral insulation region (9) is deeper than the junction of the body region of every elementary cell: the minimum distance (d2) of the body/drain junction (10) of every elementary cell from the underlying buried drain region (6) is less than or equal to the minimum distance (d1) of the buried drain region (6) from the peripheral insulation region (9). Manufacturing process according to Claim 2 comprising forming simultaneously with the formation of the region (4), a fourth region (19) in the first epitaxial layer (3), with annular shape and conductivity of a type opposed to that of the substrate and allocated and formed in such a manner as to constitute a region surrounding the area reserved for the elementary cells of the MOS tansistor; said peripheral insulation region (9) is allocated and formed in such a manner to join below with the aforesaid fourth region (19); the elementary cells of the MOS transistor are realized in the second epitaxial layer (7) in such a manner that the minimum distance (d1) between the buried drain region (2) and the entirety of the peripheral insulation and fourth regions (9,19) is not less than the minimum distance (d2) of said buried drain region (2) from the overlying body/drain junctions (10) of each elementary cell.

Inventors: GRIMALDI ANTONIO, ZAMBRANO RAFFAELE, GRIMALDI, ANTONIO, ZAMBRANO, RAFFAELE
Applicants: CONS RIC MICROELETTRONICA, SGS THOMSON MICROELECTRONICS, CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO, SGS-THOMSON MICROELECTRONICS S.R.L.
Application year: 1991
Main classification: H01L27
IPC codes: H01L27, H01L21, H01L29