A digital quadrature phase detection circuit

Abstract: An analog quadrature-modulated signal is converted into a digital signal by an A/D converter (1) using a sampling clock having a frequency four times higher than the carrier of the quadrature modulated signal. The digital signal is delayed by one sampling slot in each of four delay circuits (2-5) connected in series to the A/D converter. The output of the A/D converter and that of the fourth delay circuit are multiplied by -1/2 by respective digital weighting circuits (6,7), and the multiplied outputs together with the output of the second delay circuit are added together in an adder (8) to generate an I component (in-phase) signal. The output of the first delay circuit is multiplied by -1 by another weighting circuit (10) and this multiplied output and the output of the third delay circuit are added together in another adder (11) to generate a Q component (quadrature phase) signal. The I and Q signals are held in latches (9,12) clocked at one quarter of the sampling clock rate.

Description: This invention relates to a phase detection circuit that detects the phase changes of a phase-modulated signal and derives an in-phase component level (I signal) and a quadrature component level (Q signal) of the input signal relative to a reference signal. Quadrature detectors are conventionally used as a means of detecting phase changes of a high-frequency signal. One example is to be found in United States Patent US-A-4 849 991 (Arnold et al), see especially Figures 2 and 2A thereof. This patent describes a circuit for determining symbol timing for time division multiple access (TDMA) radio systems, which includes an A/D (analog to digital) converter clocked at a sampling rate which is a multiple of the symbol rate by at least a factor of four and preferably a factor of sixteen, this being four times the frequency of the received IF signal. The converter output is applied to a five-stage shift register (Fig.2A). A first adder forms a weighted addition of the stages in the proportions (1,0,-2,0,1) and a second adder forms a weighted addition of the stages in the proportions (0,2,0,-2,0). The inverted and non-inverted outputs of these adders are applied to two four-input multiplexers, which provide I and Q outputs. These are applied to an arc-tangent look-up ROM which outputs a phase value. With a sampling rate of sixteen times the symbol rate, the selected sample for demodulation can be chosen to be close to the desired sampling instant, by no more than 1/32 of a symbol period. United States Patent US-A-4 606 051 (Crabtree et al) describes a quadrature phase-shift keying demodulator which has an A/D converter connected to a tapped delay line. The signals are sampled at four times the carrier frequency, or three times the bit rate. The delay line has two groups of alternating signal taps which are multiplied by coefficients and the resultants summed to produce in-phase and quadrature components. The relative magnitude of these two components is used to determine the phase angle. United States Patent US-A-4 800 575 (Anderson) describes a frequency shift keying demodulator of somewhat similar construction. The invention provides a digital quadrature-phase detector circuit comprising: A/D converter means for converting an analog phase-modulated signal into a digital signal at a sampling rate determined by a clock signal having a frequency n times the carrier frequency of the analog signal, n being a positive integer; a plurality of n delay means connected in series to the output of the A/D converter means and numbered counting from the A/D converter means, each delay means delaying an input thereto by one period of the clock signal to provide an output therefrom; a plurality of weighting means for relatively weighting the said digital signal and the outputs of the plurality of delay means to provide weighted signals; first adder means for adding the weighted digital signal and the weighted outputs of even-numbered delay means; and second adder means for adding the weighted outputs of odd-numbered delay means; characterised by first and second latching means for respectively latching the outputs of the first and second adder means in synchronization with a latching signal having a period m times longer than the period of the clock signal, m being a positive integer, to produce in-phase and quadrature components of the phase-modulated signal, in which n = m and n >1. The invention also provides a method of detecting a analog phase-modulated signal to produce its in-phase and quadrature components, the method comprising the steps of: converting the analog phase-modulated signal into a digital signal in synchronization with a clock signal having a frequency n times higher than the carrier frequency of the phase-modulated signal, n being a positive integer; sequentially delaying the digital signal n times each by one period of the clock signal; weighting the digital signal and the signals delayed 2 p -times with a first set of predetermined weighting factors to produce a first set of weighted signals, p being 1, 2, ... n /2; weighting the signals delayed (2 p -1)-times to produce a second set of weighted signals; adding the first set of weighted signals to produce a first added signal; and adding the second set of weighted signals to produce a second added signal; characterised by latching the first and second added signals with a latching signal having a period m times longer than the period of the clock signal to produce the I and Q components, respectively, where n = m and n >1. A preferred embodiment of the apparatus and method of the invention, described below with reference to the drawing, incorporates an A/D converter using a sampling clock having a frequency four times higher than the carrier of the quadrature-modulated signal ( n = 4). The digital signal is delayed by one sampling slot in each of four delay circuits connected in series to the A/D converter. The output of the A/D converter and that of the fourth delay circuit are multiplied by -1/2 by respective digital weighting circuits, and the multiplied outputs together with the output of the second delay circuit are added together in an adder to generate an I component (in-phase) signal. The output of the first delay circuit is multiplied by -1 by another weighting circuit, and this multiplied output and the output of the third delay circuit are added together in another adder to generate a Q component (quadrature phase) signal. The I and Q signals are held in latches which are clocked at one quarter of the sampling clock rate ( m = 4). The invention will now be described in more detail, by way of example, with reference to the drawing, in which the sole figure, referred to as FIG.1, is a block diagram illustrating a preferred phase detection circuit embodying the present invention. In FIG.1, an A/D (analog to digital) converter 1 converts an input signal S1 to a digital signal S2 in synchronization with a sampling clock C having a frequency n times, in this case four times, higher than the carrier frequency of signal S1. The digital signal S2 is delayed by one sampling cycle of clock C by n (four) delay circuits 2, 3, 4 and 5, respectively, which output respective delayed signals S3, S4, S5, and S6. The digital signal S2 is weighted by a weighting factor of -½ at a weighting circuit 6 to become a signal S7. The output S6 of the fourth delay circuit 5 is weighted by a weighting factor of -½ at a weighting circuit 7 to become a signal S8. The outputs S7 and S8 in addition to the output S4 of the second delay circuit 3 are added by a first adder 8, the output of which (S9) is latched in a first output latching circuit 9 at a cycle m times, also in this case four times, longer than the sampling clock cycle. This latching cycle clock is obtained by dividing the sampling clock C at a divider 13. The latched signal is outputted as an I signal (in-phase component level). In addition, a weighting circuit 10 weights the output S3 of the first delay circuit 2 with a weighting factor of -1 to reverse the polarity of same and thereby to produce an output S10. The output S10 and the output S5 of the third delay circuit 4 are added by a second adder 11. The output of the second adder 11 is then latched in a second output latching circuit 12 at the latching cycle provided from the divider 13. This latched signal is outputted as a Q signal (quadrature component level). More generally, one can say that the digital signal from the converter 1 and the 2 p time delayed signals (where p is 1,2, ... n /2) are combined in adder 8 with a first set of predetermined weighting factors, and the (2 p -1) time delayed signals are combined in adder 11 with a second set of predetermined weighting factors. The above-described operation can be described by the following mathematical expressions. Let the input signal S1 be: × = Acos (ω c t + ) + v and let the sampling timing within the A/D converter 1 be: t = nT where: ω c = the angular frequency of the carrier of the input signal S1 (radians/sec) t = time (sec)  = the phase of input signal S1 (radians) v = the DC off-set n = -∞, ..., -2, -1, 0, 1, 2, ..., ∞ T = 2π/4ω c : the sampling cycle (with the sampling frequency 4-times higher than the carrier frequency) According to the above definitions, the signals S2, S3, S4, S5, and S6 are respectively expressed as: If we now let n = 4m+k, where: m = -∞, ..., -2, -1, 0, 1, 2, ..., ∞ and k = 0, 1, 2, 3, then the expressions (5) become: Substituting the expression (4) into the expressions (6) and allowing the latching timing in the output circuits 9 and 12 to be at the time when k=2, then each delay signal can be expressed as: which simplify to: Accordingly, the values that are latched within the output latching circuits 9 and 12 are: I = -S2/2 + S4 - S6/2 = -(Acos()+v)/2 + Acos()+v - (Acos()+v)/2 = 2Acos() Q = -S3 + S5 = -(Asin()+v) + Asin()+v = 2Asin() As a result, the phase  is derived as:  = tan -1 (Q/I) It should be noted that the weighting circuits 6, 7, 10 and the like can easily be realized by using circuitry that shifts the digits of the data, or by bit reversing, and as a result no complicated multipliers are required. As described above, the circuit enables quadrature phase detection of a phase-modulated wave by using an A/D converter, delay circuits, adders and latching circuits, and the DC off-set voltage in the input signal is completely eliminated in the process, which in turn eliminates phase errors. Since no analog devices such as ninety-degree phase shifters or mixers are used, which are difficult to implement and balance accurately, phase errors caused by the imperfections of such devices are eliminated. In addition, since circuits other than the A/D converter are implemented with digital circuits, and therefore large scale integration (LSI) technologies can be used, the size and power consumption of the quadrature phase detection circuit can be reduced.

Claims: A digital quadrature-phase detector circuit comprising: A/D converter means (1) for converting an analog phase-modulated signal (S1) into a digital signal (S2) at a sampling rate determined by a clock signal (C) having a frequency n times the carrier frequency of the analog signal, n being a positive integer; a plurality of n delay means (2-5) connected in series to the output of the A/D converter means and numbered counting from the A/D converter means, each delay means delaying an input thereto by one period of the clock signal to provide an output (S3-S6) therefrom; a plurality of weighting means (6, 7, 10) for relatively weighting the said digital signal (52) and the outputs (S3-S6) of the plurality of delay means to provide weighted signals; first adder means (8) for adding the weighted digital signal (S7) and the weighted outputs (S4,S6) of even-numbered delay means (3,5); and second adder means (11) for adding the weighted outputs (S3,S5) of odd-numbered delay means (2,4); characterised by first and second latching means (9,12) for respectively latching the outputs (S9-S11) of the first and second adder means (8,11) in synchronization with a latching signal having a period m times longer than the period of the clock signal, m being a positive integer, to produce in-phase and quadrature components (I,Q) of the phase-modulated signal, in which n = m and n >1. A detector circuit as claimed in claim 1, wherein n is four. A detector circuit as claimed in claim 2, wherein the plurality of delay means comprises first, second, third and fourth delay circuits (2,3,4,5) connected in series to the A/D converter means (1) for respectively delaying the digital signal by one period of the clock signal (C) to produce first, second, third and fourth delayed signals (S2,S3,S4,S5), and wherein the plurality of weighting means comprises first weighting means (6,7) for weighting the digital signal (S2) and said second and fourth delayed signals (S3,S5) with first, second and third weighting factors, respectively; and second weighting means (10)for weighting the first and third delayed signals (S2,S4) with fourth and fifth weighting factors, and wherein the first adder means comprises means for adding the outputs of the first weighting means, and the second adder means comprises means for adding the outputs of the second weighting means. A detector circuit as claimed in claim 3, wherein the first, second, third, fourth and fifth weighting factors are in the relative proportions -½, 1, -½, -1 and 1, respectively. A method of detecting a analog phase-modulated signal to produce its in-phase (I) and quadrature (Q) components, the method comprising the steps of: converting the analog phase-modulated signal into a digital signal in synchronization with a clock signal having a frequency n times higher than the carrier frequency of the phase-modulated signal, n being a positive integer; sequentially delaying the digital signal n times each by one period of the clock signal; weighting the digital signal and the signals delayed 2 p -times with a first set of predetermined weighting factors to produce a first set of weighted signals, p being 1, 2, ... n /2; weighting the signals delayed (2 p -1)-times to produce a second set of weighted signals; adding the first set of weighted signals to produce a first added signal; and adding the second set of weighted signals to produce a second added signal; characterised by latching the first and second added signals with a latching signal having a period m times longer than the period of the clock signal to produce the I and Q components, respectively, where n = m and n >1. A method as claimed in claim 5, wherein n is four. A method as claimed in claim 6, wherein the first set of weighting factors are in the relative proportions -½, 1, -½, and the second set of weighting factors are in the relative proportions -1,1.

Inventors: ICHIHARA MASAKI, ICHIHARA, MASAKI, ICHIHARA, MASAKI, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: H04L27
IPC codes: H04L27, H03D3, H03C3