CCD having a pair of horizontal resisters

Abstract: In order to prevent a horizontal stripe and a flicker from taking place due to a gain difference between two circuit systems (channels), the solid state imager of the present invention includes a pilot signal generating means provided within a solid state image pickup element for allowing two output units to generate pilot signals of the same level and a gain correcting circuit provided outside of said solid state image pickup element for comparing levels of the pilot signals passed through the two circuit systems and correcting a gain of one circuit system if the two pilot signals have a level difference therebetween. Further, in a solid state imager of the present invention, a pilot signal for detecting gains of two circuit systems which process signals from two output units of a solid state image pickup element is inserted into a video signal without modifying the rule with respect to the signal timing so that signal charges are supplied from a pilot signal generating means to respective horizontal registers so as to output the pilot signal during the dummy bit output period.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention generally relates to solid state imaging devices and, more particularly, is directed to a solid state imaging device including a solid state imaging pickup unit in form of a photoelectric conversion element array and a pair of output units which simultaneously derive signals and an external circuit having a pair of circuit channels for processing the signals from the pair of output portions. Description of the Prior Art Conventional solid state imaging devices, such as a charge-coupled device (CCD) or the like are generally designed so as to read a signal in the field read-out system. However, in order to increase resolution more, the solid state imaging device must be designed so as to read whole picture elements (i.e., pixels). If the whole pixels are read, then signals of two horizontal lines must be read during 1H period (H is the horizontal period). In order to read two horizontal line signals during 1H period, it is proposed to double the frequency of a conventional horizontal transfer clock which drives a horizontal register. This proposal cannot be substantially effected at least in the present condition. To solve the above problem, another proposal is made, in which a plurality of horizontal registers are provided and signal charges of odd lines and signal charges of even lines are simultaneously horizontally transferred by separate horizontal registers. FIG. 1 schematically shows a solid state image pickup element of the above-described previously proposed solid state imaging device. Referring to FIG. 1, it will be seen that an image unit a is composed of a number of light receiving elements arranged in a two-dimensional, i.e., a matrix shape and vertical shift registers b , b , ... disposed in accordance with every vertical columns of the light receiving elements so as to transfer the signal charges in the vertical direction. For simplicity, the light receiving elements are not shown and therefore the image unit a is illustrated in FIG. 1 as if it were composed of only the vertical registers b, b, ... As shown in FIG. 1, a first horizontal register c is disposed beneath the image unit a and a second horizontal register d is disposed in parallel to the first horizontal register c by a small distance from the first horizontal register c in the under side. A control gate e is disposed between the two horizontal registers c and d so as to control the transfer of signals charges between the first and second horizontal registers c and d . Channel stoppers f are arranged on the semiconductor substrate surface portion at its position corresponding to the underside of the control gate e in the pitch of one pixel and shown by solid rectangle blocks in FIG. 1. A first output unit g is adapted to derive the signal charges transferred thereto from the first horizontal register c and a second output unit h is adapted to derive signal charges transferred thereto from the second horizontal register d . A first correlation double sampling circuit (CDS circuit) i is adapted to reduce a noise of an output signal from the first output unit g and a second CDS circuit j is adapted to reduce a noise of an output signal from the second output unit h . A first automatic gain control (AGC) amplifier k is adapted to amplify an output signal of the first CDS circuit i and a second AGC amplifier ℓ is adapted to amplify an output signal of the second CDS circuit j . A signal processor circuit m is adapted to derive a luminance signal Y and red and blue color difference signals R-Y and B-Y by sampling respective color signals from the AGC amplifiers k and ℓ . When the storage of signal charges in the respective light receiving elements is finished, then a signal charge of the first line from the bottom of the image unit a is parallelly transferred to the first horizontal register c and then the signal charge of the first line is transferred to the second horizontal register d by the control gate e . Then, a signal charge of the second line from the bottom of the image unit a is transferred to the first horizontal register c . Thereafter, the signal charges of the first and second lines are simultaneously transferred by the first and second horizontal registers c , d , whereby video signals are simultaneously output to the outside of the solid state imager from the two output units g and h . A series of these operations are repeated at every 1H period. Japanese Laid-Open Patent Publication No. 62-92587, for example, describes research results of the above solid state imaging device having two horizontal registers to derive two video signals simultaneously. Since the solid state image pickup element includes two output units and two circuit systems in the above solid state imaging device in FIG. 1, there is then the problem that a horizontal stripe and a flicker will take place due to a gain difference between the two circuit systems. Particularly, when the signal is read in the interlace-system, a signal from the same light receiving element (pixel) is transferred by the different horizontal registers c , d at odd and even fields and then output from the different output units g , h . As a consequence, a gain difference between the two circuit systems cannot be neglected. Referring to FIG. 2, let us now describe in detail the above phenomenon such that the signal from the same light receiving element is transferred through the different circuit systems at odd and even fields. FIG. 2 shows how the signal charges, accumulated in light receiving elements (B0, A0, B1, A1, B2, A2) of one vertical column, are transferred at odd and even fields in a comparing fashion. As shown in FIG. 2, at the odd field, the light receiving elements B0 and A0, B1 and A1, and B2 and A2 form pairs and the paired signals are simultaneously read by the two horizontal registers c , d . Of the signals of the paired two horizontal lines, signals of the upper light receiving elements A0, A1, A2, ... are transferred by the first horizontal register c . The flow of the signals transferred by the first horizontal register c is represented by an open arrow in FIG. 2. Of the signals of the paired two horizontal lines, signals of the lower light receiving elements B0, B1, B2, ... are transferred by the second horizontal register d . The flow of the signals transferred by the second horizontal register d is represented by a solid arrow in FIG. 2. In this case, the open arrow and the solid arrow in FIG. 2 do not mean the difference of signal charge amounts or the like. At the even field, the light receiving elements A0 and B1, A1 and B2 are paired and the paired signals are simultaneously read by the two horizontal registers c , d . Of the signals of the paired two horizontal lines, the signals of the upper light receiving elements B1, B2, ... are transferred by the first horizontal register c , while the signals of the lower light receiving elements A0, A1, ... are transferred by the second horizontal register d. Accordingly, the signals of the respective light receiving elements are transferred by the different horizontal registers during the odd field or during the even field. More specifically, the signals of the light receiving elements A0, A1, A2, ... are transferred by the first horizontal register c during the odd field and transferred by the second horizontal register d during the even field. Further, the signals of the light receiving elements B0, B1, B2, ... are transferred by the second horizontal register d during the odd field and transferred by the first horizontal register c during the even field. As a consequence, the same signal is processed by different circuit systems (channels) during the odd field or during the even field. Accordingly, a gain difference between the two circuit systems causes noises, such as horizontal stripe, flicker and so on to occur. Patent abstracts of Japan, Vol. 14, No. 259 (E-937) (4202) & JP-A-2078382 disclose a reference signal generating circuit within a solid state imaging device for generating a reference signal charge. However, the reference signal charge is transferred to a distributing circuit and is transferred to the horizontal registers through the vertical CCD. Patent abstracts of Japan, Vol. 14 No. 105, (E-895) (4048) & JP-A-1305672 disclose an image array device using a feedback control for balancing two output signals. The structure receives two inputs which are respectively supplied via two diodes. No reference signals are formed by one input source region supplying the same signal through two input gates controlling the amount of signal charges to be transferred to two horizontal registers so that it is achieved to output pilot signals of the same level from the two output units as it is done in the present application. OBJECTS AND SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an improved solid state imaging device in which the aforementioned shortcomings and disadvantages of the prior art can be eliminated and in which a solid state image pickup element has two output units which can prevent a horizontal stripe and a flicker from taking place due to a gain difference between two circuit systems (channels) thereof. According to the present invention the pilot signals for detecting gains of two circuit systems (channels), which process signals from two output units of a solid state image pickup element, can be inserted into a video signal without modifying a rule with respect to a signal timing. The above object is according to the invention solved by the features of the independent claim 1. The depending claims 2 to 5 specify preferred embodiments thereof. In accordance with a preferred embodiment of the solid state imaging device of the present invention, the dummy bit output period is provided only in order to adjust the timing so that a signal within that period is neither a video signal nor is processed as a video signal. Accordingly, if the pilot signal is output during that period, then a gain difference between the two circuit systems due to the pilot signals can be detected without modifying the rule with respect to the timing of the output signal of the solid state image pickup element. Therefore, it is possible to perform the control operation for removing such gain difference on the basis of the detected result. The above and other objects, features, and advantages of the present invention will become apparent from the following detailed description of an illustrative embodiment thereof to be read in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram showing an example of a solid state imaging device according to the prior art; FIG. 2 is a schematic diagram showing the stream of signals, and to which references will be made in explaining the example of the prior-art solid state imaging device shown in FIG. 1; FIGS. 3 and 4 are used to explain the embodiment of a solid state imaging device according to the present invention; FIG. 3 is a schematic diagram showing an embodiment of a charge-coupled device having a pair of horizontal registers according to the present invention; FIG. 4 is a schematic diagram showing a structure of a pilot signal generating means used in the embodiment of the present invention; FIGS. 5A to 5C and FIGS. 6A to 6D are respectively timing charts of the respective examples of a timing at which a pilot signal is generated; FIGS. 5A to 5C are respectively timing charts of signals to which references will be made in explaining timings at which a pilot signal is generated during one horizontal period; and FIGS. 6A through 6D are respectively timing charts of signals to which references will be made in explaining timings at which the pilot signal is generated during one vertical period. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Before describing an embodiment of the solid state imaging device according to the present invention, a principle of the present invention will be described below. In general, the existing rule with respect to the timing of the output signal must be prevented from being varied even by the injection of the pilot signals into the output signals of the solid state image pickup element. Accordingly, having studied a method for inserting the pilot signals into the output signal without varying the above rule with respect to the output signal, the present invention utilizes the fact that a timing can be corrected by dummy bits provided at the transfer side of the horizontal register in the solid state image pickup unit, though not shown in FIG. 1. The embodiment of the charge-coupled device having a pair of horizontal registers according to the present invention will now be described with reference to the drawings. FIGS. 3 and 4 are respectively schematic diagrams used to explain the embodiment of the charge-coupled device having a pair of horizontal registers according to the present invention. FIG. 3 schematically shows a structure of the solid state imaging device of the present invention. Referring to FIG. 3, it will be seen that an image pickup unit 1 is composed of a large number of light receiving elements (several hundreds of thousands of light receiving elements to several millions of light receiving elements) and vertical registers 2, 2, ... disposed in accordance with the respective vertical columns of the light receiving elements. For simplicity, the light receiving elements are not shown and the image pickup unit 1 is illustrated in FIG. 3 as if it was composed of only the vertical registers 2, 2, ... As shown in FIG. 3, a first horizontal register 3a is disposed beneath the image pickup unit 1 and a second horizontal register 3b is disposed in parallel to the first horizontal register 3a by a small distance from the first horizontal register 3a in its under side. A control gate 4 is disposed between the two horizontal registers 3a and 3b so as to control the transfer of signals charges between the first and second horizontal registers 3a and 3b. Channel stoppers 5, 5, ... are arranged on the semiconductor substrate surface portion at its position corresponding to the underside of the control gate 4 in the pitch of one pixel and shown by solid rectangle blocks in FIG. 3. A dummy bit unit 6 is formed by extending the first and second horizontal registers 3a, 3b from the portions corresponding to the image unit 1 to the side to which the signal charge is transferred. The dummy bit unit 6 is provided in order to correct the timing or the like and the bit number thereof falls within a range of from several bit to several tens of bits depending upon the type of the dummy bit unit 6. A pilot signal insertion unit 7 is formed by extending the horizontal registers 3a, 3b and the control gate 4 from the portions corresponding to the image unit 1 toward the side opposite to the dummy bit unit 6 by the bit number substantially the same as that of the dummy bit unit 6. A pilot signal generating unit 8 is adapted to supply the signal charge, which is served as a pilot signal, to the pilot signal insertion unit 7. This pilot signal generating unit 8 is comprised of an input source region 9, a first input gate 10a and a second input gate 10b as shown in FIG. 4. While the input source region 9 is illustrated in the form of the unitary bit body whose bit number is the same as that of the pilot signal insertion unit 8 in FIG. 4, the input source region 9 is composed of, in actual practice, independent bits so as to generate signal charges of more than a predetermined amount, to be more concrete, signal charges of more than the level of the necessary pilot signal at a predetermined timing. The input gates 10a and 10b are supplied with transfer pulses and transfer signals, served as the pilot signals within the input source region 9, to the horizontal registers 3a and 3b. At that time, the input gates 10a and 10b are adapted to restrict the amount of the signal charges to the constant amount by the potential difference based on the supplied voltage difference. The timings at which the pilot signal is generated will be described more in detail later. First and second output units lla, llb are adapted to convert the signal charges transferred from the first and second horizontal registers 3a and 3b into voltages and output the same. First and second CDS circuits 12a, 12b are adapted to remove a noise (reset noise) from the signals of the first and second output units 11a, 11b, and amplifiers 13a, 13b whose gain can be controlled are adapted to amplify the output signals of the first and second CDS circuits 12a, 12b. At least one of the two amplifiers 13, 13b, for example, the amplifier 13a must be designed so as to be able to control its gain. The output unit 11a within the solid state imager, the CDS circuit 12a and the amplifier 13a both of which are located outside the solid state imaging device constitute a first circuit system (first channel), and the output unit 11b within the solid state imaging device, the CDS circuit 12b and the amplifier 13b both of which are located outside the solid state imaging device constitute a second circuit system (second channel). A signal processing circuit 14 samples respective color signals output from the amplifiers 13a, 13b and further processes the sampled color signals to thereby provide the luminance signal Y and the red and blue color difference signals R-Y and B-Y. A gain correcting circuit 15 is comprised of first and second sample and hold circuits 16a, 16b for sampling pilot signals from the output signals of the first and second amplifiers 13a, 13b and a comparing circuit 17 for comparing the outputs of the first and second sample and hold circuits 16a, 16b. An output signal of the comparing circuit 17 is supplied to one amplifier whose gain can be controlled, for example, the amplifier 13a as a gain control signal. If the level of the pilot signal sampled from the output signal from the first amplifier 13a is lower than that of the pilot signal sampled from the output signal from the second amplifier 13b, then the gain control signal goes, for example, high to increase the gain of the first amplifier 13a. Conversely, if the former level is lower than the latter level, then the gain control signal goes, for example, low to decrease the gain of the first amplifier 13a. Alternatively, two output signals of opposite phases may be supplied from the comparing circuit 17 to the first and second amplifiers 13a, 13b as the gain control signals. In that case, if the level of the pilot signal sampled from the output signal of the first amplifier 13a is lower than that of the pilot signal sampled from the output signal of the second amplifier 13b, then the gain of the first amplifier 13a is increased, while the gain of the second amplifier 13b is decreased. Conversely, if the former level is higher than the latter level, then the gain of the first amplifier 13a is decreased, while the gain of the second amplifier 13b is increased. FIGS. 5A, 5B and 5C are respectively timing charts illustrating an example of the way of how the pilot signal is generated. In this embodiment, the pilot signal is generated at every horizontal period during the horizontal blanking period. As shown in FIGS. 5A through 5C, in synchronism with a horizontal synchronizing signal HD, in other words, during the horizontal blanking period, a signal charge of a constant amount is injected from the input source region 9 to the horizontal registers 3a, 3b as a pilot signal by means of the input gates 10a, 10b. Then, a pilot signal is generated in the output signals of the solid state image pickup unit (two output signals are generated but only one output signal is shown for simplicity) with a delay time slightly longer than one horizontal period after the signal charge is inserted into the horizontal registers 3a, 3b. The pilot signal in the output signal from the first output unit lla and the pilot signal in the output signal from the second output unit llb are both the same in level because the amounts of the signal charges transferred from the input source region 9 to the horizontal registers 3a, 3b are restricted by the input gates 10a, 10b. The timings at which the pilot signals are generated in the output signals are made coincident with that of the dummy bit (however, with the delay time of one horizontal period after the signal charge is inserted into to the horizontal registers 3a, 3b). Further, the duration of the period in which the pilot signal is generated is selected to be substantially the same as that of the dummy bit period because the change of the rule (change of the timings of the respective signals in the output signal or the like) with respect to the output signal of the solid state image pickup unit must be prevented from taking place due to the insertion of the pilot signal into the output signal. Incidentally, the duration of period in whicn the pilot signal is generated (i.e., pulse width of the pilot signal) may be shorter than the duration of the dummy bit period. Further, the pilot signal may be generated at every vertical period as shown in FIGS. 6A through 6D, in which reference symbol VD denotes a vertical synchronizing signal. According to the above-mentioned solid state imaging device of the present invention, if the two circuit systems (channels), that is, the circuit system composed of the output unit lla, the CDS 12a and the amplifier 13a and the circuit system composed of the output unit llb, the CDS 12b and the amplifier 13b have a gain difference therebetween, then such gain difference takes place as a level difference between the pilot signals in the output signals of the amplifiers 13a, 13b. This level difference is detected by the comparing circuit 17 which compares the output signals of the sample and hold circuits 16a, 16b. The detected signal from the comparing circuit 17 is used to control either of or both of the gains of the amplifiers 13a, 13b so as to remove the above level difference. Accordingly, the gains of the amplifiers 13a, 13b are controlled so as to remove the gain difference therebetween; thereby keeping the circuit condition such that no gain difference exists between the two circuit systems constantly. Therefore, the troubles, such as the horizontal stripe and flicker caused by the gain difference between the two circuit systems can be avoided. As described above, the present invention is directed to the solid state imaging device which is comprised of the solid state image pickup element having two output units to simultaneously derive the signals from the two output units and the external circuit having the two circuit systems (channels) for processing the signals output from the above output units. In this case, the solid state imaging device of the present invention is provided with the pilot signal generating means formed within the solid state image pickup unit for generating the signals of the same level to the two output units as the pilot signals and the gain correcting circuit for comparing the levels of the pilot signals supplied through the two circuit systems and controlling the gains of the two circuit systems such that the level difference between the two circuits is removed. Therefore, according to the solid state imaging device according to the present invention, if the two circuit systems have a gain difference therebetween, then such level difference appears as the level difference between the pilot signals of the same level supplied from the pilot signal generating means through the circuit systems. Thus, the level difference is detected by the gain correcting circuit and the gains of the circuit systems can be controlled by the gain correcting circuit so as to remove the level difference. Accordingly, the gain difference between the two circuit systems (channels) can be removed and also the occurrence of the horizontal stripe and flicker due to the above gain difference can be prevented. Further, in the solid state imaging device of the present invention, the solid state image pickup unit is comprised of the two horizontal registers having the dummy bits provided at the transfer side, in which the two signals are simultaneously output from the two horizontal registers through the output units. In this case, the solid state image pickup element includes the pilot signal generating means for supplying the signal charges of the same amount to the two horizontal registers as the pilot signals, wherein the signal charges are supplied from the pilot signal generating means to the respective horizontal registers so that the pilot signals are output during the dummy bit output period. Therefore, according to the solid state imaging device of the present invention, the dummy bit output period is provided only in order to adjust the timing. Thus, the signal during that period is neither the video signal nor processed as the video signal. Accordingly, if the pilot signals are output during that period, then the gain difference between the two horizontal registers can be removed by the pilot signals without modifying the rule with respect to the timing at which the solid state image pickup element derives the output signal.

Claims: A solid state imaging device in which a solid state image pickup unit including a photoelectric conversion element array for converting incident light is provided, and which comprises, two horizontal registers (3a, 3b), two output units (lla, llb) each of which is connected to the respective horizontal register (3a, 3b), and an external signal processing circuit located outside the solid state image pickup unit and formed of two processing circuit channels for processing signals from the two output units, characterized in that pilot signal generating means (8) is provided within the solid state image pickup unit (1) for generating and outputting pilot signals of the same level via said output units (11a, 11b), respectively and comprises an input source region (9) for generating signal charges corresponding to said incident light and first and second input gates (10a, 10b) for separately transferring the signal charges to the two horizontal registers (3a, 3b) and controlling the amount of signal charges to be transferred to the two horizontal registers (3a, 3b), and in that said external signal processing circuit has a gain correcting circuit (15) for comparing the levels of the pilot signals passed through the two processing circuit channels and controlling gain of at least one of the two processing circuit channel so as to remove a level difference between the two processing circuit channels. The solid state imaging device according to claim 1, wherein said solid state image pickup unit (1) further comprises: vertical transfer registers (2) for transferring charges of said light receiving elements in the vertical direction; and a control gate (4) provided between said first and second horizontal registers (3a, 3b), wherein said pilot signal generating means (8) simultaneously inserts pilot signals into said first and second horizontal registers (3a, 3b). The solid state imaging device according to claims 1 or 2, wherein the charges of said plurality of light receiving elements arranged in matrix fashion are read independently. The solid state imaging device according to one of the preceeding claims, wherein each of said two processing circuit channels includes a correlation double sampling circuit (16a, 16b) and a gain control amplifier (13a, 13b) supplied with an output signal of said correlation double sampling circuit, whereby a pair of pilot signals involved in said two processing circuit channels are sampled and held and a gain of said gain control amplifier of one of said processing circuit systems can be varied by an output which results from comparing the sampled and held outputs by a comparator (17). The solid state imaging device according to one of the preceeding claims, wherein said solid state image pickup unit (1) further comprises: a dummy bit unit (6) formed by extending the two horizontal registers (3a, 3b) from the portions corresponding to the image pickup unit (1) to the side to which the signal charge is transferred, wherein dummy bits (6) are provided and simultaneously output from said transfer side of said horizontal registers (3a, 3b) through said output units (11a, 11b), wherein said pilot signal generating means is supplying signal charges of the same amount to said horizontal registers (3a, 3b) as pilot signals and signal charges are supplied from said pilot signal generating means to said horizontal registers (3a, 3b) such that said pilot signals are output during a dummy bit output period.

Inventors: KOBAYASHI ATSUSHI, ONGA MAKOTO, SASE MASATOSHI, SATO YASUSHI, KOBAYASHI, ATSUSHI, ONGA, MAKOTO, SASE, MASATOSHI, SATO, YASUSHI
Applicants: SONY CORP, SONY CORPORATION
Application year: 1991
Main classification: H04N3
IPC codes: H04N5, H04N3