A/D OR D/A CONVERTER, A/D AND D/A CONVERTER SYSTEM AND A CALIBRATION METHOD THEREOF

Abstract: The invention relates to A/D and D/A converters and converter systems and their calibration methods. Higher speeds and greater accuracy can be achieved in the converters with simpler and more advantageous circuit structures when the base number of the number system used in the converter (1, 2) is smaller than 2.

Description: A/D or D/A converter, A/D and D/A converter system and a calibration method thereof The present invention relates to A/D and D/A converters and converter systems and their calibra¬ tion methods. Digital-to-analog (D/A) and analog-to-digital (A/D) converters are used generally in electronics, especially in computer interfaces, to convert an analog signal into digital form, and vice versa. In rapid and accurate converters, it is customary to use a binary weight system in which the base number is 2: (1) U = (C + B-^ "1 + B 2 2- 2 + -n B n 2 )E, where U is the value of an analog signal, E is a reference voltage used in the converter, and B-^ ... B n are binary values (0,1), C is a constant and n is the number of the bits/weights of the converter. The binary weights 2~ k of the converters are usually realized by weight or reference elements forming a so-called weighing network. In practice, the weighing network and the weight elements are usually realized by means of resistors, capacitors and transistors. The accuracy of the converter there¬ by depends on how accurately the relationship between the values of the weight elements is the right one. This involves very high requirements for the converter manufacturing technique, and in many cases converters have to be tuned after manufacture. Further, as the values of the weight, elements vary in time (drifting), the accuracy limit of converters is usually about 12 bits. Converters having a greater accuracy than that have to be calibrated or tuned intermittently during use. Converters usually have to be calibrated by adjusting the values of the weight elements and the reference voltages. In addition, when great speed and accuracy are to be achieved, the time required for the converter to settle to the required accuracy causes problems. For this reason, the most accurate conventional converters are usually also slow. The object of the present invention is to provide a novel A/D or D/A converter which is more accurate, easier to calibrate and less demanding in view of the manufacturing technique than previously. This is achieved by means of an A/D or D/A converter which according to the invention is charac- terized in that the base number of the number system used in the converter is smaller than 2. The invention is based on the Applicant's discovery that when a number system having a base number smaller than 2 is used in the converter in place of the binary system, the obtained converter comprises number ranges in which the same number is formed by different combinations of bits. Consequent¬ ly, deviation can be allowed for the weights without the risk of gaps remaining the number range of the converter. The actual accurate value of the weight can be determined by calculation or programmatically with a certain self-calibration procedure and each conversion result can be corrected on the basis of these actual weights. For example, the offset and noise of the comparators of a weighing A/D converter do not cause an error in the conversion, as the same voltage value can be represented at the threshold value points of the comparators with two different bit series in the number system according to the invention. In a normal binary system, inaccuracy in the weights causes a gap in the number range of the converter, and the error caused by the gap is impossible to correct. By means of the invention, the weights and other parameters of the converter, such as resistor and capacitor values, comparator offset, gain, rising time, etc., can be allowed to deviate fairly largely within certain limits. The structure of the converter is simple, requiring no greater accuracy from the manufacturing technique, which, in turn, reduces costs. The speed of the A/D converter can be increased as the sampling frequency is constant and thus the amplifier need not reach its final state before conversion, because such settling time errors will be compensated for in calibration. Converters can be calibrated (the weight values can be measured) by software at desired moments. Subsequent errors occurring in conversions are caused by noise and interferences only. The bit number of the converter can be increased up to the noise limit. Using certain methods, values below the noise limit can be obtained in calibration. The invention is also concerned with a method according to claim 9 for calibrating the A/D converter of the invention. The invention further relates to an A/D and D/A system according to claim 12, comprising an A/D and D/A converter of the invention. The invention is also concerned with a method of calibrating a converter system according to claim 12. The invention will now be described in more detail with reference to the attached figure, which shows a block diagram of an A/D and D/A converter system according to the invention. In the converters according to the invention, the input voltage U of the A/D converter or the out¬ put voltage of the D/A converter fulfills the follow- ing equation: (2) U = (B 1 x 1 + B 2 A 2 + + B n x n + C ) E ' where X- j _ ... x n are the weight values of the converter, B-^ ... B n are bits having a value 0 or 1, and C is a constant containing the offset values of the converter. In order that the number range of the converter would be continuous throughout, the following condition has to be set for the weights x k of the converter: n (3) Σ X > X k - X n , k = 0,..., n-1 p=k+l Equation (4) sets a condition that the sum of weight values preceding each weight has to be greater than the value of this particular weight. According to the invention, this condition is fulfilled by using, in place of the binary number system with the base number 2, another number system in which the base number is smaller than 2, whereby Equation (2) will be: (5) U = [C + B 1 (2-Δ) -1 + B 2 (2-Δ) -2 ... + B n (2-Δ) n ]E where (2-Δ) is the base number of the number system, in which Δ is preferably in the range from 0.01 to 0.1. The base number of the number system is cor- respondingly in the range from 1.90 to 1.99. From now on, the number system according to the invention will be referred to as a (2-Δ) system. The number Δ may also slightly vary in one and the same converter from one weight to another. The figure shows a block diagram of a specific converter system according to the invention. The system comprises an analog-to-digital converter 1 (ADC) utilizing a (2-Δ* j _) system. The system further comprises a D/A converter 2 (DAC) utilizing a (2-Δ 2 ) system. The numbers Δ± and Δ 2 are different, as a result of which the base numbers of the number systems of the converters 1 and 2 are different, as calibration by a method 3 to be described later could not be carried out if the base numbers would be equal. The base number ( 2-Δ_- ) of the converter 1 and the base number (2-Δ 2 ) of the converter 2 may vary within the respective converter from one weight to another within a predetermined tolerance area, but the mean values of the base numbers of the two converters have to differ from each other. The converters 1 and 2 are connected to a control unit 3, preferably a computer, controlling them through data buses 5 and 6 and a common control bus 7. In the preferred embodiment of the invention, data to be transferred over the data bus 5 is in the number system (2-Δ--_), and data to be transferred over the data bus 6 is in the number system (2-Δ 2 ). The control unit 3 is also connected to external systems through a control bus 9 and a binary data bus 8. An analog input 12 in the A/D converter 1 is connectable by a change-over switch SI to an analog input voltage U IN , to a reference voltage E corresponding to the largest value of the number range of the converter, to another reference value (e.g. 0 V) corresponding to the zero value of the number range of the converter, to the output of a voltage generator 4 or to an analog output 13 in the D/A converter 2. The analog output 13 of the D/A converter 2 is connectable by means of a change-over switch S2 to an analog output U Q U T of the converter system or to the analog input 12 of the A/D converter 1. The control unit 3 controls the operation of the switches SI and S2 and the voltage generator 4, as is illustrated by broken lines 10 and 11. The converter system of the invention calibrates itself automatically by means of a soft¬ ware. In normal use, the analog input of the A/D converter 1 is connected to the analog input U IN of the system and correspondingly the analog output 13 of the D/A converter 2 is connected to the analog output U ouτ of the system. The A/D converter 1 performs an analog-to-digital conversion and applies the digital numbers in the (2-Δ-^) system over the data bus 5 to the control unit 3, which corrects the conversion results by means of calibration parameters calculated in accordance with a predetermined calibration procedure and converts the corrected results into the binary system. Correspondingly, the control unit 3 corrects control words to the D/A con- verter 2 by means of calibration parameters calculated for this converter and applies the control words over the data bus 6 to the converter 2. In other words, in the present invention, the inaccurate values of the weights of the converters 1 and 2 are accurately known, and each conversion result from the A/D converter 1 is corrected automatically and cor¬ respondingly each control word to the D/A converter 2 is corrected in such a way that an analog voltage obtained as a result of the conversion is accurately correct. Alternatively, the control unit 3 may contain a search-table type memory to which a corrected value corresponding to the bit pattern supplied by the A/D converter 1 has been stored at the calibration stage. Correspondingly, the control unit 3 may contain an¬ other search table in which a corrected control word to be fed to the D/A converter 2 is stored for each control word intended for the converter 2. These search tables may also perform conversions into the binary system and vice versa. The operations of the control unit 3 may also be partly or wholly integrated in the converters 1 and 2. In the following the calibration of the A/D converter 1 will be described. The input voltage U IN of the converter is obtained from the following equation: nl C-^ is a constant containing the offset voltages of the converter 1. The A/D converter 1 may be calibrated in several ways by means of the reference voltages E and 0 V and the voltage generator 4 and the D/A converter 2. 1. Calibration by the reference voltages 0 V and E When the A/D converter 1 is a cyclic 1-bit converter, it can be calibrated by connecting the input 13 alternately to the reference voltages 0 V and E, and so the following equation group can be obtained from Equation (6) nl (7) 1 = Cl + Σ B lk X k k=l nl (8) 0 = Cl + Σ B 0k X k k=l where X k = X k . From Equations (7) and (8), Cl and X k used as calibration parameters are solved. When the weights x k of the converter 1 are accurately known, the input voltage U IN can be calculated from bits supplied by the converter 1 by means of Equation (6). 2. Calibration by the voltage generator 4 The basic idea of this calibration method is that the weights X k of the A/D converter 1 can be measured by using the calibration generator 4 having an output voltage U f varying with time according to a known function, which can also be measured. General¬ ly, the function Uf is (9) U f = E f (n,α), where n = 0, 1, 2, ..., max; α = a parameter vector = (α* j _, α ,..., d p ). In practice, the function U f may be e.g. (10) U f » E (1 - α-in + α n^ α 3 n 3 ) By connecting the input of the converter 1 alternately to both the reference voltage 0 V and the calibration generator 4 and storing the measuring results, an equation group will be obtained nl (11) f(n,α) = ∑ B nk x k + C k=l nl (12) 0 = Σ D k x k k=l where n = 0, 1, , max; D k = {0,1}; B k = {0,1}. From this equation group, C, X and α can be solved. The number (max) of the input voltages has to be greater than the number n-^ of the weights x k . None of the bits from the output of the converter 1 may remain unchanged during calibration, which is ensured by a great number of input voltages. In addition, noise can be partly compensated for by a great number of equations. 3. Calibration by the D/A converter 2 In this method the D/A converter 2 is used in place of the calibration generator 4. The output voltage U QUT of the D/A converter 2 is obtained in the following way: n2 (13) U QUT /E = Σ D nk Y k + C 2 k=l where Di, = the control bit of the converter 2 = 1 or k 1 0; Y k = the weight of the converter 2 = γ k-l ? 2-Δ k C = constant. The input of the A/D converter 1 is first connected to the reference voltages E and 0 V and then to the output 13 of the D/A converter 2. The control unit 3 applies several numbers to the converter 2, which numbers are subjected to D/A con¬ version by the converter 2 and then to A/D conversion by the converter 1. The obtained measuring results are stored. The numbers to be applied to the converter 2 may be predetermined or alternately generated at random. By measuring, the following equation group is obtained nl (14) 1 = Cl + Σ B lk x k k=l nl (15) 0 = Cl + Σ B 0k x k k=l nl (16) C2 = Cl + Σ B 2k X k k=l n2 nl (17) C2 + Σ Dj k Y k = Cl + Σ Bj k X k k=l k=1 where j = 3, 4, 5, ..., ma . From the equation group, Cl, C2, Y k and x k are solved by means of the measuring results. The D/A converter 2 may also be calibrated separately through the A/D converter 1 when the converter 1 has first been calibrated by the method 1 or 2. When the weights y k of the D/A con- verter 2 are accurately known, control bits Dk from the converter 2, corresponding to a predetermined output voltage U ouτ , can be calculated from Equation (13) in the control unit 3. Each conversion to be carried out by the converters 1 and 2 thus requires that the control unit 3 performs a calculation according to Equation (6) or (13). The load of the control unit 3 (e.g. a computer) can be reduced by providing the converters 1 and 2 with a correcting memory and a calculation circuit solving the equations in question. The control unit 3 thereby still performs the calibra¬ tion, but stores the calculated calibration parameters in the correcting memories of the converters. Alternatively, differences between the assumed and actual values of the weights of the converter can be determined by calibration, and these differences are used as calibration parameters when correcting the conversion results. As the calibration methods 2 and 3 are computationally very heavy, they are basic calibrations to be performed relatively seldom. Since the relationships between the component values of the converter vary with time relatively slowly, the more rapid offsets caused e.g. by drifting or temperature variation and having a similar effect on all weights of the converter, can be calibrated more often with rapid (about 1,000 times more rapid) and computa¬ tionally light intermediate calibration methods. In one intermediate calibration system, the analog input 12 of the A/D converter 1 is connected in succession to the above-mentioned reference voltages E and 0V. When the offset correction required for the weights is denoted with the calibra- tion parameter Z, the following equation group is obtained on the basis of measurements nl (18) 1 - Cl = + Z Σ Blk X Λ k U IN = E k=l nl ( 19 ) 0 = Cl = + Z ∑ B Ok X k ; U IN = 0 k=l Herein X are the same as the previously calibrated values. From the equations, Cl and Z are solved. Thereafter the values X k are corrected with the additional parameter Z now calculated in the following way: X k = ZX k . Thereafter the D/A converter 2 can be subjected to a corresponding rapid calibration by controlling it so as to cause it to form alternately a low (D k =0) and a high voltage in its output 13 and measuring the voltages by the A/D converter 1. The above equations are valid in cases where the non-linearities of the circuits can be dis¬ regarded. When the non-linearities are taken into account, the equations and the calculation become somewhat more complicated without however deviating from the basic idea of the invention. The attached figure and the description related to it are only intended to illustrate the present invention. In their details, the converter, converter system and calibration methods of the invention may vary according to the attached claims.

Claims: Claims : 1. Analog-to-digital or digital-to-analog converter (1, 2), c h a r a c t e r i z e d in that the base number of the number system used in the converter (1, 2) is smaller than 2. 2. Converter according to claim 1, c h a r a c¬ e r i z e in that said base number is 2-Δ, where Δ is preferably within the range from 0.01 to 0.1. 3. Converter according to claim 1 or 2, c h a r a c t e r i z e d in that the base numbers 2-Δ of the different weight elements of the converter (1, 2) have values differing from each other. 4. Analog-to-digital converter (1) according to claim 2 or 3, c h a r a c t e r i z e d in that the converter comprises correcting means (3) for correct¬ ing conversion results in the 2-Δ number system of the converter or for replacing them with calibration parameters calculated by means of a predetermined calibration procedure. 5. Analog-to-digital converter according to claim 2, 3 or 4, c h a r a c t e r i z e d in that the converter (1) comprises means (3) for converting the conversion results, which are in the 2-Δ number system, into the binary system. 6. Digital-to-analog converter (2) according to claim 2 or 3, c h a r a c t e r i z e d in that the converter comprises correcting means for correcting the digital numbers of the 2-Δ system or the binary system which are to be converted or for replacing them before conversion with calibration parameters calculated by means of a predetermined calibration procedure. 7. Converter according to any of the preceding claims, c h a r a c t e r i z e d in that the correcting means are contained in a computer (3) connected to the digital side of the converter. 8. Converter according to any of the preceding claims, c h a r a c t e r i z e d in that the converter is a pipeline-type converter. 9. Method of calibrating an analog-to-digital converter according to claims 1 to 4, c h a r a c ¬ t e r i z e d in that the method comprises connecting an analog input (12) in the converter (1) alternately to a reference voltage (OV) corresponding to the zero value of the number range of the converter and to a reference voltage (E) cor¬ responding to the largest value of the number range; storing the obtained conversion results; and calculating the actual values or calibration values of the weights of the converter on the basis of the known reference voltage values and the stored conversion results corresponding to them. 10. Method of calibrating an analog-to-digital converter according to claims 1 to 4, c h a r a c ¬ t e r i z e d in that the method comprises connecting an analog input in the converter (1) to a voltage source (4) supplying a voltage varying with time according to a known function and covering the number range of the converter and to a reference voltage (0V) corresponding to the zero value of the number range of the converter (1); storing the obtained conversion results; and calculating the actual values or calibration values of the weights of the converter on the basis of said known voltage function, the reference voltage and the stored conversion results corresponding to them. 11. Method according to claim 9 or 10, c h a r- a c t e r i z e d in that the method calculates dif- ferences between the assumed and actual values of the weights of the converter, the differences being used as calibration parameters in the correction of the conversion results. 12. A/D and D/A converter system comprising an A/D converter (1) and a D/A converter (2) having analog sides (12, 13) connectable to each other for the calibration of at least the D/A converter, c h a r a c t e r i z e d in that the base numbers of the number systems used in the converters (1, 2) are mutually different and smaller than 2. 13. Converter system according to claim 12, c h a r a c t e r i z e d in that the base number of the number system of the A/D converter (1) may vary within a first tolerance area and the base number of the number system of the D/A converter (2) may vary within a second tolerance area in such a way that the mean values of the base numbers of the converters are different. 14. Method of calibrating a converter system according to claim 12, c h a r a c t e r i z e d in that the method comprises connecting the analog input (12) in the A/D converter (1) alternately to a reference voltage (OV) corresponding to the zero value of the number range of the converter, to a reference voltage (E) cor¬ responding to the largest value of the number range, and to the analog output (13) in the D/A converter (2); applying digital control values to the D/A converter when this is connected to the A/D converter; storing the obtained conversion results; and calculating the actual values or calibration values of the weights of the A/D and D/A converters when both converters are uncalibrated, or calculating the actual values or calibration values of the weights of only the D/A converter when the A/D converter is calibrated in advance, on the basis of the known reference voltage values, the stored conversion results and the control values of the D/A converter. 15. Method according to claim 14, c h a r a c ¬ t e r i z e d in that the control values of the D/A converter (2) are predetermined control values or they are generated at random.

Inventors: MANNONEN PENTTI, MANNONEN, PENTTI
Applicants: NOKIA MOBILE PHONES LTD, NOKIA MOBILE PHONES LTD.
Application year: 1991
Main classification: H03M1
IPC codes: H03M1