Semiconductor memory device

Abstract: A semiconductor memory device a memory cell array (1), a data register unit (4, 5), and a data transfer gate unit (3a, 3b). The memory cell array (1) includes first memory cell arrays (1a, 1b,...) and second memory cell arrays (2a, 2b,...) alternately disposed. The data register unit (4, 5) includes first data registers (4a, 4b,...) and second data registers (5a, 5b,...) alternately disposed. Each of a plurality of data transfer gates of the data transfer gate unit (3a, 3b) includes a gate (25) for connecting each of the first memory cell arrays (1a, 1b,...) to each of the first data registers (4a, 4b,...), and a gate (27) for connecting each of the second memory cell arrays (2a, 2b,...) to each of the second registers (5a, 5b,...), and further includes a gate (26) for connecting each of the first memory cell arrays (1a, 1b,...) to each of the second data registers (5a, 5b,...), and a gate (28) for connecting each of the second memory cell arrays (2a, 2b,...) to each of the first data registers (4a, 4b,...).

Description: The present invention relates to a semiconductor memory device, and more especially to a semiconductor memory device of a multi-port structure having a RAM port for random access of memory cells and a SAM port for serial access. In particular, the inventipn relates to a semiconductor memory device comprising: a memory cell array having random accessible memory cells disposed in a matrix form, said memory cell array including first memory cell arrays and second memory cell arrays alternatively disposed in a column direction, said first and second memory cell arrays being divided in accordance with a column address; a data register unit for storing one column of data of said memory cell array, said data register unit being serially accessible by an external circuit, said data register unit having first data registers and second data registers alternately disposed in the column direction; and a data transfer gate unit including a plurality of data transfer gates for controlling data transfer between said memory cell array and said data register unit, each of said plurality of data transfer gates comprising a first gate for connecting a predetermined one of said first memory cell arrays to a predetermined one of said first data registers, and a second gate for connecting a predetermined one of said second memory arrays to a predetermined one of said second data registers, and further comprising a third gate for connecting said predetermined one of said first memory cell arrays to said predetermined one of said second data registers, and a fourth gate for connecting said predetermined one of said second memory cell arrays to said predetermined one of said first data registers, so as to allow continuous data transfer relative to said first or second memory cell array. Such a semiconductor memory device is disclosed in EP-A-0 326 172 (Fig. 4). Reference is also made to EP-A-0 479 163, Fig. 8 of which discloses a similar semiconductor memory device, differing only in respect of the manner in which the fourth gate is connected. A conventional semiconductor memory device of a multi-port structure is shown in FIG. 5. A memory cell array 61 is provided as a RAM port, which array has memory cells disposed in a matrix shape and is randomly accessible. A data register 63 is also provided as a SAM port, which register stores one row of data and is serially accessible. The memory cell array 61 is divided into a lower level memory cell array 61a to be accessed by the most significant bit (MSB) "0" of a column address, and an upper level memory cell array 61b to be accessed by MSB "1" of a column address. The data register 63 is also divided into a lower level data register 63a and an upper level data register 63b. A data transfer gate 62a is provided for data transfer between the data register 63a and memory cell array 61a, and a data transfer gate 62b is provided for data transfer between the data register 63b and memory cell array 61b. The connection between the data transfer gate 62a and data register 63a within a circuit portion A enclosed by a broken line is as shown in FIG. 6. A pair of bit lines 71a and 71a are connected to transistors 76 serving as the data transfer gate 62a. Each of the transistors 76 becomes conductive when a drive signal is applied to its gate via a signal line 75 connected thereto. In a conventional device, a pair of bit lines 71a and 71a on the RAM port side is made in one-to-one correspondence with each data register 77 on the SAM port side. In the split transfer between the memory cell array 61 and data register 63 at upper and lower levels, data is transferred via the data transfer gate 62a between the memory cell array 61a and data register 63a, via the data transfer gate between the memory cell array 61b and data register 63b. An active one of the data registers 63a and 63b which are alternately made active is used for the data transfer of the SAM port to an external circuit. Used in the data transfer between the SAM port and RAM port, therefore, is one of the data registers alternately placed in a standby state which is not now transferring data to an external circuit. For this reason, if continuous data read/write is to be executed by using the data register 63 in the split transfer manner, it has been necessary to alternately access the lower and upper memory cell arrays 61a and 61b, and it has not been possible to continuously access only one of the memory cell arrays, i.e., to continuously access only one of the memory cell arrays 61a and 61b from the SAM port. If a frame buffer were to be constructed using such a RAM and SAM port, there arose problem of some restriction in mapping between a display screen and the memory. It is therefore an object of the present invention to provide a semiconductor memory device capable of continuously accessing the same memory cell array among memory cell arrays divided according to a column address, in the split transfer to data registers. According to the invention, there is provided a semiconductor memory device as initially defined, characterized in that the third gate is connected to the first memory array in parallel with the first gate and that the fourth gate is connected to the second memory array in parallel with the second gate, such that in operation, when said first and second gates are open at the same time data are transferred between said first memory cell arrays and said first data registers and data are transferred between said second memory cell arrays and said second data registers, and when said third and fourth gates are open at the same time, data are transferred between said first memory cell array and said second data registers and data are transferred between said second memory cell arrays and said first registers. It follows that data transfer is allowed between the first memory cell array and the first or second data register, and also between the second memory cell array and the first or second data register. In this manner, it is possible to continuously transfer data relative to one of the first and second memory cell arrays. The invention will be better understood by referring, by way of example, to the accompanying drawings, in which FIG. 1 is a block diagram showing the structure of a semiconductor memory device according to an embodiment of the present invention; FIG. 2 is a block diagram showing the structure of the data transfer gate of the device shown in FIG. 1; FIG. 3 is a block diagram showing the structure of a data transfer gate of a semiconductor memory device according to another embodiment of the present invention; FIG. 4 is a block diagram showing the structure of a data transfer gate of a semiconductor memory device according to a further embodiment of the present invention; FIG. 5 is a block diagram showing the structure of a conventional semiconductor memory device; and FIG. 6 is a block diagram showing the structure of the data transfer gate of the device shown in FIG. 5. Preferred embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 shows the structure of a semiconductor memory device according to an embodiment. As described above, in a conventional semiconductor memory device, two memory cell arrays divided by MSB of a column address are each collectively disposed into two independent groups. In contrast with this, in a memory cell array 1 of this embodiment, finely divided memory cell arrays 1a, 1b, 1c,... having MSB "0" of a column address and memory cell arrays 2a, 2b, 2c,... having MSB "1" are alternately disposed in the column direction. Similarly, finely divided lower level data registers 4 and upper level data registers 5 are alternately disposed. A data transfer gate 3a is provided between the memory cell arrays 1a, 1b and the data registers 4 and 5. Another data transfer gate 3b is provided between the memory cell arrays 1b, 2b and the data registers 4 and 5. In this memory device, one bit data is transferred by a single bit line. Bit lines 11a, 11b, 12a, 12b,... are connected respectively to the memory cell arrays 1a, 2a, 1b, 2b,... The structure of the data transfer gates 3a and 3b is shown in FIG. 2. A transistor 25 is connected between the memory cell array 1a and data register 4a both having MSB "0" of a column address. A transistor 27 is connected between the memory cell array 2a and data register 5a, both having MSB "1", In addition, the memory cell array 1a and data register 5a, each having a different MSB, are coupled by a transistor 26, and the memory cell array 2a and data register 4a, each having a different MSB, are coupled by a transistor 28. Each gate of the transistors 25, 26, 27, and 28 is connected to a corresponding one of signal lines 21, 23, 22, and 24. In an ordinary transfer operation, the conduction of the transistors are so controlled that the memory cell array and data register associated with the same MSB are connected. For example, upon application of control signals to the gates of the transistors 25 and 27 via the signal lines 21 and 22, the transistors 25 and 27 become conductive so that the memory cell array 1a and data register 4a, as well as the memory cell array 2a and data register 5a are electrically connected together. In this case, the transistors 26 and 28 are maintained non-conductive so that the memory cell array and data register, each having a different MSB, are electrically separated. In this manner, similar to a conventional device, data transfer is executed between the memory cell arrays 1a, 1b,... and lower level data resisters 4a, 4b,..., all having MSB "0", and between the memory cell arrays 2a, 2b,... and upper level data registers 5a, 5b,..., all having MSB "1". Continuous access, for example, to the memory cell arrays 1a, 1b,... having MSB "0" is carried out in the following manner. Assuming that the data registers 4a, 4b,... are in a standby state, transistors 25 are made conductive via the signal line 21 so that data transfer is allowed between the data registers 4a, 4b,... and memory cell arrays 1a, 1b,... Thereafter, when the data registers 5a, 5b,... enter the standby state, the transistors 26 are made conductive via the signal line 26 so that data transfer is allowed between the memory cell arrays 1a, 1b,... and data registers 5a, 5b,... Similarly, continuous access to the memory cell arrays 2a, 2b,... having MSB "1" is effected by alternately making conductive the transistors 27 and 28. Data transfer is then executed relative to the data registers 4a, 4b,... or data registers 5a, 5b,... in the standby state. Another embodiment of the present invention will be described below. A point of this embodiment different from the above-described embodiment is that one bit data is transferred using a pair of bit lines. The structure of the data transfer gate of this embodiment device is as shown in FIG. 3. For example, a memory cell array 1a and data register 4a, both having MSB "0", are connected by a pair of bit lines 31a and 31a , and a memory cell array 2a and data register 5a, both having MSB "1", are connected by a pair of bit lines 32a and 32a . The data transfer gate is constructed in the following manner. Transistors 43 and 45 are provided between the memory cell array 1a and data register 4a, both having MSB "0", and transistors 47 and 49 are provided between a memory cell array 2a and data register 5a, both having MSB "1". In addition, transistors 44 and 46 are connected between the memory cell array 1a and data register 5a, each having a different MSB, and transistors 48 and 50 are connected between the memory cell array 2a and data register 4a. A signal line 35 is connected to the gates of transistors 43 and 45, and a signal line 37 is connected to the gates of the transistors 44 and 46. A signal line 36 is connected to the gates of the transistors 47 and 49, and a signal line 38 is connected to the gates of the transistors 48 and 50. In an ordinary transfer operation, the memory cell array and data register associated with the same MSB are connected. For example, upon application of control signals to the signal lines 35 and 36, the transistors 43, 45, and the transistors 47 and 49 are made conductive so that the memory cell array 1a and data register 4a, and the memory cell array 2a and data register 5a, are connected together. In this manner, data transfer is carried out between the memory cell array 1a and data register 4a, and between the memory cell array 2a and register 5a. Continuous access, for example, to the memory cell arrays 1a, 1b, 1c,... having MSB "0" of a column address is carried out in the following manner. Assuming that the data registers 4a, 4b,... are in a standby state, transistors 43 and 45 are made conductive so that the memory cell array 1a and data register 4a as well as the memory cell array 1b and data register 4b are connected together to allow data transfer. Thereafter, when the data registers 5a, 5b,... enter the standby state, the transistors 44 and 46 are made conductive via the signal line 26 so that the memory cell array 1a and data register 5a as well as the memory cell array and data register 5b are connected together to allow data transfer. In this embodiment, each memory cell array in each column is connected to another data register, for example, in a manner that the memory cell array 1a is connected not only to the data register 4a but also to the data register 5a. In contrast with this, in an embodiment shown in FIG. 4, each memory cell array in each column is connected to another data register corresponding to every second column. For example in FIG. 4, a memory cell array 1a is connected not only via transistors 63 and 65 to a data register 4a, but also via transistors 64 and 66 to another data register 5a. Similarly, a memory cell array 1b is connected not only via transistors 63 and 65 to a data register 4b, but also via transistors 64 and 66 to another data register 5b. Likewise, a memory array 2a is connected via transistors 67 and 69 to the data register 5a, and via transistors 68 and 70 to the data register 4a. A memory array 2b is connected via the transistors 67 and 69 to a data register 5b, and via the transistors 68 and 70 to the data resister 4b. In an ordinary data transfer, similar to the above embodiments, for example, the memory cell array 1a and data register 4a as well as the memory cell array 2a and data register 5a are connected together. In continuously accessing memory cell arrays having MSB "0" of a column address, for example, the memory cell 1a is alternately connected to one of the data registers 4a and 5a in a standby state. As described above, in any one of the above-described embodiments, it is possible to continuously access one of the upper and lower level memory cell arrays using a SAM port in a split transfer, without accessing alternately between them. Therefore, if a frame buffer is constructed using such a RAM and SAM port, there is no restriction in mapping a display screen and the memory. The above-described embodiments of the present invention have been described only for illustrative purpose, and the present invention is not limited thereto. For example, the structure of the data transfer gate is not limited to those shown in FIGs. 2 to 4, but any other type of a data transfer gate may be used if it can properly control the connection between memory cell arrays and data registers. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A semiconductor memory device comprising: a memory cell array (1) having random accessible memory cells disposed in a matrix form, said memory cell array including first memory cell arrays (1a, 1b) and second memory cell arrays (2a, 2b) alternatively disposed in a column direction, said first and second memory cell arrays being divided in accordance with a column address; a data register unit (4, 5) for storing one column of data of said memory cell array, said data register unit being serially accessible by an external circuit, said data register unit having first data registers (4a, 4b) and second data registers (5a, 5b) alternately disposed in the column direction; and a data transfer gate unit including a plurality of data transfer gates (3) for controlling data transfer between said memory cell array (1) and said data register unit (4, 5), each of said plurality of data transfer gates comprising a first gate (25) for connecting a predetermined one of said first memory cell arrays (1a, 1b) to a predetermined one of said first data registers (4a, 4b), and a second gate (27) for connecting a predetermined one of said second memory arrays (2a, 2b) to a predetermined one of said second data registers (5a, 5b), and further comprising a third gate (26) for connecting said predetermined one of said first memory cell arrays (1a, 1b) to said predetermined one of said second data registers (5a, 5b), and a fourth gate (28) for connecting said predetermined one of said second memory cell arrays (2a, 2b) to said predetermined one of said first data registers (4a, 4b), so as to allow continuous data transfer relative to said first or second memory cell array (1a, 1b); characterized in that the third gate (26) is connected to the first memory array (1a) in parallel with the first gate (25) and that the fourth gate (28) is connected to the second memory array (2a) in parallel with the second gate (27), such that, in operation, when said first and second gates (25, 27) are open at the same time data are transferred between said first memory cell arrays (1a, 1b) and said first data registers (4a, 4b) and data are transferred between said second memory cell arrays (2a, 2b) and said second data registers (5a, 5b), and when said third and fourth gates (26, 28) are open at the same time, data are transferred between said first memory cell array (1a, 1b) and said second data registers (5a, 5b) and data are transferred between said second memory cell arrays (2a, 2b) and said first registers (4a, 4b). The semiconductor memory device according to claim 1, characterized in that said first gate has a pair of gates (43, 45) provided in a first bit line pair (31a, 31a ) connecting said predetermined one (1a) of said first memory cell arrays and said predetermined one (4a) of said first data registers, said second gate has a pair of gates (47, 49) provided in a second bit line pair (32a, 32a ) connecting said predetermined one (1b) of said second memory cell arrays and said predetermined one (4b) of said second data registers, said third gate has a pair of gates (44, 46) provided in a third bit line pair connecting said predetermined one (1a) of said first memory cell arrays and said predetermined one of said second data registers (5a), and said fourth gate has a pair of gates (48, 50) provided in a fourth bit line pair connecting said predetermined one (2a) of said second memory cell arrays and said predetermined one (4a) of said first data registers.

Inventors: WATANABE NOBUO, WATANABE, NOBUO
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1991
Main classification: G11C7
IPC codes: G11C11, G11C7