Dynamic voltage integration method and circuits for implementing and applying the same

Abstract: An integrating circuit is formed in the present invention, of which the active element is a pair of bipolar transistors (T5/T6) or a CMOS transistor (T8) which with the aid of switches (s81 to s88) controls the storing of a sample charge from the signal voltage (Us) in a sampling capacitor (Ci) and the discharging of the sample into an integrating capacitor (Co). The circuit only consumes current while charges are being transferred.

Description: The present invention relates to a method and circuit for producing a time integral of a signal voltage in which method charge samples are taken from the signal voltage as described in claim 1. The voltage integrator is an ordinary circuit implemented for instance using the CMOS technique. Voltage integration can be performed either by passive or active circuits. A passive circuit comprises only passive components, an example of which is disclosed in DE 2 933 667. An active circuit comprises at least one active component. An active voltage integrator is demonstrated by a prior art circuit shown in Fig. la using an operational amplifier. A similar active RC integrator is shown in US 3 286 100, in which a transistor is used as active component and the rate of charging the capacitor is affected by the current gain of the transistor. Further a diode is used for passing and blocking either positive or negative pulses. Fig. 1b shows an alternative prior art implementation based on the use of capacitors switched in discrete time. The output signal Uo of the integrator shown in Fig. 1a is the time integral of the input voltage Ui following the formula Similarly, the output signal Uo of the integrator shown in Fig. 1b is where fs is the sampling frequency. When the switches s1 and s4 are closed, and switches s2 and s3 are open, the sampling capacitor Ci stores a charge sample of the input signal . The sample charge (Qi = Ci x Ui) is discharged in the integrating capacitor Co by closing the switches s2 and s3 and switches s1 and s4 are now open. There may be pauses between the sample storing and sample discharge stages when all four switches s1 to s4 are open. A drawback related to state of art circuits presented in Figs 1a and 1b is that the amplifier continuously consumes power. Moreover, the amplifier is provided with a limited bandwidth which is generally proportional to the power consumption, and I/f noise harmful in the CMOS implementation. A method and circuit are disclosed in the invention as claimed in which the above drawbacks can be avoided. The design of the invention permits the integration circuits to be implemented without consuming any static current. Further a single active component controls both storage and discharge of charge samples. As taught by the invention, the integrating capacitance is isolated from the circuit by opening the switching elements after discharging each charge sample. In addition, the active members are switched in conductive connection with the supply voltage terminals only for storing the sample charge in the sampling capacitance, and discharging the sample charge into the integrating capacitor. A circuit based on this design needs no active amplifier, but the charge transfer from the sampling capacitance to the integrating capacitance is controlled by switching elements which, according to the invention, connect one of the sampling capacitance terminals to either the positive or the negative supply voltage. When the charge transfer is concluded the current stops entirely. According to an advantageous embodiment, the sampling capacitance is precharged by connecting it to the positive or the negative supply voltage for storing the sample charge. Another embodiment of the invention includes advantageously two charge sample discharge stages, whereby at the first stage a charge sample is conducted to an integrating capacitance only if it has a first sign (e.g. positive or negative), and whereby at the next stage a charge sample is conducted to the integrating capacitance only if it has the opposite sign (e.g. negative or positive), wherein the first sign is preselected. The sign of the charge of a sampling capacitance can be identified with a comparative circuit member, whereby depending on the identified sign only one of the two charge sample discharging stages is carried out. In a first embodiment of the integrating switching according to the present invention, the invention is implemented using a transistor as the switching element controlling the logical operation for discharging a sample charge In this embodiment the switching element connecting the sampling capacitance to the supply voltage is a bipolar transistor. In an alternative embodiment the switching element is a FET transistor. In a preferred embodiment, the switching element is an EPROM-type FET transistor having a floating gate arranged to carry a predetermined charge so that the threshold voltage of the FET transistor is of a desired magnitude, most preferably substantially zero. Hereby, the circuit operates almost ideally because e.g. the threshold voltage compensation needed for bipolar transistors is avoided. Examples of embodiments of the present invention will now be described with reference to the drawings in which: Figs 1a and 1b present prior art integrating circuits, Fig. 2 shows the stages of a method according to the invention by the aid of highly simplified, principle circuit diagrams; Figs. 3a, 3b, 3c, 3d, and 3e illustrate the operation of the integrating circuit at various stages of the method according to the invention; Fig. 4 shows a circuit diagram of the inverting integrator according to a preferable embodiment of the invention, based on a complementary pair of transistors and switches; Figs. 5a and 5b illustrate the operation of a circuit as shown in Fig. 4, whereby Fig. 5a shows the change in signal voltage and voltages affecting over the sampling capacitor at various operation stages of the integrating circuit. Fig. 5b shows the change in voltage affecting over the integrating capacitor, Fig. 6 presents a simplified circuit diagram of an inverting integrator as shown in Fig. 4 where for the integration cell an ideal CMOS switch is used, and Fig. 7 presents schematically the principle design of the ideal switch of Fig. 6 when implemented in the form of EPROM transistor Fig. 2 shows different stages of an example of the method of the invention by the aid of simplified principle circuit diagrams. In Fig. 2a, a sample (being either positive or negative) from an input signal Us is stored in a sampling capacitor Ci. The sample charge Qi = Us x Ci. For the sake of simplicity, it is assumed that the sampling charge is positive which is indicated by the + sign of one of the capacitor terminals. The other terminal is grounded at this stage. During the second stage, shown in Fig. 2b, the positive charge of the sampling capacitor Ci is discharged into an integrating capacitor Co by connecting the negative terminal of the sampling capacitor (in the present case) to the positive supply voltage +V and connecting the other (positive) terminal to the integrating capacitor Co by closing switch s1. A detector S is connected across Ci and keeps the switch s1 closed until the voltage of Ci has reduced to zero, whereby the detector S opens the switch s1. Thus the charge of the sampling capacitor Ci is transferred into the integrating capacitor Co. Were the sample charge negative, nothing would happen at this stage. The third stage, shown in Fig. 2c, is arranged by connecting the sampling capacitor Ci to the negative supply voltage -V for discharging the negative sample charge; were the charge positive, nothing would take place at this stage. The second (2b) stage and third (2c) stage of the method shown in Fig. 2 are controlled by detector S, which ensures that the sampling capacitor Ci is discharged to a predetermined limit. The method may be so altered that detector S indicates the sign of the charge, that is the polarity (e.g. positive or negative), as early as at the first stage. Hereby, said second and third stages are combined, which means that only one of said stages is carried out as expressed by the sign of the sample charge. The detector S could be a comparative member such as an operational amplifier or a comparator. When implemented in the above manner, the method would not give a crucially better result than the state of art method shown in Fig. lb because the noise of the amplifier would for instance at very low signals cover the signal. Instead, an advantage of the circuit of this embodiment is that the active element is only loaded by the input capacitances of the switches, not by the much bigger integrating capacitor Co. In the circuit and method of the invention the greatest advantage is that at the stages shown in Fig. 2, the supply voltage is only loaded by the detector S and switches s1, s2, and even these can be implemented advantageously e.g. using a single CMOS or bipolar transistor, as will be described below. Fig. 3 shows the function of different steps of the invention by the aid of simplified circuit diagrams having different transistors for different steps for more easy understanding of the different steps, which in Figs. 4 and 6, described later, are performed by a single transistor. In Fig. 3 switching members s11 - s42 and bipolar transistors T1 - T4 based on BiCMOS technique are used. Fig. 3 illustrates the operation of the integrating circuit at various stages of the method. All significant components are shown in Fig. 3, but in Figs 3a, 3b, 3d, 3e show only those components essential at each stage. The switching elements included in the circuit are controlled by means of devices and circuit designs familiar to those skilled in the art, so that said control members are omitted for clarity. The switching elements can also be implemented using the devices known to those skilled in the art, for instance by mechanical contacts or semiconductor switches. The signs (polarity, e.g., positive or negative) of the signals and voltages are indicated relative to earth potential (ground). The operation is described below on principle level through six different operation stages. The earth potential (ground) is assumed to be zero volts and the supply voltage polarities (positive Vd and negative Vs) are relative to the earth potential (ground). During stage 1 (Fig. 3a), Ci is charged to voltage Vd (the positive supply voltage) relative to earth potential (ground) by closing switches s10 and s12. The rest of the switches are now open. Thereafter, at stage 2 (Fig. 3a) voltage Uci(2) = Us(2) + Ube1 is charged in the sampling capacitor Ci, where Us is the signal voltage and Ube1 the base emitter voltage of the transistor T1 at the moment when power consumption through the transistor T1 during stage 1 stops. The parenthetical marking "(2)" of the capacitor Ci subsequent to the voltage Uci, refers to stage 2 and the plus sign in the drawing refers to the positive pole of the capacitor at each stage. Parenthetical indications of other stages are used below. At stage 2, the collector of the transistor T1 is connected to the negative supply voltage Vs and the switches s11 and s12 are closed. During stage 2 it is assumed that Us ≥ O, whereby Uci ≥ Ube1. During stage 3 (Fig. 3b) the charge of the sampling capacitor Ci is discharged into the integrating capacitor Co by closing switch s21 to connect the other terminal of the sampling capacitor Ci through the transistor T2 to the positive supply voltage Vd. The base of the transistor T2 is connected over a sampling capacitor Ci, whereby the passage of the current, or transfer of the charge, ends when the voltage across Ci is Uci(2) = Ube2, where Ube2 is the base emitter voltage of the transistor T2. At stage 3, the switches s21 and s22 have been closed. An additional charge dQ transferred to the integrating capacitor at stage 3 is therefore (assuming that the base current of transistor T2 at this stage is substantially zero): dQ(3) = Ci • (Us(2) + Ube1 - Ube2) When the base emitter voltages Ube1 and Ube2 of the transistors T1 and T2 are equal, the circuit integrates the charge dQ(2) = Ci x Us(2) produced by the input voltage Us into capacitance Co. The stages 2 and 3 which in operation correspond to the first and second stage described in relation to Fig. 2 require that the signal voltage Us is positive, owing to the polarity of the transistors T1 and T2. If Us during stage 2 is negative, the voltage of Ci remains lower than Ube1 during stage 2, and lower than Ube2 during stage 3 causing the transistor T2 to remain unconductive during stage 3. Therefore, no charge is transferred to the integrating capacitor Co during stages 1 to 3 if Us is negative. The voltage of the integrating capacitor Co during stages 1 to 3 is shown in Fig. 3c. The negative signal voltage Us is processed at stages 4, 5 and 6, these being equivalent to the first and third stages discussed in relation to Fig. 2. During stage 4, shown in Fig. 3d, the sampling capacitor Ci is charged to voltage Vs (the negative supply voltage). During stage 5, switches s31 and s32 are closed so the voltage charged into the sampling capacitor Ci is Uci(3) = Us - Ube3, where Ube3 is the base emitter voltage of the transistor T3. At stage 6 (Fig. 3e) the charge of the sampling capacitor Ci is discharged into the integrating capacitor Co, whereby switches s41 and s42 are closed so transistor T4 is connected to negative supply voltage Vs. After the termination of the discharge, the base emitter voltage Ube4 remains in the capacitor Ci, hence the charge transferred into the integrating capacitor Co is dQ(6) = Ci • (Us(5) - Ube3 + Ube4) When the base emitter voltages Ube3 and Ube4 of the transistors T3 and T4 are equal, the circuit integrates the input voltage Us into the capacitance Co. The integration circuit shown in Fig. 3 is preferable in that it consumes current only when sample charges are stored and discharged during stages 1 to 6. There may be pauses between the stages during which the circuit does not consume any current. In the implementation of the circuit like the one shown in Fig. 3 care has to be taken that the base emitter voltages of the transistor pairs T1/T2 and T3/T4 are selected to be of equal size. Similarly, the circuits must be dimensioned so the base currents of the transistors T2 and T4 controllably generate charging and discharging of the sampling capacitor Ci. This factor has been tested and found to exert a diminishing effect on the integration coefficient (order of magnitude less than 1%). The charge of the integrating capacitor Co is not affected by said base currents. It is useful to examine the effect of the balance of said base emitter voltages in such a situation in which the input signal Us = O, as shown in Fig. 3. In this case, the charge dQp = Ci • (Ube1 - Ube2), if Ube1 > Ube2 = O if Ube1 ≤ Ube2 is added to the integrating capacitor Co during stages 2 and 3 and the charge dQn = -Ci • (Ube3 - Ube4), if Ube3 > Ube4 = O if Ube3 ≤ Ube4 is added to the Co during stages 3 and 4. As shown in Fig. 3c, the base emitter voltage Ube1 is in the direct integrator approximately equal to Ube4, and Ube2 is approximately equal to Ube3; hence, of the charge differences dOn, dQp presented above, only one is integrated together with the signal value to the integrating capacitor Co. Therefore, asymmetric non-linearity may occur in the integrator if the base emitter voltages in the pairs are different from one another. An inverted integrator can be obtained from the circuit shown in Fig. 3 by reversing the order of performance of stages 3 (Fig. 3b) and 6 (Fig. 3e). Hereby, Ube 1 = Ube2 and Ube3 = Ube4 when no non-linearity mentioned above occurs in the inverted integrator. The direct integrator is presented in its entirety in Fig. 4 but the transistors T1 and T3, and transistors T2 and T4, have been combined into transistors T5 and T6 by using switches. The samplings to be taken from the input signal Us are conducted into the sampling capacitor Ci at different stages via transistor T5 or T6. They are then discharged into the integrating capacitor Co via the same transistor T5, resp. T6. To fully understand the operation of the integrating circuit shown in Fig. 4, the operation of the switches is indicated in the table below at stages 1 to 6 controlled by preselected operation frequency of a clock circuit (not shown). The status of the switches during each stage is shown in the table below. The sign "x" refers to a closed switch and a blank to an open switch. Stages Switch 1 2 3 4 5 6 1 s51 x x x x x s52 x x s53 x s54 x s55 x s56 x x s57 x s62 x s63 x s64 x s65 x s67 x At stage 2 a sample of the input signal Us is read into the sampling capacitor Ci via switch 54, transistor T5 and switch s53. One terminal of the sampling capacitor Ci is grounded via switch 51. At stage 3, the capacitors are coupled to one another with the switch s56 so the sample is discharged into the integrating capacitor Co. Transistor T6 is connected to the positive supply voltage Vd and the other terminal of the sampling capacitor Ci is connected to T6 via switch s63. Discharging is continued until the voltage of the capacitor Ci reaches the base emitter voltage of transistor T6 since the base of the transistor T6 is now coupled to a point between the capacitors Ci and Co via switch s65. At stage 4, the sampling capacitor Ci is precharged to the negative supply voltage Vs. At stages 5 and 6, the sample is read and discharged as above but now via transistor T6. At stage 1 the capacitor Ci is recharged to the positive supply voltage, whereby a new cycle starts again. The operation of the circuit according to Fig. 4 is also demonstrated in Figs. 5a and 5b where, as function of time t, the connections between the input signal Us, the voltage Uci affecting over the sampling capacitor Ci and the voltage Uco affecting over the integrating capacitor are presented in a time interval. On the time axis between Figs 5a and 5b is marked the order of stages 1 - 6. Fig. 5 is intended for clarifying the operation principle of the invention, therefore the voltage graphs are not exactly to scale. It is seen that the output voltage Uco (Fig. 5b) integratingly follows the input signal Us. Since in the circuit of Fig. 4, each switch s only processes either positive or negative voltage, the switches can in a manner known in the art be implemented using only one transistor for each switch so that the circuit of Fig. 4 is simpler than the circuit shown in Fig. lb. From the circuit shown in Fig. 3 a simple full wave rectifier is obtained so that instead of stage 6 (Fig. 3e), stage 3 is carried out and the integrating capacitor Co is set to zero prior to each integration step, unless the integration of the rectified voltage is wanted. Inversing said stages can also be carried out be performing the steps in reverse order, i.e. stage 6 is performed instead of stage 3. The circuit can also easily be transformed into an amplifier. A preferred circuit is a inverted amplifier free from non-ideal features. In the circuit the power consumption may, if needed, be further decreased, for instance by not carrying out the clock stages remaining passive according to the signal sign (e.g., polarity positive or negative) and not precharging the sampling capacitance Ci. Because in the circuit in Fig. 4 the charge and discharge stages are implemented in the same transistor T5, resp. T6, no potential non-ideality observed in Fig. 3 is associated with an individual sample. However, special care has to be taken in producing said circuit to make the base emitter voltages of PNP/NPN transistors T5, T6 the same because otherwise insecurity may occur in the vicinity of the zero cross-over points of the signal, that is, repetition of the voltage difference in one direction only. The circuit of Fig. 4 meets the wish presented at the beginning so that between the storing and discharge periods it will not consume any current. The circuit shown in Fig. 4 may be further enhanced by means of an inverted integrator in which the non-ideality caused by the threshold voltage differences of the NPN and PNP FET transistors is so eliminated that the threshold voltages of the transistors are made equal. If the threshold voltage is moreover zero, the completely separate processing of the negative and positive signal samples can be avoided. The inverting integrator shown in Fig. 6 is based on a CMOS transistor. A sample from the input signal Us is read into the sampling capacitor Ci by the aid of transistor T8 and switches s81 to s88. The sample is then sent into the integrating capacitor Co, which has one of the terminals fixedly coupled to the output where the inverted, integrated output signal Uo is obtained. The other terminal S (Fig. 7) of the transistor T8 is connected to the positive supply voltage Vd. In the switch table describing operation of the circuit, shown in Fig. 6, x at each stage 1 to 4 refers to a closed switch. At non-marked stages the switch is open: Stages Switch 1 2 3 4 s81 x s82 x s83 x s84 x s85 x x s86 x s87 x a88 x The operation of the circuit shown in Fig. 6 is different from the one shown in Fig. 5 in that both the positive and negative samples are processed at the same sampling stage. Stage 1 stores samples in the capacitor Ci, stages 2 and 3 discharge the samples depending on the terminal of the sample into the capacitor Co, and stage 4 charges the floating gate G1 of the transistor T8 (Fig. 7). At the charging stage (stage 4), the floating gate G1 of the transistor T8 is arranged to carry a predetermined charge which, in the case shown in Fig. 6, is brought to the gate G (Fig. 7) from the ground potential. The transistor T8 shown in Fig. 6 is provided with a slightly out of ordinary structure which is briefly described by the illustration in Fig. 7. The purpose of the figure is merely to demonstrate the principle structure with a strongly enlarged cross-sectional diagram; therefore, the figure is not to scale. The transistor is produced using e.g. the EPROM process known in the art. The CMOS transistor shown in Fig. 7 is provided with the following couplings: source S, drain D and gate G. Isolated between the gate G and base SUB is positioned the floating gate G1. At the charge stage 4 shown in Fig. 6 the floating gate G1 is arranged to carry a predetermined charge. Due to said floating gate, asymmetries possibly caused by conventional bipolar and FET transistors are avoided in the integrating circuit. A person skilled in the art understands with the aid of the figure the rest of the principle structure of the transistor and the other features of its operation. The transistor according to Fig. 7 may also be used in integrating circuits like those shown in Figs 2, 3 and 4, whereby their potential asymmetries change respectively. The circuit shown in Fig. 6 is, however, regarded to be more preferable because the number of the switching elements is smaller than in circuits 2, 3, and 4. With the aid of the circuits disclosed, filters, rectifiers, modulation detectors and other signal processing connections can be implemented. The operation of the circuits requires equal size of the base emitter voltages of the PNP and NPN transistors, which is possible to obtain especially in the case when the connection is implemented into one integrated circuit. A great advantage of the integrating circuits of the preferred embodiments is that they do not consume any static current. In addition, the circuits have only small noise level and a wide dynamics range. The circuit according to the invention using an integrating circuit requires only half of the space of what the designs known in the art require. These advantages make the invention ideal for small portable appliances, such as data detection and data filtering circuits of radio paging apparatus, speech processing circuits or modem circuits of radio telephones, and in other micro power applications. The power consumption P of the circuit according to the invention is approximately obtained using formula P = U 2 x Ctot x fs, where U is the supply voltage 5V, Ctot is the total capacitance 50 pF of the capacitor (Ci) of connectable a ten pole filter and fs is switch frequency 100 kHz. Hereby, the power consumption P = 125 ,uW, or order of magnitude of 10 ,uW per pole which can be regarded very small. The above described embodiment examples are intended to illustrate the invention. The extent of protection is determined by the terms of theclaims below.

Claims: A method for producing either one of an inverted and a direct time integral of a signal voltage, comprising the steps of: a. selectively connecting a sampling capacitance (Ci) to the signal voltage (Us); c. storing charge samples representing the signal voltage in the sampling capacitance (Ci) while connected; d. switching switch elements at predetermined intervals to selectively connect the sampling capacitance (Ci) to an integrating capacitance (Co); e. discharging the charge samples from the sampling capacitance (Ci) to the connected integrating capacitance (Co) while connected; f. isolating the integrating capacitance (Co) after the sample charge has been fully discharged, characterized by g. selecting timing of the switching elements so that current flows in the circuit only when one of the steps of storing and discharging is being performed, and h. controlling the storing and discharge of charge samples with an active component (T5 - T6, T8) so that when the charge transfer is concluded the current stops entirely, said step of controlling including storing charge samples representing the signal voltage in the sampling capacitance (Ci) via the active component, controlling the discharging of the charge samples from the sampling capacitance (Ci) to the integrating capacitance (Co), and the step of connecting the active component to any one of a positive voltage supply (+V, Vd), negative voltage supply (-V, Vs), and ground. The method according to claim 1, characterized in that before step c it further comprises the step of: b. precharging the sampling capacitance (Ci) by selectively connecting the sampling capacitance (Ci) to one of a positive (+V, Vd) and a negative (-V, Vs) supply voltage; The method according to claim 1, characterized in that said discharging in step e of the charge samples occurs in two stages: 1. a first stage conducting the sample charge to the integrating capacitance (Co) only when the sample charge has a first predetermined polarity, and 2. a second stage conducting the sample charge to the integrating capacitance (Co) only if the sample charge has a second, opposite predetermined polarity. The method according to claim 3, characterized in that it further comprises the step of identifying the polarity of the charge of the sampling capacitance before the discharging step. The method according to claim 3, characterized in that the discharging step e further includes performing only the first stage of said two stages if the sample charge has the first predetermined polarity and only the second stage if the sample charge has the second, opposite predetermined polarity. The method according to claim 1, characterized in that said discharging step e occurs for sample charges having either one of a first and a second predetermined polarity, and as a result of step g the signal voltage (Us) is rectified. The method according to claim 6, characterized in that it further includes the step of integrating the rectified signal voltages. An integrating circuit for producing either one of an inverted and a direct time integral of a signal voltage (Us), comprising a. a signal voltage (Us) input, b. a sampling capacitance (Ci), c. an integrating capacitance (Co), and d. first switch means connected in functional connection between the signal voltage (Us) input and the sampling capacitance (Ci) for selectively connecting the signal voltage (Us) to the sampling capacitance (Ci) for taking charge samples from the signal voltage and for storing the charge samples in the sampling capacitance (Ci), e. second switch means connected in functional connection between the sampling capacitance (Ci) and the integrating capacitance (Co) for selectively connecting the sampling capacitance (Ci) to the integrating capacitance (Co) for discharging the charge samples from the sampling capacitance (Ci) to the connected integrating capacitance (Co) while connected and for isolating the integrating capacitance (Co) after the sample charge has been fully discharged, characterized by comprising: f. means for timing the first and second switch means so that current flows in the circuit only when one of the steps of storing and discharging is being performed, g. an active component (T5 - T6, T8) for controlling the storing of the charge samples in the sampling capacitance (Ci) and the discharging of the charge samples from the sampling capacitance (Ci) to the integrating capacitance (Co) so that when the charge transfer is concluded the current stops entirely, and connected in functional connection between the signal voltage (Us) input and the sampling capacitance (Ci) for storing the charge samples in the sampling capacitance (Ci) via the active component, and h. means for connecting the active component (T5 - T6, T8) to any one of a positive voltage supply (+V, Vd), negative voltage supply (-V, Vs), and ground. A circuit according to claim 8, characterized in that it further comprises third switch means connected in functional connection between the sampling capacitance (Ci) and one of a positive (+V, Vd) and a negative (-V, Vs) supply voltage for selectively connecting the sampling capacitance (Ci) to one of the positive (+V, Vd) and the negative (-V, Vs) supply voltage to thereby precharge the sampling capacitance (Ci). A circuit according to claim 8, characterized in that the active component is a transistor (T5, T6 or T8).

Inventors: RAPELI JUHA, RAPELI, JUHA
Applicants: NOKIA MOBILE PHONES LTD, NOKIA MOBILE PHONES LTD.
Application year: 1991
Main classification: G06G7
IPC codes: G06G7, G01R19