Discriminating information from noise in a communication signal

Abstract: An apparatus for discriminating information signals from noise signals within a communication signal. The preferred embodiment comprises a first signal level detector (60,518), a second signal level detector (62,524), and a comparing circuit (576). Each of the signal level detectors comprises a digital low pass filter which employs a comparator (530) for comparing current signal samples with previous samples and generating a representative comparator output. Each low pass filter has an attack time and a decay time, each of which characteristics is determined by an operational coefficient, the coefficient being responsive to the comparator output. The first signal level detector receives the communications signal as an input and generates a detection signal as an output; the second signal level detector receives the detection signal as an input and generates a noise detection signal as an output. The comparing circuit compares the detection signal and the noise detection signal and produces a speech burst detection signal. The operational coefficient is valued in the first signal level detector to establish a fast attack time and a slow decay time, and the coefficient is valued in the second signal level detector to establish a slow attack time and a fast decay time.

Description: The present invention is directed to an apparatus for discriminating information signals from noise signals within a communication signal. The present invention, in its preferred embodiment, is intended for use with circuitry for facilitating communications between an analog device and a digital device, such as a hands-free speakerphone controller associated with a telephone system. A significant portion of telephone equipment manufacturing costs may be attributable to parts and equipment assembly. One approach to reducing costs is to provide a low-cost part which requires no external components. Incorporation of external components into an integrated circuit generally yields a device which is more stable in its operation, has good sensitivity, and is consistent in its performance. Additional advantages are realized when the integrated circuit is a digital circuit. Principal among such additional advantages are even further improved stability and programmability of various operational parameters associated with the circuitry. Digital programmability provides a versatile circuitry which may be easily tailored to be applicable to a wide variety of operational environments using a single integrated design. As a result, the development costs and manufacturing costs associated with the circuitry are much reduced since they are able to be spread across a wider variety of products. "A Technique for Voice Detection in a PCM Speakerphone" by D.E. Bush, Motorola Technical Developments, Vol. 5, No. 1, Schaumberg, Illinois, USA, October 1985, describes a technique whereby the absolute magnitude of a signal is used to derive a smoothed envelope which is compared with an envelope of the background noise (pages 8-9). The detector operates directly on digitally encoded PCM data in either serial or parallel form. The present invention concerns apparatus for use with a communications system for facilitating communications between an analog device and a digital device, such as hands-free controlled speakerphone circuitry, associated with a digital telephone system. In its preferred embodiment, the apparatus of the present invention provides precise speech level and background noise level signal detection. Further, the apparatus provides for precise speech burst detection, precise attack time and decay time for speech detection, and software programmability of a variety of operational parameters. Accordingly, we describe apparatus for discriminating information signals from noise signal within a communication signal. The apparatus preferably comprises a first signal level detector, receiving the communication signal as an input and generating an information level detection signal as an output, and a second signal level detector, generating a noise level detection signal as an output. The first signal level detector and the second signal level detector comprising comparators for comparing current signal samples with previous samples and generating and an output representative of the comparisons. The apparatus is characterised in that the first and second signal level detectors each comprise a digital low pass filter which operatively employs the comparators, the second signal level detector receiving the information level detection signal as an input. Each low pass filter has an attack time characteristic and a decay time characteristic, the attack time characteristic and the decay time characteristic being determined by a coefficient, the coefficient being responsive to the comparator output. The coefficient is valued in the first signal level detector to establish a fast attack time and a slow decay time relative to the attack time and the decay time in the second signal level detector, and the coefficient is valued in the second signal level detector to establish a slow attack time and a fast decay time relative to the attack time and the decay time in the first signal level detector. The values of the coefficients of the first and second signal detector digital low pass filters are digitally programmable. In its preferred embodiment, the apparatus is an integrated digital circuit having a variety of programmable operational parameters. The apparatus enables precise speech level detection, precise background noise level detection, precise speech burst detection, and has a programmable speech burst threshold capability. The apparatus also allows programmable precision attack time and programmable precision decay time parameters, and yet is inexpensive to manufacture. In the accompanying drawings, by way of example only:- Fig. 1 is a schematic diagram of an apparatus incorporating an embodiment of the present invention. Fig. 2 is a schematic diagram of a first embodiment of the present invention. Fig. 3 is a schematic diagram of the preferred embodiment of the present invention. Fig. 4 (a)-(c) are illustrations of representative signal wave forms in various loci within the apparatus of Fig. 2. In Fig. 1, an apparatus 10 for facilitating communications between an analog device (not shown) and a digital device (not shown) is illustrated. The apparatus 10 includes a transmit circuit 12, a receive circuit 14, and a control circuit 16. Transmit circuit 12 included an analog input 18 from an analog device (not shown), such as a microphone or the like, an analog-to-digital conversion circuit 20, a programmable gain amplifier 22, and a compression circuit 24 for compressing digital signals prior to passing the digital outgoing signals to a digital device (not shown), such as a digital telephone circuit, at output 26. Also included in transmit circuit 12 are an analog attenuator 30 and a digital attenuator 32. A booster amplifier 28 is included before analog attenuator 30 to increase the signal-to-noise ratio of the outgoing signal before it is treated by analog attenuator 30 or analog-to-digital conversion circuit 20. Receive circuit 14 receives digital signals from a digital device (not shown), such as a digital telephone network, at digital input 34. The received digital incoming signal is expanded by an expanding circuit 36 and is amplified by a programmable gain amplifier 38. Also included in receive circuit 14 is a limiter circuit 40 to limit excursion of the digital incoming signal, a digital-to-analog conversion circuit 42, and an analog output 44. Analog output 44 is connected to an analog output device (not shown), such as a loudspeaker, or the like. Also included in receive circuit 14 are an analog attenuator 50 and a digital attenuator 52. Control circuit 16 includes a hands-free controller circuit 54, an amplifier 56, an amplifier 58, a transmit speech detector 60, and a receive speech detector 62. Thus, control circuit 16 samples outgoing digital signals at junction 64 and samples incoming digital signals at junction 66. In operation, transmit circuit 12 accepts an outgoing signal as a differential analog input from a microphone (not shown) through analog input 18, performs analog-to-digital conversion of the outgoing signal by analog-to-digital conversion circuit 20, compresses the then-digital output signal by compression circuit 24, and presents the compressed digital output signal at digital output 26. The output signal also passes through analog attenuator 30 and digital attenuator 32, both of which are under control of hands-free controller circuit 54. Booster amplifier 28 boosts the outgoing analog signal level before analog-to-digital conversion circuit 20 performs its analog-to-digital conversion in order to improve conversion performance. Similarly, programmable gain amplifier 22 is placed in transmit circuit 12 before digital attenuator 32 in order that a user may adjust the final signal level of the outgoing digital signal, thereby further allowing for minimization of distortion and noise in the output digital signal produced at digital output 26. Receive circuit 14 accepts compressed digital incoming signals at digital input 34, expands the incoming digital signal by expanding circuit 36, passes the incoming digital signal through limiter 40, and performs digital-to-analog conversion by digital-to-analog conversion circuit 42 in order to provide an incoming analog signal to a loudspeaker (not shown) through analog output 44. The incoming signals also pass through digital attenuator 52 and analog attenuator 50, both of which are controlled by hands-free controller circuit 54. A programmable gain amplifier 38 and limiter 40 are placed before junction 66, the point at which incoming signals are sensed by control circuit 16, in order that hands-free controller circuit 54 can fairly compare outgoing transmit signals and incoming receive signal levels. Programmable amplifier 46 is provided in order to compensate for loudspeaker sensitivity, which measures output loudness for a given electrical input. Programmable amplifier 46 is placed after junction 66, the sensing point for incoming signals for control circuit 16, so that programmable amplifier 46 does not affect one-to-one comparison by control circuit 16 of outgoing signals and incoming signals. Further, programmable gain amplifier 46 is placed before digital-to-analog conversion circuit 42 in order to optimize performance of digital-to-analog conversion circuit 42. Transmit speech detector 60 samples signals from transmit circuit 12 and receive speech detector 62 samples signals from receive circuit 14. Amplifiers 56, 58 scale transmit signal levels and receive signal levels, respectively. Transmit speech detector 60 and receive speech detector 62 output to hands-free controller circuit 54 their respective scaled sampled transmit and receive signals. Addtionally, transmit speech detector 60 and receive speech detector 62 provide to hands-free controller circuit 54 an indication of whether the respective sampled transmit and receive signals comprise a speech signal or a noise signal. Signals of fairly constant amplitude over a 150 millisecond interval are generally presumed by the preferred embodiment of the present invention to be noise signals. Hands-free controller circuit 54 accepts the respective scaled sampled transmit and receive signal level information, as well as speech or noise signal type indications, from transmit speech detector 60 and receive speech detector 62. Information thus received is used by hands-free controller circuit 54 to determine allocation of losses among the various attenuators 30, 32, 50, 52. Hands-free controller circuit 54 provides three stable states and four transitional states of operation for the preferred embodiment of the present invention. Preferably, the three stable states are idle, transmit, and receive; and the four transitional states are transmit-up, receive-up, transmit-down, and receive-down. In the transmit stable state, analog attenuator 30 and digital attenuator 32 are forced to zero decibel loss, and analog attenuator 50 and digital attenuator 52 are forced to a programmable maximum loss. In such manner, hands-free controller circuit 54 allows the outgoing signal to pass through transmit circuit 12 without loss (theoretically), while any incoming signal received at digital input 34 is suppressed by subjecting it to a programmable maximum loss. In the receive stable state, on the other hand, analog attenuator 50 and digital attenuator 52 are forced to zero decibel loss, and analog attenuator 30 and digital attenuator 32 are forced to a programmable maximum loss in order that losses may be distributed to the transmit circuit 12 while allowing (theoretical) loss-free passage of incoming signals through receive circuit 14. In the idle stable state, each attenuator 30, 32, 50, 52 is forced to one-half the maximum programmable loss. In such a configuration, the apparatus is equally disposed to respond to transmit (outgoing) signals and to receive (incoming) signals. Throughout operation of the preferred embodiment of the present invention, digital attenuators 32, 52 may be modified according to volume control values programmed in hands-free controller circuit 54. The four transitional states established by hands-free controller circuit 54 are provided to ensure smooth transitions among the three stable states. During such transitions among the three stable states, losses in each attenuator 30, 32, 50, 52 are incremented or decremented appropriately to effect the correct transition, preferably in a series of 1.5 decibel steps, until a stable state is achieved by apparatus 10. In the preferred embodiment of the present invention, the losses among the various attenuators 30, 32, 50, 52 are distributed according to several rules: first, losses in analog attenuator 30 and analog attenuator 50 always sum to a constant, which constant is the programmable maximum loss. Further, losses in digital attenuator 32 and digital attenuator 52 sum to the same constant. Such conditions guarantee stability during voice switching operations and assist in ensuring linear analog-to-digital conversion. Second, at any given time, losses in analog attenuator 30 and digital attenuator 32 are the same and losses in analog attenuator 50 and digital attenuator 52 are the same. This second requirement allows hands-free controller circuit 54 to perform an unbiased comparison of transmit (outgoing) signal levels and receive (incoming) signal levels, thereby simplifying control circuitry within hands-free controller circuit 54. Total loss control by hands-free controller circuit 54 in each of transmit circuit 12 and receive circuit 14 is split evenly between attenuators 30, 32 and attenuators 50, 52 for several reasons. First, such even distribution of losses allows a two point sensing structure by providing a reliably detectable signal level at junctions 64, 66 in a configuration which is easily stabilized. As an additional benefit, cost of manufacture also decreases because any requirement for additional sensing points is eliminated. Further, even distribution between attenuators 30, 32 and attenuators 50, 52 provides an automatic voice control hysteresis which defines the ability of a receive speaker to override a transmit speaker, and vice versa. Third, such even distribution helps prevent clipping distortion in the analog-to-digital conversion process as well as increases resolution of such conversion. Finally, such even distribution enhances stability of the idle state so that hands-free controller circuit 54 may make an unbiased comparison of transmit (outgoing) signal levels and receive (incoming) signal levels. A further advantage of the all-digital circuitry of apparatus 10 is a capability to provide an interface 68 with a microprocessor (not shown). Interface 68 provides access for a microprocessor to automatically monitor the state of hands-free controller circuit 54 and provides access for a microprocessor to force hands-free controller circuit 54 to any given state by a register write to alter operational parameters utilized by hands-free controller circuit 54. It is precisely by such an access as may be provided by interface 68 that a microprocessor may be used to program operational parameters of a given apparatus 10 to adapt apparatus 10 to accommodate different operating environments. That is, change in applicability of apparatus 10 to accommodate different operating environments may be effected through using software to vary performance rather than by changing hardware. Indeed, such programmability allows operational parameters to be changed during the actual operation of a phone. Thus, alteration of operational parameters may, for example, enable the apparatus 10 to function as a normal full-duplex telephone, a simple transmitter, a simple receiver, or in its normal speakerphone function by employing software programming to change operational parameters. The present invention is an apparatus appropriate for employment as transmit speech detector 60 or receive speech detector 62 of apparatus 10. Fig. 2 is a schematic diagram of a first embodiment of the present invention. In Fig. 2, an apparatus 510 for discriminating information signals from noise signals within a communication signal is illustrated. A digital input signal is applied to apparatus 510 at input 512 of an absoluter 514. Accordingly, absoluter 514 produces an output at 516 which comprises the absolute value of the signal applied at input 512. The signal appearing at output 516 is applied to a first signal level detector circuit 518. First signal level detector circuit 518 produces an output at juncture 520. The signal present at juncture 520 represents a speech level detector signal y(nT) and is produced as an output of apparatus 10 at output 522, as well as being applied as an input to a second signal level detector circuit 524. Second signal level detector circuit 524 produces a signal at output 526 which is an indication of speech burst detection. First signal level detector circuit 518 is comprised of a gain block 528 which receives the signal at output 516. The signal at output 516 is also applied to the negative input of a comparator 530. A feedback line 532 is operatively connected in common with junction 520 and to a one sample period delay circuit 534. One sample period delay circuit 534 delays the signal present at juncture 520 by one sample period and applies that delayed signal on line 536 to the positive input of comparator 530 as well as to the input of a gain block 538. Thus, first signal level detector circuit 518 is an adaptive IIR low pass filter with a dynamically controlled pole location (i.e., time constant of the filter impulse response), which dynamic control is effected by the output 540 of comparator 530. The output 542 of gain block 538 and the output 544 of gain block 528 are each applied to a summer 546. Summer 546 sums the two gain block output signals 542, 544 to produce output signal y(nT) at juncture 520. Referring briefly to Fig. 4, Figs. 4(a)-(c) illustrate representative signals at various loci within apparatus 10, illustrated at Fig. 2. Specifically, Fig. 4(a) illustrates signal wave forms involved in the portion of apparatus 510 described thus far. That is, in Fig. 4(a), in response to an input signal 700 at input 512 of absoluter 514, output 520 of first signal level detector circuit 518 will appear as signal 702 of Fig. 4(a). Referring to Fig. 2, this is so because gain blocks 528, 538 have associated therewith a coefficient which determines the respective attack times and decay times of first signal level detector circuit 518. For first signal level detector circuit 518 the coefficient is chosen specifically to provide a fast attack time and slow decay time to produce a signal as signal 702 of Fig. 4(a). Specifically, the mathematical description of the function of the first signal level detector circuit 518 is: y(nT) = a * p(nT) + (1-a) * y(nT-T), where a is the coefficient associated with gain block 528, and the coefficient associated with gain block 538 (which is responsive to output 540 of comparator 530) is (1-a). The choice of the coefficient a is preferably made as follows: if p(nT) ≥ y(nT-T) then a = 0.0625, and if p(nT) < y(nT-T), then a = 0.002. Second signal level detector circuit 524 is constructed substantially the same as first signal level detector 518. Second signal level detector circuit 524 receives speech level detection signal y(nT) which is present at juncture 520 as an input to a gain block 548, as well as to the positive input of a comparator 550. A feedback line 552 is provided to a one sample period delay circuit 554. One sample period delay circuit 554 provides an output on line 556 to the negative input of comparator 550 as well as to the input of gain blocks 558 and 548. The output 560 of comparator 550 dynamically controls the pole position of second signal level detector circuit 524. Output 562 of gain block 558 is added with output 564 of gain block 548 by summer 566 to produce an output of second signal level detector circuit 524 at juncture 568. The output at juncture 568 is applied as an input to a comparing circuit 570. Referring briefly again to Fig. 4, wave form 704 illustrated in Fig. 4(b) is representative of the wave form of the signal present at juncture 568 of apparatus 510. As reference to Fig. 2 reveals, this is so because the coefficients of gain block 548 and gain block 558 are chosen to ensure that second signal level detector circuit 524 has a slow attack time and a fast decay time relative to the attack time and decay time of first signal level detector circuit 518. Thus, the mathematical description of the operation of second signal level detector circuit 524 is: z(nT) = b * y(nT) + (1-b) * z(nT-T), where b is the coefficient associated with gain block 548 and (1-b) is the coefficient associated with gain block 558. The choice of the coefficient b is preferably made as follows: if y(nT) ≥ z(nT-T), then b = 0.002, and if y(nT) < z(nT-T), then b = 0.0625. Comparing circuit 570 includes a gain block 572 which is employed to set sensitivity of burst detection control associated with the signal z(nT) present at juncture 568. Gain block 572 produces an output z'(nT) at line 574 which is applied as the negative input to a comparator 576. Output z'(nT) is represented as a threshold signal 705 in Fig. 4(b). The positive input to comparator 576 is the speech level detection signal y(nT) present at juncture 520. The output 526 of comparator 576 is illustrated in Fig. 4(c) as signal 706 and comprises a digital pulse which is initiated by the surpassing by signal 702 of threshhold signal 705 (which is set by the sensitivity control imposed by gain block 572) and ceases at the point where signal 705 becomes equal to signal 702 (signal 702 representing speech level detection signal y(nT), and signal 705 representing a multiple of noise level detection signal z(nT)). The fast attack time and slow decay time established by the representative choices of the coefficient a in connection with first signal level detector circuit 518 ensure that relatively rapid changes in signal level, which types of signals are associated with speech representing signals, are detected and responded to. The slow attack time and fast decay time established for second signal level detector circuit 524 by appropriate choice of the coefficient b ensures that second signal level detector circuit 524 responds to longer-term variations signal levels, such as are characteristic of background noise signals. Thus, the signal y(nT) present at juncture 520 is representative of speech level detection, and the signal z(nT) present at juncture 568 is representative of background noise signal levels. Accordingly, output 526 of comparator 576 represents the presence of a speech burst where speech level detection signal y(nT) exceeds background noise level detection signal z'(nT). Fig. 3 is a schematic diagram of the preferred embodiment of the present invention. Referring to Fig. 3, an apparatus 600 is illustrated having a first signal level detector circuit 602, a second signal level detector circuit 604, and a comparing circuit 606. First signal level detector circuit 602 is an equivalent circuit of first signal level detector circuit 518 of Fig. 2. First signal level detector circuit 518 of Fig. 2 might establish an unstable loop if f(a) + f(1-a) > 1 , where f(x) is the digital representation of real number x. However, first signal level detector circuit 602 of Fig. 3 avoids such a potential for unstable operation. A digital input signal is applied to input 612 of an absoluter 614 and an absolute value representation of the digital input signal at input 612 is produced at output 616 of absoluter 614. A digital speech level detection signal y(nT) is produced at juncture 620 and provided at output 622. Second signal level detector circuit 604 is similar in construction to first signal level detector circuit 602. Second signal level detector circuit 604 is an improvement over second signal level detector circuit 524 of Fig. 2 in its avoidance of a potential unstable operational mode if the coefficient b is improperly chosen, similar to the reason that first signal level detector circuit 602 improves over first signal level detector circuit 518 of Fig. 2. Accordingly, first signal level detector circuit 602 is comprised of a subtractor 608 to which is applied the output of absoluter 614 and a one sample period delay signal provided via line 610, one sample period delay circuit 618, and line 624. The output of absoluter 614 is also applied to the negative input of comparator 626. The one sample period delay signal is applied to the positive input of comparator 626, and the output 628 of comparator 626 adjusts the gain of gain block 630, thereby altering the pole position of first signal level detector circuit 602. Gain block 630 receives as its input the output 632 of subtractor 608. The output 634 of gain block 630 is applied to summer 636; the one sample period delay signal is also applied to summer 636 by line 638. The output of summer 636 is speech level detection signal y(nT) at juncture 620. Speech level detection signal y(nT) is applied as an input to second signal level detector circuit 604 at subtractor 640, as well as applied at the positive input of comparator 642. The output 644 of subtractor 640 is applied to a gain block 646. The output 648 of comparator 642 dynamically adjusts the gain of gain block 641, thereby altering the pole position of second signal level detector circuit 604. The output 650 of gain block 646 is applied to a summer 652. A one sample period delay signal is applied via line 654, one sample period delay circuit 656, and line 658 to subtractor 640. The one sample period delay signal is also applied to summer 652 by line 660. Further, the one sample period delay signal is applied to the negative input of comparator 642. Thus, the output 662 of summer 652 comprises the background noise level detection signal z(nT) at juncture 664. A gain block 666 is included in comparing circuit 606 to set sensitivity of burst detection and the output 668 of gain block 666 (a sensitized background noise level detection signal z'(nT)) is applied to the negative input of a comparator 670. Speech level detection signal y(nT) is applied to the positive input of comparator 670, so that the output 672 of comparator 670 comprises speech burst detection signal 706, as represented in Fig. 4(c). It is to be understood that, while the detailed drawings and specific examples given describe preferred embodiments of the invention, they are for the purpose of illustration only, that the apparatus of the invention is not limited to the precise details and conditions disclosed and that various changes may be made therein without departing from the scope of the invention which is defined by the following claims:

Claims: An apparatus (510,600) for discriminating information signals from noise signals within a communication signal; the apparatus comprising: a first signal level detector means (518,602) for detecting signal levels, said first signal level detector means receiving said communication signal as an input and generating an information level detection signal as an output; a second signal level detector means (524,604) for detecting signal levels, said second signal level detector means generating a noise level detection signal as an output; said first signal level detector means (518,602) and said second signal level detector means (524,604) each comprising comparator means (530,550; 626,642) for comparing current signal samples with previous samples and generating a comparator output representative of said comparing; characterised in that said first and second signal level detector means (518,602; 524,604) each comprise a digital low pass filter which operatively employs said comparator means (530,550; 626,642), said second signal level detector means (524,604) receiving said information level detection signal as an input, each said low pass filter having an attack time characteristic and a decay time characteristic, said attack time characteristic and said decay time characteristic being determined by a coefficient, said coefficient being responsive to said comparator output; said coefficient being valued in said first signal level detector means (518,602) to establish a fast attack time and a slow decay time relative to said attack time and said decay time in said second signal level detector means, and said coefficient being valued in said second signal level detector means (524,604) to establish a slow attack time and a fast decay time relative to said attack time and said decay time in said first signal level detector means, the values of said coefficients of said first and second signal detector digital low pass filter means being digitally programmable. Apparatus as claimed in claim 1 wherein each said digital low pass filter of said first and said second signal level detector means (518,524) receives an input signal and provides an output signal and further comprises summing means (546,566) for summing signals, delay means (534,554) for delaying signals, and gain means (528,538,548,558) for modifying the amplitude of signals; said input signal being operatively delivered to said gain means (528,538,548,558) and said comparator means (530,550), said delay means (534,554) being operatively connected to receive said output signal and provide a previous sample of said output signal, said comparator means (530,550) comparing the input signal and the previous sample of the output signal and generating a comparison signal representative of said comparing, said gain means (528,538,548,558) receiving said comparison signal and establishing the value of said coefficient responsive to the comparison signal, and said gain means (528,538,548,558) firstly modifying the amplitude of the input signal by the value of said coefficient to generate a modified input signal and secondly modifying the amplitude of said previous sample of the output signal by a value determined by said coefficient to provide a modified previous sample of said output signal, said summing means (546,566) receiving said modified input signal and said modified previous sample of said output signal to generate said output signal. Apparatus as claimed in claim 2 wherein said value, determined by said coefficient, by which the amplitude of said previous sample of said signal level detection signal is modified, is substantially equal to one minus the value of said coefficient. Apparatus as claimed in claim 1 wherein each said digital low pass filter of said first and said second signal level detector means (602,604) receives an input signal and provides an output signal and further comprises summing means (636,652) for summing signals, delay means (618,656) for delaying signals, subtracter means (608,640) for subtracting signals and gain means (630,646) for modifying the amplitude of signals; said input signal being operatively delivered to said subtracter means (608,640) and said comparator means (626,642), said delay means (618,656) being operatively connected to receive said output signal and provide a previous sample of said output signal, said comparator means (626,642) comparing the input signal and the previous sample of the output signal and generating a comparison signal representative of said comparing, said subtracter means (608,640) receiving said input signal and said previous sample of said output signal and providing an output, said gain means (630,646) receiving said comparison signal and establishing the value of said coefficient responsive to the comparison signal and said gain means (630,646) modifying the output of said subtracter means (608,640) by the value of said coefficient to generate a modified subtracter means output, said summing means (636,652) receiving said modified subtracter means output and said modified previous sample of said output signal to generate said output signal. Apparatus as claimed in any one of claims 1 to 4 wherein said apparatus further comprises an information detection comparator means (570,606) for comparing signals, said comparator means receiving said information level detection signal and said noise level detection signal and producing an information detection signal as an output. Apparatus as claimed in claim 5 wherein said information detection comparator means (570,606) comprises gain means (572,666) for defining the sensitivity of said information detection comparator means in producing said information detection signal.

Inventors: CHEN HERBERT M, HENDRICKSON ALAN F, CHEN, HERBERT M., HENDRICKSON, ALAN F.
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1991
Main classification: H04M9
IPC codes: H04M9, H04M1