Lateral bipolar transistor structure including an integrated control circuit and integrated power transistor and associated manufacturing process

Abstract: The present invention calls for the presence in a semiconductor material chip of a first buried region (3) having a first type of conductivity, second regions (6) of the same type of conductivity joining the first region with the surface of the chip, said first and second regions acting as regions insulating the control circuit, as well as the presence of a third region (4) of the opposite type of conductivity delimited by the aforesaid first and second regions. In order to minimize resistance between the base of the parasite transistor and the insulation terminal and thereby avoid the danger of firing of said transistor the structure of the transistor with lateral current flow has: a fourth region (8) having said first type of conductivity acting as the base region and provided within said third region (4), a fifth region (12) having the second type of conductivity provided in said fourth region (8) acting as the collector region, a sixth region (11) having the second type of conductivity provided in said fourth region (8) acting as the emitter region, a seventh region (10), with channel-stop function, having the first type of conductivity and more highly doped than said fourth region (8) and having annular geometry following the perimeter of said fourth region (8).

Description: The object of the present invention is a bipolar transistor structure with lateral current flow for a monolithic semiconductor device including an integrated control circuit and at least one integrated power transistor in the same chip and a associated manufacturing process. In known monolithic devices of the above mentioned type the control circuit usually comprises several low voltage npn transistors and a horizontal insulation region of type p achieved by selective dopant implantation and subsequent diffusion. This region gives rise together with the collector region of the power transistor and the collector region of a transistor of the integrated control circuit to an npn parasite transistor the firing of which must be avoided. A structure of an integrated circuit with improved insulation among components is described in EP-A-351331. According to said structure each component is realized inside a caisson region of a first type of conductivity laterally insulated from the other caisson regions by insulating walls, and formed on the surface of a layer of a second type of conductivity, said layer being realized on a substrate which is even of the second type of conductivity but with a higher concentration of dopant. The object of the present invention is to provide a new monolithic semiconductor device comprising a control circuit and at least one integrated power transistor in the same chip, which prevents firing of the parasite npn transistor by minimizing the resistance between its base and the insulation terminal, normally grounded, and its current gain as well. Said monolithic semiconductor device comprises integrated in the same chip: at least one power transistor, one control circuit including a bipolar transistor with lateral current flow and which comprises a first buried region (3) and second regions (6) joining the perimeter of said first buried region (3) with the surface of the chip, having both a first type of conductivity and both formed in a substrate of a second conductivity type and both acting as insulation regions of said control circuit, a third region (4) of the second type of conductivity opposite the first one and within said first and second regions (3,6) and reaching the surface of the chip. a fourth region (8) having said first type of conductivity, acting as the base region and provided within said third region (4) and extending from the chip surface, a fifth region (12) having the second type of conductivity, provided in said fourth region (8), acting as the collector region and extending from the chip surface, and a sixth region (11) having the second type of conductivity, provided in said fourth region (8), acting as the emitter region and extending from the chip surface. The structure of said bipolar transistor with lateral current flow is characterized by the presence of: a seventh region (10) extending from the chip surface and having the first type of conductivity and being more highly doped than said fourth region (8), having annular geometry, surrounding and being in contact with the perimeter of said fourth region (8) and with channel-stop function. A manufacturing process for said monolithic semiconductor device is set out in claims 7 and 8, respectively. Preferred embodiments are defined in the dependent claims. The characteristics of the invention will be clarified by the description given below and the annexed drawings of examples of a nonlimiting embodiment wherein: FIG.1a shows the structure of a monolithic semiconductor device in accordance with the known art, FIG.1b shows the equivalent circuit of the structure of FIG. 1a, FIG.2 shows the structure of a first example of a monolithic semiconductor device in accordance with the present invention, FIGS.3 to 6 show the steps of a process of an embodiment of the structure of FIG. 2, FIG.7 shows the equivalent circuit of the structure of FIG. 2, FIG. 8 shows the structure of a second example of a monolithic semiconductor device in accordance with the present invention, FIGS. 9-12 show some steps of a process realizing the structure of FIG. 8, and FIG.13 shows the structure of a third example of a monolithic semiconductor device in accordance with the present invention. A structure of a monolithic semiconductor device in accordance with the known art (as described e.g. in EP-B-322040) is shown in FIG. 1a. For the sake of simplicity a single component of the control circuit (a low voltage npn transistor with vertical current flow) and a single power transistor (also an npn transistor) are shown. FIG. 1b shows the electrical equivalent of the above structure. In addition to the transistor Tp and the transistor Tl of the control circuit it shows the npn parasite transistor T' (whose collector, base and emitter regions are made up respectively of the regions 1+2, 4 and 3+5+5a), which are typical of the insulation structure, and the resistance between its base and the insulation terminal ISO, which is generally grounded. It is therefore necessary to avoid that this transistor (as also the reverse) goes into conduction, and for this purpose it is necessary to minimize: resistance between the base of said transistor and the insulation terminal of the monolithic device, normally grounded; its current gain. The values of these two magnitudes are both rather high and their reduction by optimization of the process parameters is only partial. As may be seen in FIG. 2, in which the power transistor is not shown, a structure in accordance with the present invention differs from the known one of FIG. 1 because of the elimination of the buried type N layer (buried layer 3 of FIG. 1a) and the fact that the npn transistor of the control circuit has horizontal current flow instead of vertical (as in the npn transistor of FIG. 1a). The process sequence according to the present invention is shown schematically in figures 3 to 6 wherein for the sake of simplicity a single component 7 of the control circuit (a low voltage npn transistor) is shown. Said sequence consists of: 1) Epitaxial growth of a layer 2 of type N on a substrate 1 having the same type of conductivity (FIG. 3). 2) Implantation of type P dopant on the preceding epitaxy 2 of type N (FIG. 3). 3) Diffusion of the type P dopant as set forth in step 2) above to create a buried region 3 of type P designed to act as a horizontal insulation region of the control circuit (FIG. 3). 4) Provision of a second epitaxial growth of type N (layer 4 of FIG. 3). 5) Implantation and subsequent diffusion of type N dopant to create the N-well 5 (FIG. 3). 6) Implantation and subsequent diffusion of type P dopant to define the insulating regions 6 enclosing, together with region 3, a region 4. 7) Implantation and subsequent diffusion of type N dopant to provide the regions 7 of type N channel-stop (FIG. 3). 8) Oxidation of the surface (layer of SiO 2 indicated by reference number 111 in FIG. 3) and opening of a window, implantation and diffusion of type P dopant for formation of the base region 8 (FIG. 4). 9) Formation of a type P region with annular geometry following the perimeter of the base region 8 formed in step 8 for definition of the base contact and channel stop region 9 and channel-stop region 10 (FIG. 5). 10) Opening of two windows in the base region, implantation and diffusion of type N dopant for formation of the emitter region 11 and collector region 12 (FIG. 6). The latter step is followed by definition of the contact areas and metallization of the front and back of the slice. It is pointed out that between the above steps 3) and 4) there is normally inserted a step of implantation and subsequent diffusion of a type N dopant to provide a buried type N layer outside the region designed to house the npn transistor with lateral current flow which is the object of the present invention, a buried layer designed for the embodiment of other components in the control circuit and provided in accordance with the known art. FIG. 7 shows the equivalent electrical diagram of the embodied structure. T represents therein the npn lateral transistor which is the object of the present invention, T1 the parasite npn transistor (whose collector, base and emitter regions consist of the regions 1+2, 3 and 4+5+7 respectively of FIG. 2), and T 2 the associated vertical npn transistor (whose collector, base and emitter regions consist of the regions 5, 8 and 11 respectively). There can be noted the main advantage which consists of the enormous reduction of current gain of the parasite npn transistor (gain which, it is recalled, is equal to the product of the injection efficiency and the transport factor in the base). Indeed, both the injection efficiency (since the emitter region is of type N instead of N+) and the transport factor in the base are reduced since the quantity of electrically active dopant contained in this region is considerably increased following elimination of the buried type N layer (region 3 of FIG. 1a). The latter circumstance is also extremely useful in reduction of the base resistance, which also minimizes potential drops resulting from the passage of current and hence the probability of active region polarization of the parasite npn transistor. Finally, again for the same reasons, the gain of the reverse npn parasite transistor i.e. the gain obtained by exchanging the emitter and collector terminals, is substantially reduced. As a variation on the invention there can be provided a selective enrichment of the base region around the emitter, obtaining in this manner the following advantages: limitation of the gain of the associated vertical npn transistor (see FIG. 7 again), increase in Vearly, minimization of the distance of the emitter and collector regions necessary to avoid punch-through, creation of a concentration gradient in the base to improve the gain characteristics, current range and frequency response. In the process which is the object of the variation the emitter region and the base region surrounding the emitter can be the selfaligning type. The structure of the lateral npn transistor with base enrichment around the emitter is shown in FIG. 8. A possible sequence of the process which is the object of the present variation is illustrated in FIGS. 9 to 12. Said process coincides with that previously described for the structure of FIG. 3 in the first steps and specifically steps 1 to 8. As concerns the subsequent steps it continues as follows: 9) Definition and implantation of a type P region with annular geometry following the perimeter of the base region 8 defined in the previous step 8 for embodiment of the region 9' for base and channel stop contact, and channel stop 10' (FIG. 9). 10) Definition of a window 112 in the layer 111 of SiO 2 overlying the base region defined in the above step 8 for formation of the collector region (FIG. 10). 11) Definition and implantation through resist (layer 13) and the oxide layer (layer 111) of two type N regions for formation of the emitter region 11' and the collector region 12' (FIG. 11), and 12) removal of the layer 13 of resist, diffusion of the emitter and collector regions and base enrichment (FIG. 12). There follow definition of the contact areas and metallization of the front and back of the slice. As shown in FIG. 13 the structure in accordance with the present invention in its main embodiment as well as in the variation described can be used for the integration of diodes. In this case the base and collector regions are short-circuited with the epitaxial layer so as to prevent current injection on the insulation region (A 1 and C 1 in FIG. 13 represent the anode and cathode of the integrated diode).

Claims: Monolithic semiconductor device with bipolar transistor structure with lateral current flow comprising integrated in the same chip: at least one power transistor, one control circuit including a bipolar transistor with a lateral current flow and which comprises a first buried region (3) and second regions (6) joining the perimeter of said first buried region (3) with the surface of the chip, having both a first type of conductivity and both being formed in a substrate of a second conductivity type and both acting as insulation regions of said control circuit, a third region (4) of the second type of conductivity opposite the first one and within said first and second regions (3,6) and reaching the surface of the chip, a fourth region (8) having said first type of conductivity, acting as the base region and provided within said third region (4) and extending from the chip surface, a fifth region (12) having the second type of conductivity, provided in said fourth region (8), acting as the collector region and extending from the chip surface, and a sixth region (11) having the second type of conductivity, provided in said fourth region (8), acting as the emitter region and extending from the chip surface, characterized by the presence of: a seventh region (10) extending from the chip surface and having the first type of conductivity and being more highly doped than said fourth region (8), having annular geometry, surrounding and being in contact with the perimeter of said fourth region (8) and with channel-stop function. Bipolar transistor structure in accordance with claim 1 characterized in that in said third region (4) there is provided an eighth region (5) of the second type of conductivity, reaching the chip surface and more highly doped than said third region (4) said fourth (8) and said seventh (10) regions being provided within said eight region (5). Bipolar transistor structure in accordance with claim 2 characterized in that along the perimeter of said eighth region (5) there is a ninth region (7) of the second conductivity type and being more heavily doped than said eighth one (5), and having annular geometry with the function of channel stop. Bipolar transistor structure in accordance with any of the above claims characterized in that in said fourth region (8) there is a tenth region (9) having the first type of conductivity and more highly doped than the fourth region (8), acting as the base contact region. Bipolar transistor structure in accordance with claim 4 characterized in that said sixth region (11) partially overlies said tenth region (9). Bipolar transistor structure in accordance with claim 4 characterized in that said sixth region (11') is entirely contained in said tenth region (9'). Manufacturing process for a monolithic semiconductor device in which are integrated in the same chip: at least one power transistor, a control circuit which comprises : a first buried region (3) and second regions (6) joining the perimeter of said first buried region (3) with the surface of the chip and having both a first type of conductivity and acting as insulation regions for said control circuit, a third region (4) having the second type of conductivity opposite the first one and within said first and second regions (3,6) and reaching the surface of the chip, and at least one bipolar transistor with lateral current flow making up part of said control circuit and provided in said third region (4), the method comprising the following steps: a) epitaxially growing a first layer (2) having the second type of conductivity on a substrate (1) having the same type of conductivity, b) implanting a second type of dopant having the first conductivity type on said first layer (2), c) diffusing the dopant having the first type of conductivity as set forth in step b) above to create said first buried region (3) having the first type of conductivity, d) realizing a second layer (4) having the second type of conductivity by epitaxial growth on said first layer (2), e) implanting and subsequently diffusing dopant having the second type of conductivity to create a fourth region (5) in said second layer (4) and over said first region (3), f) implanting and subsequently diffusing dopant having the first type of conductivity to define said second regions (6) joining the perimeter of said first buried region (3) with the chip surface, g) implanting and subsequently diffusing dopant having the second type of conductivity to provide fifth regions (7) of channel-stop along the contour of said fourth region (5), h) forming a surface layer (111) of SiO 2 on said second layer (4), i) opening a window in said layer (111) of SiO 2 over said fourth region (5), l) implanting and diffusing dopant of the first type of conductivity for formation of a sixth region (8) designed to act as the base region of said control circuit transistor, m) forming a further region (9,9',10,10') having the first type of conductivity and more highly doped than said sixth region (8) and with annular geometry and surrounding and in contact with the perimeter of said sixth region (8) comprising a seventh region (9,9') with base contact and channel-stop function and an eighth region (10,10') with channel-stop function, n) opening two windows in said layer (111) of SiO 2 over said sixth region (8), implanting and diffusing dopant having the second type of conductivity for formation of a ninth region (11,11'), and a tenth region (12, 12'), to act as the emitter and the collector of said control circuit transistor, respectively. Manufacturing process for a monolithic semiconductor device in accordance with claim 7, in which step n) is replaced these further steps: n1) defining an opening (112) in the layer (111) of SiO 2 over said sixth region (8), n2) depositing a layer (13) of resist, n3) defining and implanting, shielded by the layers (13) of resist and (111) of SiO 2 , a ninth region (11') and a tenth region (12') respectively representing the emitter region and the collector region of said control circuit transistor, and n4) removing said resist layer and diffusing said ninth region (11'), tenth region (12') and seventh region (9').

Inventors: ZAMBRANO RAFFAELE, ZAMBRANO, RAFFAELE
Applicants: CONS RIC MICROELETTRONICA, CONSORZIO PER LA RICERCA SULLA MICROELETTRONICA NEL MEZZOGIORNO
Application year: 1991
Main classification: H01L27
IPC codes: H01L27, H01L29, H01L21