Scrambling/descrambling circuit

Abstract: A scrambling/descrambling circuit that may be manufactured as a CMOS arrangement in LSI format and free of constraints on the degree of the generating polynomial involved. Scrambled (or descrambled) "m" bits of data output by registers are multiplied by multiplication circuits by a factor of the generating element α m of the generating polynomial. The multiplied data are input back to the registers. The scrambled "m" bits of data are supplied to "m" exclusive-OR gates for exclusive-OR operation with input data.

Description: The present invention relates to a scrambling/descrambling circuit for data transmission under a clock recovery (self-clock) scheme. Fig. 8 is a block diagram of a known data transmission system. In Fig. 8, a transmitting side processing circuit 31 receives data to be transmitted, such as audio data and video data. The processing circuit 31 encodes and multiplexes the received data for output. A scrambling circuit 32 scrambles the data coming from the transmitting side processing circuit 31 and outputs the scrambled data to a modulator 33. The modulator 33 modulates the received data in accordance with a predetermined format and places the modulated data onto transmission lines of satellite, optical fiber and microwave circuits and the like. A demodulator 34 demodulates the received signal and sends the demodulated data to a descrambling circuit 35. The descrambling circuit 35 descrambles the data it receives and outputs the descrambled data to a receiving side processing circuit 36. The receiving side processing circuit 36 decodes and branches the descrambled data it receives into the original audio data, video data and others. A bit clock reproduction circuit 37 reproduces a bit clock signal from the data it receives from the demodulator 34. The bit clock signal is sent to a frame synchronization protection circuit 38, to the descrambling circuit 35 and to the receiving side processing circuit 36. The frame synchronization protection circuit 38 detects a frame signal from the data it receives from the demodulator 34. The detected frame signal is output to the descrambling circuit 35 and the receiving side processing circuit 36. The descrambling circuit 35 and the receiving side processing circuit 36 perform various kinds of processing by use of the reproduced bit clock signal from the bit clock reproduction circuit 37 and of the detected frame signal from the frame synchronization protection circuit 38. As described, bit clock reproduction on the receiving side is made easier by having the scrambling circuit 32 scramble output data. The scrambling circuit 32 (descrambling circuit 35) is illustratively constructed as shown in Fig. 9. The scrambling (descrambling) circuit of Fig. 9 comprises delay circuits 32a through 32e for successively delaying input data by one clock pulse each before output, and exclusive-OR gates 32f and 32g. The output of the delay circuit 32e is supplied to the delay circuit 32d, the output of the latter being forwarded to the delay circuit 32c. Likewise, the output of the delay circuit 32c is sent to the delay circuit 32b whose output is in turn fed to the delay circuit 32a. The output of the delay circuit 32c and that of the delay circuit 32a are input to the exclusive-OR gate 32f. The output of the exclusive-OR gate 32f is input to the delay circuit 32e. The output of the delay circuit 32a is taken as a scramble signal (descramble signal) and is supplied to the input on one side of the exclusive-OR gate 32g. The input on the other side of the exclusive-OR gate 32g receives the data to be scrambled (or descrambled). The exclusive-OR gate 32g outputs scrambled (or descrambled) data. The above-described scrambling/descrambling circuit performs scrambling/descrambling using the following generating polynomial: g(x) = x 5 + x 2 + 1 The scrambling circuit 32 (or descrambling circuit 35) may be alternatively constructed as shown in Fig. 10. In Fig. 10, the scrambling circuit 32 comprises a counter 41, a ROM 42, and exclusive-OR gates 43a through 43h. This circuit, too, scrambles (or descrambles) signals using the same generating polynomial as that for the circuit of Fig. 9. In this case, the clock cycle is 31(2⁵ - 1) since the generating polynomial above has degree five. The counter 41, which counts input clock pulses, supplies the ROM 42 with a count value between 0 and 31 as an address. In this example, eight exclusive-OR gates 43a through 43h process input data in parallel, eight bits at a time. Thus the ROM 42 contains beforehand 248 bits of data, the bit count being the least common multiple of 31 and 8. Every time an address is designated, eight bits of data are supplied to the inputs on one side of the exclusive-OR gates 43a through 43h. The inputs on the other side of the exclusive-OR gates 43a through 43h receive eight bits of parallel data to be scrambled (or descrambled). In this manner, the exclusive-OR gates 43a through 43h output the scrambled (or descrambled) data. A similar arrangement is disclosed in US-A-4965881, on which the precharacterising portion of appended claims 1 and 4 are based. The typical scrambling (descrambling) circuit of Fig. 9 is required to operate at a bit clock rate commensurate with the transmission rate at which scrambled (or descrambled) data are output one bit at a time. One disadvantage of this arrangement is that in the TTL or CMOS process, the circuit operates at rates of tens of MBPS at most. That is, it is difficult for circuits of this type to transmit high-definition television (HDTV) data and the like to be transmitted at rates of 100 MBPS or higher. One ramification of this aspect is that the scrambling (descrambling) circuit is not to be put into LSI format if manufactured as a CMOS arrangement; the circuit must be constructed as an ECL setup. The scrambling (descrambling) circuit of Fig. 10 processes eight bits of data at a time. This means that the counter 41 need only operate at one-eighth of the bit transmission rate. However, if this circuit is to be constructed in discrete format, the need to incorporate the counter 41, ROM 42 and exclusive-OR gates 43a through 43h means not only higher cost but also more space to accommodate them. In LSI format, the circuit is required to allocate disproportionately large space to the ROM 42. These disadvantages are increasingly pronounced as the degree of the generating polynomial is raised. Thus under the prior art constraints, it is difficult to adopt a generating polynomial of a substantially high degree in connection with the manufacture of the scrambling/descrambling circuit. It is therefore an object of the present invention to provide a scrambling/descrambling circuit which is manufactured as a CMOS arrangement in LSI format at low cost, and which allows the generating polynomial involved to have a high degree. In carrying out the invention and according to one aspect thereof, there is provided a scrambling/descrambling circuit for parallelly scrambling/descrambling "m" bits using a maximum length series of degree "n", characterised in that said circuit comprises: "m" exclusive-OR gates for having the inputs on one side thereof receive "m" bits of input data, one bit corresponding to one gate input; "p" multiplication circuits for multiplying data by α m in a Galois group given by a generating polynomial of said maximum length series of said degree "n", where α is the generating element; and "n × p" registers for latching "n × p" bits of data output by said multiplication circuits and for outputting the latched "n × p" bits back to said multiplication circuits, the value "n × p" being not smaller than the value "m", "m" bits of said latched data being output to the inputs on the other side of said exclusive-OR gates, one bit corresponding to one gate input. In the scrambling/descrambling circuit of the above construction, the scramble (or descramble) signal output by the registers and multiplied by α m is input back to the registers. Thus the circuit many be put into LSI format as a CMOS arrangement that is manufactured at low cost and is free of constraints on the degree of the generating polynomial adopted. Further objects, features and advantages of the invention will become more apparent from the following description given by way of example only with reference to the accompanying drawings in which: Fig. 1 is a circuit diagram of a scrambling/descrambling circuit embodying the invention; Fig. 2 is a view describing the Galois group of a typical generating polynomial; Fig. 3 is a view depicting register outputs in connection with the circuit shown in Fig. 9; Fig. 4 is a view rearranging the values in Fig. 3 for comparison with Fig. 2; Fig. 5 is a view showing how the values in Fig. 3 are related to those in Fig. 4; Fig. 6 is a circuit diagram of a circuit embodying a multiplication circuit contained in the embodiment of Fig. 1; Fig. 7 is a view depicting the construction of a data transmission system using the scrambling/descrambling circuit of Fig. 1; Fig. 8 is a view illustrating the construction of a typical prior art data transmission system; Fig. 9 is a view showing a typical scrambling/descrambling circuit used in the system of Fig. 8; and Fig. 10 is a view depicting another scrambling/descrambling circuit used in the system of Fig. 8. Fig. 1 is a circuit diagram of a scrambling/descrambling circuit embodying the present invention. In this embodiment, eight bits of parallel data are supplied to the inputs on one side of exclusive-OR gates 3a through 3h. The inputs on the other side of the exclusive-OR gates 3a through 3h are supplied with the outputs from registers la through lh, respectively. The outputs of the registers la through le are input to a multiplication circuit 2a. The output of the multiplication circuit 2a is sent back to the registers la through le via OR gates 4a through 4e. Likewise, the outputs of registers 1f through 1j are input to a multiplication circuit 2b; the output of the multiplication circuit 2b is sent back to the registers 1f through 1j via AND gates 4f to 4h and OR gates 4i and 4j. A reset signal is supplied via an inverter 5 to the OR gates 4a through 4e and the OR gates 4i and 4j. The reset signal is sent uninverted to the AND gates 4f through 4h. The embodiment above generates a scramble (or descramble) signal using the same generating polynomial x 5 + x 2 + 1 that is used in the prior art example. This polynomial has 31 Galois group generating elements (α ), as shown in Fig. 2. Fig. 3 depicts the outputs of the registers 32e through 32a in Fig. 9 (output: each of terms x⁴, x³, x², x¹ and x⁰), the vertical axis representing the time base. Fig. 4 indicates how the register outputs of Fig. 3 are rearranged in the order of generating element degrees beginning with the reset state in which all values are set to "1." Referring to Fig. 5, how Figs. 3 and 4 are related to each other will now be described. The outputs of the first eight clock pulses from the register 32a are "11111000." The first through the fifth l's correspond respectively to the values in terms 1, x, x², x³ and x⁴ of α¹⁵ in Fig. 4. The sixth through the eighth 0's correspond respectively to 0's in terms 1, x and x² of α ²⁰ in Fig. 4. Likewise, the ninth through the 18th outputs of term 1(x⁰) in Fig. 3 are "11011101." Of these outputs, the first five values "11011" correspond respectively to the values in terms 1, x, x², x³ and x⁴ of α ²³ in Fig. 4; the last three values "101" correspond respectively to the values in terms 1, x and x² of α ²⁸ in Fig. 4. With respect to degrees of the generating element α , α ²³ is α ¹⁵ multiplied by α⁸, and α ²⁸ equals α ²⁰ multiplied by α ⁸. That is, the value of term 1(x⁰) in Fig. 3 (i.e., output of register 32a in Fig. 9) appears at intervals of α ⁸ in Fig. 4. It is on the above preconditions that the circuit of Fig. 1 is constructed. In initial state, a logically low (0) reset signal is turned into a logically high (1) reset signal by the inverter 5 before being supplied to the OR gates 4a through 4e, 4i and 4j. This sets the registers 1a through 1e, 1i and 1j to "1" each. Meanwhile, the reset signal "0" is input uninverted to the AND gates 4f through 4h. This sets the registers 1f through 1h to "0" each. The registers la through le correspond to the terms 1, x, x², x³ and x⁴ of the generating polynomial, respectively. Similarly, the registers 1f through 1j correspond respectively to the terms 1, x, x², x³ and x⁴ of the generating polynomial. Assume that the outputs "11111" of the registers la through le are keyed to the terms of α ¹⁵ and the outputs "000" of the registers 1f through 1h keyed to the terms of α ²⁰. In this case, the outputs "11111000" of the registers la through 1h take on the values shown in Fig. 5. After a reset in initial state, the reset signal is brought High (1). As a result, the inputs on one side of the OR gates 4a through 4e, 4i and 4j receive "0" each. This causes the inputs on the other side of these OR gates to pass values unchanged therethrough. The inputs on one side of the AND gates 4f through 4h also receive "1" each. This causes the inputs on the other side of these AND gates to pass values unchanged therethrough. After this, the outputs b₁, b₀, b₄, b₃ and b₂ of the multiplication circuit 2a are supplied to the registers la through le via the OR gates 4a through 4e. Likewise, the outputs b₁, b₀, b₄, b₃ and b₂ of the multiplication circuit 2b are input to the registers if through 1j via the AND gates 4f through 4h and the OR gates 4i and 4j. Below is a description of inputs and outputs in connection with the multiplication circuits 2a and 2b. Using the equation below for a Galois group, the multiplication circuit 2a (as well as the circuit 2b) multiplies by α⁸ the inputs a₁, a₀, a₄, a₃ and a₂ from the registers 1a through 1e: α 8 (a 0 + a 1 α + a 2 α 2 + a 3 α 3 + a 4 α 4 ) = a 0 α 8 + a 1 α 9 + a 2 α 10 + a 3 α 11 + a 4 α 12 Comparing Fig. 2 with Fig. 4 reveals that x², x³, x⁴, 1(x⁰) and x of Fig. 4 correspond respectively to α ⁴, α ³, α ², α ¹ and α ⁰ of Fig. 2. Thus the coefficients a₄ through a₀ (i.e., outputs of registers 1a through 1e) in equation (1) correspond to the values of X², x³, x⁴, 1 and x of Fig. 4, respectively, as shown below. a 4 ... x 2 a 3 ... x 3 a 2 ... x 4 a 1 ... 1 a 0 ... x If the generating polynomial G(x) is set for 0, then α 5 + α 2 + 1 = 0 thus α 5 = α 2 + 1 If equation (2) is multiplied by α , then α 6 + α 3 + α = 0 thus α 6 = α 3 + α If equation (4) is multiplied by α, then α 7 + α 4 + α 2 = 0 thus α 7 = α 4 + α 2 By multiplying equation (6) by α and substituting equation (3) therefor, one gets α 8 + α 5 + α 3 = α 8 + (α 2 + 1) + α 3 = 0 thus α 8 = α 3 + α 2 + 1 Likewise, by multiplying equation (8) by α and substituting equation (5) therefor, one gets α 9 + α 6 + α 4 = α 9 + (α 3 + α) + α 4 = 0 thus α 9 = α 4 + α 3 + α Likewise, from the equation α 10 + α 7 + α 5 = α 10 + (α 4 + α 2 ) + (α 2 + 1) = 0 one gets α 10 = α 4 + 1 From the equation α 11 + α 8 + α 6 = α 11 + (α 3 + α 2 + 1) + (α 3 + α ) = 0 one gets α 11 = α 2 + α + 1 Furthermore, from the equation α 12 + α 9 + α 7 = α 12 + (α 4 + α 3 + α ) + (α 4 + α 2 ) = 0 one gets α 12 = α 3 + α 2 + α By substituting equations (9), (11), (13), (15) and (17) for equation (1), one gets a 0 α 8 + a 1 α 9 + a 2 α 10 + a 3 α 11 + a 4 α 12 = a 0 (α 3 + α 2 + 1) + a 1 (α 4 + α 3 + α ) + a 2 (α 4 + 1) + a 3 (α 2 + α + 1) + a 4 (α 3 + α 2 + α ) = (a 0 + a 2 + a 3 ) + (a 1 + a 3 + a 4 )α + (a 0 + a 3 + a 4 )α 2 + (a 0 + a 1 + a 4 )α 3 + (a 1 + a 2 )α 4 = b 0 + b 1 α + b 2 α 2 + b 3 α 3 + b 4 α 4 That is, b 0 = a 0 + a 2 + a 3 b 1 = a 1 + a 3 + a 4 b 2 = a 0 + a 3 + a 4 b 3 = a 0 + a 1 + a 4 b 4 = a 1 + a 2 The values b₀ through b₄ are latched by the registers 1b, 1a, 1e, 1d and 1c (or 1, 1f, 1j, 1i and 1h), to become the next new values a₀ through a₄. When the values a 0 = a 1 = a 2 =a 3 = a 4 = 1 of α ¹⁵ are substituted for equations (19) through (23), one gets b 0 = b 1 = b 2 = b 3 = 1 b 4 = 0 as the values a₀ (b₀) through a₄ (b₄) in α 23 ( = α 15 × α 8 ) The above multiplication process is carried out by the multiplication circuit 2a. When the values a 4 = a 1 = a 0 = 0 a 3 = a 2 = 1 of α ²⁰ are substituted for equations (19) through (23), one gets b 4 = b 2 = b 1 = 1 b 3 = b 0 = 0 as the values a₀(b₀) through a₄(b₄) in α 28 (= α 20 × α 8 ) The above multiplication process is carried out by the multiplication circuit 2b. In the manner described, the data latched by the registers la through 1h are supplied simultaneously to the inputs on one side of the exclusive-OR gates 3a through 3h as scramble/descramble data. This causes the eight-bit data fed to the inputs on the other side of the same gates to be scrambled/descrambled simultaneously. Because eight-bit data are processed at the same time, the registers 1a through 1i and the multiplication circuits 2a and 2b need only operate at one-eighth of the bit transmission rate. Fig. 6 is a circuit diagram of a circuit embodying the multiplication circuit 2a (2b). As illustrated, the embodied multiplication circuit 2a (2b) comprises seven exclusive-OR gates 61 through 67. The exclusive-OR gate 61 gets a₀ and a₃ exclusive-OR'ed and outputs the result to the exclusive-OR gate 63. In turn, the exclusive-OR gate 63 gets the received gate output and a₂ exclusiveOR'ed and outputs b₀(a₀ + a₂ + a₃). The exclusive-OR gate 62 gets a₁ and a₄ exclusive-OR′ed and sends the result to the exclusive-OR gate 64. In turn, the exclusive-OR gate 64 gets the received gate output and a₃ exclusive-OR'ed and outputs b₁(a₁ + a₃ + a₄). The exclusive-OR gate 65 gets the output (a₀ + a₃ ) of the exclusive-OR gate 61 and a₄ exclusive-OR′ed and outputs b₂(a₀ + a₃ + a₄). The exclusive-OR gate 66 gets the output (a₁ + a₄) of the exclusive-OR gate 62 and a₀ exclusive-OR′ed and outputs b₃(a₀ + a₁ + a₄). The exclusive-OR gate 67 gets a₁ and a₂ exclusive-OR′ed and outputs b₄(a₁ + a₂). Fig. 7 shows a typical data transmission system that utilizes the scrambling/descrambling circuit described above, as opposed to a typical prior art system. Conventionally, processing circuits 11 (11a through 11h) on the transmitting side process eight-bit data in parallel and send the processed data to a parallel-to-serial conversion circuit 12 for conversion to serial data. The output of the parallel-to-serial conversion circuit 12 is scrambled by a scrambling circuit 13, the scrambled data being placed onto a transmission line. On the receiving side, a descrambling circuit 14 descrambles the data coming over the transmission line. The output of the descrambling circuit 14 is converted by a serial-to-parallel conversion circuit 15 to parallel data for processing by processing circuits 16 (16a through 16h). Because the processing circuits 11 and 16 need only operate at one-eighth of the bit transmission rate, they may be manufactured in LSI format as a low-speed, inexpensive CMOS arrangement. With the prior art, however, the parallel-to-serial conversion circuit 12, serial-to-parallel conversion circuit 15, scrambling circuit 13 and descrambling circuit 14 must be constructed discretely in a highspeed, expensive ECL arrangement each. By contrast, the scrambling/descrambling circuit embodying the invention may operate at low speed because it processes eight bits in parallel. Thus the processing circuits 11, scrambling circuit 17, processing circuits 16 and descrambling circuit 20 can be manufactured in LSI format as a CMOS arrangement. Only the parallel-to-serial conversion circuit 18 and serial-to-parallel conversion circuit 19 need to be constructed as an ECL arrangement that operates at high speed. Thus according to the invention, the data processed by the processing circuits 11 on the transmitting side are scrambled by the scrambling circuit 17, followed by conversion from parallel to serial format. On the receiving side, the data are converted from serial to parallel format before being descrambled. Because the embodiment of the invention allows data to be output "as scrambled" from the LSI, the scrambling process provides not only for clock recovery (self-clock) but also for better data security. Furthermore, because the scope of the circuit is reduced and the power consumption involved is lowered, the overall cost is suppressed while circuit reliability is enhanced. In the above-described embodiment, the values of a₁, a₀, a₄, a₃ and a₂ are initialized to "11111" (in registers 1a through 1e) or to "00011" (in registers 1f through 1j). Alternatively, these initial values may be changed or the generating polynomial in use may be altered for data protection purposes. In the embodiment above, the degree "n" of the maximum length series is 5, the number "m" of bits for parallel processing is 8, and the number "p" of multiplication circuits is 2 (2a, 2b). However, these settings are for illustrative purposes only and are not limitative of the invention. As described, the scrambling/descrambling circuit according to the invention multiplies scramble/descramble data by α m to generate new scramble/descramble data. This scheme makes it possible to keep the processing speed low where the bit transmission rate is high. This in turn allows the circuit to be manufactured as an inexpensive CMOS arrangement in LSI format. Because no ROM is employed, the LSI setup is easy to make, with no constraints on the degree "n" of the generating polynomial or on the number "m" of bits to be processed. As a result, the scrambling/descrambling circuit may be downsized significantly. As many apparently different embodiments of this invention may be made without departing from the scope thereof, it is to be understood that the invention is not limited to the specific embodiments thereof except as defined in the appended claims.

Claims: A scrambling circuit for parallelly scrambling "m" bits using a maximum length series of degree "n", characterised in that said circuit comprises: "m" exclusive-OR gates (3a-3h) for having the inputs on one side thereof receive "m" bits of input data (BIT1-BIT8), one bit corresponding to one gate input; "p" multiplication circuits (2a,2b) for multiplying data input thereto by α m in a Galois group given by a generating polynomial of said maximum length series of said degree "n", where α is the generating element; and "n × p" registers (1a-1j) for latching "n × p" bits of data output by said multiplication circuits (2a,2b) and for outputting the latched "n x p" bits back as the inputs to said multiplication circuits (2a,2b), the value "n x p" being not smaller than the value "m", "m" bits of said latched data being output to the inputs on the other side of said exclusive-OR gates (3a-3h), one bit corresponding to one gate input. A scrambling circuit according to claim 1, wherein said input data (BIT1-BIT8) are "m" bit parallel data and wherein said exclusive-OR gates (3a-3h) output scrambled parallel data. A scrambling circuit according to claim 1 or 2, wherein said scrambling circuit is constituted at least by a CMOS arrangement in LSI format. A descrambling circuit for parallelly descrambling "m" bits using a maximum length series of degree "n", characterised in that said circuit comprises: "m" exclusive-OR gates (3a-3h) for having the inputs on one side thereof receive "m" bits of input data (BIT1-BIT8), one bit corresponding to one gate input; "p" multiplication circuits (2a,2b) for multiplying data input thereto by α m in a Galois group given by a generating polynomial of said maximum length series of said degree "n", where α is the generating element; and "n × p" registers (1a-1j) for latching "n × p" bits of data output by said multiplication circuits (2a,2b) and for outputting the latched "n × p" bits back as the inputs to said multiplication circuits (2a,2b), the value "n x p" being not smaller than the value "m", "m" bits of said latched data being output to the inputs on the other side of said exclusive-OR gates (3a-3h), one bit corresponding to one gate input. A descrambling circuit according to claim 4, wherein said input data (BIT1-BIT8) are scrambled parallel data and wherein said exclusive-OR gates (3a-3h) output "m" bit parallel data. A descrambling circuit according to claim 4 or 5, wherein said descrambling circuit is constituted at least by a CMOS arrangement in LSI format. A data transmission system comprising a transmitting section (17) for scrambling data, means (18) for modulating and transmitting the scrambled data, means (19) for receiving and demodulating the transmitted data, and a receiving section (20) for descrambling the demodulated data; said transmitting section (17) containing a scrambling circuit according to claim 1, 2 or 3 and said receiving section (20) containing a descrambling circuit according to claim 4, 5 or 6. A data transmission system according to claim 7, wherein said receiving section (20) includes a reproduction circuit for reproducing a bit clock signal contained in said demodulated data. A data transmission system according to claim 7 or 8, wherein said system transmits satellite broadcasting data.

Inventors: KOJIMA YUICHI, KOJIMA, YUICHI
Applicants: SONY CORP, SONY CORPORATION
Application year: 1991
Main classification: H04L25
IPC codes: H04L25, G06F7, H04L7, H04L9, H04K1