Parallel data processing apparatus and method with signal skew compensation

Abstract: A parallel data processing apparatus containing a plurality of processors (3₁, 3₂, ... 3 n ), a pair of signal paths (15, 16, 33a₁, 33a₂, ... 33a n , 34a₁, 34a₂, ... 34a n ) are provided for each processor (3₁, 3₂, ... 3 n ), one signal path (15, 33a₁, 33a₂, ... 33a n ) of each pair being used for supplying a predetermined signal to the processor, and the other signal path (16, 34a₁, 34a₂, ... 34a n ) being used for returning the signal from the processor to a predetermined position common to all of the processors. Each of the above signal paths containing a variable delay unit (6a₁, 6a₂, ... 6a n , 10a₁, 10a₂, ... 10a n ). The apparatus further contains a delay measuring unit (7a) for measuring a time elapsing while the signal is propagated from the above predetermined position to a corresponding processor and then returned from the processor to the above predetermined position through each pair of signal paths; and a delay adjusting unit (7a) for adjusting the delays caused by the variable delay units (6a₁, 6a₂, ... 6a n ) in all of the signal paths, based on results of a measurement by the delay measuring unit, so that times elapsing while the signal is propagated from the predetermined position to the plurality of processors, through the respective signal paths (33a₁, 33a₂, ... 33a n ) for supplying the signal to the processors, are equal.

Description: The present invention relates to an apparatus and a method for supplying a signal to be simultaneously received by data processing units according to the upper clauses of claims 1 and 13. The processing units are operated in parallel and the operation of them are typically started upon receiving a common asynchronous request signal. Typically, the present invention can be applied to a single instruction stream multiple data stream (SIMD) type parallel data processing apparatus. (2) Description of the Related Art In the above parallel data processing apparatuses the above asynchronous request signal may be an interrupt signal output from a host processor to the processors in the parallel data processing apparatus and the above asynchronous request signal must be received (latched) at the same time to ensure a synchronous parallel operation of all of the processors. Conventionally, the lengths of signal lines for each of the asynchronous request signal and the clock signal from the output point thereof to the plurality of processors are designed to be the same (equal-length wiring), so that the asynchronous request signal is received simultaneously in each of the plurality of processors. The above equal-length wiring, however, imposes a very severe design requirement on the designer of the parallel data processing apparatus. Further, high accuracy of the timing of the operations of the plurality of processors cannot be achieved by the equal-length wiring, and therefore, the frequency of the clock signal cannot be increased in a parallel data processing apparatus designed to use the equal-length wiring. USP 4,868,522 discloses a delay circuit for adjusting the propagation delay of clock signals, generated by a clock source, distributed to various receiving devices so that the receiving devices are clocked simultaneously, as described in its " ABSTRACT " and "SUMMARY OF THE INVENTION". Fig. 2 discloses the configurations of the signal supply paths and signal return paths from the signal distribution device (SDD) to the plurality of receiving devices. USP 4,868,522 assumes that the propagation delays in each pair of the signal supply path and the signal return path are the same, and does not disclose any provision for making the propagation delays in the signal supply path and the signal return path are the same. Generally, when the signal supply path and the signal return path in each pair are disposed apart from each other, the propagation delays in the signal supply path and the signal return path will be different due to the difference in the distributed capacitance and inductance around the signal supply path and the signal return path. Therefore, when there is no provision for equalizing the propagation delays in the signal supply path and the signal return path, the signal supply path and the signal return path must be disposed very near through their full length from the source to the destination. However, if the signal supply path and the signal return path are disposed very near, signals passing through these paths will interfere with each other to make the operation unstable. Therefore, the provision for equalizing the propagation delays in the signal supply path and the signal return path is very important. It is an object of the present invention to provide an apparatus and a method according to the upper clauses of claims 1 and 13, resp., where severe design requirements for equal-length wiring are reduced or eliminated, a high accuracy of the timing of the operations of the plurality of processors can be obtained, and a high frequency clock signal can be used. This object is achieved by the features of independent claims 1 and 13. Further features and advantages of the present invention can be read from the sub-claims in connection with the drawings and the following description. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings: Figure 1 is a block diagram showing a construction of the first embodiment of the present invention; Figure 2 is a diagram showing an example operation of determining additional delay times to be set in the programmable delay circuits 253 in the delay & switch circuit 25 r (r=1 to n); Figure 3 is a block diagram showing a construction of the second embodiment of the present invention; Figure 4 is a block diagram showing a construction of the third embodiment of the present invention; Figure 5 is a block diagram showing a construction of the fourth embodiment of the present invention; Figure 6 is a block diagram showing a construction of the MPU clock generator 23 in the construction of Fig. 5; Figure 7 is a state transition diagram of the frequency division rate counter 231 in the construction of Fig. 6; Figure 8 is a state transition diagram of the frequency divides 232 in the construction of Fig. 6; Figure 9 is a state transition diagram of the request reception & clock control circuit 24 in the construction of Fig. 5; Figure 10 is a timing diagram of an example operation of the MPU clock generator of Fig. 6; Figure 11 is a diagram showing an example sequence in a reception of an interrupt request signal by the parallel data processing apparatus 200 in Fig. 5; Figure 12 is a diagram showing an example sequence in a reception of a hold request signal by the parallel data processing apparatus 200 in Fig. 5; Figure 13 is a block diagram showing a construction of the delay & switch circuit 25 r (r=1 to n) of Fig. 5; Figure 14 is a block diagram showing an example construction of the programmable delay circuit 253 or 256 in the construction of Fig. 13; Figure 15 is a block diagram showing an example construction of the delay time measuring & setting circuit 27 in the construction of Fig. 5; Figure 16 is a block diagram showing an arrangement of a plurality of the delay time measuring & setting circuits 27 k (k=1 to m) and the delay & switch circuits 25 kr (r= 1 to n, k=1 to m) in the fifth embodiment of the present invention; Figures 17A and 17B are diagrams showing the construction of the delay time measuring & setting circuits 27 k (k=1 to m) in the construction of Fig. 16; Figures 18A and 18B are diagram showing signal routes used when initially setting delay times in the programmable delay circuits 253 1 to 253 4 in the construction of Figs. 17A and 17B, for making symmetrical each pair of signal paths of the delay time measuring & setting circuits 27 k (k=1 to m); Figures 19A and 19B are diagrams showing a signal route used when initially setting delay times in the programmable delay circuits 304 and 305 in the construction of Figs. 17A and 17B for making symmetrical each pair of signal paths of the delay time measuring & setting circuits 27 k (k=1 to m); Figures 20A and 20B are diagram showing a signal route used when measuring a time elapsing while a signal is propagated to the processor 221, in the delay time measuring & setting circuit 27 k (k=1 to m) of the construction of Figs. 17A and 17B; Figures 21A and 21B are diagrams showing signal routes used during a normal operation of the parallel data processing apparatus in the fifth embodiment, in the delay time measuring & setting circuit 27 k (k=1 to m) of the construction of Figs. 17A and 17B; Figures 22A and 22B are diagrams of the construction of the delay & switch circuit 25 kr (r=1 to n, k=1 to m) in the construction of Fig. 16; Figures 23A and 23B are diagrams showing signal routes used when initially setting delay times in the programmable delay circuits 272, 400, 403, 404, 410, and 411 in the construction of Figs. 22A and 22B for making symmetrical each pair of signal paths of the delay & switch circuit 25 kr (r=1 to n, k=1 to m); Figures 24A and 24B are diagrams showing a signal route used in the delay time measuring & setting circuit 27 k (k=1 to m) of the construction of Figs. 22A and 22B when measuring a time elapsing while a signal is propagated to a processor connected to one of the delay & switch circuits 25 kr (r=1 to n, k=1 to m) in the same row as the delay time measuring & setting circuit 27 k (k=1 to m) in the arrangement of Fig. 16; Figures 25A and 25B are diagrams showing a signal route used in the delay time measuring & setting circuit 27 k (k=1 to m) of the construction of Figs. 22A and 22B when the delay time measuring & setting circuit 271 in Fig. 16 measures a time elapsing while a signal is propagated to another delay time measuring & setting circuit 27 k' (k'=2 to m) in the same column as the delay time measuring & setting circuit 271 in the arrangement of Fig. 16; Figures 26A and 26B are diagrams showing a signal route used in the delay time measuring & setting circuit 27 k (k=2 to m-1) of the construction of Figs. 22A and 22B when the delay time measuring & setting circuit 271 in Fig. 16 measures a time elapsing while a signal is propagated to another delay time measuring & setting circuit 27 k' (k'=3 to m), where the shown delay time measuring & setting circuit 27 k is in a midway of the signal propagation path in the arrangement of Fig. 16; Figures 27A and 27B are diagrams showing a signal route used in the delay time measuring & setting circuit 27 k (k=2 to m) of the construction of Figs. 22A and 22B when the delay time measuring & setting circuit 27 1 in Fig. 16 measures a time elapsing while a signal is propagated to the delay time measuring & setting circuit 27 k ; and Figures 28A and 28B are diagrams showing a signal route used in the delay time measuring & setting circuit 27 k (k=2 to m) of the construction of Figs. 22A and 22B during a normal operation of the parallel data processing apparatus in the fifth embodiment, where the first routes κ1 and κ2 are used by the delay time measuring & setting circuit 27 1 in Fig. 16, and second routes λ1 and λ2 are used by the delay time measuring & setting circuits 27 k (k=2 to m) in the arrangement of Fig. 16. DESCRIPTION OF THE PREFERRED EMBODIMENTS Basic Operations Before describing the preferred embodiment of the present invention, first the basic principles of the first to third aspects of the present invention are explained below. According to the first aspect of the present invention, first, the time which elapses while the signal propagates from the predetermined position to the corresponding data processing unit and then returns from the processor to the predetermined position through each pair of signal paths, is measured by the delay measuring unit. This can be realized by the provision of the plurality of pairs of signal paths where the pairs respectively corresponding to the plurality of data processing units, and the signal paths in each of the plurality of pairs are made symmetrical with regard to the electrical length for a signal propagation. Then, the delays caused by the variable delay unit in all of the signal paths of the plurality of pairs of signal paths are adjusted, based on the results of measurement by the delay measuring unit so that times elapsing while the signal is propagated from the predetermined position to the plurality of data processing units through the respective signal paths of the plurality of pairs of signal paths for supplying the signal to the data processing units, are equal. According to the second aspect of the present invention, the above provision of the first aspect of the present invention is made for a predetermined one of the clock signal and the asynchronous request signal. According to the third aspect of the present invention, the above provision of the first aspect of the present invention is made for both the clock signal and the asynchronous request signal. Fig. 1 (First Embodiment) Figure 1 is a block diagram showing a construction of the first embodiment of the present invention. In Fig. 1, reference numeral 1 denotes a host processor, 2 denotes a parallel data processing apparatus, 3 1 , 3 2 , ··· 3 n each denote a processor, 4 denotes a clock generator, 5 denotes a request reception circuit, 6a 1 , 6a 2 , ··· 6a n each denote a programmable delay circuit, 7a denotes a delay time measuring & setting circuit, 9a 1 , 9a 2 , ··· 9a n each denote a selector, 10a 1 , 10a 2 , ··· 10a n each denote a programmable delay circuit, 11a 1 , 11a 2 , ··· 11a n each denote a selector, 12a 2 denotes an offset adjusting circuit, 13a and 13a' each denote a waveform shaping circuit, 14a denotes an offset adjusting circuit, 15 denotes a clock signal supply path, 16 denotes a return path corresponding to the clock signal supply path 15, 17 denotes an asynchronous request signal path, 18 denotes an acknowledge signal path, 33a 1 , 33a 2 , ··· 33a n each denote a branch path for supplying a clock signal to each processor, and 34a 1 , 34a 2 , ··· 34a n each denote a branch path for returning the clock signal from a corresponding processor to the return path 16. The construction of Fig. 1 is an embodiment of the above-mentioned second aspect of the present invention. In the construction of Fig. 1, the clock signal supply path 15 and the return path 16 are provided along the plurality of processors 3 1 , 3 2 , ··· 3 n . One end of each of the clock signal supply path 15 and the return path 16 is connected with the clock generator 4. Further, all other designs in the clock signal supply path 15 and the corresponding return path 16 are made symmetrical with regard to a signal propagation. The clock signal supply path 15 has a branch path 33a 1 , 33a 2 , ··· 33a n for each of the plurality of processors 3 1 , 3 2 , ··· 3 n , where each branch path 33a 1 , 33a 2 , ··· 33a n connects the clock signal supply path 15 with a clock input terminal of the corresponding processor. The return path 16 has a branch path 34a 1 , 34a 2 , ··· 34a n for each of the plurality of processors 3 1 , 3 2 , ··· 3 n , where each branch path 34a 1 , 34a 2 , ··· 34a n is provided corresponding to one of the above branch paths 33a 1 , 33a 2 , ··· 33a n , and connects the return path 16 with the clock input terminal of the corresponding processor. All other designs in the above corresponding branch paths 33a 1 , 33a 2 , ··· 33a n and 34a 1 , 34a 2 , ··· 34a n are made symmetrical with regard to a signal propagation. One of the programmable delay circuits (variable delay circuits) 6a 1 , 6a 2 , ··· 6a n is provided on a corresponding one of the branch paths 33a 1 , 33a 2 , ··· 33a n , and one of the programmable delay circuits (variable delay circuits) 10a 1 , 10a 2 , ··· 10a n is provided on a corresponding one of the branch paths 34a 1 , 34a 2 , ··· 34a n . The return path 16 comprises thereon the plurality of selectors 9a 1 , 9a 2 , ··· 9a n . Each of the selectors 9a 1 , 9a 2 , ··· 9a n-1 two input terminals are connected to a first signal coming from a processor located on the upstream side of the return path 16 (upstream side being to the right of selectors 9a1, 9a2 ... 9an in Figure 1) and a second signal coming from corresponding one of the branch paths 10a1, 10a 2 , ··· 10a n , and connects at its output terminal the downstream side of the return path 16. In order to symmetrize a path of a signal from the clock generator 4 to the clock input terminal of each processor and a path of the signal from the clock input terminal of the processor to the clock generator 4, the selectors 11a 1 , 11a 2 , ··· 11a n are provided on the clock signal supply path 15 at the locations corresponding to the locations of the selectors 9a 1 , 9a 2 , ··· 9a n on the return path 16. Each of the clock signal supply path 15 and the return path 16 comprises a waveform shaping circuit 13a or 13a' for maintaining the waveform of the clock signal. The waveform shaping circuits 13a and 13a' on the clock signal supply path 15 and the return path 16 are provided in correspondence to each other. The offset adjusting circuit 14a is provided for the corresponding waveform shaping circuits 13a and 13a' to initially adjust the delay times caused by the corresponding waveform shaping circuits 13a and 13a' so that the initial delay times caused by the corresponding waveform shaping circuits 13a and 13a' are equal. Further, the offset adjusting circuit 12a 1 , 12a 2 , ··· 12a n may be provided for each pair of corresponding programmable delay circuits 6a 1 , 6a 2 , ··· 6a n , and 10a 1 , 10a 2 , ··· 10a n to adjust the delay times caused by each pair of the corresponding programmable delay circuits 6a 1 , 6a 2 , ··· 6a n , and 10a 1 , 10a 2 , ··· 10a n so that the initial delay times caused by each pair of the corresponding programmable delay circuits 6a 1 , 6a 2 , ··· 6a n , and 10a 1 , 10a 2 , ··· 10a n are equal. A common offset adjusting circuit may be provided for all pairs of the corresponding programmable delay circuits 6a 1 , 6a 2 , ··· 6a n , and 10a 1 , 10a 2 , ··· 10a n . An input terminal of the delay time measuring & setting circuit 7a is connected to the clock signal supply path 15 at the clock output terminal of the clock generator 4, and a clock output terminal of the delay time measuring & setting circuit 7a is convected to the return path 16 at the clock input terminal of the clock generator 4. In the above construction for supplying the clock signal to the processors 3 1 , 3 2 , ··· 3 n , first the above adjustments of the delay times caused by the corresponding programmable delay circuits 6a 1 , 6a 2 , ··· 6a n and 10a 1 , 10a 2 , ··· 10a n , and the delay times caused by the corresponding waveform shaping circuits 13a and 13a', are carried out to make symmetrical each path for supplying the clock signal from the output terminal of the delay time measuring & setting circuit 7a to a clock input terminal of a corresponding processor and a corresponding path for returning the clock input terminal of the corresponding processor to the input terminal of the delay time measuring & setting circuit 7a. Then, the delay time measuring & setting circuit 7a measures a propagation delay time for a signal to be propagated from the delay time measuring & setting circuit 7a to the clock input terminal of each processor and then propagated from the clock input terminal of the processor to the delay time measuring & setting circuit 7a. Then, the delay time measuring & setting circuit 7a obtains a propagation delay time for a signal to be propagated from the delay time measuring & setting circuit 7a to the clock input terminal of each processor by dividing the above measured time by two, taking advantage of the above symmetricallity of the paths between the delay time measuring & setting circuit 7a and each processor. After obtaining the propagation delay times for all of the plurality of processors 3 1 , 3 2 , ··· 3 n , the delay time measuring & setting circuit 7a sets an additional delay time in the corresponding one of the programmable delay circuits 6a 1 , 6a 2 , ··· 6a n on the corresponding one of the branch paths 33a 1 , 33a 2 , ··· 33a n to each processor so that propagation delay times from the clock output terminal of the clock generator 4 to the input terminals of the plurality of processors 3 1 , 3 2 , ··· 3 n , are the same. Figure 2 is a diagram showing an example operation of determining additional delay times to be set in the programmable delay circuits 253 in the delay & switch circuit 25 r (r=1 to n). The above additional time for each programmable delay circuit can be determined as a difference between the maximum of the above obtained propagation delay times to the processors and the obtained propagation delay time to the corresponding processor, as shown in Fig. 2. Thus, an initial setting of the parallel data processing apparatus 2 of Fig. 1 is completed. In the operation of the parallel data processing apparatus 2 of Fig. 1, the request reception circuit 5 receives an asynchronons request signal supplied from the host processor 1. The asynchronous request signal is, for example, an interrupt signal, or a hold request signal. When receiving the asynchronous request signal, the request reception circuit 5 sends a clock frequency down control signal to the clock generator 4 through the clock frequency control circuit 8 to temporarily lower the frequency of the clock signal output from the clock generator 4. The clock generator 4 comprises an oscillator, a frequency divider, and a frequency division rate control circuit for controlling a frequency division rate of the frequency divider. When the clock generator 4 receives the above clock frequency down control signal, the frequency division rate control circuit temporarily lowers the frequency of the clock signal. Then, the frequency division rate control circuit sends a complete signal, which indicates a completion of the lowering operation of the frequency of the clock signal, to the request reception circuit 5. upon receiving the complete signal, the request reception circuit 5 sends the asynchronous request signal to the plurality of processors 3 1 , 3 2 , ··· 3 n through the asynchronous request signal path 17. When each processor receives the asynchronous request signal, the processor returns an acknowledge signal to the request reception circuit 5 through the acknowledge signal path 18. When the request reception circuit 5 receives the acknowledge signal, the request reception circuit 5 sends a clock frequency up control signal to the clock generator 4. Upon receiving the clock frequency up control signal, the frequency division rate control circuit temporarily increases the frequency of the clock signal to a predetermined frequency used in a normal operation. Namely, the above reception of the asynchronous request signal by each processor is carried out while the frequency of the clock signal supplied to the processor is lowered, i.e., the clock cycle is lengthened (for example, a normal cycle 30 nsec is increased to 240 nsec), and therefore, the operations in the respective processors 3 1 , 3 2 , ··· 3 n responding to the asynchronous request signal can start within the same clock cycle even when the times at which the asynchronous request signal reaches the respective processors differ, as long as the difference in the times is within the lengthened clock cycle. In the above construction, the above asynchronous request signal path 17 to the plurality of processors 3 1 , 3 2 , ··· 3 n may be designed by the conventional equal-length wiring. In this case, the above provision for lowering the frequency of the clock signal when receiving an asynchronous request signal may not be necessary. Fig. 3 (Second Embodiment) Figure 3 is a block diagram showing a construction of the second embodiment of the present invention. In Fig. 3, reference numeral 2' denotes a parallel data processing apparatus, 5' denotes a request reception circuit, 6b 1 , 6b 2 , ··· 6b n each denote a programmable delay circuit, 7b denotes a delay time measuring & setting circuit, 9b 1 , 9b 2 , ··· 9b n each denote a selector, 10b 1 , 10b 2 , ··· 10b n each denote a programmable delay circuit, 11b 1 , 11b 2 , ··· 11b n each denote a selector, 12b 2 denotes an offset adjusting circuit, 13b and 13b' each denote a waveform shaping circuit, 14b denotes an offset adjusting circuit, 15 denotes a clock signal supply path, 16 denotes a clock signal return path, 17 denotes an asynchronous request signal path, 18 denotes an acknowledge signal path, 19 denotes an asynchronous request signal path, 20 denotes a return path corresponding to the asynchronous request signal path 19, 21 denotes a clock signal supply path, 33b 1 , 33b 2 , ··· 33b n each denote a branch path for supplying a clock signal to each processor, and 34b 1 , 34b 2 , ··· 34b n each denote a branch path for returning the clock signal from a corresponding processor to the return path 16. The other elements in Fig. 3 which are denoted by the same reference numerals as in Fig. 1, are respectively the same elements as shown in that figure. The construction of Fig. 3 is an embodiment of the above-mentioned second aspect of the present invention. In the construction of Fig. 3, a provision for adjusting propagation delay times to the plurality of processors 3 1 , 3 2 , ··· 3 n is made for a construction for supplying the asynchronous request signal; conversely, the provision is made for the construction for supplying the clock signal in the construction of Fig. 1. The elements having the reference numerals containing the character "b" in Fig. 3, respectively correspond to the elements having the reference numerals in Fig. 1 containing the character "a" and the same remaining numerals as Fig. 2, and are respectively operated in a way similar to the corresponding elements in Fig. 1. Similar to the construction of Fig. 1, the frequency of the clock signal is lowered when an asynchronous request signal is supplied to the plurality of processors 3 1 , 3 2 , ··· 3 n . The control operations for lowering and increasing of the frequency of the clock signal are carried out by supplying the clock frequency down control signal and the clock frequency up control signal output from the request reception circuit 5' to the clock generator 4 responding to the reception of the asynchronous request signal from the host processor 1 and the reception of the acknowledge signal from the processors. The request reception circuit 5' outputs the asynchronous request signal to the plurality of processors 3 1 , 3 2 , ··· 3 n when receiving the complete signal from the clock generator 4, respectively. Namely, the above reception of the asynchronous request signal by each processor is carried out while the frequency of the clock signal supplied to the processor is lowered, i.e., the clock cycle is lengthened, and therefore, the operations in the respective processors 3 1 , 3 2 , ... 3 n responding to the asynchronons request signal can start within the same clock cycle even when the times at which the clock signal reaches the respective processors differ, as long as the difference in the times is within the lengthened clock cycle. In the above construction, the above clock signal supply path 21 to the plurality of processors 3 1 , 3 2 , ··· 3 n may be designed by the conventional equal-length wiring. In this case, the above provision for lowering the frequency of the clock signal when receiving an asynchronous request signal may not be necessary. Fig. 4 (Third Embodiment) Figure 4 is a block diagram showing a construction of the third embodiment of the present invention. In Fig. 4, reference numeral 2" denotes a parallel data processing apparatus, and 5" denotes a request reception circuit, The other elements in Fig. 4, which are denoted by the same reference numerals as Figs. 1 and 2, are respectively the same elements as shown in these figures. The construction of Fig. 4 is an embodiment of the above-mentioned third aspect of the present invention. In the construction of Fig. 4, the provision for adjusting propagation delay times to the plurality of processors 3 1 , 3 2 , ··· 3 n is made for both the construction for supplying the asynchronous request signal and the construction for supplying the clock signal, where the respective provisions are the same as those shown in Figs. 1 and 3. In the construction of Fig. 4, however, no provision is made for lowering the frequency of the clock signal, as since both the asynchronous request signal and the clock signal are respectively supplied to the plurality of processors 3 1 , 3 2 , ··· 3 n simultaneously, it is not necessary to lower the frequency of the clock signal in the construction of Fig. 4. Fig. 5 (Fourth Embodiment) Figure 5 is a block diagram showing a construction of the fourth embodiment of the present invention. In Fig. 5, reference numeral 1' denotes a host processor, 200 denotes a parallel data processing apparatus, 22 1 , 22 2 , ··· 22 n each denote a processor, 23 denotes an MPU clock generator, 24 denotes a request reception & clock control circuit, 25 1 , 25 2 , ··· 25 n each denote a delay & switch circuit, 27 denotes a delay time measuring & setting circuit, 28 denotes a control bus, 29 denotes an asynchronous request signal path, 30 denotes an acknowledge signal path, 31 denotes a clock signal supply path, and 32 denotes a return path corresponding to the clock signal supply path 31. The delay & switch circuits 25 1 , 25 2 , ··· 25 n are each provided for a corresponding one of the plurality of processors 22 1 , 22 2 , ··· 22 n , and are chain connected to the delay time measuring & setting circuit 27. The construction of Fig. 5 is an embodiment of the above-mentioned second aspect of the present Invention, and is basically similar to the construction of Fig. 1. The function for supplying the clock signal to the plurality of processors 22 1 , 22 2 , ··· 22 n , which is similar to the corresponding function in the construction of Fig. 1, is realized by the plurality of delay & switch circuits 25 1 , 25 2 , ··· 25 n and the delay time measuring & setting circuit 27. Details of each of the delay & switch circuits 25 1 , 25 2 , ··· 25 n and the delay time measuring & setting circuit 27 will be explained later. Figs. 6, 7, and 8 (MPU Clock Generator) Figure 6 is a block diagram showing a construction of the MPu clock generator 23 in the construction of Fig. 5. In Fig. 6, reference numeral 230 denotes a controller, 231 denotes a frequency division rate counter, and 232 denotes a frequency divider. The controller 230 receives an up/down control signal supplied from the request reception & clock control circuit 24, and outputs an up/down signal U/D to the frequency division rate counter 231 according to the received up/down control signal. Figure 7 is a state transition diagram of the frequency division rate counter 231 in the construction of Fig. 6. The frequency division rate counter 231 is initially in the state "S7", where the frequency division rate counter 231 outputs a count equal to seven. When the state of the frequency division rate counter 231 is in the state "S7" and the above U/D signal indicates a count down, i.e., U/D=0, the state of the frequency division rate counter 231 remains in the state "S7". When the state of the frequency division rate counter 231 is in the state "S7" and the above U/D signal indicates an instruction to increase the count by one, i.e., U/D=1, the state of the frequency division rate counter 231 is shifted one state by one state from the state "S7" to the state "S0", as "S7"→"S6", "S6"→"S5", ··· "S1"→"S0", where the frequency division rate counter, 231 outputs a count equal to i in the state "Si" (i=0 to 7). In the state "S0", the frequency division rate counter 231 outputs a COMPLETE signal to the request reception & clock control circuit 24. When the state of the frequency division rate counter 231 is in the state "S0" and the above U/D signal indicates a count down, i.e., U/D=0, the state of the frequency division rate counter 231 remains in the state "S0". When the state of the frequency division rate counter 231 is in the state "S0" and the above U/D signal indicates a count up, i.e., U/D=1, the state of the frequency division rate counter 231 is shifted one state by one state from the state "S0" to the state "S7", as "S0"→"S1", "S1"→"S2", ··· "S6"→"S7". Figure 8 is a state transition diagram of the frequency divider 232 in the construction of Fig. 6. The frequency divider 232 is realized by a counter in which the count is increased by one when a leading edge of a master clock signal is supplied thereto from a master oscillator (not shown). In Fig. 8, "Cj" denotes a state of the frequency divider (counter) 232 which outputs a count equal to j, where i=0 to j, where j is a count output of the frequency division rate counter 231. As shown in Fig. 8, in the state "Sj" of the frequency division rate counter 231, the count j of the frequency divider (counter) 232 is cyclically changed from 0 to i, and a carry signal is output when the count reaches i. When the state of the frequency division rate counter 231 is "S0", the frequency divider 232 outputs an MPU clock signal having a frequency which is the same as the frequency of the master clock signal. Namely, the frequency division rate in the frequency divider 232 is equal to i+1. Figs. 9 to 12 (Request Reception & Clock Control) Figure 9 is a state transition diagram of the request reception & clock control circuit 24 in the construction of Fig. 5. The request reception & clock control circuit 24 is in an initial state "Init" after power is made ON. When an inactive master reset signal MRESET =1 is supplied to the request reception & clock control circuit 24 which is in the initial state, from the host processor 1', the state of the request reception & clock control circuit transits to a state S1. When the request reception & clock control circuit 24 in the state "S1" receives an active start signal START=1, the state of the request reception & clock control circuit 24 transits to the state "S2". In the state "S2", the request reception & clock control circuit 24 outputs an active U/D signal U/D=1 to the MPU clock generator 23, and waits for an asynchronous request signal from the host processor 1'. When the request reception & clock control circuit 24 in the state "S2" receives an active asynchronous request (interrupt request) signal ( INT =0) from the host processor 1', the state of the request reception & clock control circuit 24 transits to the state "S1", and outputs an inactive U/D signal U/D=0 to the MPU clock generator 23 to lower the frequency of the MPU clock signal. When the request reception & clock control circuit 24 receives an active complete signal COMPLETE=1 from the MPU clock generator 23, and then receives an active acknowledge signal TACK=1, the request reception & clock control circuit 24 transits to the state "S2". When an active master reset signal MRESET =0 is supplied to the request reception & clock control circuit 24 from the host processor 1', the request reception & clock control circuit 24 transits to the initial state "Init". The timing of an example operation of the MPU clock generator 23 of Fig. 6 is shown in Fig. 10. Figs. 11 and 12 (Sequence Responding to Interrupt or Hold Request) Although not shown, generally, a plurality of paths for supplying a plurality of asynchronous request signals to the processors and a plurality of paths for returning a plurality of acknowledge signals corresponding to the plurality of asynchronous request signals to the request reception & clock control circuit 24 are provided. The plurality of asynchronous request signals may include interrupt signals of a plurality of priority levels, and a hold request signal. Figure 11 is a diagram showing an example sequence in reception of an interrupt request signal by the parallel data processing apparatus 200 in Fig. 5. When the host processor 1' sends an interrupt request to the parallel data processing apparatus 200, the request reception & clock control circuit 24 starts the above-mentioned operation for lowering the frequency of the MPU clock signal. When the operation is completed, the request reception & clock control circuit 24 outputs a LOW SPEED INDICATION to the host processor 1', and outputs an interrupt request signal to the plurality of processors 22 1 , 22 2 , ··· 22 n . Upon receiving the interrupt request signal, the processors 22 1 , 22 2 , ··· 22 n carries out interrupt processing, and when the interrupt processing is completed, the processors returns an active interrupt acknowledge signal IACK =0 to the request reception & clock control circuit 24, and the operations according to the interrupt signal are commenced in the respective processors. Upon receiving the active interrupt acknowledge signal IACK =0, the request reception & clock control circuit 24 sends an INTERUPT ACKNOWLEDGE INDICATION to the host processor 1', and starts the above-mentioned operation for increasing the frequency of the MPU clock signal to the frequency of the master clock signal. When the operation is completed, the request reception & clock control circuit 24 sends a HIGH SPEED INDICATION to the host processor 1'. Figure 12 is a diagram showing an example sequence in reception of a hold request signal by the parallel data processing apparatus 200 in Fig. 5. When the host processor 1' sends a hold request to the parallel data processing apparatus 200, the request reception & clock control circuit 24 starts the above-mentioned operation for lowering the frequency of the MPU clock signal. When the operation is completed, the request reception & clock control circuit 24 outputs a LOW SPEED INDICATION to the host processor 1', and outputs a hold signal to the plurality of processors 22 1 , 22 2 , ··· 22 n . Receiving the hold request, the processors 22 1 , 22 2 , ··· 22 n carry out a hold processing. When the hold processing is completed, the processors return an active hold acknowledge signal HOLD A =0 to the request reception & clock control circuit 24, and the processors 22 1 , 22 2 , ··· 22 n go to a hold state. Upon receiving the active interrupt acknowledge signal HOLD A =0, the request reception & clock control circuit 24 sends a HOLD COMPLETE INDICATION to the host processor 1'. When receiving the HOLD COMPLETE INDICATION, the host processor 1' sends a release request signal to the request reception & clock control circuit 24, and the release request signal is transferred to the processors 22 1 , 22 2 , ··· 22 n . Responding to the release request signal, the processors 22 1 , 22 2 , ··· 22 n carries out release processing. When the release processing is completed, the processors returns an inactive hold acknowledge signal HOLD A =1 to the request reception & clock control circuit 24, and the processors 22 1 , 22 2 , ··· 22 n go to a normal state. Receiving the inactive hold acknowledge signal HOLD A =1, the request reception & clock control circuit 24 starts the above-mentioned operation for increasing the frequency of the MPU clock signal to the frequency of the master clock signal, and when the operation is completed, the request reception & clock control circuit 24 sends a HIGH SPEED INDICATION to the host processor 1'. Fig. 13 (Delay & Switch Circuit) Figure 13 is a block diagram showing a construction of the delay & switch circuit 25 r (r=1 to n) of Fig. 5. In Fig. 13, reference numerals 250, 252, 257, and 259 each denote a buffer amplifier, 251, 254, 255, and 258 each denote a selector, and 253 and 256 each denote a programmable delay circuit. In Fig. 13, reference numerals A to G respectively correspond to the denotations of the terminals of Fig. 5. The MPU clock signal is supplied from the delay time measuring & setting circuit 27 or one of the delay & switch circuits 25 1 , 25 2 , ··· 25 n-n to the delay & switch circuit of Fig. 13 through the input port C. The MPU clock signal passes through the buffer amplifier 250 and the selector 251. The selector 251 corresponds to one of the selectors 11a 1 , 11a 2 , ··· 11a n in Fig. 1. The output of the selector 251 is divided into two ways: a way to another (if any) of the delay & switch circuits 25 1 , 25 2 , ··· 25 n-1 on the downstream side of the path for supplying the MPU clock signal through the output port E, and the buffer amplifier 252 is provided on the way; and a way to a clock input terminal of the corresponding processor through the output port A, and the programmable delay circuit 253 and the selector 254 are provided on the way. The output of the selector 254 is further divided into two ways: a way connected through the output port E with the other delay & switch circuits 25 1 , 25 2 , ··· 25 n located on the downstream side (right side in Fig. 5); and a loop-back way toward the MPU clock generator 23. The loop-back way is connected with an input terminal of the selector 255. A timing signal output from the corresponding processor is applied to the other input terminal of the selector 255 through the input port B of the delay & switch circuit. The output of the selector 255 is applied to the programmable delay circuit 256, and the output of the programmable delay circuit 256 is applied to one of the input terminals of the selector 258. A signal returned toward the MPU clock generator 23 from the above other (if any) of the delay & switch circuits 25 1 , 25 2 , ··· 25 n on the downstream side of the path for supplying the MPU clock signal (on the upstream side of the path for returning a signal toward the MPU clock generator 23) through the output port F and the buffer amplifier 257 is also applied to the second input terminal of selector 258. The output of the selector 258 is output through the buffer amplifier 259 and the output port D. As indicated in Fig. 13, the buffer amplifier 257 is provided corresponding to the buffer amplifier 252; the selector 255 is provided corresponding to the selector 254; the programmable delay circuit 256 is provided corresponding to the programmable delay circuit 253; the selector 258 is provided corresponding to the selector 251; and the buffer amplifier 259 is provided corresponding to the buffer amplifier 250; in order to make symmetrical the ways for supplying a signal to the downstream side and for returning the signal from the downstream side to the upstream side. The above programmable delay circuit 253 corresponds to one of the programmable delay circuits 6a 1 , 6a 2 , ··· 6a n in the construction of Fig. 1, and the programmable delay circuit 256 corresponds to one of the programmable delay circuits 10a 1 , 10a 2 , ··· 10a n in Fig. 1. The delay times in the programmable delay circuits 253 and 256 are set through the port G which is connected to the control bus 28 in Fig. 5. Although the provision for initially adjusting the delay times in the programmable delay circuits 253 and 256 are not indicated in Fig. 13, this provision is explained in the fifth embodiment. In some parallel data processing apparatuses, a timing signal output from each processor is used for processing data. This timing signal is generated in each processor responding to the MPU clock signal input thereto, for example, by frequency dividing the MPU clock signal. In this case, the times at which the above timing signals are output from all of the processors 22 1 , 22 2 , ··· 22 n must be simultaneous. Therefore, in this case, a portion of each processor wherein the timing signal is generated must be included in the path of the signal in the measurement of the propagation delay time. Namely, the selector 255 must select the signal from the input port B in the delay & switch circuit of Fig. 13 when the delay & switch circuit is connected to the processor for which the propagation delay time is to be measured. Fig. 14 (Programmable Delay Circuit) Figure 14 is a block diagram showing an example construction of the programmable delay circuit 253 or 256 in the construction of Fig. 13. In Fig. 14, reference numeral 901 denotes a ramp voltage generator 902 denotes a digital to analog converter, and 903 denotes a comparator. The ramp voltage generator 902 generates a ramp voltage when triggered by an input of a leading edge of the MPU clock signal. The ramp voltage increases with a predetermined rate from the time of the above input of the leading edge. The digital to analog converter is a multiplication type digital to analog converter, outputs an analog voltage proportional to a delay time value set thereto and used as a reference voltage in the comparator 903. The comparator 903 compares the above ramp voltage with the above reference voltage. When the ramp voltage exceeds the reference voltage, the output of the comparator 903 rises. Thus, the programmable delay circuit of Fig. 14 delays the MPU clock signal by an amount determined by the delay time value set in the digital to analog converter. Since there is an offset in the output voltage of each of the digital to analog converter 902 and the ramp voltage generator 901, the delay time in the programmable delay circuit of Fig. 14 also has an offset. The provision for cancelling the affect of the above offset will be explained in the fifth embodiment of the present invention. Fig. 15 (Delay Time Measuring & Setting Circuit) Figure 15 is a block diagram showing an example construction of the delay time measuring & setting circuit 27 in the construction of Fig. 5. In Fig. 15, reference numerals 270, 271, and 273 each denote a buffer amplifier, 272 denotes a programmable delay circuit, 274 denotes a D-type flip-flop circuit, and 275 denotes a controller. In Fig. 15, reference numerals G to I respectively correspond to the denotations of the terminals of Fig. 5. A signal supplied from the MPU clock generator 23 is amplified through the buffer amplifier 270, and the output of the buffer amplifier 270 is divided into two ways: a way to the first delay & switch circuits 25 1 through the output port H, and the buffer amplifier 271 is provided on the way; and a way to an edge-triggered input terminal of the D-type flip-flop circuit 274. A signal input from the input port I is applied to the data input terminal of the D-type flip-flop circuit 274 through the buffer amplifier 273, and the Q output of the D-type flip-flop circuit 274 is monitored by the controller 275. Although the provision for initially adjusting the delay times in the programmable delay circuit 272 is not indicated in Fig. 15, this provision is explained in the fifth embodiment. After the above initial adjusting operation is completed, the controller 275 controls the selectors 258 in the delay & switch circuits 25 1 , 25 2 , ··· 25 n so that the output of the selector 254 in one of the delay & switch circuits 25 1 , 25 2 , ··· 25 n is loop-backed toward the delay time measuring & setting circuit 27, where the delay & switch circuit is connected through the port A to a processor for which the propagation delay time from the delay & switch circuit 27 is to be measured. Then, the delay & switch circuit 27 causes the master clock generator (not shown) to output a single timing pulse having a predetermined width when measuring the aforementioned propagation delay time. This operation is carried out in response to a command from the host processor 1' through the host CPU bus. The Q output of the D-type flip-flop circuit 274 becomes "1" when the timing of the input of the above single timing pulse into the edge-triggered input terminal of the flip-flop circuit 274 and the timing of the input of the above single timing pulse into the D input of the flip-flop circuit 274 coincide. Namely, the Q output of the D-type flip-flop circuit 274 becomes "1" when the delay time caused by the programmable delay circuit 272 coincides with the propagation delay time of the signal output from the output port H and then returned through the input port I. Therefore, the propagation delay time can be measured by scanning the delay time set in the programmable delay circuit 272 to find the delay time value which makes the Q output of the flip-flop circuit 274 "1". As explained before, the above measurement is carried out for all of the processors 22 1 , 22 2 , ··· 22 n . Figs. 16 to 28B (Fifth Embodiment) Figure 16 is a block diagram showing an arrangement of a plurality of the delay time measuring & setting circuit 27 k (k=1 to m) and the delay & switch circuit 25 kr (r=1 to n, k=1 to m) in the fifth embodiment of the present invention. As shown later in Figs. 17A and 17B, processors similar to the processors 22 1 , 22 2 , ··· 22 n are included in the block of the delay & switch circuit 25 kr (r=1 to n, k=1 to m). Although not shown in Fig. 16, all the construction other than the above delay time measuring & setting circuit 27 k (k=1 to m) and the delay & switch circuit 25 kr (r=1 to n, k=1 to m) is assumed to exist in the parallel data processing apparatus according to the fifth embodiment of the present invention. As shown in Fig. 16, the delay time measuring & setting circuits 25 kr (r=1 to n, k=1 to m) are arrayed in an nxm matrix arrangement. Each of the plurality of delay time measuring & setting circuits 27 k (k=1 to m) is connected to the delay & switch circuit 25 kr (r=1 to n, k=1 to m) which are arrayed on the K-th row. The delay & switch circuit 25 kr (r=1 to n, k=1 to m) on each row are chain connected to the corresponding delay time measuring & setting circuit 27k as the delay time measuring & setting circuit 25 1 , 25 2 , ··· 25 n in the construction of Fig. 5. The delay time measuring & setting circuit 27 k (k=1 to m) are also chain connected as shown in Fig. 16. Each of the delay time measuring & setting circuits 27 k (k=1 to m) measures propagation delay times to the respective processors in the respective delay & switch circuit 25 kr (r=1 to n, k=1 to m) on the same row as the delay time measuring & setting circuit 27 k . Then, the delay time measuring & setting circuits 27 1 measures propagation delay times of the remaining respective delay time measuring & setting circuits 27 k (k=2 to m). The above delay times, which are measured in the respective delay time measuring & setting circuits 27 k (k=2 to m), are transferred from controllers 275' (explained later with reference to Figs. 17A, 17B, 22A, and 22B) in the respective delay time measuring & setting circuits 27 k (k=2 to m) to the controller in the delay time measuring & setting circuits 27 1 . Thus, the delay time measuring & setting circuits 27 1 can obtain propagation delay times to the respective processors in the respective delay & switch circuit 25 kr (r=1 to n, k=1 to m) on the nxm matrix. Then, the controller 275' in the delay time measuring & setting circuit 27 1 sets the delay times in the programmable delay circuits on the routes for supplying the MPU clock signal to the processors in all of the delay & switch circuits 25 kr (r=1 to n, k=1 to m) in a way similar to that explained, so that the MPU clock signal simultaneously reaches the clock input terminal of the processors in all of the delay & switch circuits 25 kr (r=1 to n, k=1 to m). In Fig. 16, references e, f, g, h, i and j each denote an input or output port of the delay time measuring & setting circuit 27 k (k=1 to m), and a, b, c and d each denote an input or output port of the delay & switch circuit 25 kr (r=1 to n, k=1 to m). In each delay & switch circuit, the MPU clock signal is supplied to the input port a from the corresponding delay time measuring & setting circuit 27 k (k=1 to m) or another delay & switch circuit on the upstream side which is located closer to the delay time measuring & setting circuit. When the MPU clock signal is supplied from a delay & switch circuit, the clock signal is output at port C to another delay & switch circuit on the downstream side. The signal returning from the downstream side is input to the delay & switch circuit from the input port d, and the signal returning to the next delay & switch circuit is output from the output port b. The MPU clock signal supplied to the delay & switch circuit 25 k1 (k=1 to m) is output from the output port f of each delay time measuring & setting circuit. The MPU clock signal returned from the delay & switch circuit 25 k1 (k=1 to m) is input from the input port g of each delay time measuring & setting circuit. The MPU clock signal supplied to the delay time measuring & setting circuit 27 k (k=2 to m) is output from the output port h of each delay time measuring & setting circuit 27 k-1 (k=2 to m). The MPU clock signal returned from the delay time measuring & setting circuit 27 k (k=2 to m) is input from the input port i of each delay time measuring & setting circuit 27 k-1 (k=2 to m). The MPU clock signal supplied from the delay time measuring & setting circuit 27 k (k=1 to m-1) is input from the input port e of each delay time measuring & setting circuit 27 k+1 (k=1 to m-1). The MPU clock signal returned from each delay time measuring & setting circuit 27 k (k=2 to m) is output from the output port j of the delay time measuring & setting circuit 27 k (k=2 to m). Details of the delay & switch circuit 25 kr (r=1 to n, k=1 to m) and the delay time measuring & setting circuits 27 k (k=1 to m) and the operations of these circuits are explained below with reference to Figs. 17A to 28B. Figs. 17A to 17B (Delay & Switch Circuit) Figures 17A and 17B are diagrams showing the construction of the delay & switch circuit 25 kr (r=1 to n, k=1 to m) in the construction of Fig. 16. In Figs. 17A and 17B, reference numerals 22 1 to 22 4 each denote a processor, 250', 252', 257', and 259' each denote a buffer amplifier, 251', 254 1 to 254 4 , 255 1 to 255 4 , 258, 300, 302, 307, 308, 309, and 312 each denote a selector, 253 1 to 253 4 , 256', 304, and 305 each denote a programmable delay circuit, 275' denotes a controller, 301 1 to 301 4 and 306 each denote a D-type flip-flop circuit, 303 1 to 303 4 each denote a monostable multivibrator, 310 1 to 310 4 and 311 1 to 311 4 each denote a level converter, 314, 315, 353 1 to 353 4 , and 356 each denote an OR circuit. The processors 22 1 to 22 4 are those to which the MPU clock signal is to be supplied, and the selector 300 is provided for selecting one of the processors 22 1 to 22 4 to measure the propagation delay time from the delay time measuring & setting circuits 27 1 to the processor. The programmable delay circuits 253 1 to 253 4 each correspond to the programmable delay circuit 253 in the construction of Fig. 13, and the programmable delay circuit 256' corresponds to the programmable delay circuit 256 in Fig. 13. The D-type flip-flop circuits 301 1 to 301 4 are provided for use in determining initial delay times in the programmable delay circuits 253 1 to 253 4 . The selector 302 is provided for selecting one of the routes to be used when initially adjusting the delay times in the programmable delay circuits 253 1 to 253 4 , and a route to be used when measuring propagation delay times for the respective processors 22 1 to 22 4 . The level converters 310 1 to 310 4 and 311 1 to 311 4 are provided on both sides of the processors 22 1 to 22 4 for converting signal levels between ECL circuitry and TTL circuitry. In this embodiment, the circuitry around the processors 22 1 to 22 4 is realized by the TTL circuitry, and the other circuitry for supplying the MPU clock signal to the processors is realized by the ECL circuitry. The monostable multivibrators 3031 to 3034 are provided for supplying an asynchronous request signal having a predetermined duty ratio to the processors 22 1 to 22 4 when the circuitry of Figs. 17A and 17B is used for simultaneously supplying the asynchronous request signal to the processors 22 1 to 22 4 as in the second and third embodiments of Figs. 3 and 4. The selectors 254 1 to 254 4 each correspond to the selector 254 in Fig. 13, and the selectors 255 1 to 255 4 each correspond to the selector 255 in Fig. 13. In each processor, X2 denotes an edge-triggered input terminal, and H1 denotes an output terminal for the aforementioned timing signal generated in the processor. The programmable delay circuit 304 and the OR circuit 314 constitute a waveform shaping circuit for shaping a signal which passes therethrough, and the programmable delay circuit 305 and the OR circuit 315 constitute a waveform shaping circuit for shaping a signal which passes therethrough. These waveform shaping circuits are respectively provided in the path for supplying the MPU clock signal and the path for returning the MPU clock signal toward the MPU clock generator 23 in order to make symmetrical these paths. The D-type flip-flop circuit 306 is provided for use in detemining initial delay times in the programmable delay circuits 304 and 305. The OR circuit 314 receives tbe output of the corresponding programmable delay circuit 304, and a master reset signal which is supplied from the host processor 1', and the output of the OR circuit 314 is applied to a reset input terminal of the programmable delay circuit 304. The OR circuit 315 receives the output of the corresponding programmable delay circuit 305, and the master reset signal, and the output of the OR circuit 315 is applied to a reset input terminal of the programmable delay circuit 305. The OR circuits 353; to 3534 are respectively connected to the corresponding programmable delay circuits 253 1 to 253 4 in a way similar to the above waveform shaping circuits for shaping waveforms of the signals passing therethrough. The selector 307 is provided for seleating one of a route to be used when initially adjusting delay times in the programmable delay circuits 304 and 305, and a route to be used when the delay time measuring & setting circuit of Figs. 17A and 17B is used as a through path between the input port d to the output port b. The selector 308 is provided symmetricallity with the selector 300, and the selector 309 is provided for symmetricallity with the selector 302. The above selectors, the programmable delay circuits, and the flip-flop circuits are controlled and monitored by the controller 275' in the delay time measuring & setting circuit 27 k (k=1 to m). Figs. 18A to 21B (Signal Routes in Delay & Switch Circuit) Figures 18A and 18B are diagrams showing signal routes used when initially setting delay times in the programmable delay circuits 253 1 to 253 4 in the construction of Figs. 17A and 17B, for making symmetrical each pair of signal paths of the delay time measuring & setting circuit 27 k (k=1 to m). In Figs. 18A and 18B, the above routes, respectively provided for initially setting delay times in the programmable delay circuits 253 1 to 253 4 , are indicated by dashed lines along the corresponding signal lines in Figs. 17A and 17B. When initially setting delay times in the programmable delay circuits 253 1 to 253 4 , the controller 275' controls the selectors in the construction of Figs. 17A and 17B so that the above indicated routes are realized. Then, the controller 275' causes the master clock generator (not shown) to output a single timing pulse having a predetermined width when measuring the aforementioned propagation delay time. This operation is carried out in response to a command from the host processor 1' through the host CPU bus. A signal input into the input port a is applied through the buffer amplifier 250', the selectors 251', 308, and 309 to the programmable delay circuits 253 1 to 253 4 . The outputs of the programmable delay circuits 253 1 to 253 4 are respectively applied to the edge-triggered input terminal of the corresponding one of the flip-flop circuits 301 1 to 301 4 . The output of the selector 308 is applied to one input terminal of the selector 302. The applied signal is selected and is output from the selector 302 to be applied to the edge-triggered input terminal of the programmable delay circuit 256'. The output of the programmable delay circuit 256' is applied to the D input terminal of the flip-flop circuits 301 1 to 301 4 . The Q output of each of the D-type flip-flop circuits 301 1 to 301 4 becomes the "1" level when the timing of the input of the above single timing pulse into the edge-triggered input terminal of each flip-flop circuit and the timing of the input of the above single timing pulse into the D input of the flip-flop circuit coincide. Namely, the Q output of each D-type flip-flop circuit becomes "1" when the delay time caused by the corresponding programmable delay circuit 253 r coincides with the propagation delay time of the signal which propagates through the programmable delay circuit 256'. Thus, the controller 275' initially sets in the programmable delay circuit 253 r the delay time value which makes the Q output of the flip-flop circuit 253 r "1". Figures 19A and 19B are diagrams showing a signal route used when initially setting delay times in the programmable delay circuits 304 and 305 in the construction of Figs. 17A and 17B for making symmetrical each pair of signal paths of the delay time measuring & setting circuit 27 k (k=1 to m). The operation for initially setting delay times in the programmable delay circuits 304 and 305 is carried out in a way similar to the above operation for setting delay times in the programmable delay circuits 2531 to 2534. In the case of Figs. 19A and 19B, the single timing signal input through the input port a is applied through the buffer amplifier 250' and the selector 251' to the edge-triggered input terminal of the programmable delay circuit 304 and one input terminal of the selector 307. The above signal is selected by the selector 307 and applied to the edge-triggered input terminal of the programmable delay circuit 305. The output of the programmable delay circuit 305 is applied to the edge-triggered input terminal of the D-type flip-flop circuit 306. The above output of the selector 251' is also applied to the edge-triggered input terminal of the programmable delay circuit 304, and the output of the programmable delay circuit 304 is applied to the D input terminal of the flip-flop circuit 306. Thus, the controller 275' initially sets in the programmable delay circuit 304 the delay time value which makes the Q output of the flip-flop circuit 304 "1" when the above single timing pulse is input into the circuit of Figs. 19A and 19B. Figures 20A and 20B are diagrams showing a signal route used when measuring a time elapsing while a signal is propagated to the processor 22 1 , in the delay time measuring & setting circuit 27 k (k=1 to m) of the construction of Figs. 17A and 17B. After the above initial adjusting operations are completed, the controller 275' controls the selectors in the construction of Figs. 17A and 17B so that the signal routes as indicated by dashed lines α, β, and γ are realized, where the route α is a signal route passing from the input port a to the output port c, the route β is a signal route passing from the input port a to the output port b, and the route γ is a signal route inputting from the input port a, loop-backing in the construction of Figs. 20A and 20B, and outputting from the output port b. The signal routes α passes through the buffer amplifier 250', the selectors 251', 308, and 309, the programmable delay circuit 253 1 , the level converter 310 1 , the selectors 254 1 and 255 1 , the level converter 311 1 , the selectors 300 and 302, the programmable delay circuit 256', the selector 258, and the buffer amplifier 259', the signal routes β passes through the buffer amplifier 250', the selector 251', the programmable delay circuit 304, the selector 312, and the buffer amplifier 252', and the signal route γ passes through the buffer amplifier 257', the selector 307, the programmable delay circuit 305, the selector 258, and the buffer amplifier 259'. The signal routes α is used when measuring the propagation delay time of a signal to one of the processors in the delay & switch circuit which is located on the downstream side of the construction of Figs. 20A and 20B, and the signal routes β and γ are used when measuring the propagation delay time of a signal to one of the processors in the upstream side construction of Figs. 20A and 20B. Figures 21A and 21B are diagrams showing signal routes used for supplying the MPU clock signal during a normal operation of the parallel data processing apparatus in the fifth embodiment, in the delay time measuring & setting circuit 27 k (k=1 to m) of the construction of Figs. 17A and 17B. In Figs. 21A and 21B, δ1 denotes a signal route of the MPU clock signal to be supplied to a processor in the delay & switch circuit located on the downstream side the construction of Figs. 21A and 21B, and δ2 denotes signal routes of the MPU clock signal to be supplied to processors 22 1 to 22 4 in the construction of Figs. 21A and 21B. The signal route δ1 passes through the buffer amplifier 250', the selector 251', the programmable delay circuit 304, the selector 312, and the buffer amplifier 252', and the signal routes δ2 pass through the buffer amplifier 250', the selectors 251', 308, and 309, the programmable delay circuit 253 1 , the level converter 310 1 , the monostable multivibrator 303 1 , and the selectors 254 1 . Figs. 22A and 22B (Delay Time Measuring & Setting Circuit) Figures 22A and 22B are diagrams showing the construction of the delay time mesuring & setting circuit 27 k (k=1 to m) in the construction of Fig. 16. In Figs. 22A and 22B, reference numerals 271', 273', 276, 277, 278, and 279 each denote a buffer amplifier, 272', 400, 403, 404, 410, and 411 each denote a programmable delay circuit, 274', 405, and 412 each denote a D-type flip-flop circuit, 275' denotes a controller, 401, 402, 406, 407, 408, 409, 413, 414, 415, and 416 each denote a selector, and 372, 420, 423, 424, 430, and 431 each denote an OR circuit. In the construction of Figs. 22A and 22B, the buffer amplifiers 271' and 273' respectively correspond to the buffer amplifiers 271 and 273 in Fig. 15, the programmable delay circuit 272' corresponds to the programmable delay circuit 272 in Fig. 15, the D-type flip-flop circuit 274' corresponds to the D-type flip-flop circuit 274 in Fig. 15, and the controller 275' corresponds to the controller 275 in Fig. 15. The programmable delay circuit 400 is provided for initially adjusting a delay time in the programmable delay circuit 272' for compensating the aforementioned offset in the programmable delay circuit 272'. The selector 401 is provided for selecting one of a route for use when initially adjusting the delay times in the programmable delay circuits 272', and a route for use when measuring the propagation delay times. The selector 402 is provided for the symmetry with the provision of the selector 401. The programmable delay circuit 403 is provided for adjusting a delay time in a path from the input port for the MPU clock signal or the input port e to the output port f. The programmable delay circuit 404 is provided for initially adjusting a delay time in the programmable delay circuit 403. The D-type flip-flop circuit 405 is provided for use when determining initial delay times in the programmable delay circuits 403 and 404. The selector 406 is provided for selecting one of a route to be used when initially adjusting the delay times in the programmable delay circuits 403 and 404, and a route to be used when loop-backing a signal which is input from the input port e, to the output port j. The selector 407 is provided for selecting one of a route to be used when initially adjusting the delay times in the programmable delay circuits 403 and 404, and a route to be used when measuring the propagation delay times. The selector 408 is provided for the symmetry with the provision of the selector 406. The selector 409 is provided symmetrically with the selector 407. The programmable delay circuit 410 is provided for adjusting a delay time in a path from the input port for the MPU clock signal or the input port e to the output port h, and shaping a waveform of a signal passing therethrough. The programmable delay circuit 411 is provided for adjusting a delay time in a path from the input port i to the output port j, and shaping a waveform of a signal passing therethrough. The D-type flip-flop circuit 412 is provided for determining initial delay times in the programmable delay circuits 410 and 411. The selector 413 is provided for selecting one of a route to be used when initially adjusting the delay times in the programmable delay circuits 410 and 411, and a route to be used when measuring the propagation delay times. The selector 414 is provided for the symmetry with the provision of the selector 413. The selector 415 is provided for selecting one of a route to be used when measuring the propagation delay times to another delay time measuring & setting circuits located in lower rows as shown in Fig. 16 for delay time measuring & setting circuits 27k (k=1 to m) and a route to be used when measuring the propagation delay times of a signal propagated to a processor in one of the delay & switch circuits which are arrayed on the same row as the delay time measuring & setting circuit of Figs. 22A and 22B. The selector 416 is provided for selecting one of a route to be used for the MPU clock signal from the MPU clock input terminal of the construction of Figs. 22A and 22B, and a route to be used for the MPU clock signal supplied from a delay time measuring & setting circuit located above the construction of Figs. 22A and 22B in a previous row as shown in Fig. 16. The programmable delay circuit 403 and the OR circuit 423, the programmable delay circuit 404 and the OR circuit 424, the programmable delay circuit 410 and the OR circuit 430, and the programmable delay circuit 411 and the OR circuit 431, respectively, function as a waveform shaping circuit for shaping a signal which passes therethrough. The above selectors, the programmable delay circuits, and the flip-flop circuits are controlled and monitored by the controller 275' in the delay time measuring & setting circuit 27 k (k=1 to m). Figs. 23A to 28B (Signal Routes in Delay & Switch Circuit) Figures 23A and 23B are diagrams showing signal routes which are used when initially setting delay times in the programmable delay circuits 272', 400, 403, 404, 410, and 411 in the construction of Figs. 22A and 22B for making symmetrical each pair of signal paths of the delay & switch circuit 25 kr (r=1 to n, k=1 to m). In Figs. 23A and 23B, the above routes respectively for initially setting delay times in the programmable delay circuits 272', 400, 403, 404, 410, and 411 are indicated by dashed lines along the corresponding signal lines in Figs. 22A and 22B. When initially setting delay times in the programmable delay circuits 272', 400, 403, 404, 410, and 411, the controller 275' controls the selectors in the construction of Figs. 22A and 22B so that the above routes as indicated by dashed lines ε, ζ, and η, are realized. Then, the controller 275' causes the master clock generator (not shown) to output a single timing pulse having a predetermined width when measuring tbe aforementioned propagation delay time. This operation is carried out in response to a command from the host processor 1' through the host CPU bus. The route ε is a signal route used when the initial delay times of the programmable delay circuits 272' and 400 are determined to be set thereto. In this case, the initial delay times are set thereto so that a propagation delay time of a signal which passes through the selector 402 and the programmable delay circuit 272', and a propagation delay time of a signal which passes through the selector 401 and the programmable delay circuit 400 are the same. The initial delay times to be set are determined by the controller 275' by setting a certain delay time in one of the programmable delay circuits 272' and 400, scanning the delay time in the other of the programmable delay circuits 272' and 400, and monitoring the Q output of the D-type flip-flop circuit 274'. The route ζ is a signal route used when the initial delay times of the programmable delay circuits 403 and 404 are determined to be set thereto. In this case, the initial delay times are set thereto so that a propagation delay time of a signal which passes through the selector 409, the programmable delay circuit 403, and the selector 408, and a propagation delay time of a signal which passes through the selectors 406 and 407 and the programmable delay circuit 404 are the same. The initial delay times to be set are determined by the controller 275' by setting a certain delay time in one of the programmable delay circuits 403 and 404, scanning the delay time in the other of the programmable delay circuits 403 and 404, and monitoring the Q output of the D-type flip-flop circuit 405. The route η is a signal route used when the initial delay times of the programmable delay circuits 410 and 411 are determined to be set thereto. In this case, the initial delay times are set thereto so that a propagation delay time of a signal which passes through the programmable delay circuit 410 and the selector 414, and a propagation delay time of a signal which passes through the selector 413 and the programmable delay circuit 411 are the same. The initial delay times to be set are determined by the controller 275' by setting a certain delay time in one of the programmable delay circuits 410 and 411, scanning the delay time which has not been set in the other of the programmable delay circuits 410 and 411, and monitoring the Q output of the D-type flip-flop circuit 412. Figures 24A and 24B are diagrams showing a signal route which is used in the delay time measuring & setting circuit 27 k (k=1 to m) of the construction of Figs. 22A and 22B when measuring a time elapsing while a signal is propagated to a processor connected to one of the delay & switch circuits 25 kr (r=1 to n, k=1 to m) in the same row as the delay time measuring & setting circuit 27 k (k=1 to m) in the arrangement of Fig. 16. In Figs. 24A and 24B, the above routes are indicated by dashed lines along the corresponding signal lines in Figs. 22A and 22B. As shown in Figs. 24A and 24B, a signal input from the MPU clock input terminal, is propagated in two ways. Namely, the signal on the first way passes through the selector 402 and the programmable delay circuit 272' to be applied to the edge-triggered input terminal of the flip-flop circuit 274', and the signal propagated on the second way passes through the selectors 416 and 409 and the programmable delay circuit 403 and is output from the output port f to be propagated to a clock input terminal of an objective processor, to be loop-backed at the clock input terminal, and to be returned therefrom. The returned signal is then input from the input port g, and passes through the selector 407, the programmable delay circuit 404, the selector 401, and the programmable delay circuit 400 to be applied to the D input terminal of the flip-flop circuit 274'. Thus, the controller 275' can measure the propagation delay time value which makes the Q output of the flip-flop circuit 274' "1" when the above single timing pulse is input into the MPU clock input terminal of the circuit of Figs. 22A and 22B. Figures 25A and 25B are diagrams showing a signal route used in the delay time measuring & setting circuit 27 k (k=1 to m) of the construction of Figs. 22A and 22B when the delay time measuring & setting circuit 27 1 in Fig. 16 measures a time elapsing while a signal is propagated to another delay time measuring & setting circuit 27 k' (k'=2 to m) in the same column as the delay time measuring & setting circuit 271 in the arrangement of Fig. 16. In Figs. 25A and 25B, the above routes are indicated by dashed lines along the corresponding signal lines in Figs. 22A and 22B. After the above initial adjusting operations are completed, the controller 275' controls the selectors in the construction of Figs. 22A and 22B so that the signal routes are as indicated by the dashed lines. As shown in Figs. 25A and 25B, a signal input from the MPU clock input terminal, is propagated in two ways. The signal on the first way passes through the selector 402 and the programmable delay circuit 272' to be applied to the edge-triggered input terminal of the flip-flop circuit 274', and the signal propagated on the second way passes through the programmable delay circuit 410 and the selector 414 and is output from the output port h to be propagated to a clock input terminal of an objective processor, to be loop-backed at the clock input terminal, and to be returned therefrom. The returned signal is then input from the input port i, and passes through the selector 413, the programmable delay circuit 411, the selector 415, the selector 401, and the programmable delay circuit 400 to be applied to the D input terminal of the flip-flop circuit 274'. Thus, the controller 275' can measure the propagation delay time value which makes the Q output of the flip-flop circuit 274' "1" when the above single timing pulse is input to the MPU clock input terminal of the circuit of Figs. 22A and 22B. Figures 26A and 26B are diagrams showing a signal route used in the delay time measuring & setting circuit 27 k (k=2 to m-1) of the construction of Figs. 22A and 22B when the delay time measuring & setting circuit 27 1 in Fig. 16 measures a time elapsing while a signal is propagated to another delay time measuring & setting circuit 27 k' (k'=3 to m), where the shown delay time measuring & setting circuit 27 k is midway the signal propagation path in the arrangement of Fig. 16. After the above initial adjusting operations are completed, the controller 275' controls the selectors in the construction of Figs. 22A and 22B so that the signal routes as indicated by dashed lines  and , are realized, where the route  is a signal route passing from the input port e to the output port h, and the route is a signal route passing from the input port i to the output port j. The signal route  passes through the buffer amplifier 276, the selector 416, the programmable delay circuit 410, the selector 414, and the buffer amplifier 277. The signal route passes through the buffer amplifier 278, the selector 413, the programmable delay circuit 411, the selector 415, and the buffer amplifier 279. Figures 27A and 27B are diagrams showing a signal route used in the delay time measuring & setting circuit 27 k (k=2 to m) of the construction of Figs. 22A and 22B when the delay time measuring & setting circuit 271 in Fig. 16 measures a time elapsing while a signal is propagated to the delay time measuring & setting circuit 27 k . After the above initial adjusting operations are completed, the controller 275' controls the selectors in the construction of Figs. 22A and 22B so that the signal route as indicated by a dashed line is realized, where the route  is a signal route passing from the input port e to the output port j. The signal routes  passes through the buffer amplifier 276, the selectors 416 and 409, the programmable delay circuit 403, the selectors 408, 406, and 407, the programmable delay circuit 404, the selector 415, and the buffer amplifier 279. Figures 28A and 28B are diagrams showing a signal route used in the delay time measuring & setting circuit 27 k (k=1 to m) of the construction of Figs. 22A and 22B during a normal operation of the parallel data processing apparatus in the fifth embodiment, where the routes κ1 and κ2 are used by the delay time measuring & setting circuit 27 1 in Fig. 16, and the routes λ1 and λ2 are used by the delay time measuring & setting circuit 27 k' (k'=2 to m) in the arrangement of Fig. 16. In Figs. 28A and 28B, the MPU clock signal input from the MPU clock input terminal of the delay time measuring & setting circuit 27 1 passes through buffer amplifier 276 and the selectors 416 and 409, the programmable delay circuit 403 and the buffer amplifier 271' (the route κ1), and is output from the output port f to the delay & switch circuits 25 1r (r=1 to n). In addition, the above MPU clock signal passes through the programmable delay circuit 410, the selector 414, and the buffer amplifier 277 (the route κ2), and is output from the output port h to the delay time measuring & setting circuits 27 k' (k'=2 to m). In the other delay time measuring & setting circuits 27 k (k=2 to m), the MPU clock signal supplied from one of the delay time measuring & setting circuit 27 k-1 (k=2 to m) located above the delay time measuring & setting circuit 27 k' (k'=2 to m), through the input port e and the buffer amplifier 276. The MPU clock signal output from the buffer amplifier 276 is propagated on the same ways (λ1 and λ2) as the above routes κ1 and κ2, respectively.

Claims: An apparatus for supplying a signal to be simultaneously received by data processing units (3 1 , 3 2 , ···, 3 n ), comprising: a plurality of first signal paths (15, 33a1, 33a2, ···, 33an) each for supplying the signal from a common position to one of the data processing units, a plurality of second signal paths (16, 34a1, 34a2, ···, 34an) each for returning the signal from one of the data processing units to said common position, where each of the plurality of second signal paths forms a pair with a corresponding one of the first signal paths, characterized by offset adjusting means (12a) for initially equalizing signal propagation delays in the first and second signal paths of each pair, delay measuring means (7a) for measuring delays while the signal is propagated from said common position to the data processing units and then returned to said common position through each pair of the first and second signal paths, and delay adjusting means (7a) for adjusting the delays measured by the measuring means to equalize delays in all of the pairs of the first and second signal paths. An apparatus according to claim 1, wherein each of the first and second signal paths in said plurality of pairs of signal paths comprises variable delay means (6a1, 6a2,···, 6an, 10a1, 10a2, ···, 10an) for delaying a propagation of said signal through said first and second signal paths. An apparatus according to claim 2, wherein said delay adjusting means adjusts the delays caused by the variable delay means (6a1, 6a2, ···, 6an, 10a1, 10a2, ···, 10an) in the first and second signal paths of said each of the plurality of pairs of signal paths, based on a measurement performed by the delay measuring means (7a). An apparatus according to any of claims 2 or 3, wherein said offset adjusting means (12a) initially adjusts delays caused by the variable delay means in the first and second signal paths of said each of the plurality of pairs of signal paths before said delay measuring means measures the delay. An apparatus according to any of claims 1 to 4, wherein said first signal path (15, 33a1, 33a2, ···, 33an) of each of the plurality of pairs of signal paths shares a common supply-side path (15), said common supply-side path comprises at least one branch means (11a1, 11a2, ···, 11an) each for branching the signal from the common supply-side path to a supply-side branch path, said supply-side branch path propagating said signal, from each branch means to the corresponding processor, and said second signal path of each of the plurality of pairs of signal paths (16, 34a1, 34a2, ···, 34an) shares a common return-side path (16), said common return-side path comprises at least one return-side branch path for propagating said signal from the corresponding processor to the common return-side path, and at least one joining means each for joining one of the at least one returnside branch path to the common return-side path. An apparatus according any of claims 2 to 5, wherein said variable delay means is provided on each of said supply-side branch path and said return-side branch path. An apparatus according to any of claims 2 to 5, wherein said variable delay means is provided on each of said common supply-side path and said common return-side path. An apparatus according to any of claims 5 to 7, wherein said plurality of processors (3 1 , 3 2 , ···, 3 n ) are arranged in a predetermined order, said common returnside path (16) being connected to the plurality of processors through at least one of said at least one joining means (9a1, 9a2, ···, 9an) and one of said at least one return-side branch path, and each joining means (9a1, 9a2, ···, 9an) comprises a selector for receiving a first signal propagated from one of the at least one return-side branch path, and a second signal propagated from said common return-side path (16) on the upstream side of the selector, selecting one of the first and second signals resulting in a selected signal, and outputting the selected signal onto said common returnside path (16) on the downstream side of said selector. An apparatus according to any of claims 1 to 8, further comprising waveform shaping means (13a, 13a', 13b, 13b') in each of the first and second signal paths of said each of the plurality of pairs for shaping the signal when the signal is transmitted through said waveform shaping means. An apparatus for parallel data processing according to any of claims 1 to 9 comprising: a plurality of processors (3 1 , 3 2 , ···, 3 n ) for processing data in parallel, said plurality of processors processing in synchronization with a common clock signal, and starting an operation upon receiving a common asynchronous request signal; and clock generating means (4) for generating a common clock signal to be supplied to said plurality of processors; said parallel data processing apparatus further comprises said apparatus as described in one of claims 1 and 5, for supplying a predetermined one of said common clock signal and said common asynchronous request signal as said signal described in claim 1, to said plurality of processors as said data processing units described in claim 1. An apparatus according to claim 10, wherein a plurality of signal paths (17) are realized by equal-length wiring for supplying the other of said common clock signal and said common asynchronous request signal to the plurality of processors. An apparatus according to any of claims 10 or 11, further comprising; a device located external to said parallel data processing apparatus for supplying the common asynchronous request signal; asynchronous request signal reception control means (24) for receiving the common asynchronous request signal supplied from said device located external to said parallel data processing apparatus; and clock frequency controlling means (23) for temporarily lowering a frequency of the common clock signal to a predetermined frequency when said asynchronous request signal reception control means receives the common asynchronous request signal supplied from said device located external to said parallel data processing apparatus; and said asynchronous request signal reception control means (24) supplying said common asynchronous request signal to each of the plurality of processors when the frequency of the common clock signal is lowered to the predetermined frequency. A method for supplying a signal to be simultaneously received by processors, comprising the steps of: (a) supplying the signal from a common position to the processors through a plurality of signal supplying paths, (b) returning the signal from the processors to said common position through a plurality of signal returning paths, where each of the plurality of signal returning paths forms a pair with a corresponding one of the signal supplying paths, characterized by (c) initially equalizing signal propagation delays in the signal supplying path and the signal returning path of each pair, (d) measuring delays while the signal is propagated from said common position to the processors and then returned to said common position through each pair of the signal supplying and signal returning paths, and, (e) adjusting said delays measured in step (d) to equalize delays in all of the pairs of the signal supplying and signal returning paths. A parallel data processing system comprising: a plurality of processors (3 1 , 3 2 , ···, 3 n ) for processing data in parallel, said plurality of processors processing in synchronization with a common clock signal, and starting an operation upon receiving a common asynchronous request signal; and clock generating means (4) for generating a common clock signal to be supplied to said plurality of processors; said parallel data processing system further comprises, a first apparatus having the construction as described in one of claims 1 to 9, for supplying said common clock signal as said signal described in claim 1, to said plurality of processors as said data processing units described in claim 1, and a second apparatus having the construction as described in one of claims 1 to 9, for supplying said common asynchronous request signal as said signal described in claim 1, to said plurality of processors as said data processing units described in claim 1.

Inventors: ICIKI HIROKI, KATO HIDEKI, MASUMOTO DAIKI, YOSHIZAWA HIDEKI, ICIKI, HIROKI, KATO, HIDEKI, MASUMOTO, DAIKI, YOSHIZAWA, HIDEKI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1991
Main classification: G06F15
IPC codes: G06F15, G06F9, G06F1