Semiconductor device having an insulating film

Abstract: There is disclosed a semiconductor device comprising a semiconductor substrate (10), a plurality of bonding pads arranged along at least one side of the semiconductor substrate, and an insulating film (13,17) provided between at least one side of the semiconductor substrate and the bonding pads opposite to that side, and provided with means for preventing immersion of moisture, thereby to prevent moisture from being immersed from the chip side surface. Further, there is also disclosed a method of manufacturing such a semiconductor device, which comprises the steps of forming an insulating film on a semiconductor wafer, forming a plurality of bonding pads arranged along dicing lines of the semiconductor wafer, and forming a contact hole or a via hole in the insulating film, and forming at the same time, a groove structure so that it is arranged between the dicing lines and the plurality of bonding pads.

Description: BACKGROUND OF THE INVENTION This invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a technology to improve moisture resistance of a semiconductor device. In semiconductor devices, aluminum wiring is frequently used at present. However, aluminum wiring is apt to be extremely corroded. Such a wiring corrosion is simply called corrosion, and is the very serious problem from a viewpoint of reliability of the semiconductor integrated circuit device. One of the cause to corrode aluminum wiring is moisture. By immersion of moisture, the moisture resistance of the semiconductor device is deteriorated. Particularly, in so called plastic packages molded by plastic resin, adhesion between the plastic resin and metal such as copper serving as a lead is poor. As a result, it is difficult to completely prevent moisture from being immersed from the lead portion on the package side surface. Further, the plastic resin itself somewhat has hygroscopic property. For this reason, as the measure for improving moisture resistance of the semiconductor chip, passivation film (surface protective film) is conventionally used. For such a passivation film, a layered product comprised of a silicon nitride film (Si 3 N 4 ), or Si 3 N 4 /PSG film, etc. is used. This passivation film can advantageously protect moisture from the upper direction of the semiconductor chip from being immersed. Meanwhile, in the process for manufacturing semiconductor devices, after a passivation film is formed on the entire surface of the wafer, the wafer is subjected to dicing. Thus, chips are quarried. In this case, however, since the side surface of the chip having a cutting plane is not covered by the passivation film, immersion of moisture from the chip side surface constitutes a great problem. Namely, moisture immersed comes into contact with BPSG film or PSG used as an insulating film to produce phosphoric acid. This phosphoric acid corrodes aluminum wiring, etc. As stated above, the conventional semiconductor devices have the problem that aluminum wirings and/or elements in the chip would be corroded by immersion of moisture from the side surface where there is a cutting plane of a semiconductor chip formed by dicing a semiconductor wafer, disadvantageously resulting in an unsatisfactory operation. US-4,001,872 relates to a plastic-packaged semiconductor device including a semiconductor chip with a hermetic passivation and metallization system, where the device has an improved resistance against adverse ambient conditions such as water vapor and corrosive atmospheres. This document discloses a device having a protective surface coating having a first layer and a top layer for the prevention of water from entering from the top. This document, however, nowhere mentions moisture intruding from the sides. JP-62181436 discloses a semiconductor device where a first protection film having compressive internal stress is covered by a second protection film having tensile internal stress, and where grooves are provided in the first protection film. The second protection film fills the grooves in the first protection film. This document also does not address the problem of moisture intruding from the side. JP-59043557 discloses a semiconductor device where a scribing region of the periphery of a substrate is formed with strip grooves for preventing moisture from infiltrating along the periphery of the substrate. The scribing region is 400 to 600 µm wide and formed in the substrate. This document does not mention the problem of moisture intruding between insulative layers from the side. SUMMARY OF THE INVENTION With the above-mentioned problems with the conventional semiconductor device in view, an object of this invention is to prevent moisture from the semiconductor chip side surface from being immersed, thus to improve the moisture resistance of the semiconductor device. In accordance with the first aspect, there is provided a semiconductor device having the features of claim 1, and in accordance with the second aspect, there is provided a method of manufacturing a semiconductor device having the steps of claim 10. Preferred and advantageous embodiments are disclosed in the corresponding subclaims. BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings; FIG. 1 is a cross sectional view showing a semiconductor device according to a prior art; FIG. 2 is a plan view showing a semiconductor device according to another prior art; FIGS. 3A to 3F are cross sectional views showing successive process steps for manufacturing a semiconductor device of a first embodiment according to this invention, respectively; FIGS. 4A to 4E are cross sectional views showing successive process steps for manufacturing a semiconductor device of a second embodiment according to this invention, respectively; FIG. 5 is a cross sectional view showing a semiconductor device that is useful in understanding the invention ; FIG. 6 is a cross sectional view showing a third embodiment according to this invention; FIGS. 7A to 7C are cross sectional views showing successive process steps of a fourth embodiment according to this invention ; FIG. 8 is a schematic view showing a fifth embodiment according to this invention; FIG. 9 is a plan view showing the entirety of the semiconductor chip 51 shown in FIG. 8, FIG. 10 is a plan view showing a modification of the groove structure, FIG. 11 is a plan view showing that a plurality of groove structures as shown in FIG. 10 are provided; FIG. 12 is a plan view showing a modification of the groove structure shown in FIG. 10; FIG. 13 is a plan view showing a sixth embodiment, and FIGS. 14A and 14B are cross sectional views showing a semiconductor device. DESCRIPTION OF THE PREFERRED EMBODIMENTS For better understanding of this invention, the problems with the prior art will now be described in detail with reference to the attached drawings. FIG. 1 is a cross sectional view showing a semiconductor chip end of a semiconductor device according to the prior art provided by dicing a semiconductor wafer, and FIG. 2 is a plan view showing a semiconductor device according to another prior art. The semiconductor chip is divided into the device region where elements at the central portions, wirings and bonding pads, etc. are ordinarily formed and the non-device region existing around the semiconductor chip. As shown in FIG. 1, in the case of a semiconductor device according to the prior art, immersion of moisture from the upper direction of the chip can be prevented by a Si 3 N 4 film 20 serving as a surface protective film. In this case, however, on the chip side surface subjected to dicing along the dicing lines of the semiconductor wafer, a field oxide film 11, a BPSG (phospho-silicate glass including boron) film 13 and a SiO 2 film 17, etc. located below the Si 3 N 4 film 20 are exposed on a semiconductor substrate 10. On the semiconductor substrate 10, a polysilicon electrode 12, an aluminum wiring 16 of the first layer connected to the polysilicon electrode, and an aluminum wiring 19 of the second layer are formed. In the semiconductor device shown in FIG. 2, a region 53 where a plurality of elements such as transistors and capacitors, etc., and wirings are formed (hereinafter called a functional region) and wirings 57 are formed. Along respective sides of the semiconductor chip, bonding pads 52 connected to the external are formed, and these wirings 57 electrically connect the bonding pads 52 and the internal circuit. Accordingly, the device region of the semiconductor device indicates the portion including the functional region, wirings and bonding pads. However, as understood from this figure, the portion 531 of the functional region 53 is close to the side 54 serving as the chip end portion. Namely, the width of the non-device region is narrow. For this reason, moisture is immersed from the chip side surface. As a result, aluminum wirings and/or elements are corroded, so unsatisfactory operation is apt to take place. This is confirmed by the moisture resistance test, etc. Meanwhile, the immersion path of moisture is the interfacial portion between films. It has been known that moisture is apt to be immersed between films of poor adhesion, e.g., a BPSG film (phospho-silicate glass film including boron) and a PCVD SiO 2 (SiO 2 formed by the plasma CVD process). This PCVD SiO 2 film has not so satisfactory relationship with other films including PSG film. Preferred embodiments of this invention implemented in order to solve the above-mentioned problems will now be described. A first embodiment of this invention will be first described with reference to FIG. 3. FIG. 3A shows a cross section of a portion of the semiconductor chip. A field oxide film 11 and a polysilicon electrode layer 12 are formed on a silicon semiconductor substrate 10. A SiO 2 film is formed thereon by low pressure CVD (Chemical Vapor Deposition) process at a temperature of about 400°C. Further, a BPSG film is formed thereon to thereby form a BPSG/CVD SiO 2 film 13 of the two-layer structure serving as an insulating film. The side surface A on the right hand shows one side of the semiconductor chip provided by cutting or quarrying a silicon wafer along a dicing line. As shown in FIG. 3B, by etching the BPSG/CVD SiO 2 film 13 by making use of a resist film exposed using a photomask (not shown), a contact hole 14 and a groove structure 15 are formed at the same time. At this time, the groove structure 15 is formed so as to reach the field oxide film 11. The width of the groove structure is 10 µm, and the depth thereof is about 1 µm. In this figure, a portion of the field oxide film 11 is etched. In this case, if the adhesion between the BPSG/CVD SiO 2 film 13 and the SiO 2 film formed thereon is poor, it is sufficient that at least BPSG/CVD SiO 2 film 13 is completely etched. Further, if the adhesion between the BPSG film of the BPSG/CVD SiO 2 film 13 and the SiO 2 film formed thereon is poor, it is sufficient that at least the BPSG film is completely etched. Namely, if there is employed an approach such that two films of poor adhesion are not connected, satisfactory effects or advantages are provided. As shown in FIG. 3C, aluminum is then vacuum-deposited by sputtering to apply patterning thereto so as to take a desired form by making use of a photomask (not shown) to thereby form an aluminum wiring 16 of the first layer. Then, as shown in FIG. 3D, a PCVD SiO 2 film 17 serving as an interlayer insulating film is deposited on the aluminum wiring 16 of the first layer, on the field oxide film 11, and on the BPSG/CVD SiO 2 film 13 by the plasma CVD process at about 300°C. Then, as shown in FIG. 3E, a via hole 18 is formed by the reactive ion etching process by making use of a photomast (not shown). Subsequently, as shown in FIG. 3F, aluminum is vacuum-deposited by sputtering to apply patterning thereto to form an aluminum wiring 19 of the second layer. Finally, a Si 3 N 4 film 20 serving as a surface protective film is deposited by the low pressure CVD process at a temperature of about 400°C. As shown, the groove structure 15 is arranged in the non-device region from the side surface A of the semiconductor chip to the portion where bonding pads (not shown) positioned internally therefrom are formed. A second embodiment of this invention will now be described with reference to FIGS. 4A to 4E. As shown in FIG. 4A, a SiO 2 film is formed, by the CVD process, on a field oxide film 11 and a polysilicon electrode 12 formed on a silicon semiconductor substrate 10. Further, a BPSG film is formed thereon to form a BPSG/CVD SiO 2 film 13 serving as an insulating film of the two-layer structure. The end surface A on the right hand indicates one side of a semiconductor chip of this embodiment. Then, by etching the BPSG/CVD SiO 2 film 13 by making use of a photomask (not shown), a contact hole 14 is formed. At this stage, the groove structure is not yet formed. Then, as shown in FIG. 4B, aluminum is vacuum-deposited by sputtering to apply patterning thereto so as to take a desired form, thus to form an aluminum wiring 16 of the first layer. Then, as shown in FIG. 4C, a PCVD SiO 2 film 17 serving as an interlayer insulating film is deposited by the plasma CVD process. Then, as shown in FIG. 4D, a via hole 18 and a groove structure 15 are formed by reactive ion etching at the same time by making use of a photomask (not shown). The width of the groove structure is approximately 12 µm and the depth thereof is approximately 1.7 µm. Further, aluminum is vacuum-deposited to apply patterning thereto to form an aluminum wiring 19 of the second layer. Finally, a Si 3 N 4 film 20 serving as a surface protective film is formed by the decompressed CVD process. A semiconductor device of a structure as shown in FIG. 4E is formed. As shown in this figure, the groove structure 15 is formed in the non-device region from one side (right side surface A) of the semiconductor chip to bonding pads (not shown) therein. An example for forming a groove structure by making use of both the process for forming the contact hole and the process for forming the via hole will now be described with reference to FIG. 5. In FIG. 5, a field oxide film 11 is formed on a semiconductor substrate 10, and a polysilicon electrode 12 and a BPSG/CVD SiO 2 film 13 of the two-layer structure are formed thereon. On the polysilicon electrode 12 and the BPSG/CVD SiO 2 film 13 of the two-layer structure, an aluminum wiring 16 of the first layer and a PCVD SiO 2 film 17 are formed in order recited by the plasma CVD process. A via hole is provided in the PCVD SiO 2 film 17. By this via hole, contact between the aluminum wiring of the second layer and the aluminum wiring 16 of the first layer is provided. Since the groove structure 15 is formed by making use of both the contact hole formation process and the via hole formation process, the Si 3 N 4 /PSG film 21 serving as a surface protective film reaches the semiconductor substrate 10. It is to be noted that the surface of the semiconductor substrate 10 is completely covered with this Si 3 N 4 /PSG film 21. The depth of the groove structure 15 at this time is approximately 2.4 µm. The right side surface A indicates one side of the semiconductor chip of this embodiment. This groove structure 15 is formed in the non-device region from that side to bonding pads (not shown) provided therein. In this example, at the time of forming a groove structure in the via hole formation process, the substrate is exposed. However, since there is the possibility that pollution impurities may be immersed into the substrate, according to the invention it is necessary to allow the field oxide film to be left to a little extent without completely removing it by etching. Further, the groove structure at two processes may be arranged at different positions, respectively. While the groove structure may be formed at any process step as previously described, an approach may be employed to etch at least one of two films of poor adhesion whereby the contact surface of two films of poor adhesion is cut off, whereas two films of good adhesion are connected. Thus, effective advantages are provided. A third embodiment in the case where the aluminum wiring is of a single layer structure will now be described with reference to FIG. 6. In FIG. 6, a polysilicon electrode 12 and a BPSG/CVD SiO 2 film 13 of the two-layer structure are formed on a field oxide film 11 formed on a silicon semiconductor substrate 10. Further, on the polysilicon electrode 12 and the BPSG/CVD SiO 2 film 13 of the two-layer structure, an aluminum wiring 16 and a Si 3 N 4 film 20 serving as a surface protective film are formed in a stacked manner in order recited. The right side surface A indicates one side of the semiconductor chip of this embodiment. A groove structure 15 is arranged in the non-device region from that side to the region where bonding pads in the chip are formed. It is further noted that this invention provides the advantages also in semiconductor devices having an aluminum wiring of three layers or more. A fourth embodiment will now be described with reference to FIGS. 7A to 7C. First, a SiO 2 film is formed by the low-pressure CVD process at a temperature of about 400°C on a field oxide film 11 and a polysilicon electrode 12 formed on a silicon semiconductor substrate 10. Further, a BPSG film is formed thereon to thereby form a BPSG/CVD SiO 2 film 13 of two-layer structure serving as an interlayer insulating film. Then, the BPSG/CVD SiO 2 film 13 is etched by making use of a photomask (not shown) to form a contact hole 14 and a groove structure 15 at the same time. The groove structure 15 is formed so as to reach the field oxide film 11. The width of the groove structure is about 10 µm. While a portion of the field oxide film 11 is also etched in the case of this figure, in the case where adhesion between the BPSG/CVD SiO 2 film and the SiO 2 film formed thereon is poor, it is sufficient that at least the BPSG/CVD SiO 2 film is completely etched so that two films of poor adhesion are not connected at the groove structure portion. Then, tungsten 23 is filled into the contact hole 14 by the buried CVD process, and the same tungsten 22 is buried also into the groove structure 15 at the same time (FIG. 7A). Thereafter, aluminum is vacuum-deposited on the contact hole 14 and the BPSG/CVD SiO 2 film 13 by sputtering to apply patterning thereto so as to take a desired form by making use of a photomask to form an aluminum wiring 16 of the first layer. This wiring 16 is electrically connected to the polysilicon electrode 12 through the tungsten 22 in the contact hole 14. Thereafter, a PCVD SiO 2 film 17 serving as an interlayer insulating film is deposited by the plasma CVD process at a temperature of about 300°C on the BPSG/CVD SiO 2 film 13 and the tungsten 22 in the groove structure 15 including the wiring 16. This insulating film 17 is subjected to reactive etching by making use of a photomask (FIG. 7B). In the same manner as at the preceding process step, tungsten 24 is buried into the via hole 18 by the buried CVD process. Then, aluminum is vacuum-deposited on the tungsten buried by sputtering and the insulating film 17 to apply patterning thereto so as to take a desired form by making use of a photomask to form an aluminum wiring 19 of the second layer. Finally, a Si 3 N 4 film 20 serving as a surface protective layer is deposited by the low pressure CVD process at a temperature of about 400°C (FIG. 7C). The right side surface A in this figure represents one side of the semiconductor chip of this embodiment quarried by dicing the semiconductor wafer. The groove structure 15 is formed in the non-device region between that side and bonding pads (not shown) provided inside that side. Moisture is immersed from the side surface A into the chip through the interface between the PCVD SiO 2 film and the BPSG/CVD SiO 2 film, but such an immersion is prevented by the groove structure 15. As a result, corrosion of metal is conducted only here, but corrosion of metal, etc. in the device region therein does not occur. Further, the presence of tungsten 22 within the groove structure 15 is advantageous to planarization of the PCVD SiO 2 film thereon. A fifth embodiment directed to arrangement on the semiconductor chip of the groove structure of this invention will now be described with reference to FIGS. 8 to 10. In the case shown in FIG. 8, a plurality of bonding pads 52 and a functional region 53 where transistors, capacitors and the like are formed are formed on a semiconductor chip 51. The length of one side of the bonding pad is approximately 100 µm. The semiconductor chip 51 is quarried from this wafer by dicing of the semiconductor wafer on which a plurality of device regions are formed. A groove structure 15 is formed substantially in parallel with an arbitrary side 54 in the non-device region between a line 55 connecting portions closest to an arbitrary side 54 of the semiconductor chip 51 of these respective bonding pads 52 and that side 54. FIG. 9 is a plan view showing the entirety of the semiconductor chip 51 shown in FIG. 8. In this example, the groove structure 15 is in the form of a continuous square frame. More particularly, that structure 15 is formed so as to completely encompass bonding pads 52 and respective functional regions on the semiconductor chip 51. In the example shown in FIG. 9, there are several separate functional regions. They are logic, memory, and CPU, etc. These components are systematically coupled to constitute a single semiconductor device. In this embodiment, the semiconductor device is a microcontroller. In the case of mounting the microcontroller on the semiconductor chip 51, there is no portion to which attention should be particularly drawn, but attention should be overall drawn to prevention of corrosion. Therefore, the groove structure 15 takes a form of square frame along respective sides of the semiconductor chip. However, it is not limited that such a groove is a groove along the entire periphery of the chip as shown. For example, as shown in FIG. 10, in order to protect, from immersion of moisture, a projected region 531 of functional region 53 particularly close to side 54 of semiconductor chip 51, a groove structure 15 may be provided only along the peripheral portion of the functional region 53. In the projected region 531, in the same manner as in other functional regions, elements such as transistor, capacitors, or the like, and wirings are formed. In the case where these components are projected to the portion in the vicinity of the region where bonding pads 52 are formed, it is required to form a groove structure as described above in the vicinity of the projected region even if there is no necessity of protecting bonding pads. The bonding pads and the functional regions are connected by means of wirings 57. While the groove structure 15 is locally provided in the example shown in FIG. 10, a plurality of such groove structures 15 are provided in the example shown in FIG. 11. Also in this example, groove structures 15 are provided at portions 531 where respective functional regions 53 are close to the sides 54 of the semiconductor chip 51. It is to be noted that the groove structure may be provided at the periphery of the region where the bonding pad is closer to the side of the chip, or at the periphery of the region where the wiring is closer to the side of the chip. Further, ordinary bonding pads are formed substantially equidistantly along the sides of the semiconductor chip. However, since there are instances where some custom products are arranged partially at a high integration, if groove structures as mentioned above are preponderantly arranged also at portions arranged at high integration, the advantage similar to the above can be sufficiently provided. Particularly, since protection of corrosion against the aluminum wiring of the first layer must be sufficiently carried out, it is required to draw more careful attention thereto as compared to protection of corrosion against metal such as other wirings. Further, as shown in FIG. 12, the groove structure 15 is not necessarily required to be completely in parallel with the side 54 of the semiconductor chip 51 as formed at the lower part of this figure. Further, in place of the groove structure in the form of slit, such a groove structure to extend to the full width of the non-device region may be employed. If there is a room therefor, the dimension of the groove structure may be further increased. From a practical point of view, if the upper limit is about 30 µm, and the lower limit is about 2 µm, sufficient advantages can be provided. It is of course that even if the dimension of the groove structure exceed that range, the ability of preventing immersion of moisture can be sufficiently exhibited. A sixth embodiment will now be described with reference to FIG. 13. This figure is a partial plan view of a semiconductor wafer before dicing. As shown in this figure, chips 51 formed along dicing lines 60 are comprised of device regions 58 and non-device regions 59 outside those regions 58. A groove region in the form of frame is formed in each non-device region 59. Since the semiconductor wafer is cut along the dicing lines 60 between respective groove structures, those groove structures 15 can be utilized as a dicing mark. An example of a device utilizing a metal film as a means for preventing immersion of moisture will now be described with reference to FIGS. 14 and 14B. A BPSG/CVD SiO 2 film 13 serving as an interlayer insulating film is formed on a field oxide film 11 and a polysilicon electrode 12 formed on a silicon semiconductor substrate 10 thereafter to etch the insulating film 13, thus to form a contact hole 14 on the polysilicon electrode 12. This process step is the same as that shown in FIG. 4A. Then, aluminum is vacuum-deposited by sputtering on the insulating film 13 to apply patterning thereto so as to take a desired form by making use of a photomask (not shown) to form an aluminum wiring 16 of the first layer to connect it to the polysilicon electrode 12. At this time, an aluminum metal film 25 is formed annular on the insulating film 13 along the side of the semiconductor chip by making use of this patterning (FIG. 14A). The right side surface A in the figure represents that side. Then, a PCVD SiO 2 film 17 serving as an interlayer insulating film is formed to etch this film to form a via hole 18 on the aluminum wiring 16. Thereafter, an aluminum wiring 19 of the second layer is formed on the PCVD SiO 2 film 17 to connect it to the aluminum wiring of the first layer. Then, a Si 3 N 4 film 20 serving as a surface protective layer is formed to coat the aluminum wiring 19 (FIG. 14B). As shown, the metal film 25 is formed in the non-device region between one side of the semiconductor chip and bonding pads (not shown) in the semiconductor substrate. Thus, moisture immersed from the semiconductor chip side surface A is prevented by the metal film 25. Thus, corrosion is conducted only here, resulting in no possibility that metal in the internal device region is corroded. The result of the reliability test of this invention using a test chip is shown below. The PCT experiment of a chip having an area of 8.1 mm was conducted under the condition of RH of 100% and temperature of 127°C. As a result, chips according to the first to third embodiments were not all damaged until 160 hours. On the contrary, even 11 of 40 conventional chips provided with no means for preventing immersion of moisture were broken before 160 hours. While the silicon semiconductor has been mainly described in the embodiments of this invention, semiconductors used in the invention are not limited to such a silicon semiconductor. Namely, this invention can be all applied to existing materials, e.g., Ge, GaAs, or InP, etc. Further, as a matter of course, this invention can be applied to three-dimensional structure or SOS structure. While this invention can be applied to all semiconductor devices, this invention becomes more advantageous to semiconductor devices integrated to a higher degree, e.g., LSI and VLSI, etc. In addition, the microcontroller shown in FIG. 9 is only one example, and therefore this invention can be widely applied to memories such as RAM and ROM, etc., microprocessors, gate arrays, and the like. As described above, in accordance with this invention, there is provided a groove structure formed in the non-device region along the outer peripheral portion in correspondence with the contact hole formation process step. Accordingly, the connecting portion of two insulating films of poor adhesion is cut off, and two insulating films of good adhesion are connected at the portion of the groove structure. As a result, moisture immersed from the side surface of the semiconductor chip is prevented from being immersed into the chip. Thus, corrosion in the device region is sufficiently prevented.

Claims: A semiconductor device having a moisture barrier comprising: a semiconductor substrate; a plurality of bonding pads arranged on a major surface of said semiconductor substrate along at least one side edge of said semiconductor substrate; an insulating film provided on said major surface between said side edge of said semiconductor substrate and the bonding pads provided along said side edge, and comprised of at least a first insulating, layer, and a second insulating layer provided on said first insulating layer, characterized in that said semiconductor device comprises means for preventing incursion of moisture, said preventing means being a groove structure formed in said insulating film, said groove extending at least through the second insulating, layer such that at least a portion of said first insulating layer remains between the bottom of said groove structure and said semiconductor substrate. A semiconductor device as set forth in claim 1, wherein said groove structure has a width of 2 to 30 µm. A semiconductor device as set forth in claim 1, wherein at least one metal selected from a group of W, Cu and Al is buried in said groove structure. A semiconductor device having a moisture barrier as set forth in claim 1, wherein groove structures are provided parallel to respective side edges of said semiconductor substrate, said groove structures provided at neighboring sides of said substrate being connected to each other. A semiconductor device as set forth in claim 1, wherein said groove structure is formed only on a region of said substrate where the bonding pads thereat are arranged at a density higher than that at other regions. A semiconductor device having a moisture barrier as set forth in claim 1, wherein said groove structure is provided along a peripheral portion of a functional region including circuit elements formed at a central portion thereof and wirings, said functional region extending between neighboring bonding pads. A semiconductor device having a moisture barrier as set forth in claim 1, wherein said insulating film includes at least two layers having poor adhesion with each other, said groove structure being formed so as to block the connection portion of said two layers. A semiconductor device having a moisture barrier as set forth in claim 1, wherein said plurality of bonding pads are arranged on a device region of the semiconductor substrate; and wherein said means for preventing intrusion of moisture prevents moisture into the device region. A semiconductor device having a moisture barrier as set forth in claim 1, wherein said insulating film is comprised of a field oxide film formed on the surface of said semiconductor substrate, a BPSG/SiO 2 film formed on said field oxide film and serving as a first interlayer insulating film, a SiO 2 film formed on said BPSG/SiO 2 film and serving as a second interlayer insulating film, and a Si 3 N 4 film serving as a surface protective film formed thereon, said groove structure being formed in said BPSG/SiO 2 film and said field oxide film so as to cut off the connection between said first and second interlayer insulating films at the bottom portion of said groove structure. A method of manufacturing a semiconductor device comprising the steps of: forming an insulating film comprising at least a first insulating, layer and a second insulating layer formed on said first insulating layer on a major surface of a, semiconductor wafer; forming a plurality of bonding pads arranged along dicing lines of said semiconductor wafer; and forming a contact hole or a via hole in said insulating film, and forming a groove structure at the same time so that said groove structure is arranged between said dicing lines and said plurality of bonding pads, and that said groove extends at least through the second insulating, layer of said insulating film such that at least a portion of said first insulating film remains between the bottom of said groove structure and said semiconductor wafer. The method of manufacturing a semiconductor device as set forth in claim 10, further comprising the step of cutting said semiconductor wafer along said dicing lines using said groove structure as a dicing mark to form a plurality of semiconductor chips. The method of manufacturing a semiconductor device as set forth in claim 10, wherein said step of forming an insulating film includes substeps of: forming a field oxide film on the surface of said semiconductor substrate, forming a BPSG/first SiO 2 film which serves as a first interlayer insulating film on said field oxide film, said first SiO 2 film being deposited by a CVD method, forming a second SiO 2 film which serves as a second interlayer insulating film on said BPSG/first SiO 2 film, said second SiO 2 film being deposited by a plasma CVD method, and forming a Si 3 N 4 film which serves as a surface protective film on said second SiO 2 film, and wherein said groove structure is formed in said BPSG/first SiO 2 film and said field oxide film so as to cut off the connection between said first and second interlayer insulating films at the bottom portion of said groove structure.

Inventors: SHIBAHARA SATOSHI, SHIRAI KENICHI, SHIBAHARA, SATOSHI, SHIRAI, KENICHI
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1991
Main classification: H01L23
IPC codes: H01L21, H01L23