Clocked driver circuit

Abstract: A clocked driver circuit includes a first gate circuit (1), a second gate circuit (3), a first time constant circuit (5, 8), a second time constant circuit, (6, 7) a first switching circuit (10), and a second switching circuit (9). The first gate circuit has one input terminal connected to a first input terminal. The second gate circuit has one input terminal connected to a second input terminal. The first time constant circuit is connected between the output terminal of the first gate circuit and the other input terminal of the second gate circuit. The second time constant circuit is connected between the output terminal of the second gate circuit and the other input terminal of the first gate circuit. The first switching circuit controls the time constant of the first time constant circuit in accordance with an output from the first gate circuit. The second switching circuit controls the time constant circuit in accordance with an output from the second gate circuit.

Description: The present invention relates to a semiconductor integrated circuit constituted by MOSFETs and, more particularly, to a clocked driver circuit. Fig. 4 shows a conventional clocked driver circuit similar to that disclosed in IBM Technical Disclosure Bulletin, Vol. 30, No. 8, January 1988, p.420-423. This circuit comprises a first NAND circuit 1 having first and second input terminals respectively connected to an input terminal 1 ○ and a node 5 ○ and having an output terminal connected to a node 3 ○, a first inverter 2 having input and output terminals respectively connected to the node 3 ○ and an output terminal 7 ○, a second NAND circuit 3 having first and second input terminals respectively connected to a node 6 ○ and an input terminal 2 ○ and having an output terminal connected to a node 4 ○, a second inverter 4 having input and output terminals respectively connected to the node 4 ○ and an output terminal 8 ○, a first resistive element 5 connected between the nodes 3 ○ and 6 ○, a second resistive element 6 connected between the nodes 5 ○ and 4 ○, a first capacitive element 7 connected between the node 5 ○ and the ground potential, and a second capacitive element 8 connected between the node 6 ○ and the ground potential. Fig. 5 shows an operation of the circuit in Fig. 4. Complementary signals indicated by 1 ○ and 2 ○ in Fig. 5 are input to the first and second input terminals. Assume that in an initial state, the signal 1 ○ is at low level; the signal 2 ○, high level; a signal 3 ○, high level; a signal 4 ○, low level; a signal 5 ○, low level; a signal 6 ○, high level; a signal 7 ○, low level; and a signal 8 ○, high level. When the signal 2 ○ as the second input is changed from high level to low level (at the same time, the signal 1 ○ as the first input is changed from low level to high level), the signal 4 ○ is changed from low level to high level, and the signal 5 ○ is changed from low level to high level by an RC time constant. When the signal 5 ○ exceeds the threshold value of the NAND circuit 1, the signal 3 ○ is changed from high level to low level, and the signal 6 ○ is changed from high level to low level by the RC time constant. When the signal 1 ○ as the first input is changed from high level to low level (at the same time, the signal 2 ○ as the second input is changed from low level to high level), the signal 3 ○ is changed from low level to high level, and the signal 6 ○ is changed from low level to high level by the RC time constant. When the signal 6 ○ exceeds the threshold value of the NAND circuit 3, the signal 4 ○ is changed from high level to low level, and the signal 5 ○ is changed from high level to low level by the RC time constant. The above operation is repeated to obtain the signals 7 ○ and 8 ○ in Fig. 5 as output signals, which are the inverted signals of the signals 3 ○ and 4 ○. A characteristic feature of the circuit is that when a single-phase signal having a frequency f is input, two-phase signals can be obtained as output signals which have the frequency f and do not overlap each other at high level, by changing the duty. In the conventional clocked driver circuit, in order to prolong an interval in which both the first and second output signals are at low level, changes in potential of the signals 5 ○ and 6 ○ are delayed by increasing the values of the resistive elements 5 and 6 or the capacitive elements 7 and 8 to increase the RC time constant. If, however, this RC time constant is excessively increased, the potentials of the signals 5 ○ and 6 ○ are not fully amplified between the power source potential and the ground potential, as shown in Fig. 6. As a result, the timings of output signals from the clocked driver circuit are undesirably changed because of fluctuations of characteristics of the resistive elements, the capacitive elements, and the MOSFETs, or noise. It is an object of the present invention to provide a clocked driver circuit in which an interval in which both first and second outputs are at low level can be prolonged by increasing an RC time constant. It is another object of the present invention to provide a clocked driver circuit which can be stably operated by preventing changes in timings of output signals due to fluctuations of characteristics of each element with an increase in RC time constant. In order to achieve the above objects, according to the present invention there is provided a clocked driver circuit comprising: a first gate circuit having one input terminal connected to a first input terminal; a second gate circuit having one input terminal connected to a second input terminal; a first time constant circuit connected between an output terminal of said first gate circuit and the other input terminal of said second gate circuit; a second time constant circuit connected between an output terminal of said second gate circuit and the other input terminal of said first gate circuit; characterised in that said clocked driver circuit further comprises a first switching circuit for controlling a time constant of said first time constant circuit in accordance with an output from said first gate circuit; and a second switching circuit for controlling a time constant of said second time constant circuit in accordance with an output from said second gate circuit, said first and second switching circuits when operative controlling the time constants of said first and second time constant circuits to increase the rate of change of potential of the other input terminal of each of said second and first gate circuits compared to the rate of change when the switching circuits are inoperative. The present invention will now be described by way of example, with reference to the accompanying drawings, in which Fig. 1 is a circuit diagram showing the first embodiment of the present invention; Fig. 2 is a timing chart showing the waveforms of signals at the respective portions in the circuit shown in Fig. 1; Fig. 3 is a circuit diagram showing the second embodiment of the present invention; Fig. 4 is a circuit diagram showing a conventional circuit; Fig. 5 is a timing chart showing the waveforms of signals at the respective portions in the circuit shown in Fig. 4; and Fig. 6 is a timing chart for explaining problems in an operation of the conventional circuit. Fig. 1 shows a circuit according to the first embodiment of the present invention. This circuit comprises a first NAND circuit 1 having first and second input terminals respectively connected to an input terminal 1 ○ and a node 5 ○ and having an output terminal connected to a node 3 ○, a first inverter 2 having input and output terminals respectively connected to the node 3 ○ and an output terminal 7 ○, a second NAND circuit 1 having first and second input terminals respectively connected to a node 6 ○ and an input terminal 2 ○ and having an output terminal connected to a node 4 ○, a second inverter 4 having input and output terminals respectively connected to the node 4 ○ and an output terminal 8 ○, a first resistive element 5 connected between the nodes 3 ○ and 6 ○, a second resistive element 6 connected between the nodes 5 ○ and 4 ○, a first capacitive element 7 connected between the node 5 ○ and the ground potential, a second capacitive element 8 connected between the node 6 ○ and the ground potential, a first depletion NchMOSFET 9 having a source, a gate, and a drain respectively connected to the ground potential, the node 8 ○, and the node 5 ○, and a second depletion NchMOSFET 10 having a source, a gate, and a drain respectively connected to the ground potential, the node 7 ○, and the node 6 ○. Fig. 2 shows an operation of the circuit. When complementary signals indicated by 1 ○ and 2 ○ in Fig. 2 are input to the first and second input terminals, the potentials of the respective points are set as indicated by 3 ○ to 6 ○ in Fig. 2, and signals having waveforms indicated by 7 ○ and 8 ○ in Fig. 2 are output from the first and second output terminals. In the clocked driver circuit of the present invention, when the potential of the signal 5 ○ is changed from high level to low level, the NchMOSFET 9 is turned on so that the change in potential is caused faster than that caused by the conventional RC time constant. Similarly, when the potential of the signal 6 ○ is changed from high level to low level, the NchMOSFET 10 is turned on so that the change in potential is caused faster than that caused by the conventional RC time constant. With this operation, the potentials of the signals 5 ○ and 6 ○ are necessarily changed from the ground potential. Hence, the circuit can be stably operated even if the RC time constant is increased to prolong an interval in which both the first and second outputs are at low level as compared with the conventional circuit. Fig. 3 shows a circuit according to the second embodiment of the present invention. In this circuit, the first and second resistive elements 5 and 6 in the first embodiment are respectively replaced with third and fourth depletion NchMOSFETs 11 and 12. The source, gate, and drain of the third depletion NchMOSFET 11 are respectively connected to a node 6 ○, power source potential V DD , and a node 3 ○. The source, gate, and drain of the fourth depletion NchMOSFET 12 are respectively connected to a node 5 ○, power source potential V DD , and a node 4 ○. Third and fourth inverters 132 and 14 are inserted between the second input of a first NAND circuit 1 and the node 5 ○. The input and output terminals of the third inverter 13 are respectively connected to the node 5 ○ and a node 11. The input and output terminals of the fourth inverter 14 are respectively connected to the node 11 and a second input terminal 13 of the first NAND circuit 1. In addition, fifth and sixth inverters 15 and 16 are inserted between the first input terminal of a second NAND circuit 3 and a node 6 ○. The input and output terminals of the fifth inverter 15 are respectively connected to the node 6 ○ and a node 12. The input and output terminals of the sixth inverter 16 are respectively connected to the node 12 and a first input terminal 14 of the second NAND circuit 3. Furthermore, the gate of the first NchMOSFET is connected to a node 10 at which an output signal is delayed most by a parasitic resistor 19 and a parasitic capacitor 20 on wiring through which output signals from the second inverter 4 are transmitted. The gate of the second NchMOSFET is connected to a node 9 ○ at which an output signal is delayed most by a parasitic resistor 17 and a parasitic capacitor 18 on wiring through which output signals from the first inverter 2 are transmitted. In the above embodiment, since the resistive elements are replaced with the Nch depletion transistors, the layout area for resistors can be reduced to 1/3 to 1/4 that in the first embodiment, while the same effect as that in the first embodiment can be obtained. In addition, the third to sixth inverters 13 to 16 are inserted, and the logic threshold values of the third and fifth inverters are changed so that the delay time can be changed without influencing other logic threshold values, while the same effect as that in the first embodiment can be obtained. Since the gates of the first and second NchMOSFETs 9 and 10 are respectively connected to the nodes and 9 ○, the following effect can be obtained in addition to the same effect as that in the first embodiment. Even if the waveforms of the output signals 7 ○ and 8 ○ from the clocked driver circuit are distorted due to the parasitic resistance and capacitance, since the NchMOSFET is not turned off unless one of the signals goes to low level, the other signal is not set at high level. Moreover, the same effect as that of the above-described circuit can be obtained even if the third and fourth depletion NchMOSFETs 11 and 12 are respectively replaced with a first depletion PchMOSFET whose source, gate, and drain are respectively connected to the node 6 ○, the ground potential, and the node 3 ○, and a second depletion PchMOSFET whose source, gate, and drain are respectively connected to the node 5 ○, the ground potential, and the node 4 ○. According to the present invention described above, NchMOSFETs are connected in parallel with capacitive elements, and each NchMOSFET is turned on when the potential of one of the terminals of a corresponding capacitive element which is not connected to the ground potential is changed from high level to low level. With this operation, the clocked driver circuit can be stably operated, and an interval in which the first and second outputs are at low level can be prolonged by increasing the RC time constant.

Claims: A clocked driver circuit comprising: a first gate circuit (1) ) having one input terminal connected to a first input terminal; a second gate circuit (3) having one input terminal connected to a second input terminal; a first time constant circuit (5,8) connected between an output terminal of said first gate circuit (1) and the other input terminal of said second gate circuit (3); a second time constant circuit (6,7) connected between an output terminal of said second gate circuit (3) and the other input terminal of said first gate circuit (1); characterised in that said clocked driver circuit further comprises a first switching circuit (10) for controlling a time constant of said first time constant circuit (5,8) in accordance with an output from said first gate circuit (1); and a second switching circuit (9) for controlling a time constant of said second time constant circuit (6,7) in accordance with an output from said second gate circuit (3); said first and second switching circuits when operative controlling the time constants of said first and second time constant circuits to increase the rate of change of potential of the other input terminal of each of said second and first gate circuits compared to the rate of change when the switching circuits are inoperative. A circuit according to Claim 1, wherein said first and second time constant circuit (5,8;6,7) are respectively controlled by inverted outputs of the outputs from said first and second gate circuits (1, 3). A circuit according to claim 1 or claim 2, wherein said first and second switching circuits (10, 9) control the time constants of said first and second time constant circuits (5, 8; 6, 7) so as to more quickly change a potential of the other input terminal of each of said second and first gate circuits (3, 1) from high level to low level. A circuit according to any of claims 1 to 3, wherein said first switching circuit (10) is a first MOSFET whose source, gate, and drain are respectively connected to a first potential, the output terminal of said first gate circuit (1), and the other input terminal of said second gate circuit (3), and said second switching circuit (9) is a second MOSFET whose source, gate, and drain are respectively connected to the first potential, the output terminal of said second gate circuit (3), and the other input terminal of said first gate circuit (1). A circuit according to claim 4, wherein said first and second MOSFETs are depletion N-channel MOSFETS. A circuit according to any preceding claim, wherein each of said first and second time constant circuits (5, 8; 6, 7) is a RC time constant circuit constituted by a resistor arid a capacitor. A circuit according to claim 6, wherein the resistor of said first time constant circuit (5, 8) is replaced with a third MOSFET (12) whose source, gate, and drain are respectively connected to the output terminal of said first gate circuit (1), a second voltage (V DD ), and the other input terminal of said second gate circuit (3), and the resistor of said second time constant circuit is replaced with a fourth MOSFET (11) whose source, gate, and drain are respectively connected to the output terminal of said second gate circuit (3), the second voltage, and the other input terminal of said first gate circuit (1). A circuit according to claim 6, wherein the resistor of said first time constant circuit (5, 8) is replaced with a fifth MOSFET whose source, gate, and drain are respectively connected to the output terminal of said first gate circuit (1), a first voltage, and the other input terminal of said second gate circuit (3), and the resistor of said second time constant circuit is replaced with a sixth MOSFET whose source, gate, and drain are respectively connected to the output terminal of said second gate circuit (3), the first voltage, and the other input terminal of said first gate circuit (1). A circuit according to any preceding claim, wherein series-connected inverters (13, 14, 15, 16) are respectively connected between the other input terminal of said first gate circuit (1) and said second time constant circuit (6, 7), and between the other input terminal of said second gate circuit (3) and the first time constant circuit (5, 8). A circuit according to any preceding claim, wherein said first and second switching circuits (10, 9) respectively have control terminals connected to nodes at which output signals are delayed most by parasitic resistances and parasitic capacitances on wiring through which outputs from said first and second gate circuits (1, 3) are transmitted. A clocked driver circuit as claimed in Claim 1, wherein said other input terminal and said output terminal of said first gate circuit (1) are respectively connected to a first node and a second node; said other input terminal and said output terminal of said second gate circuit (3) are respectively connected to a third node and a fourth node; said first time constant circuit comprises a first resistive element (5) connected between the second and third nodes, and a first capacitive element (8) connected between the third node and a first potential; said second time constant circuit comprises a second resistive element (6) connected between the first and fourth nodes, and a second capacitive element (7) connected between the first node and the first potential; said first switching circuit comprising a first MOSFET (10) having a source, a gate and a drain respectively connected to the first potential, a first output terminal of the clocked driver circuit and the third node; said second switching circuit comprising a second MOSFET (9) having a source, a gate and a drain respectively connected to the first potential, a second output terminal of the clocked driver circuit and the first node; said circuit further comprising: a first inverter (2) having input and output terminals respectively connected to the second node and said first output terminal; and a second inverter (4) having input and output terminals respectively connected to the fourth node and said second output terminal.

Inventors: NARAHARA TETSUYA, NARAHARA, TETSUYA, NARAHARA, TETSUYA, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: H03K5
IPC codes: H03K5, H03K3, H01L29