Circuit for detecting false read data from eprom

Abstract: First (30) and second (31) EPROM transistors are coupled in series to a power source (VDD), a third EPROM transistor (32) is connected in parallel with the series connection and a two input NAND gate (33) has a first input connected to the junction between the first (30) and second (31) EPROM transistors by an inverter (39) and a second input connected to the drain of the third transistor (32). The first (30) and third (32) transistors are programmed with the EPROM and the second transistor (31) is not. When a read signal is applied to the gates of all three transistors (30, 31, 32) a predetermined signal will be available at the output of the NAND gate (33) if the EPROM read condition is not faulty

Description: The present invention pertains to circuitry for detecting false read data. The invention is particularly but not exclusively applicable to circuitry for detecting changes in EPROM data due to voltage changes in the power supply and some security breaches. Background of the Invention In general, erasable programmable read only memories (EPROMs) include arrays of special transistors, such as floating gate field effect transistors, MOS ROMs, etc., (hereinafter referred to as EPROM transistors) that can be programmed for usual memory purposes. Programming an EPROM transistor consists of storing an electrical charge at the gate of the EPROM transistor being programmed so that the EPROM transistor can not be turned on. As is well known in the art, the transistors in a memory array operate like switches with some being turned off and some being turned on to provide the predetermined output data. The programmed EPROM transistors in an EPROM are the "off" switches in this arrangement. EPROM transistors are designed so that under normal conditions the programming, or the charge stored at the gate, will last for years. However, The programming must take place under prescribed voltage conditions and read lines, etc. must not exceed a prescribed voltage by too much. Sometimes excessive reading of the memory, fluctuating voltages, excessive voltage on the read line, etc. can drain the stored charge at the gates of EPROM transistors in the memory array and cause the data to become erroneous. Conversely, excessive current flow in EPROM transistors can cause them to become falsely programmed. It is essential that false or erroneous data be detected as early as possible. EP-A-0 251 429 discloses a non-volatile memory with a dummy cell. A test signal can be applied to the dummy cell in order to find the data-holding characteristics of the memory cells. During the test, a current equal to the normal data-writing current flows through the dummy cell. As a result, a potential equal to the normal data-writing potential is applied to each of the cells. By comparing the threshold of the programmed cells before and during application of this normal data-writing potential, it can be seen if the cells are in good condition. Summary of the Invention The present invention seeks to provide a new and improved circuit for detecting false read data in an EPROM. According to one aspect of the invention there is provided a circuit for detecting false read data in an EPROM, said circuit comprising first and second transistors each having a drain adapted to be coupled to a first terminal (VDD) of a power supply and a source adapted to be coupled to a second terminal of the power supply; and logic means coupled to the drains of said first and second transistors for providing a predetermined output signal indicative of false read data, in response to a test signal being applied to gates of said first and second transistors, and said second transistor not being properly programmed. According to a second aspect of the invention there is provided a circuit for detecting false read data in an EPROM, said circuit comprising at least first, second and third transistors with the first and second transistors being coupled in series between a voltage supply (VDD) and a reference point and the third transistor being coupled in parallel with the series connected first and second transistors and logic means coupled to the drains of the first and third transistors for providing a predetermined output signal indicative of false read data, in response to a read signal being applied to the gates of all three transistors, and said second and third transistors not being properly programmed. Brief Description of the Drawings Referring to the drawings: FIG.1 is a schematic diagram of one embodiment of a circuit for detecting a false read data in an EPROM in accordance with the present invention; and FIG.2 is a schematic diagram of an alternative embodiment of a circuit for detecting false read data in an EPROM in accordance with the present invention. Description of the Preferred Embodiments EPROMs are generally made up of a large number of EPROM transistors positioned in a memory array and some additional transistors utilized as sense amplifiers and the like for reading information stored in the memory. For example, an 8k EPROM has approximately 8192 transistors formed on the single chip. The present invention calls for the addition of two or three EPROM transistors and one or more logic elements to the chip for providing a circuit which detects false read data from the EPROM. FIG.1 illustrates a circuit 10 for detecting false read data from an EPROM, which circuit 10 embodies the present invention. Circuit 10 includes first and second EPROM transistors 11 and 12, respectively. Transistors 11 and 12 each have source electrodes connected to a reference potential, which in this embodiment is ground, and drain electrodes connected to a power supply V dd . The gate electrodes of transistors 11 and 12 are connected to a test signal input terminal 15. A two input NAND gate 17 has a first input coupled through an inverter 18 to the drain electrode of first transistor 11 (point A). A second input of NAND gate 17 is connected to the drain electrode of second transistor 12 (point B). As is well known to those skilled in the art, NAND gate 17 and inverter 18 may be considered a single logic element or as many as three (inverter, AND gate, inverter). The output 20 of NAND gate 17 is the test output for circuit 10. In the operation of circuit 10, transistors 11 and 12 are included on the same chip as the EPROM. It is more practical to include NAND gate 17 and inverter 18 on the same chip also, but it will be recognized that in some instances it may be desirable to locate these components off the chip. When the EPROM is programmed with the desired data, transistor 12 is also programmed to be in the nonconduction state. Whenever the data in the EPROM is to be used, a one or positive signal is first applied to test input terminal 15. The one on input terminal 15 causes transistor 11 to conduct, which causes the reference potential (ground in this embodiment) to be applied to inverter 18. This is equivalent to a zero at point A. Thus a one or positive signal is supplied to the first input of NAND gate 17. Also, a one or positive signal applied to the gate electrode of transistor 12 results in a positive signal being applied to the second input of NAND gate 17. Assuming that transistor 12 is properly programmed in the nonconduction state, the one or positive signal applied to the gate electrode of transistor 12 has no effect and the logic level at point B remains a one. Thus the test output on terminal 20 is a zero or low signal. Since transistor 12 was programmed with the EPROM, if the reading of circuit 10 is correct the read data (program) from the entire EPROM is normally correct. If the read data of transistor 12 is incorrect, the positive test signals applied to the gate electrode thereof will cause it to conduct and a one or positive signal will appear at output terminal 20, indicating a failure. The truth table for circuit 10 appears below: A B OUT X 0 0 1 Correct 0 1 0 X 1 0 1 X 1 1 1 One difficulty with circuit 10 is the fact that a continuous positive signal applied to input terminal 15 and the continuous current through transistor 11 resulting therefrom, will eventually cause transistor 11 to change from a zero (unprogrammed) to a 1 (programmed), which is referred to in the art as soft programming. That is, it will operate the same as transistor 12 and, thus, produce a failure in testing circuit 10, resulting in an apparent failure in the programmed state of the EPROM. Thus, only short test pulses can be applied to circuit 10 for testing the programmed state of (reading) an associated EPROM. Referring specifically to FIG.2, a second but preferred circuit 25 for detecting false read data from an EPROM, embodying the present invention, is disclosed. In circuit 25, two programmed EPROM transistors 31 and 32 are utilized along with a test device, which in this embodiment is a non-programmed EPROM transistor 30. Transistors 30 and 31 are coupled in series between the power source terminal and ground and transistor 32 is coupled in parallel with transistors 30 and 31. A logic element, including a NAND gate 33 and an inverter 39, is connected to the drains of transistors 30 and 32. The drain of transistor 30 is coupled to a first input of NAND gate 33 through inverter 39 and the drain of transistor 32 is connected to a second input of NAND gate 33. Transistors 31 and 32 are both programmed with the associated EPROM. Transistor 30 is illustrated as an EPROM transistor but it is unprogrammed and could be a different type of transistor, if such an arrangement is more convenient. It should be noted, however, that making transistor 30 an EPROM transistor provides the capability of preventing and detecting 0 to 1 changes. In operation, a positive test signal is supplied to a test input terminal 35, which is connected to the gates of transistors 30 through 32. The positive test signal has no effect on programmed transistors 31 and 32 but unprogrammed transistor 30 is turned on. Thus, a low or zero logic signal is supplied to inverter 39 which supplies a positive or logic one signal to the first input of NAND gate 33. At the same time transistor 32 remains off so that a positive or logic one signal is supplied to the second input of NAND gate 33. Thus, the logic circuit monitors transistors 30 through 32 and supplies a predetermined output signal at output terminal 40 if transistors 31 and 32 are properly programmed. The major advantage of circuit 25 is the fact that a continuous test signal can be applied to the test input terminal and the unprogrammed state of EPROM transistors 30 will not be effected. By placing a second programmed transistor (EPROM transistor 31) in the circuit, current flow in circuit 25 is virtually reduced to zero. Thus, circuit 25 is included on a semiconductor chip with an EPROM and a continuous test signal, for example V dd , is applied to the test input terminal. The test output is monitored by some selected instrument so that an alarm signal is produced whenever the output changes from zero to one. Since virtually no current flows in circuit 25 it will consume virtually no power. It should be noted that circuits 10 and 25 can also be used as security checking circuits. If a third party attempts to read the EPROM without knowing the exact pin usage, or without knowing that circuit 10 is a test circuit, or without having the correct read voltage, the programming of the EPROM transistors could be temporarily over-ridden to cause an apparent failure of the test circuit. Because of the apparent failure, the output of the test circuit becomes a one, or high. Since circuit 25 is connected to voltage supply Vdd of the EPROM, for example, if too high a voltage supply is connected to the EPROM programmed transistors 31 and 32 will become conductive (turn on in spite of the programming) and indicate a security breach. Since the change of state of the test circuit output indicates a failure of the EPROM programming, or in the above case a breach of security, read data from the EPROM is inhibited or otherwise not provided. Thus, a breach of security is prevented. Many other security applications will be found for the circuits embodying the present invention. It will of course be understood by those skilled in the art that additional and/or different logic elements can be utilized to get additional and/or different predetermined output signals from the detecting circuit. Also, the present embodiments utilize all EPROM transistors for the error detecting circuit but it will be understood by those skilled in the art that at least the non-programmed transistors could be a different type of transistor if the different type is easier to manufacture or otherwise incorporate. Thus, a circuit for detecting false read data from an EPROM is disclosed, which circuit is simple and inexpensive to incorporate into the EPROM during manufacture. Further, the detecting circuit makes a test of data stored in the EPROM simple and quick with virtually no lost time in setting up the test, since the EPROM transistors included in the detecting circuit are programmed at the same time as the EPROM is programmed. Also, an embodiment of the present invention can be used to continuously test EPROM programming without interrupting the EPROM operation or utilizing any substantial amount of power. As an additional feature, the detecting circuit can be used to detect security breaches under certain conditions.

Claims: A circuit (10) for detecting false read data in an EPROM, said circuit comprising first (11) and second (12) transistors each having a drain adapted to be coupled to a first terminal (VDD) of a power supply and a source adapted to be coupled to a second terminal of the power supply; and logic means (17, 18) coupled to the drains of said first and second transistors for providing a predetermined output signal indicative of false read data, in response to a test signal being applied to gates of said first (11) and second (12) transistors, and said second transistor not being properly programmed. The circuit of claim 1 wherein at least one of the transistors is an EPROM transistor. A circuit (25) for detecting false read data in an EPROM, said circuit comprising at least first (30), second (31) and third (32) transistors with the first (30) and second (31) transistors being coupled in series between a voltage supply (VDD) and a reference point and the third transistor (32) being coupled in parallel with the series connected first and second transistors and logic means (33, 39) coupled to the drains of the first (30) and third (32) transistors for providing a predetermined output signal indicative of false read data, in response to a read signal being applied to the gates of all three transistors (30, 31, 32), and said second and third transistors not being properly programmed. A circuit (25) as claimed in claim 3 wherein at least two of the three transistors (30, 31, 32) are EPROM transistors located in the EPROM in which false data is to be detected and programmed therewith.

Inventors: KOSUGE MASAHIRO, USAMI TADASHI, KOSUGE, MASAHIRO, USAMI, TADASHI
Applicants: MOTOROLA JAPAN, NIPPON MOTOROLA LTD.
Application year: 1991
Main classification: G11C29
IPC codes: G11C29, G11C17