Liquid crystal display driver circuitry

Abstract: Display driving circuitry is employed for providing to a liquid crystal display device connected with the circuitry a drive signal of a voltage level that can be selected from among a plurality of different predetermined voltage levels by application of respective digital selection signals (D₀,..,D₃) to the circuitry. The circuitry includes a voltage source for providing a set of supply voltage signals (V₀, V₁,...V n ) of respective different predetermined magnitudes; a plurality of switching elements (10,...17), each having an input terminal connected to the said voltage source for receiving therefrom one of the said supply voltage signals (V₀,...V n ) of the said set and also having an output terminal connected to a common output node (Yn) of the circuitry at which such a display device is connected when the circuitry is in use; and voltage selection means (21, 22) for connection to receive such digital selection signals and operable in response to receipt of one such selection signal to activate a predetermined group of the said switching elements, so as to cause such drive signal, of a predetermined voltage level that is associated individually with the selected switching elements, to be produced at the said common output node of the circuitry, the activation of the said switching elements being so controlled by the voltage selection means that the number of different predetermined voltage levels in the said plurality is greater than the number of supply voltage signals in the said set. Such circuitry can provide a desirably large number of different predetermined voltage levels to permit fine gray-scale control of a liquid crystal display element, without requiring an unacceptably large chip area.

Description: The present invention relates to liquid crystal display driver circuitry for controlling and driving a plurality of liquid crystal display elements forming a display panel. In recent years, active-matrix-type liquid crystal colour displays, such as thin film transistor (TFT) liquid crystal colour display units realising an excellent image quality have been marketed. The TFT liquid crystal colour display units are expected to realize, in the future, a large display capacity, multi-colour (8/16 colours) for personal computers, and full colour for television sets. A display panel driver circuit for driving and controlling such a large scale liquid crystal colour display unit of large display capacity may employ a driver IC for an STN (super-twisted nematic) mode for the multicolour display, and an analog driver IC for the full colour display. It will be necessary to make the circuit scale of these driver ICs compact and simple to form a display panel driver circuit that is capable of displaying a high-quality image with gray-scales and colours (full colour). EP-A-0071911 discloses one example of display driving circuitry suitable for providing to a display device connected with the circuitry a drive signal of a voltage level that can be selected from among a plurality of predetermined voltage levels by application of respective digital selection signals to the circuitry, which circuitry includes: a voltage source for providing a set of supply voltage signals of respective different predetermined magnitudes; a plurality of switching elements, each having an input terminal connected to the said voltage source for receiving therefrom one of the said supply voltage signals of the said set and also having an output terminal connected to a common output node of the circuitry at which such a display device is connected when the circuitry is in use; and voltage selection means for connection to receive such digital selection signals and operable in response to receipt of each such selection signal to activate a predetermined one of the said switching elements, so as to cause such a drive signal, of a predetermined voltage level that is associated individually with the activated switching element, to be produced at the said common output node of the circuitry. In such circuitry, however, the number of different predetermined voltage levels at the output node is restricted to be equal to the number of supply voltage signals. According to the present invention the said voltage selection means are operable in response to at least one of the said selection signals to activate a predetermined group of the switching elements, such that the resulting drive signal has a predetermined voltage level that is associated individually with the group concerned and that is dependent upon a combination of the supply voltage signals received by the switching elements of that group; the activation of the said switching elements being so controlled by the voltage selection means that the number of different predetermined voltage levels in the said plurality is greater than the number of supply voltage signals in the said set. The display driving circuitry may contain an additional resistance connected in series with each of the switching elements. In display driving circuitry embodying the present invention, one or a plurality of the switching elements connected to the voltage source for receiving therefrom different supply voltage signals are selectively activated (turned ON), so that the on-state resistances of the activated switching elements divide the supply voltage signals concerned and provide a larger number of different drive signal voltage levels than the number of different supply voltage signals. This simple circuit arrangement can drive a display panel with gray-scales and can realize a larger number of output gray-scale voltages than the number of input gray-scale voltages, without unacceptable fluctuations in the output voltages. The above-mentioned additional resistances (when used) can reduce a fluctuation in the drive signal voltages even if the on-state resistances of the switching elements are not constant. In a preferred circuit embodying the present invention, a plurality of the switching elements are connected as a unit for receiving each of the different supply voltage signals. One or a plurality of the switching elements in or more units may be selectively turned ON at the same time. When two or more of the switching elements are activated as a predetermined group in this way, the on-state resistances of the activated switching elements determine the drive signal voltage level as a combination of the supply voltage signals received by the activated switching elements. As a result this embodiment can realize the same number of gray-scale levels as embodiments that have only one switching element for each supply voltage signal, but with a smaller number of supply voltage signals. Also, with the same circuit size as that of a prior art circuit, circuitry embodying the present invention can realize more gray-scales. In this way, circuitry embodying the invention can reduce a fluctuation in voltage levels and can provide a gray-scale multicolour (full colour) display control to provide high-quality images. Incidentally, JP-A-63-141414 discloses a D/A converter which receives two analog input voltages and produces four different analog output voltages in response respectively to four different applied digital selection signals. One of the four analog output voltages is dependent on one of the input voltages alone, another of the four analog output voltages is dependent upon the other of the input voltages alone, and a third output voltage is dependent upon a combination of the two input voltages. However, the fourth output voltage is zero and so is independent of both input voltages. Also, the switching elements in this D/A converter are connected in parallel to ground and when activated serve effectively to disconnect the input voltages from the output node of the converter. Reference will now be made, by way of example, to the accompanying drawings, wherein: Fig. 1 is a circuit diagram of a previously-considered analog data driver of a liquid crystal display; Fig. 2 is a graph showing an exemplary applied voltage-transmissivity characteristic of a liquid crystal display element; Fig. 3 is a block diagram of a display arrangement having a liquid crystal display panel and display panel drivers; Fig. 4 is a circuit diagram of a digital data driver circuit shown in Fig. 3; Fig. 5 is a table showing the relation between an input data, applied voltage and output voltage in the digital data driver circuit of Fig. 4; Fig. 6 is a block circuit diagram of a part of the digital data driver circuit of Fig. 4; Fig. 7 is a table for use in explaining problems of the digital data driver circuit of Fig. 4; Fig. 8A is a graph showing the input voltage dependency of an ON-state resistance value of an analog switch at different values of source voltage; Fig. 8B is a graph showing the input voltage dependency of an ON-state resistance value of an analog switch at various ambient temperatures; Fig. 9A is a block diagram of a display arrangement having a display panel and display panel drivers including digital data driver circuits embodying the present invention; Fig. 9B is a circuit diagram of a first digital data driver circuit embodying the present invention; Fig. 10A is a diagram illustrating the operation of parts of the circuit of Fig. 9B; Fig. 10B is a circuit diagram presenting an equivalent circuit to the circuitry of Fig. 10A; Fig. 11 is a table showing the relation between an input data, applied voltage and output voltage in the digital data driver circuit of Fig. 9B; Fig. 12 is a graph showing the transmissivity-voltage characteristics of a liquid crystal display element and gray-scale levels corresponding to output voltages listed in the table of Fig. 11; Fig. 13 is a circuit diagram of a second digital data driver circuit embodying the present invention; Fig. 14A is a diagram illustrating operation of parts of the circuit of Fig. 13; Fig. 14B is a circuit diagram presenting an equivalent circuit to the circuitry shown in Fig. 14A; Fig. 15 is a table showing the relation between an input data, applied voltage and output voltage in the digital data driver circuit of Fig. 13; Fig. 16 is a block circuit diagram of a part of the circuit of Fig. 13; Fig. 17 is a circuit diagram showing an example of a voltage selector circuit embodying the present invention; Fig. 18 is a block circuit diagram of parts of a third digital data driver circuit embodying the present invention; Fig. 19A to 19C are respective circuit diagrams presenting equivalent circuits for use in explaining operation of the circuit of Fig. 18; Fig. 20 is a table showing the relation between an input data, applied voltage and output voltage in the digital data driver circuit of Fig. 18; Fig. 21 is a block circuit diagram of parts of a fourth digital data driver circuit embodying the present invention; Figs. 22A and 22B are respective circuit diagrams presenting equivalent circuits for use in comparing operation of the circuit parts shown in Figs. 16 and 21; Fig. 23A is a plan view showing a first example of the construction of a resistance element in the circuit of Fig. 21; Fig. 23B is a sectional view corresponding to Fig. 23A; Fig. 23C is a schematic circuit diagram presenting an equivalent circuit to the resistance element shown in Figs. 23A and 23B; Fig. 24 is a sectional view showing a second example of the construction of the resistance element in the circuit of Fig. 21; Fig. 25 is a sectional view showing a third example of the construction of the resistance element in the circuit of Fig. 21; and Fig. 26 is a block circuit diagram of parts of a fifth digital data driver circuit embodying the present invention. Figure 1 shows a previously-considered analog data driver circuit in an analog data driver for driving a liquid crystal display panel, having an analog data input terminal Da, an ON/OFF switch SWa, a sample hold capacitor Ca, a buffer Ba, and an output terminal Yn. When a switching signal is input to the switch SWa, the switch turns ON and the analog data applied on the input terminal Da is sample held by the capacitor Ca. The held analog data is output from the output terminal Yn through the buffer Ba and the gray-scale of the liquid crystal display is determined by the level of the analog data. Usually a plurality of analog data driver circuits as shown in Fig. 1 are included in one IC chip. Such an analog data driver circuit has the following problems: Firstly, an actual number of gray-scales of the analog driver circuit is limited to about 16 because analog output voltages fluctuate between IC chips when displaying an image in full colour. Namely, as shown in Fig. 2, usually a fluctuation in the output voltages ΔV between IC chips is 200 mV, and if a voltage difference between applied voltages for white and black levels of the liquid crystal display is 3 V, the number of gray-scales is 3V/200mV = 15. In addition, the analog circuit portion occupies a large area which increases the size of each chip and the cost of ICs. With a view to overcoming the above-mentioned problems a digital data driver circuit has been considered, as explained with reference to Figs. 3, 4, 5 and 6. Figure 3 is a schematic general view showing the construction of an ordinary display panel of the TFT-type LCD (liquid crystal display) and display panel drivers including digital data drivers, Fig. 4 shows a digital driver circuit forming part of a digital data driver in Fig. 3, Fig. 5 is a table showing the relation between an input data, applied voltage and output voltage in the digital data driver circuit in Fig. 4 and Fig. 6 is a view schematically showing parts of the digital data driver circuit of Fig. 4. In Fig. 3, reference numeral 100 denotes a TFT-LCD, reference numerals 151 to 158 denote conventional digital data driver serving as a display panel driver circuit for driving a TFT-LCD 100 that is capable of displaying an image with 8 gray-scales, reference numeral 200 denotes a control circuit, reference numeral 300 denotes a CPU (Central Processing Unit), and reference numerals 401 to 403 denote scan drivers for scanning horizontal electrodes of the TFT-LCD 100. To drive the TFT-LCD 100, a data clock signal, a latch signal, etc. and three bits data signals are applied to the data drivers 151 to 158, and a scan clock signal, etc. are applied to the scan drivers 401 to 403. Further, eight levels of power source voltage V0-V7 are also applied to the data drivers 151 to 158. Fig. 4 shows a digital data driver circuit serving as a display panel driver circuit for driving a TFT-LCD 100 (Fig. 3) that is capable of displaying an image with 8 gray-scales. The circuit comprises first and second latch circuits 31 and 32 for holding a data signal of three bits D0 to D2 according to clock signals CL1 and CL2 provided by a control circuit 200; a voltage selector circuit 20 for providing, according to the data signal of three bits D0 to D2 provided by the first and second latch circuits 31 and 32, voltage selection signals S00 to S70 for selecting one of power source voltages V0 to V7; inverters 10N to 17N for inverting the voltage selection signals S00 to S70 provided by the voltage selector 2 and providing inverted selection signals *S00to *S70 (not shown); and a switching circuit 1 having a plurality of analog switches 10 to 17 each having a p-channel MOS (P-MOS) FET and an n-channel MOS (N-MOS) FET that are connected parallel to each other and one of them is driven according to the voltage selection signals S00 to S70 and inverted selection signals *S00 to *S70, for selecting one of the power source voltages V0 to V7 according to the analog switches 10 to 17, and providing the selected power source voltage through an output terminal Yn.A circuit similar to that of Fig. 4 is disclosed in EP-A-0391655 which is a document falling under EPC Article 54(3). Next, operation of the display panel drivers of FIg. 3 and the digital data driver circuit of Fig. 4 having the above-mentioned arrangement will be explained. According to instructions from a CPU 300, the control circuit 200 provides the respective data drivers 151 to 158 with a parallel data signal of three bits 000 to 111, data clock signals CL1 and CL2, latch signals, etc. and one of the scan drivers 401 to 403 with a scan signal of one horizontal line. In each of the data drivers 151 to 158, the first latch circuit 31 holds or provides the data signal of three bits 000 to 111 according to the clock signal CL1, and the second latch circuit 32 receives the provided data signal of three bits 000 to 111 and holds or provides the same according to the clock signal CL2. The data signal of three bits 000 to 111 provided by the second latch circuit 32 is received by the voltage selector circuit 20, which drives and controls the analog switches 10 to 17 of the switching circuit 1 such that one of the power source voltages V0 to V7 i selected and provided according to the characteristics of the output voltages as shown in Fig. 5. According to the ON and OFF operations of the analog switches 10 to 17, one of the power source voltages V0 to V7 is selected and provided to the TFT-LCD 100 through the output terminal Yn, thereby controlling the TFT-LCD 100 with eight gray-scales. The analog switches 10 to 17 are turned ON or OFF when one of the P-MOSFET or N-MOSFET in each of the analog switches are driven according to the voltage level of a corresponding switch of the power source voltages V0 to V7 connected and applied to the transistors. Figure 6 is a schematic view showing the digital data driver circuit explained above. Such a digital data driver circuit causes no fluctuation in output voltage, unlike the aforedescribed analog driver circuit. The digital data driver circuit, however, as shown in Fig. 7, inevitably increases the number of gates and chip area ( = input voltages and analog switches) as the number of gray-scales increases, thereby drastically increasing the size of a chip. Accordingly, the number of gray-scales is limited to about 8 with such a digital data driver circuit. Further, if a load resistance value (an ON-state resistance value) of the analog switch fluctuates, the output voltage thereof also fluctuates and incorrectly displays gray-scales. The ON-state resistance fluctuates in the same chip ( ± 10%) depending on an input voltage. Figures 8A and 8B show an example of the input voltage dependency of the ON-state resistance. Particularly, Fig. 8A is a graph showing the input voltage dependency of an ON-state resistance value of an analog switch with the parameter of source voltage V D D . and Fig. 8B is a graph showing the input voltage dependency of an ON-state resistance value of an analog switch with the parameter of ambient temperature T A . According to the analog switch shown in Figs. 8A and 8B, the ON-state resistance fluctuates in a range of 200 Ω to 300 Ω when the power source voltage is ± 2.5 V. Figure 9A is a schematic general view showing the construction of a display panel of the TFT-type LCD and display panel drivers including digital data drivers embodying the present invention, and Fig. 9B shows parts of a digital data driver according to a first embodiment of the present invention. In Fig. 9A, reference numeral 100 denotes a TFT-LCD, reference numerals 161 to 168 denote digital data drivers embodying the present invention serving as a display panel driver circuit for driving a TFT-LCD 100 that is capable of displaying an image with 16 gray-scales, reference numeral 200 denotes a control circuit, reference numeral 300 denotes a CPU, and reference numerals 401 to 403 denote scan drivers for scanning horizontal electrodes of the TFT-LCD 100. To drive the TFT-LCD 100, a data clock signal, a latch signal, etc. and four bits data signals are applied to the data drivers 161 to 168, and a scan clock signal, etc. are applied to the scan drivers 401 to 403. Further, eight levels of power source voltage V0-V7 are also commonly applied to the data drivers 161 to 168. Fig. 9B shows the digital data driver circuit of a first embodiment of the present invention serving as display panel driving circuitry for driving a TFT-LCD 100 (Fig. 9A) that is capable of displaying an image with 16 gray-scales comprising first and second latch circuits 31 and 32, inverters 10N to 17N, and a switching circuit 1. In addition, the the first embodiment includes a first voltage selector circuit 21 for receiving two data signals D0 and D1 and among data signals (selection signals) DO to D3 of four bits provided by the second latch circuit 32, and generating control signals S0 to S3 of four bits (00 to 11) to selectively turn ON one of the analog switches 10 to 13 of the switching circuit 1, and a second voltage selector circuit 22 for receiving two data signals (selection signals) D2 and D3 among the data signals D0 to D3 of four bits, and generating control signals S4 to S7 of four bits (00 to 11) to selectively turn ON one of the analog switches 14 to 17 of the switching circuit 1. The switching elements (analog switches) 10 to 17 each may have two transistors having different conduction types connected in parallel between the voltage terminals VO to Vn and the output terminal Yn, and voltage selection signals (control signals) provided by the two voltage selector circuits 21 and 22 (voltage selection means) and inverted versions of the voltage selection signal generated by the inverters 10N to 17N, are supplied to the control terminals of the two transistors having different conduction types respectively. Next, an operation of the display panel drivers in Fig. 9A and the digital data driver circuit in Fig. 9B having the above-mentioned arrangement will be explained. At first, in similar manner to the Fig. 3 arrangement, a CPU 300 instructs a control circuit 200 to provide the respective display panel driver circuits with the four-bit data signal, data clock signal, latch signal, etc. The display panel driver circuits also receive power source voltages (supply voltage signals) V0 to V7 of eight levels from a power source (not shown). As shown in Fig. 9B, in each of the display panel driver circuits that receive the signals and power source voltages, the second latch circuit 32 provides the data signals D0 and D1 to the first voltage selector circuit 21, which provides the selection signals S0 to S3 of four bits to the analog switches 10 to 13. The second latch circuit 32 provides the data signals D2 and D3 to the second voltage selector circuit 22, which provides the selection signals S4 to S7 of four bits to the analog switches 14 to 17. The analog switches 10 to 13 and 14 to 17 also receive inverted selection signals *S0 to *S3 and *S4 to *S7 (not shown), respectively, obtained by inverting the selection signals of four bits S0 to S3 and S4 to S7 by inverters 10N to 13N and 14N to 17N, respectively. For example, when the data signals D0 and D1 equals "00", the first voltage selector circuit 21 provides the selection signals S0 to S3 of "1000" to the analog switches 10 to 13, and when the data signals D2 and D3 equals "00", the second voltage selector circuit 22 provides the selection signals S4 to S7 of "1000" to the analog switches 14 to 17. The selection signals S0 to S3 and S4 to S7 of four bits "1000" and "1000" and the inverted selection signals *S0 to *S3 and *S4 to *S7 of four bits "0111" and "0111" are received as parallel signals by the analog switches 10 to 17 among which an N-MOSFET of the analog switch 10 and a P-MOSFET of the analog switch 14 are turned ON. Fig. 10A is schematic circuit diagram illustrating the analog switch 10 and 14 when turned ON and Fig. 10B is an equivalent circuit of Fig. 10A explaining an operation thereof. The two turned ON analog switches 10 and 14 divide an added voltage V0+V4 of the power source voltages V0 and V4 by an ON-state resistance Ron of the load resistance of each of the analog switches 10 and 14 into a drive siqnal voltage (V0+V4)/2, provided from an output terminal Yn (onmm output node) as shown in Fig. 10B. The ON-state resistance Ron of each of the analog switches 10 and 14 is formed when the P-MOSFET and N-MOSFET act as load elements through a depletion operation. In this way, the data signals of four bits D0 to D3 are divided into data signals D0 and D1 and the data signals D2 and D3, and according to the divided data signals D0 and D1, and D2 and D3, two of the analog switches 10 to 17 are selected together as a predetermined group and turned ON so that 16 levels of drive signal voltage, greater in number than the eight levels of the input power source voltages V0 to V7, are available through the output terminal Yn. When the eight input voltages are V0=2 (V), V1=2.4 (V), V2=2.8 (V), V3=3.2 (V), V4=2 (V), V5=3.6(V), V6=5.2 (V), and V7=6.8 (V), the relation among an input data, applied voltage and output voltage at the digital data driver circuit in Fig. 9B are as shown in Fig. 11 as a table. Fig. 12 is a graph showing the transmission-voltage characteristics (gray-scale characteristics) of liquid crystal and gray-scale levels according to the output voltage shown in Fig. 11. In this way, a combination of the analog switches having different ON-state resistances can realize a digital driver IC that drives many gray-scale levels with a smaller number of power sources and analog switches. Further, under the condition that the eight input voltages are as described, the worst case of maximum power consumption to produce a largest quantity of heat, i.e., a largest current flowing through the P-MOSFET and N-MOSFET of one of the analog switches 10 to 17 is found as follows: Power consumption "Pbit" for each bit: Pbit = ( V0 - V7 ) x ( V0 - V7 / 2 Ron = 4.8 x 4.8 / (2 x 2.5) = 4.6 (mW) Power consumption "Pchip" for each chip: Pchip = 4.6(mW) x 160 bits = 740 (mW) A panel power consumption P per inch: 10" panel P = 4.6(mV) x 640 x 3 = 14.2(W) In Fig. 13, a digital data driver circuit according to a second embodiment of the present invention comprises, instead of the first and second voltage selector circuits 21 and 22 and the switching circuit 1 of the embodiment of Fig. 9B, a switching circuit 1A having analog switches 10 to 18, and a voltage selector circuit 23 for selectively turning ON two of the analog switches 10 to 18 corresponding to two adjacent power source voltages V0 to V8. The circuit of this embodiment has the analog switch 18 in addition to the analog switches 10 to 17 of the switching circuit 1 of the first embodiment, and an inverter 18N in addition to the inverters 10N to 17 N. An operation of the circuit of the second embodiment will be explained. Similar to the first embodiment, latch circuits 31 and 32 hold data signals of four bits D0 to D3 in response to clock signals CL1 and CL2. According to the held data signals of four bits D0 to D3, the voltage selector circuit 23 turns ON two adjacent analog switches m and m+1 (m is a natural number) to select two adjacent power voltages Vm and Vm+1 among predetermined power source voltages V0 to V8. Fig. 14A is schematic circuit diagram when the analog switches m and m+1 are selected to turn ON and Fig. 14B is an equivalent circuit of Fig. 14A explaining an operation thereof. The two turned ON analog switches m and m+1 divide an added voltage Vm + Vm+1 of the power source voltages Vm and Vm+1in proportion to an ON-state resistance Ron of the load resistance of each of the analog switches m and m+1 to provide a voltage (Vm+Vm+1)/2 (assuming the ON-state resistances of the two switches are equal) at an output terminal Yn as shown in Fig. 14B. The ON-state resistance Ron of each of the analog switches m and m+1 is formed when the P-MOSFET and N-MOSFET act as load elements through a depletion operation. In this way, according to the data signals D0 to D3, two adjacent analog switches m and m+1 are selected from the analog switches 10 to 18 and turned ON, so that 16 levels of power source voltages that are greater in number than the eight levels of the input power source voltages V0 to V8 are provided through the output terminal Yn. When the eight input voltages are V0=2 (V), V1=2.4 (V), V2=2.8 (V), V3=3.2 (V), V4=3.6 (V), V5=4 (V), V6=4.4 (V), V7=4.8 (V) and V8=5.2 (V), the relation between an input data, applied voltage and output voltage at the digital data driver circuit in Fig. 13 is shown in Fig. 15 as a table. In this way, the output voltage Yn based on the two adjacent power source voltages V0 to V8 may provide output voltages corresponding to 16 gray-scales (actually 17 gray-scales, and 16 of them are selected), as shown in Fig. 15. Since a voltage difference between two adjacent voltages of the power source voltages V0 to V8 is 0.4 V, power consumption may be kept acceptably low by selecting adjacent voltages among the power source voltages V0 to V8. Similar to the power consumption calculation of the first embodiment (the equations (1), (2), and (3)), power consumption of this embodiment is found as follows: Power consumption "Pbit" for each bit: Pbit = (0.4 V) 2 / 2Ron = (0.4 V) 2 / (2 x 2.5kΩ) = 0.032 (mW) Power consumption "Pchip" for each chip: Pchip = 0.032 x 160 = 5.12 (mW) Panel power consumption 10" panel P for one inch: 10" panel P = 0.032 mW x 1920 = 61.4 (mW) In this way, this embodiment can greatly reduce the power consumption compared with the equations (1), (2), and (3) of the previous embodiment. Figure 16 is a schematic block circuit diagram relating to the second embodiment, which will be a reference block circuit diagram to be compared with the block circuit diagram of other embodiments according to the present invention to be described hereinafter. Figure 17 is a circuit diagram showing one example of a voltage selector circuit 23 embodying the present invention. In Fig. 17, the voltage selector circuit 23 comprises a decoder circuit 231 for receiving three data signals D1 to D3 and providing a selection signal of eight bits, an AND circuit 232 for providing an AND of the selection signal of eight bits and another data signal D0, and an OR circuit 233 for providing an OR of outputs of the AND circuit 232 and the selection signal of eight bits. In each of the previous embodiments, two of the power source voltages V0 to V7 (or V8) are selected and divided. This embodiment optionally selects a plurality of voltage levels, and two sets of them, or a combination of them are divided to provide a divided voltage output, thereby realizing a large number of gray-scales. Figure 18 is a schematic block circuit diagram showing a digital data driver circuit according to a third embodiment of the present invention. The digital data driver circuit according to this embodiment receives power source voltages (supply voltage signals) V0 to V4 instead of the power source voltages V0 to V8 of the second embodiment of Fig. 16, and two analog switches are connected as a unit to each of the power source voltages V0 to V4. For example, in one unit two analog switches Rao and Rbo are connected to the power source voltages V0. The analog switches connected to the power source lines of different voltage levels are simultaneously turned ON to divide the power source voltages and provide more voltage levels than the five input voltage levels. Namely, the embodiment of Fig. 18 has five power sources, and a unit having two analog switches for each of the power sources, i.e., ten analog switches 180 to 189. A ratio of ON-state resistances of the two analog switches in each unit is set to 1:2 (Rai=2Rbi=Ron : i is 0 to 4). As shown in Figs. 19A, 19B, and 19C, the switches may be selected in a configuration of "one switch from one unit and two switches from another unit", "one switch from one unit and one switch from another unit" or "two switches from the one unit and one switch from the other unit", to divide adjacent power source levels into three equal levels (1/4, 1/2, and 3/4). As a result, the five power sources and ten analog switches provide output 16 gray-scale levels. Note that in Fig. 19A and 19C, 1/2 means that Rb=Ra/2. Figure 20 shows the output voltage characteristics, i.e. a relationship between input data, 16 gray-scale levels to be achieved, analog switches to be selected either individually or as a predetermined group, and output voltages of the five power source voltages and ten analog switches of Fig. 18. ON-state resistances of the two analog switches connected to the same power source are Rai=4 (kΩ) and Rbi=2 (kΩ). The power source voltages are 2.0 (V), 2.8 (V), 3.6 (V), 4.4 (V), and 5.2 (V). These realize voltage levels for the 16 gray-scales between a white level (2.0 V)) and a black level (5.0 (V)) of the TFT-LCD panel. In the third embodiment, two analog switches having different ON-state resistances are connected as a unit to the same power source level, but more than two analog switches may be connected as a unit to the same power source level. The simultaneously selected voltage levels are adjacent voltage levels according to this embodiment, but any of the voltage levels may be simultaneously selected and divided. According to this embodiment, the ON-state resistances of a plurality of the analog switches are different from one another. These ON-state resistances may be equal to one another, and a combined value of the ON-state resistances may be changed depending on the number of analog switches to be turned ON, when dividing the power source voltages. Figure 21 is a schematic block circuit diagram showing a digital data driver circuit according to a fourth embodiment of the present invention. In the digital data driver circuit according to this embodiment, additional resistances r0 to r8 are connected in series between the power source line connection points and the analog switches 10 to 18 of the second embodiment of Fig. 16. Figure 22A and 22B are an explanatory views showing a principle of operation of this embodiment. In Fig. 22A and 22B, the second and fourth embodiments are compared with each other for fluctuations in output voltages that are derived by simultaneously selecting two analog switches and dividing the output voltages thereof with ON-state resistances of the selected analog switches. According to the circuit of Fig. 22A, a fluctuation ΔR in the ON-state resistances of each of the analog switches causes a relatively large fluctuation in the output voltage. On the other hand, according to the embodiment of Fig. 22B, a fluctuation in the output can be much reduced when the additional resistance r is greater than the fluctuation ΔR in the ON-state resistance. The embodiment of Fig. 21 can suppress a fluctuation in the ON-state resistances, reduce a fluctuation in the charging and discharging time of an added capacitance, and eliminate unevenness of display due to a fluctuation in the rising characteristics of a voltage waveform, not only when selecting two analog switches but also when selecting one analog switch. In the fourth embodiment (Fig. 21), the driver IC involves nine analog switches and nine power sources to realize 16 gray-scale levels. The additional resistance r is connected in series with each of the analog switches. If the ON-state resistance Ron of the analog switch is 500( Ω ) and the fluctuation ΔR of the ON-state resistance 50%, i.e., ΔR=250(Ω ), and if Vi=V (V) and Vj=0 in Fig. 22A and 22B, the output voltage (Fig. 22A) will be: Yn = V × (1 - ΔR / Ron) / 2 so that a fluctuation Δ Yn in an output is: Δ Yn =- (V/2) × (Δ R/Ron) The output fluctuation is, therefore, 50%. On the other hand, the embodiment of Fig. 22B having the additional resistances r (for example 5kΩ) is: Yn = V × [1- Δ R / (Ron + r)] / 2 so that a fluctuation Δ Yn in an output is: Δ Yn =- (V/2) × [ Δ R / (Ron + r)] Namely, the output fluctuation is 250/(500+5000)=0.045, i.e., about 5%. Next, a method of forming the additional resistances will be explained. Resistances to be formed in an integrated circuit may be semiconductor resistances or thin film resistances. The semiconductor resistances are classified into diffusion resistances and ion implantation resistances. The diffusion resistance uses a diffusion layer for a base or an emitter. Figure 23A shows a top face showing an element structure of the diffusion resistance using a p-type base diffusion layer of an npn transistor. And Fig. 23B shows a section view of Fig. 23A. With a length L and a width W, a resistance value R is expressed as: R = pL/xjW where p is an average resistance ratio of the diffusion layer, and xj the depth of a junction. In the actual designing of a resistance, a layer resistance (or a sheet resistance) Rs=p/xj. The layer resistance is a resistance value per unit square on a plane pattern and expressed with a unit of Ω / square. When this substitutes for the equation (11), R = Rs(L/W). The Rs is usually 50 to 250 Ω / square for a base diffusion layer, and 2 to 10Ω / square for an emitter diffusion layer. The former is used as a resistance of the order of kΩ , and the latter as a resistance of the order of several to 100 Ω . Since the mobility of carriers decreases according to temperature, the Rs has a positive temperature factor of about 1000 to 3000 ppm/ °C . This temperature dependency of the Rs causes a temperature drift of an integrated circuit. Since the diffusion resistance is separated from a substrate by a pn junction of reverse bias, it has depletion layer capacitance due to a parasitic effect. As shown in Fig. 23C, a high-frequency equivalent circuit is a distributed RC circuit whose impedance decreases at a high frequency. The ion implantation resistance is a layer resistance formed on the surface of a semiconductor by injecting impurities such as boride according to an ion implantation technique. Figure 24 shows a sectioned structure of the ion implantation resistance. The impurities exist in a thin layer of typically 0.1 to 0.8 micrometers thick formed on the silicon surface. Namely, the ion implantation resistance is about 20 times thicker than the diffusion layer which is 2 to 4 micrometers in thickness, and therefore, the ion implantation resistance provides a high resistance value of the order of 100 k Ω . As shown in Fig. 25, the thin film resistance is a polysilicon film or a nichrome thin film formed on an oxide film. Since the thin film resistance holds a layer resistance of 20 to 500Ω / square, a small parasitic capacitance, and a low voltage dependency, it is easy to use. The polysilicon is frequently used in semiconductor processes and has a good affinity with an LSI. The nichrome is easily trimmed so that it is used as a load resistance for a precision D/A converter. The diffusion resistance, ion implantation resistance, and thin film resistance used is determined according to requirements of the additional resistances and ease of preparation. In the fourth embodiment (Fig. 21), the additional resistances may be arranged between the power sources and the analog switches, or between the analog switches and the output. Figure 26 is a schematic block circuit diagram showing a digital data driver circuit according to a fifth embodiment of the present invention. As shown in the figure, the digital data driver circuit of this embodiment comprises additional resistances ra0 to rb4 disposed between the power source lines and the analog switches 180 to 189 of the third embodiment of Fig. 18. The principle of operation of this embodiment is the same as that of the fourth embodiment. A fluctuation in the ON-state resistances of the analog switches is minimized by the additional resistances having high resistance values. As explained above, in embodiments of the present invention, voltage selection circuitry selectively turns ON one or a plurality of analog switches connected to a plurality of power source voltage terminals having different voltage levels, and switching circuitry divides a plurality of the power sources voltages by load resistances of the turned ON analog Switches. As a result, the number of output voltage levels becomes greater than the number of the power source voltage levels. With a simple circuit configuration and without increasing the size of a circuit a circuit embodying the invention can drive a display panel with more gray-scales. In addition, in certain embodiments it is possible to reduce fluctuations in output voltage levels due to fluctations in ON-state resistances of the analog switches, so that a high quality image with gray-scales and multicolour (full color) can be produced.

Claims: Display driving circuitry for providing to a display device connected with the circuitry a drive signal of a voltage level that can be selected from among a plurality of predetermined voltage levels by application of respective digital selection signals (D 0 to D 3 ) to the circuitry, which circuitry includes: a voltage source for providing a set of supply voltage signals (V 0 , V 1 ,..., V n ) of respective different predetermined magnitudes; a plurality of switching elements (10 to 17; 10 to 18; 180 to 189), each having an input terminal for receiving from said voltage source one of the said supply voltage signals (V 0 to V n ) of the said set and also having an output terminal connected to a common output node (Yn) of the circuitry at which such a display device is connected when the circuitry is in use; and voltage selection means (21, 22; 23; 24) for connection to receive such digital selection signals (D 0 to D 3 ) and operable in response to receipt of each such selection signal (D 0 to D 3 ) to activate at least a predetermined one of the said switching elements, so as to cause such a drive signal, of a predetermined voltage level that is associated individually with the activated switching element(s), to be produced at the said common output node of the circuitry; characterised in that the said voltage selection means (21, 22; 23; 24) are operable in response to at least one of the said selection signals (e.g. 0000 in Figure 11) to activate a predetermined group of the switching elements (10, 14), such that the resulting drive signal has a predetermined voltage level ((V 0 + V 4 )/2) that is associated individually with the group concerned and that is dependent upon a combination of the supply voltage signals (V 0 , V 4 ) received by the switching elements (10, 14) of that group; the activation of the said switching elements being so controlled by the voltage selection means that the number of different predetermined voltage levels in the said plurality is greater than the number of supply voltage signals in the said set. Display driving circuitry as claimed in claim 1, wherein the said voltage selection means (10 to 17) are operable in response to receipt of each of the said respective digital selection signals (D 0 to D 3 ) to activate respective different predetermined groups of the said switching elements. Display driving circuitry as claimed in claim 1 or 2, wherein the or each predetermined group of the switching elements is constituted such that the supply voltage signals received by the switching elements of the group are the supply voltage signals (e.g. V 0 , V 1 ) of the said set that are closest in magnitude to one another. Display driving circuitry as claimed in claim 1, wherein the said switching elements (180 to 189) are arranged in units (Ra, Rb) corresponding respectively to the different supply voltage signals (V 0 to V 4 ) of the said set, each unit of switching elements having at least two of the said switching elements of the said plurality that are each connected for receiving the corresponding supply voltage signal. Display driving circuitry as claimed in claim 4, wherein a first one (Ra) of the switching elements of each unit has an on-state resistance different from that of a second one (Rb) of the switching elements of the units concerned. Display driving circuitry as claimed in claim 5, wherein each unit comprises only two switching elements and wherein the ratio of the on-state resistance of the said first switching element (Ra) of each unit to the on-state resistance of the said second switching element (Rb) of the unit concerned is 2:1. Display driving circuitry as claimed in claim 6, wherein some of the said predetermined groups are made up of two first switching elements (Ra), or two second switching elements (Rb), of different respective units, and others of the said predetermined groups are made up of the first and second switching elements (Ra, Rb) of one unit and a further switching element (Ra/Rb) belonging to another unit. Display driving circuitry as claimed in any preceding claim, wherein the said switching elements (10 to 17; 10 to 18; 180 to 189) each have two transistors of different conductivity types (P,N) connected in parallel with one another between the said input terminal of the switching element concerned and the said output terminal; one of the two transistors (P) being activated by a control signal (S 0 to S 7 ) applied to a control terminal thereof by the said voltage selection means (21, 22; 23; 24), and the other of those two transistors (N) being activated by a further signal (*S 0 to *S 7 ) applied to a control terminal thereof, which further signal is inverted with respect to the said control signal (S 0 to S 7 ) applied to the said one transistor (P) . Display driving circuitry as claimed in claim 8, wherein the said two transistors (P,N) of each switching element (10 to 17; 10 to 18; 180 to 189) are a p-channel MOSFET and an n-channel MOSFET respectively; and the said control signal (S 0 to S 7 ) and the said further signal (*S 0 to *S 7 ) that is inverted with respect to the said control signal are applied respectively to gate terminals of the p-channel and n-channel MOSFETs. Display driving circuitry as claimed in any preceding claim, wherein an additional resistance (r0 to r8; raO to ra4, rb0 to rb4) is connected in series with each of the said switching elements (10 to 18; 180 to 189). Display driving circuitry as claimed in claim 10, wherein the resistance values of the said additional resistances (r0 to r8; ra0 to ra4, rb0 to rb4) are higher than the on-state resistances of the said switching elements (10 to 18; 180 to 189). Display driving circuitry as claimed in claim 10 or 11, wherein the said additional resistances (r0 to r8 ra0 to ra4; rb0 to rb4) are formed by a diffusion resistance method, an implantation resistance method, or a thin film resistance method.

Inventors: ODA MASAMI, TAKAHARA KAZUHIRO, YAMAGUCHI TADAHISA, ODA, MASAMI, TAKAHARA, KAZUHIRO, YAMAGUCHI, TADAHISA
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1991
Main classification: G09G3
IPC codes: G02F1, G09G3