TWO-STEP ANALOG-TO-DIGITAL CONVERTER

Abstract: Two-step analog-to-digital converter, for the conversion of an input analog signal (Vin) in a N bit digital code, consisting of a sample and hold circuit (S/H), a resistive ladder (SR), a set of comparators (COMP), a set of control (LCC), coding (COD) and storage or latch (LT, LTU) digital circuits. The converter reuses the same resistive ladder (SR) and the same comparators (COMP) for both conversion steps of input signal (Vin).

Description: TWO-STEP ANALOG-TO-DIGITAL CONVERTER The present invention refers to a two-step analog-to- digital converter for the conversion of an analog electric signal into a digital electric signal. In the first step the most significant bits (MSBs) are coded and in the second step the last significant bits (LSBs) of the digital code are determined. This converter relies on flash technique, where the input to be coded is simultaneously compared to a plurality of reference voltages. Some known implementations of the two-step flash conversion, require two resistive ladders, one for the MSBs and the other one for the LSBs. The comparators employed in the two subsequent conversion steps are the same. This implementation is disadvantageous as regards silicon die size, considering also that the resistive ladder value derives its lower limit from power dissipation specification. It is also necessary to generate two extra reference voltages, scaled down by 2 N/2 with respect to full scale values, where N is the conversion bit ' number. These voltages bias the additional ladder and have to determine the reference levels for the LSBs with the same accuracy as the levels for the MSBs on main resistance. Possible inaccuracies in this operation can originate the loss of intrinsic monotonic nature of potentiometric converters, as well as a downturn of the converter absolute linearity tied to the accuracy of the division of the full scale voltage by the resistive ladder. To avoid these drawbacks, some known solutions propose a conversion scheme where the LSBs are determined by using the same resistive ladder of the MSBs coarse conversion, introducing an amplifier circuit with gain equal to 2 N 2 . This amplifier has a loop gain-bandwidth product equal to the product between the open loop cut off frequency and the feedback factor, which is close to 1/2 N/2 . This involves the design of an operational amplifier having a potential operation speed 2 N/2 times higher than the one actually employed, with the simultaneous charge of a high slew rate specification due to the high input capacitive load, equal to 2 N 2 .Cin, where Cin is the input capacitance. The object of the present invention is to realize the analog-to-digital conversion as previously described, by using a single resistive ladder overcoming the drawback of the previous solutions. The converter forming the object of the present invention gets to obtain good operation speed, low power dissipation and limited silicon die size while preserving the monotonic nature of potentiometric converters. These targets are reached through the invention consisting of an analog-to-digital converter for the conversion of an analog input signal to a N bit digital code , including: a sample and hold circuit receiving at its input the analog signal to be coded; a ladder of resistances connected in series among them whose extrem terminals are connected to two reference voltage sources for the generation of intermediate comparison voltages; a set of comparators for comparison of the input signal and said intermediate reference thresholds; a set of latchs connected to the outputs of said comparators; a coder to combine a digital code to the said comparators output configuration, according to previously defined rules; a storage buffer for the digital code produced; characterized by the fact that said ladder consists of 2 N elementary resistances clustered in 2 N 2 segments, each one formed by 2 N 2 elementary resistances and that said comparators are 2 M/2 - 1 in number, selectively connectable to the taps of segments by means of a plurality of switches, and to the taps of each single elementary resistance of a segment via one of the switch block controlled by a selection combinatorial logic circuit whose inputs are connected to the outputs of said latches. According to the invention, it- is supposed the reuse of the same resistive ladder for the conversion both of the MSBs and of the (LSBs) without adding further analog circuitry, switching subsequently the same set of comparators from the main resistive ladder to one of its segments. It is thus obtained a considerable save in the silicon die size and a limited power dissipation. The invention shall be now described making reference to a preferred realization form, shown in the figures enclosed, where: Fig. 1 shows a general block diagram of a converter according to the invention; Fig. 2 shows in detail the architecture of the resistive ladder; Fig. 3 shows a block diagram of another realization form of the converter according to the invention; and Fig. 4 shows the time trend of the control phases Φl- Φ4 and of the S/H control phase. Referring in particular to Figg. 1 and 3, the converter according to the invention includes a resistive ladder labelled SR, a set of comparators or comparing elements (2 N/2 - 1 in number) , clustered in the COMP block. More in detail, each comparator can selectively be connected to the taps of segments GR (case A) , to the taps of the single elementary resistances Rei of a chosen segment GR (case B) and to the output of the sample and hold circuit S/H (case C) . In case A the connection is made through a plurality of switches S G; in case B it is made by a controlled switch block (SWF) selected by a combinatorial circuit (LCC) whose inputs matches the outputs of said latches LT; finally in case C, through a plurality of switches SWI. The connection to the reference voltages and to the input voltage takes place on different times. The 2 N 2 -l outputs of comparators are connected to the same number of latches or hold circuits forming the LT block, and from these ones to the encoder COD whose generated code is stored in the output latches LTU. It is also provfided a combinatorial logic circuitry LCC between the block LT and switch blocks SWF. The converter components shall now be described more in detail. The resistive ladder SR is made of 2N elementary resistances Re of equal value, where N is the number of bits by which the analog signal shall be coded, clustered in 2 N 2 segments, each one consisting of 2 N/2 elementary resistances (see Fig. 2) . The terminals of the ladder SR are connected to two reference voltages Vrefl and Vref2 defining the dynamic range of the input signal. Voltage values available at the taps of the main segments GR represent the decisional thresholds for the conversion of the MSBs and are forced at the comparators COMP through the closing of the 2 N/2 -l switches forming SWG. Voltages available at the taps of the elementary resistances Re inside each segment GR represent the reference levels for the determination of the LSBs. In this case the connection to comparators is assured by SWF blocks, each one consisting of 2 N 2 -l switches, under the control of the logic LCC. The comparators of the COMP block are preferably of the type forming the object of the patent application of the same applicant under the title: "Low power dissipation autozeroed comparator circuit" reference to which has to be made for further details. However, other comparing circuits of the known type can be employed. The S/H circuit essentially includes a capacitance referred to an analog ground voltage, followed by a unit gain de-coupling element. The middle point of the resistive ladder RS, labelled Vref in Fig. 1, is selected as reference analog ground. We shall now describe the operation of a complete conversion cycle requiring four clock-signals or phases shown in Fig. 4. During phase Φl, comparators COMP are autozeroed, and their reference inputs are connected to the 2 N/2 -l reference voltages available at the taps of segments GR, indicated also as coarse reference voltages. At the same time, the input signal Vin is sampled and stored in the S/H circuit. During subsequent phase Φ2, the inputs of comparators are switched to the output of the S/H circuit, in such a way that each comparator makes the comparison between the sample of the input signal to be coded and one of the reference levels generated by the resistive ladder SR. The output of each comparator, assumes, for instance, the high level when the input signal sample is higher than the reference threshold present at the other input. On the basis of the 2 N - /2 -l logic outputs of comparators, the digital encoder COD determines the N/2 MSBs, according to the selected coding system. This coding system can be of different type and is not described here in detail. During the same phase Φ2, the outputs of comparators are also feed to the LCC selection combinatorial logic and used to identify one of the main resistive segments GR, and more in detail the one whose upper tap corresponds to a reference voltage immediately higher than the value of the input voltage Vin. The LCC logic generates 2 N 2 -l control signals, controlling in parallel the switch blocks SWF, connected to the taps of the elementary resistances Re of each main resistive segment GR. During phase Φ3, second autozero phase of the converter, only one of the aforesaid control signal is activated, and it determines the connection of the 2 N 2 -l comparators COMP already used, to the new fine reference values internal to the segment GR identified by the LCC logic. At the beginning of phase Φ4, second comparison phase, the inputs of comparators are switched again to S/H output to determine the remaining N/2 LABS referring to the voltage Vin stored on the capacitance. Ci. The converter according to the invention requires a number of switches on the resistive ladder equal to the sum of 2 N *' 2 -1 (for the MSBs determination) and of 2 N ' 2 *(2 N / 2 -l) (for LSBs determination) . These switches conduct current only during a brief transient, therefore they do not affect the voltage value of the point where references for comparison are withdrawn. According to a preferred realization form of the invention, shown in Fig. 3, however the number of switches can be reduced, and this without adding further control logic circuitry. The same references used in Fig. 1 have been used in Fig. 3 for the components performing equal or similar f nctions. This realization form presents a single switch block SWF connected to the resistances of the middle GR segment of the resistive ladder, whose lower tap is referred to the analog ground voltage (Vref) . Furthermore the capacitance Ci of the sample and hold circuit (S/H) has a plate which can be connected to the input voltage to be converted (Vin) , and the other plate selectively connectable to a lowering voltage (Vlow) chosen by a combinatorial logic LCA, and to the analog ground voltage (Vref) . According to this realization form, during the second conversion step, the conversion of the difference between the input voltage Vin and the reference one resulting immediately lower than Vin, is performed. This difference ranges between 0 and 5v, with δv = (Vrefl - Vref2)/2 N * /2 and is referred to the analog ground. The operation of the analog-to-digital converter of Fig. 3 is the following. During phase Φl the operation is alike that of the converter of Fig. 1. During phase Φ2 coding of the MSBs takes place as before. Furthermore, the selection of an appropriate voltage Vlow takes place in this phase, maintaining the voltage to convert during the second conversion step, within the same predetermined voltage interval δv, for any input voltage. The lowering voltage Vlow is selected among a finished set of possible values made of the voltages at the taps of GR segments, including Vrefl. Referring to the structure of the S/H circuit shown in Fig. 3, the voltage Vx at the S/H output is equal to (Vin + Vlow - Vref) , where Vref corresponds to the middle point of the resistive ladder. Two cases occur which shall be described below, making reference to a 2.5V analog ground voltage Vref. Case A Vin -2.5V + nδv < Vin < 2.5 + (n+1) δv with n integer ranging from 0 to N/2. In this case it is selected Vlow = 2.5 - nδv and voltage Vx becomes: lower limit 2.5+nδv-nδv=2.5 Vx=Vin-2.5+2.5-nδv( upper limit 2.5+(N+l) v-nδv=2.5+δv Case B Vin <2.5V 2.5 - (n + 1) δv < Vin < 2.5 - nδv In this case it is selected Vlow = 2.5 + (n + 1) v and voltage Vx becomes: lower limit 2.5-(n+l) δv+(n+l) δv=2.5 Vx=Vin-2.5+2.5+(n+l) δv{ upper limit 2.5-nδv+(n+1) δv=2.5+δv Depending on comparators outputs the selection logic LCA, generates the 2 N 2 control signals to determine Vlow by means of switches SW, being active one signal at a time. Determining the new level of scaled down input voltage is affected by error, due to the parasitic capacitance of the top plate of the hold capacitance Ci, which determines the conversion accuracy. In the implemented realization form this limit is equal to 8 bits. During phase Φ3, second autozero phase, comparator inputs, already used for the MSBs,. are switched to the voltages of fine reference. These thresholds are obtained at the taps of the elementary resistances Re of the GR resistive segment, referred at the bottom to 2.5 V (Vref) and at the top to (2.5 +δv) V. At the same time, the bottom plate of the hold capacitance Ci of S/H is connected to the Vlow voltage previously identified. Finally, during phase Φ4 the operation is similar to the one previously described referring to Fig. 1. During this phase the capacitance Ci of S/H is referred to Vlow. With the described structure, the number of switches which persist on the ladder is equal to the sum of 2 N 2 -l (for the MSBs determination) and of 2 N -' 2 -l + 2 N <' 2 (for the LSBs determination) .

Claims: CLAIMS 1. Analog-to-digital converter for the conversion of an input analog signal (Vin) to a N bits digital code, including: a sample and hold circuit (S/H) receiving at its input the analog signal (Vin) to be coded; a ladder of resistances (SR) connected in series among them, whose extreme terminals are connected to two reference voltage sources (Vrefl, Vref2) for the generation of intermediate comparison voltages; a set of comparators (COMP) connectable for the comparison among the input signal and said intermediate reference thresholds; a plurality of latches (LT) connected to the outputs of said comparators; a coder (COD) to associate a digital code to the output configuration of said comparators, according to preset rules; a storage buffer (LTU) to store the digital code produced; characterized by the fact that said ladder consists of 2N elementary resistances (Re) clustered in 2 N/2 segments (GR) , each one made of 2 N 2 elementary resistances, and that said comparators (COMP) are 2 N 2 -1 in number, selectively connectable to the taps of segments (GR) by means of a plurality of switches (SWG) , and to the taps of the single elementary resistances (Re) of a segment through one of the switch blocks (SWF) controlled by a selection combinatorial logic circuit (LCC) whose inputs are connected to the outputs of said latches (LT). 2. Analog-to-digital converter according to claim 1, characterized by the fact to require 2 N/2 switch blocks, the outputs of said selection combinatorial logic circuit (LCC) forming the enabling signals for only one of said switch blocks. 3. analog-to-digital converter according to claim 1, characterized by the fact to require a single switch block (SWF) to connect the reference inputs of comparators (COMP) to the elementary resistances (Re^ of a predetermined segment (GR) , and by the fact that the sample and hold circuit (S/H) receives as reference a lowering voltage (Vlow) selected by the combinatorial logic circuit (LCA) and the analog ground voltage (Vref) corresponding to the voltage of the middle point of the resistive ladder (SR) . 4. Analog-to-digital converter according to claim 3, characterized by the fact that said predetermined resistive segment (GR) is the one referred at the bottom to the analog ground (Vref) . 5. Analog-to-digital converter according to claim 3 or 4, characterized by the fact that the sample and hold circuit (S/H) includes a storage capacitor having a plate which can be connected to the input voltage to conver (Vin) , and the other plate which can be connected to said lowering voltage (Vlow) and to the analog ground voltage (Vref) . 6. Analog-to-digital converter according to claims 3, 4 or 5, characterized by the fact that said lowering voltage (Vlow) is selected among 2 N 2 possible values depending on the value of the input voltage (Vin) , in such a way to reduce the second conversion step to the same predetermined resistive segment (GR) , regardless of the value of the input voltage (Vin) .

Inventors: BAGGINI BARBARA, COPPERO LUCIANA, MALOBERTI FRANCO, PALMISANO GIUSEPPE, BAGGINI, BARBARA, COPPERO, LUCIANA, MALOBERTI, FRANCO, PALMISANO, GIUSEPPE
Applicants: ITALTEL SPA, ITALTEL SOCIETA ITALIANA TELECOMUNICAZIONI S.P.A.
Application year: 1991
Main classification: H03M1
IPC codes: H03M1