Method of manufacturing semiconductor device having gate electrode self-aligned to source and drain electrodes

Abstract: According to this invention, there is provided a method of manufacturing a compound semiconductor which can be formed at a high yield and in which variations in characteristics of elements caused by variations in distances between a source and a gate and between a drain and the gate can be minimized. In addition, there is provided a compound semiconductor device having a structure capable of increasing a power gain and obtaining a high-speed operation. According to this invention, an active layer (2, 4, 5) is formed on a compound semiconductor substrate (1), and source/drain electrodes (9) are formed on the active layer (2, 4, 5) to be separated from each other. The wall insulating films (13) are respectively formed on side walls of the electrodes (9), and a gate electrode (16₂) is formed between the side wall insulating films (13) to be respectively in contact therewith.

Description: The present invention relates to a method of manufacturing a semiconductor device. A recess structure is conventionally known as a structure of an FET or obtaining a large power gain. According to this recess structure, a semiconductor region serving as a channel region is formed deeper than other semiconductor regions, and especially the source resistance of the surface depletion layer is reduced. Therefore, the transconductance gm can be increased, and a large power gain can be obtained. Although the recess structure is generally and frequently used in a compound semiconductor device represented by a GaAs semiconductor device, some problems are posed in manufacturing the recess structure. According to a conventional manufacturing method, after an active layer is formed by a predetermined compound semiconductor, a source/drain electrode pattern is formed. A resist pattern of a gate electrode pattern is formed, and wet etching for obtaining a recessed groove (to be referred to as a groove) is performed using the resist pattern as a mask. A gate electrode is formed using a lift-off technique. According to a conventional manufacturing method, the gate electrode can be formed to be self-aligned in the groove. However, the gate electrode cannot be formed to be self-aligned to the source/drain electrodes. For this reason, distances between the gate and source electrodes and between the gate and drain electrodes are different from each other. For example, when the distance between the gate and drain electrodes is decreased, the breakdown voltage is decreased. At the same time, the distance between the gate and source electrodes is increased. For this reason, the source resistance is increased, and the current transconductance gm is decreased. As a result, the obtained compound semiconductor device such as a MESFET or an HEMT has characteristic variations. In the worst case, the compound semiconductor device is not shipped as a product. Therefore, the yield of the production is decreased. As described above, according to that conventional method, after source/drain electrodes are formed, a new resist pattern is formed, and a gate electrode is formed using the pattern as a mask. Therefore, since a gate electrode is formed by mask alignment, distances between the gate and source electrodes and between the gate and drain electrodes are different from each other, thereby causing characteristic variations in semiconductor devices. Variations in the distance between, e.g., gate and drain electrodes appear as variations in breakdown voltage, and variations in distance between gate and source electrodes cause variations in source resistance and appear as variations in high-frequency characteristic. EP-A-0 308 939 shows a method of manufacturing a MESFET having a gate self-aligned with both the source/drain regions and the source/drain electrons, comprising forming a groove and a gate electrode between sidewall insulating films. Lattice damage is cured by tempering. "Gate Formation in GaAs MESFETs Using Ion-Beam Etching Technology" by Chang-Lee Chen and Kensall D. Wise, IEEE Transactions on Electron Devices, Vol. 29, No. 10, October 1982 describes in Section IIID thereof an ion-beam deposition technique for MESFET gate formation in which deposition is conducted immediately following patterning by etching without breaking vacuum. The present invention has been made in consideration of the above problem, and has as its object to provide an improved method of manufacturing a semiconductor device. According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming an active layer on a semiconductor substrate; etching a mesa thereon to isolate an element region; coating the entire surface of the resultant structure with a first photoresist; removing said first photoresist from said element region by photoetching; forming a first metal layer on the entire surface of the resultant structure, said first metal layer providing an ohmic contact with said active layer; removing said first metal layer except from on said element region, together with said photoresist using a selective lift-off technique; coating the entire surface of the resultant structure with a second photoresist; forming an opening in the second photoresist on said element region by photoetching; using said second photoresist as a mask to selectively remove the exposed portion of the first metal layer; forming a groove in a portion of said active layer through said opening using reactive ion etching or ion milling; wet-etching a surface of said groove; removing said second photoresist; forming an insulating layer on the entire surface of the resultant structure; subjecting said insulating layer to reactive ion etching in order to remove said insulating layer, except from on the side walls of said groove and on the corresponding side walls of said first metal layer, thus exposing the bottom of said groove; wet-etching said bottom of said groove; forming a second metal layer on the entire surface of the resultant structure, said second metal layer forming a Schottky-contact with said active layer in the groove; forming a mask pattern from a third photoresist on said second metal layer; and etching said second metal layer in order to form a gate electrode in the groove and source and drain electrodes on respective portions of the first metal layer. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figs. 1A to 1J are sectional views showing an HEMT manufactured according to the first portion of the invention in the order of manufacturing steps; Fig. 2 is a sectional view showing the remainder of the manufacturing method explained with reference to Figs. 1A to 1J; Fig. 3 is an enlarged view showing a portion near a groove 12 of the HEMT shown in Fig. 1J; Figs. 4A to 4F are sectional views showing steps in the manufacture of a MESFET, and do not show all the features of the invention, but are included for explanatory purposes; Fig. 5 is a sectional view showing an HEMT formed by the manufacturing method explained with reference to Figs. 4A to 4F. The present invention will be described below with reference to the accompanying drawings. Figs. 1A to 1J and 2 are sectional views showing an HEMT (High Electron Mobility Transistor) manufactured according to the invention in the order of manufacturing steps except for Fig. 2. As shown in Fig. 1A, an undoped GaAs layer 2 is formed on a semi-insulating GaAs substrate 1 by, e.g., an MBE method or an MOCVD method, to have a thickness of about 500 nm. An undoped GaAℓAs layer 3 is formed on the undoped GaAs layer 2 by, e.g., the MBE method or the MOCVD method, to have a thickness of about 5 nm. An n-type GaAℓAs layer 4 is formed on the undoped GaAℓAs layer 3 by, e.g., the MBE method or the MOCVD method, to have a thickness of about 80 nm. An n-type GaAs layer 5 is formed on the n-type GaAℓAs layer 4 by, e.g., the MBE method or the MOCVD method, to have a thickness of about 100 nm. The n-type GaAs layer 5 is an ohmic region, and the n-type GaAℓAs layer 4 is an electron supply layer. Since the undoped GaAℓAs layer 3 is formed to obtain excellent characteristics of the HEMT, it is not necessarily formed. The undoped GaAs layer 2 is formed to obtain a heterojunction between the undoped GaAs layer 2 and the undoped GaAℓAs layer 3 or between the undoped GaAs layer 2 and the n-type GaAℓAs layer 4. In this case, a two-dimensional electron channel is formed near the interface of the heterojunction. Thus, the n-type GaAs layer 5, the n-type GaAℓAs layer 4, and the undoped GaAs layer 2 constitute the active layer of the HEMT. As shown in Fig. 1B, mesa etching is performed by a known method to isolate an element region 6. Reference numeral 7 in Fig. 1B denotes a portion where the mesa etching is performed. As shown in Fig. 1C, a photoresist 8 is coated on the entire surface of the resultant structure, and the photoresist is removed from the element region 6 using a photoetching method. A metal such as AuGe which can form ohmic contact with an n-type GaAs is formed on the entire surface of the resultant structure by, e.g., a sputter method to have a thickness of about 200 nm. A film made of, e.g., Au or Pt, is formed by, e.g., the sputter method to have a thickness of about 200 nm, and an ohmic metal layer 9 consisting of a stacked film made of AuGe and Au or made of AuGe and Pt. As shown in Fig. 1D, the ohmic contact layer 9 is removed together with the photoresist 8 (a selective removing process using a lift-off technique). A photoresist 10 is coated on the entire surface, and an opening 11 is formed in the photoresist 10 using a photoetching method. For example, the size of the opening 11 has a width W = 2.5 µm. As shown in Fig. 1E, the ohmic metal layer 9 is selectively removed using the photoresist 10 as a mask by using, e.g., ion milling. As shown in Fig. 1F, the n-type GaAs layer 5 is selectively removed using the photoresist 10 as a mask by an RIE method serving as anisotropic etching. Subsequently, the n-type GaAℓAs layer 4 is partially removed to have a thickness of about 50 nm from the n-type GaAℓAs layer 4 having the thickness of about 80 nm. Thus, a groove 12 for constituting a recess structure is formed. A depth D from the ohmic metal layer 9 of the groove 12 is about 350 nm. The step shown in Fig. 1F may be performed by not only an RIE method but the ion milling which is used in the step shown in Fig. 1E. In consideration of damage to the n-type GaAs layer 5 and the n-type GaAℓAs layer 4, the RIE method which has the damage to these layers smaller than that of the ion milling is desirable. Although the RIE method is used, the n-type GaAs layer 5 and the n-type GaAℓAs layer 4 are slightly damaged. Therefore, in order to remove the damaged semiconductor surface, after the RIE process described in Fig. 1F, wet etching is performed using a solution mixture or PH 3 + H 2 O 2 + H 2 O to lightly remove the exposed surfaces (damaged surface) of the n-type GaAs layer 5 and the n-type GaAℓAs layer 4. As another method of removing the damaged surface which is not claimed, after the RIE process, the photoresist 10 is removed, and annealing is performed at a temperature of, e.g., 300°C, for 10 minutes, thereby correcting the damage surface. As shown in Fig. 1G, a plasma CVD oxide film 13 is formed on the entire surface of the resultant structure by, e.g., a plasma CVD method. As shown in Fig. 1H, the plasma CVD oxide film 13 is etched back by an RIE method. Thus, the side wall insulating film 13 (to be referred to as a side wall 13 as needed, hereinafter) consisting of the plasma CVD oxide film along the side wall of the groove 12 is formed. Note that n-type GaAℓAs layer 4 is exposed at the bottom portion of the groove 12, and the exposed surface is represented by reference numeral 14. After the step shown in Fig. 1H, in order to remove the damaged surface, the exposed surface 14 (damaged surface) of the n-type GaAℓAs layer 4 at the bottom portion of the groove 12 is lightly wet-etched using the plasma CVD oxide film 13 as a mask, as shown in Fig. 2. In Fig. 2, the portion where the exposed portion is lightly removed is shown in a circle 15. In addition, in order to eliminate the damage, the above annealing may be performed to correct the damage. As shown in Fig. 1I, a metal film made of, e.g., Ti, which can form a Schottky contact with an n-type GaAℓAs is formed on the entire surface by, e.g., a sputter method. Subsequently, an Aℓ film is formed by, e.g., a sputter method, to form a Schottky metal layer 16 consisting of a stacked film made of Ti and Aℓ. The Schottky metal layer 16 may be formed by stacked films consisting of three films respectively made of Ti, Pt, and Aℓ. A photoresist 17 is coated on the entire surface, and a pattern for forming a gate electrode, a source electrode, and a drain electrode is formed on the metal layer 16. As shown in Fig. 1J, the Schottky metal layer 16 is removed using the photoresist 17 as a mask by, e.g., ion milling. Thus, a source electrode 16 1 , a gate electrode 16 2 , and a drain electrode 16 3 are formed. The source electrode 16 1 and the drain electrode 16 3 are electrically integrated with the ohmic metal layer 9 under these electrodes. According to the above method, an HEMT is formed. According to the above manufacturing method, the gate electrode 16 2 can be formed to be self-aligned to the source electrode 16 1 (which is electrically integrated with the ohmic metal layer 9) and the drain electrode 16 3 (which is electrically integrated with the ohmic metal layer 9). As a result, distances between the gate and drain electrodes 16 2 and 16 3 and between the gate and source electrodes 16 2 and 16 1 are constant, and variations in characteristics are decreased in each of the formed HEMTs. In addition, a yield of production can be increased. Fig. 3 is an enlarged view showing a portion near the groove 12 of the HEMT shown in Fig. 1J. The same reference numerals in Fig. 3 denote the same parts as in Fig. 1J. As shown in Fig. 3, the groove 12 for obtaining a recess structure is formed to have a side surface almost perpendicular to the GaAs substrate 1. A side wall consisting of the plasma CVD oxide film 13 is formed along the side surface. The gate electrode 16 2 is formed to be in contact with the exposed surface or the side wall 13. In a conventional HEMT, the above groove is formed by wet etching (isotropic etching), and the side surfaces of the groove are tapered. This tapered portion prevents micropatterning in the horizontal direction. In addition, the method of forming the gate electrode prevents the micropatterning in the horizontal direction by using a photoetching method such as a lift-off technique. In the HEMT shown in Fig. 3, since the groove 12 is formed almost perpendicularly to the GaAs substrate 1, the micropatterning in the horizontal direction can be easily obtained. As described above, since the gate electrode is formed to be self-aligned to the source/drain electrodes, the micropatterning in the horizontal direction can be further easily obtained. In addition, since the taper included in the conventional HEMT is formed in a semiconductor layer constituting the source/drain regions, a transitional change in the source/drain regions is caused. At the taper bottom, the thickness of the above semiconductor layer is necessarily decreased, and a parasitic high-resistance region appears. In the HEMT shown in Fig. 3, since no taper is formed, a transitional change in resistance of the n-type GaAs layer 5 or the n-type GaAℓAs layer 4 constituting the source/drain regions is small, and a parasitic high-resistance region is not formed. As described above, micropatterning can be easily obtained, and a high power gain and a high-speed operation can be obtained. Since the groove 12 is formed by anisotropic dry etching represented by an RIE method or ion milling, a groove having a depth larger than that obtained by wet etching can be formed. This is because a pattern of a photoresist is hard to be deformed due to the dry etching. Therefore, a thickness t of the GaAs layer 5 can be increased, and the resistance of the GaAs layer 5 can be reduced. For example, although the maximum thickness t = 50 nm is obtained by conventional wet etching, the thickness t = 100 nm or more can be obtained in the above manufacturing method. As described above, in an HEMT manufactured according to the present invention, especially a contact resistance of the source/drain regions can be further decreased, and a large transconductance gm can be obtained. As a result, according to the present invention, a high-performance HEMT capable of obtaining a large power gain, a small noise index, and a high S/N ratio can be obtained. A major source resistance Rs and a major drain resistance Rd in the n-type GaAℓAs layer 4 can be exactly controlled by variously changing the width w of the side wall 13. It is proved that the controllability for the width w is highly accurate at a present manufacturing level, and a change in resistance is small due to a change in the width w . Therefore, the transconductance gm can be appropriate to a breakdown voltage or the like with high accuracy. For example, when the groove 12 has a width W = about 2.5 µm and a depth D = about 350 µm, the thickness of the side wall 13 is controlled to be about 1.0 µm. Since the gate electrode 16 2 is in contact with the exposing surface of the side wall 13 and formed to fall in the groove 12, a positioning error of the gate electrode does not occur. Since the groove 12 is formed such that its bottom is narrow by the side wall 13, a thickness T G of the gate electrode 16 2 can be formed to be large. When a width W G of the gate electrode 16 2 is sufficiently large by a lithographic process, the thickness T G and the width W G can be increased, thereby decreasing the gate resistance. From this point, a high-speed operating HEMT especially having an excellent high-frequency response can be obtained. This gate electrode 16 2 , the source electrode 16 1 , and the drain electrode 16 3 are formed by etching the Schottky metal layer 16 using ion milling in the above manufacturing method. Figs. 4A to 4F are sectional views showing a MESFET in order of the manufacturing steps and not claimed. As shown in Fig. 4A, a buffer layer (not shown, which is not necessarily formed) and an active layer 52 are formed on a semi-insulating GaAs substrate 51. An ohmic metal layer 53 which is a three-layered film consisting of, e.g., an AuGe film having a thickness of 200 nm, an Ni film having a thickness of 30 nm, and an Au film having a thickness of 800 nm is formed on the active layer 52. A plasma SiON film 54 is formed on the ohmic metal layer 53. As shown in Fig. 4B, the plasma SiON film 54 and the ohmic metal layer 53 are anisotropically dry-etched using ion milling to form a source electrode portion 55 1 consisting of a source electrode 53 1 and a plasma SiON film 54 1 which is formed thereon and a drain electrode portion 55 2 consisting of a drain electrode 53 2 and a plasma SiON film 54 2 which is formed thereon. Thereafter, annealing (at a temperature of 430°C for 5 minutes) is performed to improve ohmic characteristics. Undesired portions are removed to isolate elements from each other (mesa etching). As shown in Fig. 4C, a plasma SiON film is formed to have a thickness of about 500 nm, and the plasma SiON film is anisotropically etched by an RIE method to form side wall insulating films 56 on the side walls of the electrode portions 55 1 and 55 2 . As shown in Fig. 4D, a groove 57 is formed in the active layer 52 between the electrode portions 55 1 and 55 2 using the side wall insulating films 56 as masks (recess etching). As shown in Fig. 4E, a photoresist (not shown) is coated on the resultant structure, and an opening is formed between the electrode portions 55 1 and 55 2 by a photoetching method. A gate metal layer which is a three-layered film consisting of, e.g., a Ti film having a thickness of 100 nm, a Pt film having a thickness of 50 nm, and an Au film having a thickness of 500 nm is formed. The gate metal layer is removed together with the photoresist (not shown) to obtain a gate electrode 58 (a lift-off technique). As shown in Fig. 4F, a plasma SiN film 59 is formed as an insulating interlayer, and a through hole reaching the source electrode 53 1 , the drain electrode 53 2 , and the like is formed in the plasma SiN film 59. A pad metal layer which is a three-layered film consisting of, e.g., a Ti film having a thickness of 100 nm, a Pt film having a thickness of 50 nm, and an Au film having a thickness of 800 nm is formed. The pad metal layer is patterned to form a source wiring 60 1 and a drain wiring 60 2 . According to the above method, another MESFET is formed. According to the other MESFET obtained by the above manufacturing method, the following effect can be obtained. In the first point, assuming that an interval between the source electrode 53 1 and the drain electrode 53 2 is set to be, e.g., 1.5 µm and that the width of the side wall insulating film 56 is set to be, e.g., 0.5 µm a fine element in which a distance between the source electrode 53 1 and the gate electrode 58 is set to be 0.5 µm, a distance between the drain electrode 53 2 and the gate electrode 58 is set to be 0.5 µm, and a gate length is set to be 0.5 µm can be uniformly formed at a high yield. This is because the side wall insulating films 56 are formed on both the side walls of the source electrode 53 1 and the drain electrode 53 2 and the gate electrode 58 is formed to be self-aligned to the source electrode 53 1 and the drain electrode 53 2 by using the side wall insulating films 56. As a result, variations in distances between the gate and source electrodes and between the gate and drain electrodes are eliminated, and variations in breakdown voltage of the element and variations in source resistance which influences high-frequency characteristics are relieved. In the second point, even when an interval between the source electrode 53 1 and the drain electrode 53 2 is further decreased, since the plasma SiON films 54 1 and 54 2 serving as insulating films are respectively formed on the source electrode 53 1 and the drain electrode 53 2 , the gate electrode 58 is not short-circuited with the source electrode 53 1 and the drain electrode 53 2 . When the distances between the source and gate electrodes and between the gate and drain electrodes are decreased, although high-frequency characteristics in the element are improved, the source or drain electrode is easily short-circuited with the gate electrode, thereby decreasing a yield. According to this method this disadvantage can be improved, and elements each having excellent high-frequency characteristics can be manufactured. In the third point, since the groove 57 for forming a recess structure can be formed using the side wall insulating film 56 as a mask, the probability of formation of the groove 57 can be increased. This is because, e.g., a plasma SiON film (the side wall insulating film 56) having a higher adhesion strength with an underlying region such as a substrate or an electrode than that of a photoresist or the like is used as a mask. Pattern crush caused by removing the underlying from the photoresist is hard to occur. Therefore, a probability of forming the groove 57 is increased, and an increase in yield can be realized. Fig. 5 is a sectional view showing an HEMT formed by the manufacturing method as described above. The reference numerals in Fig. 5 denote the same parts as in Fig. 4, and only the different parts will be described below. As shown in Fig. 5, in order to form the HEMT, an undoped GaAs layer 61 having a thickness of, e.g.; 1 µm, an undoped Ga 0.7 Aℓ 0.3 As layer 62 having a thickness of 5 nm, and an n-type Ga 0.7 Aℓ 0.3 As layer 63 having a thickness of 30 nm are sequentially formed on a semi-insulating GaAs substrate 51 in place of the active layer. Thereafter, an n-type GaAs layer 64 is formed as a source/drain. The following steps are the same as the steps described with reference to Figs. 4A to 4F. As described above, according to the present invention, an HEMT is exemplified. However, the present invention is not limited to the HEMT and can be generally applied to semiconductor devices.

Claims: A method of manufacturing a semiconductor device, comprising the steps of: forming an active layer (2, 4, 5) on a semiconductor substrate (1); etching a mesa thereon to isolate an element region (6); coating the entire surface of the resultant structure with a first photoresist (8); removing said first photoresist (8) from said element region (6) by photoetching; forming a first metal layer (9) on the entire surface of the resultant structure, said first metal layer (9) providing an ohmic contact with said active layer (2, 4, 5); removing said first metal layer (9) except from on said element region (6), together with said photoresist (8) using a selective lift-off technique; coating the entire surface of the resultant structure with a second photoresist (10); forming an opening (11) in the second photoresist (10) on said element region (6) by photoetching; using said second photoresist (10) as a mask to selectively remove the exposed portion of the first metal layer (9); forming a groove (12) in a portion of said active layer (2, 4, 5) through said opening (11) using reactive ion etching or ion milling; wet-etching a surface of said groove (12); removing said second photoresist (10); forming an insulating layer (13) on the entire surface of the resultant structure; subjecting said insulating layer (13) to reactive ion etching in order to remove said insulating layer (13), except from on the side walls of said groove (12) and on the corresponding side walls of said first metal layer (9), thus exposing the bottom of said groove (12); wet-etching said bottom (15) of said groove (12); forming a second metal layer (16) on the entire surface of the resultant structure, said second metal layer (16) forming a Schottky-contact with said active layer (2, 4, 5) in the groove; forming a mask pattern from a third photoresist (17) on said second metal layer (16); and etching said second metal layer (16) in order to form a gate electrode (16-2) in the groove (12) and source and drain electrodes (16-1, 16-3) on respective portions of the first metal layer (9).

Inventors: FUKUDA TOSHIKAZU, IMAMURA SOUICHI, KISHITA YOSHIHIRO, OCHI MASANORI, FUKUDA, TOSHIKAZU, IMAMURA, SOUICHI, KISHITA, YOSHIHIRO, OCHI, MASANORI, FUKUDA, TOSHIKAZU, INTELLECT. PROPERTY DIV., IMAMURA, SOUICHI, C/O INTELLECT.PROP. DIVISION, KISHITA, YOSHIHIRO, C/O INTELLECT.PROP. DIV., OCHI, MASANORI, C/O INTELLECT. PROP. DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: H01L21
IPC codes: H01L29, H01L21