A biCMOS process with low base recombination current bipolar transistors

Abstract: A process for manufacturing an integrated circuit having both field effect and bipolar transistors provides, in one embodiment, a polycide film over the gate and field oxides on the surface of the semiconductor substrate. The process then patterns the polycide film such that a protective structure of gate material is formed on top of the base region of the bipolar transistor while the gate of the field effect transistor is formed, in a single process step. The channel region of the field effect transistor is defined by the gate, which also serves as a mask for etching away the gate oxide from the source and drain regions of the filed effect transistor. Ionic species are implanted to form the source and drain of the field effect transistor and the collector contact of the bipolar transistor. The protective structure of gate material in the active region of the bipolar transistor is removed just before the base region is implanted with ionic species to form the base of the bipolar transistor. A polysilicon or polycide film provides the emitter of the bipolar transistor.

Description: This invention pertains to the field of semiconductor integrated circuit (IC) fabrication, and in particular, to the field of semiconductor IC fabrication involving bipolar-complementary metal-oxide-semiconductor (BiCMOS) circuits. As is well known in the art, CMOS transistors, including both PMOS (p-channel metal-oxide-semiconductor) and NMOS (n-channel metal-oxide-semiconductor) transistors, and bipolar transistors are fabricated on the same substrate in a BiCMOS process. Discussions of the BiCMOS technology and device characteristics may be found in (i) an article entitled "Advanced BiCMOS Technology for High Speed VLSI" by T. Ikeda et al., IEDM technical digest, International Electron Devices Meeting, Los Angeles, December 7-10, 1986, pp.1 408-411, and (ii) an article entitled "A Production Proven High Performance 1.0 µm Double-level Polysilicon BiCMOS Technology" by P. Tong et al., Semiconductor Technical Journal, vol. 5, No. 1, 1990, pp. 106-112. The patent abstract "Manufacture of Semiconductor Device", Patent Abstracts of Japan, Vol. 12, No. 393, 19 October 1988, and JP-A-63 133 662, discloses process steps in a BiCMOS, showing the structures of the bipolar transistors and field effect transistors on a common semiconductor substrate. European Patent Application EP-A-0226892 A2 discloses a BiCMOS structure including NMOS, PMOS and bipolar transistors fabricated on a common semiconductor substrate. A process for fabricating BiCMOS integrated circuits is shown in Fig. 1. Figure 1a shows a semiconductor structure being fabricated in a BiCMOS process, at the step after a pattern of the photoresist layer 103 is developed in preparation for etching the immediately underlying polycide layer 104. The polycide layer 104 can be, for example, a tungsten silicide/polysilicon stack. The structure carved out of the polycide layer 104 by the etching step forms the gate of an NMOS transistor. As shown in Figure 1a, the regions 100 and 101 are, respectively, regions in which a bipolar transistor and a NMOS transistor are to be fabricated. Region 100 includes an n-type buried layer 108 underneath an N-well 110, which included a collector plug region 109. Region 101 includes a p-type buried layer 107 beneath a P-well 106. On the wafer surface, on top of both P-well 106 and N-well 110, is shown an oxide layer, which includes gate oxide 105a and field oxide 105b regions. A polycide layer 104 is formed on top of the oxide layers 105a and 105b. In the process shown, the polycide layer 104 comprises tungsten silicide on top of a phosphorus-doped polysilicon. Figure 1b shows the semiconductor structure after a selective etch of polycide layer 104 to form the gate of the NMOS transistor, and removal of photoresist layer 103. An annealing step for the polycide gate 104 is then performed, which is followed by the deposition of a layer 111 of low temperature oxide (Figure 1c). This low temperature oxide layer 111 is then anisotropically etched to leave portions llla and 111b (Figure 1d), called oxide spacers, on the sidewalls of the polycide gate 104. Generally, the oxide layer 111 is overetched in forming spacers 111a and 111b, in order to achieve across the wafer uniform junction depth and sheet resistivity at the MOS transistors' source and drain regions. Uniformity in these regions is important because the implant range of the dopant species, such as arsenic or boron difluoride, is sensitive to the oxide thickness left on top of the active regions after the spacer etch. A uniform junction depth and sheet resistivity is necessary to manufacture devices which actual electrical characteristics are closer to the predicted values used in their design. Photoresist layer 112 is then applied and patterned for implanting p-type ionic species in the bipolar region 100 to form the base 113 of a bipolar transistor (Figure 1e). During this step, an ionic species such as boron is implanted into the bare silicon surface exposed after the spacer etch. This implant step may cause "channeling", if no special precaution is taken. Channeling occurs when atoms of an implanted species are introduced into the crystal lattice at such an angle that they are met with little resistance in the interatomic space until they reach a great depth. This effect causes a small but significant impurity concentration deep into the implanted surface called the "channeling tail." The channeling tail is a major obstacle to achieving small base width desirable in advanced bipolar devices. One method to alleviate the channeling effect is to implant the ionic species at an angle to the lattice structure, such as 7 degrees from the normal of the surface of implant. Such off-axis implants, however, cause other device performance problems because of the non-uniform concentration over the surface due to "shadows" cast by other structures on the semiconductor surface, affecting adversely device characteristics to cause such effects as perimeter-punch through and tunnelling leakage currents. Examples of effects can be found in "Effect of off-axis Implant on the characteristics of Advanced Self-aligned Bipolar Transistors," by C.T. Chuang et al., IEEE Electron Device Letters, Vol. EDL-8, No. 7, July, 1987, pp. 321-23. After the base implant step, and having stripped off photoresist 112, a new photoresist layer 114 is deposited and patterned to open the collector contact 114c inside the collector plug region 109 of the bipolar transistor in bipolar region 100. The source 114a and drain 114b regions of the NMOS transistor in region 101 are also exposed at this step. The exposed regions are then implanted with n-type ionic species (Figure 1f). After an oxygen plasma cleaning step (commonly known as ashing) is applied to remove photoresist 114, the base contact areas 116a and 116b of the bipolar transistor, and the source and drain regions of the PMOS transistor (not shown) are formed by suitably patterning on the photoresist layer 115 and implanting with p-type ionic species (Figure 1g). After stripping off photoresist layer 115, a blanket layer of low temperature oxide 117b is deposited over the entire surface, including the electronic-states rich bare silicon base region 113. This low temperature oxide layer is then patterned and selectively etched to form a contact region for use with a second film of polysilicon (see below), e.g. the emitter contact 117a shown. A second polysilicon film ("POLY II") is then deposited. Thereafter, a layer of photoresist is deposited over this POLY II layer, and is suitably patterned in accordance with a POLY II mask and etched to define second polysilicon features, including the emitter of the Bipolar transistor 117 in bipolar region 100. The remaining portions of the POLY II layer are overlaid by a layer of photoresist which is suitably patterned and developed in accordance with a POLY II implant mask to expose conductive sections for ion implant. Such regions for ion implant include prospective emitter regions in the remaining portions of the POLY II layer. A POLY II implant is then made using an n-type dopant. The photoresist layer which defines the exposed POLY II features is then removed. The implanted n-type dopant in the POLY II features is driven into the base region 113 through the emitter contact 117a by an oxidation cycle. The surface of the wafer is then provided with a layer of undoped oxide, followed by and a layer of Boro-Phospho-Silicate glass (BPSG) 119, which is patterned and selectively etched to allow the circuit elements to be interconnected by one or more layers of metallization 118 insulated by intermetal dielectric layer 120. The entire surface is then passivated by a passivation layer 121. The completed semiconductor structure is shown in Figure 1h. In the BiCMOS process just described, the finished bipolar transistors are prone to excessive emitter-base junction recombination currents. Such currents are observed in a special case study "Increased Current Gain and Suppression of Peripheral Base Currents in Silicided Self-Aligned Narrow-Width Polysilicon-Emitter Transistors of an Advanced BiCMOS Technology" IEEE Electron Device Letters, vol. EDL-9, No. 5, pp. 247-49, May 1988, by M.H. El-Diwany et al., in a different context. To prevent damage to the bipolar active region, the oxide spacer etching step has been designed to leave a suitable thickness (e.g. 150 angstroms) of oxide on top of the active regions. However, this approach causes undesirable varying CMOS device performance because of (1) the inherent variations in thickness of the oxide layer 111 (which forms the oxide spacers 111a and 111b), and (ii) the selectivity of the etch and the non-uniformity caused by the oxide etcher. The major contribution is observed to stem from the configuration of the oxide etcher, which etches at different rates at the centre of the wafer and at the edge of the wafer. Typically, across the wafer, variations of up to 350 Å (1Å = 10 -10 m) can result. According to the present invention there is provided a process of manufacturing field effect and bipolar transistors in respective active areas of a semiconductor substrate, comprising the steps of: forming a layer of gate oxide over the surface of said semiconductor substrate including said active areas; forming a conductive layer of gate material on said gate oxide over said field effect transistor active area and said bipolar transistor active area; forming from said layer of gate material a gate over a first region of said field effect transistor active area, and a protective structure over said bipolar transistor active area; implanting a dopant into source and drain regions in said field effect transistor active area, proximate to said first region, said protective structure being intact over said bipolar transistor active area during said drain and source implant step; removing said layer of gate oxide from said surface of said semiconductor substrate not protected by said gate and said protective structure; and removing said protective structure. In accordance with one embodiment of the present invention, a process for manufacturing semiconductor structure of BiCMOS circuits achieves low base recombination current in the bipolar transistor by forming from gate material a protective structure over a bipolar transistor active area. Source and drain regions are formed in the field effect transistor active area while the protective structure over the bipolar transistor active area remains intact, thereby shielding the base region from the harsh processing steps associated with the formation of the field effect transistors (e.g. the spacer etch step). In addition to facilitating the fabrication of bipolar transistors having reduced base recombination current, the present invention also decouples the process-related performance parameters of the bipolar and CMOS transistors. A process in accordance with the present invention provides base active regions which are protected from particle contamination at the LTO deposition step, and prevents plasma damage at the ashing and resist-strip steps following the NMOS transistor source-drain implantation step. A further advantage of the present invention is the avoidance of boron channeling during the base implant step. The present invention will be better understood after consideration of the following detailed description in conjunction with the accompanying drawings. Figures 1a-h show various steps of a process in the prior art. Figures 2a-j show various steps in an embodiment of the present invention. In this description, the areas in which the channels, sources and drains of MOS transistors, and the base-emitter and base-collector junctions of bipolar transistors are formed will b respectively referred to as the active areas of the field effect transistors, and the active areas of the bipolar transistors. Such active areas may be formed in a substrate of silicon or other suitable semiconductor, in epitaxial silicon, or in any other material suitable for the formation of semiconductor devices. It has been observed that the anisotropical overetching of the low temperature oxide layer to form the oxide spacers on the sidewalls of the polycide gate of a MOS field effect transistor can actually etch into the active regions. This over-etching step is believed to create surface states underneath the low temperature oxide similar to those electronic states located in bare silicon. These surfaces states can significantly increase the forward-biase emitter-base junction recombination current, resulting in degradation of the current gain ("beta") in the finished bipolar transistor, and are detrimental to bipolar device reliability. The present invention alleviates the enhanced recombination current problem due to surface states in the bipolar transistor. The steps of a first embodiment of the present invention are illustrated in Figure 2a-j. Figure 2a shows a BiCMOS semiconductor structure at an early stage of fabrication. The regions 200 and 201 are, respectively, regions of a semiconductor wafer in which a bipolar transistor and a NMOS transistor are to be formed. (Henceforth, region 200 is referred to as the bipolar region 200, and region 201 is referred to as NMOS region 201). The PMOS transistor is not shown in this figure. Bipolar region 200 includes an n-type buried layer 208 underneath an N-well 210, which included a collector plug region 209. Likewise, NMOS region 201 includes a p-type buried layer 207 beneath a P-well 206. On top of both P-well 206 and N-well 210 is formed in any suitable manner an oxide layer, which includes gate oxide 205a and field oxide 205b regions. The gate oxide and the field oxide layers are typically formed in separate fabrication steps. Gate oxide layer 205a and field oxide layer 205b are also often of different qualities. A polycide layer 204, which is the material used to form the gates of the NMOS and PMOS transistor, is provided on top of the oxide layers 205a and 205b. This polycide layer 204 comprises tungsten silicide and phosphorus-doped polysilicon. This polycide layer 204 is formed by a first deposit of a polysilicon film about 3000Å thick using any suitable deposition equipment, such as a LPCVD tube available from Thermco Corporation, California, at a deposition temperature of 615°C. The polysilicon film is doped to 24 ohms/square using any suitable equipment, such as a POCl 3 tube, also available from Thermco Corporation. Following deglaze and sulfuric acid clean steps, a film of tungsten silicide about 2000Å thick is deposited using any suitable equipment, such as Model #8402 CVD reactor available from Genus Corporation, Mountain View, California. The combination of the phosphorous doped polysilicon and tungsten silicide is collectively referred to as the polycide layer 204. Materials other than polycide, such as molybdenum, may also be used to form the gates of NMOS and PMOS transistors. A polycide mask 203 is formed from a patterned photoresist layer 203. Polycide mask 203 not only masks the gate region of the NMOS transistor in NMOS region 201 and generally the gate regions of other field effect transistors, but also masks the active regions of the bipolar transistor in bipolar region 200, and generally the active regions of other bipolar transistors. Polycide layer 204 is selectively etched to leave the gate 204a of the NMOS transistor in NMOS region 201 and a protective structure 204b atop the active region of the bipolar transistor in bipolar region 200 (Figure 2b). The gate of any PMOS transistor (not shown) is also formed at this step. After an annealing step for the remaining polycide structures (e.g. gate 204a and protective structure 204b), a low temperature oxide (LTO) layer 211 about 3000Å thick is deposited in any suitable manner, such as using a CVD reactor obtainable from Anicon Inc., San Jose, California. (Figure 2c). As can be readily seen in Figure 2c, the protective structure 204b separates the LTO layer 211 from the active region of the bipolar region 200. Because gate oxide 205a covers the surface of the bipolar active region 200, this surface is naturally passivated by this layer of thermally grown gate oxide 205a, resulting in reduced density of electronic traps at the silicon surface. During the LTO deposition step, the active region of bipolar region 200 is protected by the protective structure 204b from particle contamination. The material forming the protective structure 204b over the base region of the bipolar transistor may be any material suitable to form the gates of field effect transistors. The choice of material is primarily determined by the requirements of the field effect transistors. For example, pure tungsten is not suitable because of its susceptibility to channeling effects during the ion implant steps such as used to form the sources and drains of the field effect transistors. Channeling results in contamination by the implanted ionic species in the channel region of the transistor, thus affecting its operational characteristics. As mentioned above, since the gate material is chosen for the protective structure 204b over the bipolar transistor active region 200, the surface of the bipolar region is naturally passivated by the layer of thermally grown gate oxide 205a. Such passivation markedly reduces the density of electronic traps at the silicon surface in the base region to result in a more stable bipolar transistor having electrical characteristics closer to an ideal bipolar transistor. E.H. Nicollian et al. discussed this effect in "MOS (Metal Oxide Semiconductor) Physics & Technology" John Wiley & Sons, New York, 1982, pp. 756-759. This LTO layer 211 is then anisotropically etched using, for example, an AMT8310 RIE plasma etcher available from Applied Materials, Inc. of Santa Clara, California, to form both oxide spacers 211a and 211b on the sidewalls of gate 204a, and oxide spacers 211c and 211d on the sidewalls of protective structure 204b. Because of the inherent variation of oxide thickness across the wafer, the selectivity of the reactive ions used to perform the etching, and the configuration of the etcher, which tends to etch in different etch rates at the center and at the edge of the wafer, it is difficult to precisely control the thickness of oxide throughout the wafer. Variation of up to 350Å is seen from a center location on the wafer to the edge of the wafer. However, because protective structure 204b provides a barrier between the LTO layer 211 and the underlying thermally grown gate oxide 205a, which passivates the silicon surface of the base region in bipolar region 200, the LTO layer 211 atop the active regions of the field effect transistors, such as in NMOS region 201, may be etched to substantial completeness (Figure 2d). without any deleterious effect on gate oxide layer 205a and introducing defects in the bipolar region 200, thereby avoiding excessive base recombination current in the finished bipolar transistor. The present invention thus makes unnecessary the requirement of leaving a precisely controlled thickness of oxide on top of the active regions to avoid damage to the base region of the bipolar transistor. At the same time, the removal of substantially all oxide from the active region of the field effect transistors results in uniform and controllable electrical characteristics in the field effect transistors and resistors formed by the same source/drain implants. Photoresist layer 213 is deposited and patterned to form openings for n-type ion implant in the collector contact 212c inside the collect plug region 209 of the bipolar region 200, and source and drain regions 212a and 212b of NMOS region 201 (Figure 2e). The n-type ionic species used for this implant can be phosphorous, arsenic, or both. If both arsenic and phosphorous are used, suitable implant doses are 8.0x10 15 at 65 KeV and 1.5 x 10 14 at 65 KeV respectively. The photoresist layer 213 is removed by an ashing step using oxygen plasma, followed by a resist-strip step, using a reagent commonly known as "piranha" solution. During the ashing and resist-strip steps, protective structure 204b shields the passivated active area of bipolar region 200. Photoresist layer 214 is then deposited and patterned to form openings for ion implant in the active area of bipolar region 200 (Figure 2f). A wet etch step, called a buffered oxide etch, using a 7:1 (by volume) solution of HF and ammonium fluoride at 30°C, removes the oxide spacer structures 211c and 211d from the sidewalls of the protective structure 204b (Figure 2g). After the buffered oxide etch, a polycide etch, using any suitable plasma etcher, such as LAM model 490 available from LAM Research Corporation, Fremont, California, removes the protective structure 204b to expose the gate oxide 205a atop the active area of bipolar region 200. The wet etching step to remove the oxide spacers 211c and 211d improves planarity, but oxide spacers 211c and 211d may be left in place if desired. Improved planarity prevents breakage in metal interconnect, which may happen if the BPSG layer in a subsequent step is too thinly deposited. The polycide etch step is allowed up to 15% overetch to ensure complete removal of the polycide protective structure 204b. P-type ions are then implanted into the gate oxide 205a atop the active region of bipolar region 200. The implanted ions, such as boron, penetrate the silicon under gate oxide 205a to form the base 215 of the bipolar transistor in bipolar region 200 (Figure 2h). Because the boron ions are implanted through an oxide layer 205a, which is preserved by the protective structure 204b, the channeling tail effect associated with a boron-bare silicon implant is avoided, since channeling does not occur in an oxide layer. As a result, very narrow base width necessary for high bipolar transistor performance is achieved. Furthermore, the gate oxide layer 205a serves to passivate the surface of the base active area by eliminating the formation of trap sites and dangling bonds on the silicon surface. This passivation effect enhances reliability in the bipolar transistor. After photoresist layer 214 is removed by ashing and resist-strip steps, using suitable reagents such as oxygen plasma and sulfuric acid respectively, photoresist layer 217 is provided and patterned to make openings for ion implant in the base contact areas 216a and 216b (Figure 2i) of the bipolar transistor, and the source and drain regions of PMOS transistors (not shown). One suitable ionic species for forming source and drain regions of PMOS transistors is boron difluoride (BF 2 ), using an implant dose of 3.0 x 10 15 at 45 KeV. After stripping off photoresist layer 217, a 2000Å thick low temperature oxide (LTO) layer 224 is deposited by any suitable method for low temperature oxide deposition, such as a CVD reactor from Anicon Inc., San Jose, California. This low temperature oxide layer 224 is then patterned and then selectively etched to form contact regions for a second layer of polysilicon ("Poly II"). Such contact regions include emitter contact region 217a. A patterned second layer 218 of polycide or polysilicon provides the emitter of the bipolar transistor (Figure 2j). The emitter is formed as the n-type dopant, such as arsenic, in the polysilicon diffuses into the silicon surface underneath. The surface of the wafer is then provided with a layer 220 of Boro-Phospho-Silicate glass (BPSG) which is patterned and selectively etched to allow the circuit elements to be interconnected by one or more layers of metallization 219 insulated by intermetal dielectric layer 221. This dielectric layer 221 comprises a low temperature oxide (LTO) of about 15500Å thick, deposited by a suitable apparatus, such as the ACVD reactor obtainable from Anicon Inc. discussed earlier. Planarization of this dielectric surface is achieved by etching back the LTO layer 221 until 17500Å of oxide remains in the field regions. The etch back step is followed by deposition of a film of undoped plasma oxide, about 8000Å thick, using a suitable apparatus, such as the Concept One (Trademark) reactor, obtainable from Novellus Systems, Inc. of San Jose, California. Both via and a second layer of metal can be suitably patterned to provide extra interconnections, as is well known in the art. The entire surface is then passivated by a passivation layer 222. Passivation layer 222 may be any suitable passivation layer, such as a deposited film of polysilicon glass of about 6000 Å thick, followed by a similarly thick nitride. Both films can be deposited by the Novellus reactor discussed earlier in conjunction with the deposition of plasma oxide in dielectric layer 221. The completed semiconductor structure is shown in Figure 2j.

Claims: A process of manufacturing field effect and bipolar transistors in respective active areas of a semiconductor substrate, comprising the steps of: forming a layer of gate oxide (205a) over the surface of said semiconductor substrate including said active areas; forming a conductive layer of gate material (204) on said gate oxide over said field effect transistor active area and said bipolar transistor active area; forming from said layer of gate material (204) a gate (204a) over a first region of said field effect transistor active area, and a protective structure (204b) over said bipolar transistor active area; implanting a dopant into source and drain regions (212a, 212b) in said field effect transistor active area, proximate to said first region, said protective structure being intact over said bipolar transistor active area during said drain and source implant step; removing said layer of gate oxide (205a) from said surface of said semiconductor substrate not protected by said gate (204a) and said protective structure (204b); and removing said protective structure (204b). A process as in claim 1, wherein said conductive layer comprises a polysilicide film. A process as in claim 1, wherein said conductive layer comprises a doped polysilicon film. A process as claimed in any preceding claim, wherein said step of forming said gate (204a) and said protective structure (204b) is a single masking step. A process as claimed in any preceding claim, further comprising the steps of: forming a collector plug region (209) in said semiconductor substrate prior to said step of forming a layer of gate material; and implanting said dopant into said collector plug region (209) during said step of implanting source and drain regions, to form a collector contact region (212c). A process as claimed in any preceding claim, further comprising between said step of forming a gate (204a) and a protective structure (204b) and said step of implanting a dopant, the steps of: forming a layer of oxide (211) over the side of said substrate having said active areas of said field effect transistor and said bipolar transistor; and etching said oxide layer to leave oxide spacers (211a-211d) on the sides of said gate and said protective structure. A process as claimed in any preceding claim, wherein said field effect transistor is a NMOS transistor and said bipolar transistor is an NPN transistor, and wherein said dopant is an N-type dopant. A process as claimed in any preceding claim, wherein after said step of removing said protective structure, said method further comprises the steps of: implanting a dopant into said bipolar transistor active area (200) to form a base (215) of said bipolar transistor; and forming an emitter (218) of said bipolar transistor. A process as claimed in claim 8, wherein said field effect transistor is an NMOS transistor and said bipolar transistor is an NPN transistor, and wherein said source and drain implanting step comprises the step of implanting an N-type dopant, and said base implanting step comprises the step of implanting a p-type dopant. A process as claimed in claim 9, wherein said semiconductor substrate includes PMOS and NMOS field effect transistors, and wherein said base contact implanting step further comprises the step of implanting said P-type dopant into a PMOS transistor active area to form source and drain regions of said PMOS transistor.

Inventors: TONG PAUL C F, TONG, PAUL C.F.
Applicants: SAMSUNG SEMICONDUCTOR INC, SAMSUNG SEMICONDUCTOR, INC.
Application year: 1991
Main classification: H01L21
IPC codes: H01L21, H01L27