FET having U-shaped gate electrode

Abstract: According to this invention, in an element region (11) formed in a semiconductor substrate, a plurality of regions (13) for constituting one electrode of source and drain electrodes of an FET are formed. A gate electrode (12) is formed to surround the plurality or regions (13). The other electrode (14) of the FET is formed in the element region (11) except for the plurality of regions (13) surrounded by the gate electrode.

Description: The present invention relates to a semiconductor device having a FET and, more particularly, to improvement of an integration density of the semiconductor device. Fig. 1 is a plan view of a pattern showing a conventional MOSFET. In Fig. 1, reference numeral 10 denotes a field region. An element region 11 in which MOSFETs are formed is isolated by the field region 10. MOSFETs Q100 and Q102 are formed in the element region 11. Each of the MOSFETs Q100 and Q102 consists of a gate electrode 12, a source region 13, and a drain region 14. The source and drain regions 13 and 14 are formed on both sides of the gate electrode 12. As described above, in a conventional technique, the MOSFETs Q100 and Q102 are isolated from each other by the field region 10. For this reason, a ratio of an area required for the field region 10 to an area of a chip is necessarily increased, and a semiconductor device consisting of a plurality of MOSFETs cannot obtain a high integration density. Patent Abstracts of Japan, vol. 8, no. 53 and JP-A-58 207 677 disclose a semiconductor device comprising a U-shaped gate electrode, wherein it is the purpose to enable a pair of transistors to have uniform electric characteristics. Patent Abstracts of Japan, vol. 12, no. 375 and JP-A- 63 122 276 disclose a semiconductor device employing a U-shaped gate electrode. In the shown device the parallel portions of the U-shaped gate electrode and the field region end thereof surround one of the source and drains of a transistor which is surrounded by a U-shaped electrode. The invention has been made in consideration of the problem described in connection with Fig. 1, and has as its object to increase an integration density of a semiconductor device having a plurality of FETs and to provide a high-density semiconductor device. This object is solved by a semiconductor device as described by claim 1. The subclaims show further advantageous embodiments of the invention. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a plan view of a pattern showing a conventional MOSFET; Fig. 2 is a plan view of a pattern showing a MOSFET according to the first embodiment of the present invention; Fig. 3 is an equivalent circuit diagram showir the MOSFET in Fig. 2; Fig. 4 is a circuit diagram showing a sense amplifier (CMOS type); Fig. 5A is a plan view of a pattern showing an arrangement wherein the sense amplifier in Fig. 4 consists of MOSFETs according to the present invention and, more particularly, showing a pattern of an arrangement of a gate electrode; Fig. 5B is a plan view of a pattern showing an arrangement wherein the sense amplifier in Fig. 4 consists of MOSFETs according to the present invention, and showing a condition wherein the MOSFETs are connected to each other by wiring; Fig. 6 is a plan view of a pattern showing an arrangement wherein the sense amplifier in Fig. 4 consists of conventional MOSFETs; Fig. 7 is a plan view of a pattern showing a part extracted from Fig. 5B; Fig. 8 is a plan view of a pattern showing a MOSFET according to the second embodiment of the present invention; Fig. 9 is a plan view of a pattern showing a MOSFET according to the third embodiment of the present invention; Fig. 10 is a plan view of a pattern showing a MOSFET according to the fourth embodiment of the present invention; Fig. 11 is a plan view of a pattern showing a MOSFET according the fifth embodiment of the present invention; Figs. 12 to 14 are plan views of patterns showing MOSFETs according to modifications of the fifth embodiment of the present invention; Figs. 15 and 16 are plan views of a pattern showing a MOSFET according to the sixth embodiment of the present invention; Fig. 17 is a plan view of a pattern showing a MOSFET according to the seventh embodiment of the present invention; and Fig. 18 is a sectional view showing the MOSFET along a line 18 - 18 in Fig. 17. Embodiments of the present invention will be described below with reference to the accompanying drawings. [First Embodiment] Fig. 2 is a plan view of a pattern showing a MOSFET according to the first embodiment of the present invention, and Fig. 3 is an equivalent circuit diagram thereof. As shown in Fig. 2, MOSFETs Q10 and Q12 are formed in an element region 11 isolated by a field oxide region 10. Each of the gate electrodes 12 of the MOSFETs Q10 and Q12 has a U-shaped two-dimensional pattern, both the ends of the gate electrode 12 are formed to cover the field region 10, and the central portion of the gate electrode 12 is formed in the element region 11. A portion of the element region 11 is surrounded by the U-shaped gate electrode 12, and the surrounded portion 13 is used as one electrode (to be referred to as a drain electrode 13 hereinafter) of the MOSFET. The remaining region 14 of the element region 11 serves as the other electrode (to be referred to as a source electrode 14 hereinafter) of the MOSFET. According to the semiconductor device having the above arrangement, each of the gate electrodes 12 of the MOSFETs Q10 and Q12 has a U-shaped two-dimensional pattern, and both the ends of each of the U-shaped gate electrodes 12 extend to a field region end 10A, thereby surrounding a portion of the element region 11. In other words, the portion of the element region 11 is surrounded by the U-shaped gate electrode 12 and the field region 10, thereby independently forming the drain regions 13 in the MOSFETs Q10 and Q12. The source electrode 14 is formed in the element region 11 except for the portion serving as the drain electrodes 13, and the source electrode 14 is commonly used in the MOSFETs Q10 and Q12. Therefore, a semiconductor integrated circuit consisting of the MOSFETs Q10 and Q12 commonly using the source electrode 14 and independently using the drain electrodes 13 can be obtained. According to the above embodiment, when a circuit shown in Fig. 3 is formed in a semiconductor substrate, a field region for separating the drain electrodes 14 from each other is not required, and the area of the field region 10 can be decreased. Therefore, the above circuit can be integrated at a high density. In the first embodiment, the drain electrode may be used as a source electrode, and the source electrode 14 may be used as a drain electrode. This applies to the following embodiments to be described later. As a circuit device consisting of the circuits shown in Fig. 3, a sense amplifier or the like for amplifying a potential difference between a pair of wires is available. Fig. 4 is a circuit diagram of the sense amplifier (CMOS type). In this sense amplifier, a part corresponding to the circuit shown in Fig. 3 is given as parts surrounded by broken-line frames A and B in Fig. 4. Figs. 5A and 5B are plan views of a pattern showing an arrangement wherein the sense amplifier in Fig. 4 consists of MOSFETs according to the present invention. Fig. 5A is a plan view of a pattern showing an arrangement of a gate electrode, and Fig. 5B is a plan view of a pattern showing a condition wherein the MOSFETs are connected to each other by wiring. The same reference numerals as in Figs. 2 and 4 denote the same parts in Figs. 5A and 5B. As shown in Figs. 5A and 5B, the surface of a semiconductor substrate is divided into an element region 11N for forming an n-channel MOSFET and an element region 11P for forming a p-channel MOSFET by the field region 10. N-channel MOSFETs Q22 to Q26 are formed in the element region 11N, and p-channel MOSFETs Q28 to Q34 are formed in the element region 11P. The n-channel MOSFETs are to be referred to as NMOSs, and the p-channel MOSFETs are to be referred to as PMOSs hereinafter. The MOSFETs Q20 to Q34 have U-shaped gate electrodes 22A to 22H, respectively. The U-shaped gate electrodes 22A to 22H surround portions of the element regions 11N and 11P, and drain electrodes 23A to 23H are respectively formed on the surrounded portions. Source electrodes 24A and 24B are formed in the element regions 11N and 11P except for the surrounded portions. Connection of active elements is performed as described below. A bit line BL1 consisting of a conductive film such as a silicide film or an aluminum film is connected to a drain 23G of the PMOS Q28 through a contact hole 25A, connected to the gate 22E of the PMOS 30 through a contact hole 26A, connected to the gate 22C of the NMOS Q22 through a contact hole 26B, and connected to the drain 23A of the NMOS Q20 through the contact hole 25B. As in the above description, a bit line BL1 is connected to the gate 22G of the PMOS Q28 through a contact hole 26C, connected to the drain 23E of the PMOS Q30 through a contact hole 25C, connected to the drain 23C of the NMOS Q22 through a contact hole 25D, and connected to the gate 22A of the NMOS Q20 through a contact hole 26D. A bit line BL2 is connected to the drain 23H of the PMOS Q32 through a contact hole 25E, connected to the gate 22F of the PMOS Q34 through a contact hole 26E, connected to the gate 22D of the NMOS Q26 through a contact hole 26F, and connected to the drain 23B of the NMOS Q24 through a contact hole 25F. A bit line BL2 is connected to the gate 22H of the PMOS Q32, connected to the drain 23F of the PMOS Q34 through a contact hole 25G, connected to the drain 23F of the PMOS Q34 through a contact hole 25G, connected to the drain 23D of the NMOS Q26 through a contact hole 25H, and connected to the gate 22B of the NMOS Q24 through a contact hole 26H. The source 24A is commonly used in the NMOSs Q20 to Q24, consists of a conductive film such as an aluminum film, and is connected to a ground wire GND through contact holes 27A to 27F. The source 24B is commonly used in the PMOSs Q28 to Q34 and connected to a wire VCC having a high potential, e.g., 5 V, through contact holes 27G to 27L. The present invention is applied to the above sense amplifier, thereby obtaining a sense amplifier having a high integration density. An effect of an increase in integration density of the sense amplifier having the above arrangement will be described below with reference to Figs. 6 and 7. Fig. 6 is a plan view of a pattern showing an arrangement wherein the sense amplifier (Fig. 4) consists of conventional MOSFETs, and the plan view showing a part extracted from the pattern. Fig. 7 is a plan view of a pattern showing a part extracted from Fig. 5B. In a conventional sense amplifier shown in Fig. 6, an interval X1 between MOSFETs connected to a pair of bit lines BLn and BLn is given by equation (1): X1 = 3A + 2L + 4B + 2C + D In equation (1), reference symbol A denotes the width of a contact; L, a gate length; D, the width of a field region; B, a distance between the gate and the contact (including a margin for mask alignment); and C, a distance between the contact and the field region (including a margin for mask alignment). According to the present invention, as shown in Fig. 7, an interval X2 of MOSFETs connected to the pair of bit lines BL1 and BL1 is given by equation (2): X2 = 2A + 2L + 4B + α In equation (2), reference symbol A denotes the width of a contact; L, a gate length; B, a distance between the gate and the contact (including a margin for mask alignment); and α, an extending amount of a bit line BL from the gate. In the pattern shown in Fig. 7, the extending amount α is equal to a value obtained by subtracting a sum of gate length L and a distance F between a wire end and the gate from a patterning limit value E of a wire (bit line). Note that, in a practical pattern, the extending amount α is substantially equal to the width A of the contact. In equation (2), the extending amount α need not be required. For example, when the bit line BL does not extend from the upper portion of the gate due to a change in pattern, the extending amount α is removed from equation (2). Therefore, according to the present invention, the interval X2 is given by equation (3) when a integration density is maximally increased. X2 = 2A + 2L + 4B As a result, as is apparent from equation (1) according to a conventional technique and equation (3) according to the present invention, the interval of the MOSFETs is decreased as follows: X1 - X2 = 3A + 2L + 4B + 2C + D - (2A + 2L + 4B) = A + 2C + D In equations (1) to (3), when a design rule is set to be 1.0, the values A, B, C, D, and L are given as follows. A = L = D = 1.0 µm B = C = 0.8 µm When equations (5) and (6) are substituted in equations (1) and (3), the following values are given. X1 = 10.8 µm X2 = 7.2 µm Therefore, a difference between the intervals X1 and X2 is given by the following equation: X1 - X2 = A + 2C + D = 3.6 µm When the design rule is set to be 1.0, an interval between MOSFETs connected to a pair of bit lines can be decreased by about 3.6 µm as compared with that of a conventional technique. In addition, when an extending amount α is set as in equation (2), even if α = 0.8 µm is satisfied, the interval can be decreased by about 2.8 µm. [Second Embodiment] Since the sense amplifier shown in Fig. 4 has Y, amounts of mask shifting are equal to each other in two MOSFETs such as the NMOSs Q20 and Q22 formed to be in contact with the same end of the field region 10. For this reason, amounts of shifting of gate widths W caused by shifting masks are equal to each other in the NMOSs Q20 and Q22, and the characteristics of the MOSFETs thereof are equal to each other. As a result, MOSFETs each having a gate electrode contacting the end of the field region 10 along one direction thereof have good matching. [Third Embodiment] The third embodiment will be described below with reference to Fig. 9. The same reference numerals as in Fig. 2 denote the same parts in Fig. 9, and a detailed description thereof will be omitted. As shown in Fig. 9, a gate electrode 12 is curved once to extend its both ends to field region ends 10A or 10B at each corner of an element region, and the field region end 10A (or 10B) is adjacent to the field region end 10A (or 10B), thereby obtaining a drain electrode 13. An element region 11 except for the region surrounded by the gate electrode 12 is used as a source electrode 14. In the above arrangement, the same effect as described in the first embodiment can be obtained. [Fourth Embodiment] The fourth embodiment will be described below with reference to Fig. 10. Fig. 10 is a plan view of a pattern showing a MOSFET according to the fourth embodiment of the present invention. The same reference numerals as in Fig. 2 denote the same parts in Fig. 10, and a detailed description thereof will be omitted. In the third embodiment, both the ends of the gate electrode 12 are formed at each corner of the element region to extend to the field region ends 10A (or 10B) which are adjacent to each other, and the electrode 12 is curved once, thereby obtaining the drain e a function for amplifying a potential difference between a pair of bit lines, matching of transistors must be considered in a combination of NMOSs Q20 and Q22 or NMOSs Q24 and Q26. In order to improve this matching, the characteristics of the NMOSs Q20 and Q22 are equal to each other. In the second embodiment, the matching is considered, and a sense amplifier consists of transistors having good matching. Fig. 8 is a plan view of a pattern showing a MOSFET according to the second embodiment. The same reference numerals as in Fig. 5A denote the same parts in Fig. 8, and a detailed description thereof will be omitted. As shown in Fig. 8, the gate electrodes of two transistors required to have good matching are formed to be in contact with the end of a field region 10 along one direction thereof. For example, an element region 11N has two ends along a Y direction, as indicated by reference numerals 10A and 10B. The gates 22A and 22C of the NMOSs Q20 and Q22 required to have good matching are formed to be adjacent to, e.g., the end 10A, and the gates 22B and 22D of the NMOSs Q24 and 26 are formed to be adjacent to the end 10B. In the sense amplifier shown in Fig. 4, the NMOSs Q20 to Q26 are actuated in advance, and PMOSs Q28 to Q34 are actuated after the NMOSs are actuated. For this reason, good matching is required in the NMOSs, and the above arrangement is applied to only at least the NMOSs. The above arrangement may be applied to an element region 11P. In Fig. 10, the gates 22H and 22F of the PMOSs Q32 and Q34 are formed to be in contact with an end 10C, and the gates 22E and 22G of the PMOSs Q28 and Q30 are formed to be in contact with an end 10D. According to the sense amplifier with the above arrangement, even when masks for patterning, e.g., gate electrodes 22A to 22H are shifted in a direction X or electrode 13. In the fourth embodiment, as shown in Fig. 10, a linear gate electrode 12 which is not curved is formed across the field region ends 10A and 10B, thereby obtaining a drain electrode 13. With the above arrangement, the same effect as described in the first embodiment can be obtained. [Fifth Embodiment] A MOSFET according to the present invention has a U-shaped gate electrode as described in the first embodiment. Both the ends of the gate electrode having such a shape are across the same end of a field region. As in the third and fourth embodiments, both the ends of the gate electrode cover the ends of field regions which are adjacent to each other. In other words, the gate electrode of the MOSFET according to the present invention does not cover the ends of field regions which are opposite to each other, and the gate electrode does not divide the element region. For this reason, the gate width (almost equal to a channel width) cannot be defined by the width of the element region. When a mask for patterning the gate electrode is shifted, the gate width is varied, and the characteristics of the MOSFET are varied. As described above, the gate width is easily varied. In order to solve this problem, in the fifth embodiment, when a gate length required to actuate a MOSFET is set to be L1, a region 15 having a gate length L2 larger than the gate length L1 is arranged so as to limit a gate width W. Fig. 11 is a plan view of a pattern showing a MOSFET according to the fifth embodiment. The same reference numerals as in Fig. 2 denote the same parts in Fig. 11, and a detailed description thereof will be omitted. As shown in Fig. 11, a gate electrode 12 of a MOSFET Q30 has the gate length L1 at a portion operated as a MOSFET, and the regions 15 each having the gate length L2 larger than the gate length L1 are arranged at both the ends of the gate electrode 12. The regions 15 partially cover an element region 11 and a field region 10. According to the MOSFET Q30, in a region having the gate length L1, a sufficiently wide channel is open, and a sufficient source-drain current I D flows. In the region 15 having the gate length L2, since the gate length L2 is larger than the gate length L1, a threshold value V TH of the MOSFET is increased to make it difficult to open its channel. Therefore, the source-drain current I D does not flow in the region 15. That is, the gate width of the MOSFET is sufficiently large in only a portion immediately below a portion of the gate electrode 12 having the gate length L1. Therefore, the gate width W is limited to only the portion of the gate electrode 12 having the gate length L1. Even when a mask is shifted, the gate width W is not varied. The source-drain current ID of the MOSFET shown in Fig. 11 will be practically calculated below. In order to calculate the source-drain current I D , the MOSFET Q30 is divided into a transistor Tr1 having the gate length L1 and a transistor Tr2 having the gate length L2. A current I D 1 of the transistor Tr1 is given by equation (7): I D 1 = [(W - 2P)/L] · µ · C OX ·[(V G - V TH 1) · V D - (V D 2 /2)] In equation (7), reference symbol µ denotes effective mobility of carriers on a surface; C OX' capacitance of a gate oxide film; V G , a gate-source voltage; V TH 1, a threshold value of the transistor Tr1; and V D ' a drain source voltage. As in equation (7), a current I D 2 of the transistor Tr2 can be expressed by equation (8): I D 2 = [2P/(L + 2N)] · µ · C OX ·[(V C - V TH 2) · V D - (V D 2 /2)] In equation (8), reference symbol V TH 2 denotes a threshold value of the transistor Tr2. The source-drain current I D of the MOSFET Q30 can be expressed by a sum of the drain current I D 1 of the transistor Tr1 and the drain current I D 2 of the transistor Tr2. Therefore, the drain current I D of the MOSFET Q30 is given by equation (9): I D = I D 1 + I D 2 According to equation (8), when the value N is set to be large and the threshold value V TH 2 is increased, it is understood that the drain current I D 2 of the transistor Tr2 is decreased. Therefore, according to equation (9), it is understood that the drain current I D of the MOSFET Q30 can be set to be equal to the drain current I D 1 of the transistor Tr1. Assuming that the drain current I D 1 is varied due to mask shifting, the drain current I D 1 is rarely varied. Note that, even when mask shifting occurs, when the region 15 covers the field region end 10A, the gate width of the transistor Tr1 is not varied, and the current I D 1 of the transistor Tr1 is not varied. As described above, since the regions 15 each having a large gate length are respectively arranged on both the ends of the gate electrode 12, even when a mask for patterning the gate electrode 12 is shifted, when the regions 15 is located on the field region end 10A, the channel width W of the MOSFET Q30 is not varied. As shown in Fig. 12, the above method of limiting the channel width W can be applied to the second and third embodiments and can also be applied to the third and fourth embodiments as respectively shown in Figs. 13 and 14. Note that the same reference numerals as in Fig. 11 denote the same parts in Figs. 12 to 14. [Sixth Embodiment] The sixth embodiment will be described below with reference to Figs. 15 and 16. The same reference numerals as in Fig. 2 denote the same parts in Figs. 15 and 16, and a detailed description thereof will be omitted. As shown in Fig. 15, an opening 40 is formed in a gate electrode 12 on an element region 11 so as to expose the element region 11. When a drain electrode 13 is formed in the opening 40, MOSFETs Q40 and Q42 having the same effect as described in the first embodiment can be obtained. In this embodiment, since the opening 40 is formed in a portion of the gate electrode 12 having a sufficiently large width, when the opening 40 is formed, a portion of the gate electrode 12 having a short gate length L serves as the gate electrode 12. Therefore, since a gate width W is limited in a portion of the gate electrode 12 along the opening 40, even when a mask is shifted as in the fifth embodiment, the gate width W is not varied. As shown in Fig. 16, each of the gate electrode 12 may be curved three times in the same direction to form the opening 40 described above. In this case, although a channel is open in each region having a gate length L3, the regions are on the single source electrode 14 and have the same potential. Therefore, even when the channel is open, no current flows. In the MOSFETs Q44 and Q46 shown in Fig. 16, the gate widths W can be limited in portions along the openings 40, respectively, and the gate widths W are not varied even when a mask is shifted. [Seventh Embodiment] The seventh embodiment will be described below with reference to Figs. 17 and 18. Fig. 17 is a plan view of a pattern showing a device according to the seventh embodiment, and Fig. 18 is a sectional view showing a device along a line 18 - 18 in Fig. 17. The same reference numerals as in Fig. 5B denote the same parts in Figs. 17 and 18, and a detailed description thereof will be omitted. As shown in Figs. 17 and 18, an n-type well region 34 is formed in, e.g., a p-type silicon substrate 32. A field region 10 is formed in the surface region of the p-type silicon substrate 32. Various wires 22A to 22H, a GND, and a VCC are insulated by insulating films 36 and 38 and the like. In a semiconductor device with the above arrangement, a channel stopper is formed immediately below the field region 10. Ion implantation for forming the channel stopper is generally performed to a prospective portion of the field region 10 as a whole. However, an impurity for forming the channel stopper is diffused in the vertical direction by thermal hysterisis of a manufacturing process and oozed in element regions 11N and 11P. Therefore, an effective channel width W eff (channel width ∼ gate width) of each of MOSFETs formed in the element regions 11N and 11P is decreased. This problem typically occurs when boron having a high diffusion coefficient is used as the above impurity. In a MOSFET according to the present invention, since both the ends of the gate electrode 12 are across the same field region end, an influence of a decrease in effective channel width W eff caused by oozing the impurity for the channel stopper remarkably appears. In the MOSFET shown in Fig. 11, it is assumed that such an impurity for a channel stopper is oozed in an element region and diffused to the region of the transistor Tr1 through the region of the transistor Tr2. At this time, assuming that the length of a vertical diffusion reaching the region of the Tr1 is set to be reference symbol Q, a decrease in effective channel width W eff is given by equation (10): W eff = (W - 2P) - 2Q In a case wherein two MOSFETs each having a U-shaped gate electrode and shown in Fig. 12 are opposed to each other, it is assumed that a mask is shifted. Assuming that an amount of mask shifting is set to be reference symbol M, effective channel widths W eff 1 and W eff 2 of the two MOSFETs are expressed by equations (11) and (12): W eff 1 = (W - 2P - 2Q) - 2M W eff 2 = (W - 2P - 2Q) + 2M According to equations (11) and (12), the channel widths W eff 1 and W eff 2 of the two MOSFETs are largely different from each other. As a result, characteristics of the MOSFETs have a large difference, and matching between the MOSFETs is degraded. For this reason, the MOSFETs are not suitable for a circuit such as a sense amplifier for performing a comparing operation. As shown in Figs. 17 and 18, thermal hysterisis in a manufacturing process is considered, and ion-implanted regions 30P and 30N in which an impurity for forming a channel stopper is ion-implanted are separated from the field region 10A. In order to obtain this arrangement, before thermal oxidation is performed in a LOCOS process for forming, e.g., a field region 10, the ion-implanted regions 30P and 30N are limited by, e.g., a photoresist film or the like. Since the ion-implanted regions 30P and 30N are separated from a field region end 20A, a decrease or a variation in effective channel widths W eff of the MOSFETs Q20 to Q32 can be suppressed. In the resultant MOSFET, the effective channel width W eff is not decreased. Therefore, a MOSFET suitable for a circuit such as a sense amplifier for performing a comparing operation can be provided. In addition, in this embodiment, MOSFETs each having a small variation in effective channel width W eff can be integrated at a high density. The various MOSFETs described in the above embodiments can be applied to not only a CMOS sense amplifier, but various circuits such as a multiplexer and a demultiplexer with the above effect. Since the MOSFETs can be changed into MESFETs, the FETs can be used as not only MOSFETs but MESFETs. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A semiconductor device comprising: a semiconductor substrate; an element region (11, 11N, 11P) formed on the semiconductor substrate; an element isolation region (10) partitioning the element region, said element isolation region defining a first field region end (10A, 10C) with reference to one side of the element region and defining a second field region end (10B, 10D) with reference to another side which opposes to said one side; insulated gate FETs (Q12, Q14, Q20, Q24, Q30, Q34), each having: a first end portion extending from the element region to the element isolation region by way of the first field region end, a second end portion extending from the element region to the element isolation region by way of the first field region end, and a connecting portion by which the first end portion and the second end portion are connected to each other on the element region; and other insulated gate FETs (Q10, Q16, Q22, Q26, Q28, Q32), each of said other insulated gate FETs including a gate electrode having: a first end portion extending from the element region to the element isolation region by way of the second field region end, a second end portion extending from the element region to the element isolation region by way of the second field region end, and a connecting portion by which the first end portion and the second end portion are connected to each other on the element region, wherein said gate insulated FETs (Q12, Q14, Q20, Q24, Q30, Q34) are provided in the element region, one of source and drain electrodes being formed on the element region and located in a first portion surrounded by the gate electrode and the first field region end; said other gate insulated FETs (Q10, Q16, Q22, Q26, Q28, Q32) are provided in the element region, one of source and drain electrodes being formed on the element region and located in a first portion surrounded by the gate electrode and the second field region end, the other one of the source and drain electrodes being formed on the element region and located in a second portion different from the first portion, and said other one of said source and drain electrodes being used in common to both said gate insulated FETs (Q12, Q14, Q20, Q24, Q30, Q34) and said other gate insulated FETs (Q10, Q16, Q22, Q26, A semiconductor device according to claim 1, characterized by further comprising sense amplifiers provided in the element region, each of said sense amplifiers including: a first insulated gate FET (Q20, Q28) having (a) a current path, one end of which is supplied with an electrical current from a first bit line (BL1) and another end of which is supplied with a power from a power supply terminal (GND, VCC), and (b) a gate is supplied with a voltage from a second bit line ( BL1 ) which is paired with said first bit line (BL1); and a second insulated gate FET (Q22, Q30) having (a) a current path, one end of which is supplied with an electrical current from the second bit line ( BL1 ) and another end of which is supplied with a power from the power supply terminal (GND, VCC), and (b) a gate is supplied with a voltage from the first bit line (BL1); a third insulated gate FET (Q24, Q32) having (a) a current path, one end of which is supplied with an electrical current from a third bit line (BL2) and another end of which is supplied with a power from the power supply terminal (GND, VCC), and (b) a gate is supplied with a voltage from a fourth bit line ( BL2 ) which is paired with said third bit line (BL2); and a fourth insulated gate FET (Q24, Q34) having (a) a current path, one end of which is supplied with electrical current from the fourth bit line ( BL2 ) and another end of which is supplied with a power from the power supply terminal (GND, VCC), and (b) a gate is suplied with a voltage from the third bit line (BL2); said first and third insulated gate FETs being said insulated gate FETs, and said second and fourth insulated gate FETs being said other insulated gate FETs. A semiconductor device according to claim 1, characterized by further comprising sense amplifiers provided in the element region, each of said sense amplifiers including: a first insulated gate FET (Q20, Q28) having (a) a current path, one end of which is supplied with an electrical current from a first bit line (BL1) and another end of which is supplied with a power from a power supply terminal (GND, VCC), and (b) a gate is supplied with a voltage from a second bit line ( BL1 ) which is paired with said first bit line (BL1); and a second insulated gate FET (Q22, Q30) having (a) a current path, one end of which is supplied with an electrical current from the second bit line ( BL1 ) and another end of which is supplied with a power from the power supply terminal (GND, VCC), and (b) a gate is supplied with a voltage from the first bit line (BL1); a third insulated gate FET (Q24, Q32) having (a) a current path, one end of which is supplied with an electrical current from a third bit line (BL2) and another end of which is supplied with a power from the power supply terminal (GND, VCC), and (b) a gate is supplied with a voltage from a fourth bit line ( BL2 ) which is paired with said third bit line (BL2); and a fourth insulated gate FET (Q24, Q34) having (a) a current path, one end of which is supplied with electrical current from the fourth bit line ( BL2 ) the power supply terminal (GND, VCC), and (b) a gate is suplied with a voltage from the third bit line (BL2); said first and second insulated gate FETs being said insulated gate FETs, and said third and fourth insulated gate FETs being said other insulated gate FETs. A semiconductor device according to claim 1, characterized in that said element isolation region has a first projection extending from the first field region end to the second field region end, and a second projection extending from the second field region to the first field region, and insulated gate FETs (Q12 and Q14), each of said insulated gate FETs includes a second end portion which extends from the element region to the first projection of the element isolation region, and other insulated gate FETs (Q10, Q16), each of said other insulated gate FETs includes a second end portion which extends from the element region to the second projection of the element isolation region. A semiconductor device according to any of the preceding claims, characterized in that said gate electrode includes a first region having a first gate length, and a second region having a second gate length greater than said first gate length, said second region extending between the single element region and the element isolation region.

Inventors: OGIHARA MASAKI, SAWADA SHIZUO, OGIHARA, MASAKI, SAWADA, SHIZUO, OGIHARA, MASAKI, C/O INTELLECTUAL PROPERTY DIV., SAWADA, SHIZUO, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1991
Main classification: H01L29
IPC codes: H01L27, H01L29, H01L21