Stabilized power supply circuit

Abstract: A stabilized power supply circuit for use in a television receiver is disclosed. At least two SCRs (107, 111) are connected in series and forward between a non-stabilized DC voltage generating circuit (105) and a horizontal output circuit (101) serving as load. OFF timing of the SCRs is controlled in response to horizontal collector pulses generated from horizontal output circuit (101). Increasing the number of the SCRs connected in series with an increase in level of the non-stabilized DC voltage suppresses an increase in maximum values of currents flowing through the SCRs. Thus, the SCRs are turned off in a short time, avoiding the occurrence of erroneous operations caused by a delay in the OFF timing.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates generally to stabilized power supply circuits and, more particularly, to a stabilized power supply circuit for stabilizing an applied non-stabilized direct current (DC) voltage by employing controllable switching elements. The invention has a particular applicability to a stabilized power supply circuit for applying a stabilized direct current voltage to a horizontal output circuit of a television receiver. DESCRIPTION OF THE BACKGROUND ART The present invention is widely applicable to a stabilized power supply circuit for receiving a non-stabilized direct current voltage obtained by rectifying an alternating current (AC) power supply voltage, to supply a stabilized direct current voltage to load. As an example, a description will now be made of the case of application to a stabilized power supply circuit for supplying a stabilized direct current voltage to a horizontal output circuit in a television receiver. Fig. 1 is a block diagram of a conventional horizontal deflection circuit in the television receiver. Referring to Fig. 1, this horizontal deflection circuit includes a synchronous AFC and horizontal oscillation circuit 99 operable in response to a synchronizing circuit 98, a horizontal drive circuit 100, and a horizontal output circuit 101 for supplying a sawtooth current to a horizontal deflecting coil 11. A power supply circuit 202 rectifies a supplied AC power supply voltage to generate a non-stabilized DC voltage as a direct current power supply voltage. This non-stabilized DC power supply voltage is applied to a stabilized power supply circuit 300. The stabilized DC voltage is applied to horizontal output circuit 101. A high voltage circuit 201 generates a high voltage in response to so-called collector pulses generated from horizontal output circuit 101 and then supplies the generated high voltage to an anode of a picture tube 200. Fig. 2 is a circuit block diagram of the conventional stabilized power supply circuit shown in Fig. 1. The circuit configuration shown in Fig. 2 is illustrated in further detail in Fig. 4. Fig. 4 is a circuit diagram of a conventional horizontal deflection circuit, which is disclosed in U.S. Patent No. 3,970,780. Referring to Fig. 2, a DC voltage generating circuit 105 generates a non-stabilized DC voltage V DC . That is, DC voltage generating circuit 105 corresponds to the circuit 202 shown in Fig. 4 and serves to output the non-stabilized DC voltage V DC by rectifying the AC power supply voltage. The DC voltage V DC generated from DC voltage generating circuit 105 often varies, i.e., becomes unstable due to an increase or decrease in load connected to DC voltage generating circuit 105 or due to variations in the AC power supply voltage. Accordingly, a stabilizing circuit including a flyback transformer (FBT) 102, a silicon controlled rectifier (SCR) 107 and a smoothing capacitor 108 receives the unstable DC voltage to supply a stabilized DC voltage to horizontal output circuit 101. Horizontal output circuit 101 responds to a drive signal applied from horizontal drive circuit 100 to supply a deflection current to the horizontal deflecting coil (denoted with the reference numeral 11 of Fig. 1) and apply so-called horizontal collector pulses Va to one terminal of a primary winding 103 of flyback transformer 102. A secondary winding 106 has one terminal connected to receive the non-stabilized DC voltage V DC from DC voltage generating circuit 105. Secondary winding 106 serves to superimpose or add horizontal collector pulses with a negative polarity onto the DC voltage V DC by electromagnetic coupling. Thus, a voltage Vf is output through the other terminal of secondary winding 106 and then applied to an anode of SCR 107. The horizontal collector pulses Va, voltage Vf and a current Id flowing through SCR 107 are illustrated in a waveform diagram of Fig. 3. A capacitor 108 for smoothing is connected between a cathode of SCR 107 and ground. Accordingly, a cathode voltage of SCR 107 is first smoothed by capacitor 108. A smoothed voltage Vb is thereafter applied to the other terminal of primary winding 103. The voltage Vb is already stabilized and hence applied as a stabilized DC voltage via primary winding 103 to horizontal output circuit 101. A control circuit 109 responds to variations of the stabilized DC voltage Vb to control conduction timing of SCR 107. Nonconduction timing of SCR 107 is determined in response to the negative polarity pulses included in the voltage Vf, which are superimposed by secondary winding 106. A more detailed description will now be given on an operation of this stabilized power supply circuit with reference to Fig. 3. Horizontal collector pulses Va are periodically generated in a horizontal blanking period P1. A period P2 indicates a horizontal scanning period. First, control circuit 109 generates a signal Son (not shown) for rendering SCR 107 conductive at a time t1. Accordingly, SCR 107 is turned on at time t1, so that the current Id starts flowing through SCR 107. The current Id attains a maximum value Ip1 at a time t3 when horizontal scanning period p2 ends. The voltage Vf falls in response to the superimposed negative polarity pulses at a time t4, so that SCR 107 becomes nonconductive in response to a falling edge thereof. This causes a decrease in the current Id and thus renders SCR 107 nonconductive. After time t4, SCR 107 is kept in an OFF state until the next conduction control signal Son is applied from control circuit 109. After the application of the next conduction control signal Son, the same operation as the one described above repeats. When the voltage Vb applied to load, i.e., horizontal output circuit 101 in this example varies, control circuit 109 serves to control the timing of generating conduction control signal Son so as to stabilize the voltage Vb. More specifically, since a conduction period of SCR 107 is controlled depending on the variation of the load, a constant and stabilized voltage Vb can be applied to the load (horizontal output circuit 101). The feature to be noted in the foregoing operation is that the maximum value Ip1 of the current Id is determined depending on a voltage difference Ve1 between the anode and the cathode of SCR 107. The voltage difference Ve1 is defined as the difference between a stabilized DC voltage level Vb and the voltage Vf as shown in Fig. 3. In other words, as the voltage difference Ve1 becomes increased, the maximum value Ip1 of the current Id flowing through SCR 107 also becomes increased. Currently, television receivers incorporating picture tubes are available on the market. Thus, in such a television receiver, load such as horizontal output circuit 101 is increased. With the increase of the load, a power supply current supplied from the stabilized power supply circuit is also increased. In other words, the current Id flowing through SCR 107 shown in Fig. 2 becomes increased, and the maximum value Ipl of the current Id becomes increasingly higher. In another example, the television receivers incorporating such stabilized power supply circuits are exported to other countries where higher AC power supply voltages for commercial use are used. In the United States and Europe, for example, AC power supply voltages higher than those for use in Japan are used (e.g., AC120, 220, 240V, etc.), and hence the voltage V DC generated from DC voltage generating circuit 105 shown in Fig. 2 becomes higher. Consequently, the voltage difference Ve1 between the anode and the cathode of SCR 107 increases, resulting in such disadvantages as follows. With the DC voltage V DC rising, the voltage Vf has a higher level as shown by dotted lines in Fig. 3. Accordingly, since the voltage difference between the anode and the cathode of SCR 107 increases from Vel to Ve2, a maximum value Ip2 of the current Id also becomes higher than the maximum value Ip1. In general, the current Id flowing through SCR 107 is expressed as follows as a function of the voltage difference Ve between the anode and the cathode of SCR 107: Id = Ve/L·t where L indicates inductance of winding 106, and t indicates a conduction time length of SCR 107. Therefore, it is understood that with the voltage difference Ve increased, a still higher maximum value of the current Id is provided. It is noted that with the increase in the maximum value of the current Id, a longer time period is required for the current Id to attain a 0 level. In the example shown in Fig. 3, the current Id attains the 0 level at a time t5. That is to say, OFF timing of SCR 107 is delayed. If the OFF timing of SCR 107 is delayed more than a certain limit time length, then this stabilized power supply circuit is rendered uncontrollable, leading to malfunction of the television receiver. SUMMARY OF THE INVENTION One object of the present invention is to prevent occurrence of erroneous operation of a stabilized power supply circuit due to a rising of an applied non-stabilized DC voltage. Another object of the present invention is to prevent occurrence of erroneous operation of a television receiver due to a rising of an applied non-stabilized DC voltage to a stabilized power supply circuit thereof. In one aspect, the present invention provides the stabilized power supply circuit defined by claim 1. Preferred embodiments of the invention are disclosed in claims 2-7. In another aspect, the present invention provides the television receiver defined by claim 8. In operation, since the at least two controllable switching elements are connected in series between the non-stabilized direct current voltage source and the load, the voltages across the respective switching elements decrease. More specifically, even if a non-stabilized direct current voltage having a higher level is supplied, since a plurality of switching elements (whose number is determined in dependence on the level of the supplied voltage) are connected in series, the supplied non-stabilized direct current voltage is divided. Thus, the divided voltages are applied across the respective switching elements. As a result, a maximum value of a conduction current flowing through the switching elements decreases, thereby avoiding delays in OFF timing of the switching elements. That is, the occurrence of erroneous operation in the stabilized power supply circuit is avoided. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a conventional horizontal deflection circuit in a television receiver; Fig. 2 is a circuit block diagram of a conventional stabilized power supply circuit shown in Fig. 1; Fig. 3 is a signal waveform diagram for use in explaining an operation of the stabilized power supply circuit shown in Fig. 2; Fig. 4 is a circuit diagram of the conventional horizontal deflection circuit; Fig. 5 is a circuit block diagram of a stabilized power supply circuit showing one embodiment of the present invention; Fig. 6 is a signal waveform diagram for use in explaining an operation of the circuit shown in Fig. 5; Fig. 7 is a circuit block diagram of a stabilized power supply circuit showing another embodiment of the present invention; and Fig. 8 is a circuit block diagram of a stabilized power supply circuit showing still another embodiment of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS The stabilized power supply circuit of Fig. 5 differs from the conventional circuit of Fig. 2 in the following points. An additional stabilizing circuit is connected to one terminal of secondary winding 106 of flyback transformer 102. That is, another secondary winding 110 included in flyback transformer 102 has its one terminal connected to receive a non-stabilized DC voltage V DC generated from DC voltage generating circuit 105. Secondary winding 110 has the other terminal connected with an anode of an additional SCR 111. A cathode of SCR 111 is connected to the one terminal of secondary winding 106. A smoothing capacitor 112 is connected between the cathode of SCR 111 and ground. SCR 111 has its gate connected to receive a conduction control signal Son generated from control circuit 109. Accordingly, a DC voltage Vb1 stabilized by the additional stabilizing circuit including winding 110, SCR 111 and capacitor 112 is supplied to the conventionally provided stabilizing circuit. It is assumed that winding 110 has inductance L of the same value as that of winding 106. A description will now be made on an operation of the circuit shown in Fig. 5, with reference to Fig. 6. As can be seen in Fig. 5, two SCRs 107 and 111 are connected in series and forward biased between DC voltage generating circuit 105 and horizontal output circuit 101 serving as load. These SCRs 107 and 111 are turned on at the same time in response to the conduction control signal Son generated from control circuit 109. In addition, since negative polarity pulses based on horizontal collector pulses Va are superimposed onto anode voltages Vf1 and Vf2 of the SCRs by two secondary windings 110 and 106, SCRs 107 and 111 are turned off simultaneously. Since SCRs 107 and 111 are connected in series, a potential difference between a stabilized DC voltage Vb2 applied to horizontal output circuit 101 and a non-stabilized DC voltage V DC is divided by SCRs 107 and 111. More specifically, a voltage difference Ve3 of one half the value of the voltage difference between the anode and the cathode of SCR 107 shown in Fig. 2 is applied between the respective anodes and the respective cathodes of SCRs 107 and 111. Accordingly, respective maximum values Ip3 of currents Id2 and Idl flowing through respective SCRs 107 and 111 decrease to one half of the maximum value of the current Id flowing through SCR 107 shown in Fig. 2. Since the respective maximum values of the respective currents Id2 and Id1 flowing through SCRs 107 and 111 decrease to a half value thereof, the time required for the currents Id2 and Id1 to attain the zero level is shortened. In other words, the delay in the OFF timing of SCRs 107 and 111 can be avoided. Consequently, SCRs 107 and 111 are not kept conductive exceeding an allowable limit time, thereby avoiding the occurrence of erroneous operations in this stabilized power supply circuit. The description has been made on the stabilized power supply circuit employing two combinations of the secondary windings of flyback transformer 102, the SCRs and the capacitors in the embodiment shown in Fig. 5; however, it should be noted that it may be easy for those skilled in the art to further add such a combination in association with the level of the non-stabilized DC voltage V DC generated from DC voltage generating circuit 105. That is, even if a still higher non-stabilized DC voltage V DC is supplied, since an additional SCR is further connected in series between DC voltage generating circuit 105 and horizontal output circuit 101 serving as load, maximum values of the respective currents flowing through the respective SCRs can be decreased. While the present invention is applied to the stabilized power supply circuit for supplying the stabilized DC voltage to horizontal output circuit 101 in the television receiver in the embodiment of Fig. 5, it is noted that the present invention is not limited to this application and can be widely applied to stabilized power supply circuits employed in other electrical apparatus. More specifically, Fig. 7 shows another embodiment of the present invention, in which a circuit 113 for generating a pulse signal having a predetermined frequency is provided in place of horizontal output circuit 101 of Fig. 5. Switching elements S1 and S2 are provided in place of SCRs 111 and 107. Pulse signal generating circuit 113 generates pulses for determining OFF timing of switching elements S1 and S2. A stabilized DC voltage is outputted through an output node Nb. A further embodiment of the present invention is shown in Fig. 8. Referring to Fig. 8, switching elements S1 and S2 of Fig. 7 are replaced by pnp transistors Q1 and Q2 and diodes D1 and D2. Transistors Q1 and Q2 have their respective bases connected to receive conduction control signals Son generated from control circuit 109. It is noted that the stabilized power supply circuit of Fig. 8 also operates in the same manner and provides the same advantages as the circuit shown in Fig. 5. As described above, since the stabilized power supply circuit includes a plurality of or at least two switching controllable diode elements (SCRs) 107 and 111 connected in series and forward biased between non-stabilized DC voltage generating circuit 105 and load 101, maximum values of currents flowing upon the conduction of the respective elements are decreased. That is to say, an increase in number of switching controllable diode elements in association with an increase in level of the non-stabilized DC voltage V DC can inhibit an increase in peak currents flowing through the respective elements. Accordingly, the currents flowing through the switching controllable diode elements can rapidly attain the zero level, thereby preventing this stabilized power supply circuit from being rendered incontrollable. In other words, the occurrence of malfunctions in the television receiver can be avoided.

Claims: A stabilized power supply circuit for receiving a non-stabilized direct current voltage from a non-stabilized direct current voltage source and generating therefrom a stabilized direct current voltage for supply to a load, comprising: at least two controllable switching elements (107, 111), arranged in series connection between the non-stabilized direct current voltage source and the load, and a respective smoothing means (108,112) connected to each said controllable switching element for smoothing an output voltage of the controllable switching element; pulse signal generating means (101) for generating a pulse signal during a predetermined period; pulse signal superimposing means (102), connected to said controllable switching elements, for superimposing pulses generated by said pulse signal generating means onto direct current voltages applied respectively to said controllable switching elements to produce a superimposed pulse signal, said controllable switching elements being rendered non-conductive simultaneously in response to said superimposed pulse signal being applied to the switching elements simultaneously; and timing control means (109), responsive to the direct current voltage supplied to the load, for controlling conduction timing of said controllable switching elements and arranged so as to render said controllable switching elements conductive at the same time. A stabilized power supply circuit according to claim 1, wherein: said pulse signal superimposing means comprises a transformer (102) which includes an input winding (103) and two output windings (106, 110), said transformer having said input winding connected to said pulse signal generating means and having said two output windings connected respectively to said two controllable switching elements between the non-stabilized direct current voltage source and the load. A stabilized power supply circuit according to claim 1 or claim 2, wherein: said two controllable switching elements include two silicon controlled rectifiers (107, 111) arranged in forward-biased series connection between the non-stabilized direct current voltage source and the load, said two silicon controlled rectifiers having respective gates connected to said timing control means to receive control signals for controlling conduction timing. A stabilized power supply circuit according to claim 1 or claim 2, wherein said two controllable switching elements include: two diodes (D1, D2) arranged in forward-biased series connection between the non-stabilized direct current voltage source and the load; and two switching devices (Q1, Q2), each connected to a respective one of said two diodes and controlling current flow therethrough, said two switching devices being connected to said timing control means to receive control signals for turning said devices on. A stabilized power supply circuit according to any one of the preceding claims, wherein: said pulse signal generating means includes a horizontal output circuit (101), responsive to a horizontal synchronizing signal, for outputting pulses during a horizontal blanking period. A stabilized power supply circuit according to claim 5, wherein said horizontal output circuit (101) constitutes the load to which said stabilized direct current voltage is supplied. A stabilized power supply circuit according to any one of the preceding claims, comprising a number of said controllable switching elements arranged in series connection between the non-stabilized direct current voltage source and the load, the number of switching elements being determined by the level of the non-stabilized direct current voltage generated by the non-stabilized direct current voltage source. A television receiver comprising: a non-stabilized direct current voltage source (105) which generates a non-stabilized direct current voltage; and a stabilized power supply circuit, coupled to said non-stabilized direct current voltage source for generating from said non-stabilized direct current voltage a stabilized direct current voltage for supply to a load, said stabilized power supply circuit comprising: a plurality of controllable switching elements (107, 111) arranged in series connection between said non-stabilized direct current voltage source and the load, and a respective smoothing means (108,112) connected to each said controllable switching element for smoothing an output voltage of the controllable switching element; pulse signal generating means (101) for generating a pulse signal during a predetermined period; pulse signal superimposing means (102), connected to said plurality of controllable switching elements, for superimposing pulses generated by said pulse signal generating means onto direct current voltages applied respectively to said controllable switching elements to produce a superimposed pulse signal, said plurality of controllable switching elements being rendered non-conductive simultaneously in response to said superimposed pulse signal being applied to the switching elements simultaneously; and timing control means (109), responsive to the direct current voltage applied to the load, for controlling conduction timing of said plurality of controllable switching elements and arranged so as to render said plurality of controllable switching elements conductive at the same time.

Inventors: SHIRAKAWA MASARU, SHIRAKAWA, MASARU
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1991
Main classification: H02M3
IPC codes: H02M3, H04N3