Current source

Abstract: A Safe Operating Area (SOA) circuit is constructed including a synthetic large value resistor that is an active current source whose output current is related to the power supply voltage, and whose absolute value may be arbitrarily low. A piece-wise current source is provided which includes means for generating one or more control voltages in order to control the level of output current in response to the input voltage. In one embodiment, each of the control signal means includes feedback means and a summing node, so that one or more functions are performed using a control signal as an input, with the result fed back to the summing node. In this manner, a complex function can easily be provided for controlling the magnitude of the output current. In one embodiment, the one or more control signals are provided by one or more saturating current mirrors in order to limit the output current made available. The saturating current mirror comprises a bipolar transistor having a plurality of collectors, one of the collectors serving to provide the output current, and one or more collectors connected to circuit elements which have current characteristics with respect to the input voltage. In another embodiment, the bipolar transistor having a plurality of collectors is replaced by a plurality of MOS transistors, having channel widths of desired ratios in order to provide a desired transfer function.

Description: This invention relates to voltage regulator output power transistor safe operating area protection (SOA). A wide variety of protection techniques are known in the prior art, including techniques which reduce output transistor conduction by reducing base (or gate) drive to synthesize current limits, over-voltage limits, and junction temperature limits. What the continuous safe area limit techniques (as opposed to the more simple digital on/off protection techniques) have in common is a resistor that senses the supply voltage for the current limit circuit. However, when the quiescent current of the circuit must be made very low, the required resistor becomes an inefficient solution. For example, a 3 MΩ resistor sensing a 30 V supply draws 10 µA. (A resistor having much higher resistance will consume excessive integrated circuit die area). This amount of current, plus the current consumed by the remainder of the current limiting circuitry, is unacceptably high. Figure 1 is a schematic diagram of a typical prior art current source, utilizing resistor 11 to sense supply voltage V in . The circuit of Figure 1 provides an output current I out in response to input voltage V in . As shown in the graph of Figure 2, as input voltage V in increases, current I R increases, which flows through diode connected transistor 14. Transistor 12 mirrors this current, thereby increasing the amount of current I from current source 13 which is sunk by transistor 12, and thus decreasing the available output current I out . A schematic diagram of a prior art current limit circuit 300 is shown in Figure 3. Differential amplifier 311 turns on transistor 317, in an analog fashion, to reduce base current drive to transistor 316, assuming that the error amplifier signal applied to lead 318 driving the base of transistor 316 has limited drive capability. Current I from current source 310 produces a voltage drop across resistor 312. In current limit, differential amplifier 311 adjusts power transistor 316 conduction until resistor 313's voltage drop equals that of resistor 312, thereby making I O proportional to I, with I O /I equal to the ratio of the resistance of 312 to 313. Let the power dissipation of transistor 316 be held approximately constant by making I inversely proportional to V in - V out . This is achieved, for example, by using the prior art circuit of Figure 1 as current source 310 of Fig. 3. Current I is produced by generating a current approximately proportional to V in - V out by resistor 11, and by subtracting that current from a constant current I 13 , to produce I out graphed in Figure 2. Other methods of producing the approximate constant power dissipation of a pass transistor such as transistor 316 of Figure 3 rely on multiplying a sample of load current I O by a resistor-divided supply voltage. Such methods not only require the large valued resistors of the voltage divider, but a more accurate error amplifier to perform the multiplication. Figure 4 is a schematic diagram of a typical prior art multiplying power limit circuit 200. Circuit 200 includes differential amplifier 230 which provides a control signal to the base of output transistor 205, which in turn controls output voltage V out . The output current available on output lead 203 is controlled by differential amplifier 230, in response to input voltage V in applied to lead 201. Transistor 206 is connected in parallel with output transistor 205 in order to mirror the current flowing through output transistor 205. PNP transistor 207 is connected as a load device having one of its collectors 207-1 connected to its base and in turn connected to the collector of transistor 206. Collector 207-2 of transistor 207 provides a current which mirrors the current flowing through collector 207-1 of transistor 207. This mirrored current is applied to load device 208, which in turn causes current source 209 to mirror the current flowing through transistor 208. Current source 209 feeds differential transistor pair 213 and 214, with transistor 213 receiving its base drive input signal from output lead 203. A resistive voltage divider formed of resistors 210 and 211 (having resistances R 2 and R 1 , respectively) is connected between V in lead 201 and V out lead 203, and provides a voltage to the base of differential transistor 214. Transistor 215 serves as a load device connected between V in lead 201 and the collector of transistor 213. Transistor 216 mirrors the current flowing through transistor load device 215, and has its collector connected to the inverting input lead of differential amplifier 230 and to the collector of differential input transistor 214. The non-inverting input lead of differential amplifier 230 is connected to a bias voltage above ground provided by bias circuitry 204. A negative feedback loop includes amplifier 230, pass transistor 205, and the transconductance amplifier consisting of transistors 209, 213, 214, 215, and 216. Because of the high loop gain, the voltages on the inverting and non-inverting input leads of amplifier 230 are forced to be equal. The voltage drop across resistor 212 (having resistance R 3 ) is therefore equal to the offset voltage V offset depicted as 231. If I x is the output current of the transconductance amplifier then I x = V offset R 3 Also, I x = G M V R2 ; where V R2 = the voltage drop across resistor 210 having resistance R 2 = (V in - V out )R 2 R 1 + R 2 ; and G M = transconductance = I c209 2V T ; where V T = the thermal voltage KT/q; and, due to current mirrors of transistors 205 and 206, 207, and 208 and 209 I c209 = I out N ; where is the collector current of transistor 209; I out is the emitter current of pass transistor 205; and N is a proportionality factor. Eq. (2) thus becomes I x = I out 2NV T x (V in - V out )R 2 R 1 + R 2 Setting this equal to Eq. (1) we get I out (V in - V out )K 2NV T = V offset R 3 ; where K = R 2 R 1 + R 2 or I out (V in - V out ) = 2NV T x V offset KR 3 Since (V in - V out ) equals the power dissipation of pass transistor 205, the circuit of Fig. 4 gives a constant power dissipation. Unfortunately, prior art circuit 200 of Figure 4 is undesirably sensitive to manufacturing tolerances, for example the inherent DC offset voltage V offset of differential amplifier 230. Furthermore, prior art circuit 200 requires large value resistors 210 and 211 connected between V in lead 201 and V out lead 203, which are difficult to fabricate on an integrated circuit to precise tolerances, and require a large amount of integrated circuit area. It is an object of this invention to provide a current source whose output falls as V in - V out rises. It is a further object of the invention to permit provision of a current source whose output current may vary as a wide range of functions of V in - V out It is still a further object of the invention to enable production ofthe output current as a function of V in - V out with any absolute value of current, supply current, and without large valued resistors. The basic concept of the invention is defined in claim 1. A current source having the features set forth in the preamble of patent claim 1 is disclosed by US-A-4,605,891. In accordance with the teachings of this invention, a circuit is constructed to limit power transistor conduction to within its safe operation area (SOA), the circuit including a synthetic large value resistor that is an active current source whose output current is related to the power supply voltage, and whose absolute value may be made arbitrarily low. To implement a complex SOA protection function, the SOA circuit of this invention synthesizes currents that are nonlinear fractions of voltage and has a topology that allows the current source output current to be a function of many variables such as junction temperature and machine state. The topology of the invention makes it flexible in terms of the transfer function that may be synthesized, and the invention relates to a current source whose voltage-to-current transfer function may synthesize a wide variety of functions such as a linear resistor, a nonlinear resistor, and a negative resistor. The transfer functions are piece-wise approximations of the desired functions, with as many pieces as desired for a desired accuracy in generating the transfer functions. The invention generally relates to the generation of a current that is a piece-wise function of a control voltage. In accordance with the teachings of this invention, a novel piece-wise current source is provided which includes means for generating one or more control voltages in order to control the level of output current in response to the input voltage. In one embodiment of this invention, each of the control signal means includes feedback means and a summing node, so that one or more functions are performed using a control signal as an input, with the result fed back to the summing node. In this manner, a complex function can easily be provided for controlling the magnitude of the output current. In one embodiment of this invention, the one or more control signals are provided by one or more saturating current mirrors in order to limit the output current made available. In one embodiment of this invention, the saturating current mirror comprises a bipolar transistor having a plurality of collectors, one of the collectors serving to provide the output current, and one or more other collectors connected to circuit elements which have current characteristics with respect to the input voltage. In one embodiment, these other collectors are connected to one or more zener diodes in order to provide a current path through these collectors when the input voltage increases above the predetermined level, thereby decreasing the output current available. In one embodiment of this invention, the circuit elements connected to the collectors provide equal step sizes of the output current to input voltage transfer function, while in another embodiment these steps are made unequal in any desired configuration. In another embodiment of this invention, the collector areas vary among the various collectors, thereby providing a desired ratio among the steps of the transfer function. In another embodiment of this invention, the bipolar transistor having a plurality of collectors is replaced by a plurality of MOS transistors, having channel widths of desired ratios in order to provide a desired transfer function. Another embodiment of the invention is disclosed in the appended claims 13 to 18. This embodiment is not illustrated by the drawings. Figure 1 is a schematic diagram of a typical prior art current source; Figure 2 is a graph depicting the operation of the circuit of Figure 1; Figure 3 is a schematic diagram depicting a prior art current limit circuit which, when used with the current source of Figure 1, limits the power dissipation of a pass device; Figure 4 is a schematic diagram depicting a prior art multiplying power limit circuit; Figure 5a is a schematic diagram of one embodiment of a current source constructed in accordance with the teachings of this invention utilizing a bipolar transistor having a plurality of collectors; Figure 5b is a graph depicting the transfer function of the circuit of Figure 5a; Figure 6 is a schematic diagram of one embodiment of a current source constructed in accordance with the teachings of this invention utilizing a saturated current mirror; Figure 7a is a schematic diagram of another current source constructed in accordance with the teachings of this invention utilizing a bipolar transistor having a plurality of collectors; Figure 7b is a graph depicting the transfer function of the circuit of Figure 7a; and Figure 8 is a schematic diagram of one embodiment of a current source constructed in accordance with the teachings of this invention which utilizes a plurality of MOS transistors. The object of this invention is obtained in the embodiment of this invention depicted as circuit 600 of Figure 5a, which operates as follows with reference to the graph of Fig. 5b. When V in is a high voltage (above V out - V be + 7v + 7v ≥ ≃ 20 volts) all collectors 606-1 through 606-4 of multiple collector lateral PNP transistor 604 are active and conducting (equally, if collectors 606-1 through 606-4 are matched). Since collectors 606-1 through 606-4 are matched, of the current I provided by current source 603, I/3 passes through transistor 602 via collector 606-4, and I/3 passes through collector 606-3, I/3 passes through collector 606-2. Therefore, I/3 flows from collector 606-1 through resistor 607, shown here being grounded, for simplicity. As V in falls, collector 606-2 is the first to saturate, with the current conducted by collector 606-2 falling to zero. Neglecting the controllable effects of collector 606-2 emitting minority carriers to its neighboring collectors, I/2 now flows through transistor 602 from collector 606-4, I/2 flows through collector 606-3, and I/2 flows through collector 606-1 as output current. The resulting output voltage increases, as shown as point 609 in the graph of Figure 5b. As V in falls further, collector 606-3 saturates and its current falls to zero. There is now no feedback current, the circuit is operating open-loop, transistor 602 conducts current I from collector 606-4, and collector 606-1 is conducting I as output current. The output voltage rises further, as shown at point 610 of the graph of Figure 5b. In one embodiment, V in is 5 volts and V out applied to the base of transistor 602 is a constant 2.5 volts, for convenience and in order to allow circuit 600 to be operational with V in of as low approximately 2.5 volts. The relative widths of each collector of transistor 604 are selected to provide the desired transfer function. For example, the transfer function of circuit 600 for matched collectors, as shown in Figure 5b, allows greater power dissipation at low V in where the power transistor (not shown, but typically formed as a portion of a voltage regulator integrated circuit which is controlled by control voltage V control ) can dissipate more power. In one embodiment, transistor 604 is formed as four separate transistors having their emitters connected in common and their bases connected in common. The base width associated with collector 606-1 is wider than the base widths associated with collectors 606-2 through 606-4 in order to reduce the effect of size of collector 606-1 relative to the sizes of collectors 606-2 through 606-4, and to increase the output resistance. In one embodiment, transistor 604 is formed including P type guard rings to minimize the collection by the usually active collectors 606-1 and 606-4 of minority carriers emitted by the saturated collectors. Figure 6 is a schematic diagram of another embodiment of this invention. Circuit 500 includes differential amplifier 510 which receives input voltage V in on its noninverting input lead. Its inverting input lead is connected to its output lead which in turn is connected to saturating current mirror 504. Saturating current mirror 504 includes a number of output leads 504-1 through 504-N which are connected to a variety of voltage sources V 1 through V n , respectively. These voltage sources serve to provide a current path for currents I l through I n , respectively, as input voltage V in increases above voltage levels V l through V n , respectively, thereby causing the output current I out to decrease with increasing input voltage V in . By utilizing a desired set of voltages V l through V n of desired magnitudes, the output current function is tailored to any desired accuracy as a function of V in . For example, for very small step sizes between voltages V 1 through V n , the step sizes of output current I out in response to input voltage V in will be small. If desired, the step sizes between voltages V 1 through V n are equal, although they need not be. Circuit 500 also includes differential amplifier 501 which receives a bias voltage V bias on its noninverting input lead, and whose output lead drives transistor 502 in order to provide output current I out . Of course, the voltage applied to transistor 502 by saturating current mirror 504 is established by the amount of current I l through I n , as established by voltages V l through V n , respectively. Figure 7a is a schematic diagram of another circuit constructed in accordance with the teachings of this invention. The operation of the circuit of Figure 7a is easily understood with reference to the graph of output current versus input voltage shown in Figure 7b. Assume 0.1 volt saturation for PNP transistor 704, 0.7 forward biased volt base-emitter voltage drop, and 7 volt Zener voltage drop. Then Zener diodes 709 through 712 conduct for the following situations: (a) all Zener diodes 709 through 712 conduct: V in ≥ V out + 0.1v + (2 x 7v) + (5 x 0.7v) = V out + 17.6v This yields V in - V out ≥ 17.6v (b) for 17.6v > V in - V out ≥ 14.1v, Zener diode 710 is off. (c) for 14.1v > V in - V out ≥ 10.6v, Zener diodes 710 and 712 are off. (d) for 10.6v > V in - V out ≥ 7.1, Zener diodes 709, 710, and 712 are off. (e) for 7.1v > V in - V out , all Zener diodes 709 through 712 are off. Condition (a) I = 5I x I x = I/5 (b) I e = 4I x I x = I/4 (c) I x = I/3 (d) I x = I/2 (e) I x = I; where I x = the current per collector in PNP transistor 704. As shown in Figure 7b, the output current available on lead 708 has a step function corresponding to the number of Zener diodes 709 through 712 which are turned on. With a low V in -V out , all Zener diodes 709 through 712 are non-conducting, and maximum voltage drop across resistor 707 (and thus maximum output current) is obtained. At approximately V in - V out = 7.1 volts, Zener diode 711 begins to conduct, thereby reducing the voltage drop across resistor 707. A second stepwise decrease in the voltage drop across resistor 704 occurs when V in -V out increases to approximately 10.6 volts, when Zener diode 709 begins to conduct. Additional stepwise decreases occur when V in - V out increases to approximately 14.6 volts and 16.6 volts when Zener diodes 712 and 710 begin to conduct, respectively. Figure 8 is a schematic diagram of another embodiment of this invention which utilizes MOS transistors rather than bipolar transistors in order to cause Zener diodes 809 through 812 to conduct current through associated transistors 819 through 822, respectively, in order to cause a stepwise decrease in output current I out made available on lead 808 as input voltage V in increases. For the embodiment depicted in the schematic diagram of Figure 8, let I x = the current flowing through a suitably sized P channel MOS transistor. (a) For V in - V out < 7v + V gs , all Zener diodes 809 through 812 are off and I x = I in (b) For 7v ≤ V in - V out - V gs < 14v, only Zener diode 812 is on I in = 2I x so I x = I in /2 (c) For 14v ≤ V in - V out - V gs < 21v, Zener diodes 812 and 811 are on, and thus I x = I in /3 (d) For 21v ≤ V in - V out - V gs < 28v, Zener diodes 810, 811, and 812 are on, and thus I x = I in /4 (e) For 28v + V GS < V in - V out , all Zener diodes 809 through 812 are on I in = 3I x + 4I x I x = I in /7 In all conditions, I = 12I x. In one embodiment of this invention, for example the embodiment of Figure 7a, the area sizes of collectors 706-1 through 706-6 are scaled by the desired size relationships in order that the step sizes and output current are not equal. For example, for a collector having twice as much area as another, its effect on the decrease in the available output current will be twice as much. In another embodiment of this invention, for example, that of Figure 8, the channel widths of transistors 819 through 822 are scaled in order to have a similar effect.

Claims: A current source (600) comprising: an input lead for receiving an input voltage (V IN ); an output lead for providing an output current; a current mirror (604) having an input lead coupled to receive an input signal in response to said input voltage, a control lead, and an output lead coupled to said output lead of said current source; and a plurality of output current control means (609, 610), characterized in that said plurality of output current control means are connected to a respective one of a plurality of control leads (606-2, 606-3) of said current mirror (604), each one of said output current control means conducting current from said current mirror (604) when said input voltage (V IN ) reaches a predetermined level associated with said output current control means, thereby affecting the current available on said output lead of said current mirror. A current source as in claim 1 which further comprises a buffer (510) comprising an input lead for receiving said input voltage (V IN ) and output lead connected to said input lead of said current mirror (604). A current source as in claim 1 wherein said plurality of output current control means (609, 610) provide a plurality of steps in said output current with respect to said input voltage, said plurality of steps being of equal values as a function of the difference between the input voltage (Y IN ) and the output voltage (V OUT ). A current source as in claim 3 wherein said plurality (709-710; 711-712) of output current control means are connected in series, and wherein said plurality of control leads of said current mirror are connected to associated ones of the interconnections between said plurality of output current control means. A current source as in claim 1, wherein said current source comprises a current mirror transistor (604) comprising: a base; an emitter serving as said input lead of said current source; a first collector coupled to said base and coupled to a second current source (603); a second collector serving as said output lead of said current mirror; and a plurality of additional collectors serving as said plurality of control leads (602, 603) of said current mirror. A current source as in claim 5 which further comprises a coupling transistor (602) having a base for receiving an output voltage (V OUT ), a collector coupled to said base of said current mirror transistor, and an emitter coupled to said second current source (603). A current source as in claim 5 wherein said output current control means (609, 610) are coupled between an associated one of said plurality of additional collectors and said second current source (603). A current source as in claim 7 wherein said output current control means comprise zener diodes (609, 610). A current source as in claim 8 wherein said output current control means comprise a plurality of zener diodes (609, 610) connected in series, one end of said series coupled to said second current source (603), and the other end of said series and the intermediate nodes of said series connected to respective ones of said plurality of additional collectors. A current source as in claim 9 wherein said zener diodes (609, 610) have approximately equal zener breakdown voltages. A current source as in claim 5 wherein said plurality of additional collectors have approximately equal current carrying ability. A current source as in claim 5 wherein said plurality of additional collectors have unequal current carrying ability. A current source as in claim 6 which further comprises one or more additional current sources coupled to said base of said current mirror transistor, wherein selected ones of said output current control means are coupled to selected ones of said current sources. A current source as in claim 13 which further comprises voltage shift means associated with at least some of said current sources, such that said output current control means are coupled to associated ones of said current sources with a predetermined voltage translation. A current source as in claim 14 wherein said voltage shift means comprise diodes. A current source as in claim 15 which further comprises one or more additional transistors, each having a collector coupled to said collector of said coupling transistor, a base coupled to said base of said coupling transistor, and an emitter coupled to an associate one of said additional current sources. A current source as in claim 16 wherein at least some of said additional transistors have their emitters connected to said associated current sources through voltage shift means. A current source as in claim 17 wherein said voltage shift means comprise one or more diodes. A current source as in claim 1 wherein said current mirror comprises: a first transistor having a control element, a first current handling lead serving as said input lead of said current mirror and a second current handling lead coupled to said control element and coupled to a current source; a plurality of additional transistors, each having a control element coupled to said control element of said first transistor, a first current handling lead coupled to said first current handling lead of said first transistor, and a second current handling lead serving as one of said plurality of control leads of said current mirror.

Inventors: WRIGHT MICHAEL E, WRIGHT, MICHAEL E.
Applicants: NAT SEMICONDUCTOR CORP, NATIONAL SEMICONDUCTOR CORPORATION
Application year: 1991
Main classification: G05F1
IPC codes: G05F3, G05F1