Motion image data compression system

Abstract: A motion data image compression system comprises a first element (21, 24) to divide an I′th frame (I = 1, 2, ... N-1) between the two frames F₀ and F N out of N frames (where N is an integer of 2 or more) of digital motion image data, into a block B I formed of a plural number of pixels, and to determine the motion vector MV0I of frame F₀ and F I for each of the divided blocks B I and to determine the block B₀ that uses the motion vector MV0I to predict the block B I , a second element (22, 25) to determine the motion vector MVNI between frame F N and F I for each block B I and that uses the motion vector MVNI to determine the block B N that predicts the block B I , a third element (53, 54, 55, 56, 57, 58, 59) that determines the motion vectors MV0N and MVN0 of frame F N and F₀ for each block B I , and uses the motion vectors MV0N and MVN0 to determine the predective motion vector MV0I′ between frame F₀ and F I , determine the block B 0′ that predicts the block B I , determine the predictive motion vector MVNI′ between frames F N and F I , and that uses the predictive motion vector MVNI′ to determine the block B N′ that predicts block B I and the block B 0N′ that is the linear sum of blocks B 0′ and B N′ , a fourth element (45) that determines the block B DC from the average value of block B I , and a fifth element (46) that selects the block out of the blocks B₀, B N , B 0N , and B DC for which the correlation with block B I is greatest.

Description: BACKGROUND OF THE INVENTION The present invention relates to a favourable motion image compression system used when motion image data are compressed and transmitted. FIG. 1 is a block diagram showing the configuration of a conventional motion image data compression system that processes motion images as units of N frames (where in this example, N = 4). One such system is disclosed in ITEJ Technical Reports Vol. 13 No. 60 pp 13-18, VIR '89-26, Nor 1989 in an article by Kenji SUGIYAMA. Five frames of digitally connected image data from the 0th frame (F,) to the 4th frame (F4) from a circuit (not indicated in the figure) are respectively stored in frame memories 1 through 5 (refer to FIG. 2). A motion vector detection circuit 6 divides the data of frame I (l = 1, 2, 3) into blocks B 1 for each 8 x 8 pixels for examples and each block B 1 units has the motion vector MVOI between frame F O and frame F I and the motion vector MV4I between frame F4 and frame F I , calculated and output to a motion compensation predictor circuit 7. The motion compensation predictor circuit 7 uses the motion vectors MVOI and MV4I as the reference for performing motion compensation predictive for the block B I for a required mode, and the prediction error signals are output to a predictive error signal coding circuit 10 via a switch 8. In addition the motion compensation predictor circuit 7 outputs data relating to the motion vector and the predictive mode to the predictive error signal coding circuit 10. The predictive error signal coding circuit 10 codes the data that is read from the input frame F 2 via the switch 8. and codes the predictive error signals output from the predictive compensation predictor circuit 7. In addition a motion vector mode coding circuit 9 codes the motion vector and the predictive mode. A microprocessor 11 overlaps the output of the predictive error signal coding circuit 10 and the motion vector mode coding circuit 9. and outputs it to a demodulation system via a transmission system not indicated in the figure. The motion compensation predictor circuit 7 is configured as indicated in FIG. 3 for example. An address generating circuit 21 generates an address of block B 0 from an address of block B I input by an address generating circuit 23 and the motion vector MVOI for between frames F 0 and F I , reads the data of that address from frame memory 1, and stores it in a work memory 24. In the same manner, an address generating circuit 22 generates an address of block B 4 from the address of the block B I input from the address generating circuit 23 and the motion vector MV4I for between frames F 4 and F I , reads that address from the frame memory 2 and stores it in the work memory 25. During this time, the number of blocks is counted by a block counter 29. The data of block B 0 that is written to the work memory 24 is input to the mode judgment circuit 28 and also supplied to an adder 27. In the same manner, the data of block B 4 that is written to a mode judgment circuit 28 is input to the mode judgment circuit 28 and also supplied to the adder 27. The adder 27 multiplies the data of block B 0 input from the work memory 24, by a coefficient (1 - ω) (where ω = I/4), and the data for block B 4 input from a work memory 25 is multiplied by the coefficient ω and the two are added. More specifically, the adder 27 outputs the block B 04 by linear interpolation of blocks B 0 and B 4 , as shown by the following equation. B 04 = (B 0 × B(4-I) + B 4 × B I )/4 The data of this block B 04 is also output to the mode judging circuit 28. During this time, the number of pixels is counted by a pixel counter 30. In addition, the address generating circuit 23 reads the address of block B I from one of the frame memories 3 through 5 and outputs it to a work memory 26. The data of block B I that is stored in the work memory 26 is supplied to the mode judging circuit 28. The mode judging circuit 28 is configured as shown in FIG. 4, for example. The data of the block B I that is stored in the work memory 26 is supplied to correlation calculation circuits 41 through 44, and to the direct current (DC) component calculation circuit 45. The DC component calculation circuit 45 averages the data of block B I , generates a block B DC and outputs it to the correlation calculation circuit 44. The data of blocks B 0 , B 4 and B 04 are input to correlation calculation circuits 41 through 43. The correlation calculation circuit 41 calculates the correlation between blocks B 0 and B I and the mean square error (MSE0) between the two and outputs them. In the same manner, the correlation calculation circuit 42 calculates the correlation between blocks B 4 and B I and the mean square error (MSE4) between the two and outputs them, the correlation calculation circuit 43 calculates the correlation between blocks B 04 and B I and the mean square error (MSE04) between the two and outputs them, and the correlation calculation circuit 44 calculates the correlation between blocks B DC and B I and the mean square error (MSEDC) between the two and outputs them. Then, the respective coefficient values SEL0, SEL4, SEL04 and SELDC are determined as follows. SEL0 = MSE0 SEL4 = MSE4 SEL04 = MSE04 SELDC = MSEDC × α + β Where α and β are coefficients the satisfy the following conditions. 0 < α < 1 0 < β These correlation values becomes smaller when the correlation with block B I becomes higher. A minimum value judgment circuit 46 judges the smallest value from the four correlation values, and makes the corresponding mode the predication mode. Then, that predictive mode and the motion vector in that predictive mode is output to the motion vector coding circuit 9 and a predictive error signal corresponding to the difference between the block B I and a constant value and the blocks B 0 , B 4 , B 04 predicted in the predictive mode is generated and output to the predictive error signal coding circuit 10. More specifically, each of the modes can be described in the following manner. Mode 1: Block B 0 is the predictive block and the motion vector MV0I is coded. Mode 2: Block B 4 is the predictive block and the motion vector MV4I is coded. Mode 3: Block B 04 is the predictive block and the motion vectors MV0I and MV4I are coded. Mode 4: Block B DC is the predictive block and the motion vector is not coded. In this manner, in the conventional apparatus, when mode 3 is selected, coding is performed for the two motion vectors MV0I and MV4I and there is the problem that the amount of coding becomes large. In addition, when there is movement of one pixel in four frames, there is a minute movement of one pixel or less between frames. However, it is not possible to predict movement of one pixel or less and so since there is no method for the expression of movement in units of one pixel, the error between the predicted pixel and the actual pixel becomes large. Accordingly, the amount of coding of the predictive error block corresponding to the predictive error signal becomes large. SUMMARY OF THE INVENTION In order to solve the problem described above, an object of the present invention is to provide a motion image data compression system that can perform accurate and efficient motion compensation with respect to minute movement by reducing the amount of coding and without producing image deterioration by the generation of a predictive block using the predicted motion vector. The present invention provides motion image data compression apparatus comprising: first means for dividing an I-th frame (I=1,2,...,N-1) between two frames F O and F N of N frames (where N is an integer of 2 or more) of digital motion images, into a block B I formed of a plural number of pixels, for generating the motion vector MVOI of frame F O and F I for each of the divided blocks B I and for generating the block B O that uses the motion vector MVOI to predict the block B I ; and second means for generating a motion vector MVNI between the frames F N and F I , for each block B I , and for generating a block B N predicting the block B I on the basis of the motion vector MVNI; where blocks B O and B N are formed of pixel data of frames F O and F N respectively; characterised by: third means 1) for generating motion vectors MVON or MVNO of frame F N and F O for each block B I , 2) for generating a predictive motion vector MVOI' between the frame F O and F I , by using said motion vectors MVON or MVNO, 3) for generating a block B O ' predicting the block B I by using said motion vectors MVOI,. 4) for generating a predictive motion vector MVNI' between frames F N and F I by using said motion vectors MVON or MVNO, 5) for generating a block B N ' predicting block B I by using the predictive motion vector MVNI', and 6) for generating a block B ON ' being the linear interpolation of blocks B O ' and B N ', fourth means for generating a block B DC from the average value of said block B I , and fifth means for selecting and outputting a block for which the correlation with the block B I is greatest. The invention enables the prediction of movements of one pixel or less, and therefore reduces the amount of coding. According to the present invention, it is possible to use the predictive motion vector to generate a predictive block and therefore reduce the number of motion vectors for coding and therefore reduce the amount of coding. In addition, it is possible to raise the motion vector resolution performance and therefore enable the accurate and efficient performance of motion compensation even with respect to minute movements. In addition, according to the motion image data compression system according to the other aspect and as has been described above, the block B ON is determined from the linear sum of block B O and B N and the block out of blocks B O , B N ,B ON ,B ON ' and B DC that has the greatest correlation with block B I is selected. Accordingly, it is possible to prevent deterioration of the image quality. In addition, according to the motion image data compression system according to the other aspect and as has been described above, the block B ON is further determined from the linear sum of the block B O and B N and so there is no deterioration of the image quality, and the amount of coding can be further reduced. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a configuration of a motion image data compression system of a conventional technique and the present invention; FIG. 2 is a view describing the operation of the system in FIG. 1; FIG. 3 is a block diagram showing a configuration of a motion compensation predictor circuit in the system of FIG. 1; FIG. 4 is a block diagram showing the configuration of a mode judgment circuit in the system of FIG. 1; FIG. 5 is a block diagram showing the configuration of a motion compensation predictor circuit in the motion image data compression system according to a first embodiment of the present invention; FIG. 6 is a block diagram showing the configuration of a mode judgment circuit in the motion image data compression system according to a first embodiment of the present invention; FIGS. 7 and 8 are graphs showing the interpolation operation of the systems of the embodiments shown respectively in FIGS. 5 and 6; FIG. 9 is a block diagram showing the configuration of a motion compensation predictor circuit in the motion image data compression system according to a second embodiment of the present invention; and FIG. 10 is a graph describing the operation of a motion compensation predictor circuit of the system of the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following is a description of the preferred embodiments of the motion image data compression system according to the present invention. The basic configuration of the motion image data compression system according to a first embodiment of the present invention is the same as that indicated for the conventional technology in FIG. 1. However, in the motion image data compression system of the first embodiment, the motion compensation predictor circuit 7 of FIG. 1 has the configuration as shown in FIG. 5, for example. The configuration of the address generating circuit 21 through to the pixel counter 30 is practically the same as that shown in FIG. 3 and so the description thereof is omitted. In the first embodiment shown in FIG. 5, the motion vector MV04 from the motion vector detection circuit 6 and the number of frames I from a frame counter 52 are respectively input to a vector division circuit 51. The vector division circuit 51 generates predictive motion vectors MV0I' and MV4I' and respectively inputs them to address generating circuits 53 and 54. The address generation circuits 53 and 54 read the data of the addresses corresponding to the predictive motion vectors MV0I' and MV4I' and respectively store them in work memories 55 and 56. The data of the work memories 55 and 56 are respectively supplied to interpolation circuits 57 and 58 where the vector division circuit 51 multiplies them by a coefficient corresponding to the output signal k, and outputs the result to an adder 59. The output of the adder 59 is output to the mode judging circuit 28. The mode judging circuit 28 is configured as shown in FIG. 6. More specifically, in the configuration shown in FIG. 4, there is a correlation calculation circuit 61 added and the block B 04' and block B I are input to the correlation calculation circuit 61. Then, the minimum value judgment circuit 46 is configured so as to judge the minimum value of the output of the correlation calculation circuit 61 and the correlation calculation circuit 41 through 44. The other portions of the configuration are the same as those in the configuration shown in FIG. 4. In this first embodiment of the present invention and having the configuration as described above, the first means is configured from the address generating circuit 21 and the work memory 24, the second means is configured from the address generation circuits 2 and the work memory 25, the third means is configured from the address generation circuits 53 and 54, the work memories 55 and 56, the interpolation circuits 57 and 58 and the adder 59, the fourth means is configured from the DC calculation circuit 45, the fifth means is configured from the minimum value judging circuit 46 and the sixth means is generated from the adder 27. The following is a description of the operation. The operation up to the input of the blocks B 0 , B 4 , B 04 and B I to the mode judging circuit 28 is the same as has been described above and so the description will be omitted. In addition to the motion vectors MV0I and MV4I, the motion vector detection circuit 6 generates the motion vector MV04 between frames 0 and 4, and outputs this motion vector MV04 to the vector division circuit 51. In addition, the number of frames I counted by the frame counter 52 is input to the vector division circuit 51. The vector division circuit 51 uses this input to perform the following calculations, and generates the predictive motion vectors MV0I' and MV4I'. MV0I' = MV04 × I/4 MV4I' = -MV04 × (4-1)/4 Accordingly, for example, when I = 3 and MV04 = (5, 7) the predictive motion vectors MV03' and MV3I' become MV03' = (3.75, 5.25) MV43' (-1.25, -1.75) More specifically, these predictive motion vectors have a resolution of 1/4 of a pixel. As shown in FIG. 7, the address generating circuit 53 reads for example, the 16 pixel data P ij (i = 0, 1, 2, 3; j = 0, 1, 2, 3) of the periphery of the interpolation position (shown by x in the figure) indicated by the predictive motion vector MV0I' (MV03' in the case of this example) and writes to the work memory 55. At the same time, the address generating circuit 54 reads for the 16 pixel data P ij of the periphery of the interpolation position indicated by the predictive motion vector MV4I' and writes to the work memory 56. On the other hand, as shown in FIG. 8, when the predictive motion vector has a resolution of 1/4 of a pixel, there are 16 interpolation positions. The vector division circuit 51 outputs the signals k (k = 0, 1, 2, ... 15) corresponding to these interpolation positions, to the interpolation circuits 57 and 58. The interpolation circuits 57 and 58 store coefficients F kij corresponding to the signals k and perform the following calculations with the 16 pixel data Pij described above. P = ΣΣP ij × F kij The interpolation circuit 57 uses this value P to generate the predictive block B 0' . In the same manner, the interpolation circuit 58 uses this value P to generate the predictive block B 4' . The adder 59 multiplies the data of the block B 0' inserted from the interpolation circuit 57 by the coefficient (1 - ω), and multiplies the data of the block B 4' input from the interpolation circuit 58 by the coefficient ω, and adds the two together. More specifically, the adder 59 outputs the block B 04' by the linear interpolation of blocks B 0' and B 4' in the same manner as the adder 27 and as shown by the following equation. B 04' = {B 0' × (4-I) + B 4' × I}/4 This predictive block B 04' is input to the correlation calculation circuit 61 of the mode judgment circuit 28. The correlation calculation circuit 61 calculates the mean square error (MSE04') between the block B I and the predictive block B 04' and also calculates the correlation value SEL04' using the following equation. SEL04' = MSE04' - γ Here, γ is a coefficient that satisfies the following condition. 0 < γ Accordingly, the minimum value judgment circuit 46 judges the minimum value of the five correlation values SEL0, SEL4, SEL04, SELDC and SEL04'. Then, when the correlation value SEL04' has been selected as the minimum value, the difference between the predictive block B 04' and the block B I is output to the predictive error signal coding circuit 10 as the signal of the predictive error block. In addition, the motion vector MV04 used in frames 1, 2 and 3 is output to the motion vector mode coding circuit 9. Then, when the predictive mode is mode 5 at this time, the data for this mode 5 is also output to the motion vector mode coding circuit 9. In this manner, in the case of this first embodiment, the modes 1 through 4 described above also have mode 5 added to them. In mode 5, there is one motion vector and so the amount of coding is less than for mode 3. In addition, when mode 4 is not selected, and when the predictive motion vector MV0I' is in the vicinity of the motion vector MV0I and the predictive motion vector MV4I' exists in the vicinity of the motion vector 4I, the value of the coefficient γ is set to a value that is large to a certain extent and the selection of mode 5 is made easier. Accordingly, it is possible for the mean amount of coding to be reduced. In addition, in the case of the first embodiment shown in FIG. 5, at least one portion of the multiplexed data is written to the work memories 55 and 56 as well as the work memories 24 and 25 and so the time that it takes to access the frame memories 1 and 2 is twice that conventionally required. However, it is possible to have the configuration of the second embodiment as shown in FIG. 9. In the case of the second embodiment, the address generating circuits 53 and 54 and the work memories 55 and 56 of the first embodiment shown in FIG. 5 are omitted and the predictive motion vectors MV0I' and MV4I' output from the vector division circuit 51 are respectively supplied to the address generating circuits 21 and 22, and the corresponding data are written to the work memories 24 and 25. The other portions of this configuration are the same as for the case of the first embodiment shown in FIG. 5. In FIG. 9, a vector division circuit 41 judges whether or not the predictive motion vector MV0I' exists in the vicinity of the motion vector MV0I and whether the predictive motion vector MV4I' exists in the vicinity of the motion vector MV4I. Numeral 42 shows a frame counter. When the predictive motion vector MV0I' does not exist in the vicinity of the motion vector MV0I and when the predictive motion vector MV4I' does not exist in the vicinity of the motion vector MV4I, the vector division circuit 41 stops the operation for the generation of the predictive block B 04' by interpolation circuits 47 and 48, and an adder 59. As a result, the selection of modes 1 through 4 is performed in the same manner as in the case of the conventional configuration. On the other hand, when the predictive motion vector MV0I' exists in the vicinity of the motion vector MV0I and when the predictive motion vector MV4I' exists in the vicinity of the motion vector MV4I, then as shown in FIG. 10, pixels of a range that includes both the block B 0 and the predictive block B 0' are read from the frame memory 1 and written to the work memory 24. In the same manner, pixels of a range that includes both the block B 4 and the predictive block B 4' are read from the frame memory 2 and written to the work memory 25. By this, it is possible to reduce the access time with respect to frame memories 1 and 2. Moreover, although it is not indicated in the figure, the coding system codes the mode and the codes modes are used to perform coding of the motion vectors MV0I, MV4I and MV04. In addition, the motion vector is used in the same manner as the coding system for each mode and the calculations are performed in the same manner to determine the predictive block. Furthermore, the sum of the coded predictive error block and the coded block is used to determine the coded block for each block unit. Moreover, in the above description, the predictive vector is used to calculate the data of the interpolation position but instead of performing these calculations, it is also possible to use data of pixels in the position closest to the interpolation position as it is. If this is done, then it is not possible to increase the resolution but the complex calculations are no longer necessary and so the configuration can be simplified. Also, it is possible to not use the mode 3 described above and for only modes 1, 2, 4 and 5 to be used. If this is done, then the image quality will deteriorate when compared to the case when mode 3 is used but there will be no cases when two motion vectors are coded and so the amount of coding can be reduced when compared to the case when mode 3 is used.

Claims: A motion image data compression apparatus comprising: first means (21,24) for dividing an I-th frame, I=1 2,... N-1, between two frames F O and F N of N frames, where N is an integer of 2 or more, of digital motion images, into a block B I formed of a plural number of pixels, for generating the motion vector MVOI of frame F O and F I for each of the divided blocks B I and for generating the block B O that uses the motion vector MVOI to predict the block B I ; and second means (22,25) for generating a motion vector MVNI between the frames F N and F I , for each block B I , and for generating a block B N predicting the block B I , on the basis of the motion vector MVNI; where blocks B O and B N are formed of pixel data of frames F O and F N respectively; characterised by: third means (53-59) 1) for generating motion vectors MVON or MVNO of frame F N and F O for each block B I , 2) for generating a predictive motion vector MVOI' between the frame F O and F I by using said motion vectors MVON or MVNO, 3) for generating a block B O ' predicting the block B I , by using said motion vector MVOI', 4) for generating a predictive motion vector MVNI' between frames F N and F I by using said motion vectors MVON or MVNO, 5) for generating a block B N ' predicting block B I by using the predictive motion vector MVNI', and 6) for generating a block B ON ' being the linear interpolation of blocks B O ' and B N ', fourth means (45) for generating a block B DC from the average value of said block B I , and fifth means (46) for selecting and outputting a block for which the correlation with the block B I is greatest. The motion image data compression apparatus of claim 1, further comprising: sixth means (27) for generating a block B ON formed by the linear interpolation of said blocks B O and B N ' with the fifth means selecting the block out of blocks B O B N B ON B ON ' and B DC for which the correlation with block B I is greatest. The motion image data compression apparatus of claim 1, wherein: said fourth and fifth means configure a mode judgment circuit (28). The motion image data compression apparatus of claim 3, wherein: said first means comprises a first address circuit (21) to determine said block B O as first address data on the basis of the output of a first frame memory and a motion vector detection circuit, and a first work memory (24) that stores first address data output from this circuit, said second means comprising a second address circuit (22) to determine said block B N as second address data on the basis of the output of a second frame memory and said motion vector detection circuit, and a second work memory (25) that stores second address data output from this circuit, said third means comprising third and fourth address generation circuits (53, 54), third and fourth work memories (55, 56) to store third and fourth address data output from these circuits, first and second interpolation circuits (57, 58) that perform linear interpolation calculation of output from these third and fourth work memories, and a first adder (59) that adds outputs of said first and second interpolation circuits, said fourth means comprising a direct current (DC) component calculation circuit (45) provided to said mode judgment circuit (28) and performing the DC component calculations on the basis of a fifth address data output from a fifth address generation circuit (23), and said fifth means comprising a minimum value judgment circuit (46) that judges a minimum value on the basis of an output of said DC calculation circuit (45) and address data output from said first through fourth work memories (21, 22, 23, 53, 54) provided to said mode judgment circuit (28). The motion image data compression apparatus of claim 4, wherein: said mode judgment circuit (28) is provided with a first correlation calculation circuit (44) to calculate a correlation of an output calculated by said DC calculation circuit (45), and second through fifth correlation circuits (41, 42, 43) that calculate correlations of first through fourth data output from said first through fourth work memories (24, 25, 26, 55, 56). The motion image data compression apparatus of claim 4, further comprising: a sixth means (27) to determine a block B ON formed by the linear interpolation of said blocks B O and B N , said fifth means (46) selecting the block out of said block B O , B N , B ON and B DC for which the correlation with block B I is greatest. The motion image data compression apparatus of claim 6, wherein: said sixth means comprises a second adder (27) that determines said block B ON by adding said first and second address data output to said mode judgment circuit (28) from said first and second work memories (55, 56). The motion image data compression apparatus of claim 4, further comprising: a third and fourth address generation circuit (21, 22) configuring said third and fourth means to which predictive motion vector signals are supplied, and further provided with a vector division circuit (51) that supplies an interpolation coefficient to said first and second interpolation circuits (57, 58). The motion image data compression apparatus of claim 8, further comprising: a frame counter (52) that supplies a number of frames of said motion image data to said vector division circuit (51), said vector division circuit (51) being supplied with said number of frames and said motion vector detection circuit (9) being supplied with a detected motion vector. The motion image data compression apparatus of claim 1, wherein: said first means comprises a first address circuit (21) to determine said block B O as first address data on the basis of the output of a first frame memory (1) and a motion vector detection circuit (6), and a first work memory (24) that stores first address data output from this circuit, said second means comprising a second address circuit (22) to determine said block B N as second address data on the basis of the output of a second frame memory (2) and said motion vector detection circuit (6), and a second work memory (25) that stores second address data output from this circuit, said third means comprises a frame counter (42) that counts a number of frames of said motion image signals, a vector division circuit (41) that divides a predictive motion vector on the basis of the value counted by this counter and a motion vector (MV4I, MV0I and MV04) detected by said motion vector detection circuit, an interpolation circuit (47, 48) that performs interpolation calculation on the basis of an output of this division circuit (41) and either of the outputs of said first and second work memories (24, 25), and a first adder (49) that adds outputs of said first and second interpolation circuits (47, 48), said fourth means comprising a direct current (DC) component calculation circuit (45) provided to said mode judgment circuit and performing DC component calculations on the basis of a fifth address data output from a fifth address generation circuit (23), and said fifth means comprising a minimum value judgment circuit (46) that judges a minimum value on the basis of an output of said DC calculation circuit (45) and address data output from said first, second and fifth work memories provided to said mode judgment circuit (28). The motion image data compression apparatus of claim 10, further comprising: a sixth means (27) that determines the block B ON formed by the linear interpolation of block B O and B N , with the fifth means selecting the block out of block B O , B N , B ON , B ON' and B DC for which the correlation with block B I is greatest.

Inventors: NIIHARA TAKAMI, NIIHARA, TAKAMI
Applicants: VICTOR COMPANY OF JAPAN, VICTOR COMPANY OF JAPAN, LTD.
Application year: 1991
Main classification: H04N7
IPC codes: H04N7, G06T9, H04N11, G06T7, H04N1, H03M7