Trimming code setting circuit having high reliability

Abstract: A semiconductor integrated circuit has a trimming code setting circuit so configured that a desired trimming code is set dependently upon whether or not a thin film resistor is cut. The trimming code setting circuit comprises first and second ratio circuits each of which includes a P-channel transistor having a source connected to a high voltage line and a drain connected through a thin film resistor to a low voltage. A gate of the P-channel transistor is biased to allow a predetermined current to flow through the thin film resistor and a source-drain current path of the transistor. A connection node between the drain of the transistor and the thin film resistor forms a voltage output node. The voltage output node of each of the first and second ratio circuits is connected to a comparator, which in turn outputs a logical signal determined on the basis of whether or not the voltage on the voltage output node of the first ratio circuit is higher than the voltage on the voltage output node of the second ratio circuit.

Description: The present invention relates to a semiconductor integrated circuit, and more specifically to a semiconductor integrated circuit having a trimming code setting circuit. In general, in case of setting a reference voltage value or a circuit current value for an analog circuit and other circuits in a semiconductor integrated circuit, a very severe value has often been required as a catalog standard or specification. In such a case, a so-called "trimming code setting circuit" has been required in order to cause the reference voltage value or the circuit current value to be within a range defined by the catalog standard or specification. For example, one typical trimming code setting circuit, which is incorporated in a semiconductor integrated circuit and which the inventor is aware of, includes a current setting circuit composed a P-channel MOS transistor having the source connected to a first high voltage supply line V DD (for example +5V) and the drain connected through a constant current source to a first low voltage supply line V SS (for example, -5V). The gate of the P-channel MOS transistor is connected to the drain of the P-channel MOS transistor itself. The gate of the P-channel MOS transistor of the current setting circuit is connected to a plurality of trimming code setting circuits. Each of the trimming code setting circuits includes a P-channel MOS transistor having the source connected to a second high voltage supply line VDD (for example +5V) and the drain connected through a thin film resistor to a second low voltage supply line V SS (for example, -5V). The gate of the P-channel MOS transistor of each trimming code setting circuit is connected commonly to the gate of the P-channel MOS transistor of the current setting circuit. Therefore, the P-channel MOS transistor of each trimming code setting circuit constitutes a mirror circuit for the P-channel MOS transistor of the current setting circuit. A connection node between the thin film resistor and the drain of the P-channel MOS transistor of each trimming code setting circuit is connected to an input of an inverter, which in turn has an output for supplying a unitary code signal to a predetermined decoder. Therefore, a circuit composed of the P-channel MOS transistor and the thin film resistor of each trimming code setting circuit is connected in parallel to a circuit composed of the P-channel MOS transistor and the thin film resistor of the other trimming code setting circuit or circuits. Here, since the trimming code setting circuits have the same construction, explanation of function and operation will be made on only one of the trimming code setting circuits. As mentioned above, since the P-channel MOS transistor of each trimming code setting circuit is connected in the form of a mirror circuit for the P-channel MOS transistor of the current setting circuit, a predetermined current defined by the constant current source of the current setting circuit will flow through the P-channel MOS transistor of each trimming code setting circuit. Therefore, the series-connected circuit formed of the P-channel MOS transistor and the thin film resistor of each trimming code setting circuit constitutes a so-called ratio circuit. In ordinary cases, the thin film resistor is formed to have a resistance smaller than an ON resistance of the P-channel MOS transistor when the thin film resistor has not yet been cut off. Therefore, when the thin film resistor has not yet been trimmed, namely when the thin film resistor has not yet been cut off, the drain potential of the P-channel MOS transistor of the trimming code setting circuit is sufficiently lower than the logical threshold voltage of the associated inverter, so that the associated inverter generates a high level signal to the associated decoder. On the other hand, when the thin film resistor has been cut off, the drain potential of the P-channel MOS transistor of the trimming code setting circuit becomes higher than the logical threshold voltage of the associated inverter, so that the associated inverter generates a low level signal to the associated decoder. As seen from the above, the trimming code can be set depending upon whether the thin film resistor is cut off or not. Namely, the inverter of the trimming code setting circuit having an uncut thin film resistor outputs a low level signal, and the inverter of the trimming code setting circuit having a cutoff thin film resistor outputs a high level signal. Thus, a plurality of trimming code setting circuits cooperate to generate a plural-bit trimming code as a whole. Incidentally, the cutoff of the thin film resistor is attained by causing a current to flow through a thin film resistor to be cut off so that the thin film resistor is fused off, or by cutting the thin film resistor to be cut off by means of a laser beam. In the former case, the drain of the P-channel transistor associated to the thin film resistor is previously connected to a pad formed of for example aluminum, and in a wafer testing process using for example a tester, a voltage is applied between the low voltage supply terminal and a pad connected to the drain of the P-channel transistor associated to a thin film resistor to be cut off, so that the thin film resistor is cut off by an electric current flowing through the thin film resistor itself. In the semiconductor integrated circuit incorporating therein the above mentioned trimming code setting circuit, once the trimming code has been set, the trimming code has to be permanently constant in a proper operation of the semiconductor integrated circuit after the trimming code has been set. In other words, a high degree of reliability is required. In practice, however, in some cases the cutoff of the thin film resistor is incomplete, and in the way of the operation of the semiconductor integrated circuit, the trimming code becomes defective or faulty. This is one important cause lowering the reliability of the semiconductor integrated circuit. A semiconductor integrated circuit as mentioned above comprising a single ratio circuit for generating a bit value of a trimming code is disclosed in Patents Abstracts of Japan, Vol. 13, No. 551 (E-857), December 8, 1989 (& JP-A-01228144); this circuit comprises the features according to the preamble of claims 1 and 2, respectively. It is an object of the invention to provide a trimming code setting circuit which has overcome the defects mentioned above and which is capable of generating a trimming code even if cutoff of a thin film resistor is incomplete. This object is achieved by semiconductor integrated circuits as defined in claims 1 and 2, respectively; the dependent claim relates to a further development of the invention. The above and other objects, features and advantages of invention will be apparent from the following descripti of preferred embodiments of the invention with reference to the accompanying drawings. Figure 1 is a circuit diagram of a first embodiment of the trimming code setting circuit in accordance with the present invention; and Figure 2 is a circuit diagram of a second embodiment of the trimming code setting circuit in accordance with the present invention. Referring to Figure 1, there is shown a circuit diagram of a first embodiment of the trimming code setting circuit in accordance with the present invention, which circuit is incorporated in a semiconductor integrated circuit. In Figure 1, three trimming code setting circuit portions 30A, 30B and 30C are shown. Since these trimming code setting circuit portions have the same circuit construction, the internal circuit of only the trimming code setting circuit portion 30A is shown and described on construction and on operation. In addition, since the three trimming code setting circuit portions 30A, 30B and 30C are provided, the shown circuit can generate three bits of trimming code. If only one bit of trimming code is required, the trimming code setting circuit portions 30B and 30C are omitted. On the other hand, if more than three bits of trimming code are required, a required number of trimming code setting circuit portions having the same circuit construction as the trimming code setting circuit portion 30A are added in parallel to the trimming code setting circuit portion 30A. The shown circuit also includes a current setting circuit composed of a P-channel MOS transistor 1 having the source connected to a first high voltage supply terminal V DD 51 (for example +5V) and the drain connected through a constant current source 2 to a first low voltage supply terminal V SS 52 (for example, -5V). The gate of the P-channel MOS transistor 1 is connected to the drain of the P-channel MOS transistor 1 itself. The trimming code setting circuit portion 30A includes a pair of ratio circuits. The first ratio circuit is composed of a P-channel MOS transistor 3 having the source connected to a second high voltage supply terminal VDD 53 (for example +5V) and the drain connected through a thin film resistor 6 to a second low voltage supply line V SS 54 (for example, -5V). The gate of the P-channel MOS transistor 3 is connected to the gate of the P-channel MOS transistor 1 of the current setting circuit. The second ratio circuit is composed of a P-channel MOS transistor 4 having the source connected to the second high voltage supply terminal V DD 53 and the drain connected through a thin film resistor 7 to the second low voltage supply line V SS 54. The gate of the P-channel MOS transistor 4 is connected to the gate of the P-channel MOS transistor 1 of the current setting circuit. As seen from the above description and from Figure 1, each of the P-channel MOS transistors 3 and 4 constitutes a current mirror circuit for the P-channel MOS transistor 1 of the current setting circuit. A connection node between the thin film resistor 6 and the drain of the P-channel MOS transistor 3 is connected to a non-inverting input of a comparator 5. A connection node between the thin film resistor 7 and the drain of the P-channel MOS transistor 4 is connected to an inverting input of the comparator 5. The comparator 5 has an output for supplying a unitary code signal to a decoder not shown. In the above mentioned circuit, the resistance R₁ of the thin film resistor 6 and the resistance R₂ of the thin film resistor 7 are set to fulfil the following relation: R 1 > R 2 The setting of the trimming code in the above mentioned circuit is achieved depending upon whether the thin film resistor 7 is cut off or not. First, consider the case in which the thin film resistor 7 is not cut off. As mentioned above, since each of the P-channel MOS transistors 3 and 4 is connected in the form of a mirror circuit to a the P-channel MOS transistor 1, each of the P-channel MOS transistors 3 and 4 is controlled to pass the same amount of current defined by the constant current source 2. Accordingly, since it is set that R₁ > R₂ as mentioned above, the following inequality is established between the drain potential V₁ of the P-channel MOS transistor 3 and the drain potential V₂ of the P-channel MOS transistor 4: V 1 > V 2 As mentioned above, since the drain potential V₁ of the P-channel MOS transistor 3 and the drain potential V₂ of the P-channel MOS transistor 4 are connected to the non-inverting input and the inverting input of the comparator 5, respectively, the voltage difference between V₁ and V₂ is amplified by the comparator 5, and the comparator 5 outputs a high level signal as one bit of trimming code. On the other hand, if the thin film resistor 7 is cut off, the following inequality is established between the drain potential V₁ of the P-channel MOS transistor 3 and the drain potential V₂ of the P-channel MOS transistor 4: V 1 < V 2 Therefore, the comparator 5 outputs a low level signal as one bit of trimming code. In general, the constant current source is set to flow a constant current on the order of 10 µA for the purpose of saving a consumption current. In the conventional circuit, therefore, if a leakage current of not less than 10 µA flows through the cutoff thin film resistor, the trimming code changes, with the result that it is judged to be a fault. In other words, if leakage resistance of the cutoff thin film resistor becomes less than 500 kΩ, the semiconductor integrated circuit is discriminated to be defective. In the trimming code setting circuit in accordance with the present invention, on the other hand, even if a leakage current occurs in the cutoff thin film resistor 7, the semiconductor integrated circuit is not discriminated to be defective unless the leakage resistance of the cutoff thin film resistor 7 becomes smaller than the resistance of the thin film resistor 6. In ordinary cases, since a thin film resistor of the ratio circuit is set to have a resistance on the order of 100 Ω, unless the leakage resistance of the cutoff thin film resistor 7 becomes 100 Ω or less, the semiconductor integrated circuit is not discriminated to be defective. This means that the semiconductor integrated circuit in accordance with the present invention is not discriminated to be defective unless there flows a leakage current 5000 times as large as the leakage current which has caused to be discriminated to be defective in the conventional example. However, the resistance of the incomplete cutoff thin film resistor will in no way become lower than 100 Ω, and therefore, the semiconductor integrated circuit in accordance with the present invention never becomes defective in the way of an operation of the semiconductor integrated circuit. Turning to Figure 2, there is shown a circuit diagram of a second embodiment of the trimming code setting circuit in accordance with the present invention, which circuit is incorporated in a semiconductor integrated circuit. The shown circuit includes a current setting circuit composed a P-channel MOS transistor 8 having the source connected to a first high voltage supply terminal V DD 55 and the drain connected through a constant current source 9 to a first low voltage supply terminal V SS 56. The gate of the P-channel MOS transistor 8 is connected to the drain of the P-channel MOS transistor 8 itself. The shown circuit also includes one trimming code setting circuit portion 40, which in turn includes a P-channel MOS transistor 10 having the source connected to a second high voltage supply terminal V DD 58 and the gate connected to the gate of the P-channel MOS transistor 8. Therefore, the P-channel MOS transistor 10 constitutes a current mirror circuit for the P-channel MOS transistor 8 of the current setting circuit. The drain of the P-channel MOS transistor 10 is connected to a differential amplifier circuit, which is composed of a P-channel MOS transistor 11 having the source connected to the drain of the P-channel MOS transistor 10 and the drain connected through a thin film resistor 14 to a second low voltage supply line V SS 59, and another P-channel MOS transistor 12 having the source connected to the drain of the P-channel MOS transistor 10 and the drain connected through a thin film resistor 15 to the second low voltage supply line V SS 59. Gates of the P-channel MOS transistors 11 and 12 are connected in common to a predetermined voltage terminal 57. A connection node between the thin film resistor 14 and the drain of the P-channel MOS transistor 11 is connected to a non-inverting input of a comparator 13. A connection node between the thin film resistor 15 and the drain of the P-channel MOS transistor 12 is connected to an inverting input of the comparator 13. The comparator 13 has an output for supplying a unitary code signal to a decoder not shown. Similarly to the first embodiment, the resistance R₃ of the thin film resistor 14 and the resistance R₃ of the thin film resistor 15 are set to fulfil the following relation: R 3 > R 4 The setting of the trimming code in this second embodiment is achieved depending upon whether the thin film resistor 15 is cut off or not. Since the second embodiment operates similarly to the first embodiment, description of the operation of the second embodiment will be omitted. However, it should be noted that since the P-channel MOS transistors 11 and 13 form a differential amplifier having a corresponding gain, stability of the trimming code setting circuit is further enhanced by cooperation of the amplification function of the comparator and the amplification function of the differential amplifier.

Claims: A semiconductor integrated circuit having a trimming code setting circuit for setting a trimming code dependent on whether or not a thin film resistor is cut comprising: a first ratio circuit including a first MOS transistor (3) having its main current path connected in series with a thin film resistor (R₁), said series connection being connected at one end to a high voltage source (V DD ) and at the other end via said film resistor (R₁) to a low voltage source (V SS ), said first transistor (3) being biased to allow a predetermined current to flow through said series connection (3, R₁), the connection node between said main current path of said first transistor (3) and said film resistor (R₁) forming a voltage output node, characterized by a second ratio circuit comprising a second MOS transistor (4) and a second thin film resistor (R₂) connected in series, having a voltage output node analogous to that of the first ratio circuit and being connected parallel to said first ratio circuit, a current setting circuit comprising a further MOS transistor (1) having its main current path connected at one end to the high voltage source (V DD ) and its other end via a constant current source (2) to the low voltage source (V SS ), the gate of said further MOS transistor (1) being connected to one end of its main current path, wherein the gates of the transistors (3, 4) of the first and second ratio circuits are connected to the gate of the further MOS transistor (1), and a comparator (5) having a non-inverting input (+) connected to the voltage output node of the first ratio circuit and an inverting input (-) connected to the voltage output node of the second ratio circuit, said comparator (5) operating to output to a decoder a logical signal determined on the basis of whether or not the voltage on said voltage output node of said first ratio circuit is higher than the voltage on said voltage output node of said second ratio circuit, said logical signal defining one bit of a trimming code. A semiconductor integrated circuit having a trimming code setting circuit for setting a trimming code dependent on whether or not a thin film resistor is cut comprising: a first ratio circuit including a first MOS transistor (11) having its main current path connected in series with a thin film resistor (R₃), said series connection being connected at one end thereof via said film resistor (R₃) to a low voltage source (V SS ), said first transistor (11) being biased to allow a predetermined current to flow through said series connection (11, R₃), he connection node between said main current path of said first transistor (11) and said thin film resistor (R₃) forming a voltage output node, characterized by a second ratio circuit, comprising a second MOS transistor (12) and a second thin film resistor (R₄) connected in series, having a voltage output node analogous to that of the first ratio circuit and being connected parallel to said first ratio circuit, a current setting circuit comprising a further MOS transistor (8) having its main current path connected at one end to a high voltage source (V DD ) and its other end via a constant current source (9) to the low voltage source (V SS ), the gate of said further MOS transistor (8) being connected to one end of its main current path, a current mirror circuit comprising another MOS transistor (10), the gate of which being connected to the gate of said further MOS transistor (8) of said current setting circuit and having its main current path connected at one end to the high voltage source (V DD ) and at the other end in common to the main current paths of the transistors (11, 12) of the first and second ratio circuits, wherein the gates of the transistors (11, 12) of the first and second ratio circuits are connected to a terminal (57) to receive a predetermined voltage, and a comparator (13) having a non-inverting input (+) connected to the voltage output node of the first ratio circuit and an inverting input (-) connected to the voltage output node of the second ratio circuit, said comparator (13) operating to output to a decoder a logical signal determined on the basis of whether or not the voltage on said voltage output node of said first ratio circuit is higher than the voltage on said voltage output node of said second ratio circuit, said logical signal defining one bit of a trimming code. A semiconductor integrated circuit as claimed in claims 1 or 2, wherein said thin film resistor (R₁, R₃) of said first ratio circuit is a fixed resistor having a resistance higher than that of said thin film resistor (R₂, R₄) of said second ratio circuit when said thin film resistor of said second ratio circuit is untrimmed so that after said thin film resistor of said second ratio circuit is trimmed, the resistance of said thin film resistor of said first ratio circuit becomes smaller than that of the trimmed thin film resistor of said second ratio circuit.

Inventors: HINOOKA KIYONOBU, HINOOKA, KIYONOBU
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: H01L27
IPC codes: H01L27, H01L21