Method of manufacturing a solid-state image sensing device

Abstract: The solid-state image sensing device comprises an operating voltage (e.g. overflow drain voltage) generating circuit formed on the semiconductor substrate. The circuit includes plural resistors connected in series between two voltage supply terminals; plural fuses (109-114) connected in parallel to the resistors (R, 2R, 4R, 8R, 16R, 32R, 63 x 7R/8), respectively; and plural voltage selecting signal input terminals (101-108). In response to an external voltage selecting signal, since some parallel-connected fuses are melted away, a desired voltage lying within a predetermined range can be obtained at one of the series-connected resistors. Therefore, it is unnecessary to indicate the operating voltage on the device or to directly use the generated voltage for device activation.

Description: BACKGROUND OF THE INVENTION The present invention relates to a method of manufacturing a solid-state image sensing device. In the solid-state image sensing device, the input condition thereto changes according to the luminance of a subject to be sensed. Therefore, when a subject of a high luminance is image-sensed, since an excessive electric charge transduced from light energy by the photodiode section of the device leaks to the vertical register, so that a phenomenon can be observed such that light spreads on a monitor picture from a high luminance position to a low luminance position. This phenomenon is referred to as blooming phenomenon. To prevent this phenomenon, an overflow drain is conventionally provided for the image sensing device, as shown, for example, in GB-A-2 177 542. Fig. 5 is a sectional diagram of a solid-state image sensing device having an overflow drain, which is conventionally used, as in, for example, GB-A-2 177 542. An n region 20 is formed in the surface of a p-type silicon substrate 10. A p-n junction formed by the n region and the substarate forms a photo diode. If light 30 is irradiated at this photo diode, electric charges are generated at the photo diode and in response to open/close state of a transfer gate 50, these electric charges are moved to a CCD section 40 which stores and transferrs the charges. At the other side of the photo diode, an overflow drain 60 is provided. Amount of excessive electric charges is controlled by a voltage applied to a gate 70. Fig. 6 shows the relationship between the blooming rate and the voltage V OFD applied to the gate provided for the overflow drain. In the drawing, when the overflow drain voltage V OFD is sufficiently high as within a range A, since the blooming phenomenon can be sufficiently suppressed, it is possible to extremely reduce the blooming rate in the case where high luminance subject is image-sensed. In contrast, when the overflow drain voltage V OFD is low as within a range B, since the blooming phenomenon cannot be sufficiently suppressed, the blooming phenomenon is observed. As described above, the lower limit of the overflow drain voltage V OFD at which the blooming phenomenon can be suppressed is a point C corresponding to a boundary between the two ranges A and B. Therefore, the range A of the overflow drain voltage V OFD is a practical voltage range. On the other hand, the overflow drain voltage V OFD exerts an influence upon the saturation characteristics in relation to the quantity of electric charge to be accumulated. Fig. 7 shows the relationship between the overflow drain voltage V OFD and the saturation voltage obtained by converting the quantity of accumulated electric charge. To increase the saturation voltage, it is desirable to reduce the overflow drain voltage V OFD . However, since there exists a limit of the quantity of accumulated electric charge, it is impossible to increase the electric charge quantity beyond the limit, even if the voltage V OFD is reduced unnecessarily. On the other hand, it is required to determine the saturation voltage to be higher than a white-clip level when the image signals are processed. Therefore, although it is effective to determine a higher overflow drain voltage V OFD in order to sufficiently suppress the blooming phenomenon, since the lower overflow drain voltage or the higher saturation voltage is required for signal processing, the overflow drain voltage V OFD is usually set to a point E higher than the lower limit point C. Accordingly, the saturation voltage D at a point E of the overflow drain voltage V OFD is lower than the voltage F at the point C of V OFD . As described above, the overflow drain voltage V OFD is adjusted according to the usage. Further, since this voltage V OFD differs according to the manufacturing process, the voltage V OFD ranges between several volts and tens and several volts. In practice, therefore, each solid-state image sensing device is inspected at the wafer stage in order to detect an optimum overflow drain voltage V OFD . However, it is necessary to indicate or store the detected optimum voltage V OFD by use of some means. Or else, the same inspection work must be repeated at the stage of device forming process. Conventionally, therefore, an optimum overflow drain voltage V OFD is indicated on a predetermined position 702 of a casing 701 of a solid-state image sensing device, as shown in Fig. 8, in order to eliminate the waste inspection work. That is, when the solid-state image sensing device is assembled in an apparatus (e.g. camera), an optimum overflow drain voltage is applied to the image sensing device by reading the previously indicated V OFD . The prior-art method of indicating various optimum voltages by stamping work, for instance is very troublesome in mass-production process, in particular. This is because since the optimum overflow drain voltage V OFD of the devices differ from each other as already explained, the optimum voltages must be classified into about several tens of ranges at 0.5V intervals in general before stamping the indication values. Where the above-mentioned troublesome work is performed by workers, the efficiency is extremely low and further there exists a problem in that error is inevitably produced during the classification and stamping work. To overcome this problem, although it may be possible to automatize the above-mentioned work, the automation system may be extremely high in both development and manufacturing cost, because the optimum values inspected in the inspection process must be stored in relation to the corresponding devices and further stamped on the corresponding devices. The similar problems arise when other device operating voltages (e.g. reset voltage) are inspected, classified and stamped, as well as the overflow drain voltage. SUMMARY OF THE INVENTION Therefore, the object of the present invention is to provide a method of manufacturing a solid-state image sensing device which can reduce the optimum operating voltage indicating work, without use of any automatic voltage indicating system. To achieve the above-mentioned object, the present invention provides a method of manufacturing a solid-state image sensing device according to claim 1. In the method of manufacturing a solid-state image sensing device according to the present invention, whenever an external voltage selecting signal is inputted to the device, the voltage generating means generates a voltage corresponding to the inputted voltage selecting signal and lying within a predetermined range. Since the above-mentioned voltage generating means is formed in the solid-state image sensing device, a required operating voltage can be generated by the device itself. Therefore, it is unnecessary to indicate the voltage on the device casing, and further it is possible to directly use the generated voltage for device activation. Here, the voltage generated by the voltage generating means is preferably the voltage applied to the overflow drain of the device. When the voltage generating means is a resistance divider circuit, since some fuses are melted in response to the voltage selecting signal inputted to the device from outside the device, the resistance between a voltage supply terminal and a ground terminal changes, so that a voltage corresponding to the inputted voltage selecting signal is generated at the connection end of the series-connected resistors. As described above, since the method of manufacturing a solid-state image sensing device according to the present invention provides means for generating a voltage determined in response to a voltage selecting signal inputted to the device from outside, it is possible to generate a necessary voltage from the device itself, thus eliminating the indication of device voltage on the device surface. Therefore, it is unnecessary to develop a new automatic voltage indicating system for automatically stamping operating voltages on the device casings, by spending much development cost therefor. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram showing a configuration of an embodiment of the voltage generating circuit of the solid-state image sensing device for manufacture according to the method of the present invention; Fig. 2 is an enlarged plan view showing a fuse and a resistor formed on a semiconductor substrate of the device; Fig. 3 is a diagram showing an equivalent circuit of Fig. 1; Fig. 4 is a graphical representation showing the relationship between the fusing cord C and the overflow drain voltage V OFD in the voltage generating circuit of the solid-state image sensing device shown in Fig. 1; Fig. 5 is a sectional view of a conventional solid-state image sensing device having an overflow drain similar to that shown in GB-A- 2 177 542; Fig. 6 is a graphical representation showing the relationship between the overflow drain voltage V OFD and the blooming rate in the ordinary solid-state image sensing device; Fig. 7 is a graphical representation showing the relationship between the overflow drain voltage V OFD and the saturation voltage of the ordinary solid-state image sensing device; and Fig. 8 is a perspective view showing a casing of a prior-art solid-state image sensing device. DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described hereinbelow with reference to the attached drawings. The method of manufacturing a solid-state image sensing device according to the present invention provides means for generating a voltage lying within a predetermined range. This voltage generating means is so controlled as to generate an optimum overflow drain voltage V OFD in response to an external signal. Fig. 1 shows the voltage generating means provided for the solid-state image sensing device in the method according to the present invention. The voltage generating means is a resistance divider circuit for generating any required voltage. A plurality of resistors R, 2R, 4R, 8R, 16R, 32R and (63 × 7/8)R are connected in series between a voltage supply terminal 101 and a ground 120. The resistance values of these resistors 2R to 32R are determined into two's multiple arrangement. In addition, each of a plurality of fuses 109 to 114 are connected in parallel to each of the resistors R to 32R. In more detail, the resistor R and the fuse 109 are both connected between two fusing terminals 102 and 103; the resistor 2R and the fuse 110 are connected between two fusing terminals 103 and 104; the resistor 4R and the fuse 111 are both connected between two fusing terminals 104 and 105; the resistor 8R and the fuse 112 are both connected between two fusing terminals 105 and 106; the resistor 16R and the fuse 113 are both connected between two fusing terminals 106 and 107; and the resistor 32R and the fuse 114 are both connected between two fusing terminals 107 and 108, respectively. Further, an overflow drain voltage V OFD required to be generated can be outputted through an output terminal 108. Fig. 2 is an enlarged view showing the resistor R and the fuse 109 both formed on a semiconductor substrate, by way of example. In the drawing, n + diffusion layers 203 and 204 are formed on both ends of a gate region 202, and an n diffusion layer 201 constituting the resistor R is formed between the two n + diffusion layers 203 and 204. These two n + diffusion layers 203 and 204 are connected to two aluminium wires 205 and 206 via two contacts 203 and 204, respectively at each one end thereof, and the two fusing terminals 102 and 103 are formed on the wires 205 and 206, respectively at each other end thereof. The two aluminium wires 205 and 206 are connected to each other via a bridge wire 203 formed with a narrower portion 209. Since being high in resistance, this narrower portion 209 corresponds to a fuse 109 melted away when a predetermined high voltage is applied between the two fusing terminals 102 and 103. In the resistance divider circuit as described above, any desired voltages can be outputted through the output terminal 108 by selecting the resistance of the series-connected resistors R to 32R as follows: For instance, the assumption is made that a voltage of 10.00V is required to be outputted through the output terminal 108 when a supply voltage of 15.00V is applied to the voltage supply terminal 101, as shown by an equivalent circuit in Fig. 3. In this example, the following formula (1) can be established: 5.00 V : 10.00 V = xR : (63 × 7/8)R where xR denotes the resistance required between the voltage supply terminal 101 and the output terminal 108. Therefore, the resistance of xR is 27.5625 or approximately 28 as a two's multiple value. If six resistors R to 32R are considered as 6-bits and therefore indicate integers from 0 to 63, the third, fourth and fifth resistors 4R, 8R and 16R are to be selected in order to obtain a resistance 28R between the voltage supply terminal 101 and the output terminal 108. That is, the fuses 111, 112 and 113 must be melted away to allow current to flow through the three resistors 4R, 8R and 16R. Therefore, these three fuses 111, 112 and 113 are melted by passing fusing current between the two fusing terminals of 104 and 105, 105 and 106, and 106 and 107, respectively. In general, a sum total resistance to be selected is referred to as fusing code C. The fusing code C required to generate a desired voltage (i.e. an optimum overflow drain voltage V OFD ) through the output terminal 108 can be expressed as C = (15.00 - V OFD ) × 63 × 7/(V OFD × 8) Fig. 4 shows the relationship between the fusing code C as expressed by the formula (2) and the overflow drain voltage V OFD . Therefore, it is possible to easily obtain any required fusing code C by use of the graph as shown in Fig. 4. Fig. 4 indicates that the voltage range obtainable through the output terminal 108 is from 7 to 15 volts. However, this voltage range can be changed easily by adjusting the supply voltage applied to the voltage supply terminal 101 and the resistances of the respective resistors. As described above, in the embodiment of the present invention, it is possible to generate any desired voltages through the output terminal 108 by passing fusing current between some pairs of the fusing terminals from the outside to melt some fuses from 109 to 114, so that some resistors from R to 32R can be selected. Therefore, it is possible to generate any optimum overflow drain voltage V OFD determined during the inspection process at the wafer stage, inside the device. Accordingly, since an optimum voltage applied to the overflow drain of the device can be easily known, it is unnecessary to inspect the same optimum voltage again at the stage where the wafer is manufactured into the device or to develop an automatic voltage indicating system at the expense of high cost, thus reducing the inspection time and the device cost. The above embodiment has been described only by way of example, without limiting the present invention thereto. For instance, the voltage generating means is not limited to only the resistance divider circuit as shown in Fig. 1, but any voltage generating means for generating any required operating voltages in response to external signals can be adopted. Further, the generated voltage is not limited to only the overflow drain voltage, but the reset voltage can be generated. Further, it is not necessarily required that the device is provided with means for outputting the generated voltage externally. That is, it is possible to directly apply the generated voltage to the overflow drain within the device itself. In this case, it is also possible to reduce the device cost, without need of any automatic voltage indicating system. Reference signs in the claims are intended for better understanding and shall not limit the scope.

Claims: A method of manufacturing a solid-state image sensing device having: a) photoelectric transducing means (10, 20) for generating electric charges in response to incident light intensity; b) charge transferring means (40) for accumulating and transferring electric charges generated by said photoelectric transducing means (10, 20); c) an overflow drain (60) to drain excessive charge; and d) voltage generating means connected to said overflow drain (60), for generating an overflow drain voltage (V OFD ) to be applied to said overflow drain (60); said method comprising the steps of setting the overflow drain voltage (V OFD ) to have a selected value (E) lying in a range (A) sufficiently high to suppress blooming when the solid-state image sensing device senses a high luminance subject and sufficiently low for the saturation voltage (D) of the photoelectric transducing means (10, 20) at the selected value (E) of the overflow drain voltage (V OFD ) to be higher than a white-clip level when image signals are processed, by applying external signals to said voltage generating means to generate the selected value of the overflow drain voltage (V OFD ). A method according to claim 1, wherein said step of applying external signals includes melting one or more of a plurality of fuses (109-114) of a voltage divider circuit (R-32R, 101 - 114) included in said voltage generating means and having (i) a plurality of resistors (R-32R) connected in series between voltage supply terminals (101, 120), a plurality of fuses (109-114) being respectively connected in parallel to said plurality of resistors, and (ii) a plurality of voltage selecting signal input terminals (102-108) respectively provided between two ends of each of said fuses to receive the externally provided voltage selecting signal; said melting step being conducted by applying a voltage selecting signal to selected ones of the voltage selecting signal input terminals (102-108), thus changing the resistance between the voltage supply terminals (101, 120) to generate the selected value of the overflow drain voltage (V OFD ).

Inventors: HONJO ATSUSHI, TOKITOU YOSHIHIKO, HONJO, ATSUSHI, TOKITOU, YOSHIHIKO
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: H01L21
IPC codes: H04N3, H01L27, H01L21, H04N5, H01L23