Thin film field effect transistor array for use in active matrix liquid crystal display

Abstract: A thin film field effect transistor array comprises a plurality of parallel gate bus lines formed on a transparent insulative substrate, and a plurality of parallel drain bus lines formed on the transparent insulative substrate so as to intersect the gate bus lines. A plurality of pixel electrodes are each formed in proximity of a corresponding one of intersections between the gate bus lines and the drain bus lines, and a plurality of thin film field effect transistors are each formed in proximity of a corresponding one of intersections between the gate bus lines and the drain bus lines. Each of the thin film field effect transistors is connected to a corresponding one of the pixel electrodes. A plurality of storage capacitors are each formed in proximity of and connected in parallel to a corresponding one of the pixel electrodes. Each of the storage capacitors is formed of a stacked structure having at least first, second and third level capacitor electrodes which are stacked in the named order and separated from each other by an intervening insulating layer. At least one of the first, second and third level capacitor electrodes is connected to a corresponding one of the gate bus lines.

Description: The present invention relates to an active matrix liquid crystal display, and more specifically to a thin film field effect transistor array used in the active matrix liquid crystal display and having a storage capacitance formed by utilizing a gate bus line. At present, liquid crystal displays have been focused as a flat display panel for portable computers and wall mounting type television displays. In particular, active matrix type liquid crystal displays composed of an array of thin film field effect transistors formed on a glass plate and each used as a switching element for an associated pixel, have been expected for application to the television displays and others, since they have possibility of a full color display. Therefore, the active matrix type liquid crystal displays are being actively studied and developed by many research organizations. In this active matrix type liquid crystal display, a high picture quality and a high definition are current important problems. For this purpose, a method of providing a storage capacitance in parallel with a pixel capacitance has been known. The storage capacitance can be realized either by forming a storage capacitance line independently of the thin film field effect transistor, or by utilizing the gate bus line of a preceding stage thin film field effect transistor. The latter is very effective, since it is not necessary to provide, within each pixel, an opposing electrode and a bus line for the storage capacitance, and since it is possible to avoid increase of manufacturing processes. One example of the storage capacitance realized by utilizing the gate bus line has been proposed by E. Takeda et al in 1988 INTERNATIONAL DISPLAY RESEARCH CONFERENCE, pages 155-158. In this case, the gate electrode of a preceding stage thin film field effect transistor is extended to overlap with a succeeding stage pixel. Here, in order to obtain a high quality of displayed image by preventing flicker and/or crosstalk, it is necessary to provide the storage capacitance as large as possible. However, if the storage capacitance is made large in the above mentioned prior art storage capacitance realized by utilizing the gate bus line, an area of the electrode for the storage capacitance must be inevitably made large, with the result that an aperture ratio in the pixel matrix section decreases. This means that a bright image having high contrast cannot be obtained. A thin film field effect transistor array according to the preamble of claim 1 is disclosed in JP-A-60 230 117. This document relates to a liquid crystal display device which has a relatively high aperture rate by forming a storage capacitor in a multilayered structure in which a minus electrode side is sandwiched from both sides. It is an object of the invention to provide an active matrix type liquid crystal display which has overcome the above mentioned defect of the conventional one. It is another object of the invention to provide a thin film field effect transistor array used in an active matrix liquid crystal display, which has a structure capable of having a large storage capacitance, with reducing or minimizing the decrease of the aperture ratio which would be caused by increase of the storage capacitance in the prior art. These objects are achieved by thin film field effect transistor arrays as defined in claim 1; the dependent claims relate to further developments of the invention. Figure 1 is a circuit diagram of a general active matrix liquid crystal display panel, in which a storage capacitance is formed in parallel to each pixel capacitance; Figure 2A is a diagrammatic partial layout pattern diagram of the conventional thin film field effect transistor array used in the active matrix liquid crystal display, in which a storage capacitance is formed by utilizing the gate bus line; Figure 2B is a diagrammatic partial sectional view taken along the line A - A in Figure 2A; Figure 3A is a diagrammatic partial layout pattern diagram of a first embodiment of the thin film field effect transistor array in accordance with the present invention and used in the active matrix liquid crystal display; Figure 3B is a diagrammatic partial sectional view taken along the line B - B in Figure 3A; Figure 4A is a diagrammatic partial layout pattern diagram of a second embodiment of the thin film field effect transistor array in accordance with the present invention and used in the active matrix liquid crystal display; Figure 4B is a diagrammatic partial sectional view taken along the line C - C in Figure 4A. Referring to Figure 1, there is shown a circuit diagram of a general active matrix liquid crystal display panel, in which a storage capacitor is formed in parallel to each pixel capacitor. The active matrix liquid crystal display panel comprises a number of horizontal drive lines or gate bus lines 10, and a number of vertical drive lines or drain bus lines 12 intersecting the gate bus lines 10, so that a matrix is formed by cooperation of the gate bus lines 10 and drain bus lines 12. On each of intersecting points between the gate bus lines 10 and the drain bus lines 12, one pixel is formed. Namely, on each of the intersecting points between the gate bus lines 10 and the drain bus lines 12, one thin film transistor 14 is formed, which includes a drain 16 connected to a corresponding drain bus line 12, a gate 18 connected to a corresponding gate bus line 10 and a source 20 connected to a corresponding individual or pixel transparent electrode 22 and a storage capacitor 24. Referring to Figure 2A, there is shown a diagrammatic partial layout pattern diagram of the conventional thin film field effect transistor array used in the active matrix liquid crystal display, which is based on the above mentioned technical conception proposed by E. Takeda et al in 1988 INTERNATIONAL DISPLAY RESEARCH CONFERENCE, pages 155-158. Figure 2B is a diagrammatic sectional view taken along the line A - A in Figure 2A. In Figures 2A and 2B, elements similar to those shown in Figure 1 are given the same Reference Numerals, and when elements having the same function should be distinguished from each other, the suffix "A" or "B" will be added to the Reference Numerals. In Figure 2A, each of the thin film transistors 14 has a gate electrode 30, a drain electrode 32 and a source electrode 34, all of which are formed of for example chromium. The source electrode 34 is connected to a corresponding pixel electrode 22 through a plurality of contact holes 36. The drain electrode 32 is integral with and continuous to the drain bus line 12, which is also formed of for example chromium. The storage capacitor is formed by the pixel electrode 22 and an storage capacitor electrode 38 which is formed of an extension of the gate bus line 10. As shown in Figure 2B, the storage capacitor electrode 38 and hence the gate bus line 10 (not shown in Figure 2B) are formed on a glass plate 40, and a first insulator layer 42, a second insulator layer 44 and a surface protection layer 46 are also deposited on the glass plate 40 in the named order so as to cover the storage capacitor electrode 38 and hence the gate bus line 10. Furthermore, the pixel electrode 22 is formed on the surface protection layer 46. Accordingly, the storage capacitor is formed by the pixel electrode 22 and the storage capacitor electrode 38 which are separated by the three-layer insulator. Another glass plate 48 is provided separately from the glass plate 40. The glass plate 48 has a common transparent electrode 50 formed to cover a surface of the glass plate 48, and a color filter 52 located selectively on the common transparent electrode 50. Liquid crystal 52 is filled in a space formed between the glass plates 40 and 48. In the above mentioned structure, it would be readily understood that the storage capacitor is formed between the storage capacitor electrode 38 and a portion of the pixel electrode 22 that is overlapped or blinded by the storage capacitor electrode 38. Therefore, if an area of the storage capacitor electrode 38 is increased in order to increase the capacitance of the storage capacitor, the area of the portion of the pixel electrode 22 overlapped or blinded by the storage capacitor electrode 38 is correspondingly inevitably increased. As a result, the aperture ratio correspondingly lowers. Here, explanation will be made about a basic operation of the active matrix liquid crystal display having the array of thin film field effect transistors each having the storage capacitor formed by utilizing the gate bus line. A scanning pulse is sequentially supplied to the gate bus lines 10, for example in the order of the gate bus lines 10 → 10A → 10B in Figure 2A, so that only thin film transistors receiving the scanning pulse are turned on so as to write a signal appearing on a corresponding drain bus line, to an associated pixel electrode. Now, assume that a pulse is supplied to the gate bus line 10A. At this time, a voltage supplied through the drain bus line 12 is written to the pixel electrode 22A, so that an electric charge is stored in a storage capacitor formed between the storage capacitor electrode 38A and a portion of the pixel electrode 22A opposing to the storage capacitor electrode 38A, and in a pixel capacitor formed between the pixel electrode 22A and the common electrode 50 opposing to the pixel electrode 22A. Thereafter, the pulse is removed from the gate bus line 10A and applied to the gate bus line 10B, so that all the thin film transistors connected to the gate bus line 10A are turned off and the gate bus line 10A itself is brought to a constant voltage. On the other hand, the common electrode is maintained at a constant voltage. Therefore, after the thin film transistors connected to the gate bus line 10A are turned off, a voltage between the pixel electrode 22A and the common electrode 50 is unchanged, and a voltage between the pixel electrode 22A and storage capacitor electrode 38A is also unchanged. As a result, a constant voltage continues to be applied to the liquid crystal. This voltage is maintained until the pulse is supplied to the gate bus line 10A, again. Thus, one two-dimensional image can be displayed in the liquid crystal display panel as a whole, by sequentially scanning the gate bus lines are by the pulse. When the pulse is supplied to the gate bus line 10A, a voltage of the storage capacitor electrode 38B varies, so that a voltage between the pixel electrode 22B and the common electrode 50 also correspondingly varies. However, this voltage variation occurs only during a period in which the pulse is supplied to the gate bus line 10A, and the period is so extremely short that eyes of a human being cannot sense. Therefore, this voltage variation is not a problem. Referring to Figure 3A, there is shown a diagrammatic partial layout pattern diagram of a first embodiment of the thin film field effect transistor array in accordance with the present invention and used in the active matrix liquid crystal display. Figure 3B shows a diagrammatic sectional view taken along the line B - B in Figure 3A. In these figures, elements similar to those shown in Figures 1, 2A and 2B are given the same Reference Numerals, and explanation thereof will be omitted for simplification of description. In addition, in Figure 3B, the common electrode, the glass plate and the color filters are omitted for simplification of the drawing and since those elements are similar to the conventional ones. In the embodiment shown in Figures 3A and 3B, the chromium gate bus lines 10 are formed at the same time as the chromium gate electrode 30 of each thin film transistor, and the chromium drain electrode 32 and the chromium source electrode 34 of each thin film transistor are formed at the same time as the chromium drain bus lines 12. Each pixel electrode 22 is formed of ITO (indium tin oxide). As shown in Figure 3B, the gate bus line 10 is formed on the glass plate 40, and the first insulator layer 42 of silicon oxide (SiO 2 ) is deposited on the glass plate 40 so as to cover the gate bus line 10. A first chromium storage capacitor electrode 60 is deposited on the first insulator layer 42 in such a manner that the first storage capacitor electrode 60 is offset from the gate bus line 10. The second insulator layer 44 of silicon nitride (SiN X ) is deposited on the first insulator layer 42 so as to cover the first storage capacitor electrode 60. In addition, a second chromium storage capacitor electrode 62 is deposited on the second insulator layer 44 so as to overlap the first storage capacitor electrode 60 and the gate bus line 10. The surface protection layer 46 of silicon nitride (SiN X ) is deposited on the second insulator layer 44 so as to cover the second storage capacitor electrode 62. Furthermore, the pixel electrode 22 is formed on the surface protection layer 46. The second chromium storage capacitor electrode 62 is interconnected to the gate bus line 10 through contact holes 64 which are formed to pierce through the first insulator layer 42 and the second insulator layer 44. The pixel electrode 22 is interconnected to the first storage capacitor electrode 60 through contact holes 66 which are formed to pierce through the second insulator layer 44 and surface protection layer 46. Accordingly, the storage capacitor is formed by the pixel electrode 22, the first storage capacitor electrode 60, and the second storage capacitor electrode 62 which are stacked in a three-layer structure. The above mentioned storage capacitor structure could have a capacitance which is about double larger than that of the conventional one (as shown in Figures 2A and 2B) having the single storage electrode of the same area as that of the second storage electrode of the above mentioned storage capacitor structure. In addition, the display panel having the above mentioned storage capacitor structure was actually prepared. The display panel thus prepared gave a high picture quality. Referring to Figure 4A and 4B, there is shown a modification of the embodiment shown in Figures 3A and 3B. In these figures, elements similar to those shown in Figures 3A and 3B are given the same Reference Numerals, and explanation thereof will be omitted for simplification of description. As seen from comparison between Figures 3A and 3B and Figures 4A and 4B, the modification shown in Figure 4A and 4B is characterized in that a third storage capacitor electrode 68 formed of chromium is provided to extend from the gate bus line 10 underneath the first storage capacitor electrode 60, so that an additional storage capacitance is formed between the third storage capacitor electrode 68 and the first storage capacitor electrode 60. In other words, the storage capacitor can have a further increased capacitance. As seen from the above, the embodiment shown in Figures 3A and 3B and Figures 4A and 4B can have the storage capacitance which is about double or more of the conventional one, without increasing the area of the storage capacitance in the plan view or layout pattern view. In addition, since the thickness of the insulator between opposing electrodes of the storage capacitor can be made thinner than the conventional one, the capacitance of the storage capacitor can be further increased. On the other hand, the embodiment shown in Figures 3A and 3B and Figures 4A and 4B that has the same storage capacitance as the conventional one, can be realized with an area in the plan or layout pattern view which is smaller than that of the conventional one. In this case, the effective area of the picture electrode, namely, the aperture ratio can be increased. In the embodiment shown in Figures 3A and 3B and Figures 4A and 4B, the pixel electrode 22 has been formed of the ITO film, but can be formed of In 2 O 3 or SnO 3 . In addition, the gate insulator has been formed of SiN X , but may be formed of SiO 2 . The gate bus line, the drain bus line, and the electrodes of the storage capacitor has been formed of chromium, but can be formed of another metal, for example, Ta, Al, Mo, or Ti.

Claims: A thin film field effect transistor array comprising: a transparent insulating substrate (40); a plurality of parallel gate bus lines (10) formed on said transparent insulating substrate (40); a plurality of parallel drain bus lines (12) formed on said transparent insulating substrate (10) so as to intersect said gate bus lines (10); a plurality of pixel electrodes (22) each formed in proximity of a corresponding one of intersections between said gate bus lines (10) and said drain bus lines (12); a plurality of thin film field effect transistors (14) each formed in proximity of a corresponding one of intersections between said gate bus lines and said drain bus lines, each of said thin film field effect transistors being connected to a corresponding one of said pixel electrodes (22); at least two storage capacitors formed in proximity of a corresponding one of each of said pixel electrodes, each of said two storage capacitors connected at its one end to said corresponding one of said pixel electrodes and at its other end to the gate bus line which is preceding said gate bus line corresponding to said pixel electrode; the first storage capacitor of said two storage capacitors is formed by a part of the pixel electrode (22), a third insulater layer (46) and a second storage capacitor electrode (62); the second storage capacitor of said two storage capacitors is formed by said second storage capacitor electrode (62), a second insulater layer (44) and a first storage capacitor electrode (60); characterized in that said gate bus lines (10) are formed on the transparent insulating substrate (40) and a first insulator layer (42) is formed to cover said gate bus lines (10), said first storage capacitor electrode (60) is formed on said first insulator layer (42) so as to be offset from said gate bus line and said second insulator layer (44) is formed to cover said first storage capacitor electrode, said second storage capacitor electrode (62) is formed on said second insulator layer (44) so as to partially overlap said gate bus line and said first storage capacitor electrode (60), said second storage capacitor electrode (62) being connected to said gate bus line through a contact hole formed to pierce through said first and second insulator layers, said third insulator layer (46) is formed to cover said second storage capacitor electrode (62), and said pixel electrode (22) is connected to said first storage capacitor electrode (60) through a contact hole formed to pierce through said second and third insulator layers. A thin film field effect transistor array as claimed in claim 1 wherein a fourth storage capacitor electrode (68) which is an extension of said gate bus line (10) extends underneath said first storage capacitor electrode (60), so that said four storage capacitor electrodes form a four-layer stacked structure. A thin film field effect transistor array as claimed in claim 2 wherein said fourth storage capacitor electrode (68) is formed at the same level as said gate bus line (10).

Inventors: IKEDA NAOYASU, NAKAMURA KENICHI, IKEDA, NAOYASU, IKEDA, NAOYASU, C/O NEC CORPORATION, Nakamura Kenichi, c/o NEC Corporation
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: G02F1
IPC codes: H01L21, H01L29, G02F1, H01L27