Bus driver circuit

Abstract: A bus driver circuit (200) includes a data input line adapted to receive a binary data input signal having a first voltage range between high and low logic level signals and, when enabled, to provide, on a data transfer bus, binary data output signals which are clamped to maintain a second voltage range less than the first voltage range, thereby enabling high data transfer rates to be achieved. The bus driver circuit (200) includes first and second series-connected transistors (228,242), with the first transistor (228) acting as a clamping diode to prevent negative overshoots of the low level output voltage provided by the second transistor (242). Similarly, the second transistor (242) acts as a clamping diode to prevent positive voltage overshoots of the high level output voltage provided by the first transistor (228). The clamping remains effective when the bus driver circuit (200) is disabled.

Description: This invention relates to bus driver circuits of the kind having input means adapted to receive data input signals and an output node connected to a data transfer bus adapted to transfer data in the form of first and second logic level signals. Prior art data transfer systems, such as the system 100 in Figure 1, often contain a pre-charging transistor 102 coupled to a data bus 104 for pre-charging the bus 104 to a logic high level (e.g., 5 volts). This approach normally assumes that it is faster to pull the bus voltage down to a logic low level (e.g., 0 volts) from the logic high level, than the reverse. Pull-down transistors 106, 110 and 114 with their respective bus logic 108, 112 and 116 are operated to pull the bus voltage down to the logic low level by creating conduction paths to ground when activated. The bus 104 is maintained at a logic high voltage, which voltage is nearly instantaneously available at an input of an inverter 118. The bus 104 is pulled down when a logic low voltage is to be provided to the inverter 118. Pre-charging can thus increase the operating speed of data transfer systems. However, repeated pre-charging cycles without the intervention of a pull-down operation can raise the pre-charge voltage to such a high level that the overall advantage of pre-charging is lost since the time for going from the logic high voltage to the logic low voltage is directly proportional to the pre-charge voltage. Even where there is not repeated pre-charging, the bus transition time for changing from the logic high voltage level to the logic low voltage level, and vice versa, may still be undesirably large for some high-speed applications. It is an object of the present invention to provide a bus driver circuit of the kind specified adapted to provide a high data transfer speed on the data transfer bus. In the prior art, according to US-A-4 029 971, there is provided a bus driver circuit having input means adapted to receive data input signals, and an output node connected to a data transfer bus adapted to transfer data in the form of first and second logic level signals, clamping means adapted to prevent the voltage on said data transfer bus from transcending the range defined by said first and second logic levels, a first transistor connected to a first voltage source defining said first logic level and to said data transfer bus, a second transistor connected to a second voltage source defining said second logic level and to said data transfer bus, a disable line which is arranged to enable said driver circuit when an enabling signal is on said line. The present invention is further characterized in that said first transistor is adapted to act as a clamping diode to prevent the voltage on said data transfer bus from falling below said second logic level either when a disabling signal is on said disable line, or when said enabling signal is on said disable line and a signal on a data line is low, and in that said second transistor is adapted to act as a clamping diode to prevent the voltage on said data transfer bus from rising above said first voltage level either when said disabling signal is on said disable line, or when said enabling signal is on said disable line and said signal on said data line is high. It will be appreciated that a bus driver circuit according to the invention enables high speed data transfer to be achieved by limiting voltage swings on the data transfer bus. One embodiment of the present invention will now be described by way of example, with reference to the accompanying drawings, in which:- Figure 1, previously discussed, is a generalized schematic diagram of a prior art data transfer system; Figure 2 is a detailed schematic diagram of the preferred embodiment of the present inventive data transfer system; Figure 3 is an electrical equivalent of the schematic diagram in Figure 2 when the DISABLE signal is set to 0.0 volts; and Figure 4 is an electrical equivalent of the schematic diagram in Figure 2 when the DISABLE signal is set to 5.0 volts. Figure 2 shows the preferred embodiment for a high speed computer data bus driver 200 implemented using CMOS technology for transferring data signals DATA (via a data input line 206) in the form of logic high and logic low voltages. The bus driver is connected by its output node 238 to a data transfer bus (not shown). All transistors are of the junction field-effect type (JFET), with a bubble at the gate indicating a p-channel device, and the absence of a bubble at the gate indicating an n-channel device. The data bus driver 200 will be described in connection with data transfer operations. The data bus driver 200 is enabled (allowing it to transfer data) by setting the DISABLE signal at line 202 to 0.0 volts. In this mode transistors 218 (via line 204) and 232 turn on (are conducting), while transistors 220 (connected to VHO via line 222) and 236 turn off (non-conducting). In this condition, the circuit in Figure 2 behaves like the circuit in Figure 3, the circuit in Figure 3 being used here only for pedagogical reasons. While the bus driver 200 is in the enabled state, if the DATA signal is a CMOS logic low signal (0.0 volts), a transistor 230 turns on and a transistor 240 turns off, which places 5.0 volts on a line 234. This turns on a transistor 242, and pulls the output node 238 to VLO (0.0 volts), which is the low voltage level output by the driver 200 during data transfers. The logic low DATA signal also turns on (via line 208) transistor 210, and turns off transistor 212, the result of which is to place 5.0 volts on a line 214. The 5.0 volts on line 214 turns off transistor 216 and turns on transistor 226. This places a line 224 at VHO (1.0 volts), which is the high voltage level output by the driver 200 during data transfers, and is also the data bus pre-charge voltage. VLO and VHO represent the logic low (0) and logic high (1) voltage swing levels used on the data transfer bus, in order to reduce bus transition times. VHO at the gate of transistor 228 is normally not enough to activate it. However, transistor 228 is turned on if the voltage at the output node 238 (via line 244) falls below VHO - VT 228 , where VT 228 represents the threshold voltage (for conducting) of the transistor 228. If the transistor 228 is activated, it will pull the voltage at 238 up until the node voltage is no longer low enough to cause it to conduct. Thus, transistor 228 acts like a clamping diode to ensure that negative overshoots (voltages below VLO) do not occur. VHO and VLO are of course chosen so that the transistor 228 does not turn on until the voltage at the output node 238 falls below VLO. Still assuming that the data bus driver 200 is in the enabled state, if the DATA signal is at the CMOS logic high level, the transistor 210 is turned off while the transistor 212 is turned on, which pulls the line 214 down to 0.0 volts. The voltage on line 214 turns on the transistor 216 and turns off the transistor 226, which places the line 224 at 5.0 volts. The 5.0 volts on line 224 turns on the transistor 228, which passes VHO to the output node 238. The 5.0-volt DATA signal also turns off the transistor 230 and turns on the transistor 240, which places the line 234 and the output node 238 at the same level. In the preferred embodiment, VHO at the gate of transistor 242 is normally not enough to activate it. However, transistor 242 is turned on if the voltage at the output node 238 rises above VLO + VT 242 . If the transistor 242 is activated, it will pull the voltage at the output node 238 down until the node voltage is no longer high enough to cause it to conduct. Thus, transistor 242 acts like a clamping diode to ensure that positive overshoots (voltages above VHO) do not occur. VHO and VLO are chosen so that the transistor 242 does not turn on until the voltage at the output node 238 rises above VHO. The data bus driver 200 is disabled (the tri-state mode) by setting the signal DISABLE to 5.0 volts. In this condition, the transistors 218 and 232 are turned off, while the transistors 220 and 236 are turned on. This forces the voltage on line 224 to be equal to VHO, and the voltage on line 234 to be equal to the voltage at the output node 238. In this state, the transistors 210, 212, 216, 218, 220, 226, 230, 232, 236 and 240 do not affect the operation of the bus driver 200. Therefore, a disabled bus driver 200 behaves like the circuit shown in Figure 4. The voltages VHO and VLO are chosen so that if the data bus voltage (at node 238) rises above VHO (or VLO - VT 242 , where VT 242 is the threshold voltage of the transistor 242), the transistor 242 is activated to pull the output node 238 down to VHO. Likewise, if the voltage at the output node 238 falls below VLO (VHO - VT 228 ) the transistor 228 is activated to pull the node 238 up to VLO. Thus, whether the data bus driver 200 is enabled or disabled, the transistors 228 and 242 act as clamping diodes to prevent overshoot and undershoot of VHO and VLO, respectively. Variations and modifications to the present invention are possible within the definition of the invention as claimed. Such variations include, inter alia , an inverting data bus driver, circuit variations using P-channel transistors, a different number of clamping transistors, transistor-transistor logic (TTL) compatible drivers, and drivers using gallium arsenide transistors. Also, VLO and VHO may assume values other than those disclosed.

Claims: A bus driver circuit (200) having input means adapted to receive data input signals, and an output node (238) connected to a data transfer bus adapted to transfer data in the form of first and second logic level signals, clamping means (228,242) adapted to prevent the voltage on said data transfer bus from transcending the range defined by said first and second logic levels, a first transistor (228) connected to a first voltage source defining said first logic level and to said data transfer bus, a second transistor (242) connected to a second voltage source defining said second logic level and to said data transfer bus, a disable line (202) which is arranged to enable said driver circuit when an enabling signal is on said line (202), characterized in that said first transistor (228) is adapted to act as a clamping diode to prevent the voltage on said data transfer bus from falling below said second logic level either when a disabling signal is on said disable line (202), or when said enabling signal is on said disable line (202) and a signal on a data line (206) is low, and in that said second transistor (242) is adapted to act as a clamping diode to prevent the voltage on said data transfer bus from rising above said first voltage level either when said disabling signal is on said disable line (202), or when said enabling signal is on said disable line (202) and said signal on said data line (206) is high. A bus driver circuit according to claim 1, characterized by a third transistor (226) connected between said first voltage source and the gate of said first transistor, and a fourth transistor (240) connected between said output node (238) and the gate of said second transistor (242). A bus driver circuit according to claim 2, characterized by a fifth transistor (216) connected between a third voltage source and the gate of said first transistor (228) and a sixth transistor (230) connected between said third voltage source and the gate of said second transistor (242) and in that said input means is coupled to the gates of said fourth and sixth transistors (240,230) and via inverter means (210,212) to the gates of said third and fifth transistors (226,216). A bus driver circuit according to claim 3, characterized in that the voltage value of said third voltage source is greater in magnitude than the voltage value of said first voltage source. A bus driver circuit according to any one of the preceding claims, characterized by disabling means (218,220,232,236) adapted to disable said bus driver circuit from providing said first and second logic level signals on said data transfer bus, while maintaining said clamping means (228,242) operative.

Inventors: TIPON DONALD G, TIPON, DONALD G.
Applicants: NCR INT INC, NCR INTERNATIONAL, INC.
Application year: 1991
Main classification: H03K19
IPC codes: G11C11, G06F13, H03K19, H04L25