Semiconductor memory device

Abstract: Electric field stress applied to memory cells (107) is relieved in a semiconductor memory device. For this purpose, an X-decoder circuit (104) applies a low level signal to a selected memory cell in a selected memory cell block of a selected memory cell matrix, and a high level signal to non-selected memory cells in the selected memory cell block, while the X-decoder circuit applies the low level signal to memory cells of non-selected memory cell blocks of the selected memory cell matrix and memory cells of non-selected memory cell matrices.

Description: This invention relates to a semiconductor memory device, and more particularly to, a mask programmable read only memory in which electric field stress applied to memory cells is relieved. A conventional mask programmable read only memory comprises a plurality of memory cell matrices each having a plurality of memory cell blocks. Each of the memory cell blocks comprises a plurality of memory cells serially connected, and the serially connected memory cells are connected through a block selection transistor to a digit line on one side thereof, and are connected to ground on the other side thereof. In this mask programmable read only memory, the memory cell unit is composed, for instance, in such a manner that N channel MOS enhancement transistor having a threshold voltage of 1.0 V and N channel MOS depletion transistor having a threshold voltage of -5.0 V are assigned to store binary signals in accordance with the difference of the threshold voltages which is resulted from the injection of impurity, for instance, P into the transistors. In operation, one of the memory cell matrices is selected by a Y-decoder circuit, while one of the memory cell blocks is selected in the selected memory cell matrix by a block decoder circuit. In the selected memory cell block, one of the memory cells is accessed in accordance with the application of low level signal (O V) by an X-decoder circuit, while non-accessed memory cells are applied with high level signal (5 V). As a result, if the accessed memory cell is the depletion transistor, it is turned on even under the application of low level signal. On the other hand, the non-accessed memory cells are turned on regardless of the type of transistors. Thus, a potential of the digit line which is thereby connected through the turned-on memory cells including the accessed memory cell to ground is lowered, for instance, from 1.2 V to 1.1 V. This potential change is amplified in a sense amp circuit to provide information read from the accessed memory cell. On the contrary, if the accessed memory cell is the enhancement transistor, it is not turned on under the application of low level signal. Therefore, the potential change does not occur. In this manner, information stored in the memory cell unit is read upon the access of a predetermined one of the memory cells by applying a low level signal thereto, while a high level signal is applied to the non-accessed memory cells of the selected block, and to the remaining memory cells of the selected memory cell matrix and the non-selected memory cell matrices. In this conventional mask programmable read only memory, however, there is a disadvantage in that electric field stress applied to the memory cells is large to shorten the life thereof, thereby lowering the reliability thereof, because a high level signal is applied to all word lines except for one word line which is selected at the access time by the X-decoder circuit. The same thing can be said at the stand-by time, because all the word lines are applied with a high level signal. EP-A-0 297 540 discloses a semiconductor memory device as indicated in the preamble of claim 1. It comprises of a plurality of selection transistors, each being connected at one end to a column line and each having a gate connected to a common row line, and a plurality of groups of cell transistors, each group being connected in series between the other end of a respective one of said selection transistors and a reference potential and whose control gates are connected to row lines, each group of cell transistors being connected to common lines. Accordingly, it is an object of the invention to provide a semiconductor memory device in which electric field stress applied to memory cells is relieved at the time of stand-by and active modes to enhance the reliability thereof. According to the invention, a semiconductor memory device comprises a memory cell unit comprising a plurality of memory cell groups each of said memory cell groups comprising a digit line and a plurality of memory cell blocks, each of said memory cell blocks comprising a predetermined number of serially connected memory cells which are connected to a predetermined number of word lines, respectively, and serially connected between said digit line and a fixed potential, each of said predetermined number of memory cells including a transistor for storing information according to first and second threshold voltages, said first threshold voltage being higher than said second threshold voltage; first means for selecting one memory cell group from said plurality of memory cell groups according to an address signal; second means for selecting one memory cell block from said plurality of memory cell blocks in said one memory cell group according to said address signal; and third means for selecting one memory cell from said serially connected memory cells in said one memory cell block according to said address signal; wherein: said third means applies a first voltage to said one memory cell and a second voltage to said serially connected memory cells excluding said one memory cell in said one memory cell block (FIRST MEMORY CELL BLOCK) of a selected memory cell group, said first voltage being lower than said first threshold voltage and higher than said second threshold voltage, and said second voltage being higher than said first threshold voltage, characterised in that corresponding memory cells in each of the memory cell blocks within a single memory cell group are connected to the same word lines, each memory cell group being respectively connected to different word lines, that said third means applies said first voltage to one memory cell and the second voltage to said serially connected memory cells, excluding said one memory cell in said memory cell block, in each of the remaining memory cell blocks (SECOND MEMORY CELL BLOCK) of said selected memory cell group, and that said third means applies said first voltage to the memory cells of the memory cell blocks of the nonselected memory cell groups. This invention will be explained, by way of example and in more detail in conjunction with the appended drawings, wherein; Fig. 1 is a block diagram showing a conventional mask programmable read only memory; Fig. 2 is a circuit diagram showing one of memory cell matrices in the conventional mask programmable read only memory in Fig. 1; Fig. 3 is a circuit diagram showing a selection signal generating circuit in the conventional mask programmable read only memory in Fig. 1; Fig. 4 is a circuit diagram showing an X-decoder circuit in the conventional mask programmable read only memory in Fig. 1; Fig. 5 to 7 are truth tables explaining operation in the conventional mask programmable read only memory in Figs. 1 to 4; Fig. 8 is a circuit diagram showing an X-decoder circuit in a mask programmable read only memory of a first preferred embodiment according to the invention; Figs. 9 to 11 are truth tables explaining operation in the mask programmable read only memory of the first preferred embodiment according to the invention; and Fig. 12 is a circuit diagram showing an X-decoder circuit in a mask programmable read only memory of a second preferred embodiment according to the invention. Before explaining a mask programmable read only memory of preferred embodiments according to the invention, the aforementioned conventional mask programmable read only memory will be explained in more detail. In Fig. 1, the conventional mask programmable read only memory comprises an address buffer circuit 101 for temporally storing an address signal of n bits (a 1 , a 2 , ..... a n ), assuming that n is 7 hereinafter, a chip enable signal buffer circuit 102 for temporally storing a chip enable signal Ce, a selection signal generating circuit 103 for generating a selection signal Sj, assuming that j is 1 to 4 hereinafter, by receiving the two bits a 1 and a 2 of the address signal and the chip enable signal Ce, an X-decoder circuit 104 for generating a word line signal Wjk, assumping that k is 1 to 4 hereinafter, by receiving the two bits a 3 and a 4 of the address signal and the selection signal Sj, a block decoder circuit 105 for selecting one memory cell block (to be explained in Fig. 2) by receiving the bit a 5 of the address signal, a Y-decoder circuit 106 for controlling the selection of one memory cell matrix (to be explained in Fig. 2) by receiving the two bits a 6 and a 7 of the address signal, a memory cell unit 107 having memory cell matrices 107a, 107b, 107c and 107d (to be explained in Fig. 2), a Y-selector 108 for selecting one of the memory cell matrices 107a, 107b, 107c and 107d, and a sense amp circuit 109 for amplifying a signal read from an accessed memory cell. In Fig. 2, the memory cell unit 107 comprises the memory cell matrices 107a, 107b, 107c and 107d, each of which comprises the two memory cell blocks as shown in the block of the memory cell matrix 10 7a. In a first one of the memory cell blocks, memory cells M 1 , M 2 , M 3 and M 4 , each consisting of a transistor selected dependently on storing binary states from an N-MOS enhancement transistor having a threshold voltage of 1.0 V and an N-MOS depletion transistor having a threshold voltage of -5.0 V, are connected serially to be positioned between ground and a block selection transistor Q B1 of an N-MOS enhancement transistor having a threshold voltage of 1.0 V. The block selection transistor Q B1 is connected commonly to a digit line D 1 and to a Y-selection transistor Q Y1 of an N-MOS enhancement transistor having a threshold voltage of 1.0 V. The memory cells M 1 , M 2 , M 3 and M 4 are connected at gates to the word lines W 11 , W 12 , W 13 and W 14 each connected to the X-decoder circuit 104, and the block and Y-selection transistors Q B1 and Q Y1 are connected at gates to the block and Y-decoder circuits 105 and 106, correspondingly. In a second one of the memory cell blocks, serially connected memory cells M 5 , M 6 , M 7 and M 8 are positioned between a block selection transistor Q B2 connected to the digit line D 1 and ground, wherein type and threshold voltage of the transistors are the same as those of the first one of the memory cell blocks. In Fig. 3, the selection signal generating circuit 103 comprises inverters 31 and 32 for inverting the two bits a 1 , and a 2 of the address signal, inverters 33 and 34 for inverting output signals of the inverters 31 and 32, NAND circuits 39 to 42, respectively, for receiving the output signals of the inverters 31 and 32, the output signal of the inverter 31 and an output signal of the inverter 34, an output signal of the inverter 33 and the output signal of the inverter 32, and the chip enable signal Ce and the output signals of the inverters 33 and 34, inverters 35 to 38, respectively, connected to the NAND circuits 39 to 42 to provide the selection signals S 1 to S 4 which are supplied to the X-decoder circuit 104. In Fig. 4, the X-decoder circuit 104 comprises a NAND circuit 21 for receiving the two bits a 3 and a 4 of the address signal and the selection signal Sj, and inverters 22 and 23 for receiving an output signal of the NAND circuits 21 and supplying output signals, respectively, to a P-MOS transistor 24 connected to a power supply Vcc and an N-MOS transistor 25 connected to ground, wherein the word line signal Wjk is supplied from a common node of source to drain path of the P-and N-MOS transistors 24 and 25. In operation, the address signal a 1 , a 2 , ..... a 7 having the two bits a 1 and a 2 of a high level is supplied to the address buffer circuit 101, and the chip enable signal Ce of a low level is supplied to the chip enable buffer circuit 102, so that the selection signal Sj of a low level is generated in the selection signal generating circuit 103 to be supplied to the X-decoder circuit 104, in which the word line signal Wjk of a high level is generated to be supplied to all of the memory cells in the memory cell matrices 107a, 107b, 107c and 107d of the memory cell unit 107 regardless of the address signal bits a 3 and a 4 . As a result, the stand-by mode is set, as shown in Fig. 5. When the chip enable signal Ce becomes high, one of the selection signals S 1 , S 2 , S 3 and S 4 becomes high in the selection signal generating circuit 103 dependently on contents of the address signal bits a 1 and a 2 , as shown in Fig. 7. Assuming that the selection signal S 1 is high due to the two bits a 1 and a 2 of a low level, while the selection signals S 2 to S 4 are low, the word line signals W 11 , W 12 , W 13 and W 14 are determined in the X-decoder circuit 104 by contents of the two bits a 3 and a 4 supplied to the NAND circuit 21 along with the selection signal S 1 , as shown in Fig. 6. Assuming that the two bits a 3 and a 4 are high, the word line signal W 11 is low, because the N-MOS transistor 25 is turned on, while the P-MOS transistor 24 is turned off. On the other hand, the word line signals W 12 , W 13 and W 14 are high, as shown in Fig. 7. At this time, the address signal bit a 5 of a high level is decoded in the block decoder circuit 105, so that the block selection transistor Q Y1 is turned on to select the first one of the memory cell blocks in the memory cell matrix 107a which is selected in accordance with the turning-on of the Y-selection transistor Q Y1 by the address signal bits a 6 and a 7 supplied to the Y-decoder circuit 106. As a result, the first memory cell M 1 ; M 5 of each of the memory cell blocks in the memory cell matrix 107 a is applied with a low level signal, while all of the remaining memory cells of the memory cell matrix 107a and the memory cells of the memory cell matrices 107b, 107c and 107d are applied with a high level, as shown in Fig. 7. If the accessed memory cell M 1 is an N-MOS enhancement transistor, it is not turned on, so that the digit line D 1 is not changed regarding a potential (for instance, 1.2 V to be maintained). On the contrary, if the accessed memory cell M 1 is an N-MOS depletion transistor, it is turned on, so that the digit line D 1 is changed regarding the potential (for instance, lowering from 1.2 V to 1.1 V). This change is transmitted to the sense amp circuit 109, in which it is amplified to be supplied to an output buffer circuit (not shown). Thus, information stored in the memory cell M 1 is read. Next, a mask programmable read only memory of the first preferred embodiment according to the invention will be explained. In Fig. 8, an X-decoder circuit included in the mask programmable read only memory of the first preferred embodiment is shown, while other circuits are not shown, because the same circuits as used in the conventional mask programmable read only memory as shown in Figs. 1 to 4 are adopted in the first preferred embodiment. The X-decoder circuit 104 comprises a first NAND circuit 11 for receiving two bits a 3 and a 4 of an address signal of, for instance, seven bits a 1 , a 2 , ..... a 7 and generating a first NAND signal, a second NAND circuit 12 for receiving a selection signal Sj from a selection signal generating circuit (Fig. 1) and the first NAND signal from the first NAND circuit 11 and generating a second NAND signal, a third NAND circuit 13 for receiving the selection signal Sj from the selection signal generating circuit and the first NAND signal from the first NAND circuit 11 and generating a third NAND signal, a P-MOS transistor 14 for generating a word line signal Wjk of a high level in accordance with the turning-on by receiving the second NAND signal, and an N-MOS transistor 15 for generating the word line signal Wjk of a low level in accordance with the turning-on by receiving the third NAND signal. In operation, the selection signals S 1 to S 4 are all low at the time of stand-by mode, as shown in Fig. 9. When any of the selection signals S 1 to S 4 of a low level is supplied to the second NAND circuit 13 of the X-decoder circuit 104, the word line signal Wjk is low, as shown in Fig. 9, because the P-MOS transistor 14 is turned off, while the N-MOS transistor 15 is turned on, regardless of contents of the address signal bits a 3 and a 4 supplied to the first NAND circuit 11. Next, when the chip enable signal Ce becomes high, the active mode is set to read information from an accessed memory cell of the memory cell unit. Here, it is assumed that a memory cell M 1 will be accessed. For the purpose, the two bits a 1 and a 2 of the address signal are low, so that the selection signal S 1 becomes high in the selection signal generating circuit, while the selection signals S 2 to S 4 becomes low, as shown in Fig. 11. As a result, the memory cell matrix 107a (Fig. 2) including the memory cell M 1 is selected, and the memory cell matrices 107b, 107c and 107d are not selected. In the X-decoder circuit 104, the address signal bits a 3 and a 4 of a high level are supplied to the first NAND circuit 11, as shown in Fig. 10, so that the first NAND signal of a low level is supplied to the second and third NAND circuits 12 and 13. At the same time, the selection signal S 1 of a high level is supplied to the third NAND circuit 13, so that the P-MOS transistor 14 is not turned on, while the N-MOS transistor 15 is turned on to provide the word line signal W 11 of a low level for the memory cell M 1 . On the other hand, even if the bits a 3 and a 4 are high, the word line signals W 12 , W 13 and W 14 are high, because the selection signals S 2 , S 3 and S 4 supplied to third NAND circuits 13 of respective X-decoder circuits 104 are low. Otherwise, all word line signals are low in the memory cell matrices 107b, 107c and 107d of the memory cell unit 107 which are not selected in accordance with the selection signals S 2 to S 4 of a low level, regardless of contents of the bits a 3 and a 4. As a result, the first memory cell M1;M5 of each memory cell block in the memory cell matrix 107a is applied with a low level signal, the remaining memory cells M2-M4; M6-M8 in the memory cell blocks of said memory cell matrix 107a are applied with a high level signal, and all of the memory cells M1-M4; M5-M8 in all of the memory cell blocks in the memory cell matrices 107b, 107c, 107d are applied with said low level signal as shown in Fig. 11. As clearly understood from the first preferred embodiment, all of the word lines are set to be low at the time of stand-by mode, and the word lines connected to the memory cells of the memory cell matrices which are not selected are all set to be low at the time of active mode. Consequently, electric field stress applied to memory cells is relieved to enhance the reliability of the mask programmable read only memory. In Fig. 12, an X-decoder circuit included in a mask programmable read only memory of the second preferred embodiment according to the invention is shown, wherein like parts are indicated by like reference numerals as used in Fig. 8. Even in the second preferred embodiment, other circuits than the X-decoder circuit are the same as those in the conventional mask programmable read only memory. The X-decoder circuit comprises a voltage control circuit 16 connected to a common node of source to drain path of the P- and N-MOS transistors 14 and 15 to supply a word line signal Wjk to word lines connected to memory cells, in addition to the structure as shown in Fig. 8. In operation, when the word line signal W 12 , W 13 and W 14 of a high level which are indicated as "j=1" in Fig. 11 are controlled to be a voltage less than a power supply voltage Vcc and more than a threshold voltage of the N-channel MOS enhancement transistor by the voltage control circuit 15, so that electric field stress is more relieved in the second preferred embodiment than the first preferred embodiment. Although the invention has been described with respect to specific embodiment for complete and clear disclosure, all modifications and alternative construction that may occur to one skilled in the art, which fairly fall within the basic teaching herein set forth, are also covered by the invention.

Claims: A semiconductor memory device, comprising: a memory cell unit (107) comprising a digit line and a plurality of memory cell groups (107a-107d), each of said memory cell groups comprising a digit line and a plurality of memory cell blocks (M 1 - M 4 , M 5 - M 8 ), each of said memory cell blocks comprising a predetermined number of serially connected memory cells (M 1 - M 4 ) which are connected to a predetermined number of word lines (W 11 - W 14 ), respectively, and serially connected between said digit line and a fixed potential, each of said predetermined number of memory cells including a transistor for storing information according to first and second threshold voltages, said first threshold voltage being higher than said second threshold voltage; first means (108) for selecting one memory cell group (107a) from said plurality of memory cell groups according to an address signal; second means (105) for selecting one memory cell block from said plurality of memory cell blocks in said one memory cell group according to said address signal; and third means (104) for selecting one memory cell (M 1 ) from said serially connected memory cells in said one memory cell block according to said address signal; wherein: said third means applies a first voltage to said one memory cell (M 1 ) and a second voltage to said serially connected memory cells (M 2 - M 4 ) excluding said one memory cell in said one memory cell block (FIRST MEMORY CELL BLOCK) of a selected memory cell group (107a), said first voltage being lower than said first threshold voltage and higher than said second threshold voltage, and said second voltage being higher than said first threshold voltage, characterised in that corresponding memory cells in each of the memory cell blocks (M 1 - M 4 , M 5 - M 8 ) within a single memory cell group (107a) are connected to the same word lines (W 11 - W 14 ), each memory cell group (107a, 107b, 107c, 107d) being respectively connected to different word lines, that said third means applies said first voltage to one memory cell (M 5 ) and the second voltage to said serially connected memory cells (M 6 - M 8 ), excluding said one memory cell (M 5 ) in said memory cell block, in each of the remaining memory cell blocks (SECOND MEMORY CELL BLOCK) of said selected memory cell group (107a), and that said third means applies said first voltage to the memory cells of the memory cell blocks of the nonselected memory cell groups (107b,..,107d). A semiconductor memory device, according to Claim 1, wherein: said third means (104) are provided to be equal in number to said word lines, each of said third means comprising first and second transistors (15, 14) which are alternatively turned on and off according to said address signal and a chip enable signal, said first and second transistors provide said first and second voltages, respectively. A semiconductor memory device, according to Claim 1 or Claim 2, wherein; said each of said third means further comprises a voltage control circuit (16) for controlling said second voltage to be lower that a power supply voltage (V cc ) to a predetermined extent.

Inventors: KOHNO TAKAKI, KOHNO, TAKAKI, Kohno, Takaki, c/o NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: G11C17
IPC codes: G11C17