LOW POWER DISSIPATION AUTOZEROED COMPARATOR CIRCUIT

Abstract: The comparator circuit of the autozeroed type, for implementation in CMOS technology, includes two identical cascaded amplifier stages (A1, A2), and one final stage at which output a square-wave signal, representing the times during which the input signal (Vin) is higher than the reference signal (Vref), is present. Each one of the two amplifier stages (A1, A2) includes an inverter (M1, M2; M5, M6) driven by a follower circuit (M3, M4; M7, M8).

Description: "LOW POWER DISSIPATION AUTOZEROED COMPARATOR CIRCUIT" DESCRIPTION The present invention relates to a low power dissipation autozeroed comparator circuit suitable for CMOS integration. As known, a comparator circuit receives at its input a constant reference signal and a signal generally variable in time, and produces a sguare-wave signal representing the times during which the level of the variable signal is higher (or lower) than the threshold represented by the reference signal. The operation of an autozeroed comparator occurs in two times or phases, an autozero phase §1 where the circuit initial conditions are resetted, and phase Φ2 where the input signal Vin is compared to the reference signal Vref. Comparators are used in a variety of digital processing systems requiring a conversion interface. CMOS comparators with autozero-phase designed through switched capacitors (SC) tecnigue, are already well known. Fig. 1 shows a known circuit of this type, consisting of two cascaded autozeroed inverters, followed by a so- called latch L. The basic structure, shown inside the dotted section, includes two transistors MAI and MA2, n channel and p channel respectively, connected in series between two voltages V DD and V ss , whose gates are shorted. To the gates common node one of plates of comparator input capacitor Cl, is connected. Two switches SI and S2 are foreseen to connect alternatively and subsequently the other plate of capacitance Cl to an input voltage Vin and to a reference voltage Vref, respectively. The gates common node is connected to capacitance C2 of the subsequent stage through a switch S3, this stage being alike to the previous one and formed by components C2, MA3, MA4 and S4. In autozero operation (during which the switch S3 is closed) the two transistors MAI and MA2 are biased in the saturation range with high voltage between gate and source V GS equal to approx (V DD - V ss )/2. This condition causes a high bias current Ip to flow through the transistors MAI and MA2 and, consequently a considerable power dissipation. One of the objects of the present invention i therefore to eliminate or at least to limit thi disadvantage of the present known autozeroed comparators, and in particular to realize a low power dissipatio circuit, suitable for integration in CMOS technology. Another object of the invention is to propose comparator having improved performances, in particular abl to obtain an advantageous compromise between operatio speed and power dissipation, together with improve sensitivity performances. These objects are achieved with the comparator of thi invention thanks to the characteristics which form the object of claim 1. Further favourable characteristics result from the sub-claims. The invention shall be now described referring to the preferred, but not limiting, realization forms, illustrated in the enclosed figures, where: Fig. 1 shows an example of comparator according to the known technique; Fig. 2 shows a schematic of the comparator according to the invention; Fig. 3 shows the timing of phase or clock signals; and Fig. 4 shows a realization variant of the single gain stage of comparator according to the invention. Fig. 1 refers to a comparator according to the known technique which has already been examined briefly and shall not therefore be furtherly described. Fig. 2 shows a schematic of the comparator according to the invention, consisting of a three stage cascade Al, A2 and INV. Stages Al and A2 are essentially alike and realize the gain required for the operation, while the INV stage is an inverter stage employed to square the outgoing waveform Vout. According to a not shown realization variant, INV stage could be replaced by a latch whose function is to store the voltage at node B on the edge of an appropriate control phase. Each of the two stages Al and A2 includes four transistors, M1-M4 and M5-M8, respectively. Being the two stages essentially identical, stage Al only shall be described in detail. This stage includes an inverter- circuit (transistors Ml and M2) driven by a follower circuit formed by transistors M3 and M4, shown in Fig. 2 as n channels. An autozeroed CMOS switch S3 is connected between these two circuits; its control clock or phase signal is described below. Switch S3 is closed when phase $1 is active (high) and conventionally, in the Figures, each controlled switch is marked also by a phase signal " , meaning by that the switch results being closed when this phase signal is high. Stage Al needs two supply voltages V DD and V ss , and also two bias voltages, Vbiasl and Vbias 2 for the gates of M2 and M4 transistors, respectively. M3 gate is connected to a plate of the comparator input capacitance Cl, whose other plate is connected, selectively and subsequently, to the input voltage Vin and to the reference voltage Vref. In Fig. 2 stray capacitances of Cl plates labelled C BP and C up £- are also highlighted, and the same for capacitance C2 o stage A2. Connections between Cl and voltages Vin and Vref ar assured via the controlled switches SI and S2 respectively. More in detail, the switch SI is closed whe phase $2 is high, while the switch S2 is controlled by Φl' signal. As can be seen in Fig. 3, l' is a replica o phase §1 where the opening edge has a delay equal to compared to the same edge for phase Φl. However, this dela is such to uphold the transition in the disoverlap rang between Φl and Φ2. The output of stage Al is withdrawn at the common nod A of Ml and M2 drain terminals. As already pointed out, th connection between M3 gate and output node A is provide via switch S3 controlled by phase Φl. Stage A2 is cascaded to the previous one and is alike. A2 stage output is withdrawn at node B common to M5 and M drain terminals. The connection between M8 gate and outpu node B takes place via switch S4 controlled by phase Φl 7 . The inverter stage INV consists of two transistors M and M10 and this stage needs to generate an output wavefor with very steep transition edges between high logic leve and low logic level. The comparator circuit operates as follows. During phase Φl the comparator autozero is carried out (S3 and S4 switched on) as well as the charging of the input capacitance Cl to the reference level (S2 switched on) . Being phases Φl and Φl' simultaneous, the autorezero operation is carried out on both gain stages Al and A2. The autozero is introduced to have all the transistors of the two stages Al and A2 led again to the linear operation range, between a switching phase and the subsequent one. At the end of this operation, the circuit resets in the initial bias conditions, imposing a voltage value equal to approximately (V DD - V ss )/2 at nodes A and B. By this operation the values of input and output voltages of each gain stage result equal between them and equal to the half of swing range voltage. This equal distance of output voltages (intermediate ones in each single stage) from both final logic levels allows to balance the response times (and therefore the speed) of the comparator for input signals higher and lower, of a same quantity than the reference voltage. The autozero phase is requested also to compensate the comparator offset, approximately egual to the offset of the first stage Al since the offset charge stored on capacito C2 of stage A2, referred to the input of the comparator, is divided by the gain of the first stage and therefore highl attenuated. In the comparator, measures are taken to minimize voltage peaks • in input capacitor Cl, due to the clockfeedthrough charge injection at the end of phase Φl. This charge injection has to be reduced as much as possible since it is amplified by the gain of both stages Al and A2 and can originate a false switching of the output towards one of the two possible logic states, depending on the charge sign. The contribution of this charge tends to originate an asymmetrical behaviour of the comparator, accelerating one transition and delaying the other one. To reduce this charge, CMOS switches S3 and S4 are adequately sized and S4 is also controlled by phase Φl 7 whose opening edge is slightly delayed in respect with the one of signal Φl controlling S3. Thus, when S3 is open, S4 remains still closed for the time T, and the charge injected towards C2 sees low impedance towards the output, entering C2 and traducing an offset voltage equal to (Q/C2) for the stage A2, where (Q) is the clockfeedthrough charge. The charge injected towards Cl sees a low impedance path towards Vref and entrs Cl. When after the delay T S4 opens too, the charge injected towards A charges the parasitic capacitance of C2 (C BP ) . Due to the fact that the voltage drop produced is inversely proportional to such parasitic capacitance, it is preferred to connect the bottom plate of C2 to the gate of M8 as shown in Fig. 2. In this way there is also the advantage to avoid a too high capacitive load at node A which would originate a slowing down of stage Al. Similarly, the charge deriving from the delayed opening of S2 charges the parasitic capacitance (C BP ) at the input of stage Al to which the bottom plate of Cl is connected in order to avoid a partition of the input signal between Cl and the stray capacitance at M3 gate. During phase Φ2 , switch SI connecting Cl to the input voltage Vin, is closed and the comparison between this voltage and the reference precharged in Cl takes place. In stages Al and A2 according to the invention, the follower transistor (M3, M8 respectively) allows biasing the corresponding gain transistors (Ml, M5 respectively) in the saturation area, characterized by a low drop voltage between gate and source, with an ensuring reduction of the bias current Ip. Making reference to stage Al , the gain of each stage can be expressed as follows: gml G = gdsl + gds2 where gml is the transconductance of the gain transistor, equal to: J 2μC 0X (W/L)I D' and gdsl and gds2 are the channel conductances of th gain transistor and of the load transistor, respectively. Thus G is proportional to 1/ ϊp, consequently, th possibility to perform a low bias current operation help the realization of a high gain and therefore of a goo sensitivity. At fixed bias current to meet the low dissipation specification, the switching speed can be assured through an adequate sizing of transistors Ml and M5, respectively; in fact speed is proportional to gml, which in its turn depends on ip(W/L) , where W is the width and L is the length of the gain transistor. The gain required for the correct toggling of the comparator is assured by the cascade of the two gain stages. The final inverter stage INV is constantly unbalanced and not affecting therefore the total power dissipation. According to a further realization form partially shown in Fig. 4, the comparator circuit can include a further follower stage including transistors Mil and M12 driving transistor M2. A similar follower stage is introduced to drive transistor M6, thus obtaining an increase of the gain of each stage and of the switching speed. Moreover it must be noticed that the optimization between operation speed and circuit power dissipation Jo according to the invention enables also an improvement of sensitivity performance, thanks to the gain enhancement deriving from a lower stationary current.

Claims: / / CLAIMS 1. Autozeroed comparator circuit, including a first amplifier stage (Al) whose input can be selctively connected to an input voltage (Vin) and to a reference voltage (Vref) ; a second amplifier stage (A2) connected to the output of this last, and a final stage at which output a rectangular signal is present, representing the times during which the input signal (Vin) is higher than the reference signal (Vref) , characterized by the fact that the two amplifier stages (Al; A2) are identical and each one includes an inverter (Ml, M2; M5, M6) driven by a follower circuit (M3, M4; M7, M8) . 2. Comparator circuit according to claim 1, characterized by the fact that said first amplifier stage (Al) includes an input capacitance (Cl) having a selectively and not simultaneously connectable plate, via two controlled input switches (S2, SI), to the reference voltage (Vref) and to the input voltage (Vin) , respectively, and a first controlled switch (S3) between the follower transistor (M3) and the output (A) of said first stage (Al) . 3. Comparator circuit according to claim 1, characterized by the fact that said second stage (A2) has a second controlled switch (S4) between the follower transistor (M8) and the output (B) of said second stag (A2). 4. Comparator circuit according to claim 3, characterized by the fact that said first controlled switc (S3) of the first amplifier circuit (Al) is closed when first phase signal (Φl) is high during which the autozer operation occurs. 5. Comparator circuit according to claim 4, characterized by the fact that said controlled input switc (SI) for the connection to the input voltage (Vin) i closed when a second phase signal (Φ2) is active, subsequent in time to said first phase signal (Φl) . 6. Comparator circuit according to claim 4 or 5, characterized by the fact that said controlled input switc (S2) for the connection to the reference voltage (Vref) an said second controlled switch (S4) of the second amplifie circuit (A2) are controlled by a phase signal (Φl 7 ) remaining active for a longer time compared to said firs phase signal (Φl) , but not superimposing to said secon phase signal (Φ2) . 7. Comparator circuit according to claim 1 characterized by the fact that said follower circuit (M3 M4; M7, M8) is realized with n channel CMOS transistors. 8. Comparator circuit according to claim 1 characterized by the fact that said follower circuit (M3 M4; M7, M8) is realized with p channel CMOS transistors. 9. Comparator circuit according to claim 1 characterized by the fact to have a further inverte circuit (Mil, M12) between said first follower circuit (M3 M4; M7, M8) and the first inverter (Ml, M2; M5, M6) .

Inventors: BAGGINI BARBARA, PALMISANO GIUSEPPE, BAGGINI, BARBARA, PALMISANO, GIUSEPPE
Applicants: ITALTEL SPA, ITALTEL SOCIETA ITALIANA TELECOMUNICAZIONI S.P.A.
Application year: 1991
Main classification: H03K5
IPC codes: H03K5