SEMICONDUCTOR DEVICE MANUFACTURING PROCESS

Abstract: A semiconductor device manufacturing process characterized in that, when the limit values of wafer warpage and the internal defect density in the device fabrication process are specified in certain ranges for a single-crystal silicon wafer of a substrate according to the conditions of the device yield and the gettering capability, preheating treatment for producing the oxygen precipitation nucleus is applied to a wafer having an initial oxygen concentration capable of simultaneously meeting the above ranges for a heat treatment time simultaneously meeting the range between the upper- and lower-limit values of the initial oxygen concentration and the range of the above internal defect density. The process of the present invention makes it possible to efficiently select a combination of the above conditions for securing the BMD density required to minimize the wafer warpage and to enable the wafer to exhibit the desired gettering capability in a short time not by trial and error.

Description: INDUSTRIAL FIELD OF THE INVENTION This invention relates to a process for manufacturing semiconductor devices, and more particularly to a technique in which there is taken advantage of a relationship among the initial oxygen concentration (hereinafter called initial Oi) of a wafer, the SORI of the wafer in heat treatment process, and the Bulk Micro Defect density (hereinafter called BMD density), to limit to the minimum extent the SORI of the wafer, which is caused by the heat treatment subjected to during the manufacturing process of elements and to retain the BMD density required for a gettering action whereby the yield of the elements is improved. PRIOR ART In manufacturing semiconductor elements using a silicon single crystal as a substrate a variety of gettering methods have been conventionally developed and used to improve the yield. Particularly, the so-called intrinsic gettering (hereinafter called IG) is generally well employed as a method of clean gettering, said IG using as a gettering site the bulk micro defects which generate in the wafer in the heat treatment process, being caused by the supersaturated oxygen involved in a CZ silicon single crystal. The IG capability is closely concerned with the BMD density, and the different kinds of elements require their respective IG capabilities correspondingly. In short, depending on the kinds of elements the optimum BMD density for the wafer is required. Additionally, said BMD density is a general naming of micro defects in silicon. As is known, the measuring means of the BMD density is such that the section of a silicon wafer is etched by about two microns with a selected etching solution (mixed solution of acetic acid, hydrofluoric acid, nitric acid, and chromic acid), and the etched surface is observed with an optical microscope (usually 400 magnification), and the number of the counted defects is converted to that per unit area (n/cm 2 ). On the other hand, the initial Oi of a CZ silicon single crystal wafer in general use is usually in the range 12x10 17 to 18x10 17 atoms/cc, and to obtain the optimum BMD density a preheat treatment is carried out for the production of oxygen precipitate nuclei at 600-900°C depending on the initial Oi of the wafers of the respective substrates. In wafers which can be internally generated with BMD density determined by the gettering capability by heat treatment in the manufacturing process of the semiconductor devices, a thermal stress often occurs due to the temperature gradient within the wafer face, following the insertion into and withdrawing from the heat treatment furnace, when a displacement and propagation takes place in the wafer by the bulk micro defects thereby deforming the wafer not a little whereby a SORI or a slip of continuous defects generates. The portion thus slipped causes a deterioration in the characteristics of the devices. On the other hand, even the SORI of a wafer brings about a pattern slip in fine processing such as mask mating. Thus both the SORI and slipping lower the device yield. The present invention has been made to solve the above problems, and is characterized in that when the limit value of the SORI of the wafer after passing the device process, and the BMD density, are specified in predetermined ranges for a silicon single crystal to be a device, being required by the device yield and the gettering capability in making a semiconductor device, said wafer having the initial Oi sufficient to simultaneously satisfy said predetermined ranges, is subject to a preheat treatment by using a time that can simultaneously satisfy a predetermined range between the upper limit and lower limit values of said initial Oi and the predetermined range of said BMD density. That is, there is previously obtained, for each group of silicon wafers in plurality having different initial oxygen concentrations, a relation between the BMD density within the wafers in the heat treatment in said device making process or the simulation heat treatment, and the SORI of the wafers. Then, there are obtained based on said relation the upper limit value (x) and lower limit value (y) of the initial Oi, which intersect in the region that simultaneously satisfy the limit value (a) of the SORI and the BMD density range (b), said upper and lower limit values (x) and (y) being determined when said limit value (a) and said density range (b) are specified, being restricted by the device yield and the gettering capability. On the other hand, in a relation which has previously been obtained similarly for each period of time of preheat treatment between the initial Oi in the wafers and the BMD density, the silicon wafers having the initial Oi in said upper limit value (x) and lower limit value (y) are subject to a preheat treatment relying on the heat treatment time intersecting in the region of simultaneously satisfying a predetermined range (c) between the upper limit value (x) and lower limit value (y) of said initial Oi, and the BMD density range (b). By the "preheat treatment" in the present invention is meant a heat treatment before the device process (including the simulation heat treatment). Further, use of a light scattering tomography method employing an infrared laser will clarify the judgment in measuring said BMD density. In the drawings: FIGURE 1 shows a relation between the BMD density in wafers and the SORI of said wafers; FIGURE 2 is a graph showing a relation between the BMD density in the wafers and the SORI of said wafers for every initial Oi; FIGURE 3 is a graph showing a relation between the BMD density in the wafers and the amount of oxygen precipitation for every initial Oi; FIGURE 4 is a graph showing a simulation heat treatment; FIGURE 5 is a graph showing a relation between the initial Oi in the wafers and the BMD density for every preheat treatment time; and FIGURE 6 is a graph showing a relation between the SORI of the wafers and the amount of oxygen precipitation. As will be understood from FIGURE 1 (Warpage of Czochralski - Grown Silicon Wafers as Affected by oxygen Precipitation: Japanese Journal of Applied Physics, Vol. 24, No. 7, July, 1985, P. 818), it is known that referring to the relationship between the BMD density and the SORI of a wafer said SORI increases as said density increases. The inventors of this invention have made a further research in detail as to said relationship, and as a result, they have found that even if the BMD density is the same a difference occurs in the SORI values of the wafer after being subjected to a simulation heat treatment because of the different initial oxygen concentrations. This result appears in FIGURE 2. FIGURE 3 is a graph where the amount of precipitated oxygen is given in the axis of the abscissas. It will be found from FIGURE 3 that even in the case of the same BMD density and the same amount of oxygen precipitation the SORI of wafer after simulation heat treatment is smaller in the lower initial Oi in the wafer. By the simulation heat treatment referred to herein is meant a heat treatment process as illustrated in FIGURE 4. This heat treatment is conventionally, most generally adopted in business circles of this technical field, as the one where steps of the device process are simulated. As abovementioned, even in the same BMD density the SORI of a wafer after simulation heat treatment becomes smaller in the lower initial Oi in the wafer, and therefore, to decrease the SORI as much as possible it results in that advantageously wafers lowest in initial Oi are selected for presentation to manufacturing. Practically, however, wafers of too low initial Oi need an extremely long period of time for a preheat treatment which is effected before the simulation heat treatment, so that in selecting the lower initial oxygen concentration there naturally is a lower limit from the viewpoint of productivity. If on the other hand the wafers are of too high initial Oi the wafers are greatly warped even if the BMD density could be guaranteed with a heat treatment of a shorter period of time, or the wafers themselves become brittle, so that there is also a suitable upper limit in the too high initial oxygen concentration. Now, if, in a first step, the wafer SORI and the BMD density in the simulation heat treatment to be an index or in the heat treatment in the processing are specified in certain desired ranges being required by the device yield or the gettering capability, the range of the initial Oi to satisfy said ranges becomes limited. It is added that generally the initial oxygen concentration is in the range from 1x10 17 to 20x10 17 atoms/cc. Then, if, in a second step, there is obtained a preheat treatment time of simultaneously satisfying the initial Oi range and the desired BMD density range both limited in the first step, in view of the relation between the initial Oi and the BMD density obtained previously for every period of time of preheat treatment, said period of time obtained becomes a preheat treatment condition for ensuring the desired BMD density and limiting the SORI below a desired range. Thus, the feature of the present invention is to subject the wafer in the initial Oi range chosen in the first step to a preheat treatment for the period of time obtained in the second step. EXAMPLE 1 CZ silicon mirror wafers (polished wafers) of 3.5x10 17 to 17.5x10 17 atoms/cc in initial Oi range, 5" diameter, crystallographic axis <100>, P-type, and resistivity in the range 2-6Ω·cm were subject, being divided in initial oxygen concentrations, to a preheat treatment for 0.5 to 78 hours at 650°C respectively. Then, said wafers were thermally treated (hereinafter called C-MOS simulation) on the assumption of the DRAM manufacturing processing shown in FIGURE 4 to obtain thereby a relationship among the wafer SORI generated by thermal stress, the BMD density in the wafers, and the amount of oxygen precipitation, a result of which is as shown in FIGURES 2 and 3. It will be found from this Example that if the initial oxygen concentrations differ the wafers also differ in their SORI even in the case of the same BMD density after heat treatment. This means that lower initial Oi provides smaller SORI. Additionally, FIGURE 5 shows a graph where the initial Oi is taken in the axis of the abscissas and the BMD density is taken in the axis of the ordinates, and the relation there-between is illustrated for every period of preheat treatment time at 650°C. [EXAMPLE 2] Usually, the BMD density in the silicon wafers presented to the manufacturing of, for example, DRAM, is approximately in the range from 1 x 10 6 to 2 x 10 6 n/cm 2 . If, in view of the relation shown in FIGURE 2 of Example 1, the BMD density is in the range from 1 x 10 6 to 2 x 10 6 n/cm 2 and the SORI is required, for example, by less than 50 µm, it is evident that to satisfy the area (the slant line portion in FIGURE 2) surrounded by the axis of abscissas and the axis of ordinates, the wafers are limited to those whose initial Oi is less than 17 x 10 17 atoms/cc. It will also be evident that an initial Oi of at least more than 10 x 10 17 atoms/cc is necessary. That is, the setting of the initial Oi to higher than 10 x 10 17 atoms/cc as a necessary condition is due to the two reasons that if a CZ single crystal is drawn up as usual the oxygen concentration generally becomes higher than 10 x 10 17 atoms/cc, and as will be seen from FIGURE 5, if the initial Oi is too low in obtaining the BMD density, it takes too much time for the preheat treatment so as not to be practical. Therefore, when wafers whose initial Oi is less than 17 x 10 17 atoms/cc and more than 10 x 10 17 atoms/cc, for example whose initial Oi is 15.5 x 10 17 atoms/cc, are chosen, it will be clear that the wafers of said 1 x 10 6 to 2 x 10 6 n/cm 2 are limited particularly to 1 x 10 6 to 1.3 x 10 6 n/cm 2 in the BMD density range in order that the SORI value is less than 50 µm, if the intersecting area marked with said slant lines is observed from the axis of the abscissas. Then the invention will be described with reference to FIGURE 5. It will be evident from the curve partitioned with the BMD density range of 1x10 6 to 1.3x10 6 n/cm 2 and intersecting with the line of said initial Oi 15.5x10 17 atoms/cc that to insure the desired BMD density it suffices to adopt 135 to 175 minutes as the period of preheat treatment time at 650°C for the wafers of the initial Oi being 15.5x10 17 atoms/cc. EXAMPLE 3 25 CZ silicon wafers (of 5" diameter, crystallographic axis <100>, P-type, and resistivity 2-6 Ω·cm) whose initial Oi is less than 16x10 17 atoms/cc and more than 12x10 17 atoms/cc, were subject to a preheat treatment at every period of time at 650°C for every initial oxygen concentration, which periods of time were obtained in the manner of Example 2, and the wafers were formed with DRAM whereby the yield was observed with regard to the elements of 206 n/sheet. As a result, the quality devices were 187 n on average of 25 pieces and the yield was more than 90%. The SORIs of the wafers were all less than 50 µm while the BMD density fell under the range from 1x10 6 to 2x10 6 n/cm 2 . That is, referring to FIGURE 2, the relation thereof fits in the slant line area. COMPARATIVE EXAMPLE 1 CZ silicon mirror wafers (polished wafers) (of 5" diameter, crystallographic axis <100>, P-type, and resistivity 2-6 Ω·cm) whose initial Oi is less than 16x10 17 atoms/cc and more than 12x10 17 atoms/cc, were suitably subject to a preheat treatment at 650°C in a way that only the BMD comes under the range from 1x10 6 to 2x10 6 n/cm 2 , and said wafers were formed with DRAM elements whereby the yield was observed with regard to the elements of 206 n/sheet. As a result, the quality devices were 132 n on average of 25 pieces and the yield was 64%. Though the BMD density fell within the range from 1x10 6 to 2x10 6 n/cm 2 , almost half of the SORIs of the wafers was more than 50 µm. COMPARATIVE EXAMPLE 2 CZ silicon mirror wafers (polished wafers) (of 5" diameter, crystallographic axis <100>, P-type, and resisitivity 2-6 Ω·cm) whose initial Oi is more than 17x10 17 atoms/cc, were suitably subject to a preheat treatment at 650°C in such a way that only the BMD density comes within the range from 1x10 6 to 2x10 6 n/cm 2 , and said wafers were formed with DRAM whereby the yield was observed with regard to the devices of 206 n/piece. As a result, the quality devices were 21 n on average of 25 pieces and the yield was only 10%. Though the BMD density came under the range from 1x10 6 to 2x10 6 n/cm 2 , almost all of the SORIs of the wafers were greater than 50 µm. COMPARATIVE EXAMPLE 3 It was tried to effect a preheat treatment suitably at 650°C in such a manner that only the BMD density comes under the range from 1x10 6 to 2x10 6 n/cm 2 , to CZ silicon mirror wafers (polished wafers) (of 5" diameter, crystallographic axis <100>, P-type, and resisitivity 2-6 Ω·cm) whose initial Oi is less than 12x10 17 atoms/cc. However, it took an extremely long period of time for such a trial, to find that such wafers could hardly be usable when viewed from productivity. Additionally, though the BMD density in the wafers were measured in the respective Examples and Comparative Examples by using a light scattering tomography method, an etching method may be substituted therefor. Though each of said Examples is the one to apply the present invention to the manufacture of DRAM it was found that in SRAM the suitable BMD density is in the range from 2x10 6 to 5x10 6 n/cm 2 , and if the manufacturing steps are of high cleanness it is in the range from 1x10 4 to 5x10 4 n/cm 2 . That is, depending on the kinds of respective devices or the cleanness in the manufacturing steps the optimum BMD density is required for the wafers. FIGURE 2 used in the Examples expresses a relationship between the BMD density and SORI of wafers in the C-MOS simulation on the assumption of DRAM, and it is possible to easily obtain a relationship between the BMD density and the SORI by suitably adopting proper simulations for respective elements of SRAM, mask ROM, BIPOLAR, etc. The relationship between the BMD density and the SORI slightly varies according to the thermal treatment conditions in the manufacture of the respective elements or the kinds of wafers employed in manufacturing devices, but the dependency upon the initial oxygen concentration was the same in all simulations. In order to secure a certain BMD density that is required from the gettering capability a suitable selection may be possible by combining the initial Oi in the wafer with the preheat treatment condition. However, in using the present process it is capable of efficiently selecting, at a short period of time, without relying on trial and error, a combination of said various conditions for restraining the SORI of wafer minimum and securing the BMD density necessary for the manifestation of a desired gettering capability. According to the present invention, wafers are chosen on the basis of the initial oxygen concentration in wafer, as a target, said concentration correlating with the occurrence of SORI, and finally the time of preheat treatment in making devices is determined, so that as will be clear even from the Examples, the yield is improved and the productivity is enhanced compared with known processes. Though the present invention has been described mainly in respect of SORI of wafers, but according to the invention it is also possible to cope similarly with a slip to be continuous defects caused by the SORI. Moreover, though the temperature of preheat treatment has been fixed to determine the time for the preheat treatment in the invention, it is possible to determine the optimum time for the preheat treatment even if said temperature changes, by means of a similar operation in response to the change of temperature. Further, it is possible to apply the present invention even to wafers subjected to a heat treatment at high temperature (usually higher than 1,100°C) for the outward diffusion of oxygen before the preheat treatment for the formation of oxygen precipitate nuclei thereby setting the optimum preheat treatment conditions without relying on trial and error. This is because that it has been confirmed with a C-MOS simulation, as shown in FIGURE 6, that any difference does not occur in the relationship between the SORI value and the amount of oxygen precipitaiton if the initial oxygen concentration remains the same, irrespective of entry or non-entry into a heat treatment process at high temperature before the preheat treatment for the formation of an oxygen precipitate nucleus. The present invention is applied in manufacturing semiconductor devices.

Claims: A process for manufacturing a semiconductor device from a silicon single crystal wafers characterised in that suitable silicon single crystal wafers for the manufacturing process are selected by determining that the initial oxygen concentration of the wafer is within a range such as to produce after heat treatment during the required device processing a SORI below a limiting value as required by the intended device yield and a bulk micro defect density in a range corresponding to the required gettering capability of the device, and the selected wafer is preheat treated is to obtain a bulk micro defect density which is within the aforesaid range of bulk micro defect density, the period of time of said preheat treatment being dependent on the said initial oxygen concentration of the selected wafer. A process for manufacturing a semiconductor device as claimed in claim 1 wherein the SORI limiting value of the wafer is not higher than 300 µm, and the bulk micro defect density is not greater than 10 10 n/cm 2 .

Inventors: KAWAHARA HIROYUKI, KONO MITSUO, KAWAHARA, HIROYUKI, KONO, MITSUO, KAWAHARA, HIROYUKI, 812-1, SHINOMIYA, KONO, MITSUO, WAKAMIYA HEIGHTS 1-505
Applicants: KOMATSU DENSHI KINZOKU KK, KOMATSU ELECTRONIC METALS CO., LTD
Application year: 1991
Main classification: H01L21
IPC codes: H01L21