MOS-type semiconductor integrated circuit device

Abstract: In the semiconductor integrated circuit device of the present invention which uses MOSFETs as its components, the gate electrode of the MOSFET is constructed by using a silicide gate, a polycide gate or a metal gate. The source-drain region of the MOSFET for the internal circuit which does not require connection to an external circuit has the salicide structure, and the source-drain region of the MOSFET for the buffet circuit which requires a direct connection to an external device has a region which is not of salicide structure at least in a portion adjacent to the gate electrode. The gate electrode and the source-drain region of the internal circuit become to have low resistances so that it is possible to realize an increase in the operating speed by using them as a part of the wirings. Further, in the source-drain region of the buffer circuit there is provided a region of high resistance in the vicinity of the gate electrode so that it is possible to enhance the ESD resistance.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit device containing MOSFETs. More particularly, the present invention relates to a semiconductor integrated circuit device including MOSFETs having metal silicide films on the surface of source and drain regions. Description of the Prior Art In semiconductor integrated circuit devices, reduction in the element dimension has been progressing rapidly due to increase in the device density and increase in the operating speed. Further, in semiconductor integrated circuit devices including MOSFETs, suppression of the short channel effect of the MOSFETs is also required. For this purpose, source and drain regions are made shallow. However, making the junction of the source-drain diffused layer shallow brings about an increase in the sheet resistance thereof. Since the source and drain diffused layers and the gate electrodes are used as a part of the wirings, the increase in the sheet resistance of the diffused layers and the reduction in the size of the gate electrodes causes increase in the wiring resistance to lower the operating speed of the circuit. The increase in the sheet resistance of the gate electrode due to the reduction in the size thereof can be prevented by using suitable material for the gate electrodes. In recent years, in place of a gate electrode only made of a polycrystalline silicon film (the so-called silicon gate electrode), a gate electrode having a structure of laminating a metal silicide film on a polycrystalline silicon film (the so-called polycide structure) or a gate electrode only made of a metal silicide film has been used. Further, a gate electrode made of a refractory metal has been employed. On the other hand, concerning the sheet resistance, a structure for reducing the sheet resistance of regions was disclosed in IEDM Tech. Dig., 1982, pp. 714-717 by C.K. Lau et al. According to this structure, a metal film is deposited on the surface of a diffused layer (or region) formed in the surface portion of a silicon substrate, silicification reaction is induced by heat treatment between silicon of the diffused layer and the metal film, the metal film left unreacted being thereafter removed. Thus, a metal silicide film is formed in self-aligned fashion with respect to the diffused layer. The structure of MOSFET obtained thus is called "salicide" (abbreviation for self-aligned silicide). The sheet resistance of the diffused layer is thereby converted from several tens to one hundred and several tens of ohms/square (Ω/□) into several ohms/square (Ω/□). However, a MOSFET with the salicide structure has resistance against electrostatic discharge (called hereinafter "ESD resistance") that is remarkably smaller than ESD of a MOSFET not having the salicide structure, as reported by K.L. Chen, et al, in IEDM Tech. Dig., 1986, pp. 484-487. According to the present inventor, moreover, ESD resistance of a MOSFET with the salicide structure is about one-third of that of a MOSFET not having the salicide structure. The reason for this can be considered as follows. That is, the salicide structure reduces the resistance of the diffused layer itself. When a discharge current due to static electricity flows into the diffused layer (in particular the drain diffused layer) of a MOSFET, therefore, the current tends to concentrate at the portion of the layer just under the end part of the gate electrode. Consequently, a local thermal breakdown is apt to be generated in the gate insulating film in the vicinity of the gate electrode end part. The MOSFET is thereby destoyed. Thus, MOSFETs with the salicide structure in buffer circuits such as an input buffer circuit, an output buffer circuit and an I/O buffer circuit deteriorate EDS resistance of an integrated circuit device. Patent Abstracts of Japan vol. 11, no. 41 (E-478), (2488) of JP-A-61207051 discloses a TRA consisting of a source region, a drain region and a gate electrode to be formed through a thick gate oxide film and a TRB consisting of source region, a drain region and a gate electrode to be formed through a thin gate oxide film. Both of the TRA and the TRB are formed in an offset structure. Accordingly, even though a shortening of the channels of electronlc device goes one, these MOS transistors having the drain regions, which are formed in an offset structure, are used as ones for the protective circuit and even when high voltage is impressed between the source region and the drain region or between the gate electrode and the drain region, an electric field does never concentrate on the end parts of the drain regions. Therefore, electrons do never gate. SUMMARY OF THE INTENTION It is an object of the present invention to provide an improved semiconductor integrated circuit device adapted for increasing an operating speed. It is another object of the present invention to provide a semiconductor integrated circuit device for increasing the operating speed without reducing ESD resistance. It is a still another object of the present invention to provide a method of fabricating a semiconductor integrated circuit device operating at a high speed with large ESD resistance. A semiconductor integrated circuit device according to the present invention is defined in claim 1. It includes a first MOSFET employed in buffer circuit for interfacing with an external device and a second MOSFET employed in an internal circuit. Each of gate electrodes of the first MOSFET and the second MOSFET is made of a first metal, or a silicide film of the first metal, or a laminated film consisting of a polycrystalline silicon film and a silicide film of the first metal. The first MOSFET has a silicide film of a second metal that is provided on the surface of a source and/or drain region away from the gate electrode thereof, whereas the second MOSFET has the silicide film of the second metal that is provided on the surface of a source/drain region adjacent to the gate electrode thereof. It is convenient that the first metal is selected from tungsten, molybdenum and titanium and that the second metal is selected from titanium, cobalet and tantalum. Since each of the first and second MOSFETs is lowered in resistance of the gate electrode and the second MOSFET has low resistance in the source-drain diffused layer, a.high speed operation is performed. Moreover, the ESD resistance of this semiconductor integrated circuit device is high because the first MOSFET has selectively high resistance in the source-drain region adjacent to the gate electrode. There is provided a method of fabricating a semiconductor, integrated circuit device including a buffer circuit containing a first MOSFET and an internal circuit containing a second MOSPET, the method comprising the steps of forming a buffer circuit forming region and an internal circuit forming region by selectively forming a field insulating film on the surface of a silicon substrate, forming gate insulating films on the surface of the buffer circuit forming region and the internal circuit forming region, forming on the gate insulating films a gate electrode of the first MOSFET and a gate electrode of the second MOSFET by patterning a first metal, or a silicide film of the first metal, or a laminated layer of a polycrystalline silicon film and a silicide film of the first metal, which is formed over the entire surface, forming a low concentraion source-drain diffused layer of the first MOSFET and a low concentration source-drain diffused layer of the second MOSFET by using the gate electrode of the first MOSFET and the gate electrode of the second MOSFET as the mask, forming spacers consisting of a first insulating film on he side faces of the gate electrode of the first MOSFET and the gate electrode of the second MOSFET, removing the gate insulating film except for the regions directly beneath the gate electrode of the first MOSFET, the gate electrode of the second MOSFET and the spacers, covering the gate electrode of the first MOSFET and at least a predetermined region adjacent to this gate electrode with a second insulating film, forming a film consisting of a second metal, and forming a silicide film of the second metal by heat treatment. When the gate electrode of the first MOSFET and the gate electrode of the second MOSFET are made of the first metal, and when the second metal is the same as the first metal, it is preferable that the aforementioned fabrication method further comprises the step of forming a third insulating film over the entire surface after the formation of the first metal or the silicide film of the first metal or the laminated layer of the polycrystalline silicon film and the silicide film of the first metal. The third insulating film thus prevents the first metal or the silicide film of the first metal from being in direct contact with the film of the second metal, so that it is possible to avoid abnormality in the shapes of the gate electrodes and the surface levels of the channel regions. BRIEF DESCRIPTION OF THE DRAWINGS The above-mentioned and other objects, features and advantages of this invention will become apparent by reference to the following detailed description taken in conjunction with the accompanying drawings, wherein: FIG. 1A is a schematic plan view for describing a first embodiment of the present invention, and FIG. 1B is a schematic sectional view of the first embodiment along the line XY; FIGs. 2A to 2H are schematic sectional views arranged in the order of the processes for describing the fabrication method of the semiconductor integrated circuit of the first embodiment; FIG. 3 is a schematic sectional view for describing a first example of application of the first embodiment in the above; FIG. 4 is a schematic sectional view for describing a second example of application of the first embodiment; FIG. 5 is a schematic sectional view for describing a third example of application of the first embodiment; FIGS. 6A to 6D are schematic sectional views arranged in the order of processes for describing the fabrication method of a second embodiment of the present invention; FIG. 7 is a schematic circuit diagram for describing the ESD measurement of the output buffer circuit; and FIGs. 8A and 8B are diagrams for describing the effects of the first and the third embodiments, respectively, of the present invention, and are the graphs for showing the measurement result of ESD of the output buffer circuits in the semiconductor integrated circuit devices that are applications of the first embodiment of the present invention. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Referring to FIG. 1A and FIG. 1B which show a schematic plan view and a schematic sectional view, respectively, for describing the constitution of the first embodiment of the present invention, the semiconductor integrated circuit device of the present invention is constituted of a buffer circuit (it may be one of the three types of an input buffer circuit, output buffer circuit and I/O buffer circuit, but it will be referred to simply as a buffer circuit hereinafter) that is directly connected to an external device (not shown), and an internal circuit which is coupled via the buffer circuit to the external device. The buffer circuit and the internal circuit can be constructed by a single channel MOSFET, C-MOSFET, or Bi-CMOSFET. For simplicity, the present embodiment will be described by reference to a semiconductor integrated circuit device constructed exclusively by an N-channel MOSFET that has a source-drain diffused layer of a so-called LDD structure. Selectively formed on the surface of a P-type silicon substrate 101 is a field oxide film 102 having thickness of about 800 nm. By the presence of the field oxide film 102, the surface of the silicon substrate 101 is partitioned into a buffer circuit region 121 and an internal circuit region 122. In the buffer circuit region 121 and the internal circuit region 122 there are formed a first N-channel MOSFET and a second N-channel MOSFET. The first and the second MOSFETs have a gate oxide film with thickness of 21.5 nm and gate electrodes 106a and 106b of the polycide structure, respectively. The gate electrode 106a is formed of an N + -type polycrystalline silicon film 104a and a tungsten silicide film 105a, and the gate electrode 106b is formed of an N + -type polycrystalline silicon film 104b and a tungsten silicide film 105b. The thickness of the polycrystalline silicon films 104a and 104b is about 200 nn, and the thickness of the tungsten silicide films 105a and 105b is about 200 nm. The sheet resistance of the gate electrodes 106a and 106b is about 6 Ω/□. On the side faces of the gate electrodes 106a and 106b there is formed respectively a spacer 109 consisting of a silicon oxide film. The width of the spacer 109 is about 200 nm. The first and the second MOSFETs have N - -type source-drain diffused layers 107a and 107b, respectively, that are formed in self-alignment manner with the gate electrodes 106a and 106b. In addition, the first and the second MOSFETs respectively have N + -type source-drain diffused layers 113a and 113b that are formed in self-alignment manner with the spacer 109 and the gate electrode 106a, and the spacer 109 and the gate electrode 106b. On the surface of the N + -type source and drain diffused layers 113a there are formed titanium silicide films 112a with a distance of d (see FIG. 1A) from the gate electrode 106a. On the other hand, titanium silicide films 112b are formed on the source and drain regions 113b in self-alignment manner with the spacer 109. The titanium silicide films 112a and 112b have a thickness of about 160 nm, and their sheet resistance is about 2 Ω/square. Note that each of the N + -type source and drain diffused layers 113 and 113b itself has sheet resistance of about 40 Ω/square. On the surface of the semiconductor integrated circuit device there is formed an interlayer insulating film 114 with thickness of about 1 µm. In this titanium silicide film 114 there are provided contact holes 115 which reach the titanium silicide films 112a and 112b. In the present embodiment, the titanium silicide films 112a and 112b function as barrier metals. Because of this, the increase in the contact resistance can be kept small even if the diameter of the contact holes 115 is made small. Moreover, there is no need for intentionally making the diameter of the contact holes for the first MOSFET. The source-drain diffused layer (consisting of an N - -type source-drain diffused layer 107, titanium silicide film 112 and N + -type source-drain diffused layer 113) and the gate electrode in the present embodiment will lead to no inconvenience even if they are diverted as a part of wirings. This is due to the fact that the sheet resistance of the source-drain diffused layers and the gate electrodes in the present embodiment is sufficient low compared with that of the conventional case. Moreover, in the first N-channel MOSFET that constitutes the buffer circuit of the present embodiment, the gate electrode 106a and the titanium silicide film 112a are isolated. The source-drain region in between is constituted of the N + -type source-drain diffused layer 113a that has a sheet resistance of about 40 Ω/□. Because of this, the thermal breakdown at the edges of the gate electrode 106a will not be conspicuous even if a discharge current flows in from an external device to the source-drain diffused layer 113a of the buffer circuit. Next, referring to FIGs. 2A to 2H which show the method of fabrication of the semiconductor integrated circuit described in the above, first, on the surface of a P-type silicon substrate 101, a field oxide film 102 with thickness of about 800 nm is formed by a selective oxidation method. By the formation of the field oxide film 102, there are formed simultaneously a buffer circuit region 121 and an internal circuit region 122. The regions 121 and 122 are respectively surrounded by the field oxide film 102 (see FIG. 1A). On the surface of the regions 121 and 122 a gate oxide film 103 with thickness of 21.5 nm is formed by a thermal oxidation method. Following that, an N + -type polycrystalline silicon film 104 with thickness of about 200 nm is formed allover the surface by a CVD method. Then, a tungsten silicide film 105 with thickness of about 200 nm is deposited allover the surface by a sputtering method. On the tungsten silicide film 105 there is formed a pattern for the photoresist film 131. The photoresist film 131 is the etching mask for the gate electrodes (FIG. 2A). The width of the photoresist film 131 corresponds to the gate length. In the present embodiment it is assumed that the gate lengths of the first and the second MOSFETs are equal, but it needs not be limited to that case only. Next, the tungsten silicide film 105 and the polycrystalline silicon film 104 are etched in succession by using the photoresist film 131 as the mask. By this operation, the gate electrodes 106a and 106b with the polycide structure of the first and the second MOSFETs are formed. The gate electrode 106a is formed by the N + -type polycrystalline silicon film 104a and the tungsten silicide film 105a, and the gate electrode 106b is formed by the N + -type polycrystalline silicon film 104b and the tungsten silicide film 105b. The N - -type source-drain regions 107a and 107b of the first and the second MOSFETs are formed by ion implantation of phosphorus. The N - -type source-drain regions 107a and 107b are self-aligned with respect to the gate electrodes 106a and 106b. The conditions for the phosphorus ion implantation are an implantation energy in the range of 20 to 100 keV and a dose of about 1 x 10 13 cm -2 . After removed of the photoresist film 131, a silicon oxide film 108 with thickness of about 200 nm is deposited allover the surface by a CVD method (FIG. 2B). Next, the silicon oxide film 108 is etched back, and a spacer 109 consisting of a silicon oxide film is formed on the side face of the gate electrodes 106a and 106b. Then, a silicon oxide film 110 with thickness of about 30 nm is deposited allover the surface by a CVD method (FIG. 2C). Next, a pattern for the photoresist film 132 is formed on a predetermined region of the buffer circuit region 121. The predetermined region is the region of the gate electrode 106a and the region within a distance d (see FIG. 1A) from the gate electrode 106. A silicon oxide film 110a is formed by etching the silicon oxide film 110 using the photoresist film 132 as the mask (FIG. 2D). Next, the photoresist film 132 is removed, and a titanium film 111 with thickness of about 100 nm is deposited allover the surface by sputtering (FIG. 2E) Next, titanium silicide films 112a and 112b are formed by a heat treatment at 600 to 800°C in an inert atmosphere. The unreacted titanium film 111 is removed by etching (FIG. 2F). At the time of the silicification reaction the tungstem silicide film 105b and the titanium film 111 are in direct contact, but the silicification reaction will not take place in that section. The fabrication method according to the present embodiment can be applied to the case where a metallic silicide film consisting of the first metal is the component element of the gate electrode by making the first metal (tungsten in the present embodiment) different from the second metal (titanium in the present embodiment). However, the present fabrication method is not applicable when the first metal and the second metal are the same, and when the gate electrode is formed of a metal consisting of the first metal. Next, the silicon oxide film is removed. Then, the N + -type source-drain diffused layers 113a and 113b are formed by an arsenic ion implantation that uses the field oxide film 102, the gate electrodes 106a and 106b and the spacers 109 as the mask. The ion implantation conditions are an implantation energy in the range of 70 to 100 keV ana a dose of 1 x 10 15 to 5 x 10 15 cm -2 (FIG. 2G). Next, an interlayer insulating film 114 with thickness of about 1 µm is formed allover the surface by a CVD method (FIG. 2H). In the interlayer insulating film 114 there are formed contact holes 115 that reach the titanium silicide films 112a and 112b (FIGs. 1A and 1B). The fabrication method in the above has been described with reference to the case of N-channel MOSFET but the fabrication method is also applicable to P-channel MOSFET. Further, the method is also applicable to C-MOSFET and Bi-CMOSFET. Referring to FIG. 7, and FIGs. 8A and 8B, ESD related to the semiconductor integrated circuit device of the present embodiment will be described. The buffer circuit and the internal circuit are constructed by using C-MOSFETs to which are applied the present embodiment. The output buffer circuit consists of a C-MOS inverter. In the C-MOS inverter, the gate length L and the gate width W are 1.5 and 500 nm, respectively, for both cases of the N-channel MOSFET and the P-channel MOSFET. The thickness of the gate oxide film of the N-channel MOSFET and the P-channel MOSFET is about 21.5 nm. The gate electrode for both cases of the N-channel MOSFET and the P-channel MOSFET is constructed by a 200 nm thick tungsten silicide film and a 200 nm thick N + -type polycrystalline silicon film. The spacer is made of a silicon oxide film, and its width is about 200 nm. On the surface of the source-drain diffused layer for both cases of the N-channel MOSFET and the P-channel MOSFET there is formed a titanium silicide film with thickness of about 160 nm. The spacing d between the titanium silicide film and the gate electrode is 4 µm for both cases of the N-channel MOSFET and the P-channel MOSFET. On the other hand, as a semiconductor integrated circuit device of the conventional structure, a device identical to the present embodiment except for the spacing d between the titanium silicide film and the gate electrode is 200 nm (spacer width) was manufactured. In this device, allover the surface of the source-drain diffused layer of the C-MOSFET that constitutes the output buffer circuit there is formed a titanium silicide film. In this C-MOS inverter the spacing between the gate electrode and the contact hole is 4 µm shorter than the device of the present embodiment. For the two output buffer circuits described above, an ESD test based on MIL-STD-883C, Method 3015.2 was carried out. An example of the ESD test is that, in the circuit shown in FIG. 7, the GND terminal is taken as the standard, a bias voltage is applied between the output terminal and the GND terminal and the Vdd terminal, input terminal (not shown), I/O terminal (not shown) and another output terminal (not shown) are left opened. The results of the test are as shown in FIGs. 8A and 8B. FIG. 8A is a graph that shows the dependence of the non-defective ratio on the positive bias voltage, while FIG. 8B is a graph that shows the dependence of the non-defective ratio on the negative bias voltage. In FIGs. 8A and 8B, the broken line A represents the result for the applied example of the present embodiment, and the broken line C represents the result for the conventional structure. As is clear from the figures, for the case of the positive bias voltage, the ESD resistance of the applied example of the present embodiment is enhanced to about 1.5 times that of the conventional structure. On the other hand, for the case of negative bias voltage, the ESD resistance of the applied example of the present embodiment is enhanced to about 1.2 times that of the conventional structure. The first embodiment of the present invention represents the case of the application to the N-channel MOSFET which has a source-drain diffused layer of the LDD structure. This case is suited for the case when the buffer circuit and the internal circuit are driven by a relatively high source voltage, for example, of 5V class. FIG. 3, FIG. 4 and FIG. 5 are schematic sectional views for examples when the first embodiment is applied to N-channel MOSFETs having source-drain diffused layers of other structures (or combinations with other structures). Referring to FIG. 3 which is a schematic sectional view for describing the first applied example of the first embodiment, the first N-channel MOSFET of the buffer circuit region 121 in this applied example is the same as that of the first embodiment. On the other hand, the second N-channel MOSFET of the internal circuit region 122 has a source-drain diffused layer of the single drain structure. This source-drain diffused layer is constructed by the titanium silicide film 112b and an N + -type source-drain diffused layer 113d formed in self-alignment with the gate electrode. The present applied example is suited for a semiconductor integrated device in which the peripheral circuits containing the buffer circuit is driven by a source voltage of 5V class and the internal circuit is driven, for example, by a source voltage of 3.3V class. In the present applied example it is possible to make the internal circuit region have a finer geometry than in the first embodiment, and hence the device can be made to have higher operating speed than the case of using the first embodiment. The key points of the fabrication method of the present applied example will be described. After formation of the gate electrodes, the internal circuit region 122 is covered with a photoresist film, and an N - -type source-drain diffused layer 107a is formed by the ion implantation of phosphorus. Then, the buffer circuit region 121 is covered with another photoresist film, and an N + -type source-drain diffused layer 113d is formed by ion implantation of arsenic under the implantation conditions of 70 keV and 1 x 10 15 cm -2 . Besides these points, the process of the present applied example that differ from the first embodiment is that the internal circuit region 122 is covered with a photoresist film at the time of ion implantation in the formation of the N + -type source-drain diffused layer 113a. Referring to FIG. 4 which is a schematic sectional view for describing the second applied example of the first embodiment, the second N-channel MOSFET of the internal circuit region 122 in the present applied example has a source-drain diffused layer of the DDD structure. This source-drain diffused layer consists of a titanium silicide film 112b, an N - -type source-drain diffused layer 107d formed in self-alignment with the gate electrode and an N + -type source-drain diffused layer 113d. Analogous to the first applied example, the present applied example is adapted for a semiconductor integrated circuit whose peripheral circuits including the buffer circuit is driven by a source voltage of 5V class, and whose internal circuit is driven, for example, by a source voltage of 3.3V class. Compared with the first applied example, the present applied example has a higher reliability for the hot carriers. The principal points of the method of fabricating the present applied example will be described. After formation of the gate electrodes, the internal circuit region 122 is covered with a photoresist film, and an N - -type source-drain diffused layer 107a is formed by ion implantation of phosphorus. Then, the buffer circuit region 121 is covered with another photoresist, and an N - -type source-drain diffused layer 107d is formed by ion implantation of phosphorus under the conditions of 70 keV and 1 x 10 14 cm -2 or so. Further, an N + -type source-drain diffused layer 113d is formed by ion implantation of arsenic under the approximate conditions of 70 keV and 1 x 10 15 cm -2 . Besides these, the process which is different from that of the first embodiment is that the internal circuit region 122 is covered with a photoresist film at the time of ion implantation for the formation of the N + -type source-drain diffused layer 113a. Referring to FIG. 5 which is a schematic sectional view for describing the third applied example of the first embodiment, the first MOSFET of the buffer circuit region 121 and the second MOSFET of the internal circuit region 122 in the present applied example have a source-drain diffused layer of the DDD structure. The source-drain diffused layer of the first MOSFET is constituted of a titanium silicide film 112a, an N - -type source-drain diffused layer 107c formed in self-alignment with the gate electrode and an N + -type source-drain diffused layer 113c formed in self-alignment with the gate electrode. The present applied example is adapted for a semiconductor integrated circuit device in which the peripheral circuit including the buffer circuit, and the internal circuit are driven by a relatively low, for example, 3.3V class, source voltage. The principal points of the fabrication method of the present applied example are the formation of the gate electrodes, followed by the formation of N - -type source-drain diffused layers 107c and 107d by ion implantation of phosphorus under approximate conditions of 70 keV and 1 x 10 14 cm -2 , followed further by the formation of N + -type source-drain diffused layers 113c and 113d by ion implantation of arsenic under approximate conditions of 70 keV and 1 x 10 15 cm -2 . Referring to FIGs. 6A to 6D which are schematic sectional views arranged in the order of the processes for describing the fabrication method of the second embodiment of the present invention, it can be seen that the present embodiment can be applied to the first embodiment and the applied examples of the first embodiment, and can also be applied to the case where the second metal is the same as the first metal and to the case where the gate electrodes are made of a metallic film. In the present embodiment, description will be presented for the case of the N-channel MOSFET where the first metal and the second metal are titanium. First, on the surface of a P-type silicon substrate 201 there is formed a field oxide film 202 with thickness of about 800 nm by a selective oxidation method. As a result of formation of the field oxide film 202, a buffer circuit 221 and an internal circuit region 222 that are respectively surrounded by the oxide film 202 are formed simultaneously. On the surface of the regions 221 and 222 there is formed a gate oxide film 203 with thickness of 21.5 nm by a thermal oxidation method. Next, an N-type polycrystalline silicon film 204 with thickness of about 300 nm is formed allover the surface by a CVD method, and a titanium film 216 of thickness of about 100 nm is deposited by a sputtering method (FIG. 6B). Next, the sample is subjected to a heat treatment at 600 to 800°C in an inert atmosphere. As a result of this heat treatment a titanium silicide film 217 with thickness of about 200 nm is formed, and at the same time the N-type polycrystalline silicon film 204 is converted to an N-type polycrystalline silicon film 224 with thickness of about 200 nm. The sheet resistance of this laminated film is about 2 Ω / □. Then, a silicon oxide film 218 with thickness of about 200 nm is deposited by a CVD method. On the silicon oxide film 218 there is formed a photoresist film 231. The photoresist film 231 is the etching mask for gate electrodes (FIG. 6B). Next, the silicon oxide film 218, the titanium silicide film 217 and the polycrystalline silicon film 224 are sequentially etched by using the photoresist film 231 as the mask. As a result, gate electrodes 206a and 206b of the polycide structure for the first and the second MOSFETs are formed. The gate electrode 206a is formed by the N-type polycrystalline silicon film 224a and the titanium silicide film 217a. The gate electrode 206b is formed by the N-type polycrystalline silicon film 224b and the titanium silicide film 217b. On the top faces of the gate electrodes 206a and 206b there is remaining the silicon oxide film 218. The N - -type source-drain regions 207a and 207b of the first and the second MOSFETs are formed by ion implantation of phosphorus. After removal of the photoresist film 231, a silicon oxide film with thickness of about 200 nm is deposited allover the surface by a CVD method, and a spacer 209 is formed by etching back the silicon film. In this process of etching-back, the thickness of the silicon oxide film 218 is reduced somewhat, but the thickness of about 150 nm still remains there. A silicon oxide film 210 with thickness of about 30 nm is deposited allover the surface by a CVD method (FIG. 6C). Following that, titanium silicide films 212a and 212b, N + -type source-drain diffused layers 213a and 213b are formed by the same method as in the fabrication of the first embodiment, an interlayer insulating film 214 is deposited by a CVD method, and contact holes 215 are formed (FIG. 6D). Since the present embodiment has a sheet resistance of the gate electrode which is smaller than that of the first embodiment, so that there can be obtained a semiconductor integrated circuit device with higher operating speed. It is to be noted that a method is employed in the present embodiment by which the titanium silicide film 217 and the titanium silicide film 212 are formed separately. The reason for doing so is that if a method is employed in which a pattern for the gate electrodes is formed first by means of a polycrystalline silicon film alone, followed by the formation of the spacers, and the gate electrodes are silicified simultaneous with the source-drain forming region, then the shape of the gate electrodes tend to be deformed due to volume expansion of the gate electrode part, which renders the fine geometry of the gate electrodes extremely difficult.

Claims: A semiconductor integrated circuit device comprising a buffer circuit including a first MOSFET (121) to interface with an external device and an internal circuit operatively coupled to said buffer circuit and including a second MOSFET (122), said first MOSFET having a first gate electrode (106a) formed on a first gate insulating film (103), a first source region (113a, 107a) and a first drain region (113a, 107a) being arranged such that there is no lateral offset between an an edge of each of said source and drain regions (113a,107a) and adjacent edge of said first gate electrode, said second MOSFET having a second gate electrode (106b) formed on a second gate insulating film (103), a second source region (113b, 107b) and a second drain region (113b, 107b), said first MOSFET further having a first silicide film (112a) selectively formed on a surface of at least one of said first source and first drain regions at a first lateral distance from an edge of said first gate electrode, said second MOSFET further having a second silicide film (112b) selectively formed on a surface of at least one of said second source and second drain regions at a second lateral distance from an edge of said second gate electrode; said first distance being lager than said second distance. The semiconductor integrated circuit device as claimed in claim 1, wherein each of said first and second gate electrodes includes a third silicide film (105a, 105b) of a first metal and each of said first and second silicide films is made of silicon end a second metal. The semiconductor integrated circuit device as claimed in claim 2, wherein said first metal is selected from tungsten, molybdenum and titanium and said second metal is selected from titanium, cobalt and tantalum.

Inventors: OOKA HIDEYUKI, OOKA, HIDEYUKI, OOKA, HIDEYUKI, C/O NEC CORPORATION
Applicants: NEC ELECTRONICS CORP, NEC ELECTRONICS CORPORATION
Application year: 1991
Main classification: H01L27
IPC codes: H01L29, H01L23, H01L27