Method of manufacturing a thin-film semiconductor device on a transparent insulative substrate

Abstract: In a method of manufacturing a TFT on a transparent insulative substrate 11, a gate electrode 12 is formed selectively on the surface of the substrate 11, and an insulative films 13 and 14, a semiconductor active layer 15 and a channel protection layer 16 are deposited on the entire surface of the resultant structure. Thereafter, the reverse side of the substrate is exposed to pattern the channel protection layer 16, with the gate electrode 12 used as a mask. The reverse side of the substrate is exposed once again, thereby patterning the semiconductor activation layer 15 with the gate electrode 12 used as a mask, such that the width in the channel direction of the semiconductor activation layer 15 is greater than that of the channel protection layer 16. Thus, the semiconductor activation layer 15 and the channel protection layer 16 are formed in a self-alignment manner in relation to the gate electrode 12.

Description: The present invention relates generally to a method of manufacturing a thin-film semiconductor device on a transparent insulative substrate, and more particularly to a method of manufacturing a thin-film semiconductor device by means of a reverse-side exposure process. As a conventional thin-film semiconductor device, there is known a reverse stagger type thin-film transistor (TFT), as shown in Fig. 3. The reverse stagger type TFT is manufactured in the following manner. A metal thin film is deposited on an insulative substrate 1. The metal thin film is patterned by means of photolithography with use of a photomask, thereby forming a gate electrode 2. Thereafter, insulative layers 3 and 4, a semiconductor active layer 5 and a channel protection layer 6 are deposited by means of plasma CVD. Subsequently, the channel protection layer 6 is patterned by means of lithography with use of a photomask. After a contact layer 7 is deposited, the active layer 5 for the TFT is formed in an island shape by means of lithography with use of a photomask. Then, in order to attain a contact with the gate electrode 2 of the TFT, the insulative layer 3 is patterned to form an aperture by means of lithography with use of a photomask. After the aperture is formed, a metal layer for forming a source/ drain electrode is deposited, and a source/drain electrode 8 is formed by means of lithography with use of a photomask. As has been described above, in order to manufacture the TFT, at least five photomasks are required. In the example shown in Fig. 3, except the gate patterning, the patterning using photomasks must be performed while the patterns are aligned with each other. The alignment of the patterns directly determines the shape of the semiconductor device. If the patterns are not precisely aligned, desired characteristics are not obtained. In particular, in a liquid crystal display device using this type of TFT at a large area, non-uniformity in the shape and characteristics of the TFT results in a non-uniformity quality of images. Consequently, the productivity and yield is degraded. Regarding the TFT shape shown in Fig. 3, the formation of the channel protection layer 6 is especially important. The reason is that the channel protection layer 6 serves not only as a protection layer but also as a pattern for determining the channel length and channel width of the TFT. When the pattern is formed with use of a photomask, the exact alignment between the pattern and the gate electrode 2 is very important in order to attain constant TFT characteristics. In this case, the pattern must be aligned with respect to vertical/horizontal components as well as rotational components. Therefore, the alignment precision is required strictly. On the other hand, not only the shape and alignment of the channel protection layer 6 but also the overlapping of the source/drain and the gate electrode 2 is essential for ensuring reliability. In Fig. 3, the length of an overlapped region between the source/drain and the gate electrode 2 is AL. The region corresponding to AL is indispensable for ensuring stable contact between the contact layer 7 and the active layer 5. When a voltage is applied to the gate electrode 2, a carrier-accumulation layer is formed within the semiconductor active layer 5 and the TFT is turned on. Since the accumulation layer is formed in a region over which an electric field of the gate electrode 2 extends, the substantial junction between the active layer 5 and the contact layer 7 depends on the area of the region ΔL. Thus, in the case of patterning, an erroneous alignment of the region AL greatly affects the characteristics of the TFT. In other words, if the region ΔL is erroneously aligned, variation may occur in an ON-current of the TFT or carrier mobility, and an off-set TFT, with which adequate ON-current and carrier mobility cannot be obtained, may be manufactured. When the TFT is applied to a liquid crystal device, such drawbacks as non-uniform display, flickering, or luminance points may occur. In the prior art, a photomask is manually aligned in an exposure apparatus, or mechanical auto-alignment is employed, as in a stepper exposure apparatus. When the photomask is manually aligned, as in the former case, the patterning precision varies depending on who operates the exposure apparatus. In the latter case, the alignment precision depends on mechanical operations, and the patterning precision is limited by the mechanical precision of the exposure apparatus. Under the situation, when a liquid crystal display device using a TFT is manufactured, it is very difficult to carry out patterning alignment over the entire area. In particular, in the prior art, it is difficult to manufacture large liquid crystal display devices with high reproducibility. As has been stated above, in the conventional method of fabricating a thin-film semiconductor device, a number of photomasks are required, and it is very difficult to precisely align the patterns of the photomasks with high reproducibility. In particular, in the TFT, the erroneous alignment of the channel protection layers greatly affects the TFT characteristics. The object of the present invention is to provide a method of manufacturing a thin-film semiconductor device, wherein the number of photomasks employed can be reduced and a channel protection layer of a TFT or the like can be precisely aligned with a gate electrode. We acknowledge that EP-A-338 766 discloses the fabrication of a thin film transistor on a transparent insulative substrate by forming an opaque metal gate electrode on the substrate, followed by an insulative film, then an active layer, then a channel protection layer and then a positive first resist; photolithographically exposing the first resist from the reverse face of the substrate using the gate electrode as a mask and then patterning the active layer in the same way. The invention provides a method as defined in Claim 1. This invention can be more fully understood from the following detailed description of preferred embodiments, by way of example only, when taken in conjunction with the accompanying drawings, in which: Figs. 1A to 1F are cross-sectional views for illustrating a method of manufacturing a TFT according to a first embodiment of the present invention; Fig. 2 is a cross-section view showing an element structure, for explaining a method according to a second embodiment; and Fig. 3 is a cross-sectional view showing the element structure of a conventional TFT. Embodiments of the present invention will now be described in detail. Figs. 1A to 1F are cross-sectional views for illustrating a method of manufacturing a TFT according to a first embodiment of the present invention. As is illustrated in Fig. 1A, for example, Mo-Ta is deposited on a transparent insulative substrate 11 of, e. g. glass, by means of sputtering, thereby forming an opaque metal thin film on the substrate 11. The metal film is patterned by means of conventional lithography, thus forming a gate electrode 12. Subsequently, a lamination of, a silicon oxide film 13 and a silicon nitride film 14 is formed on the substrate 11 and the gate electrode 12 by means of plasma CVD. For example, an amorphous silicon film is deposited as an active layer 15 by means of plasma CVD. Subsequently, a silicon nitride film is deposited as a channel protection layer 16. Thereafter, a first photoresist 21 of a positive type is coated on the silicon nitride film deposited as the channel protection layer 16, and the reverse side of the substrate 11 is exposed. In the step of the reverse-side exposure, the amount of exposure light is made sufficiently greater than that necessary for patterning (i.e. the amount of exposure light necessary for forming a resist pattern which is the same as the pattern of the gate electrode 12). In the exposure step, the gate electrode 12 serves as a mask, and the resist 21 is selectively exposed. The amount of exposure light is excessive, and therefore the width of the developed resist pattern is less than that of the gate electrode 12 used as the mask, as shown in Fig. 1B. Using the resist 21, the silicon nitride film serving as channel protection layer 16 is selectively etched, so as to leave a selected portion of the channel protection layer 16 above the gate electrode 12. After the resist 21 is removed, a second photoresist 22 of a positive type is coated once again, as shown in Fig. 1C, and the reverse side of the substrate 11 is exposed once again. In this case, the amount of exposure light is less than that of exposure light used for forming the channel protection layer 16. The resist 22 is developed after exposure, thereby forming a resist pattern, as shown in Fig. 1D. The resist pattern has a greater width than the channel protection layer 16. Subsequently, using the resist 22 as a mask, the semiconductor active layer 15 and silicon nitride film 14 are selectively etched. Thus, the semiconductor active layer 15 having a greater width than the channel protection layer 16 can be formed. In other words, the semiconductor active layer 15 and the channel protection layer 16 can be formed in a self-alignment manner in relation to the gate electrode 12. In addition, the length of the channel protection layer 16 in the channel direction can be made less than that of the semiconductor active layer 15. After this step, the resist 22 is removed. After the channel protection layer 16 and the semiconductor active layer 15 are formed in the above manner, a contact layer 17 serving as a phosphor-doped amorphous silicon (n + a-Si) film is deposited, as shown in Fig. 1E. Then, in order to prevent the formation of a parasitic TFT on the gate pattern, the amorphous silicon is patterned in an island shape with use of a photomask. In this case, unnecessary portions of the channel protection layer 16 are simultaneously etched. The etching in this case is carried out, for example, by a chemical dry etching (CDE) using a Freon gas. In this process, the precision of alignment between the photomask and other patterns may not be so strict, since the active layer region and the contact region with the active layer, which determine the TFT characteristics, have already been formed. Subsequently, as in the conventional method, a source/drain electrode 18 of a lamination layer of chromium and aluminum is formed and a contact hole for attaining a contact with the gate electrode 12 is formed. Thus, the fabrication of the TFT is completed. In this embodiment, reverse-side exposure is performed two times with different amounts of exposure light. Thus, the patterning of the channel protection layer 16 and the semiconductor active layer 15, which is conventionally very difficult, can be carried out in a self-alignment manner in relation to the gate electrode 12. Thus, the manufacturing process is simplified, with high reproducibility and high productivity. Since the width of the channel protection layer 16 is less than that of the semiconductor active layer 15, the junction between the semiconductor active layer 15 and the contact layer 17 is stabilized, and a highly reliable TFT can be fabricated. Regarding the above embodiment, it should be noted that since the channel protection layer 16 can be formed within the gate electrode 12 in a self-alignment manner, a length ΔL of an overlapped portion of the source/drain region and the gate electrode 12 can be set with high precision, and the length ΔL on one side can easily be made equal to the length ΔL on the other side. The value ΔL affects the characteristic of the TFT considerably. The value ΔL determines the parasitic capacitance between the gate and source formed in the TFT and the stability of contact between layers 15 and 17. If the value ΔL is increased, the stability of contact between layers 15 and 17 is enhanced but the parasitic capacitance is increased. On the other hand, if the value ΔL is decreased, the parasitic capacitance is decreased but the stability of contact between layers 15 and 17 is degraded. Under the circumstances, it is necessary to find a point of compromise between the parasitic capacitance and the contact. In addition, it is necessary to overcome problems in the process, such as a decrease in adhesion of a resist and in thickness of the resist due to excessive reverse-side exposure. Taking these into account, it is desirable that the value ΔL in the TFT be: 0.3 µm ≦ ΔL ≦ 3.0 µm According to the above embodiment, this requirement was easily met by determining the amount of exposure light (over exposure) on the resist 21, without a need for alignment. Fig. 2 is a view for describing a method according to a second embodiment of the present invention. In the second embodiment, the TFT according to the first embodiment is applied to an active matrix type liquid crystal display device. In the process of manufacturing the TFT according to the first embodiment, after the amorphous silicon is patterned in an island shape, a transparent electrode 25, e.g. ITO (Indium Tin Oxide) is deposited on the silicon oxide film 13. The ITO is patterned in the shape of a display electrode, and thereafter a source/drain electrode 18 is formed. A liquid crystal material 28 is interposed between the TFT array substrate, thus manufactured, and a glass substrate 27 provided with a transparent electrode 26, thereby fabricating a liquid crystal display device. Where a large liquid crystal display device is fabricated, erroneous patterning with use of a photomask results in a defective display screen. By virtue of the method of this embodiment, the number of photomasks employed can be reduced, and patterns, which have not easily been aligned in the prior art, can be formed easily. In addition, according to this embodiment, products can be manufactured with high reproducibility, without depending on the mechanical precision of a stepper, etc. Consequently, the productivity can be enhanced. As has been described above, according to the present invention, when the thin film semiconductor device is manufactured, the gate electrode on the transparent insulating substrate is utilized, and the reverse side of the substrate is exposed to pattern the channel protection layer and the semiconductor active layer. Thus, the channel protection layer and the semiconductor active layer can be formed without positioning using photomasks. Therefore, the patterning can be performed precisely with high reproducibility. In other words, the main part of the thin film semiconductor device can be formed in a self-alignment manner in relation to the gate electrode. In addition, the width of the channel protection layer is made less than the channel width of the semiconductor active layer, thereby attaining reliable, high TFT characteristics. In other words, since the channel protection layer and semiconductor active layer are patterned with the gate electrode used as a mask, the number of photomasks employed can be reduced, and the channel protection layer and the semiconductor active layer can be precisely aligned. Thus, the reliability and the characteristics of the thin film semiconductor device can be enhanced.

Claims: A method of manufacturing a thin-film semiconductor device on a first major surface of a transparent insulative substrate (11) which also has a second major surface opposite to said first major surface, the method comprising the steps of: depositing an opaque metal film on the first major surface of the substrate (11) and patterning said opaque metal film so as to form a gate electrode (12); forming successively an insulating film (13,14), a semiconductor active layer (15) and a channel protection layer (16) on the first major surface of said substrate (11) and said gate electrode (12); patterning the channel protection layer (16) by means of photolithography with a first resist (21) exposed by means of reverse side overexposure using the gate electrode (12) as a mask; and patterning the semiconductor active layer (15) by means of photolithography with a second resist (22) exposed by means of reverse side exposure, with an amount of exposure light being less than that used during the step of patterning the channel protection layer (16) with the gate electrode (12) used as a mask, thereby making the width in the channel direction of the semiconductor active layer (15) greater than that of the channel protection layer (16); characterized in that said insulation film comprises a lamination of two films, of which one is a silicon oxide film (13) and the other is a silicon nitride film (14), formed on the major surface of said substrate (11) and said gate electrode (12). A method according to claim 1, in which a distance ΔL between an end portion of the patterned semiconductor active layer (15) and an end portion of the patterned channel protection layer (16) is set to 0.3 µm < ΔL < 3.0 µm. A method according to claim 1, further comprising, in the step of patterning the channel protection layer, the steps of: coating a positive-type first resist (21) on the channel protection layer (16); radiating light on the second major surface of the substrate (11) and exposing the first resist (21) with the gate electrode (12) used as a mask, thereby leaving a patterned portion of the first resist (21) which is smaller than the gate electrode (12); patterning the channel protection layer (16) with the first resist (21) used as a mask; and, in the step of patterning the semiconductor active layer (15), the steps of: removing the first resist (21) and coating a positive-type second resist (22) on the semiconductor active layer (15) and the patterned channel protection layer (16); radiating light on the second major surface of the substrate (11) and exposing the second resist (22) with the gate electrode (12) used as a mask, thereby leaving a patterned portion of the second resist (22), which is greater than the patterned portion of the first resist (21); patterning the semiconductor active layer (15) with the second resist (22) used as a mask; and further comprising the step of: removing the second resist (22) and forming a source/drain electrode (17) on the patterned semiconductor active layer (15). A method according to claim 3, in which a distance ΔL between an end portion of the patterned portion of the first resist (21) and an end portion of the patterned portion of the second resist (22) is set to 0.3 µm ≤ ΔL ≤ 3.0 µm. A method according to claim 3 or 4, in which said first resist (21) is exposed by means of over-exposure, with the amount of exposure light greater than that necessary for forming a resist pattern equal in size to the gate electrode pattern.

Inventors: UCHIKOGA SHUICHI C O INTELLECT, UCHIKOGA, SHUICHI C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: H01L21
IPC codes: H01L21, G02F1, H01L29