Nonvolatile semiconductor memory circuit

Abstract: A memory cell transistor includes a semiconductor substrate (11), a N-type source region (13), a N-type drain region (14), a control gate (19) and a P⁺-type emitter region (20), which is formed in the surface region of the drain region (14). An insulating film (21) overlies the source region (13), the drain region (14), the emitter region (20), and the control gate (19). A contact hole (22) is formed in the insulating film (21) so that the surface of the emitter region (20) is exposed. An emitter electrode (23) is formed in and around the contact hole (22). A PNP vertical bipolar transistor is constituted by the semiconductor substrate (11) serving as a collector region, a P⁺-type buried layer (12) serving as a collector contact, and the drain region (14) serving as a base region.

Description: This invention relates generally to a nonvolatile semiconductor integrated device such as a nonvolatile semiconductor memory, and more particularly to a nonvolatile memory cell from which data can be read out at a high speed and a nonvolatile semiconductor memory device having the same. Nonvolatile semiconductor memory devices have been widely used, which comprise a multilayer-gate type nonvolatile memory cell transistor having a floating gate and a control gate. The nonvolatile semiconductor memory devices include an EEPROM (electrically erasable and programmable read only memory) and an EPROM (erasable and programmable read only memory). The conventional multilayer-gate type nonvolatile memory cell transistor having a floating gate and a control gate has a threshold voltage higher than a normal MOS transistor. Hence, the current driving capacity thereof is low and data cannot be easily read out at high speed. US-A-3 893 085 discloses a nonvolatile semiconductor memory device comprising interconnected FAMOS and bipolar transistors. The FAMOS transistor comprises an N-type semiconductor body having a major surface and having first and second spaced P-type regions; a first gate insulating layer on the major surface of said semiconductor body and extending between and slightly overlapping, the first and second spaced P-type regions; a floating gate on the gate insulating film; a second gate insulating layer on the first gate; and an erase gate on the second gate insulating layer. The bipolar transistor including an N-type emitter region formed in the second P-type region, which comprises a base of said bipolar transistor, the N-type semiconductor body comprising a collector of the bipolar transistor and there being an N-type collector contact region, part of which is buried within the semiconductor body and which is spaced from the major surface thereof. EP-A-0 055 182 discloses an electrically erasable high speed, non-volatile, memory cell comprising a floating gate pMOS transistor for data storage and a merged npn bipolar transistor for selective access to stored data. Reference is also made to Patent Abstracts of Japan, vol. 8, no. 181 (JP-A-59 074 666), in which one diffused region of rewritable semiconductor nonvolatile memory cells and the base region of a bipolar transistor use the same diffused region in common. A plurality of bit lines connects the emitters of the memory. It is an object of the present invention to provide a nonvolatile semiconductor memory circuit comprising a nonvolatile memory cell from which data can be read out at a high speed. According to the present invention, there is provided a nonvolatile semiconductor memory device comprising: (I) a MOS transistor, comprising: (a) a semiconductor body of a first conductivity type having a major surface and having first and second spaced regions containing an impurity of a second conductivity type opposite to said first conductivity type and having a surface; (b) a first insulating layer on said major surface of said semiconductor body and extending at least between said first and second spaced regions; (c) a floating gate on said first insulating layer; (d) a second insulating layer on said floating gate; and (e) a control gate on said second insulating layer; and (II) a bipolar transistor, comprising: (a) an emitter region of the first conductivity type, said emitter region being formed in a contact hole etched in an insulating film overlying said second spaced region, and on said surface of said second spaced region and in contact therewith, said second spaced region comprising a base of said bipolar transistor, and said semiconductor body comprising a collector of said bipolar transistor; and (b) a collector contact region comprising a buried region of the first conductivity type within said semiconductor body and spaced from said major surface thereof. This invention can be more fully understood from the following detailed description given by way of example and taken in conjunction with the accompanying drawings, in which: Fig. 1 is a cross-sectional view showin the element structure of a nonvolatile memory cell useful for understanding the present invention; Fig. 2 is a diagram showing an equivalent circuit of the memory cell shown in Fig. 1; Fig. 3 is a circuit diagram showing a nonvolatile semiconductor memory device having the memory cell shown in Fig. 1; Fig. 4 is a diagram showing voltages applied to portions of the memory device shown in Fig. 3; Fig. 5 is a cross-sectional view showing the element structure of a nonvolatile memory cell according to a first embodiment of the present invention, again having the equivalent circuit shown in Fig. 2; Fig. 6 is a cross-sectional view shoring the element structure of a nonvolatile memory cell according to a second embodiment of the present invention, again having the equivalent circuit shown in Fig. 2; Fig. 7 is a diagram showing voltages applied to the source, the emitter, the control gate, and the collector of a modification of the nonvolatile memory cell according to Fig. 1, 5 or 6; Fig. 8 is a diagram showing an alternative combination of voltages applied to the source, the emitter, the control gate, and the collector of the modified nonvolatile memory cell; Fig. 9 is a cross-sectional view showing the element structure of a nonvolatile memory cell useful for understanding the present invention; Fig. 10 is a circuit diagram showing a nonvolatile semiconductor memory circuit according to a third embodiment of the present invention; and Fig. 11 is a diagram showing voltages applied to the bit lines, the word lines and the source of the nonvolatile semiconductor memory device shown in Fig. 10. Embodiments of the present invention will now be described with reference to the accompanying drawings. Fig. 1 is a cross-sectional view of a nonvolatile memory cell not being an embodiment of the present invention and described for the purpose of explanation only. Fig. 1 shows a P-type semiconductor substrate 11 having a resistivity of 5Ω on a plane [100]. A P + -type buried layer 12 is formed in the substrate 11. The surface region of the substrate 11 includes an N + -type source region 13 of 0.2 µm in depth, doped with an N-type impurity of a concentration of 1 × 10 20 /cm 3 , and an N - -type drain region 14 of 0.5 µm in depth, doped with an N-type impurity of a concentration of 1 × 10 17 /cm 3 . The source and drain regions 13 and 14 are separated from each other by a channel region 15 interposed therebetween. The channel region 15 is 0.6 µm in length and 0.9 µm in width. A floating gate 17 made of polysilicon and having a thickness of 100nm is formed on the channel region 15 with a first gate oxide film 16 having a thickness of 10nm provided therebetween. A control gate 19 made of polysilicon having a thickness of 400nm is formed on the floating gate 17 with a second gate oxide film 18 having a thickness of 20nm provided therebetween. The source region 13, the drain region 14, the first gate oxide film 16, the floating gate 17, the second gate oxide film 18, and the control gate 19 constitute a multilayer-gate type nonvolatile memory cell transistor. The substrate 11 serves as the substrate of the memory cell transistor. The surface region of the drain region 14 includes a P + -type emitter region 20 of 0.3 µm in depth, doped with a P-type impurity of a concentration of 1 × 10 20 /cm 3 . An insulating film 21 overlies the source region 13, the drain region 14, the emitter region 20, and the control gate 19. A contact hole 22 is formed in the insulating film 21, so that a portion of the surface of the emitter region 20 is exposed. An emitter electrode made of aluminum or the like 23 is formed in and around the contact hole 22. The semiconductor substrate 11 functioning as a collector region, the P + buried layer 12 as a collector contact, and the drain region 14 as a base region constitute a PNP vertical bipolar transistor including the emitter region 20. Fig. 2 shows an equivalent circuit of the nonvolatile memory device shown in Fig. 1. In Fig. 2, each element is accompanied by the same numeral as that of the corresponding element in Fig. 1. In the following descriptions, the control gate, the source, and the drain of the memory cell transistor may be represented by CG, S, and D, respectively, and the emitter and the collector of the bipolar transistor by E and C, respectively. Fig. 3 is a circuit diagram showing a nonvolatile semiconductor memory device comprising a nonvolatile memory cell shown in Fig. 1. In Fig. 3, a voltage supply circuit 30 generates various voltages for driving the above-mentioned memory cell, and is connected to the control gate CG, the source S, the emitter E, and the collector C of the memory cell. A method of driving the cell by means of the voltage supply circuit 30 will be described below with reference to Fig. 4. First, a data reading operation will be described. When data is read out from the nonvolatile memory cell transistor, the voltage supply circuit 30 outputs various voltages. The output voltages of 0V, 2V, 5V, and 0V are respectively applied to the source S, the emitter E, the control gate CG, and the collector C. When the voltage of 5V is applied to the control gate CG, the memory cell transistor which is erased is turned on, with the result that a drain current flows, thereby turning on the bipolar transistor. At this time, the voltage at the drain D decreases from 2V to 1.4V, i.e., decreases by the value of the base-emitter voltage of the bipolar transistor, and a channel current of about 100 µA flows through the bipolar transistor as a base current thereof. As a result, the base current is amplified to an emitter current, which is 10 times as large as the base current. The current amplified to about 1mA contributes to the discharge of a bit line (not shown) connected to the emitter E of the bipolar transistor. Thus, the current driving capacity for a bit line is considerably increased as compared to a conventional nonvolatile memory cell transistor of a multilayer-gate type having a floating gate and a control gate. Accordingly, data can be read out at a higher speed. In addition, since the emitter is formed within the drain of the memory cell transistor, the increase in size of the cell is suppressed. A data writing operation is performed by applying a high voltage to a portion between the control gate 19 and at least one of the semiconductor substrate 11, the source region 13 and the drain region 14, thereby tunnel-injecting a charge to the floating gate 17. The voltage supply circuit 30 outputs various voltages. For example, as is shown in Fig. 4, a voltage of 0V is applied to the source S, the emitter E, and the collector C, and a voltage of 20V to the control gate CG. As a result, electrons are injected from the source S to the floating gate 17, tunneling through the first gate oxide film 16. Even if that portion of the first gate oxide film 16 which does not in contact with the source region 13 is thicker than 10nm, electrons can be injected from the source 13 to the floating gate 17, tunneling through the first gate oxide film 16. When data in the memory cell transistor in the non-volatile semiconductor memory device of Fig. 3 is erased, the voltage supply circuit 30 applies a voltage of 0V to the source S, the emitter E, and the collector C, and a voltage of -20V to the control gate CG. As a result, electrons flows in a direction reverse to that in the above-mentioned writing operation, thereby discharging the floating gate 17. Thus, the data in the memory cell transistor is erased. Fig. 5 shows a nonvolatile memory cell according to a first embodiment of the present invention. In the memory cell shown in Fig. 5, a P + -type semiconductor region 24 serving as an emitter is formed in contact with the drain region 14, in place of the P + type emitter region 20 in the bipolar transistor shown in Fig. 1. A polycrystalline silicon layer 25 containing a P + type impurity is deposited on the semiconductor region 24 in the contact hole 22. An emitter electrode 23 made of aluminum is formed on the polycrystalline silicon layer 25. In the memory cell of this embodiment, the P + type semiconductor region 24 formed in the contact hole 22 is used as an emitter of the bipolar transistor. Fig. 6 shows a nonvolatile memory cell according to a second embodiment of the present invention. In the memory cell shown in Fig. 6, a polycrystalline silicon layer 25 containing a P + type impurity and functioning as an emitter is deposited in the contact hole 22, in place of the P + type emitter region 20 in Fig. 1. In other words, this embodiment differs from the first embodiment in that the contact hole 22 is filled with the polycrystalline silicon 25 without forming the semiconductor region 24. Accordingly, the P + type polycrystalline silicon layer 25 containing a P + type impurity serves as an emitter of the bipolar transistor. A modified nonvolatile memory cell will now be described. The equivalent circuit of the modified nonvolatile memory cell is the same as that shown in Fig. 2, and the cross-section thereof is the same as that shown in Fig. 1, 5 or 6. The modified memory cell differs from Figs. 1, 5 or 6 only in that the first gate oxide film 16 is twice as thick, i.e. 20 nm, and hence the capacitance between the semiconductor substrate 11 and the floating gate 17 is half of that in the memory cells according to Figs. 1, 5 and 6. Accordingly, the capacitance between the floating gate 17 and the control gate 19 is half of that in Figs. 1, 5 and 6. The other portions are the same as those in these Figures. In a reading operation, the modified nonvolatile memory cell is driven by the voltage supply circuit in the same manner as in the first example, as is shown in Fig. 7. In a writing operation, a first voltage is applied to the control gate CG, a second voltage of the same polarity as that of the first voltage is applied to the source S, and a third voltage of the opposite polarity is applied to the emitter E. The third voltage is approximate to the junction breakdown voltage in the reverse direction between the emitter and the drain. The first to third voltages cause a channel current to flow, thereby generating channel hot carriers, which are injected into the floating gate 17. For example, voltages of 12V, 6V, -7V, and 0V are respectively applied to the control gate CG, the source S, the emitter E, and the collector C, as is shown in Fig. 7. In this case, since the impurity concentration of the drain D is 1 × 10 17 cm 3 as described above, the junction breakdown voltage in the reverse direction between the emitter and the drain is approximately 7V. The drain D is fixed at the voltage of 0V, and the breakdown current flows from the source S through the drain D to the emitter E as a channel current. At this time, hot electrons generated near the source are injected into the floating gate 17, thus executing a writing operation. A data erasing operation in the modified memory cell is performed by applying ultraviolet lights. Another modified nonvolatile memory cell will now be described. Again, the equivalent circuit of the nonvolatile memory cell is the same as that of the first example shown in Fig. 2, and the cross-section thereof is the same as that shown in Fig. 1, 5 or 6. The further modified memory cell differs from the unmodified versions only in that the impurity concentration of the entire drain region 14 is set higher than that in the first example, e.g. 3 x 10 17 cm 3 . Accordingly, the breakdown voltage in the reverse direction between the emitter and the drain is 6V or lower, for example, 3V. The other portions of the further modified memory cell are the same as those in Figs. 1, 5 and 6. In a reading operation, the further nonvolatile memory cell is driven by the voltage supply circuit in the same manner as in Figs. 1, 5 and 6, as is shown in Fig. 8. In a writing operation, a fourth voltage is applied to the control gate CG, a fifth voltage of the same polarity as that of the fourth voltage is applied to the source S, and the emitter E is grounded. These voltages cause a channel current to flow, thereby generating channel hot carriers, which are injected into the floating gate 17. For example, voltages of 15V, 9V, 0V, and 0V are respectively applied to the control gate CG, the source S, the emitter E, and the collector C, as is shown in Fig. 8. In this case, the emitter E is fixed at the voltage of 3V, i.e., the breakdown voltage in the reverse direction between the emitter and the drain, and the junction breakdown current flows from the source S through the drain D to the emitter E as a channel current. At this time, hot electrons generated near the source are injected into the floating gate 17, thus executing a writing operation. Fig. 9 shows a second example for explaining the present invention. In the second example, the impurity concentration of the entire drain region is set higher than that of the first example, thereby reducing the breakdown voltage in the reverse direction between the emitter and the drain. However, in the second example, the drain region 14 include an N + -type semiconductor region 26 which has an impurity concentration higher than that of the other portion thereof and abuts on the emitter region 20. In this example also, the breakdown voltage in the reverse direction between the emitter and the drain is lower than that of the first example. According to the first and second embodiments, the nonvolatile memory cell has approximately the same area as that of the conventional nonvolatile memory cell transistor, since the emitter is formed within the contact hole 22 in a self-aligning manner. Next, a nonvolatile semiconductor memory circuit according to a third embodiment of the present invention will be described. This embodiment differs from the first example shown in Fig. 1 in that the nonvolatile memory cells are arranged in a matrix. Fig. 10 is a circuit diagram showing an example of the third embodiment, in which four nonvolatile memory cells MC1 to MC4 are arranged in a matrix. The control gates CG of the memory cells MC1 and MC2 in one row are connected to a word line WL1. The control gates CG of the remaining memory cells MC3 and MC4 in the other row are connected to a word line WL2. The emitters E of the memory cells MC1 and MC3 in one column are connected to a bit line BL1, and those of the memory cells MC2 and MC4 in the other column to the other bit line BL2. The sources S of all of the memory cells MC1 to MC4 are connected to a source line SL, and the collectors C thereof are grounded. In the above-described memory circuit, voltages used when data is written into or read from the memory cells are the same as those shown in Fig. 7. More specifically, as is shown in Fig. 11, in a data reading operation, voltages of 5V and 0V are respectively applied to the word lines WL1 and WL2, so that the voltage of 5V is applied to the control gate of a selected memory cell, and the voltage of 0V to that of a non-selected memory cell. A voltage of 2V is selectively applied to the bit line BL1 or BL2, so that it is applied to the emitter E of the selected memory cell. A voltage of 0V is applied to the source line SL. In a data writing operation, voltages of 12V and 0V are respectively applied to the word lines WL1 and WL2, so that the voltage of 12V is applied to the control gate CG of a selected memory cell, and the voltage of 0V to that of a non-selected memory cell. A voltage of -7V is selectively applied to the bit line BL1 or BL2, so that it is applied to the emitter E of the selected memory cell. A voltage of 6V is applied to the source line SL. The above-description of the third embodiment is related to the nonvolatile semiconductor memory circuit having memory cells according to the modified memory cells described with reference to Figs. 5 and 6. However, the memory cells of the embodiments shown in Figs. 5 and 6 can be used in the third embodiment. As has been described above, according to the disclosed embodiments, the cell current flowing in a reading operation can be increased by several times that of the conventional nonvolatile memory cell transistor having the same area as that of this invention. Hence, the semiconductor integrated circuit having a nonvolatile memory cell can perform a reading operation at a higher speed. Accordingly, a Bi-(bipolar) CMOS (complementary insulating gate type) high speed EPROM, EEPROM can be provided.

Claims: A nonvolatile semiconductor memory device comprising: (I) a MOS transistor, comprising: (a) a semiconductor body (11) of a first conductivity type having a major surface and having first and second spaced regions (13, 14) containing an impurity of a second conductivity type opposite to said first conductivity type and having a surface; (b) a first insulating layer (16) on said major surface of said semiconductor body and extending at least between said first and second spaced regions; (c) a floating gate (17) on said first insulating layer; (d) a second insulating layer (18) on saidfloating gate; and (e) a control gate (19) on said second insulating layer; and (II) a bipolar transistor, comprising: (a) an emitter region (24,25;25) of the first conductivity type, said emitter region being formed in a contact hole (22) etched in an insulating film (21) overlying said second spaced region (14), and on said surface of said second spaced region (14) and in contact therewith, said second spaced region comprising a base of said bipolar transistor, and said semiconductor body comprising a collector of said bipolar transistor; and (b) a collector contact region (12) comprising a buried region of the first conductivity type within said semiconductor body and spaced from said major surface thereof. A nonvolatile semiconductor memory device according to claim 1, characterized by further comprising a voltage supply circuit (30) for applying a high voltage between said control gate and at least one of said semiconductor body, said first spaced region, and said second spaced region, thereby tunnel-injecting a charge from said semiconductor body to said floating gate. A nonvolatile semiconductor memory device according to claim 1, characterized by further comprising a voltage supply circuit (30) for applying a first voltage having a first polarity to said control gate, a second voltage having the first polarity to said first spaced region, and a third voltage to said emitter region, the third voltage having a second polarity and a value approximately equal to a reverse junction breakdown voltage between said emitter region and said second spaced region, to thereby generate a channel current between said first and second spaced regions and inject hot carriers generated by the channel current into said floating gate for data writing. A nonvolatile semiconductor memory device according to claim 1, characterized in that the impurity concentration of said second spaced region is set so that the junction breakdown voltage in the reverse direction between said emitter region and said second spaced region is substantially 6 V or lower. A nonvolatile semiconductor memory device according to claim 4, characterized by further comprising a voltage supply circuit (30) for applying a fourth voltage to said control gate, a fifth voltage of the same polarity as that of the fourth voltage to said first spaced region, and a ground voltage to said emitter region, thereby causing a channel current to flow between said first and second spaced regions to generate channel hot carriers, which is injected into said floating gate, thus performing a data writing operation. A nonvolatile semiconductor memory device according to claim 1, characterized in that said emitter region is constituted by a semiconductor region (24) on which a polycristalline silicon layer (25) containing an impurity of the first conductivity type is deposited. A nonvolatile semiconductor memory device according to claim 1, characterized in that said emitter region is constituted by a polycrystalline silicon layer (25) containing an impurity of the first conductive type.

Inventors: MATSUKAWA NAOHIRO, MIYAMOTO JUNICHI, MATSUKAWA, NAOHIRO, MIYAMOTO, JUNICHI, Matsukawa, Naohiro, c/o Intellectual Property Div., MIYAMOTO, JUNICHI, C/O INTELLECTUAL PROPERTY DIV.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: H01L27
IPC codes: H01L29, H01L27, H01L21