Method for managing a cache memory system

Abstract: In a method for reading a multiple byte data element stored in both a cache (16) and a main memory (12), selected bytes of the data element are invalidated in the cache (16) and valid bytes from the cache (16) are combined with remaining bytes from the main memory (12) in response to a read request.

Description: This invention relates to computer memory systems. The performance of a computer system can be enhanced by the use of a memory hierarchy. For example, a three tiered memory can be constructed from low, medium, and high speed memories. A low speed memory may be a magnetic disk for low cost, bulk storage of data. A medium speed memory may be constructed from DRAMs for use as the computer system's main memory. A high speed memory may employ SRAMs for use as a processor cache memory. The theory behind memory hierarchy is to group code (instructions) and other data to be executed by the system processor in the highest speed memory. Since high speed memory is typically the most expensive memory available, economics dictate that it be relatively small. Main memory consisting of DRAMs is denser and less expensive than a cache memory with SRAMs, and can therefore be significantly larger than the cache memory. During operation, instructions and other data are transferred from system memory to the cache memory in order to have quick access to the variables of the currently executing program. As additional data, not in the cache, is required, such data is transferred from the main memory by replacing selected data in the cache. Various replacement algorithms are utilized to determine which data is replaced. An efficiently operating cache architecture exhibits a high ratio of "hits" to accesses. A "hit" occurs when data requested is in the cache. A number of factors influence the hit ratio. The dominant factor is the locality of reference of the code being executed. In other words, if the code is located in proximate physical locations in memory, the hit ratio will be higher than if the code is widely distributed throughout memory. Another factor influencing the hit ratio of a cache is the number of devices having access to the memory. If only a single bus master, such as the system processor, has access to the memory, the data stored in the cache can be controlled to achieve a reasonably high hit ratio. However, when more than a single bus master has access to the memory through the same cache, the cache can bounce back and forth between requests from the bus masters, greatly reducing the hit ratio. In other words, the cache is non-discriminatory, with the demands of the system processor and other bus masters affecting the cache equally. One operation can significantly impact the data make-up of the cache. For example, data cached in response to memory accesses from a non-host CPU bus master will overwrite data needed by the host processor. Another factor affecting the hit ratio relates to the fact that both code and non-code data are cached. Blocks of data in the system memory are mapped into different physical locations in the cache. If each block of data in system memory may be mapped to only a single location, the cache is known as a direct mapped cache. Set associative mapping involves each block of data being mapped to more than a single location. For example, if each block of data may be mapped to either of two locations, the cache is known as two-way set associative. Irrespective of the number of locations available for a system memory block, when both code and non-code data are being cached, there will be overlap in their respective mappings. Thus, when both code and non-code data are cached, there can be significant thrashing which takes place as data is replaced in response to memory accesses. An issue related to cache hits is whether or not a data element in a cache is valid and/or dirty. A data element in the cache is valid as long as no corresponding element in the system memory is more current. A data element in a cache is dirty if it is more current than a corresponding element in the system memory. A data element becomes dirty when a bus master writes the element to a cache and not to system memory. On a cache hit, if all the bytes of a data element are valid, the cache will provide the requested data element. If any of the bytes are invalid, the system memory will respond to the memory read for the data element. However, if one but not all of the data bytes are valid and dirty, any such bytes are first written from the cache to the system memory before the data element can be read from the system memory. Such a prior art is known from EP-A-0 379 769. This write back feature increases the response time of the memory system which adversely impacts system performance. From US-A-4157586 there is known a method for performing a partial store operation. In this operation, a word of data to be stored is placed in a data register. In accordance with control bits stored in a separate mask register, selected bytes of the word in the data register are merged in a merge register with selected bytes from a cache, the output of the merge register being fed to a storage control unit for a main memory. It is an object of the present invention to provide a method of improving the response time of a computer memory system. Therefore, according to the present invention, there is provided a method for reading a multiple byte data element stored in both a cache and a system memory in which selected bytes of said data element in said cache are invalidated, characterized by the steps of storing in said cache a valid/invalid flag for each byte of said data element stored therein representing whether the byte is valid or invalid, and responding to a first read request for said data element by combining valid bytes from said cache with remaining bytes from said system memory without prior write-back operation of said valid bytes to said system memory. One embodiment of the present invention will now be described by way of example with reference to the accompanying drawings, in which:- Figure 1 is a block diagram of a high performance computer memory system which embodies the present invention.; and Figure 2 is a more detailed diagram of the computer memory system shown in Figure 1. Figure 1 shows a block diagram of a computer memory system 10. System 10 includes a system memory 12 which in a preferred embodiment consists of dynamic random access memory (DRAM) chips. The data stored in memory 12 can be generally divided into code data (instructions) and non-code data. As used herein, the term "data" refers to information and includes both code data (instructions) and non-code data. Memory 12 is connected to other parts of a computer system (not shown) by a bus 14. Memory system 10 is designed for use with two or more bus masters. More particularly, it is designed for use with a host processor such as an Intel processor 386, 386sx or 486 in combination with other bus masters or devices which will compete with the host processor for access to memory system 10. Access to DRAM 12 is controlled by DRAM controller 22 which is located within bus means 14. Memory system 10 also includes an internal cache 16, a pre-fetch cache 18 and a write buffer cache 20, each connected to bus means 14. In a preferred form, internal cache 16 is a 4K byte, fourway set associative cache, pre-fetch cache 18 is a 128 byte, direct-mapped cache, and write buffer cache 20 is a 128 byte, two-way set associative cache. A feature of the caches is that their functionality may be varied depending upon the host processor type (386, 386sx or 486) utilized. However, certain features of the caches do not vary. For example, internal cache 16 holds data which is selected solely on the basis of memory accesses by the host processor. In other words, internal cache 16 is dedicated to the host processor and will not be affected by memory accesses by other bus masters. It will be appreciated that each of the caches is readable by any of the bus masters. Thus, even though cache 16 will not allow data writes therein based on memory accesses by other than the system processor, it will be read by another bus master if requested data happens to reside therein. It will further be appreciated that each of the caches snoops (observes) any data writes not intended for it in order to invalidate its contents upon snoop hits, thereby ensuring coherency. Another immutable feature of the caches is that pre-fetch cache 18 contains solely code data pre-fetched from DRAM 12. Furthermore, it only pre-fetches code based on a memory access by the host processor. In operation, whenever the system processor requests code data not already in the pre-fetch cache, the next sequential 128 bytes of code are pre-fetched into cache 18 as a queue in anticipation of subsequent requests for code. Write buffer cache 20 only buffers data to be written into DRAM 12. It is not merely a write buffer, but is a cache which, as mentioned above, can be read by any bus master. However, it will not cache data from DRAM 12. An important feature of the caches is the separation of the functionality of each of the caches, such that the selective definition of those functions based on the processor type is readily effected. By this insight, the present system is able to achieve or exceed the performance of a system utilizing a single cache many times larger than the cumulative size of the subject caches. With respect to the selective definition of function based on processor type, for a system employing a 486 system processor, write buffer cache 20 buffers data writes by any bus master other than the system processor. For a system employing a 386 or 386sx system processor, internal cache 16 holds only code data and is a read only cache for the system processor, and write buffer cache 20 buffers data writes by any bus master including the system processor. The operational characteristics of the caches are defined through self configuration at power-on time based on information relating to the type of host processor present. DRAM controller 22 supports fast page mode for accesses to DRAM 12. Fast page mode is a well known technique for speeding up accesses to DRAM by activating a row line in a memory page and then strobing sequential column lines to transfer data into or out of DRAM. DRAM 12 is divided into pages which contain either code or non-code data. A register associated with DRAM 12 is located either in DRAM 12 or DRAM controller 22 and holds the page address of a most recently accessed page. In effect, the system provides a bias towards code pages or non-code pages depending upon the type of processor connected to the system. For example, if the system processor is a 486, the address of the most recently accessed code address page is held in the register. In operation, both code and non-code data pages in DRAM 12 can be randomly accessed. If a code page is accessed on one cycle and a non-code page is accessed on the next cycle, the address of the code page is held in a register while the non-code page is accessed. Immediately after the non-code page access, the address in the register is used to reopen the code page. In contrast, if the system processor is a 386 or 386sx, the address of the most recently accessed non-code address page is held in the register. The combination of selective open page bias, fast page mode accesses and multiple caches provides increased system performance. Write buffer cache 20 is a two-way set associative cache. The non-code data region of memory may be divided into three areas known as list, heap and stack. Data blocks in memory are reserved for the list, heap and stack, each of which has its own organization and purpose. For example, a stack is a set of data elements, only one of which can be accessed at a time. The list data is primarily read and generally not written to. In structured programs, a high percentage of writes occur to the stack with the second most data writes occurring to the heap. By proper assignment of the heap and stack data blocks in DRAM and mapping respective blocks to opposing sets in the two-way set associative cache, increased operational efficiency can be realized. Furthermore, an open page bias in the DRAM for non-code data will effectively be an open page bias for list data. In this manner, operational efficiency is further enhanced. Figure 2 shows more detail of computer memory system 10. DRAM 12 and controller 22 are connected to bus 14 through tristate devices 300. Bus 14 has a width of four bytes so that the four bytes of a double word (designated 0, 1, 2 and 3) may be transmitted in parallel. Each byte of a double word transmitted from DRAM 12 passes through a tristate device 300 which may block or pass selected bytes according to the control signals received by each device 300. Each tristate device 300 receives a blocking signal on control line 302 from caches 16 and 20. Caches 16 and 20 are connected to bus 14 through tristate devices 304 and 306, respectively. As with DRAM 12, data elements in caches 16 and 20 are accessible in four parallel bytes (double word). Individual bytes may be blocked or passed in tristate devices 304 and 306 according to control signals received from caches 16 and 20. In one embodiment, the control signal for blocking a data byte from DRAM 12 is active when the corresponding data byte in either cache 16 or 20 is valid and dirty. Each byte of a multiple byte data element in cache 16 and 20 has a bit associated therewith which is set as "valid" when the data element is first written into the cache. Under certain operating conditions it may be necessary to invalidate one or more bytes in an element. For example, if a high speed transfer from a bus master directly to DRAM 12 (fast page mode) is performed, each cache will watch or "snoop" bus 14. If any data elements corresponding to those in a cache are written into DRAM 12 in this manner, the respective bytes in such corresponding data element are set as "invalid". As a further example, it may sometimes be desirable to transfer data elements from one cache to another. Any byte so transferred will be set invalid in the source cache to avoid ambiguity. Each multiple byte data element in cache 16 and 20 also has a bit associated therewith which is designated as its "dirty" bit. A dirty bit is a flag which indicates that the cache written to has information that has not yet been written to memory, i.e., it represents the most up-to-date value of a given data element. The dirty bit is typically set when data is written into the cache from a bus master. "Dirty" data is "cleaned" by writing the data to the system memory. Although the subject invention provides a valid bit at the byte level and a dirty bit at the element level, it is possible to change the granularity. The present invention has several modes of operation. In the first mode, individual data elements are requested to be read by a bus master. Normally, the caches are checked and if the data element resides therein it is returned very quickly to the bus master. If the data element is not in the cache, DRAM controller 22 and DRAM 12 are activated and the data element fetched from DRAM 12 (a somewhat longer procedure than obtaining the element from a cache). If the data element is in one or more of the caches, and if some but not all of its data bytes are valid and dirty, DRAM controller 22 and DRAM 12 are activated and its bytes provided to tristate devices 300. However, for any byte having a corresponding dirty and valid byte in one of the caches, such byte is blocked by a tristate device 300. At the same time, tristate devices 304 and 306 will only pass bytes which are both dirty and valid. In this manner, a complete data element may be read by a bus master. More particularly, when a data element is stored in both a cache and DRAM 12, it is possible that selected bytes of the data element in the cache have been invalidated. A valid/invalid flag is provided for each byte of each data element stored in the cache. The flags for respective bytes are set valid when the data element is first written to the cache. Selected flags are thereafter set invalid for conditions such as stated previously. In most applications, a further necessary condition is that selected bytes have also been written into the cache from other than DRAM 12 and designated as dirty. When a bus master attempts to read the data element, the caches are first checked. If the element is found in a cache, but it contains some invalid bytes, a signal is provided to activate DRAM 12. Only a valid and dirty byte from the cache is combined with bytes from DRAM 12. The valid flag for a dirty byte is used to disconnect the corresponding line from DRAM 12 to bus 14 to block the transfer of the corresponding data byte from DRAM 12. Similarly, the valid flag for a dirty byte (or an inverted form thereof) is used to connect a corresponding byte line from the cache to bus 14. The method also is effective when the subject data element is spread over more than a single cache. In other words, the data element has been provided to a second cache from other than DRAM 12 and has thus been designated as dirty. Furthermore, selected data bytes in the second cache data element have been invalidated. However, it is important that at least one of each of the corresponding bytes in the two caches is invalid to prevent ambiguity. In response to a data read by a bus master, each cache is again checked for the specified data element. If the element is resident in both caches and if any pair of corresponding data bytes in the two caches are both detected as being invalid, a signal is sent to activate DRAM 12. As before, valid and dirty bytes are provided from a cache and the corresponding bytes from DRAM 12 are blocked. In a second mode of operation, the present invention responds to large transfers of data directly from DRAM 12 to a bus master. For example, the subject invention supports a "streaming mode" such as found on the IBM Micro Channel architecture. In this mode, DRAM 12 operates in a fast page mode, and sequentially responds to read requests by transferring data elements from DRAM 12. The caches are checked for each data element but at the same time as DRAM 12 is activated, and not prior to DRAM 12 being activated, as in the first mode described above. Whenever, a dirty and valid byte in one of the caches is detected, the corresponding data byte line from DRAM 12 is blocked and the dirty and valid data byte is merged.

Claims: A method for reading a multiple byte data element stored in both a cache (16) and a system memory (12) in which selected bytes of said data element in said cache are invalidated, characterized by the steps of storing in said cache (16) a valid/invalid flag for each byte of said data element stored therein representing whether the byte is valid or invalid, and responding to a first read request for said data element by combining valid bytes from said cache (16) with remaining bytes from said system memory (12) without prior write-back operation of said valid bytes to said system memory. A method according to claim 1, characterized in that flags for respective bytes of said data element in said cache (16) are set valid when said data element is first written to said cache, and in that said flags are set invalid when a corresponding data element is written into said system memory (12) or another memory (20). A method according to either claim 1 or claim 2, characterized in that, prior to responding to said read request, selected bytes of said data element are written into said cache (16) other than from said system memory (12), such bytes being designated as dirty. A method according to claim 3, characterized in that only a valid and dirty byte from said cache (16) is combined with bytes from said system memory (12). A method according to claim 4, characterized in that, prior to combining bytes, said responding step includes the steps of checking said cache (16) for said element, and generating a signal, when invalid bytes in said cache are detected, to activate said system memory (12). A method according to claim 5, characterized in that flags for valid and dirty bytes are used to block the transfer of corresponding data bytes from said system memory (12). A method according to claim 6, characterized in that said cache (16) and system memory (12) are connected to bus means (14) for the transfer of data elements, in that said bus means (14) has the same number of byte wide lines as the number of bytes in said data element, in that data bytes are blocked by disconnecting corresponding lines from said system memory (12), and in that each dirty and valid byte from said cache (16) is combined with remaining bytes from said system memory (12) by connecting corresponding lines from said cache (16). A method according to claim 3, characterized in that said system memory (12) and cache (16) are connected to bus means (14) for the transfer of data elements, in that a second cache (20) is also connected to said bus means (14), and in that said responding step includes: checking each cache (16,20) for said data element. A method according to claim 8, characterized by the steps of: prior to responding to said first read request, providing said data element to said second cache (20), wherein at least one byte of said data element is written into said second cache (20) from other than said system memory (12) and designated as dirty; invalidating selected data bytes in said second cache data element so that for each byte in said data element at least one of the corresponding bytes in said first or second cache is invalid; and generating a signal, when corresponding data bytes of said cache element are both detected as being invalid, to activate said system memory (12). A method according to claim 3, characterized by the steps of: prior to responding to said first read request, sequentially responding to other read requests by transferring a plurality of data elements from said system memory (12); and activating said system memory (12) while checking said cache (16) for a data element responsive to said first read request, wherein valid bytes from said cache (16) are combined with remaining bytes from said system memory (12) only for bytes of said cache data element which are dirty and valid.

Inventors: ARNOLD FORREST O, ELLIS JACKSON L, KING EDWARD C, MOUSSAVI ROBERT B, VERMEER FULPS V, WEISSER PIRMIN L, ARNOLD, FORREST O., ELLIS, JACKSON L., KING, EDWARD C., MOUSSAVI, ROBERT B., VERMEER, FULPS V., WEISSER, PIRMIN L.
Applicants: NCR INT INC, NCR INTERNATIONAL, INC.
Application year: 1991
Main classification: G06F12
IPC codes: G06F12