ENABLING CODE FOR RADIOTRANSMISSION OF DATA

Abstract: A radiotransmission station (12) transmits digital data at a predetermined rate to a receiving station (18). The receiving station is controlled by a timing circuit (22) which recognises a predetermined enabling code. The digital data is transmitted as bit sequences and each sequence contains a first group of bits (BR) for synchronising the timing circuit and the data transmission rate. This first group of bits is followed by a second group of bits (SC) which includes the enabling code. The recognition of the enabling code enables the reviewing station (18) to receive and process the transmitted information. The enabling code is derived from a sequence of logical "1" and "0" bits and certain bits of the sequence are altered to form groups of three like bits (111,000). Each group of three bits has no more than two adjacent pairs of like and opposite bits (10,01). The groups of like bits are arranged in a first part of the second group (SC) so that the chances of incorrect recognition are minimised and the synchronisation achieved by the first group (BR) is unaltered.

Description: ENABLING CODE FOR RADIOTRANSMISSION OF DATA This invention relates to apparatus for the radiotrans ission of data between a radiotransmitting station and a radioreceiving station and more specifically, to the recognition of enabling codes capable of enabling the receiving station to recognise and to process transmitted data encoded according to a predetermined key. It is known for radioreceivers to be provided with devices which recognise enabling codes to enable the radioreceiver to receive data transmitted through air. Generally, the enabling code is a sequence of bits, and follows a group of bits used to synchronise the receiver to the transmission frequency. In some cases, as a result of radio frequency disturbances or of interferences with other transmissions, these enabling codes are erroneously interpreted by the recognising device as other synchronisation signals, but out of phase with the true transmitted synchronisation signals transmitted. The result is that the radioreceiver is not longer capable of recognising and processing the data transmitted. The present invention aims to overcome the problem outlined above and to provide apparatus which has an enabling code recognition device which, in association with a particular code or key structure, is very rugged, and has a low susceptibility to incorrectly recognising codes, and also has the ability to improve the synchronisation of the radioreceiver with the data transmission frequency. According to the invention, there is provided for the radiotransmission of data as defined in Claim 1. An embodiment of the invention will now be defined, by way of example, and with reference to the accompanying drawings, in which: Figure 1 is a block diagram showing, in outline, the general structure of an embodiment of the invention; Figure 2 shows a complete bit string containing the information transmitted by the apparatus of claim 1; Figure 3 shows wave forms of digital signals processed by the apparatus of Figure 1; Figure 4 shows a functional logic diagram of a portion of the structure in Figure 1; Figure 5 shows a simplified block diagram of a phase locking circuit of the apparatus of Figure 1; Figure 6 is a representative in binary form of information processed by the apparatus of Figure 4; Figure 7 shows an example of the sampling performed by the apparatus of Figure 4; Figure 8a shows a signal corresponding to the sequence of an optimised recognition key, and Figure 8b shows the harmonic content of the signal of Figure 8a. The apparatus for radiotransmission of data is designed to transmit data in digital form at radio frequencies between two or more personal computers which are located in the same building or in separate buildings within a radius of no greater than approximately 500m. Figure 1 shows a typical configuration of the above mentioned apparatus for transmission, in which a first system for processing data, for example a personal computer PCI, processes in known manner data to be transmitted in digital form to a second system for processing data, for example a personal computer PC2. PCI is equipped with a digital radiotransmitting apparatus 12 of known type, which is capable of transmitting the data processed by PCI by means of a transmitting antenna 14. The electromagnetic signals transmitted are picked up by a receiving antenna 16 which is connected to a radio receiving apparatus 18 which is incorporated in the form of an additional card or module in the personal computer PC2. The signals transmitted by the radiotransmitting apparatus 12 are organised in the form of successive blocks or strings ST of bits (Fig. 2). Each string ST is made up in total of 480 bits, the first 32 bits of which constitute the so-called synchronisation sequence SS, while the following group of bits SD represents the set of data transmitted. Each string ST is followed by a group of 64 non-significant bits, not shown in Fig. 2, which are used to separate the strings ST from one another. The synchronisation sequence SS is in turn subdivided into a first group BR of 16 bits known as a bit reverse sequence and it is used, as will be seen below, to sychronise the radioreceiving apparatus. A second group SC of 16 bits is used to recognise the end of the period of synchronisation and the start of reception of the data. The first group BR is made up of an ordered sequence of logic "l"s and "0"s represented by the hexadecimal number "AAAA", equivalent to the binary form 1010101010101010. The second group SC of bits of recognition key is made up of a set of variously grouped "1" and "0" bits, represented for example by the hexadecimal number BA8C, equivalent to the binary form 1011101010001100. Similarly, the sequence SD of data situated following the key is made up of a series of variously grouped bits. Fig. 3a represents the form of the electric signal corresponding to the groups BR, SC and SD of the string ST transmitted by the antenna 14 in the form of positive and negative pulses, each of a duration T ( sec). It is clear that the group BR forms a series of eight complete square waves, the harmonic analysis of which, as is known, reveals a superimposition of one wave of fundamental frequency fo=3/2T; f2=5/2T etc. The fundamental frequency fO is selected for example as 576 kHz as this frequency is correctly used for the transmission of data, for which duration T of a pulse is 0.868 sec. The repetition frequency or transmission rate of the bits of the strings ST is: ft=l/T=1.152 megabit/sec. The radioreceiving apparatus 18 (Fig. 4) comprises an input stage 20 which expediently amplifies the signal picked up by the antenna 14. The stage 20 sends the signal to a synchronisation circuit 22 and to a decoding circuit 24. The circuit 22 carries out the function of synchronising the characteristic timing of the receiving apparatus 18 with the transmission rate I/T of the signals sent by the transmitting apparatus 12. Since the transmission is in digital form, the abovementioned synchronisation consists in locking the phase t of the timing signal t of the radioreceiver 18 with the phase 1 of the signals transmitted by the transmitter 12. To this end, use is expediently made of a phase-locking oscillator circuit 22, known in the art by the abbreviation PPL and distributed commercially under the abbreviation SN74LS297 by Texas Instruments. The functioning of the circuit 22 (Fig. 4) is known to the expert in the field and will therefore only be described in brief below. -o- For further information on the circuit 22, refer to the article by W.T. Greer and B. Kean in Electronic Design of 31st March 1982. The signal received, SI (Figs 4, 5), which has a characteristic phase 1 and is expendiently amplified by the circuit 20, is applied to an input 23 (Fig. 5) of a phase comparator 25 containing an XOR gate 26. The comparator 25 compares the phase 1 with the phase 2 of the timing signal t2 derived in known manner from the signal t by means of an up/down-counter 28 and by a divider 29. The error signal Se present at the output 30 of the comparator 25 is represented in Fig. 3c and, in the absence of error, has a useful cycle of 501 in relation to each bit of the input signal SI. In the presence of positive or negative phase error, the signal Se has "0" bits or "1" bits respectively of longer duration in order to operate an up/down-counter 32 which operates between two predetermined limits +K and -K and the counter 28 so as to keep exactly in phase with one another or locked the input signal SI and the signal t2. When locking has taken place, the signal t2 at the output 34 of the circuit 22 is made up (Fig. 3c) of an ordered sequence of "1" and "0" bits, each having a duration T/2, and, in other words, the signal t2 is balanced perfectly. The circuit 22 moreover comprises a programming circuit 36 which is connected to the counter 32 and capable of modifying the value of K in response to a signal AB1 present at one of its inputs 38, as will be explained below. Therefore, when the receiving apparatus receives the sequence BR, it synchronises with the transmission rate of the signal SI. When, after the sequence BR, the sequence SC is received, it can be seen from the diagrams in Fig. 3a, b, c that groups of 3 like bits, such as for example 40, 42, generate two adjacent like pulses 43 and 45 of opposite sign and of duration T. The fact that the pulses 43 and 45 are adjacent has the effect that the counter 32 does not reach the limits +K or -K, as a result of which the synchronisation previously brought about by means of the sequence BR is not altered. However, groups of two like bits always generate two consecutive like pulses. If the groups of two like bits are in like and opposite pairs such as 46 and 47, two pairs of pulses 49, 51 of opposite value are generated, but separated by two other single pulses, as a result of which, in this case, the counter 32 is operated for a longer time, although it does not reach the limits +K or -K. In this case also the synchronisation is not altered, but the risk is greater. At the end of the examination of the bits of the sequence SC, the synchronisation is locked in the manner described below, as a result of which the data represented by the following sequence SD (Fig. 2) can be processed correctly. With reference again to Fig. 4, the signal SI is also sent to a sampling circuit 24 which, under the control of the signal t2 emitted by the circuit 22, recognises the "1" or "0" level of the bits of the string ST at the rising edges 54 (Fig. 7) of the signal t2. At the ouput 56 made up of the same bits of the string ST received, with a wave form which is perfectly digital, that is to say completely devoid of any distrubance or imperfection of the wave form, and thus in a condition to be correctly processed by the following stages of the receiving apparatus 18. The signal S2 is then sent to a 16-cell shift register 58 which has a loading cycle of one bit at a time, upon each cycle, the content of the register 58 is compared simultaneously in two comparators 60 and 61 with a real enabling key SCI and respectively with its negation CSCI, both extracted from two sections 53-1, 63-2 of a memory 63 of known type which is connected to both the comparators 60 and 61. The positive outcome of the comparison effected by the comparators 60 and 61 means that the key represented by the sequence SC is the real one and is therefore recognised by the receiving appratus 18. In such a situation, the comparators 60 and 61 means that the key represented by the sequence SC is the real one and is therefore recognised by the receiving apparatus 18. In such a situation, the comparators 60 and 61 generate an approval signal AB1 in order to operate an enabling circuit 64 the data SD of the string ST to the personal computer PC2. If, on the other hand, as a result of disturbances of various types, some bits of the real code SC transmitted by the apparatus 12 are altered, the comparators will not recognises it and the circuit 64 will not authorise the output of the data bits as a rsult of which these are lost. The enabling circuit 64 comprises an AND gate 66 for output of the data, controlled by a flip-flop 67, which, in the presence of the signal AB1, keeps the AND gate 66 active for the transfer of the data SD to PC2. The signal AB1 is simultaneously sent, as already mentioned above, to the cirucit 36 which programs a value K', -K * . In this manner, the intervention of the phase corrector PLL is practically excluded, as a result of which the data bits of the sequence SD, however they may be ordered, do not alter the synchronisation of the receiving apparatus 18 already achieved by means of the sequence BR and maintained during the reception of the sequence SC. As is known in the art of radiotransmission, the key SC must have two improtant perogatives: one is that of not causing the loss of the data transmitted, the other is the capacity of not altering the synchronisation of the receiving apparatus, brought about by means of the sequence BR. The first perogative is called the "robustness" of the recognition key. This indicates the degree of insusceptibility to incorrect recognition. The robustness is represented by the probabilites that the real key wil be erroneously recognised in incorrect positions within the extent of the sequences SS, both during the bit to bit comparison between the real key and the sequence SS and during the bit to bit comparison between the negation CSC of the key and the same sequence SS. Causes which can give rise to false recognition are generally noise and/or interference which can alter the content of the string ST. A genuinly robust key is unlikely to suffer such effects. In studying the robustness of a key, it is appropriate to separate two cases of false recognitions: anticipated recognition and delayed recognition. Anticipated recognition takes place when the real key SC (Fig. 6a) is compared with an equivalent group of bits straddling the sequence BR and the same key SC within the extent of the sequence SS as is shown by way of example in Fig. 6a. In the relative position of SC, there is anticipated incorrect recognition if nine bits in the positions indicated by "e" of the key received are simultaneously erroneously inverted because of the above entioned disturbances. Therefore the probability Pa that such an event will take place for each position of comparison is given by: Pa=BER H . (l-BER) 16 -" where BER is the rate of error conventionally admitted for the bits of the string ST, H is the displacement to the left of the key SC in relation to the key SC (Fig. 6a). Delayed recognition takes place when the real key SC ' (Fig. 6b) is compared with an equivalent group of bits of the sequence SS straddling the group SC of bits and the following series of data SD, as is shown by an example in Fig. 6b. In such a relative position of SC , delayed incorrect recognition takes places if five bits of the key received in the positions indicated by "e" are simultaneously erroneously inverted by transmission disturbances. Therefore the probability Pr that such an event will take place for each position of the comparison is given by: Pr=[BER H . (1-BER) 32 - H - D ]/2 D - 16 (D=17 ...31) 2) where D is the displacement to the right of the key SC ' in relation to the key SC and where the denomintor indicates the probability that the first D-16 bits of the series of data SD are the same as the correponding bits of the key SC. Considering the comparison of the sequence SS with the negation of the key CSC, two similar expressions Pac and Pre of the probabilities of incorrect recognitions of CSC are obtained. In conclusion, a total probability coefficient of incorrect recognitions of the real key and its negation is defined: Pt= Ptc= r~. Pac + - Pre 4 ) Lower values of Pt and Ptc indicate greater robustness. Calculation of Pt and Ptc for all the keys which can be obtained from the combinations of the 16 bits of the sequence SC has made it possible to pinpoint a certain number of such combinations which have the minimum value of the probabilities of incorrect recognitionε. In order to pinpoint among these combinations or keys that key which "functions" best, it is necessary to specify certain further conditions. As has already been pointed out, each sequence of three like bits generates (Fig. 3) a pair of adjacent error signals of opposite sign, thus very well balanced. Therefore such a sequence can be obtained wihtout limits in the optimum key. It has moreover been established that each sequence of two like bits generates a single error signal which has to be balanced by another sequence of two like and opposite bits arranged immediately afterwards: since, then, sequences of two like and opposite bits generate error signals which are more spaced out, that is to say less balanced that those generated by a single sequence of three bits, it is concluded that it would be better to exclude them; however, it has been noted that the best combinations, that is to say those with the minimum value of probability Pt and Ptc of incorrect recognitions, comprise at least one sequence of two bits. Therefore the optimum key C an contain one sequence of two like and opposite bits. Examining Fig. 6c, in which the sequence BR-SC of Fig. 6a is shown and in which the negation CSC of the key SC is added, it can be seen that the E2 discordance number in relation to the negation CSC is the complement on 16 of the El discordances in relation to SC . Since the higher the number of discordances is, the lower the probability of incorrect recognition is, in the calculation of the total probabilities resulting from the comparison of the real key SC and of the negation CSC, is is clear that there is a lower total probability of incorrect recognitions when the discordances El and E2 tend to be equal. Therefore a further condition arises, that the optimum key must have a number of discordances tending to its complement on 16 in all the comparisons between the same key and its negation in relation to the sequence SS in the subsequent relative positions. By examining the numerous combinations which can be obtained using the 16 bits of the sequence SC of the recognition key, it has been found that the best combination, which satisfies the preceding conditions is that made up of a sequence of "1" and "0" bits comprising one or more groups of three Ike bits, alternating or associated with not more than two adjacent pairs of like and opposite bits, preferably arranged in the first part of sequence SC. This key is represented by the hexadecimal number E98A, corresponding to the binary form 1110100110001010. The key chosen must moreover start with a bit of opposite sign to the last bit of the timing sequence BR which precedes the sequence SC. The key chosen as optimum and indicated above has a corresponding electric wave form, shown in Fig. 8a. Harmonic analysis of the wave form in Fig. 8 reveals that each sequence of two like bits generates frequency peaks at a fundamental frequency f'o =1/4T and at its odd harmonics: f'ι =3/6T, f ' 2 =5/61 etc. From the diagram of the harmonic content of the wave form of the key in Fig. 8a, shown in fig. 8b, a clear and isolated peak emerges at the fundamental frequency fo=l/2T=576kHz, equal to the frequency of synchronisation of the receiving apparatus 18. Therefore it can be seen that the sequence of two bits of the key Fig. 8a does not make any contribution to the fundamental frequency of 576kHz, having frequency peaks at a great distance from it, which the sequence of three bits makes a certain contribution with its second odd harmonic 3/6T=l/2T = 576kHz to the synchronisation frequency. Therefore it has been verified that the key chosen and indicated above not only does not interfere with the synchronisation of the apparatus 18 but makes a contribution to keeping it locked to the signal received. This is also brought about by virtue of the balanced content of "1" and "0" bits, that is to say of eight "1" bits and eight "0" bits. It is to be understood that variations, additions and substitution of various integers described may be made without departing from the scope of the invention. For example, the radiotransmitting apparatus 12 and the radioreceiving apparatus 18 can be respectively integrated in two separate portable telephone apparatus, each connected to the corresponding personal computer and adapted to transmit and respectively to receive via radio on telephone channels the data processed by the corresponding personal computer.

Claims: CLAIMS 1. Apparatus for the radiotransmission of data, comprising a radiotransmitting station capable of transmitting to a receiving station, digital information at a predetermined rate, the receiving station neing controlled by a timing circuit having means for recognising a predetermined enabling code, the digital information being transmitted as bit sequences, each sequence comprising at least a first group of synchronisation bits for synchronising the timing cirucit and the data transmission rate, the first bit group being followed by a second group of bits including the enabling code, the recognition of which by the recognition means enables the receiving station to receive and process the transmitted information, characterised in that the enabling code is dervied from an ordered sequence of logical "1" and logical "0" bits, in which certain bits in the sequence are altered to form groups of three like bits, (111,000), wherein each group of three like bits has not more than two adjacent pairs of like and opposite bits (10,01), the group of like bits being arranged in a first part of the second bit group to enable the recognition means to recognise the code with the minimum probability of incorrect recognition and to maintain unaltered the syncrhonisation achieved by the first bit group. 2. Apparatus according to Claim 1, wherein the enabling code comprises sixteen bits, at least 8 of which are of a value of logical "1", while the remaining bits are of a value of logical "0". 3. Apparatus according to Claim 1 or 2, wherein the enabling code has a number of discordances tending to its complement of 16 in all the bit to bit comparisons between said key and its logical negation in relation to said consecutively considered first and second group of bits. 4. Apparatus according to Claim 1, 2 or 3, wherein the initial bit of the enabling code has the opposite value to that of the last bit of the synchronisation group. 5. Apparatus according to any of the preceding claims, wherein the enabling code is represented by the hexadecimal number E98A. 6. Apparatus according to any preceding claim, wherein the enabling code has the minimum probability of incorrect recognition of all possible bit combinations in the second group of bits. 7. Apparatus according to any preceding claim, wherein the code is represented by a digital signal which has a significant harmonic content exclusively in the region of the frequency corresponding to said transmission rate. 8. Apparatus according to any preceding claim, wherein the radiotransmitting station comprises a radiotransmitting apparatus integrated in a first data processing system and the receiving station comprises a receiving apparatus integrated in a second data processing system separate from the first system. 9. Apparatus according to claim 8, wherein the radiotransmitting and receiving apparatus comprise portable telephone apparatus connected respectively to the first and second system and capable respectively of transmitting and receiving said data at radio frequencies on pre-arranged telephone channels. 10. Apparatus according to Claim 8 or 9, wherein the first and second data processing system each comprise at least one personal compute . 11. Apparatus according to any preceding claim, wherein the receiving station comprises an antenna capable of detecting information transmitted by the radiotransmitting sation for transfer as an electric signal to an input amplification circuit, a phase-locking circuit for locking the phase of the timing circuit with the phase of the amplified signal, a sampling circuit connected to the input circuit and controlled by said phase-locking circuit to reconstruct said amplified signal as a digital signal, a shift register connected to the sampling circuit and capable of storing portions of the digital signal which are cylically variable and of a length equal to the code length, wherein said recognition means comprises means for comparing each portion with a reference code stored in a memory of the receiving station and an enabling circuit connected to the sampling circuit and instructed by the comparing means to transfer the digital signal when the reference code coincides with a predetermined portion of the digital signal. 12. Apparatus according to Claim 11, wherein the memory further contains the logical inverse of the reference code and wherein the comparison means comprises two digital comparators for simultaneously comparing the code and its inverse with each of said digital signal portions. AMENDED CLAIMS [received by the International Bureau on 10 May 1992 (10.05.92); original claims 1,2 and 4 replaced by amended claim 1; claims 3,5-10,11 and 12 replaced by new claims 2,3-8,9 and 10 (3 pages)] 1. Enabling code for an apparatus for the radiotransmission of data, comprising a radiotransmitting station capable of transmitting digital information at a predetermined rate, to a receiving station, the receiving station being controlld by a timing circuit having means for recognising a predetermined enabling code, the digital information being transmitted as bit sequences, each sequence comprising at least a first group of synchronisation bits for synchronising the timing circuit with the data transmission rate, and a second group of bits including the enabling code, immediately following the first bit group, the enabling code comprising sixteen bits, at least 8 of which are of a value of logical "l", the recognition of said code by the recognition means enables the receiving station to receive and process the transmitted information, characterised in that the enabling code is derived from an ordered sequence of logical "1" and logical "0" bits, in which certain bits in the sequence are altered to form groups of three like bits, (111,000), wherein the initial bit of the enabling code has the opposite value to that of the last bit of the synchronisation group, at least two groups of three like bits being alternate by no more than two adjacent pairs of like and opposite bits (00,11), the pairs of like bits being substantially arranged in a first part of the second bit group to enable the recognition means to recognise the c-de with the minimum probability of incorrect recognition and to maintain unaltered the synchronisation achieved by the first bit group. 2. Enabling code according to claim 1 characterised by having a number of discordances tending to its complement of 16 in all the bit to bit comparisons between said key and its logical negation in relation to said consecutively considered first and second group of bits. 3. Enabling code according to any of the preceding claims, wherein the enabling code is represented by the hexadecimal number E98A. 4. Enabling code according to any preceding claim, wherein the enabling code has the minimum probability of incorrect recognition of all possible bit combinations in the second group of bits. 5. Enabling code according to any preceding claim, wherein the code is represented by a digital signal which has a significant harmonic content exclusively in the region of the frequency corresponding to said transmission rate. 6. Enabling code according to any preceding claim, wherein the radiotransmitting station comprises a radiotransmitting apparatus integrated in a first data processing system and the receiving station comprises a receiving apparatus integrated in a second data processing system separate from the first system. 7. Enabling code according to claim 8, wherein the radiotransmitting and receiving apparatus comprise portable telephone apparatus connected respectively to the first and second system and capable respectively of transmitting and receiving said data at radio frequencies on pre-arranged telephone channels. 8. Enabling code according to Claim 8 or 9, wherein the first and second data processing system each comprise at least one personal computer. 9. In an apparatus using an enabling code according to any preceding claim, wherein the recognition means comprises a comparator to generate an error signal responsive to the comparison of the successive portions of transmitted digital informations with a reference code stored in a memory of said receiving station, an up/down counter set at predetermined limits (+K, -K) by a limit programming circuit, and an enabling circuit controlled by said counter to allow the transfer of said digital informations when said counter does not reach said limits and to prevent the transfer of said digital informations when said counter reaches said limits. 10. In an apparatus according to claim 9, wherein the limit programming circuit is caused by said error signal to change said limits when said counter does not reach said predetermined limits.

Inventors: RATTI UMBERTO, RATTI, UMBERTO
Applicants: SIXTEL SPA, SIXTEL S.P.A.
Application year: 1991
Main classification: H04L7
IPC codes: H04B1, H04B7, H04L7, H04W88