Data conversion method and pilot signal formation method using the same

Abstract: A data conversion method from m bits of data words into n bits of code words in recording or transmission, in which n is larger than m. A number of bit "0" arranged between one bit "1" and a next bit "1" is restricted to at most 4 in a code string of each code word, and a pair of groups of the n bits of code words corresponding to CDSs (code word digital sum) of two codes +1 and -1 are allowed to correspond to the m bits of data words. One of the two codes +1 and -1 is selectively used according to a DSV (digital sum variation) control signal to convert the m bits of data word into the n bits of code word. A pilot signal formation method using the data conversion method for obtaining a tracking error signal in a magnetic recording and reproducing apparatus, and a rotary magnetic head device for use in a magnetic recording and reproducing apparatus are also disclosed.

Description: The present invention relates to a data conversion method for converting digital data into suitable signals for a recording or transmission system in recording or transmitting the digital data and a pilot signal formation method using the data conversion method for obtaining a tracking error signal in a magnetic recording and reproducing apparatus such as a digital VTR (video tape recorder) system or the like. As a conventional data conversion system, for example, an 8/10 modulation system has been developed, as disclosed in "The Dat Conference Standard", June 1987. In the conventional 8/10 modulation data conversion system, digital data are delimited by data words of 8 bits, and the data words are converted into code words of 10 bits, as shown in Figures 1 to 3. In Figure 1, a data word a of 8 bits and a first table selection signal Q' of 1 bit are input to an encoder 1, and the encoder 1 outputs a code word b of 10 bits and a second table selection signal Q of 1 bit for a next code word. A flip flop 2 receives the second table selection signal Q for the code word b and delays the table selection signal Q for one data word a . In the encoder 1, for instance, a data conversion table shown in Figure 2 for converting the data words into code words is stored in a ROM (read only memory) or the like. In the data conversion table, 256 data words of hexadecimal codes of "00" to "FF" correspond to code words of CDS (code word digital sum) = 0 in one-to-one relation and also to the code words of CDS ≠ 0 with reference to a pair of CDS values of +2 and -2, and tables Q' = -1 and Q = +1 are composed of data words of CDS = +2 and CDS = -2, respectively. The signal Q selects the CDS (table) so as to suppress divergence of charges in a code word string. In Fig. 3, signals a , b and Q correspond to those at the points a , b and Q in Fig. 1, and a signal c is obtained after a NRZI (non-return-to-zero inverse) modulation where inversion is carried out by data "1". A signal d represents DSV (digital sum variation) at the end of each code word after the NRZI modulation. The operation of the 8/10 modulation system described above will now be described in detail. First, when an 8 bit data word a of and a first table selection signal Q' = -1 are input to the encoder 1, the encoder 1 outputs a 10 bit code word b of 1111101010 having a CDS = +2 corresponding to of the signal Q' = -1 and a second table selection signal Q = -1. Then, the 10 bit signal is converted from a parallel signal into a serial signal, and the NRZI modulation of the serial signal is carried out. Hence, the DSV value of the end of the code word becomes +2. Then, when a data word a of is input to the encoder 1, a 10 bit code word b of 0101010101 having a CDS = 0 corresponding to of the signal Q' = -1 resulted from delaying the just preceding output signal Q = -1 by one symbol in the flip flop 2, and a signal Q = 1. As a result, the DSV value of the end of the code word b after the NRZI modulation is +2. Next, when a data word a of is input to the encoder 1, a 10 bit code word b having a CDS = -2 corresponding to of the signal Q' = 1 and a signal Q = -1. Accordingly, the DSV value of the end of the code word b after the NRZI modulation is 0. That is, in general, when an 8 bit data word a is input to the encoder 1, the encoder 1 outputs a code word b selected from either the table where Q' = -1 or Q' = 1 corresponding to the data word a according to a first table selection signal Q output right before, and as a result, a DSV value at the end of each code word b after the NRZI modulation is restricted to 0 or ±2n. This means that the divergence of the DSV is suppressed, and as a result, a DC free data conversion excluding any direct current component can be realized. In the conventional data conversion system, as described above, since the CDS values of the code words obtained in the conversion are selected from only 0 and ±2, the suppression control of the DSV values for the code words can not be positively or actively carried out, and the spectrum of the code word includes relatively low frequency components. Further, when a DSV control circuit is provided to use a DSV value as one of data, the DSV value can not be controlled every code word. In Figs. 4 and 5, there is shown a pilot signal formation circuit and a tracking error detecting circuit for use in producing a tracking error in a conventional magnetic recording and reproducing apparatus, as disclosed in Japanese patent laid-open No.Sho 59-68862. As shown in Fig. 4, a reference oscillator 101 for generating a reference signal, a presetable counter 102, a flip flop 103, a filter 104 and a mixer 105 for adding a reference sine wave signal 106 output from the filter 104 and a data signal 107 representing an audio or visual signals are connected in series. A magnetic head 109 for carrying out the recording or reproducing of a signal onto or from a magnetic medium 122, such as a magnetic tape, is coupled with the mixer 105 through a turnover switch 108 for selecting recording or reproducing, and a frequency dividing ratio controller circuit 10 receives a track switch signal 111 and a record and reproduction switch signal 112 and controls the frequency dividing ratio of the presetable counter 102. A low pass filter 113 for inputting a reproduction signal 114 fed from the magnetic head 109 via the turnover switch 108, a mixer 115 for adding the reproduction pilot signal output from the low pass filter 113 and the reference signal 106 fed from the filter 104, an amplifier 116 and a divider circuit 117 are connected in series. The divider circuit 117 outputs a signal to a pair of envelope detector circuits 119a and 119b through respective band pass filters 118a and 118b, and a differential amplifier 120 receives the output signals of the two envelope detector circuits 119a and 119b and compares them to output a tracking control signal 121. Fig. 5 illustrates the magnetic medium 122 such as the magnetic tape and the magnetic head 109 which is movable along recording tracks 123 on the magnetic tape in the conventional magnetic recording and reproducing apparatus. The operation of the conventional magnetic recording and reproducing system shown in Figs. 4 and 5 will now be described in detail. First, in the recording of a signal onto a magnetic tape, the frequency dividing ratio of the presetable counter 102 is switched by the frequency dividing ratio controller circuit 110 according to the track switch signal 111, and the output signal of the presetable counter 102 is further frequency-divided by the flip flop 103. The filter 104 receives the output signal of the flip flop 103 and outputs the reference sine wave signal (pilot signal) 106 to the mixer 105, and the mixer 105 adds the reference signal 105 and the data signal 107 to output a recording signal to the magnetic head 109 via the turnover switch 108. The magnetic head 109 records the recording signal onto the magnetic tape 122. In this case, since the track switch signal 111 is changed every time the recording track is changed, for example, four kinds of pilot signals f1, f2, f3 and f4 can be recorded onto the magnetic tape, as shown in Fig. 5. In this instance, it is necessary to determine the frequencies of the pilot signals from, for instance, several tens of kHz to several hundreds of kHz, so that the data signal 107 may not be damaged when the pilot signal is extracted and the data signal 107 is reproduced. By determining the frequencies of the four pilot signals f1 to f4 to the following formulas in consideration of a 4 frequency pilot system of an 8 mm VTR (video tape recorder) for public use, f1 + fA = f2, f2 + fB = f3 f4 + fA = f3, f1 + fB = f4 when the recording signal is reproduced from the magnetic tape by the magnetic head 109 shown in Fig. 4 in a reproducing mode, the pilot signal mixed with the data signal 107 recorded onto the magnetic tape is also reproduced. This pilot signal can be extracted by the low pass filter 113, and at this time, not only the pilot signal for the track now being scanned by the magnetic head 109 but also the pilot signals of both adjacent tracks thereto are picked up as crosstalk. Since the frequency of the pilot signals of the adjacent tracks is low enough compared with the video signal or the like, for example, even in an azimuth recording, the azimuth effect will be negligible, and thus the pilot signals can be reproduced as a large crosstalk amount. When the pilot frequency of the reference signal 106 written in the scanning track is added to the pilot signals reproduced as above in the mixer 115, a beat is caused between the reference signal 106 and the pilot signals due to the crosstalk of the adjacent tracks, and beat frequencies of the beat signals fA and fB in formula (1) above-described can be obtained. As shown in Fig. 5, for instance, on reproducing the track 123 in which the pilot signal having the frequency f2 is written, the pilot signals having the frequencies f1 and f3 can also be obtained as crosstalk, and, when the pilot signals are added to the reference signal 106 in the mixer 115, the beat signals fA and fB can be obtained from above formulas (1) and (2) such as f2 - f1 = fA and f2 - f3 = -fB. Next, the output signal of the mixer 115 is fed through the amplifier 116 and the divider circuits 117 and is extracted in the band pass filters 118a and 118b. Then, the filtered signals are detected in the envelope detector circuits 119a and 119b. At this time, while the magnetic head 109 scans on-track along the track of the signal f2, when the magnetic head 109 is shifted a slight amount toward the f1 side, the beat signal fA increases, or a slight amount toward the f3 side, the beat signal fB increases, and hence the output signal of the differential amplifier 120 can be output as the tracking control signal 121. In the conventional magnetic recording and reproducing apparatus as described above, high density recording or reproducing is carried out, and a tracking system with extremely narrow tracks is provided. Hence, in this case, a device capable of detecting a track shift with high accuracy is required, and in general, as described above, by recording the low frequency pilot signals, the track shift can be detected. However, in the case of digital magnetic recording, there is a power spectrum extending over a wide frequency range from a component near a direct current to a maximum recording frequency in usual recording and reproducing, and thus a gap in the so-called frequency allocation can not be formed outside the range of a carrier and its periphery as in conventional analog FM recording. In particular, in a digital recording, it is difficult to insert a low frequency pilot signal for tracking into a gap in the frequency allocation like present analog 8 mm VTR. When the power level of the pilot signal recorded in the frequency range of the pilot signal for tracking is large enough compared with the power level of the recording signal obtained by modulating the digital data even in the digital recording, the pilot signal for tracking can be extracted by a band pass filter or the like and reproduced in the same manner as a conventional example. However, in the case where the power level of the pilot signal is enlarged too much with reference to the recording or reproducing signal of visual or audio data as described above, when the signal is demodulated during reproducing, the wave form deformation is enlarged and the error rate of the digital data increases. Particularly, when the digital data after the modulation and the pilot signal for tracking are added in an analog way before being input to the recording amplifier, since there is no relationship between the digital data and the pilot signal, the two signals mutually act as only disturbance signals. That is, in a digital data recording and reproducing apparatus such as a digital audio recorder or a digital video recorder, the frequency spectrum of a recording or reproducing signal includes many low frequency components due to a feature of digital recording, and, when a low frequency pilot signal for tracking is added to the recording or reproducing signal to record the added signal, since there is no relationship between the recording or reproducing signal and the pilot signal, a wave form deformation is caused when demodulating the modulated digital signal, and the data error rate increases. In order to reduce the wave form deformation caused in the demodulating, the power level of the pilot signal is lowered, and a necessary S/N ratio for a servo (tracking) detection signal can not be obtained. Accordingly, the servo can not be given, and the recording density in the tracking direction in the magnetic tape can not be gained. In Fig. 6, there is shown a conventional rotary magnetic head device, as disclosed in Japanese patent laid-open No.Sho 58-47383. Fig. 7 shows a track pattern recorded on a recording medium such as a magnetic tape by the rotary magnetic head device shown in Fig. 6, and in this instance, the recording is carried out without any guard band, adjacent two tracks having different azimuth angles. As shown in Fig. 6, two double azimuth heads 202 each composed of a pair of heads H L1 and H H1 , or H L2 and H H2 having different azimuth angles are arranged on the periphery of a rotary drum 201. The pairs of heads H L1 , H H1 , H L2 and H H2 are aligned in opposite positions through 180° with reference to the central axis of the rotary drum 201, and the pair of heads H L1 , and H H1 or H L2 and H H2 are arranged at a distance away from each other corresponding to 6H (H means a horizontal scanning period) time. A recording medium 203 such as a magnetic tape is wound around approximately half the rotary drum 201. The operation of the conventional rotary magnetic head device shown in Figs. 6 and 7 will now be described in detail. First, in a recording mode, a composite color signal composed of a luminance signal and a color signal multiplied by each other is divided into two system signals such as a low range signal SL including a signal representing a brightness component and a high range signal SH including a color signal component (carrier color signal) and a high range luminance signal component, and the low and high range signals SL and SH are frequency-modulated. Then, the modulated low and high range signals are input to the double azimuth head 202 composed of two heads H L1 and H H1 or H L2 and H H2 arranged on the rotary drum 201 and are recorded in two channels on the recording medium 203. In this instance, the divided two range signals SL and SH are passed through two different systems, and hence their delay times can be different on reproducing. Hence, a timing-axis adjustment may be required, and as reference signals for the timing-axis adjustment, a burst signal and a horizontal synchronizing pulse (PH) are used for the low range signal SL and the high range signal SH, respectively. The PH signal is a low frequency signal with negligible azimuth effect. As a result, as shown in Fig. 7, by determining the head distance between the two heads H L1 and H H1 or H L2 and H H2 to 6H, the H-alignment is achieved in the tracking pattern recorded on the recording medium 203. Hence, even when the crosstalk is increased in the P H portions by mistracking, such sections correspond to the horizontal blanking periods,and no image quality deterioration by the crosstalk will be caused. US4833471 discloses a m/n bit code converter in which the variance of DC level is suppressed by checking the CDS of the code words, inverting or not the first bit of the code word and adding or substracting the CDS from the DSV. The CDS of the code words is not limited to +1 or -1. EP-A-0 104 700, on which the precharacterising portion of claim 1 is based, discloses a method of recording data which has been code converted from 3 to 5 bits. For each input data word, two code words are provided of equal but opposite DC content and these are selected depending on a control signal which depends on the desired tracking signal. Accordingly, it is an object of the present invention to provide a data conversion method in view of the above-described problems of the prior art, which is capable of controlling a DSV value every code word, and reducing relatively low frequency components in a spectrum of a code word to achieve a DC free data conversion. It is another object of the present invention to provide a pilot signal formation method for forming a tracking error signal in a magnetic recording and reproducing system, in order to prevent problems of the prior art, which is capable of largely reducing wave form deformation in demodulating a signal by adding pilot signals to a data signal, obtaining a large S/N ratio of a servo detection signal and narrowing a tracking pitch to achieve high density recording and reproducing. In accordance with one aspect of the present invention, there is provided a method of encoding data for storage on a magnetic storage medium comprising: providing data arranged in data words of m bits; developing first and second code words of n bits from each said data word of m bits, n being larger than m, said first and second code words differing by the most significant bit thereof and the number of "0" bits arranged between each bit "1" and the next bit "1" being at most 4 in a code string of each code word; allowing a first and a second n-bit code word having respectively a CDS (code word digital sum) of +1 and -1 or having respectively a CDS of -1 and +1 to correspond to each m bit data word; providing a DSV (digital sum variation) control signal representative of the desired change in DSV; and selecting one of said first and second code words having a known CDS based on the provided DSV control signal to make the DSV of said code word string approach the desired DSV; characterised in that: the first code words are developed by using code words of n bits whose most significant bit is "0" and whose CDS is either +1 or -1; the second code words are developed by changing the most significant bit of the first code word to "1". In one embodiment, the present invention provides a pilot signal formation method for obtaining a tracking error signal in a magnetic recording and reproducing apparatus in which digital signals are recorded or reproduced onto or from a magnetic medium by using a rotary magnetic head device mounted on a rotary drum, comprising encoding the digital signals in accordance with the method above and controlling a DSV (digital sum variation) of a string of digital data by using selected one of the two code strings having respectively a CDS of +1 and -1 according to a DSV control signal, an initial phase of the DSV control signal being preset by a signal synchronised with a drum PG signal for controlling the phase of the drum to form a pilot signal synchronised with the digital data. In another embodiment, the present invention provides a pilot signal formation method for obtaining a tracking error signal in a magnetic recording and reproducing apparatus in which digital signals are recorded or reproduced onto or from a magnetic medium by using a rotary magnetic head device mounted on a rotary drum, comprising encoding the digital signals in accordance with the method above, and forming two kinds of DSV (digital sum variation) control signals by counting a code conversion cycle (SYCK), and selecting one of them by using a drum PG signal (DPG) for controlling the phase of the drum; and setting the DSV to zero at the end of each cycle of a predetermined number of the code words by using the selected DSV control signal to select one of the two code strings having respectively a CDS of +1 and -1 to form two kinds of pilot signals of differing frequency which are alternately selected every recording track. The invention will be further described by way of example, with reference to the accompanying drawings, in which:- Fig. 1 is a schematic block diagram of a circuit structure for a conventional data conversion system; Fig. 2 shows a data conversion table used in the data conversion system shown in Fig. 1; Fig. 3 is a schematic chart for explaining the operation of the data conversion system shown in Fig. 1; Fig. 4 is a schematic block diagram of a pilot signal formation circuit and tracking error detection circuit for forming a tracking error in a conventional magnetic recording and reproducing apparatus; Fig. 5 shows a relationship between a recording medium and a magnetic head movable thereon for use in the conventional system shown in Fig. 4; Fig. 6 shows a conventional rotary magnetic head device arranged on a rotary drum; Fig. 7 shows a relationship between a recording track pattern recorded on a recording medium and the rotary magnetic head device shown in Fig. 6; Fig. 8 is a circuit diagram of a data conversion system according to the present invention; Fig. 9 shows code word numbers obtained under certain conditions in the data conversion system shown in Fig. 8; Figs. 10a to 10d show a code conversion table for use in the data conversion system shown in Fig. 8; Fig. 11 is a schematic chart for explaining an operation of the data conversion system shown in Fig. 8; Fig. 12 is a graphical representation showing a power frequency spectrum of a signal obtained in the data conversion system according to the present invention; Fig. 13 is a graphical representation showing another power frequency spectrum of a signal obtained in the data conversion system according to the present invention; Fig. 14 is a block diagram of one embodiment of a pilot signal formation circuit for forming a tracking error in a magnetic recording and reproducing apparatus according to the present invention; Fig. 15 shows code words of original data for use in the circuit shown in Fig. 14; Figs. 16 and 17 are timing charts of a DSV value of a code word according to the present invention; Fig. 18 is a schematic chart for explaining an operation of the circuit shown in Fig. 14; Fig. 19 is a graphical representation showing a power frequency spectrum of a code string obtained in the circuit shown in Fig. 14; Fig. 20 shows recording tracks and magnetic heads for recording the tracks in the circuit shown in Fig. 14; Fig. 21 is a timing chart showing an error signal formation from pilot signals according to the present invention; Fig. 22 shows a relationship among phases of pilot signals of adjacent tracks according to the present invention; Fig. 23 is a time chart showing wave forms appearing in the circuit shown in Fig. 14; Fig. 24 is a block diagram of another embodiment of a pilot signal formation circuit and a tracking error detection circuit for forming a tracking error in a magnetic recording and reproducing apparatus according to the present invention; Fig. 25 is a schematic chart for explaining an operation of the circuit shown in Fig. 24; and Fig. 26 shows a relationship between a recording medium and a magnetic head movable thereon for use in the circuit shown in Fig. 24. The present invention will now be described with reference to the accompanying drawings, wherein like reference characters designate like or corresponding parts throughout the several views and thus the repeated description thereof can be omitted for brevity. Now, codes satisfying the conditions that a data word length m = 12; a code word length n = 15; and Tmax/Tmin = 5, will be formed. In this case, it is defined that d (the minimum number of "0" between any "1" and the next "1") = 0, and k (the maximum number of "0" between any "1" and the next "1") = 4. The NRZI (non-return-to-zero inverse) (F) rule is applied to the codes. Hence, in order to satisfy k = 4, the maximum number of continuous "0" in each code word is at most 2 in the MSB (most significant bit) side and the LSB (least significant bit) side and is also at most 4 within the code word itself. In this case, in the code words in which the MSB starts from "0", the code word numbers satisfying the "0" run-length condition are shown in Fig. 9. In this embodiment, although the data word length m and the code word length n (n > m) are selected to 12 and 15, respectively, the present invention is not restricted to these values, and any numbers can, of course, be used within the scope of the present invention. Now, in order to form DC (direct current) free codes, by considering code words having different polarities of the CDS (code word digital sum) as one pair, 2 12 (4096) codes are sufficient. The code word numbers shown in Fig. 9 are only of the code words whose MSB is "0". Hence, by replacing the MSB with "1" in place of "0", the code words having the inverse polarity of CDS and satisfying the "0" run-length condition can be obtained. Consequently, only by the use of the above-described code words with CDS = ±1, can the data words = 2 12 (4096) < code word number = 4616 be obtained. By using only the code words with the MSB = "0" and the CDS = ±1 and controlling the MSB to either "0" or "1", the divergence of the DSV (digital sum variation) can be suppressed. Also, the control of the MSB can be settled by checking up the CDS data ("1" by +1 and "0" by -1) of the code words converted right before and the level data ("1" at high level and "0" at low level) at the end of the code word after the NRZI modulation on the basis of a control signal command. Thus the obtained code conversion table is shown in Figs. 10a to 10d. In Figs. 10a to 10d, two-value digital signals are shown by hexadecimal codes. As to the 12 bits of input data words, when the MSB of the code word is "0", the CDS data is represented by 1 bit, and the level data (hereinafter referred to as "Q" and the start end of the code word starts from 0 level) at the end of the code word after carrying out the NRZI modulation of the converted serial data is represented by 1 bit, and the remaining 14 bits correspond to the LSB to the 14th bit of the code word. In Fig. 8, there is shown one embodiment of a data conversion system according to the present invention. An encoder 3 includes the code conversion table shown in Figs. 10a to 10d. The encoder 3 receives 12 bits of digital data or data words and converts the data words into 16 bits of digital data or code words shown in the code conversion table shown in Figs. 10a to 10d. A MSB controller 4 includes four EXOR circuits A, B, C and D and a one symbol (code word) delay circuit 4a. The MSB controller 4 receives CDS and Q output from the encoder 3 and a DSV control signal command and outputs a signal Y representing a MSB level. A parallel-serial (P/S) converter 5 receives 14 bits of code words output from the encoder 3 and the signal Y output from the MSB controller 4 and converts 15 bits of parallel data into a serial data string to output a serial code word to an NRZI modulator 6. The NRZI modulator 6 processes the serial data string of the code word so as to repeat an inversion every "1" level to output a modulated signal. In Fig. 11, there are shown signals at the points (e), (f), (g), (h), (i), (i'), (Y), ((Y)+(j)) and (k) which appear in Fig. 8 along with (ℓ) DSV values at the end of a code word. The operation of the data conversion according to the present invention will now be described in detail in connection with Figs. 8 to 11. First, in the initial set state, the output (i') of the 1 symbol delay 4a of the MSB controller 4 and the output of the NRZI modulator 6 are reset to a "0" level. In this state, when a data word (e) of is input to the encoder 3, the encoder 3 outputs 14 bits of code word composed of the LSB to the 14th bit, 1 bit of CDS signal and 1 bit of Q signal corresponding to the code word in the form of a total of 16 bits of signal of obtained by the code conversion table shown in Figs. 10a to 10d. The detail of the 16 bits of signal of is as follows. That is, the MSB bit of the 4 bits 0011 of 3 is the Q signal for the code word, and "0" and "1" represent a low level and a high level, respectively, of the end of the code word after the NRZI modulation when the MSB of the code word is "0" (the start end of the code word starts from a low level in the NRZI modulation). The second bit from the MSB of the 4 bits 0011 of 3 is the CDS signal of the code word, and "0" and "1" represent -1 and +1, respectively, when the MSB of the code word is "0". The lower two bits of the 4 bits 0011 of 3 correspond to the 14th and 13th bits of the code word. Then, 4 bits 1111 of , 4 bits 1100 of and 4 bits 1001 of successively correspond to 12th to 9th bits, 8th to 5th bits and 4th to the LSB, respectively, of the code word. The 14 bits of code word (j) are sent to the P/S converter 5, and the Q signal (h) and the CDS signal (g) together with the DSV control signal command (f) are fed to the MSB controller 4. In the MSB controller 4, the MSB of the code word is determined as hereinafter described in detail and is output as the Y signal to the P/S converter 5. The DSV control signal command (f) is set to "1" (high level) or "0" (low level) when the divergence of the DSV is carried out in the (+) direction or the (-) direction, respectively. In this embodiment, as shown in Fig. 11, relating to the data word of the DSV control signal command (f) is output so that the DSV may diverge in the (-) direction, and hence it is required to control the code word so that the CDS may be (-) in the code string. Thus, in the MSB controller 4, by checking up the output (i') of the 1 symbol delay 4a which represents "0" or "1" when the level of the end of the code word after the NRZI modulation of a just preceding code word is low or high, respectively, it is checked by the EXOR circuit A whether or not the divergence directions of the CDS and the DSV are coincident with each other when the MSB of the code word to be output at present is "0". When the divergence directions of the CDS and the DSV are coincident or not coincident, the output of the EXOR circuit A is "0" or "1", respectively, thereby operating so that the CDS of the code word may be coincident with the divergence direction command of the DSV when the NRZI modulation of the MSB of the code word is carried out from the low level. Then, the output of the EXOR circuit A and the output (i') of the 1 symbol delay 4a are fed to the EXOR circuit B. When the output (i') is "0" (that is, the end of the just preceding code word is ended as the low level after the NRZI modulation), the output of the EXOR circuit A is output as the MSB signal (Y) of the code word from the EXOR circuit B as it is. On the other hand, when the output (i') is "1" (that is, the end of the just preceding code word is ended as the high level), since the polarity of the CDS of the code word is inverted during the NRZI modulation, thus the output of the EXOR circuit A is inverted in the EXOR circuit B, and the inverted output of the EXOR circuit A is output as the MSB signal (Y) of the code word from the EXOR circuit B. By applying the above-described operation to one embodiment, as apparent from Fig. 11, when the data word of is input to the encoder 3, the DSV control signal command (f), the CDS (g), the output of the EXOR circuit A, and the output (i') of the 1 symbol delay 4a are all "0", and the output of the EXOR circuit B is also "0" to output the MSB of the code word. As described above, the 12 bits of data word are converted into 15 bits of code word according to a divergence direction command of a DSV. Further, as described above, it is necessary to check the level of the end of the code word after the NRZI modulation, and this checking is carried out as follows. When the MSB of the code word is "0", the Q signal (h) and the MSB signal (Y) of the code word are input to the EXOR circuit C of the MSB controller 4. When the MSB of the code word is "0", the Q signal is output from the EXOR circuit C as it is. On the other hand, when the MSB of the code word is "1", since the code word is inverted during the NRZI modulation process, the Q signal is inverted in the EXOR circuit C, and the inverted Q signal is output from the EXOR circuit C. Then, the output of the EXOR circuit C and the output (i') of the 1 symbol delay 4a, which represents the level of the end of the just preceding code word after the NRZI modulation, are fed to the EXOR circuit D. In the case where the output (i') is "0" (that is, the level of the end of the just preceding code word after the NRZI modulation is low), when the code word now being converted is continuous to the just preceding code word, the level of the end of the code word after the NRZI modulation becomes the output level of the EXOR circuit C. Hence, the output of the EXOR circuit C is output, as it is, from the EXOR circuit D to the 1 symbol delay 4a for use as an end level signal for the just following code conversion after the NRZI modulation of the just preceding code word. On the other hand, in the case where the output (i') is "1" (that is, the level of the end of the just preceding code word after the NRZI modulation is high), when the code word now being converted is continuous to the just preceding code word, it is necessary to convert the output of the EXOR circuit C, to that obtained when the level of the end of the code word after NRZI modulation starts from the high level. Hence, the output of the EXOR circuit C is inverted in the EXOR circuit D, and the inverted output is output from the EXOR circuit D to the 1 symbol delay 4a for use as the end level signal for the just following code conversion after the NRZI modulation of the just preceding code word. By showing the aforementioned operation with one embodiment, when the data word of is input to the encoder 3, the output (i'), the Q signal (h) of the encoder 3, the output (Y) of the EXOR circuit B, and the output of the EXOR circuit C are all "0". Further, the output (i') and the output of the EXOR circuit D become "0", which is coincident with the fact that the level of the end of the converted code word after the NRZI modulation is low. The above-described operation is repeated every code word conversion, and the 1 symbol delay is carried out. Accordingly, the level check of the end of the code string in the continuous code word string can be correctly carried out. Thus the obtained 15 bits of code word is input to the P/S converter 5 and is converted into a string of serial signal or serial code words therein, as shown in the form of a signal ((Y)+(j)) in Fig. 11. The obtained serial signal is fed to the NRZI modulator 6 which outputs an NRZI-modulated signal (k), as shown in Fig. 11. Then, the data words of " ", " ", " ", " ", " ", " ", ...... are converted into code words shown as the signal ((Y)+(j)) in Fig. 11 while the DSV control is carried out by the DSV control signal command (f) in the same manner as described above, and then the NRZI modulation of the code words is carried out in the NRZI modulator 6 to output the signal (k). The DSV value of the end of each code word in the output signal (k) is within a variation width of ±1 at a 4 code word cycle, as shown in Fig. 11 (ℓ), and thus the code words can be obtained as signals synchronizing with the DSV control signal command. In this embodiment, although the code word (j) composed of the LSB to the 14th bit of the 16 bits of the converted code in the code conversion table shown in Figs. 10a to 10d is output by the encoder 3 and the MSB is decided by the MSB controller 4 to carry out the data conversion from the 12 bits of data word into the 15 bits of code word, two groups of 15 bits of code words composed of a pair of ± code words groups can be prepared, and one of the groups can be selected by the DSV control signal command (f) and the level signal of the end of the just preceding code word after the NRZI modulation so as to directly output 15 bits of code word. Further, in this embodiment, although an example where the code word is further NRZI-modulated is output has been described, after the P/S conversion of the code word, the obtained string of serial code word can be output as it is. In this instance, by using only code words whose run-length codes satisfies at least 2 (3) continuous bits of the same level in the MSB side, at least 3 (2) continuous bits of the same level in the LSB side and at least 5 continuous bits of the same level within the code word itself and the CDS value is either +1 or -1 obtained at "1" or "0" level, respectively, each pair of code words having different polarities of the CDS are allowed to correspond to one data word, and one of each pair of code words is selected according to the DSV control signal command (f) with the same effects as the above-described embodiment. As described above, according to the present invention, the number of the same level of continuous codes within the code word after the NRZI modulation is at least 5, and the coding is carried out by using only the code words with the CDS of ±1 while the CDS value is controlled so as to suppress the divergence of the DSV according to the DSV control signal command. Hence, a data conversion system having a large suppression effect against a relatively low frequency range can be achieved compared with a conventional data conversion system. According to the present invention, by allowing a pair of code words having CDSs of ±1 to correspond to one data word, a DSV control can be freely carried out every code word unit, and hence suppression of a relatively low frequency range can be realized. Figs. 12 and 13 show power spectra obtained according to the present invention. That is, a circuit is constructed by one embodiment of a data conversion system of the present invention, and random signals of M series represented by a formula of (X 23 + X 5 + 1) are partitioned every 12 bits and are input to the circuit to obtain the power spectra. Fig. 12 shows a spectrum extending from 0 Hz to a frequency of a signal for carrying NRZI modulation data. In this case, frequency components less than 0.05 x fcH ( carrier frequency) are suddenly damped to accomplish a DC free modulation. Fig. 13 shows a spectrum extending from 0 Hz to a frequency of 0.1 x fcH. In this case, the DC free modulation is achieved, and it is apparent that a strong spectrum only in the frequencies of the DSV control signal command cycle can be obtained. Further, the signals of the DSV control signal command cycle can be extracted by a band pass filter, and hence the signals can be used as the second signal synchronizing with the digital signal. For instance, when the present invention is applied as a data converter to a magnetic recording and reproducing apparatus in which digital signals are recorded or reproduced onto or from a magnetic tape by using a rotary drum, such signals can be used as pilot signals for a head to correctly scan along recording tracks in the reproducing mode. Next, one embodiment of a pilot signal formation circuit for realizing a pilot signal formation system according to the present invention will now be described in detail in connection with Figs. 14 to 23. In this case, data conversion is carried out in the same manner as described above with reference to Figs. 8 to 13. As shown in Fig. 14, an encoder 124 having a code conversion table shown in Fig. 15 carries out data conversion from 12 bits of parallel input digital signal or data word into a 15 bit parallel digital signal or code word, charge storage (CDS) within the code word allowing a pair of code words having different polarities of -1 and +1 to correspond to one input digital signal. A flip flop 125 outputs a DSV control signal for setting the CDS value of the code word output from the encoder 124. A counter 126 for counting up a code conversion cycle (SYCK) is provided with a load terminal for input of a preset count value, a set input terminal of 3 bits and a CY output terminal for outputting a 1 level to the flip flop 125 when the count value is 7. A parallel-serial (P/S) converter 127 converts the 15 bits of parallel code word fed from the encoder 124 into a string of serial code words to be transferred at a serial data transfer frequency (fcH). A recording amplifier 128 capable of supplying a certain current even on a low load receives the serial code word from the P/S converter 127 and outputs an amplified signal to a double azimuth magnetic head 129 arranged on a rotary drum 134. The double azimuth head 129 includes two heads A and B having different azimuth angles. A recording medium 130 such as a magnetic tape is wound around approximately half the rotary drum 134. An initial phase adjuster circuit 131 synchronized with the rotation of the rotary drum 134 receives a drum PG (DPG) signal, generated by a sensor (not shown) mounted to the rotary drum 134, for generating one pulse per one rotation of the rotary drum 134 and the SYCK and sets an initial phase of a pilot signal at a recording start point every one rotation of the rotary drum 134. A selector 132 selectively outputs signals to the set input terminal and the load terminal of the counter 126. A cycle set 133 for setting the cycle of the counter 126 outputs 3 bits of signal to one terminal of the selector 132. The above-described components, except the double azimuth head 129 and the rotary drum 134, constitute an A-channel (Ach) circuit section 135A. A B-channel (Bch) circuit section 135B having the same structure as the A-channel circuit section 135A (and thus its detailed description is omitted for brevity) is also provided. In this embodiment, although the data word length m and the code word length n (n > m) are selected to 12 and 15, respectively, the present invention is not restricted to these values, and any numbers can, of course, be used within the scope of the present invention. The operation of the system shown in Fig. 14 will now be described in detail in connection with Figs. 14 to 23. In Fig. 14, 12 bits of digital signal are input to the encoder 124 and converted therein into 15 bits of code word selected from one of a pair of code word groups corresponding to a pair of CDSs of ±1 in a code conversion table shown in Fig. 15 according to the DSV control signal output from the flip flop 125. The obtained code word is output from the encoder 124 to the P/S converter 127. Fig. 16 shows, for example, 15 bits of code word obtained from an input digital signal of 001 (hereinafter indicated in the same manner as a parallel signal such as 012, ...., EF) according to the code conversion table shown in Fig. 15, output from the encoder 124, and also shows the charge storage of a string of the code word output from the encoder 124 when the DSV control signal is 0 level. It is clear from Fig. 16 that the charge storage or the level of the end of the code word is -1. Fig. 17 shows another 15 bits of code word obtained from an input digital signal of 001 output from the encoder 124 when the DSV control signal is 1 level, and also shows the charge storage of a string of the code word. It is readily understood that the level of the end of the code word is +1. The charge storage or CDS within the code word is either -1 or +1 for all code words, as shown in Fig. 15, and the CDS at the end of the code word is properly controlled to -1 or +1 by the output level or the DSV control signal output from the flip flop 125. Hence, for example, as shown in a timing chart in Fig. 18, the counter preset value of the counter 126 which counts up to every SYCK, is set to 3, and the CY output of the counter 126 to which the preset value is repeatedly loaded by the CY output at the count value of 7, is fed to the flip flop 125. The flip flop 125 divides the CY output frequency to 1/2, and by controlling the CDS by the 1/2 frequency-divided signal, the code string having a cycle of ten times as large as the SYCK and the DSV = 5 at the end can be obtained in the encoder 124. The power spectrum of the digital signal having two-values such as 1 and 0 can be decided by the appearance of a state transition probability diagram. For example, in the case of the random digital signal in M system, the power spectrum is approximately flat in the frequency range from DC to a carrier clock signal frequency. On the other hand, like the present invention, in the code string where the DSV is regularly and correctly varied at a fixed cycle, in cooperation with the limited DSV, a signal having no DC component and having a spectrum resistant to DSV frequency can be obtained. Fig. 19 shows a power spectrum obtained as follows. That is, under the conditions where the CDS control cycle of the code word is ten times as much as the code conversion cycle, 15 bits of parallel digital signal output from the encoder 124 are fed to the P/S converter 127 and are converted therein into serial data, and the obtained serial data are transferred at 1/15 of the code conversion cycle to the magnetic head 129 through the recording amplifier 128. The power spectrum flowed in the magnetic head 129 is measured, as shown in Fig. 19, and it is confirmed that the spectrum resistant to the DSV cycle (1/150 of the series data carrier frequency fcH) can be obtained. Accordingly, by recording such a signal onto the magnetic tape 130, a low frequency pilot signal can be recorded in synchronization with a digital signal in the same manner as a conventional method. Next, a method of recording a pilot signal formed by the present system will now be described in detail with reference to Figs. 20 and 21. In Fig. 20, on A channel tracks A0, A1 and A2, a first signal output from the recording amplifier 128 to the double azimuth magnetic head 129 composed of two heads A and B is recorded by the head A, and on B channel tracks B0, B1 and B2, a second signal having a different DSV cycle from that of the first signal, coded in the same manner as described above, is recorded by the head B. In this case, the distance L between the two heads A and B is 400 to 1000 µm, and the head A precedes a distance an integral number of times as much as the pilot wavelength from the head B. In this embodiment, what is noteworthy is a 180° shift between the phases of the pilot signals of two tracks A1 and A2 on both sides of the track B1, so head B detects the error signal in order to carry out a tracking control in the reproducing mode. In recording such pilot signals, as shown in Fig. 21, when the head B is on-track in the center of the track B1, the pilot signals picked up by the head B from the two tracks A1 and A2 adjacent to the track B1 as the head B scans are zero, and, when the head B is off-track in the direction of the track A1, the phase is the same as that of the pilot signals picked up by the preceding head A, or when the head B is off-track in the direction of the track A2, the phase is reverse to that of the pilot signals picked up by the head A. Therefore, by carrying out a synchronous detection of the pilot signals picked up by the head B by using the pilot signals picked up by the head A, when the head B is on-track, zero is obtained, and when the head B is off-track in the direction of either track A1 or A2, either (+) or (-) tracking error signals can be formed. Hence, by using the thus obtained tracking error signal, the tracking control in the reproducing mode is possible in the same manner as a conventional method. In the present system, as described above, by recording the pilot signals on every other track so that the phases of the pilot signals may be inverted through 180† every recording of the pilot signal on the track, as shown in Fig. 20, when the head is on-track, the crosstalk of the pilot signals disappears, and hence the disturbance on reproducing the digital signal is removed. Then, the obtained pilot signals are recorded under the above conditions as follows. As shown in Fig. 20, for example, assuming that a track slant angle is  and a track pitch is TP, the head B picks up signals having a track step difference LT = (2TP/tan) between the recording start points of the two tracks A1 and A2 adjacent to the track B1 the head B now scans and picks up the pilot signals from the two tracks A1 and A2. Accordingly, it is necessary to control the DSV phase so that the phase of the pilot signal of the track A2 may be reverse to the phase of the pilot signal of the track A1 at the point (2TP/tan) from the recording start point. On the other hand, assuming that the relative speed of a head with respect to a tape is Vh, a wavelength λ(PILOT) of a pilot signal is exhibited as λ(PILOT) = (Vh/DSV) cycle, and the resolution of phase control becomes (360°/DSV) cycle coded block number X. In this case, the DSV cycle is, of course, the same as the aforementioned CDS control cycle. Therefore, in order to settle the phase difference of 180† between the pilot signals of the tracks A1 and A2 with reference to the head B, the phase difference Δ1 between the pilot signals due to the track step difference LT is obtained under the condition of LT > λ (PILOT)·P (P: integer) as follows. Δ1 = (LT - λ·P/λ)·360° Then, the phase control amount Δ2 for achieving the phase difference of 180° is calculated as follows. Δ2 = Δ1 - 180° On the other hand, in the present system, the resolving power of the phase control of the pilot signal is (360°/DSV) cycle coded block number X, as described above, and it is enough to shift the phase of the DSV control signal for a value of Y of which |Δ2 - (360/X)·Y| becomes the minimum. In this instance, Y is an integer satisfying Y ≦ (X/2). Next, the operation of the phase control will be described more specifically in connection with Fig. 22 in which specific values are substituted for parameters for better understanding. Now, with the comparative speed Vh = 9.4 m/sec, the coding frequency = 2.28 MHz and the DSV cycle = 10 coded block, the DSV frequency, i.e., the pilot frequency becomes 2,74 MHz/10 = 228 KHz, and the wavelength of the pilot signal λ(PILOT) = 9.4/(228 x 10 3 ) = 41.23 µm. Further, with the track pitch TP = 6.1 µm and the track slant angle  = 4.69°, the track step difference LT between the tracks A1 and A2 becomes 2.61 µm/tan4.69° = 148.71 µm. Hence, according to the above formulas, the phase difference Δ1 is calculated to obtain 218.46°, and the phase control amount Δ2 is 218.46° - 180° = 38.46°. On the other hand, the phase control resolution of the DSV control is (360°/10) block = 36°, and Y of which |Δ2 - (360/X)·Y| the minimum is 1. Accordingly, when the DSV initial phase signal of the pilot signal starts from 0 at the start of the recording of the track A1, by starting from 1 in the track A2, the pilot signals of the tracks A1 and A2 with the 180° phase difference therebetween with reference to the head B can be recorded. Then, for the track A3 to the track An, the recording of the pilot signals can be carried out by starting from a number which is obtained by adding +1 to the DSV initial phase signal value of the preceding track in the same manner as described above. Hence, as a specific circuit operation, as is apparent from Fig. 23, by counting up a counter in the initial phase adjuster circuit 131 with Y = Y+1 by the DPG pulse signal generated every one rotation of the rotary drum in synchronization with the rotation of the rotary drum, the selector 132 is switched to preset the initial phase value in the counter 126 just before the recording start. For instance, when the track A1 is recorded, 3 of 0 + 3 ( 3 is an offset value for outputting CY from the counter 126 at the count value of 7) is output from the initial phase adjuster circuit 131 to the counter 126, and, when the track A2 is recorded, 4 is output from the initial phase adjuster circuit 131 to the counter 126. Then, the counter within the initial phase adjuster circuit 131 is counted up by Y in every X/2 base every one rotation of the rotary drum in the same manner as described above. Further, every carry signal in the counting, it is required to set and reset the flip flop 125 for deciding the initial polarity of the DSV by the initial polarity set signal. After the initial phase value is loaded to the counter 126, the counter 126 is counted up by the SYCK of the code conversion rate and outputs the signal CY at the count value of 7. The signal CY is input to the flip flop 125, and the DSV control signal is inverted from 0 to 1 or from 1 to 0 by the trailing edge of the signal CY. Also, after the initial phase value is loaded into the counter 126, the selector 132 is switched together with the cycle set 133 for deciding the DSV phase so that the the signal CY may be input to the counter 126. Hence, by inputting the cycle set value by the signal CY, the counter 126 is configured as a ring counter (of 8-cycle set value) and outputs the signal CY every time the count value of 7 is reached. Accordingly, the initial phase value is decided by the initial phase adjuster circuit 131, and then the DSV control signal repeatedly inverted by the trailing edge of the signal CY is provided with a cycle of (8-cycle set value) x 2 coded block number with a 50% duty cycle. Thus, by controlling the CDS of the code word output from the encoder 124 by using the obtained DSV control signal, the DSV phase with respect to the track position can be controlled at will, and the pilot signals having a 180° phase difference can be recorded every other track so that phases of the pilot signals may be inverted through 180° every recording of the pilot signal on the track, as shown in Fig. 20. In Fig. 24, there is shown another embodiment of a pilot signal formation circuit and a tracking error detecting circuit for use in producing a tracking error according to the present invention. In this embodiment, an encoder 124, a P/S converter 127, a magnetic head 129, a recording medium 130 and a rotary drum 134 are the same as those shown in Fig. 14 and the explanation of the same is omitted for brevity. Further, a turnover switch 108, a low pass filter 113, an amplifier 116, a divider circuit 117, a pair of band pass filters 118a and 118b, a pair of envelope detector circuits 119a and 119b and a differential amplifier 120 are the same as those shown in Fig. 4 and the explanation of the same is omitted for brevity. As shown in Fig. 24, a pair of first and second counters 136A and 136B count up the SYCK and output respective first and second DSV clock signals having different frequencies such as one by an even number of the SYCK and a duty ratio of 50%. A selector 137 selects one of the first and second DSV clock signals output from the first and second counters 136A and 136B according to the drum PG signal. The operation of the system shown in Fig. 24 will now be described in detail in connection with Figs. 15, 19, 24, 25 and 26. In the recording mode, the first counter 136A counts up the SYCK and outputs the first DSV control signal, and the second counter 136B also outputs the second DSV control signal having a different frequency from that of the first DSV control signal in the same manner as the first counter 136A. Then, the selector 137 selects one of the first and second DSV control signals according to the drum PG signal and outputs the selected DSV control signal to the encoder 124. In the encoder 124, in accordance with the first or second DSV control signal output from the selector 137, 12 bits of parallel input digital signal are converted into 15 bits of parallel code word selected from one of a pair of code word groups corresponding to the CDS of ±1, as shown in Fig. 15. By controlling the CDS of the code word, a code word string having a cycle of 2i (i = integer) times as much as the code conversion cycle and the DSV = i at the end of the code word can be obtained. The obtained 15 bits of parallel code word are fed to the P/S converter 127 and converted therein into serial data by a clock fcH having one fifteenth the cycle of the SYCK, and the serial data is sent to the magnetic head 129 through the switch 108 and a recording amplifier (not shown). The magnetic head 129 records the serial data on the magnetic tape 130. Fig. 25 shows the input signal, the DSV control signal and the DSV of the recorded code word when the cycle of the DSV control signal is one tenth of the SYCK, and the DSV of the code word necessarily becomes 0 every ten symbols. That is, the pilot signal having a frequency of one tenth of the SYCK can be recorded. The power spectrum of the digital signal having two-value such as 1 and 0 can be decided by the appearance of a state transition probability graph. For example, in case of the random digital signal in M system, the power spectrum is approximately flat in a frequency range from DC to a carrier clock signal frequency. On the other hand, like the present invention, in the code string in which the DSV is regularly and correctly varied at a fixed cycle, in cooperation with the limited DSV, a signal having no DC component and having a spectrum resistant to DSV frequency can be obtained. Fig. 10 shows a power spectrum of the output of the P/S converter 127, that is, the recording signal obtained under the condition that the CDS control cycle of the code word is ten times as much as the code conversion cycle, and it is confirmed that the spectrum resistant to the DSV cycle (1/150 of the series data carrier frequency fcH) can be obtained. Accordingly, by recording such a signal onto the magnetic tape 130, a low frequency pilot signal can be recorded in synchronization with a digital signal in the same manner as a conventional method. Fig. 26 shows the relationship between the recording tracks 123 recorded on the magnetic tape 130 as described above and the magnetic head 129. In Fig. 26, f1 is the frequency of the pilot signal settled by the first counter 136A and f2 is the frequency of the pilot signal settled by the second counter 136B. The two frequencies f1 and f2 are different from each other. Next, in the reproducing mode, when the recording signal is reproduced from the magnetic tape 130 by the magnetic head 129, the data signal including the pilot signals is reproduced. Since the frequency of the pilot signals is very low compared with the data signal, even in an azimuth recording, the azimuth effect hardly appears, and the pilot signals of both the adjacent tracks are picked up as crosstalk. Hence, the data signal is reproduced by using one of the pair of magnetic heads 129 which records no pilot signal, and the two pilot signals are extracted by using the band pass filters 118a and 118b. Then, the extracted pilot signals are detected in the respective envelope detector circuits 119a and 119b, and the detected signals are compared in the differential amplifier 120. When the tracking is shifted to the f1 side or f2 side, a negative or positive signal as a tracking control signal 121 is output from the differential amplifier 120. In this case, the central frequencies of the band pass filters 118a and 118b are f1 and f2, respectively. As described above, according to the present invention, the pilot signals required for the tracking control can be formed by the DSV of the digital signal, and the phase of the DSV can be controlled at will. Hence, the pilot signals having a high accuracy can be obtained without causing any disturbance of the digital signal, and the whole system is carried out using digital signal processing, enabling a reduction in the cost. Further, since the pilot signal is formed and recorded as a part of the recording data signal in the modulation, the waveform deformation is small in the digital demodulation, and the large S/N ratio of the servo detection signal can be obtained. Further, the tracking pitch can be narrowed to achieve high density recording and reproducing. Further, since the pilot signals are formed in the modulation at the same time, a pilot signal generator and a mixer are not required in the recording, thus simplifying the system. According to the present invention, by controlling the polarity of a CDS according to a DSV control signal by using only code words corresponding to the CDS of ±1, pilot signals of the DSV cycle are synchronized with digital data in a low frequency range where the power spectrum of the digital data is rapidly damped. Further, by recording a digitally-modulated signal including pilot signals having two different frequencies, by using only code words corresponding to CDS ±1, the pilot signals of the DSV cycle are synchronised with digital data in the low frequency range where the power spectrum of the digital data is rapidly damped, to obtain a drop in the data error rate due to the pilot signals in the reproduced signal. Although the present invention has been described in its preferred embodiments with reference to the accompanying drawings, it will be readily understood that the present invention is not restricted to the preferred embodiments and that various changes and modifications can be made by those skilled in the art without departing from the scope of the present invention as defined in the claims.

Claims: A method of encoding data for storage on a magnetic storage medium comprising: providing data arranged in data words of m bits; developing first and second code words of n bits from each said data word of m bits, n being larger than m, said first and second code words differing by the most significant bit thereof and the number of "0" bits arranged between each bit "1" and the next bit "1" being at most 4 in a code string of each code word; allowing a first and a second n-bit code word having respectively a CDS (code word digital sum) of +1 and -1 or having respectively a CDS of -1 and +1 to correspond to each m bit data word; providing a DSV (digital sum variation) control signal representative of the desired change in DSV; and selecting one of said first and second code words having a known CDS based on the provided DSV control signal to make the DSV of said code word string approach the desired DSV; characterised in that: the first code words are developed by using code words of n bits whose most significant bit is "0" and whose CDS is either +1 or -1; and the second code words are developed by changing the most significant bit of the first code word to "1". The method of claim 1, wherein m is 12 and n is 15. The method of claim 1 or 2, wherein the minimum number of "0" bits arranged between one bit "1" and the next bit "1" is 0 in the code string of each code word. The method of claim 1, 2 or 3, wherein the number of bit "0" is restricted to at most 2 in an MSB (most significant bit) side and at most 3 in a LSD (least significant bit) side in the code string of each code word. A pilot signal formation method for obtaining a tracking error signal in a magnetic recording and reproducing apparatus in which digital signals are recorded or reproduced onto or from a magnetic medium by using a rotary magnetic head device mounted on a rotary drum, comprising encoding the digital signals in accordance with the method of any one of claims 1 to 4 and controlling a DSV (digital sum variation) of a string of digital data by using selected one of the two code strings having respectively a CDS of +1 and -1 according to a DSV control signal, an initial phase of the DSV control signal being preset by a signal synchronised with a drum PG signal for controlling the phase of the drum to form a pilot signal synchronised with the digital data. The method of claim 5, wherein m is 12 and n is 15. A pilot signal formation method for obtaining a tracking error signal in a magnetic recording and reproducing apparatus in which digital signals are recorded or reproduced onto or from a magnetic medium by using a rotary magnetic head device mounted on a rotary drum, comprising encoding the digital signals in accordance with the method of any one of claims 1 to 5, and forming two kinds of DSV (digital sum variation) control signals by counting a code conversion cycle (SYCK), and selecting one of them by using a drum PG signal (DPG) for controlling the phase of the drum; and setting the DSV to zero at the end of each cycle of a predetermined number of the code words by using the selected DSV control signal to select one of the two code strings having respectively a CDS of +1 and -1 to form two kinds of pilot signals of differing frequency which are alternately selected every recording track. The method of claim 7, wherein m is 12 and n is 15.

Inventors: IDO KIHEI, OHTA MASAYUKI, IDO, KIHEI, OHTA, MASAYUKI, Ido, Kihei, c/o MITSUBISHI DENKI K. K., Ohta, Masayuki, c/o MITSUBISHI DENKI K. K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1991
Main classification: G11B5
IPC codes: G11B15, G11B20, G11B5, G06F13