Synchronization circuit for ATM cells

Abstract: A synchronization circuit for ATM cells transferred in an ATM communication system, wherein the synchronization circuit receives and holds in a bit serial manner the input bit trains constituting the received ATM cells by a shift register unit, performs a CRC operation in a bit serial manner on the held input bit trains by a continuous CRC arithmetic unit in accordance with a simplified CRC operation process different from the usual CRC operation process, and performs the necessary synchronization control upon receiving the CRC arithmetic operation result at a synchronization control unit, thereby enabling CRC arithmetic operations to be performed continuously and by simple hardware on the headers in the ATM cells.

Description: The present invention relates to a synchronization circuit for receiving a fixed bit length cell including a m-bit length header with CRC code and payload, comprising, a shift register unit for receiving an input bit stream constituting the fixed length cell stream and for temporarily storing the input bit stream, a unit for performing CRC arithmetic over the input bit stream and for outputting a CRC arithmetic result, and a synchronization detector for detecting synchronization of an input bit stream, the shift register unit, having at least an m-bit-stage for storing consecutive m bits, being arranged to shift a received bit of the input bit stream from the first stage to the m-th stage, and the synchronization detector being arranged to receive the CRC arithmetic result from the arithmetic unit and to identify the m-bit length header of the fixed length cell in case the received arithmetic result shows a prescribed value. Such a circuit is known from US-A-3 336 467. The invention is particularly concerned with a synchronization circuit in an asynchronous transfer mode (ATM) communication system for synchronization of ATM cells connected on the lines in the system, that is, cell synchronization. At the present time, the CCITT is proposing ATM communications suitable for broad band ISDN's etc., that is, data transfer by an asynchronous transfer mode, and is pressing forward with standardization of such systems. One proposal is for use of a full ATM for a layer 1. If full ATM is used for the layer 1 in accordance with that proposal, technology would become necessary for extracting each and every ATM cell, the units of data transferred by the ATM communications network., That is, it would be necessary to establish cell synchronization and detect the positions of the cells (extraction of the cells). To extract cells in this way, cyclic redundancy check (CRC) arithmetic operations are said to be extremely effective. That is, the CRC arithmetic operation is performed on the header of a cell, the cells are detected when the results of the CRC arithmetic operation become fixed values, and cell synchronization is performed. In this case, even detection of errors of the cell header itself can naturally be performed by the inherent CRC function. Note that even when an error is included in a cell, cell synchronization can be sufficiently ensured by so-called front protection and rear protection. Usually, ATM cells are comprised of the above header and a payload for transmitting the inherent information. The header also includes a field known as a header error control (HEC). The result of the CRC arithmetic operation are written into this HEC. The present invention relates to a synchronization circuit which writes, at the transmission side of the ATM cell, the result of the CRC arithmetic operation on the header in the HEC as a cell synchronization establishment signal and detects, at the reception side of the ATM cell, the coincidence of the results of the CRC arithmetic operation on the header of the ATM cell received and the result of the CRC arithmetic operation written at the transmission side in the HEC of the ATM cell received so as to detect if cell synchronization has been achieved and outputs a synchronization detection signal. A detailed explanation will be made later of several conventional CRC arithmetic units referring to the attached figures. Here, in summary, however, conventional CRC arithmetic units basically are constructed to receive input bit trains having definite time series, perform CRC arithmetic operations on the trains, and obtain a CRC arithmetic operation result. On the other hand, in the ATM transmission art, a synchronization circuit of the full ATM transmission system does not cover such input bit trains having definite time series, but cover input bit trains having indefinite time series (ATM cell groups), so it is necessary to shift the input bit trains one bit at a time to continuously obtain CRC arithmetic operation results C out . If a conventional CRC arithmetic unit is assembled and designed to perform a CRC arithmetic operation on such input bit trains having indefinite time series (ATM cell groups), the assembled CRC arithmetic operation circuit would enlarge the size of the apparatus (hardware) . Further, if the CRC arithmetic operation is performed on ultrahigh speed data, the problem will arise of an increased processing delay. In addition to the prior art cited in the opening paragraph of the specification, reference is made to IEEE Global Telecommunications Conference, vol. 1, 28.11.1988, Hollywood (US), p. 394-402, Hsing et all: "On cell size and header control of asynchronous transfer mode (ATM)", which is concerned with the use of ATM in B-ISDN services. It examines the need for CRC implementation and concludes that it can correct a single bit error in the cell header, reducing the risk of misdirection of cells. Additionally, reference is made to Electronics Letters, vol. 19, no. 3, 3rd February 1983, Hitchin (GB), pages 109-110, Ely and all: "High-speed decoding technique for slip detection in data transmission systems using modified cyclic block codes", which discloses a synchronisation circuit for receiving a fixed bit length cell including a m-bit length head with CRC code and payload, comprising, a shift register unit for receiving an input bit stream constituting the fixed length cell stream and for temporarily storing the input bit stream, an arithmetic unit for performing CRC arithmetic over the input bit stream and for outputting a CRC arithmetic result, and a synchronization detector for detecting synchronization of an input bit stream. The present invention, in view of the above-mentioned problems, has as its object the provision of a synchronization circuit provided with a CRC arithmetic unit which, in at least some embodiments thereof, can obtain continuous CRC arithmetic operation results from input bit trains comprised of indefinite time series without increasing the processing delay and without increasing the size of the apparatus even in the case of ultrahigh speed data of several 100 Mb/s or more. The invention relates to a communication system as defined in the opening paragraph and is characterised, according to one aspect of the invention, in that said unit for performing CRC arithmetic over the input bit stream and for outputting said CRC arithmetic result is an arithmetic unit comprising, a first CRC arithmetic unit arranged to deem the overflow bits forced out from said shift register as the term of the m-th order to divide the term of the m-th order by a generator polynomial used for the CRC operation, and to output the remainder which is obtained as a first CRC arithmetic operation result, a second CRC arithmetic unit arranged to receive as input an input bit train divided at the input stages of the shift register, to deem the bit appearing at the divided input bit train side as the term of the 0-th order, and to output as the second CRC arithmetic operation result the term of the 0-th order plus the remainder obtained by dividing the CRC arithmetic operation result obtained just before by the said generator polynomial, and a subtraction unit arranged to obtain the difference between said first CRC arithmetic operation result and said second CRC arithmetic operation result, said arithmetic unit being arranged to obtain the said CRC arithmetic operation result in a time series manner from said difference obtained by said subtraction unit and to output it to the said synchronization detector. According to the invention from a second aspect, there is provided a synchronization circuit as claimed in Claim 6. According to the invention from a third aspect, there is provided a synchronization circuit as claimed in Claim 11. According to the invention from a fourth aspect, there is provided a synchronization circuit as claimed in Claim 13. The present invention will be better understood from the following description of preferred embodiments given by way of example and with reference to the accompanying drawings, wherein: Fig. 1 is a view of a first example of a conventional CRC arithmetic unit; Fig. 2 is a view of a second example of a conventional CRC arithmetic unit; Fig. 3 is a view of an example of an improvement of the first example of the conventional CRC arithmetic unit; Fig. 4 is a view of an input bit train having a definite time series; Fig. 5 is a view of an input bit train having an indefinite time series; Fig. 6 is a view of a first example of a synchronization circuit handling input bit trains having indefinite time series; Fig. 7 is a view of a second example of a synchronization circuit handling input bit trains having indefinite time series; Fig. 8 is a block diagram of the principle of the synchronization circuit according to the present invention; Fig. 9 is a view of the general format of an ATM cell to which the present invention is applied; Fig. 10 is a view of a first embodiment of the present invention; Fig. 11 is a view of an example of realization of the first embodiment; Fig. 12 is a view of a second embodiment according to the present invention; Fig. 13 is a view of an example of realization of the second embodiment; Fig. 14 is a view showing a first more detailed example of realization of the first embodiment; Fig. 15 is a view showing a second more detailed example of realization of the first embodiment; Fig. 16 is a view showing a third more detailed example of realization of the first embodiment; Fig. 17 is a view showing a first more detailed example of realization of the second embodiment; Fig. 18 is a view showing a second more detailed example of realization of the second embodiment; Fig. 19 is a view showing a third more detailed example of realization of the second embodiment; Fig. 20 is a view of a third embodiment according to the present invention; Fig. 21 is a view of an example of realization of the third embodiment; Fig. 22 is a view of the bit pattern for constituting the wired logic unit of Fig. 21; Fig. 23 is a view of a fourth embodiment according to the present invention; Fig. 24 is a view of the general format of the ATM cell used for explaining the fourth embodiment; Fig. 25 is a view of an example of realization of the fourth embodiment; Fig. 26 is a timing chart of signals appearing at key portions of Fig. 25; Fig. 27 is a view of a detailed example of a remainder arithmetic unit; Fig. 28 is a view of the bit pattern for constituting the portion corresponding to the bit output D0 in the wired logic unit of Fig. 27; Fig. 29 is a view of the bit pattern for constituting the portion corresponding to the bit output D5 in the wired logic unit of Fig. 27; Fig. 30 is a view of the bit pattern for constituting the portion corresponding to the immediately preceding CRC arithmetic operation result C n-1 in the wired logic unit of Fig. 27; Fig. 31 is a block diagram of the principle of a synchronization circuit including a reset means; Fig. 32 is a view of an example of application of the reset means to the synchronization circuit of Fig. 14; Fig. 33 is a view of an example of a synchronization control unit 23 in Fig. 32; Fig. 34 is e timing chart showing the reset signal in Fig. 33; Fig. 35 is a view of an example of incorporation of the reset means in the circuit of Fig. 25; Fig. 36 is a timing chart of signals appearing at key portions of Fig. 35; Fig. 37 is a view of a specific example of a header error correction means; Fig. 38 is a timing chart of signals appearing at key portions of Fig. 37; Fig. 39 is a view of an example of an S -1 arithmetic unit in Fig. 37; Fig. 40 is a view of the bit pattern for constituting the S -1 arithmetic unit of Fig. 39; Fig. 41 is a view of one example of the S 1 arithmetic unit in Fig. 37; Fig. 42 is a view of the bit pattern for constituting the Si arithmetic unit in Fig. 41; Fig. 43 is a view of an example of the bit correction unit of Fig. 37; Fig. 44 is a timing chart of signals appearing at key portions of Fig. 43; Fig. 45 is a block diagram of the principle of a synchronization circuit including a logic inversion means; and Fig. 46 is a view of an example of a logic inversion means. Before describing the embodiments of the present invention, the related art and the disadvantageous therein will be described with reference to the related figures. First, an explanation will be made of the conventional CRC arithmetic unit used for the previously mentioned CRC arithmetic operations. Figure 1 is a view of a first example of a conventional CRC arithmetic unit. The first conventional example (Fig. 1) is of a type which reads out the CRC arithmetic operation results by a table and includes a ROM 11 storing the table, that is, a ROM table. All CRC arithmetic operation results C out for the bit trains B in of the input m number of bits are stored in advance in the ROM table. The input bit trains B in are considered as addresses of the ROM 11 and the data read out at this time is the CRC arithmetic operation result sought. Figure 2 is a view of a second example of a conventional CRC arithmetic unit. The second conventional example (Fig. 2) is of a so-called shift register type and includes serially connected shift registers 12 and exclusive OR gates (EX-OR) 13 inserted between the shift registers. The exclusive OR gates 13 have connectors 14 connected to them. The connectors 14 connect or do not connect (truth value set to "0") the CRC arithmetic operation results C out ' in accordance with the coefficients of each order of the general polynomials used in the CRC arithmetic operation ("1" or "0"). Subtraction by the EX-OR 13 is not performed when the coefficient is "0". Therefore, at the initial state, the values of all shift registers 12 are cleared to "0", then bit trains are successively input from the left side of the figure. The values of all shift registers 12 (χ 0 , χ 1 ... χ n-1 ) when the final bit is input to the shift register 12 (χ 0 ) at the left side show the CRC arithmetic operation result sought. Therefore, the values of χ o to χ n-1 are read out at that point of time and the arranged value C out is the value sought. Figure 3 is a view of an example of an improvement of the first example of the conventional CRC arithmetic unit. The improved version of the first example of the conventional CRC arithmetic unit is a type which reads out the CRC arithmetic operation result and is comprised of a combination of a plurality of ROM tables and a plurality of EX-OR logic gates, with a plurality of ROM's 11 and a plurality of exclusive OR gates (EX-OR) 13 being connected in parallel as illustrated. The contents of these ROM's 11 differ, however, so the ROM's are referred to as the ROM 1, ROM 2···. For example, the ROM 1 contains arithmetic operation results of "XXX···X 000···0" (XXX···X being the α1 bit and 000···0 being the m-α 1 bit), the ROM 2 contains the arithmetic operation result of "XXX···X 0000" (XXX···X being the α 2 bit and 000···0 being the m-α 1 -α 2 bit). The bit train B in of the input m number of bits is divided into suitable numbers of bits (shown by α 1 , α 2 ···α p , for example, each comprised of five bits). The CRC arithmetic operation result read out from the corresponding ROM 11 (each being of 1 number of bits) are input to the EX-OR's 13 as illustrated. The CRC arithmetic operation result C out sought is obtained from the final stage EX-OR 13. Note that when the number of bits of the remaining α p+1 bits is smaller than the number of bits of the generator polynomial, α p+1 is input to the final stage EX-OR 13 as is as the remainder. According to this improved example, even if the number of bits m increases, the address space sought in the ROM 11 does not increase exponentially as in the first conventional example (Fig. 1). Further, compared with the above-mentioned second conventional example, since the CRC arithmetic operation processing is parallel processing, there is the advantage that a high speed is not required in the logic devices (ROM 1 and EX-OR 13). The examples of the CRC arithmetic units given above are convenient for performing CRC arithmetic operations on segmented bit trains formed by dividing a continuous bit train into certain bit lengths. That is, they are suitable for CRC arithmetic operations on input bit trains having definite time series. Figure 4 is a view of an input bit train having a definite time series. In this figure, for example, a bit train B in divided into lengths of m bits is shown. It shows in particular the q-th segmented bit train and the q+1-st segmented bit train. Figure 5 is a view of an input bit train having an indefinite time series. The figure shows the state of shifting the object of the CRC arithmetic operation one bit at a time. That is, the extraction of a cell at the full ATM mentioned above is performed by successively shifting the input bit train B in by a bit and executing a CRC arithmetic operation each time. The figure shows the input bit train B in covered by the q-th, q+1-st, and q+2-nd CRC arithmetic operations. Figure 6 is a view of a first example of a synchronization circuit handling input bit trains having indefinite time series. Figure 7 is a view of a second example of a synchronization circuit handling input bit trains having indefinite time series. Continuously sought CRC arithmetic operation results C out are obtained from these circuits. Note that C p , C p+1 ··· in Fig. 7 are issued at respectively inherent timings and all form the C out . The first example of the circuit (Fig. 6) corresponds to one based on the improvement of the first conventional example mentioned earlier (Fig. 3) and includes a multiple stage shift register 12 and a CRC arthmitic unit 16. Th CRC arithmetic unit 16 is basically the same in circuit construction as the ones shown in Fig. 1 and Fig. 3. The second example of the circuit (Fig. 7) includes a number of CRC arithmetic units 17 provided in parallel and a control apparatus 18 for controlling the same. The arithmetic units 17 are basically the same in construction as the fore-mentioned second conventional example (Fig. 2). However, when the first conventional example (Fig. 1) is used, an increase in the number of bits m is accompanied by an exponential increase in the address space in the ROM 11 and the problem occurs of a large size of the hardware. When the improvement (Fig. 3) is used, EX-OR's 13 are connected to numerous stages and the operating speed of the layer 1 of the ATM is 620 Mb/s or 155 Mb/s, so the gate (EX-OR) delay during the processing becomes a problem. On the other hand, the second conventional example (Fig. 2) is constructed so that the results appear at the point of time when the input of m bits has ended, so the second example of the circuit (Fig. 7) requires a plurality of CRC arithmetic units 17, resulting in the problems of an increased size of hardware and the need for the control apparatus 18. Below, an explanation will be given on the synchronization circuit of the present invention, which can resolve the above-mentioned problems. Figure 8 is a block diagram of the principle of the synchronization circuit according to the present invention. In the figure, the synchronization circuit 20 according to the present invention includes a shift register unit 12, a continuous CRC arithmetic unit 22, and a synchronization control unit 23. The shift register unit 21 receives and holds in a bit serial fashion the input bit train B in constituting the ATM cell (Fig. 9) supplied for the data transmission. The continuous CRC arithmetic unit 22 performs CRC arithmetic operations in accordance with a modified CRC arithmetic operation process comprised of the usual CRC arithmetic operation process modified to reduce the amount of operations. The synchronization control unit 23 receives as input the CRC arithmetic operation result C out from the continuous CRC arithmetic unit 22, inserts, at the transmission side of the ATM cell, the CRC arithmetic operation result C out as the synchronization establishment signal S e in the ATM cell and transmits the same and, at the reception side of the ATM cell, outputs a synchronization detection signal S d when the CRC arithmetic operation result C out sent from the transmission side and the CRC arithmetic operation result C out obtained by operations of the continuous CRC arithmetic unit 22 at the reception side coincide. Figure 9 is a view of the general format of an ATM cell to which the present invention is applied. In the figure, the 1, 2, 3··· 8 at the top show the bit positions from the LSB (1) to the MSB (8), and the 1, 2, 3··· 53 at the right side are octets showing the divisions in the ATM cell (hereinafter simply referred to as "cell"). The cell is divided into a header and a payload (data in the cell). VPI (virtual path identifier) and VCI (virtual circuit identifier) show destinations of the cell. CLP is the cell loss priority. Among these, VPI1 is part of the VPI at NNI and includes information for cell conflict control, known as GFC, when UNI. The previously mentioned HEC is the portion for monitoring the header as a whole. The cell of the structure shown in Fig. 9 continuously flows along the transmission path of the ATM communication network in the order of the first octet MSB -> LSB and second octet MSB -> LSB. The HEC covers from the first octet to the fourth octet. If a CRC arithmetic operation including the HEC is performed, the CRC arithmetic operation results C out should be all "0" if the cell is normal. Further, the generator polynomial used is, for example, G = χ 8 + χ 2 + χ 1 + χ 0 This all "0" state is detected and cell synchronization continuously secured. The usual CRC arithmetic operation process, mentioned earlier, is as follows: For an input bit train B in of a certain time series: ···a n , a n+1 , a n+2 ···a n+m+1 , a n+m , a n+m+1 , a n+m+2 ··· if the CRC arithmetic operation results from a n to a n+m-1 are C n , and the generator polynomial used for the CRC arithmetic operation is for example the above-mentioned G, these can be expressed as C n = R[(a n χ m-1 +···+a n+m χ 1 +a n+m-1 χ 0 )/G] F n = a n χ m-1 +···+a n+m χ 1 +a n+m-1 χ 0 = Q n G+C n (Q n is a quotient) Here, R(f/g) is the function for finding the remainder of f/g. Further, the operation is a modulo 2 operation, which is mathematically expressed as R(f/g)=fmod(g). Usually, the amount of operations required for the above function R (f/g) is tremendous, therefore the hardware required for the CRC arithmetic operation becomes large in size and the above-mentioned problem occurs. The present invention greatly reduces the amount of the operations by the shift register unit 21 and the continuous CRC arithmetic unit 22. Figure 10 is a view of a first embodiment of the present invention. In the figure, the first CRC arithmetic unit 31 deems the overflow bit (B1) forced out from the shift register unit 21 to be a term of the m-th order, divides this term of the m-th order by the generator polynomial used for the CRC arithmetic operation, and deems the remainder to be the first CRC arithmetic operation result C1. The second CRC arithmetic unit 32 deems the bit appearing at the second bit train B2 side at the same time as the overflow bit B1 is forced out to be the term of the 0-th order, adds the 0-th order term and the remainder after dividing the immediately preceding CRC arithmetic operation result C out by the generator polynomial G, and uses the value as the second CRC arithmetic operation result C2. The difference between the C1 and C2 is then taken by the subtraction unit 33 and is used as the CRC arithmetic operation result C out sought. In the above first embodiment, the continuous CRC arithmetic unit 22 was formed based on the point expressed by the following equation: Referring once again to the above-mentioned equation (2) and equation (3), first the CRC arithmetic operation result C n+1 obtained after shifting the C n in equation (2) by one bit is C n+1 = R[F n+1 /G] F n+1 is the object of the CRC arithmetic operation shifted one bit from F n , so C n+1 = R [(F n χ-a n χ m +a n+m χ 0 )/G] =R [(Q n G+C n )χ-a n χ m +a n+m χ 0 /G] Breaking this down, C n+1 = R [(Q n Gχ)/G]+R[(C n χ-a n χ m +a n+m χ 0 )/G] The first term is the remainder 0, so this is deleted and C n+1 = R[(C n χ-a n χ m +a n+m χ 0 )/G] Breaking this down further, C n+1 = R[(C n χ)/G]-R[(a n χ m )/G]+R[(a n+m χ 0 )/G] The C n in the operator of the first term corresponds to the value from the feedback line of Fig. 10. The operation of the second term relates to the arithmetic unit 31 and the operation of the third term relates to the arithmetic unit 32. Note that the third term is of a lower order than the generator polynomial G and in actuality is in itself immediately the remainder, so the following expression is possible: C n+1 = R[(C n χ)/G]-R[(a n χ m )/G]+a n+m χ 0 Equation (7) means that to find C n+1 , one may perform a CRC arithmetic operation on C n χ-a n χ m +a n+m χ 0 . Further, equation (9) means that to find C n+1 , one may [1] perform a CRC arithmetic operation on C n χ, [2] subtract the results of the CRC arithmetic operation on a n χ m , and [3] add a n+m χ 0 . Here, [1] is possible even in the first conventional example (Fig. 1) since the number of bits is small and further, since continuous processing is possible, is possible in the second conventional example (Fig. 2) as well. [2] gives figures which are known in advance since when a n is "0", the operation results are all "0" and when a n is "1",the operation results are R=[ χ m /G] [3] indicates if the results are inverted at the last 1 bit in the results of [1] and [2]. If the first embodiment is more practically constructed, it becomes as shown in Fig. 11. Figure 11 is a view of an example of realization of the first embodiment. As illustrated, this includes an m-bit shift register 21, a CRC arithmetic unit 35, and a CRC memory unit 36. The operation will be explained below: i) In the initial state (state where the data bit train B in is not input to the continuous CRC arithmetic unit 22), the shift register 21 and the CRC memory unit 36 are reset to all "0". ii) In the state after the initial state, a 1 is input to the LSB of the shift register 21 and the CRC arithmetic unit 35. At this time, in the shift register 21, the data is shifted in direction from the LSB to the MSB. Further, at this time, at the same time, the CRC arithmetic operation result of the state just before (initial state), that is, the all "0" state, from the CRC memory unit 36 and the "0" from the MSB (output) of the shift register 21 are input to the CRC arithmetic unit 35. In this state, the CRC arithmetic unit 35 determines the next CRC arithmetic operation value and sets it in the CRC memory unit 36. iii) In the state after ii), a 2 is input to the LSB (input) of the shift register 21 and the CRC arithmetic unit 35. At this time, in the shift register 21, the data is shifted in the direction from the LSB to the MSB. Further, at this time, at the same time, the CRC arithmetic operation value of the state just before (above i) from the CRC memory unit 36 and the "0" from the MSB of the shift register 21 are input to the CRC arithmetic unit 35. In this state, the CRC arithmetic unit 35 determines the next CRC arithmetic operation value and sets it in the CRC memory unit 36. iv) When a m+1 is to be input, a m+1 is input to the LSB (input) of the shift register 21 and the CRC arithmetic unit 35. At this time, in the shift register 21, the data is shifted in the direction from the LSB to the MSB. Further, at this time, at the same time, the CRC arithmetic operation value of the state just before from the CRC memory unit 36 and the a 1 from the MSB of the shift register 21 are input to the CRC arithmetic unit 35. In this state, the CRC arithmetic unit 35 determines the next CRC arithmetic operation value and sets it in the CRC memory 36. v) In the usual state, C n (CRC arithmetic operation result from a n to a n+m-1 ) is stored. At this point of time, the next data a n+m is input to the LSB (input) of the shift register 21 and the CRC arithmetic unit 35. At this time, in the shift register 21, the data is shifted in the direction from the LSB to the MSB. Further, at this time, at the same time, the C n from the CRC memory unit 36 and the a n from the MSB of the shift register 21 are input to the CRC arithmetic unit 35. In this state, the CRC arithmetic unit 35 determines the next CRC arithmetic operation value C n+1 and sets it in the CRC memory unit 36. The CRC arithmetic operation of the first embodiment (Fig. 10) mentioned above may be summarized as follows: The shift register unit 21 gives a delay of a length of m bits to the input bit train B in . The first CRC arithmetic unit 31 fetches the first bit train B1 forced out from the shift register unit 21 and performs the first CRC arithmetic operation. The second CRC arithmetic unit 32 fetches the second bit train B2 divided at the input stage of the shift register unit 21 and performs the second CRC arithmetic operation. The subtraction unit 33 finds the difference between the first CRC arithmetic operation results C1 and the second CRC arithmetic operation results C2 from the first CRC arithmetic unit 31 and the second CRC arithmetic unit 32. The CRC arithmetic operation result C out is obtained from the subtraction unit 33 in a time series. The continuous CRC arithmetic unit 22 of the present invention, referring to Fig. 5, when performing a CRC arithmetic operation of the q+1-st bit train, shifts the bits at the q+1-st place and thereby matches the past bit excluded from the q-th bit train (or the bit train) and the newly entered current bit (or bit train) at the same timing, performs the CRC calculation, and sends out the difference of the CRC arithmetic operation results continuously for each bit. Figure 12 is a view of a second embodiment according to the present invention. In the figure, a third CRC arithmetic unit 41 divides the first bit train B1, which has been delayed by m bits and deemed as the m-th order term, by the generator polynomial used for the CRC arithmetic operation and deems the remainder obtained to be the third CRC arithmetic operation results C3. A fourth CRC arithmetic unit 42 divides the second bit train B2, deemed to be the same bit train as the first bit train B1 with the same bit train as the bit train stored in the shift register 21 attached to the bottom thereof, by the generator polynomial G and deems the remainder obtained to be the fourth CRC arithmetic operation results C4. That is, the third CRC arithmetic unit 41 and the fourth CRC arithmetic unit 42 perform CRC arithmetic operations on the following B1 and B2 for the bit train comprised of a n-2 , a n-1 , a n , a n+1 ··· a n+m-1 , a n+m , a n+m+1 : B1: "···a n-2 , a n 00000···0" (wherein there are m number of 0's) B2: "···a n-2 , a n , a n+1 , a n+2 ···a n+m-1 " Here, the portions "······" in the headers of the above-mentioned B1 and B2 start at the same time positions for both B1 and B2, for example, from a 0 or a 1 . The difference between C3 and C4 is obtained by the subtraction unit 43 and is used as the CRC arithmetic operation result sought. In the above-mentioned second embodiment, the continuous CRC arithmetic unit 22 was formed based on the point expressed by the following equation: In the same way as explained with regard to the first embodiment, if, for an input bit train B in of a certain time series: ···a n , a n+1 , a n+2 ···a n+m-1 , a n+m , a n+m+1 , a n+m+2 ··· The CRC arithmetic operation results from a n to a n+m-1 are C n and the generator polynomial used for the CRC arithmetic operations is G, they can be expressed by the above-mentioned equations (2) and (3). At this time, C n is expressed as C n =R[(a n χ m-1 +···+a n+m χ 1 +a n+m-1 χ 0 )/G] The equation (11) may be rewritten in the following way: C n =R[(···+a n-2 χ m+1 +a n-1 χ m +a n χ m-1 +···+a n+m χ 1 +a n+m-1 χ 0 )/G] -R[(···+a n-2 χ m+1 +a n-1 χ m )/G] The principle of derivation of this equation (12) is as follows: Consider the bit train of a t , a t+1 , ···a n-1 , a n , a n+1 , ··· a n+m , a n+m+1 divided into the following two bit trains: B1: a t , a t+1 , ··· a n-1 , 0,0,0 ··· 0 (wherein there are m number of 0's) B2: a t , a t+1 , ···a n , a n+1 , ···a n+m , a n+m+1 Equation (12) originally covered the following bit train: B0: a n , a n+1 , ···a n+m , a n+m+1 Therefore, B0 is equivalent to B2-B1. Here, the first term on the right side (R[ ······ ]} of equation (12) shows the bit train B2, while the second term (-R[ ······ ]) shows the bit train B2. Here, the header bits of the bit trains B1 and B2 are both at, so the bit trains start at the same time position. If the second embodiment is constructed more practically, the result is Fig. 13. Figure 13 is a view of an example of realization of the second embodiment. As illustrated, it includes a m-bit shift register 21, the above-mentioned third CRC arithmetic unit 41 and fourth CRC arithmetic unit 42, and an EX-OR processing unit 44. The operation will be explained below: The third CRC arithmetic unit 41 is for performing the operation of the second term of the equation (12), and the fourth CRC arithmetic unit 42 is for performing the operation of the first term of the equation (12). In modulo 2 operations, the addition and subtraction can be processed by EX-OR, so by finding the EX-OR of the operation results of the CRC arithmetic unit 41 and the CRC arithmetic unit 42 by the EX-OR processing unit 42, the target CRC arithmetic operation results C out sought can be obtained. It is possible therefore to continuously obtain CRC arithmetic operation results for input bit trains having indefinite time series while shifting by one bit at a time and the extraction of cells under the above-mentioned full ATM can be easily realized. Below, detailed examples will be given of the above-mentioned first embodiment and second embodiment. Figure 14 is a view showing a first more detailed example of realization of the first embodiment. The CRC arithmetic unit 35 of Fig. 11 is shown as a ROM 35 in this figure. Further, the ROM 35 may be replaced with the parallel connection type of Fig. 3. In the example of Fig. 14, m = 40 bits and 1 (remainder) = 8 bits. 40 = 8 bits x 5 octets. Figure 15 is a view showing a second more detailed example of realization of the first embodiment. This second detailed example was based on the second conventional example (Fig. 2) mentioned earlier. Among the first and second CRC arithmetic units 31 and 32 of Fig. 10, the former (31) is an arithmetic unit with a n and the latter (32) corresponds to the CRC arithmetic unit of Fig. 2. The arithmetic unit 31 with a n mentioned above finds the EX-OR of R[χ m /G] and the output of the shift register when a n is "1" and outputs the value of the equation (13) as it is when a n is "0". Further, the results (C n+1 ) are reloaded to the shift register 12. Note that the EX-OR gate 13 and connector 14 are as previously explained. In the example of Fig. 15, m = 40 bits and 1 = 8 bits and R[χ 40 /G]=χ 7 +χ 6 +χ 1 Further, from the above-mentioned equation (1), the "0", "1", and "2" of the connector 14 are connected while the "3","4", "5", "6", and "7" of the connector 14 (not shown in the figure) are not connected and are fixed at "0". Figure 16 is a view showing a third more detailed example of realization of the first embodiment and is based on the construction of Fig. 15 with some modifications. Of the first and second CRC arithmetic units 31 and 32 of Fig. 10, the former (31) corresponds to the CRC arithmetic unit of Fig. 9 and the latter (32) is comprised of an R(χ m /G) output unit. The R(χ m /G) output unit 32 outputs the value of the above-mentioned equation (13) when a n is "1". Therefore, D i outputs the truth value "1" in accordance with R(χ m /G) when the header of χ 1 is "1" and a n is "1". Further, reference numeral 13 is an EX-OR gate which obtains the EX-OR of the output of the shift register 12 and the corresponding output and D i of the connector 14 and outputs the result. Here, the constants are the same as in the case of the above-mentioned second detailed example (Fig. 15). Regarding D i , R[χ 40 /G] = χ 7 +χ 6 +χ 1 so D 1 , D 6 , and D 7 are "1" when a n is "1" and D 0 , D 2 , D 3 , D 4 , and D 5 are fixed at "0". Figure 17 is a view showing a first more detailed example of realization of the second embodiment. As the CRC arithmetic units 41 and 42 of Fig. 13, use is made of the construction of the ROM 35 and the CRC memory unit 36 of Fig. 14. Figure 18 is a view showing a second more detailed example of realization of the second embodiment. Use is made of a CRC arithmetic unit 45 combining the two CRC arithmetic units 41 and 42 shown in Fig. 17. Note that as the ROM 35 of Fig. 17, use is made of the ROM 35' of a 21+2 bit input and 21 bit output in Fig. 18. Figure 19 is a view showing a third more detailed example of realization of the second embodiment. As the CRC arithmetic unit 41 of Fig. 13, use is made of the construction of Fig. 16, as the CRC arithmetic unit 42 of Fig. 13, use is made of the construction of Fig. 2, and as the EX-OR processing unit 44 of Fig. 13, use is made of the R(χ m /G) output unit 46. The constants in Fig. 19 are the same as in the case explained for Fig. 16. Figure 20 is a view of a third embodiment according to the present invention. In the figure, the continuous CRC arithmetic unit 22 includes a wired logic unit 51 and a remainder arithmetic unit 52. The wired logic unit 51 receives as input the m number of bit outputs b corresponding to the bits from the m-bit shift register unit 21 and distributes the m number of bit outputs b to predetermined bit positions set in advance for each of the m bits of output in the plurality of bit positions. The remainder arithmetic unit 52 is provided with a plurality of input gates 53 corresponding to the above-mentioned plurality of bit positions, executes the addition of the above-mentioned bit outputs b input distributed to each of the input gates 53, and calculates the remainder, which is equal to the remainder which would be obtained by dividing the input bit train B in by the generator polynomial G. This is given to the synchronization control unit 23 as the CRC arithmetic operation results C out . The third embodiment was established taking note of a mathematical method. The explanation of this mathematical method would be somewhat complicated, so first the general image will be briefly explained. Assume that remainder (R) obtained by dividing the decimal number "1013" (corresponding to the input bit train B in ) by "2" (corresponding to the generator polynomial G) is usually found by the process as follows: Taking note of a certain mathematical property, however, it is possible to similarly find the remainder by adding the remainders of the digits, that is, by making 1013 = 1000 ··· 0 10 ··· 0 3 ··· 1 and adding the remainders of each digit units, 0+0+1="1" so it is possible to obtain the remainder "1". Next, a more detailed explanation will be made of the above-mentioned mathematical method. If the received code of the input bit train B in held by the m-bit shift register unit 21 is expressed as the polynomial C(χ), the following equation is obtained: C(χ)=C m-1 χ m-1 +C m-2 χ m-2 +χ m-3 +··········+C 0 χ 0 Next, C(χ) is divided by the generator polynomial G(χ). Here, the explanation will be made of the case of division by the generator polynomial of g+1 bits as the generator polynomial G(χ). If G(χ)=χ8+χ2+χ+1, g=8 (8-th order), but here the explanation will be made of the general method in the case of finding the CRC arithmetic operation result (remainder) R(χ) by performing the CRC arithmetic operation (division) by the generator polynomial of g+1(=9) bits. The operation result R(χ) at this time is expressed by: mod is a modulo 2 operation. Further, p is the order of the input bit train B in , for example, p=0 to p=39 (in case of input bit train B in of 40 bits). Here, to further develop the equation, a code train E p (χ) with a special value is introduced: E p (χ)=χ p That is, E p (χ) is a figure where only the coefficient of the term of the p-th order is 1 and the remainder are all 0 (see above-mentioned 1000 and 10). If the E p (χ) is inserted in the above equation (17), then the following is obtained: R p (χ)=E p (χ)mod(G(χ)) =χ p-3 mod(G(χ)) The R p (χ) of this equation (19) can be expressed as follows: Note that g in equation (20) is the above-mentioned g. Therefore, if equation (20) and equation (17) are inserted in equation (19), the following equation (21) is obtained: The point to be noted here is the conversion from equation (21) to equation (22). This is based on the known conversion rule that the value does not change even if the order of Σ is switched. The coefficient r j of the term of the j-th order of the remainder R(χ) found by this equation (22) may be found by calculating the equation (23): This equation (23) corresponds to finding the sum of the remainders of the digit units in the above-mentioned brief explanation (0+0+1="1"). Therefore, the number of the terms where the coefficient of the term of the p-th order (0 to 39) of the received code C(χ) is "1", that is, the term of r pj =1 (j is 0 to 7) is counted. If the result of the counting is an odd number, then r j =1, while if the result of the counting is an even number, then r j =0. This can be easily found by a parity check operation. When incorporating a wired logic unit 51 of Fig. 20 based on the above-mentioned mathematical method, the remainder R(χ) obtained by dividing each of the above-mentioned E p (χ) by the generator polynomial G(χ) is decided readily in advance, so by using this it is possible to make the wired logic unit 51 and the remainder arithmetic unit 52 extremely simple in construction and reduce the size of the hardware required. Figure 21 is a view of an example of realization of the third embodiment. In the figure, the wired logic unit 51 is made of the wiring illustrated. The input side is connected to an m-bit shift register 21 (in the figure, m=0 to m=39), each bit part being comprised of a flipflop FF. C 00 , C 01 ··· C 39 correspond to the above-mentioned C(χ). The output side of the wired logic unit 51 enters the input gates 53 of the remainder arithmetic unit 52. The input gates 53 are, for example, comprised of known parity check circuits (PC). The bits (χ 7 ,χ 6 ··· χ 0 ) output from the parity check circuits PC (for example, comprised of EX-OR gate group) become the CRC arithmetic operation results C out (corresponding to the above-mentioned R(χ)) sought. In the same way as the above-mentioned embodiment, this C out is input to the synchronization control unit 23. Since the CRC arithmetic operation results for a monomial can be found in advance by calculation, the wired logic unit 51 of Fig. 21 has its internal wiring determined by the calculation results. That is, as mentioned above, the remainder R(χ) obtained by dividing the above-mentioned E p (χ)'s one by one by the generator polynomial G(χ) is determined readily in advance, so this is used. Figure 22 is a view of the bit pattern for constituting the wired logic unit of Fig. 21. In the bit pattern diagram, the monomials E p (χ) are bit trains with just one of the 40 bits being "1" and the remainder all being "0", with the "1" bit differing in bit position. In the figure, the "1" bits are arranged in a line slanting from the top left to the bottom right. The remainders R(χ)'s obtained by dividing the values of the E p (χ)'s corresponding to χ 39 , χ 38 ··· χ 00 by the generator polynomial G(χ) become the 8-bit bit trains shown in the right column of the figure. For example, for the term of χ 39 , the remainder becomes: 00110001 For the term of χ 39 , the wiring is performed on the input gates 53 corresponding to the bit positions (3) of the "1" bits among the above-mentioned eight bits (00110001). In Fig. 14, it will be understood, wiring is performed for χ 5 and χ 0 for C 39 (illustration omitted for χ 4 ). Further, for example, for the term of χ 38 , the remainder becomes: 10011011 For the term of χ 38 , the wiring is performed on the input gates 53 corresponding to the bit positions (5) of the "1" bits among the above-mentioned eight bits (10011011). In Fig. 14, it will be understood, wiring is performed for χ 7 and χ 0 for C 38 (illustration omitted for χ 1 , χ 3 , and χ 4 ). The horizontally extending wiring group and the parity check circuits (PC) receiving the same in the wired logic unit 51 in Fig. 21 are used to perform an operation equivalent to the addition of the bit trains in the right column of Fig. 22 in the lateral direction with the bit positions (j bits) matched and to obtain the desired remainder R(χ). Figure 23 is a view of a fourth embodiment according to the present invention. In the figure, the continuous CRC arithmetic unit 22 is made of a remainder arithmetic unit 61 and a delay unit 62. Further, the shift register unit 21 is comprised of a k-stage shift register. k is a specific number which is larger than 1 and smaller than the number of bits (for example, 8) making up one octet of the ATM cell. The bit output of the first stage of the k-stage shift register and the bit output of the k-th stage form two of the three inputs used for the CRC arithmetic operation in the remainder arithmetic unit 61. The remaining one input is the output from the delay unit 62. From the remainder arithmetic unit 61 is output the CRC arithmetic operation results C out successively and continuously in accordance with the shift timing. This C out is on the one hand output to the synchronization control unit 23 in the same way as the previously mentioned embodiment and on the other hand is output to the delay unit 62. Therefore, what is given from the delay unit 62 to the input of the remainder arithmetic unit 61 is the CRC arithmetic operation result obtained just before. Therefore, the remainder arithmetic unit 61 executes the predetermined operation receiving these three inputs and produces the CRC arithmetic operation results C out . The fourth embodiment is established taking note of a certain mathematical method which will be explained below. First, see Fig. 24. Figure 24 is a view of the general format of the ATM cell used for explaining the fourth embodiment. The figure shows the ATM cell shown in Fig. 9 with the header data in bit units. The following explanation will be made in terms of these bit units. If the time series in the input bit train B in is taken out and made W, then it may be expressed as: W:······· ω n-1 ω n ω n+1 ω n+2 ω n+3 ω n+4 ω n+5 ······· ω n is a numeral series expressed by eight factors: ω n0 ω n1 ω n2 ω n3 ω n4 ω n5 ω n6 ω n7 That is, if ω n is expressed by a polynomial, the result is: ω n = ω n0 χ 7 + ω n1 χ 6 + ω n2 χ 5 + ·········· + ω n7 χ 0 Here, in the above-mentioned time series W, when five octets corresponding to the header of the ATM cell, that is, ω n + ω n+4 are taken out, the CRC arithmetic operation results C out are made C n . Further, the generator polynomial used for the CRC arithmetic operation is made G. Then, the CRC calculation results C n are expressed by C n = (F n )mod(G) that is, the remainder obtained by dividing F n by G. Here, F n is expressed by the polynomial shown in the following equation: F n = ω n χ 8x4 + ω n+1 χ 8x3 + ········· ω n+4 χ 8x0 = Q n ·G+C n (Q n is the quotient) In equation (26), ω n χ 8x4 corresponds to the first octet, ω n+1 χ 8x3 corresponds to the second octet, ··· and ω n+4 χ 8x0 corresponds to the fifth octet. Here, if a mathematical inductive method is used and consideration given to the C n+1 appearing at the timing following C n , then C n+1 can be expressed as follows: C n+1 =(F n+1 )mod(G) = (F n χ 8 -ω n χ 8x5 +ω n+5 χ 8x0 )mod(G) ={(Q n ·G+C n )χ 8 -ω n χ 8x5 +ω n+5 χ 8x0 }mod(G) =(C n χ 8 )mod(G)-(ω n χ 8x5 )mod(G)+ω n+5 χ 8x0 Here, the following six initial conditions are set for the equation (27): C 5 =0 C 4 =ω 0 C 3 =(ω 0 χ 8 +ω 1 )mod(G) C 2 =(ω 0 χ 8x2 +ω 1 χ 8 +ω 2 )mod(G) C 1 =(ω 0 χ 8x3 +ω 1 χ 8x2 +ω 2 χ 8 +ω 3 )mod(G) ω 4 =ω 3 =ω 2 =ω 1 =0 If the above initial conditions are set in the equation (27), the CRC arithmetic operation results C n sought are expressed by the following equation: C n =(C n-1 χ 8 )mod(G)-(ω n-1 χ 8x5 )mod(G)+ω n+4 χ 8x0 As clear from the final conclusion, that is, the above equation (28), the CRC arithmetic operation results C n sought can be expressed extremely simply using the three elements C n-1 , ω n-1 , and ω n+4 . These three elements, however, are coefficients of χ 8 , χ 8x5 , and χ 8x0 and occur at different times from each other, so when the remainder arithmetic unit 61 executes the arithmetic operations on the three elements, the three elements must be obtained at the same timing at the input of the remainder arithmetic unit 61. The k-stage shift register 21 and delay unit 62 shown in Fig. 23 exist for matching the above timings. Note that the three elements C n-1 , ω n-1 , and ω n+4 shown in the above-mentioned equation (28) appear at the portions shown in Fig. 23. Figure 25 is a view of an example of realization of the fourth embodiment. In the figure, the k-stage shift register 21 is comprised of a 6-stage shift register (comprised of six flipflops FF connected in tandem). The above-mentioned element ω n-1 is supplied from the first stage output receiving the input bit train B in , while the above-mentioned element ω n+4 is supplied from the sixth stage output. These are applied to the remainder arithmetic unit 61. The other element C n-1 to be input to the remainder arithmetic unit 61 is given from the delay unit 62. This may be comprised of a D-flipflop DFF as illustrated. The clock CLK defining the overall timing is, for example, a speed of 4M. The bit outputs D 0 , D 1 ···D 5 are sent out from these FF's in synchronization with this. Further, the reset signal RST is given to the reset inputs of the FF's. The reset signal RST rises at the same time as the reception of the input bit train B in (see Fig. 26) and falls when the reception of B in is completed. Figure 26 is a timing chart of signals appearing at key portions of Fig. 25. In the figure, the same references (CLK, B in ···) are given to the rows corresponding to the signals of Fig. 25. The downward facing arrow B in in the row of D 0 shows that the above-mentioned three elements (ω n-1 , ω n+4 , C n-1 ) are matched at the same time as ω 5 , ω 0 , and C 0 for the first time since being input. The CRC arithmetic operation results sought are C 1 . Next, a detailed explanation will be given of the remainder arithmetic unit 61 in Fig. 25. Figure 27 is a view of a detailed example of a remainder arithmetic unit. In the figure, the remainder arithmetic unit 61 is comprised, for example, of the illustrated wired logic unit 63, the EX-OR gate 64, and 8-bit leading wires 65 for output of the CRC arithmetic operation results. The wired logic unit 63 receives at the input side the above-mentioned three elements ω n+4 , ω n-1, and C n-1 as the bit outputs D 5 and D 0 of the 6-stage shift register 21 and the output of the delay unit 62 and is connected at the output side to eight EX-OR gates 64 (only three shown) corresponding to the eight bits. The wired logic unit 63 is assembled as shown in Fig. 27 for a similar reason as to why the wired logic unit 51 is assembled as shown in Fig. 21 in the above-mentioned third embodiment. That is, the CRC arithmetic operation results for the inputs D 5 and D 0 and C n-1 in Fig. 27 can be calculated in advance (see row R(χ) in Fig. 22), so this is used for wiring the wired logic unit 61. Figure 28 is a view of the bit pattern for constituting the portion corresponding to the bit output D 0 in the wired logic unit of Fig. 27, Fig. 29 is a view of the bit pattern for constituting the portion corresponding to the bit output D 5 in the wired logic unit of Fig. 27; and Fig. 30 is a view of the bit pattern for constituting the portion corresponding to the immediately preceding CRC arithmetic operation result C n-1 in the wired logic unit of Fig. 27. Regarding D 0 of Fig. 28, for example, the line connection corresponding to the "1" bit in the bit train of the order χ 7 becomes the connection point A of the D 0 row in Fig. 27. Further, for D 5 of Fig. 29, for example, the line connection corresponding to the "1" bit in the bit train of the order χ 41 (only the two consecutive bits on the left side shown) becomes the connection point B of the D 5 row of Fig. 27. Further, for C n-1 of Fig. 30, for example, the line connection corresponding to the "1" bit in the bit train of the order χ 14 (only the two consecutive bits of the left side and the one bit of the right side shown) becomes the connection point C of the row C n-1 of Fig. 27. After this line connection, connection is made to the corresponding inputs of the EX-OR gate 64 made into bundles of eight corresponding to the 8 bits of the C n . The EX-OR gate performs an addition function and the results of the addition are sent out as Cn to the leading wires 65 corresponding to the bits. When the synchronization circuit (20 in Fig. 8) is actually used in an ATM communication system, the synchronization circuit provided at the side receiving the ATM cells must function to provide rear protection and front protection as well. That is, the synchronization control unit (23 in Fig. 8) must include a rear protection and front protection means. Usually, rear protection is provided seven times and front protection six times. Even if cell synchronization is detected for the first time by the above-mentioned CRC arithmetic operation from the header of the ATM cells begun to be received, it is not known if that true cell synchronization is detected. Therefore, if similar cell synchronization is detected continuously seven times, it is deemed that true cell synchronization has been detected and the synchronization detection signal (S d in Fig. 8) is started to be supplied. This is what is meant by seven times of rear protection. Once cell synchronization has been established, cell synchronization is continued to be detected during the usual reception of data, but the synchronization detection signal S d is not always normally received. Cases when the S d is not received include cases where the cell synchronization is lost and S d is not obtained and cases where the synchronization detection signal should be obtained, but noise or the like causes the synchronization detection signal to be not received in actuality. In the former case, the reception of data is immediately suspended and cell synchronization must be detected again. In the latter case, however, there is no need for this. This is because the data can continue to be normally received under these conditions. Therefore, once cell synchronization has been established, it is deemed that cell synchronization has really been lost only when cell synchronization cannot be detected six successive times, in which case the supply of the synchronization detection signal S d is stopped. This is what is meant by six times of front protection. Therefore, the synchronization circuit 20 of the present invention is preferably provided with a rear protection and front protection function. Figure 31 is a block diagram of the principle of a synchronization circuit including a reset means. The synchronization circuit 20 in the figure is provided with a reset means 70 at the synchronization control unit 23 at the reception side. The reset signal R/S from the reset means 70 is applied to the shift register unit 21 and the continuous CRC arithmetic unit 22. According to the CCITT recommendations, once cell synchronization has been established, it is possible to predict the timing at which the next synchronization detection is possible, so during that period the synchronization detection operation may be suspended. In accordance with this, the rear protection function and the front protection function can be started up at cycles of 53 bytes (53 octets). In this case, the synchronization circuit of the present invention would not function with just the synchronization detection started up every 53 bytes. This is because the synchronization circuit 20 has the shift register unit 21 with the data holding function and the CRC arithmetic unit 22 (CRC memory unit 36 and delay unit 62). That is, it is necessary to reset the past data remaining in the data holding function unit. Therefore, the reset means 70 is provided. This reset means 70 is essential for performing the rear protection and front protection. A detailed example will be provided below: Figure 32 is a view of an example of application of the reset means to the synchronization circuit of Fig. 14. The operation in the figure is as follows: Here, the ROM 35 has written in it the results of calculation of the C n+1 from a n , a n+40 , and C n in advance. i) When n=-39 (initial state) The synchronization control unit 23 sends the reset signal R to the CRC arithmetic processing unit 71. This resets the internal states of the shift register 21 and the CRC memory unit 36 in the CRC arithmetic processing unit 71. ii) When n=-38 The initial data a 1 is input in the LSB of the shift register 21 and the ROM 35. At this time, at the shift register 21, the data is shifted in the direction from the LSB to the MSB (right direction in the figure). Further, at this time, simultaneously the CRC arithmetic operation result of the state just before (initial state), that is, the all "0" state, from the CRC memory unit 36 and, further, the "0" from the MSB of the shift register are input. In this state, the next CRC arithmetic operation result is read from the ROM 35 and is set in the CRC memory unit 36.At this time, data of the number of bits sufficient for performing the desired CRC arithmetic operation is not input to the CRC arithmetic processing unit 71, so the synchronization control unit 23 does nothing. iii) When -37≤n≤0 The data a n+39 is input to the LSB of the shift register 21 and the ROM 35. At this time, in the shift register, the data is shifted in the direction from the LSB to the MSB (right direction in the figure). Further, at this time, simultaneously the CRC arithmetic operation result of the state just before (initial state) from the CRC memory unit 36 and, further, the "0" from the MSB of the shift register are input. In this state, the next CRC arithmetic operation result is read from the ROM 35 and is set in the CRC memory unit 36.At this time, data of the number of bits sufficient for performing the desired CRC arithmetic operation is not input to the CRC arithmetic processing unit 71, so the synchronization control unit 23 does nothing. iv) When n=1 The data a 40 is input to the LSB of the shift register 21 and the ROM 35. At this time, in the shift register, the data is shifted in the direction from the LSB to the MSB (right direction in the figure). Further, at this time, simultaneously the CRC arithmetic operation result of the state just before (initial state) from the CRC memory unit 36 and, further, the "0" from the MSB of the shift register are input. In this state, the next CRC arithmetic operation result is read from the ROM 35 and is set in the CRC memory unit 36.Data of the number of bits sufficient for performing the desired CRC arithmetic operation is input to the CRC arithmetic processing unit 71, so the synchronization control unit 23 waits until the desired CRC arithmetic operation results become synchronized. v) When n≥2 The data a n+39 is input to the LSB of the shift register 21 and the ROM 35. At this time, in the shift register, the data is shifted in the direction from the LSB to the MSB (right direction in the figure). Further, at this time, simultaneously the CRC arithmetic operation result of the state just before (initial state) from the CRC memory unit 36 and, further, the a n-1 , from the MSB of the shift register are input. In this state, the next CRC arithmetic operation result is read from the ROM 35 and is set in the CRC memory unit 36.Data of the number of bits sufficient for performing the desired CRC arithmetic operation is input to the CRC arithmetic processing unit 71, so the synchronization control unit 23 waits until the desired CRC arithmetic operation results become synchronized. In the state after vi) and iv), the synchronization detection signal S d is output from the synchronization control unit 23 in the state where the conditions for front protection for synchronization have been met. In the state after vii) and vi), when the desired CRC arithmetic operation results are not synchronized at the desired position, the set signal is output from the synchronization control unit 23. The CRC arithmetic processing unit is set to a state waiting for the same meaning as the internal state desired in the synchronization state (shift register → all "0", CRC memory unit → all "0"). In the state of viii) and vi), when loss of synchronization is detected, a reset signal is output from the synchronization control unit 23, the synchronization detection signal disappears, and the state i) is returned to. Figure 33 is a view of an example of a synchronization control unit 23 in Fig. 32. This includes a reset means 70. Figure 34 is a timing chart showing the reset signal in Fig. 33. 424 in the figure means 53 (all octets in ATM cell) x 8 (bits) and 40 means 5 (all octets of header in ATM cell) x 8 (bits). The reset signal R/S is output cyclically as illustrated and is output to the CRC arithmetic processing unit 71 (Fig. 32). (1) Initial state The hunt processing unit 72 is in a hunting state. (2) Hunting state When the reset of the master is released, the CRC arithmetic processing unit 71 starts the CRC arithmetic operation and C n 's are successively input to the comparator unit 24.In the comparator unit 24, when C n matches the desired value, the coincidence signal is output. At this time, the signal PS showing that the pseudo synchronization has started is output from the hunt processing unit 72, and the rear protection operation is started at the rear protection unit 73. (3) Rear protection state The rear protection unit 73 which starts the rear protection operation checks that the coincidence signal is received successively seven times for each 53 bytes from the point of time when the signal PS is input. At this time, the synchronization start signal SS is output to the front protection unit 74.When seven successive coincidence signals cannot be received, the reset signals R2 and R/S are sent to the hunt processing unit 72 and the CRC arithmetic processing unit 71 and the above-mentioned state (2) is returned to. (4) Synchronization state Continuing after the above-mentioned state (3), the synchronization state exists while the coincidence signal is input to the front protection unit 74 every 53 bytes. (5) Front protection state When the coincidence signal coming every 53 bytes stops, the front protection unit 74 enters the front protection state. At this time, just the synchronization detection signal Sd is output every 53 bytes. When the coincidence signal is not input for six successive times, the front protection unit 74 outputs the reset signals R1 and R/S and the above-mentioned state (1) is returned to. When the coincidence signal is once again input in the 53 x i (i<6) byte, the above-mentioned state (4) is returned to. Figure 35 is a view of an example of incorporation of the reset means in the circuit of Fig. 25. The reset means 70, in brief, executes the CRC arithmetic operation on the 5 octets from the header every 53 octets (length of one ATM cell) and is essential for the rear protection and front protection. A detailed example was given in Fig. 32. The second detailed example shown in Fig. 35 has a reset means 70 built in the synchronization circuit of Fig. 25. The reset means 70 can be extremely easily realized by an AND gate 75. This is also an advantage of the synchronization circuit of Fig. 25. The AND gate 75 receives as input the above-mentioned reset signal RST and the output H of a header counter (not shown) and outputs the reset signal R/S. The reset signal R/S is applied to the sixth stage flipflop FF and the reset inputs of the flipflop forming the delay unit 62. Note that the above-mentioned header counter produces a cyclic output H synchronized with 53 octets.The waveform is shown in the row H of Fig. 36. Figure 36 is a timing chart of signals appearing at key portions of Fig. 35. As mentioned in the beginning, the CRC arithmetic operation is used not only for the detection of cell synchronization, but also for correcting errors in the header itself of the ATM cells. Therefore, the synchronization control unit 23 in the synchronization circuit 20 is provided with a header error correction means in addition to the above-mentioned reset means 70. Below, an example of a header error correction means suitable for being incorporated in the synchronization control unit 23 is shown. As mentioned above, the header error correction means enters the active state after the synchronization circuit enters the synchronization state through the above-mentioned rear protection. Strictly speaking, this is the synchronization state when there is no error in the header of the ATM cell appearing just before. Therefore, consider the definite time series ψ: ψ 0 ψ 1 ψ 2 ψ 3 ψ 4 where ψi is ψ i0 ψ i1 ψ i2 ψ i3 ψ i4 ψ i5 ψ i6 ψ i7 Expressing this by a polynomial, the time series ψ is a numerical equation expressed by: ψ i =ψ i0 χ 7 +ψ i1 χ 6 +ψ i2 χ 5 +···+ψ i7 χ 0 Here, it is considered that the CRC arithmetic operation results C aimed at are C=0. That is, C=ψmod(G)=0 However, assume that a one-bit error E enters the time series ψ. In this case, E is expressed by E=χ e (0≤e≤39) 0≤e≤39 means the range of 5 octets (5x8=40) of the header. This being so, the syndrome S (remainder) when a one-bit error E is included can be expressed by the following equation from equation (30): S=(ψ+E)mod(G) =ψmod(G)+Emod(G) =Emod(G) since ψmod(G) is 0. Therefore, it becomes possible to calculate the syndrome S for correcting the one-bit error E. Here, if 0≤e≤7 that is, if there is a one-bit error in the eight bits 0 to 7, then S=Emod(G)=E and the syndrome S coincides with the bit error E of the monomial. On the other hand, analyzing the generator polynomial G, the general generator polynomial G (=χ 8 +χ 2 +χ+ 1 ) becomes G=(χ+1)(χ 7 +χ 6 +χ 5 +χ 4 +χ 3 +χ 2 +1) so the period τ becomes τ=2 7 -1=127 Therefore, when the code length of the time series covered is deemed to be 127, if the bit train (ψ+E) of the time series ψ including the one-bit error E is cyclically replaced to the higher order side by i bits (i being a natural number less than 127), then (ψ+E) becomes (ψ+E)'. Here, (ψ+E)' can be rewritten to the following equation: (ψ+E)'=[χ i (ψ+E)]mod(χ 127 -1) =(χ i ψ)mod(χ 127 -1)+(χ i ψ)mod(χ 127 -1) Therefore, the syndrome S' for this (ψ+E)' becomes: S'=[(χ i ψ)mod(χ 127 -1)+(χ i E)mod(χ 127 -1)]mod(G) =[(χ i E)mod(χ 127 -1)]mod(G) =(χ i E)mod(G) =χ (i+e)mod(127) mod(G) The term of (χ i ψ)mod(χ 127 -1) in the above does not include an error, so is 0. In equation (36), if the value i which gives 0≤(i+e)mod(127)≤7 is selected, the syndrome S' can be simply found. That is, S'=χ (i+e)mod(127) and error correction becomes possible. Here, as a result, it is known that S'=(χ i S)mod(G) so with respect to the syndrome S, the following is found: S'=(χ 95+8χm S)mod(G) (where m=0, 1, 2, 3, 4) This becomes: S'=χ (95+8χm+e)mod(127) (where, 0≤(95+8m+e)mod(127)≤7) and the error can be easily detected. Note that this is not applicable to a plurality of bit errors. Next, the following are found: S=C p0 S -1 =(χ 87 S)mod(G) S i =(χ 8 S i-1 )mod(G)(0≤i≤4) Note that C p0 is shown in Fig. 38. S in equation (40) shows the initial state of the data and may be illustrated as follows: Note that [1] to [5] correspond to the first octet to fifth octet of the header of the ATM cell. Further, the code length is 127 bits. The above-mentioned equation (41) means that the 87 bits of the header in the S: of the above figure are moved to the right in the bit train. As a result, the header is cyclically replaced to the higher order side as shown by the following S -1 : Next, if the first octet [1] of the header is moved to the right, the following S 0 is obtained. This S 0 has the i in the above equation (42) made i=0. S 0 =(χ 8 S -1 )mod(G) Below, similarly if another octet is moved to the right, S 1 , becomes S 1 =(χ 8 S 0 )mod(G) and can be expressed as the following S 1 : Therefore, finally the following results: a) When S=0 (or S -1 =0) -> no error. b) When S i = χ j (0≤j≤7) -> the processing of ω i(7- j) <-1+ω i(7-j) becomes necessary (bit inversion). c) When (0≤j≤4) and the condition in the previous two terms are not met -> cell disposal is indicated. Here, one of the error correction information a), b), and c) are obtained. An example of the specific constitution of the header error correction means based on the above will be explained below: Figure 37 is a view of a specific example of a header error correction means. However, this is an example of application to the synchronization circuit shown in Fig. 35. Further, Fig. 38 is a timing chart of signals appearing at key portions of Fig. 37. The example will be explained referring to these figures. First, in Fig. 37, the portion other than the bit correction unit 89 is the bit error detection unit. The bit error detection unit is comprised of the illustrated circuit elements 82 to 88. The flipflops 82, 83, 85, and 88 in the figure are mainly provided to match the timing and match with the timing of D'' and S''' at the two inputs of the bit correction unit 89. Further, the S -1 , arithmetic unit 84 and the S i arithmetic unit 87 execute the bit shift mentioned above. Figure 39 is a view of an example of the S -1 arithmetic unit in Fig. 37. Figure 40 is a view of the bit pattern for constituting the S -1 arithmetic unit of Fig. 39. Figure 41 is a view of one example of the S 1 arithmetic unit in Fig. 37. Figure 42 is a view of the bit pattern for constituting the S i arithmetic unit in Fig. 41. Next, an explanation will be made of the bit correction unit 89 of Fig. 37. Figure 43 is a view of an example of the bit correction unit of Fig. 37. Figure 44 is a timing chart of signals appearing at key portions of Fig. 43. In Fig. 43, 91 is an arithmetic circuit, 92 to 94 are flipflops, and 95 is an EX-OR gate. A header error is detected at the stage in front of the block 89 in Fig. 37. After this, the error is corrected by the bit correction unit 89 of Fig. 43 by the operation of Fig. 44. In the header error correction here, by obtaining the EX-OR E of the data when Si has a one-bit error and ω i by the EX-OR gate 95, the corrected data bit T is obtained. Here, first, consideration will be given to the arithmetic circuit 91. The arithmetic circuit 91 (i) outputs "1" when S i =0 or when S i has a one-bit error and (ii) outputs "0" when S i has two or more bits of error. The construction of the arithmetic circuit 91 will be discussed later, but here note that the corrected data bit T is obtained by resetting the D-flipflop 92 by the output R c of the circuit 91. This is because the EX-OR can be obtained only when S i =0 or S i has a one-bit error. On the other hand, looking at the RS flipflop 93, the Q output U i) becomes "1" when S i =0 or S i has a one-bit error and ii) becomes "0" when S i has two or more bits of error. Therefore, when S i includes two or more bits of error, U 4 still shows "0". At this time, the ATM cell is discarded. Note that the RS flipflop 93 is set by S1 showing the header of the ATM cell. The above-mentioned arithmetic circuit 91 will be explained in further detail below. Here, assume that the S i mentioned above is expressed by S i : s 10 s 11 s 12 s 13 s 14 s 15 s 16 s 17 i) When S i =0 R ca = S 10 ∩ s 11 ∩ s 12 ∩ s 13 ∩ s 14 ∩ s 15 ∩ s 16 ∩ s 17 becomes "1". R ca is the first result in the arithmetic circuit 91. ii) When S i has a one-bit error becomes "1". R cb is the second result in the arithmetic circuit 91. Other than the above, there are two or more bits of error. In the final analysis, the output R c of the arithmetic circuit 91 becomes the logical OR output of the above-mentioned R ca and R cb . The ATM cells are continuously sent in from the transmission side on the transmission channel. If this transmission channel is disconnected, the all "0" or all "1" data appears at the reception side. If the all "0" data appears, the CRC arithmetic operation result also becomes "0" and the reception side enters a state equivalent to one where synchronization is established. This is the pseudo synchronization detection state. Therefore, it has been proposed at the CCITT that an offset bit train be mapped at the HEC region (HEC in Fig. 9) in the header of the ATM cells at the transmission side in advance. This offset bit train would, for example, be as follows: 01010101 To deal with the case of mapping of such an offset bit train, a logic inversion means is introduced in the present invention. Figure 45 is a block diagram of the principle of a synchronization circuit including a logic inversion means. Reference numeral 100 in the figure is a logic inversion means. For "1", the bit corresponding to the CRC arithmetic operation result is inverted in logic. On the other hand, for "0", the bit corresponding to the CRC arithmetic operation result is passed with its logic as is. Showing this operation by a numerical equation, looking at the above-mentioned equation (17), R(χ)=[C(χ)+offset(χ)]mod(G(χ)) Figure 46 is a view of an example of a logic inversion means. The logic inversion means 100 is applied to the continuous CRC arithmetic unit 22 of Fig. 21 (third embodiment). The logic inversion means of Fig. 45 is comprised of a group of invertors 101. The invertor 101 is connected at the bit position corresponding to "1" in the above-mentioned offset bit train. As explained above, according to the present invention, it is possible to perform a CRC arithmetic operation continuously on the header portion of bit trains of continuously input ATM cells and to detect synchronization at a high speed. Further, the hardware for this can be extremely simply realized based on a mathematical method. Reference signs in the claims are intended for better understanding and shall nct limit the scope.

Claims: A synchronization circuit for receiving a fixed bit length cell including a m-bit length header with CRC code and payload, comprising; a shift register unit (21) for receiving an input bit stream (B in ) constituting the fixed length cell stream and for temporarily storing the input bit stream; a unit (22) for performing CRC arithmetic over the input bit stream and for outputting a CRC arithmetic result; and a synchronization detector (23) for detecting synchronization of an input bit stream; the shift register unit (21), having at least an m-bit-stage for storing consecutive m bits, being arranged to shift a received bit of the input bit stream from the first stage to the m-th stage; and the synchronization detector (23) being arranged to receive the CRC arithmetic result from the arithmetic unit (22) and to identify the m-bit length header of the fixed length cell in case the received arithmetic result shows a prescribed value; characterised in that said unit (22) for performing CRC arithmetic over the input bit stream and for outputting said CRC arithmetic result is an arithmetic unit (22) comprising: a first CRC arithmetic unit (31) arranged to deem the overflow bits forced out from said shift register as the term of the m-th order to divide the term of the m-th order by a generator polynomial used for the CRC operation, and to output the remainder which is obtained as a first CRC arithmetic operation result; a second CRC arithmetic unit (32) arranged to receive as input an input bit train divided at the input stages of the shift register, to deem the bit appearing at the divided input bit train side as the term of the 0-th order, and to output as the second CRC arithmetic operation result the term of the 0-th order plus the remainder obtained by dividing the CRC arithmetic operation result obtained just before by the said generator polynomial; and a subtraction unit (33) arranged to obtain the difference between said first CRC arithmetic operation result and said second CRC arithmetic operation result; said arithmetic unit (22) being arranged to obtain the said CRC arithmetic operation result (C out ) in a time series manner from said difference obtained by said subtraction unit (33) and to output it to the said synchronization detector (23). A synchronization circuit as claimed in claim 1, wherein: said first CRC arithmetic unit (31) and said second CRC arithmetic unit (32) comprise a single CRC arithmetic unit (35); said subtraction unit (33) comprises a CRC memory unit (36); and said CRC arithmetic unit (35) is arranged to receive as input the output of said shift register, the output appearing at the said divided input bit train side, and the CRC arithmetic operation result of just before held in said CRC memory unit, to perform the CRC operation, to hold the CRC arithmetic operation result in the said CRC memory unit, and to output the held CRC arithmetic operation result to the said CRC arithmetic unit (35) and the said synchronization detector (23). A synchronization circuit as claimed in claim 2, wherein said CRC arithmetic unit (35) comprises a read only memory (ROM) and is arranged to receive as address input the output of said shift register, the output appearing at the said divided input bit train side, and the CRC arithmetic operation result of just before held in said CRC memory unit, and to read out the CRC arithmetic operation result corresponding to the address. A synchronization circuit as claimed in claim 1, wherein: said first CRC arithmetic unit (31) comprises an arithmetic unit which is arranged to output the CRC arithmetic operation result; said second CRC arithmetic unit (32) comprises a CRC operator; said CRC operator comprises a plurality of shift registers (12) connected in series, a plurality of EX-OR gates (13) inserted between the shift registers and arranged to receive at the first stage said divided input bit train, and a connector (14) connected to said EX-OR gates and arranged to connect or not connect the output from the final stage shift register in accordance with coefficients of orders of a generator polynomial, said arithmetic unit being arranged to receive as input the output from said shift register unit (21) and the output from the shift registers in said CRC operator; the first stage EX-OR gate in said CRC operator being arranged to receive said divided input bit train; and said arithmetic unit being arranged to operate so as to obtain the EX-OR of the remainder R[χ m /G] (where G is the generator polynomial and χ m is the term of the m-th order; R[χ m /G]=χ m mod(G)) and the output of said shift registers when the output of the shift register unit is "1", to operate to output the remainder as is when it is "0", and to operate to load the output operation result in the shift registers once again. A synchronization circuit as claimed in claim 1, wherein: said first CRC arithmetic unit (31) comprises a CRC operator arranged to output a CRC arithmetic operation result, said second CRC arithmetic unit (32) comprises of an output unit arranged to output a remainder R[χ m /G] (where G is a generator polynomial and χ m is a term of an m-th order; R[χ m /G]=χ m mod(G)); said output unit is arranged to receive as input the output from the said shift register unit and to output a remainder R; and said CRC operator comprises a plurality of shift registers (12) connected in series, a plurality of EX-OR gates (13) inserted between the shift registers and arranged to receive at the first stage said divided input bit train, and a connector (14) connected to said EX-OR gates and arranged to connect or not connect the output from the final stage shift register in accordance with coefficients of orders of a generator polynomial. A synchronization circuit for receiving a fixed bit length cell including a m-bit length header with CRC code and payload, comprising; a shift register unit (21) for receiving an input bit stream (B in ) constituting the fixed length cell stream and for temporarily storing the input bit stream; a unit (22) for performing CRC arithmetic over the input bit stream and for outputting a CRC arithmetic result; and a synchronization detector (23) for detecting synchronization of an input bit stream; the shift register unit (21), having at least an m-bit-stage for storing consecutive m bits, being arranged to shift a received bit of the input bit stream from the first stage to the m-th stage; and the synchronization detector (23) being arranged to receive the CRC arithmetic result from the arithmetic unit (22) and to identify the m-bit length header of the fixed length cell in case the received arithmetic result shows a prescribed value; characterised in that said unit (22) for performing CRC arithmetic over the input bit stream and for outputting said CRC arithmetic unit result is an arithmetic unit (22) comprising: a third CRC arithmetic unit (41) which is arranged to divide the first bit train, delayed by m bits by the said shift register and deemed a term of an m-th order, by the generator polynomial used for the said CRC operation and to output the remainder obtained as the third CRC arithmetic operation result, a fourth CRC arithmetic unit (42) arranged to divide a second bit train, deemed to be the same bit train as said first bit train with the same bit train as the bit train stored in the said shift register attached to the bottom portion, by said generator polynomial and to output the remainder obtained as the fourth CRC arithmetic operation result, and a subtraction unit (43) arranged to obtain a difference between said third CRC arithmetic operation result and said fourth CRC arithmetic operation result; said arithmetic unit (22) being arranged to obtain the said CRC arithmetic operation results (C out ) in a time series manner from said difference obtained by said subtraction unit (43) and to output the same to said synchronization control unit (23). A synchronization circuit as claimed in claim 6, wherein said subtraction unit (43) comprises an EX-OR processing unit (44) which is arranged to obtain the EX-OR of the outputs from the said third and fourth CRC arithmetic units (41, 42). A synchronization circuit as claimed in claim 6, wherein: said third CRC arithmetic unit (41) comprises a first read only memory (ROM) and a CRC memory unit which is arranged to hold the output of the first ROM, said first ROM being arranged to receive the output of the said CRC memory unit and the output of the shift register unit as address input and to output the CRC arithmetic operation result corresponding to the address and said fourth CRC arithmetic unit (42) comprises a second read only memory (ROM) and a CRC memory unit which is arranged to hold the output of the second ROM, said second ROM being arranged to receive the output of the said CRC memory unit and said input bit train as address input and to output the CRC arithmetic operation result corresponding to the address. A synchronization circuit as claimed in claim 8, wherein said first read only memory and said second read only memory comprise a single read only memory which is arranged to sum up the same in one. A synchronization circuit as claimed in claim 7, wherein: said third CRC arithmetic unit (41) comprises an output unit which is arranged to receive as input the output from said shift register unit (21) and to output a remainder R[χ m /G] (where G is a generator polynomial and χ m is a term of the m-th order) ; R[χ m /G]=χ m mod(G)) and a first CRC operator; said fourth CRC arithmetic unit (42) comprises a second CRC operator which is arranged to receive said input bit train; said EX-OR processing unit (44) is realised by an output unit (46) which is arranged to output a remainder R[χ m /G]; and said first and second CRC operators respectively comprise a plurality of serially connected shift registers (12); EX-OR gates (13) inserted between the shift registers; and a connector which is connected to the EX-OR gates and is arranged to connect or not connect the output from the final stage shift register in accordance with coefficients of orders of the generator polynomial. A synchronization circuit for receiving a fixed bit length cell including a m-bit length header with CRC code and payload, comprising; a shift register unit (21) for receiving an input bit stream (B in ) constituting the fixed length cell stream and for temporarily storing the input bit stream; a unit (22) for performing CRC arithmetic over the input bit stream and for outputting a CRC arithmetic result; and a synchronization detector (23) for detecting synchronization of an input bit stream; the shift register unit (21), having at least an m-bit-stage for storing consecutive m bits, being arranged to shift a received bit of the input bit stream from the first stage to the m-th stage; and the synchronization detector (23) being arranged to receive the CRC arithmetic result from the arithmetic unit (22) and to identify the m-bit length header of the fixed length cell in case the received arithmetic result shows a prescribed value; characterised in that said unit for performing CRC arithmetic over the input bit stream and for outputting said CRC arithmetic result is a continuous CRC arithmetic unit (22) comprising: a wired logic unit (51) which is arranged to receive as input m number of bit outputs (b) from the shift register and to distribute the bit outputs (b) to predetermined bit positions set in advance for the bit outputs (b) among a plurality of bit positions and a remainder arithmetic unit (52) which is arranged to execute the addition of the bit outputs (b) distributed to each of the plurality of input gates (53) corresponding to the plurality of bit positions and input to each of the input gates (53), to perform an equivalent operation as the said CRC operation on the said input bit train (B in ), and to output said CRC arithmetic operation result (C out ) ; and said continuous CRC arithmetic unit (22) being arranged to output the said CRC arithmetic operation result (C out ) to the said synchronization detector (23). A synchronization circuit as claimed in claim 11, wherein said remainder arithmetic unit (52) comprises a parity check circuit (PC). A synchronization circuit for receiving a fixed bit length cell including a m-bit length header with CRC code and payload, comprising; a shift register unit (21) for receiving an input bit stream (B in ) constituting the fixed length cell stream and for temporarily storing the input bit stream; a unit (22) for performing CRC arithmetic over the input U bit stream and for outputting a CRC arithmetic result; and a synchronization detector (23) for detecting synchronization of an input bit stream; the shift register unit (21), having at least an m-bit-stage for storing consecutive m bits, being arranged to shift a received bit of the input bit stream from the first stage to the m-th stage; and the synchronization detector (23) being arranged to receive the CRC arithmetic result from the arithmetic unit (22) and to identify the m-bit length header of the fixed length cell in case the received arithmetic result shows a prescribed value; characterised in that said unit (22) for performing CRC arithmetic over the input bit stream and for outputting said CRC arithmetic result is an arithmetic unit (22) comprising: a remainder arithmetic unit (61) which is arranged to receive as input the first stage bit output (D 0 ) and the k-th stage bit output (D 5 ) of the k-stage shift register and the CRC arithmetic operation result (C n-1 ) obtained by the CRC operation just before and to calculate the CRC arithmetic operation result (C n ) and a delay unit (62) which is arranged to give a delay to the said CRC arithmetic operation result (C n ) output from the remainder arithmetic unit (61) and to return it as the CRC arithmetic operation result (C n-1 ) of the time when obtaining the CRC arithmetic operation result to the remainder arithmetic unit (62); said arithmetic unit (22) being arranged to divide the said CRC arithmetic operation result (C n ) output from the remainder arithmetic unit (61) and to supply it to the said synchronization detector (23). A synchronization circuit as claimed in claim 13, wherein said delay unit (62) comprises a D-flipflop and is arranged to apply a timing clock the same as the timing clock applied to the said k-stage shift register to the said D-flipflop. A synchronization circuit as claimed in claim 13, wherein: said remainder arithmetic unit (61) comprises a wired logic unit (63), a plurality of EX-OR gates (64), and leading wires (65) which are arranged to send out the said CRC arithmetic operation result; said wired logic unit comprises a first wire group which is arranged to receive the first-stage output and k-th stage output of the k-stage shift register and the output of the said delay unit (62) and a second wire group which is connected by a predetermined bit pattern to the first wire group and reaches to the input of the said EX-OR gates; and said leading wires are connected to the output of the EX-OR gates. A synchronization circuit as claimed in claim 1, wherein said synchronization control unit (23) is provided with a reset means (70), the internal states of the shift register unit (21) and arithmetic unit (22) are arranged to be reset by the reset signal (R/S) output from said reset means (70), and said reset means (70) is arranged to output said reset signal (R/S) cyclically in synchronization with the header of said ATM cells. A synchronization circuit as claimed in claim 16, wherein: said reset means (70) in said synchronization detector (23) comprises a hunt processing unit (72), a rear protection unit (73), and a front protection unit (74); said synchronization detector (23) is arranged to judge if the CRC arithmetic operation result of the input bit train coincides with the desired value; if coinciding, a coincidence signal is arranged to be given to the said hunt processing unit and a signal indicating the start of pseudo synchronization is arranged to be issued; said rear protection unit is arranged to start operation after receiving the signal; a synchronization start signal is arranged to be applied to the said front protection unit if rear protection is confirmed, and said front protection unit is arranged to issue said synchronization detection signal (S d ) and to issue said reset signal. A synchronization circuit as claimed in claim 16, wherein: said shift register unit (21) comprises a k-stage shift register (where k is a specific natural number of 1 or more which is less than the number of bits of the octets constituting the headers of the ATM cells) and said arithmetic unit (22) comprises: a remainder arithmetic unit (61) which is arranged to receive as input the first-stage bit output (D 0 ) and the k-th stage bit output (D 5 ) of the k-stage shift register and the CRC arithmetic operation result (C n-1 ) obtained by the CRC operation just before and to calculate the CRC arithmetic operation result (C n ) and a delay unit (62) which is arranged to give a delay to the said CRC arithmetic operation result (C n ) output from the remainder arithmetic unit (61) and to return it as the CRC arithmetic operation result (C n-1 ) of the time when obtaining the CRC arithmetic operation result to the remainder arithmetic unit (62) and to divide the said CRC arithmetic operation result (C n ) output from the remainder arithmetic unit (61) and to supply it to the said synchronization control unit (23), said reset means (80) comprises an AND gate 75, which AND gate is arranged to receive at one input a separate reset signal than said reset signal and to receive at the other input the output of a header counter which is arranged to count the number of arrivals of headers of ATM cells, the output of the AND gate being supplied to the final shift register stage of the k-stage shift register and the delay unit (62) comprising a D-flipflop as a clock input and said separate reset signal is a signal which is arranged to rise along with the reception of the said input bit train and to fall with the end of the reception. A synchronization circuit as claimed in claim 1, wherein said synchronization detector (23) is provided with a header error correction means (80) for correcting the bit error of a U header in an ATM cell, said header error correction means (80) comprising a portion for cyclically replacing predetermined amounts of bits in the bit train corresponding to the said header to a higher order, a portion for performing a predetermined logical operation while shifting bits successively so as to produce error correction information, and a bit correction portion for correcting one-bit errors in accordance with said error correction information. A synchronization circuit as claimed in claim 1, wherein said arithmetic unit (22) is provided with a logic inversion means (100) which is arranged to invert the logic of a predetermined plurality of bits in a bit train of said CRC arithmetic operation results (C out ), and said predetermined plurality of bits are the number of bits corresponding to the "1" bits in an offset bit train mapped in an HEC region in the header in the ATM cells in advance at the transmission side. A communication system comprising a transmitter and a receiver each having a synchronization circuit as claimed in any preceding claim.

Inventors: HYODO RYUJI, ISONO OSAMU, MIYAMOTO NAOYUKI, NISHINO TETSUO, OOMURO KATSUMI, TACHIBANA TETSUO, YONETA TSUYOSHI, HYODO, RYUJI, ISONO, OSAMU, MIYAMOTO, NAOYUKI, NISHINO, TETSUO, OOMURO, KATSUMI, TACHIBANA, TETSUO, YONETA, TSUYOSHI, NISHINO, TETSUO, YAJIMA MANSHON 303, YONETA, TSUYOSHI, FUJITSU DAI 6 SHINJO-RYO
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1991
Main classification: H04L7
IPC codes: H04L7, H04Q11, H04L12, G06F11, H03M13