Drive circuit for a display apparatus

Abstract: A drive circuit for a display apparatus having parallel signal electrodes has at least one voltage selecting circuit, a plurality of signal voltage circuits, one selection signal circuit, and one control signal circuit. The voltage selecting circuit selects one of voltages having different levels in accordance with an input digital video signal. The signal voltage circuits are respectively provided for the signal electrodes, and include two signal lines which are disposed between the voltage selecting circuit and the respective signal electrode. Each of the two signal lines is provided with a input switch, a capacitor and an output switch. The selection signal circuit generates a signal for controlling the two input switches of one of the signal voltage circuits to alternatingly receive a selected voltage from the voltage selecting circuit. The control signal circuit controls the two output switches of the one signal voltage circuit to alternatingly output the voltages toward the respective signal electrode, in an inverted manner with respect to the control of the selection signal circuit.

Description: This invention relates to a drive circuit for a display apparatus, and more particularly to a drive circuit for a display apparatus which is capable of gray-scale display by means of amplitude modulation. In this specification, a matrix type liquid crystal display apparatus will be described as a typical example of a display apparatus, but this invention can also be applied to drive circuits for other types of display apparatus such as electroluminescent (EL) display apparatus and plasma display apparatus. When driving a liquid crystal display (LCD) apparatus, since the speed of response of a liquid crystal is very slow as compared with a luminescent material used in a cathode ray tube (CRT) display apparatus, a special drive circuit is used. That is, in a drive circuit for an LCD apparatus, video signals which are sequentially sent are not immediately supplied to respective pixels, but the video signals are sampled for each of the respective pixels in one horizontal period and held for the horizontal period. The held video signals are output at the same time at the beginning of the next horizontal period, or at an appropriate point of time in the next horizontal period. After the output of video signal voltages to the respective pixels are begun, the signal voltages are held for a period of time sufficiently over the speed of response of the liquid crystal. In order to hold the signal voltages, a prior art drive circuit utilizes capacitors. Figure 16 shows a signal voltage output circuit (a source driver) for supplying drive voltages to a plurality of pixels (in this case, 120 pixels) on one scanning line selected by a scanning signal. A portion for the nth pixel of the source driver is shown in Figure 17. The portion includes an analog switch SW 1 , a sampling capacitor C SMP , an analog switch SW 2 , a holding capacitor C H , and an output buffer amplifier A . The operation of the signal voltage output in the prior art will be described with reference to the circuit diagrams of Figures 16 and 17, and also to the signal timing chart of Figure 18. Analog video signals v s to be input to the analog switches SW 1 are sequentially sampled in accordance with sampling clock signals T SMP1 - T SMP120 which correspond to the respective 120 pixels on one scanning line selected by each horizontal synchronizing signal H syn . By this sampling, the sequential instantaneous voltages V SMP1 - V SMP120 of the video signals v s are applied to the corresponding sampling capacitors C SMP . The nth sampling capacitor C SMP is charged up to the value of the video signal voltage V SMPn corresponding to the nth pixel, and holds this value. The signal voltages V SMP1 - V SMP120 which are sequentially sampled and held in one horizontal period are transferred from the sampling capacitors C SMP to the holding capacitors C H for holding outputs, in response to an output pulse OE which is supplied to all of the analog switches SW 2 at the same time. Then the signal voltages V SMP1 - V SMP120 are output to source lines O 1 - O 120 connected to the respective pixels through the buffer amplifiers A . To the drive circuit described above, analog video signals are supplied. Such a drive circuit presents the following problems (A1) and (A2) when attempts are made to increase the size or improve the resolution of a liquid crystal panel. (A1) When the charges in the sampling capacitors C SMP are transferred to the holding capacitors C H , the relationship between the voltage V H of the holding capacitor C H and the sampled voltage V SMP (the voltage of the sampling capacitor C SMP ) is represented by expression (1) as follows: V H = 1 1 + C H C SMP · V SMP Accordingly, in order that the voltage V H held by the holding capacitor C H is substantially equal to the sampled voltage V SMP , a condition of C SMP >> C H is required to be satisfied. That is, it is necessary to use the sampling capacitor C SMP of a large capacitance. However, if the capacitance of the sampling capacitor C SMP is too large, it is necessary to make the time for charging (i.e. a sampling period) longer. On the contrary, as the size of the LCD apparatus is made larger or the resolution is improved, the number of pixels corresponding to one horizontal period increases, thereby necessitating a sampling period to be shortened in reverse proportion. It can be seen that there is a limit to the increase in size or the improvement in resolution of the LCD apparatus. (A2) In the drive circuit for a matrix type display apparatus, unlike the display in a CRT, analog video signals are sampled in accordance with a clock signal and displayed in pixels arranged in a matrix. At this time, since delays of signals in the drive circuit including delays in the bus lines is unavoidable, it is extremely difficult to accurately establish the sampling position for the analog video signals. Particularly, when displaying a computer graphic image in which the relationship between video signals and pixel addresses should be precisely defined, shift in the image display position, bleeding of the image, etc., due to signal delays in the drive system and deterioration of the frequency characteristics cause significant problems. These problems which occur when using analog video signals are solved by using digital data as video signals. When video signals are supplied in the form of digital data, a drive circuit shown in Figures 19 and 20 is used, see for example EP-A-0 391 655 published on 10th October 1990. For the sake of simplicity, the video signal data is composed of 2 bits (D 0 , D 1 ). That is, video signal data have four values 0 - 3, and a signal voltage applied to each pixel is any one of four levels V 0 - V 3 . Figure 19 is a circuit diagram showing a digital source driver circuit corresponding to the analog source driver circuit shown in Figure 16. The circuit diagram of Figure 19 shows the entire source driver for supplying driving voltages to 120 pixels similar to that shown in Figure 16. Figure 20 shows a portion for the nth pixel in the circuit. The portion of the circuit comprises a D-type flip-flop (sampling memory) M SMP at a first stage and a flip-flop (holding memory) M H at a second stage which are provided for the respective bits ( D 0 , D 1 ) of the video signal data, a decoder DEC, and analog switches ASW 0 - ASW 3 each of which is provided between corresponding one of four external voltage sources V 0 - V 3 and a source line O n . For the sampling of digital video signal data, various circuits may be used other than the D-type flip-flop. The digital source driver operates as follows. The video signal data ( D 0 , D 1 ) are sampled at the rising of a sampling pulse T SMPn corresponding to the nth pixel, by the sampling memory M SMP . At the time when the sampling for one horizontal period is completed, an output pulse OE is fed to the holding memories M H . All the video signal data ( D 0 , D 1 ) held in the holding memories M H are simultaneously output to the respective decoders DEC. Each of the decoder DEC decodes the 2-bit video signal data ( D 0 , D 1 ). In accordance with the values (0 to 3), one of the analog switches ASW 0 - ASW 3 is conductive, and the corresponding one of the four external voltages V 0 - V 3 is output to the source line O n . The source driver in which digital video signals are used for sampling can solve the problems (A1) and (A2) which arise when analog video signals are used for sampling. However, this source driver still has the following problems (D1) and (D2) to be solved. (D1) With the increase in the number of bits of digital video signal data, the size of each of memory cells, decoders, etc., constituting a drive circuit is drastically enlarged. Therefore, the size of a chip and the production cost are greatly increased. (D2) When voltage sources supplied externally ( V 0 - V 3 in Figures 19 and 20) are selected by using analog switches, the selected voltage source is directly connected to a source line of the liquid crystal panel and drives the source line. Accordingly, the circuit is required to have a performance capable of sufficiently driving the heavy load, i.e. the liquid crystal panel. This causes the production cost to increase. Especially, in the case where the number of gray-scale levels for image display is increased so that the number of bits of video signal data is increased, in the circuit of Figure 19 (or Figure 20), the required number of external voltage sources is increased by a power of 2. For example, when the video signal data is composed of 2 bits as in the circuit of Figure 19 (or Figure 20), the number of the external voltage source levels is 2 2 = 4. For 3-bit video signal data, the number of levels is 2 3 = 8, and for 4-bit, the number of levels is 2 4 = 16. In this manner, the number of levels is drastically increased. As mentioned above, when the number of external voltage sources is drastically increased with the increase in number of data bits, and moreover, each of the external voltage sources must drive the above-mentioned heavy load, the source device for the drive circuit becomes enormous. The objective of this invention is to provide a drive circuit for a display apparatus which can solve the disadvantages (A1) and (A2) in analog sampling, and moreover eliminate the problems (D1) and (D2). This invention provides a drive circuit for driving a display apparatus as defined by claim 1. The sub-claims are directed to embodiments of the invention. According to a preferred embodiment, in a first phase, in response to a selection signal input from the selection signal generating means to each of the input switching elements, in the drive voltage supply means, a signal voltage sent from the sampling and conversion means is accepted by one signal line and held in the signal holding capacitor, while the other signal line does not accept the signal voltage. On the other hand, in response to a control signal input from the control signal generating means to one of the output switching elements, a signal is not output to a signal electrode from the one signal line which receives the signal voltage, but a signal is output to the signal electrode from the other signal line which has already received and held a signal voltage. In a second phase after completing the first phase, the operation is performed in the inverse manner with respect to the first phase. Thereafter, the first and second phases are repeated. Thus, in each drive voltage supply means, one signal line does not accept the signal voltage but outputs the signal voltage which has been received and held in the previous phase to the signal electrode. The other signal line receives a signal voltage from the sampling and conversion means and holds it, but does not output it to the signal electrode until the next phase. Figure 1 is a circuit diagram showing a source driver for an LCD apparatus in one embodiment of the invention. Figure 2 is a timing chart illustrating the operation of the source driver of the embodiment. Figure 3 is a block diagram showing the circuit of Figure 1 in a simplified manner. Figure 4 is a circuit diagram showing a source driver provided with two DA circuits in a second embodiment of the invention. Figure 5 is a timing chart illustrating the operation of the source driver of the second embodiment. Figure 6 is a timing chart illustrating the operation for a longer period of the source driver of the second embodiment. Figure 7 is a block diagram showing the circuit of Figure 4 in a simplified manner. Figure 8 is a block diagram showing a source driver provided with three DA circuits. Figure 9 is a timing chart illustrating the operation of the source driver of Figure 8. Figure 10 is block diagram showing a source driver provided with four DA circuits. Figure 11 is a timing chart of the source driver of Figure 10. Figure 12 is a circuit diagram showing the configuration of a DA circuit for 4-bit digital video signal data. Figure 13 shows equivalent circuits of the source drivers in the first and second embodiments and the prior art source driver in which a signal voltage is supplied to a source line. Figure 14 shows equivalent circuits of signal input portions in the source drivers of the prior art and the invention. Figure 15 is a plan view showing a liquid crystal panel having a drive circuit according to the invention. Figure 16 is a circuit diagram showing a drive circuit for analog video signals. Figure 17 is a circuit diagram showing a portion of one source line in the circuit of Figure 16. Figure 18 is a timing chart illustrating the operation of the drive circuit. Figure 19 is a circuit diagram showing a drive circuit in which a digital sampling circuit is provided for each source line. Figure 20 is a circuit diagram showing a portion of one source line in the drive circuit of Figure 19. Figure 1 shows a signal voltage output circuit (a source driver) for supplying signal voltages to a plurality of signal lines (source lines) in a drive circuit for a matrix type LCD apparatus in one embodiment of the invention. In this embodiment, for the sake of simplicity, 2-bit video signal data are used and the number of source lines assigned to the source driver is 120. The source driver of Figure 1 comprises a circuit (hereinafter, this circuit is referred to as "a DA circuit") provided for 120 pixels on one scanning line and for selecting one of plural external voltages in accordance with digital video signal data, and signal voltage hold circuits MO i (i is 1 to 120) provided for the respective pixels (120 pixels). In the DA circuit, the 2-bit video signal data of D 0 and D 1 is sampled by a sampling memory M SMP and input into a decoder DEC . The sampling memory M SMP includes two D-type flip-flops corresponding to the respective bits of the input data. In accordance with the video signal data ( D 0 , D 1 ) input into the decoder DEC through input terminals A and B thereof, the decoder DEC outputs an ON-control signal to one of analog switches ASW 0 - ASW 3 through the corresponding one of four output terminals Y 0 - Y 3 . External voltage sources V 0 - V 3 are connected to terminals of the analog switches ASW 0 - ASW 3 , respectively. The other terminals of the analog switches are connected to two analog switches ASWM 1 and ASWM 2 in the input portion of each of the signal voltage hold circuits MO i (i is 1 to 120). Next, the configuration of each of the signal voltage hold circuits MO i will be described. Two output lines from the DA circuit (the outputs thereof are always the same) are connected to two signal lines in a signal voltage hold circuit MO i . These same outputs are independently processed in parallel. To the two signal lines, are connected in series input analog switches ASWM 1 and ASWM 2 , and output analog switches ASWO 1 and ASWO 2 , respectively. Between each of the output-side terminals of the input analog switches ASWM 1 and ASWM 2 and the ground, a corresponding one of capacitors C M1 and C M2 for holding signal voltages is connected. The two signal lines are connected to each other to constitute one line which is then connected to a source line O i via a buffer amplifier A . The ON-control of the four analog switches ASWM 1 , ASWM 2 , ASWO 1 and ASWO 2 in each output voltage hold circuit MO i will be described. Into the control terminal of one input analog switch ASWM 1 (of a first signal line), the output CNT 1 of an AND circuit AND 1 is input. An external control signal S and a selection pulse Tm i are supplied to the inputs of the AND circuit AND 1 . Into the control terminal of the other input analog switch ASWM 2 (of a second signal line), the output CNT 2 of an AND circuit AND 2 is input. The inverted signal S INV of the control signal S and the selection pulse Tm i are supplied to the inputs of the AND circuit AND2 . The control terminal of the output analog switch ASWO 2 of the second signal line receives the external control signal S directly. The control terminal of the output analog switch ASWO 1 of the first signal line receives the inverted signal S INV of the control signal S . The operation of the source driver shown in Figure 1 will described with reference to the timing chart of Figure 2. The 2-bit digital video signal data ( D 0 , D 1 ) is fed in synchronization with the falling edge of a clock pulse CK . The sampling memory M SMP of the DA circuit latches digital video signal data Data 1 , Data 2 , Data 3 , ... corresponding to the respective pixels at the rising of the clock pulse CK , and outputs them to the decoder DEC as data DAM . The decoder DEC which receives the data Data i makes one of the outputs of the output terminals Y 0 - Y 3 effective, and the corresponding one of the analog switches ASW 0 - ASW 3 is conductive. For example, if the contents of the Data 1 is ( D 0 , D 1 ) = (1, 1), the switch ASW 3 is conductive, and the external voltage V 3 is selected to be output as the output DA out of the DA circuit. The outputs DA out of the DA circuit are supplied to the two signal lines of all the signal voltage hold circuits MO i . However, the voltage is not applied to the capacitor C M1 or C M2 and not taken into each signal voltage hold circuit MO i until the input analog switch ASWM 1 or ASWM 2 of the signal voltage hold circuit MO i is conductive. In this embodiment, the control signal S is at a high level (H) as shown in Figure 2. The inverted signal S INV of the control signal S is at a low level (L), so that the output CNT 2 of the second AND circuit AND 2 into one input of which the inverted signal S INV is input is always L . Therefore, during the H period of the control signal S (in the timing chart of Figure 2, the control signal S is kept H), the input analog switch ASWM 2 of the second signal line of each signal voltage hold circuit MO i is always non-conductive, and the output DA out of the DA circuit is not applied to the capacitor C M2 . On the other hand, the output of the first AND circuit AND 1 to which the control signal S is supplied at one input varies depending on the level of the selection pulse Tm i . In the circuit of this embodiment, as shown in Figure 2, the selection pulses Tm 1 , Tm 2 , Tm 3 , ... sequentially become H in synchronization with the rising of the clock pulse CK . The H duration of each of the selection pulses Tm 1 , Tm 2 , Tm 3 , ... is equal to one period of the clock pulse CK . When the selection pulse Tm 1 corresponding to the first signal voltage hold circuit MO 1 becomes H , the output CNT 1 of the AND circuit AND 1 also becomes H , and the input analog switch ASWM 1 of the first signal line is conductive. Thus, the output DA out of the DA circuit is applied to the capacitor C M1 to charge it. The charging time for the capacitor C M1 is the H duration of the selection pulse Tm 1 , that is, one period of the clock pulse CK . As soon as the selection pulse Tm 1 corresponding to the first signal voltage hold circuit MO 1 drops to L, the selection pulse Tm 2 corresponding to the next signal voltage hold circuit MO 2 becomes H . Thus, the capacitor C M1 of the first signal line of the second signal voltage hold circuit MO 2 is charged by the external voltage corresponding to the data Data 2 . In this way, the capacitors C M1 of the first signal line of respective signal voltage hold circuits MO i are sequentially charged by the voltages which correspond to the data Data i sampled. Since the inverted signal S INV (in this case, always L) of the control signal S is applied to the control terminal of the output analog switch ASWO 1 of the first signal line, during this period (i.e., the period for which the capacitors C M1 of the first signal line are sequentially charged by the applied signal voltages), the output analog switches ASWO 1 of all the signal voltage hold circuits MO i are non-conductive. Therefore, the voltages of the capacitors C M1 are held as they are. When the control signal S drops to L after the capacitors C M1 of the first signal line of the signal voltage hold circuits MO i corresponding to all the pixels on one scanning line are charged, the output analog switches ASWO 1 of all the signal voltage hold circuits MO i become conductive. Thus, the signal voltages held in the respective capacitors C M1 are output to the source lines O i through the buffer amplifiers A , at the same time. During the L period of the control signal S , the operation is performed in an inverse manner with respect to the operation performed during the H period of the control signal S as described above. Namely, the input analog switches ASWM 1 in all of the signal voltage hold circuits MO i are always non-conductive, and the signal voltages held in the capacitors C M1 are output to the source lines O i as described above. The input analog switches ASWM 2 of the second signal line are sequentially conductive as the selection pulses Tm i become H . Thus, external voltages corresponding to the sampled video signal data Data 1 , Data 2 , Data 3 , ... are held into the capacitors C M2 in the signal voltage hold circuits MO i , respectively. When the control signal S changes to H again after the signal voltages are held in the capacitors C M2 in all of the signal voltage hold circuits MO i , the output analog switches ASWO 2 of the second signal line become conductive at the same time. Accordingly, the signal voltages held in the capacitors C M2 are output to the respective source lines O i , so as to charge the respective pixels in the LCD apparatus by the corresponding signal voltages. As described above, in the source driver of the embodiment shown in Figure 1, the external voltage source V x is connected only to one of the two capacitors C M1 and C M2 of one signal voltage hold circuit MO i selected by a selection pulse Tm i . The equivalent circuit in this case is shown in (a) of Figure 13. The load of the external voltage V x consists of only the on-resistance R ON of the selected one input analog switch ASWM 1 (or ASWM 2 ) and the capacitance of the capacitor C M1 (or C M2 ). Since the on-resistance of the analog switch ASWM 1 (or ASWM 2 ) is very small and the capacitance of the capacitor C M1 (or C M2 ) can be made as small as 0.4 pF, the load of the external voltage source is small. By contrast, for example, in the drive circuit shown in Figure 19, the external voltage V x directly drives the pixels. Therefore, as shown in (c) of Figure 13, the resistance R s and the electric capacitance C s of the source line also are connected to the on-resistance R ON of the analog switch ASWM . Specifically, the values of the resistance R s and the capacitance C s have a large value such as approximately 30 kΩ and 120 pF, respectively. Moreover, in the circuit of Figure 19, the selected external voltage source V x is connected to a large number of pixels on one scanning line (for example, in a color display apparatus with 640 dots for one horizontal line, the maximum number of pixels is 640 x 3 (RGB) = 1920). In the drive circuit of Figure 19, since the loads of the external voltage sources V 0 - V 3 are very large, it is necessary to prepare voltage sources having a large capacity. By contrast, in the embodiment of Figure 1, since the external voltage sources V 0 - V 3 are respectively used only for applying a voltage to one capacitor C M1 (or C M2 ), the power source device is a very simple one, irrespective of the number of pixels. Furthermore, when the number of external voltage sources is drastically increased with the power of 2 by the increase of the bit number of the digital video signal data (which will be described below), the light load of the power source device will be very advantageous as a drive circuit. Moreover, in the embodiment of Figure 1, the voltage charged in the capacitor C M1 (or C M2 ) of the signal voltage hold circuit MO i as it is becomes the voltage output to the source line O i via the buffer amplifier A . In the prior art circuit shown in Figure 17, since the voltage of the sampling capacitor C SMP is transferred to the holding capacitor C H , the voltage is decreased as indicated by expression (1). In the circuit of this embodiment, since only one capacitor is used, the signal voltage can be prevented from decreasing. Accordingly, the values of the capacitors C M1 and C M2 in the circuit of the invention are not restricted unlike those in the circuit of Figure 17, and these values can be made small as long as the charge can be held for a required time period. This will be described in more detail with reference to Figure 14. The equivalent circuit for a case where the prior art capacitor C SMP is charged is shown in (a) of Figure 14, and that for another case where the capacitor C M1 in the circuit of the invention is charged is shown in (b) of Figure 14. The time periods τ SMP and τ M1 necessary to charge the capacitors C SMP and C M1 are represented as follows: τ SMP = k · R ONS x C SMP τ M1 = k · R ONM x C M1 where R ONS is the on-resistance of the analog switch SW 1 shown in Figure 17, and R ONM is the on-resistance of the input analog switch ASWM 1 shown in Figure 1. As described above, since the capacitance of the capacitor C M1 can be made sufficiently smaller than that of the capacitor C SMP in the prior art ( C M1 << C SMP ), if the charge time periods are equal ( τ SMP = τ M1 ), the on-resistance R ONM of the analog switch ASWM 1 can be sufficiently larger than the on-resistance R ONS of the analog switch SW 1 of the prior art circuit (Figure 17) ( R ONM >> R ONS ). For example, if the capacitance of the capacitor C M1 is one tenth as compared with the prior art ( C M1 = C SMP / 10), the on-resistance R ONM of the analog switch ASWM 1 can be ten times as large as in the prior art (R ONM = 10· R ONS ). It means that the analog switches ASWM 1 and ASWM 2 , and the capacitors C M1 and C M2 can be made much smaller than in the prior art. The amount of charge to be transferred via the output analog switches ASWO 1 and ASWO 2 is small, so that it is not necessary to make the on-resistances of the output analog switches ASWO 1 and ASWO 2 small. Moreover, since such elements can be made smaller in each of the signal voltage hold circuits MO i the number of which is equal to that of the source lines O i (in Figure 1, the number is 120), the reduction in element size as a whole greatly contributes to the reduction of the area, and the drive circuit LSI can be highly integrated. The size-reduced elements also contribute to the reduction of the production cost. The characteristics of capacitors C M1 (or C M2 ) may be different among the signal voltage hold circuits MO i so long as the capacitor C M1 (or C M2 ) can sufficiently hold the signal voltage, whereby the chip can be produced readily and at a low cost. Figure 3 is a block diagram showing in a simplified manner the source driver in the embodiment of Figure 1. The source driver in this embodiment is provided with one DA circuit. The output DA out is connected to two signal lines of each of 120 signal voltage hold circuits MO 1 - MO 120 . Actually, the signal voltage is sent out only to one signal voltage hold circuit MO i (in more detail, to one of the two signal lines) selected by a selection pulse Tm i . In Figure 3, digital video signal data is i-bits, and represented by a vector D i . Accordingly, the number of external voltage levels should be 2 i , and the external voltage is represented by a vector V i . A second embodiment of the invention is shown in Figure 4. The second embodiment comprises a source driver which is provided with two DA circuits DA1 and DA2 . In the embodiment, half of the 120 source lines O 1 - O 120 ((120/2) = 60) is assigned to each of the DA circuits. The two DA circuits receive digital video signal data, and output one of external voltages V 0 - V 3 as outputs DA 1out and DA 2out in accordance with the values of the received data, respectively. The first DA circuit DA1 is connected to the signal voltage hold circuits MO 2k-1 for odd source lines O 2k-1 such as the 1st and 3rd source lines. The second DA circuit DA2 is connected to the signal voltage hold circuits MO 2k for even source lines O 2k such as the 2nd and 4th source lines. In this embodiment, the clock pulse CK is not used as it is, but a pulse CKH the frequency of which is divided in half as compared with the clock pulse CK is used as a sampling pulse in a sampling memory M SMP in the first DA circuit DA1 . In a sampling memory M SMP in the second DA circuit DA2 , the inverted pulse of the pulse CKH through an inverter INV is used as a sampling pulse. The operation of the circuit is described with reference to the signal timing chart of Figure 5. The digital video signal data (D 0 , D 1 ) in sampled by the sampling memory M SMP of the first DA circuit DA1 at every rising of the clock pulse CKH having half-divided frequency (times t 1 , t 3 , ...), and sampled by the sampling memory M SMP of the second DA circuit DA2 at every rising of the inverted signal CKH INV of the pulse CKH (i.e., the falling of the pulse CKH ) (times t 2 , t 4 , ...). Thus, the first sampling memory M SMP1 samples data of odd numbers such as the first data Data 1 and the third data Data 3 . The second sampling memory M SMP2 samples data of even numbers such as the second data Data 2 and the fourth data Data 4 . The sampling memories sample at every period of the clock pulse CKH having a half-divided frequency, so that the data are held in the sampling memories M SMP1 and M SMP2 for two periods of the clock pulse CK . The outputs DAM 1 and DAM 2 of the sampling memories M SMP1 and M SMP2 are supplied to the decoders DEC 1 and DEC 2 , respectively. Each of the decoders DEC 1 and DEC 2 selects one of the external voltages V 0 - V 3 in accordance with the same logic as in the decoder DEC shown in Figure 1. The external voltages selected by the decoders DEC 1 and DEC 2 are output to the odd and even signal voltage hold circuits MO i as outputs DA 1out and DA 2out , respectively. Two signal lines of each of the signal voltage hold circuits MO 1 - MO 120 receive one of the outputs DA 1out and DA 2out of the two DA circuits. In the same way as in the first embodiment (Figure 1), only in one of the signal voltage hold circuits MO i sequentially selected by the selection pulse Tm i , the signal voltage DA 1out or DA 2out is applied to the capacitor C M1 or C M2 of the corresponding one of the signal lines. Unlike the embodiment of Figure 1, this embodiment is provided with the two DA circuits for sampling the data, so that the duration of the selection pulse Tm i is equal to the two periods of the clock pulse. Therefore, the signal voltage DA 1out or DA 2out is applied to the capacitor C M1 (or C M2 ) for a time period twice as long as that in the embodiment of Figure 1. Thus, when all of the capacitors C M1 (or C M2 ) of the 120 signal voltage hold circuits MO 1 - MO 120 hold the signal voltages the control signal S is inverted. Then, the output analog switches ASWO 1 (or ASWO 2 ) of the signal voltage hold circuits MO 1 - MO 120 become conductive at the same time, so that the signal voltages ages held in the respective capacitors C M1 (or C M2 ) are output to the source lines O 1 - O 120 so as to be applied to the pixels. The timing chart of Figure 5 shows the case where the control signal S is H as in Figure 2. The timing chart of Figure 6 shows the case where the control signal S is sequentially inverted. In the case of Figure 6, when the control signal S is H for the first time, digital video signal data Data n1 , Data n3 , ... on the nth line are sampled by the first DA circuit DA1 , and applied to the capacitors C M1 of the first signal line in the odd signal voltage hold circuits MO 1 , MO 3 , ···. For example, the voltage V Datan1 corresponding to the data Data n1 is applied to and held in the capacitor C M1 of the first signal voltage hold circuit MO 1 ((1) of Figure 6). The even digital video signal data Data n2 , Data n4 , ··· are sampled by the second DA circuit DA2 , and applied to the capacitors C M1 of the first signal line of the even signal voltage hold circuits MO 2 , MO 4 , ···. After the capacitors C M1 of all the signal voltage hold circuits MO i hold the signal voltages and when the control signal S changes from H to L , the output analog switches ASWO 1 of the first signal line of all the signal voltage hold circuits MO i become conductive. Accordingly, the signal voltages V Datan1 , V Datan2 , ··· held in the respective capacitors C M1 are output to the source lines O 1 , O 2 , ··· ((2) of Figure 6). Since the output analog switches ASWO 1 are kept conductive during the time when the control signal S is L , the signal voltages of the capacitors C M1 continue to be output to the source lines O i . During this time period, the data Data (n+1)1 , Data (n+1)2 , ··· on the (n+1)th line are sequentially held in the capacitors C M2 of the second signal line. Thereafter, when the control signal S changes from L to H , the voltages V Data(n+1)1 , V Data(n+1)2 , ... corresponding to the data are output to the source lines O 1 , O 2 , ... ((3) of Figure 6). In the second embodiment in which two DA circuits are provided, there may occur a case where the selected one of external voltage sources V 0 - V 3 simultaneously supplies voltages to a maximum of two signal voltage hold circuits MO i through the two DA circuits. The equivalent circuit in this case is shown in (b) of Figure 13. Though the loads in this case are increased as compared with the first embodiment shown in (a) of Figure 13, the number of loads is reduced and the loads are much lighter compared with the prior art circuit shown in (c) of Figure 13 (the loads are 0.4 pF x 2 in this embodiment, but 30 kΩ x 120 and 120 pF x 120 in the prior art circuit). In the embodiment shown in Figure 4, the signal voltage DA 1out or DA 2out generated by the selected external voltage can be applied to the capacitor C M1 (or C M2 ) for the period of time twice as long as the duration of the digital video signal data (i.e., the period of the clock pulse). In other words, even if the duration of the digital video signal data is shortened, it is possible to take sufficient time for charging the capacitor C M1 (or C M2 ) in the circuit of this embodiment. Another embodiment having a drive circuit which is provided with three DA circuits DA 1 , DA 2 and DA 3 is shown in Figure 8. In this embodiment, the output DA 1out of the first DA circuit DA 1 is supplied to the (3k-2)th signal voltage hold circuits MO (3k-2) such as the first, fourth and seventh signal voltage hold circuits. The output DA 2out of the second DA circuit DA 2 is supplied to the (3k-1)th signal voltage hold circuits MO (3k-1) such as the second, fifth and eighth signal voltage hold circuits. The output DA 3out of the third DA circuit DA 3 is supplied to the 3kth signal voltage hold circuits MO 3k such as the third, sixth and ninth signal voltage hold circuits. The signal timing chart in this embodiment is shown in Figure 9. Each of the DA circuits DA 1 , DA 2 and DA 3 samples digital video signal data every three data in accordance with the pulses CK 1 , CK 2 and CK 3 , and the memory holds the data for the three periods of the clock pulse CK . The frequency of each of the pulses CK 1 , CK 2 and CK 3 is divided into three with respect to the clock pulse CK . Accordingly, the duration of the selection pulse Tm i equals three periods of the clock pulse CK , so that the capacitor C M1 (or C M2 ) is charged for a sufficiently long time. A further embodiment in which four DA circuits are provided is shown in Figure 10, and the timing chart thereof is shown in Figure 11. In this embodiment, it is possible to take a long time equal to four periods of clock pulse for charging the capacitor C M1 (or C M2 ). As described above, the provision of plural DA circuits makes it possible to take a longer data holding time, also to take a sufficiently long time for charging the capacitor C M1 (or C M2 ). Therefore, the drive circuit is extremely advantageous, when the duration of the input signal is shortened as the number of pixels is increased by increasing the size and improving the resolution of the display apparatus. In the circuits shown in Figures 1 and 4, the digital video signal is a 2-bit data, for the convenience of the explanation. The configuration of a DA circuit to which digital video data of 4 bits is supplied is shown in Figure 12. In this case, the number of gray-scale levels of the display can be increased. According to the number of bits of the data, a sampling memory M SMP comprises four flip-flops, and the required levels of external voltage is 2 4 = 16. This may cause the decoder DEC to become large (4 inputs and 16 outputs). However, after one of the external voltages V x selected by analog switches ASW 0 - ASW 15 is output as an output DA out , the circuit operates in the same manner as in the circuits of Figures 1 and 4. When the number of bits of the digital video signal data is further increased, the sampling memory M SMP becomes larger merely in proportion, but the numbers of output terminals of the decoder DEC , external voltage sources and the analog switches ASW are drastically increased by the power of 2. In the drive circuit shown in Figure 19 or 20, since the sampling memory M SMP , decoder DEC , etc. are provided for every source line, the numbers are further drastically increased (in the case of Figure 19, the number becomes 120 fold), so that the LSI chip is extremely difficult to produce. However, in the drive circuit according to the invention, though the DA circuit including the sampling memory M SMP , decoder DEC , etc. becomes larger as described above, the number of DA circuits is much smaller than that of source lines, such as one, two (Figure 7), three (Figure 8), or four (Figure 10). Therefore, the drive circuit of the invention has a configuration in which the increase in the number of bits of the digital video signal data can be sufficiently tolerated. As seen from the block diagram of Figure 3 or 7, in the drive circuit of the invention, the DA circuit for converting the digital data into voltages, and the signal voltage hold circuits MO i for temporarily holding and outputting the signal voltages are separately provided. The DA circuit has no relation to the number of the source lines (i.e., the pixels in one horizontal line), and the signal voltage hold circuit portion has no relation to the bit number of data. Figure 15 shows a display apparatus which is constructed in such a manner that DA circuit portions 100 and signal voltage hold circuit portions (MO) 102 are separately formed in different LSIs and positioned around a liquid crystal panel 104 . If the liquid crystal panel 104 is a TFT liquid crystal display of 640 dots, it is necessary to mount 16 signal voltage hold circuit portions 102 including 120 signal voltage hold circuits, in order to output signal voltages to source lines of 640 x 3 (RGB) = 1920. When the DA circuit portions 100 are constructed in the form of a gate array, 1000 or less gates will be required in order to accommodate 6-bit video signal data and four DA circuits (Figure 10). In this invention, digital video signal data are first converted into analog voltage signals, and then the signal voltages are sequentially output to respective capacities for holding signal voltages in accordance with selection pulses, in the same manner as in the prior art analog drive circuit. Therefore, since the external voltage source is connected only to the selected pixels, the loads for the external voltage source can be made very small. Accordingly, even when the number of pixels is increased with the increase in size and the improvement in resolution of the display apparatus, the capacitance of the external voltage sources can still be extremely small. In the circuit of the invention, since a digital sampling circuit is not provided for each pixel, the numbers of flip-flops, decoders and the like are still small, even if the number of pixels is increased. Moreover, even if the number of bits of the digital video signal data is increased, the number of flip-flops, decoders and the like which become larger in size is small. Therefore, if the size is increased and the resolution is improved in the display apparatus, the chip size can be prevented from being drastically enlarged. Furthermore, by providing a plurality of circuits for selectively outputting an external voltage based on the digital video signal data, the external voltage can be supplied to the capacitor of each signal voltage hold circuit for a longer time period than the duration of the digital video signal data. Therefore, the drive circuit can be sufficiently used in a display apparatus with high resolution in which the duration of the video signal is short.

Claims: A drive circuit for driving a display apparatus including a plurality of signal electrodes (O i ) using an input digital video signal (D 1 ,D 0 ;D 3 ,D 2 , D 1 ,D 0 ), the circuit including sampling and conversion means (DA;DA1,DA2;DA1,DA2,DA3;DA1,DA2,DA3,DA4) which is operable to repetitively sample the digital video signal and to output for each digital sample a signal voltage derived from a set of supply voltages (V 3 -V 0 ; V 15 -V 0 ) in accordance with that digital sample; a plurality of drive voltage supply means (MO i ), each provided for supplying a said signal voltage to a respective one of said signal electrodes (O i ) and each having a first and second input coupled to receive the signal voltages output from said sampling and conversion means, said drive voltage supply means (MO i ) each having first and second switching/signal storage means (ASWM 1 ,CM1,ASWO 1 ,ASWM 2 ,CM2,ASWO 2 ) each connected between a respective one of said first and second inputs on the one hand, and the output of said drive voltage supply means on the other hand; and control means (AND 1 ,AND 2 ) for controlling said switching/signal storage means so that as one of said switching/signal storage means receives and stores a said signal voltage from said sampling and conversion means, the other outputs a signal voltage previously supplied to said drive voltage supply means, and entered and stored in said other switching/signal storage means, wherein said signal voltage is received and stored sequentially by the first or second switching/signal storage means of said plurality of drive voltage supply means and said previously supplied signal voltage is output simultaneously by the second or first switching/signal storage means of said plurality of drive voltage supply means. A drive circuit according to claim 1, wherein said first and second switching/signal storage means each comprise an input switching element (ASWM 1 , ASWM 2 ), an output switching element (ASWO 1 ,ASWO 2 ) and a signal holding capacitor (CM1,CM2), and wherein said control means comprises selection signal generating means (AND 1 ,AND 2 ) and control signal generating means, said selection signal generating means (AND 1 ,AND 2 ) controlling said input switching element (ASWM 1 ,ASWM 2 ) connected thereto so that said input switching element (ASWM 1 ) of said first switching/signal storage means and said input switching element (ASWM 2 ) of said second switching/signal storage means alternately receive said signal voltage from said sampling and conversion means, and said control signal generating means controlling said output switching element (ASWO 1 ,ASWO 2 ) connected thereto so that said output switching element (ASWO 2 ) of said second switching/signal storage means and said output switching element (ASWO 1 ) of said first switching/signal storage means alternately output the signal voltage previously received. A drive circuit according to claim 2, comprising a predetermined number of said sampling and conversion means (DA1,DA2;DA1,DA2,DA3;DA1,DA2,DA3,DA4) and wherein each of said sampling and conversion means is connected to drive voltage supply means (MO i ) corresponding to signal electrodes at every said predetermined number, and said selection signal generating means (AND 1 ,AND 2 ) generates selection signals by which said input switching elements (ASWM 1 ,ASWM 2 ) are closed for a period which continues said predetermined number of times as long as the duration of said digital sample of the input digital video signal. A drive circuit according to claim 2 or claim 3, wherein said signal holding capacitor (CM1,CM2) is connected between said input switching element (ASWM 1 ,ASWM 2 ) and said output switching element (ASWO 1 ,ASWO 2 ).

Inventors: OKADA HISAO, TANAKA KUNIAKI, OKADA, HISAO, TANAKA, KUNIAKI
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1991
Main classification: G09G3
IPC codes: G09G3, G02F1, H04N3