Information processing apparatus

Abstract: An information processing apparatus includes an arithmetic operation executing unit (2), a memory unit (4), a memory control unit (3), a resource managing unit (13), and an execution designating unit (1). The arithmetic operation executing unit (2) executes an arithmetic operation on the basis of an instruction. The memory unit (4) stores the arithmetic operation result from the arithmetic operation executing unit (2). The memory control unit (3) has a buffer (32) for temporarily storing data from the arithmetic operation executing unit (2) and controls data transfer between the arithmetic operation executing unit (2) and the memory unit (4). The resource managing unit (13) manages use states of resources of the arithmetic operation executing unit (2). When an instruction is a data store instruction, the execution designating unit (1) sends a buffer holding request to the memory control unit (3) regardless of the resource state of the arithmetic operation executing unit (2). When a buffer holding response is supplied from the memory control unit (3), the execution designating unit (1) designates execution of the data store instruction to the arithmetic operation executing unit (2) and the memory control unit (3) on the basis of management information from the resource managing unit (13).

Description: The present invention relates to an information processing apparatus and, more particularly, to an information processing apparatus for performing control of a vector store instruction used in vector processing. A conventional information processing apparatus will be described below with reference to Fig. 2. Referring to Fig. 2, this conventional information processing apparatus comprises an instruction register 11 for storing instructions, a decoding/checking circuit 12 for decoding an instruction from the register 11, and a resource managing means 13 for monitoring, when the instruction is decoded to be a vector store instruction, the use state of a vector register having data to be stored and acknowledging the decoding/checking circuit 12 that the vector register is readable. On the basis of the acknowledgement from the resource managing means 13, the decoding/checking circuit 12 sends a vector store instruction execution designation signal to a line 53. A memory control unit 3 has a buffer 32 connected to a memory unit 4 and a path 6 for connecting the buffer 32 to an arithmetic operation executing unit 2. In response to the vector store instruction execution designation signal, a buffer managing means 31 and a path managing means 33 in the control unit 3 checks the use state of the buffer 32 and that of the path 6. When the buffer 32 and the path 6 are set in a data transfer enable state, the memory control unit 3 sends a data transfer designation signal to the arithmetic operation execution unit 2 through a line 7. In response to this data transfer designation signal, the arithmetic operation executing unit 2 starts transferring to-be-stored elements in the vector register to the buffer 32. When this data transfer is finished, the memory control unit 3 sends a resource release designation signal to the resource managing means 13 through a line 8. This resource release designation signal indicates the end of use of the stored vector register. Practical instructions used in an information processing apparatus of this type for executing vector processing will be described in detail with reference to Fig. 3A. Referring to Fig. 3A, (1) VADD V2 ← V0 + V1 is a vector addition instruction for adding data of vector registers V0 and V1 in units of elements and storing the sum in a vector register V2. (2) VST M ← V2 is a vector store instruction for storing data of the vector register V2 which stores the sum as the result of the vector addition instruction VADD indicated by (1) in the memory unit 4. (3) VMPY V4 ← V2 * V3 is a vector multiplication instruction for multiplying data of vector registers V2 and V3 in units of elements and storing the product in a vector register V4. An operation of a conventional information processing apparatus using the above instructions will be described below with reference to Figs. 2 and 3B. Referring to Figs. 2 and 3B, when the vector addition (VADD) instruction is stored in the instruction register 11, the resource managing means 13 checks the use states of the vector registers V0 and V1 having data to be read out in accordance with the VADD instruction and that of the vector register V2 for storing the sum. If the registers are being used, the decoding/checking circuit 12 sends a VADD instruction execution designation signal to the arithmetic operation executing unit 2, and the resource managing means 13 is informed of the use of the vector registers V0, V1, and V2. The resource managing means 13 sets the registers V0, V1, and V2 in a usable state when a predetermined time period has elapsed. Subsequently, when the vector store (VST) instruction is supplied to the register 11, the resource managing means 13 checks the use state of the vector register V2 having data to be read out in accordance with the vector store (VST) instruction. When the register V2 becomes usable, the decoding/checking means 12 sends a VST instruction execution designation signal to the arithmetic operation executing unit 2 and the memory control unit 3 through the line 53, and the resource managing means 13 is informed of the use of the vector register V2. At this time, the managing means 13 indicates that the register V2 is being used. In response to the VST instruction execution designation signal, the buffer managing means 31 of the memory control unit 3 checks the use state of the buffer 32, and the path managing means 33 checks the use state of the data path 6. If the two means 31 and 33 determine that the buffer and the path are in a usable state, a data transfer designation signal is sent to the arithmetic operation executing unit 2 through the line 7. In response to this data transfer designation signal, the arithmetic operation executing unit 2 starts transferring data of the vector register V2 to the buffer 32 when a predetermined time period has elapsed. When the transfer is finished, the memory control unit 3 sends a resource release designation signal to the resource managing means 13 through the line 8. In response to the resource release designation signal, the managing means 13 changes the use state designation of the vector register V2 used in accordance with the vector store (VST) instruction to be "usable". Subsequently, when the vector multiplication (VMPY) instruction is stored in the instruction register 11, the resource managing means 13 checks the use states of the registers V2, V3, and V4 to be used in accordance with the VMPY instruction. If the registers are in a usable state, the circuit 12 sends a VMPY instruction execution designation signal to the arithmetic operation executing unit 2. In this information processing apparatus, a timing of starting data transfer performed in accordance with the vector store instruction by the arithmetic operation executing unit 2 with respect to a vector register having data to be stored is controlled by the memory control unit 3. Since, therefore, a timing at which the memory control unit 3 sends a transfer designation signal to the arithmetic operation executing unit 2 is unknown, the execution designation control unit 1 must check the use state of a vector register having data to be stored and confirm that the resource is usable before sending an execution designation signal. In addition, a time period of using a vector register in accordance with the vector store instruction is not predetermined from the generation timing of execution designation. If, therefore, an instruction using the same vector register is present after the vector store instruction, this instruction must be issued after the memory control unit 3 sends a resource release designation signal. As a result, the entire processing is delayed before and after the vector store instruction. US-A-3,718,912 discloses an instruction execution system comprising an arithmetic unit, execution means for storing an instruction for controlling said arithmetic unit, further means for storing at least one subsequent instruction, a plurality of data storage means for use in connection with execution of instructions by said arithmetic unit under the control of an instruction stored in said execution means, means for specifying one of said data storage means for use in connection with the execution of an instruction, storage logic responsive to an instruction for storing an indication of said one of said data storage means specified by said specifying means, and modification logic responsive to said storage logic for inserting in said subsequent instruction the indication of said specified data storage means stored by said storage logic. "Proceedings of the 1986 International Conference on Parallel Processing", August 19-22, 1986, pages 515-518 describes pipelined register-storage (RS) architectures, and discusses several points at which stores can be issued to memory in an RS pipeline. First, they can be issued at the same point as loads. Second, stores can be issued at the same point at which function execution begins. Third, stores may be sent to memory following the execution phase. It is a principal object of the present invention to provide an information processing apparatus capable of shortening an instruction executing time. It is another object of the present invention to provide an information processing apparatus capable of issuing a subsequent instruction at an early timing. In order to achieve the above objects of the present invention, there is provided an information processing apparatus according to the claims. An embodiment of the present invention will be described in detail below with reference to the accompanying drawings, in which Fig. 1 is a block diagram showing an arrangement of an embodiment of the present invention; Fig. 2 is a block diagram showing an arrangement of a prior art; Fig. 3A is a view showing practical instructions; Fig. 3B is a timing chart for explaining an operation of the prior art; and Fig. 3C is a timing chart for explaining an operation of the embodiment of the present invention. Referring to Figs. 1 and 3C, the embodiment of the present invention comprises a memory unit 4 for storing data, an arithmetic operation executing unit 2 for executing a vector arithmetic operation, a memory control unit 3 for controlling data transfer between the arithmetic operation executing unit 2 and the memory unit 4, and an execution designation control unit 1 for decoding instructions, managing resource states of the arithmetic operation executing unit 2, and sending an execution designation signal to the memory control unit 3 and the arithmetic operation executing unit 2. The execution designation control unit 1 includes an instruction register 11 for holding an instruction to be executed, a resource managing means 13 for managing the use states of resources of the arithmetic operation executing unit 2, a path managing means 14 for managing the use state of a data path 6 between the arithmetic operation executing unit 2 and the memory control unit 3, and a decoding/checking circuit 12 as one characteristic feature of the embodiment of the present invention. The memory control unit 3 includes a buffer 32 for storing data transferred between the arithmetic operation executing unit 2 and the memory unit 4, and a buffer managing means 31 as another characteristic feature of the embodiment of the present invention. A relationship between the characteristic parts of the embodiment of the present invention will be described in detail below. If the decoding/checking circuit 12 decodes and determines that an instruction stored in the instruction register 11 is a vector store instruction, it sends a buffer holding request to the buffer managing means 31 of the memory control unit 3 through a line 51 regardless of the use state of a vector register to be used by the instruction. The instruction register 11 holds the vector store instruction until the decoding/checking circuit 12 receives a buffer holding response sent through a line 52 in correspondence with the request. Upon reception of the buffer holding request from the decoding/checking circuit 12 through the line 51, the buffer managing means 31 checks the buffer 32. If a capacity capable of executing the vector store instruction is available, the buffer managing means 31 assures this capacity and sends the buffer holding response to the circuit 12 through the line 52. Upon reception of the buffer holding response, the decoding/checking circuit 12 checks the use state of the vector register supplied from the resource managing means 13 and that of the data path 6 supplied from the path managing means 14. If the decoding/checking circuit 12 determines that the vector register is usable and the path 6 is empty, the circuit 12 sends a vector store instruction execution designation signal to the arithmetic operation executing unit 2 and the memory control unit 3 through a line 53. In response to the execution designation signal, the arithmetic operation executing unit 2 sends data from the vector register to the buffer 32 through the data path 6 when a predetermined time period has elapsed. The memory control unit 3 stores the data sent through the data path 6 in the buffer 32. An operation of the embodiment of the present invention using instructions shown in Fig. 3A will be described in detail below with reference to the accompanying drawings. Referring to Figs. 1, 3A, and 3C, when a vector addition (VADD) instruction is stored in the instruction register 11, the resource managing means 13 checks the use states of vector registers V0 and V1 storing input data to be subjected to vector addition and that of a vector register V2 for storing the sum. If the registers V0, V1, and V2 are usable, the decoding/checking circuit 12 sends a vector addition (VADD) execution designation signal to the arithmetic operation executing unit 2. On the basis of this execution designation signal, the arithmetic operation executing unit 2 reads out the data from the vector registers V0 and V1 and writes the sum data in the vector register V2 when a predetermined time period has elapsed. Upon sending of the execution designation, the decoding/checking circuit 12 informs the resource managing means 13 of the use of the vector registers V0, V1, and V2. In response to this information, the resource managing means 13 sets the vector registers V0, V1, and V2 in a currently-being-used state and sets them in a usable state when a predetermined time period has elapsed. After the VADD instruction execution designation signal is sent, a vector store (VST) instruction is set in the instruction register 11. Upon this setting, a write operation to be executed by the VADD instruction as a preceding instruction has not yet been started for the vector register 2 having the data to be read out by the VST instruction. The circuit 12, however, sends a buffer holding request to the memory control unit 3 through the line 51. In accordance with this request, the buffer managing means 31 holds the buffer 32 and sends a buffer holding response to the circuit 12 through the line 52. On the basis of this buffer holding response, the decoding/checking circuit 12 checks the use state of the register V2 having the data to be read out by the VST instruction, supplied from the resource managing means 13 and that of the data path 6 supplied from the path managing means 14. If the decoding/checking circuit 12 determines that a timing of starting the write operation for the vector register V2 according to the vector addition (VADD) instruction is determined or the write operation is already started and the data path is in a non-used state or at an end-of-use timing, the circuit 12 sends a VST instruction execution designation signal to the arithmetic operation executing unit 2 and the memory control unit 3 through the line 53. In addition, the circuit 12 acknowledges the resource managing means 13 to display that the vector register V2 as an object to be used by the VST instruction is being subjected to a read operation and acknowledges the path managing means 14 to display that the path 6 as an object to be used by the VST instruction is being used. When a predetermined time period has elapsed after the execution designation is acknowledged, the resource managing means 13 changes the display indicating that the vector register V2 is being subjected to a read operation to a display indicating that the vector register V2 is usable, and the path managing means 14 changes the display indicating that the data path 6 is being used to a display indicating that the data path 6 is usable. In response to the execution designation signal indicating the execution start of the vector store (VST) instruction, the arithmetic operation executing unit 2 reads out the data from the vector register V2 and sends the readout data to the data buffer 32 through the data path 6. When a predetermined time period has elapsed after the VST instruction execution designation is acknowledged, the memory control unit 3 stores the data supplied from the vector register V2 through the data path in the buffer 32. After the VST instruction execution designation is acknowledged, a vector multiplication (VMPY) instruction is set in the instruction register 11. The decoding/checking circuit 12 checks the use states of the vector registers V2 and V3 having data to be read out by the vector multiplication (VMPY) instruction and that of the vector register V4 for writing the product. At this time, the vector register V2 as an object to be processed by the vector multiplication (VMPY) instruction is being subjected to the read operation by the preceding vector store (VST) instruction. The decoding/checking circuit 12, however, can determine that the vector register V2 is set in a usable state by the resource managing means 13 when a predetermined time period has elapsed. When the resource becomes usable, the circuit 12 sends information indicating execution of the vector multiplication (VMPY) instruction to the arithmetic operation executing unit 2. According to the present invention, a buffer is held regardless of a busy state of a vector register to be processed by a vector store instruction, and the arithmetic operation executing unit extracts data when a predetermined time period has elapsed after the instruction is issued, thereby releasing the busy state of the vector register to be processed by the vector store (VST) instruction at an early timing. Therefore, when an instruction string is formed such that a vector register to be processed by the VST instruction is supposed to be immediately processed by a subsequent instruction, the subsequent instruction can be issued at an early timing. As a result, although the performance of the individual instruction remains unchanged, an execution time of the processing can be shortened as a whole.

Claims: An information processing apparatus comprising: arithmetic operation executing means (2) for executing an arithmetic operation on the basis of an instruction; memory means (4) for storing the arithmetic operation result from said arithmetic operation executing means; memory control means (3), having a buffer (32) for temporarily storing data from said arithmetic operation executing means, for controlling data transfer between said arithmetic operation executing means and said memory means, and a buffer managing means (31) for checking the capacity of the buffer (32) and reserving space therein upon receipt of a buffer holding request; resource managing means (13) for managing use states of resources of said arithmetic operation executing means; and execution designating means (12) for sending, when an instruction is a data store instruction, said buffer holding request to said buffer managing means (31) of said memory control means regardless of the resource state of said arithmetic operation executing means, and when a buffer holding response is supplied from said buffer managing means (31) of said memory control means, designating execution of the data store instruction to the arithmetic operation executing means and said memory control means on the basis of management information from said resource managing means. An apparatus according to claim 1, further comprising path managing means (14) for managing a use state of a data path between said arithmetic operation executing means and said memory control means, and wherein said execution designating means is adapted to designate execution of the data store instruction on the basis of management information from both of said resource managing means and said path managing means. An apparatus according to claim 1 or 2, wherein said execution designating means is constituted by decoding/checking means for decoding an instruction from an instruction register (11) and checking the management information from said resource managing means and said path managing means. An apparatus according to any of claims 1 to 3, wherein said arithmetic operation executing means executes a vector arithmetic operation on the basis of a vector instruction. An apparatus according to any of claims 1 to 4, wherein said arithmetic operation executing means includes a vector register storing a vector to be processed by the data store instruction, and said resource managing means manages a use state of said vector register.

Inventors: OMATA MAKOTO, OMATA, MAKOTO, OMATA, MAKOTO, C/O NEC KOUFU, LTD.
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: G06F15
IPC codes: G06F9, G06F17, G06F15