Method for manufacturing a semiconductor memory device

Abstract: A method for manufacturing a semiconductor device including steps of (i) laminating a first insulating film over a semiconductor substrate having a plurality of gate electrodes, on which side walls are at least formed, through capacitor formation regions, removing the first insulating film in the capacitor formation region so as to form a direct contact, and laminating a first conductive film over the semiconductor substrate including the residual first insulating film, (ii) removing the first conductive film with remaining at least in the capacitor formation region, (iii) sequentially laminating over the semiconductor substrate including the residual first conductive film (a) a second insulating film, a second conductive film and a third insulating film, or (b) a second insulating film and a second conductive film, and then laminating a resist layer over the whole surface, and (iv) patterning the resist layer and removing with the use of a resist pattern (a) the third insulating film, second conductive film, second insulating film and first conductive film, or (b) the second conductive film, second insulating film and first conductive film, so that the capacitor electrodes of a FEC type DRAM cell including a capacitor upper electrode, a capacitor insulating film and a capacitor lower electrode can be formed in the capacitor formation region.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for dividing capacitor electrodes of a FEC (Floating Electrode Capacitor) type memory cell which is useful as a DRAM (Dynamic Random Access Memory) cell having a wiring width of 0.8µm or less such as a 16 MDRAM. 2. Description of the Prior Art Figs. 6 and 7 show electric equivalent circuits of a FEC type DRAM cell and a conventional DRAM cell, respectively. Referring to the FEC type DRAM cell, a capacitor 61 is connected to transistors 62 and 63. If four kinds of potentials are applied to lower and upper electrodes 61a and 61b of the capacitor 61 as shown in Table 1, the information for 2 bits can be stored by the capacitor 61 and transistors 62 and 63 shown in Fig. 6. Such a DRAM is known for example from IBM Technical Disclosure Bulletin, vol. 31, No. 7, Dec. 1988 pp. 409-417. Applied potential of a FEC type DRAM cell State Upper electrode Lower electrode "0" Vcc 0 "1" (2/3) Vcc (1/3) Vcc "2" (1/3) Vcc (2/3) Vcc "3" 0 Vcc Referring to the conventional memory cell shown in Fig. 7, the capacitor electrodes comprise storage electrodes 31 and plate electrodes 32. The storage electrodes 31 are electrically insulated from each other per memory cell. The plate electrodes 32 are electrically connected to each other and serve as fixed potentials of (1/2) Vcc. The storage electrodes 31 are formed by etching an electrode material such as polysilicon and dividing the same per memory cell. The plate electrodes 32 are common electrodes. Consequently, it is not necessary to divide the plate electrodes 32 per memory cell. In the FEC type memory cell, it is necessary to electrically divide both electrodes of the capacitor similarly to the storage electrodes 31 of the conventional memory cell. The requirements of capacitor formation are different. Accordingly, a method for forming the capacitor of the conventional DRAM cell is not suitable for forming the capacitor of the FEC type DRAM cell for the following reasons. Figs. 8 and 9 are plan views of the electrodes of a memory capacitor which is formed in a capacitor formation step of the conventional method. Fig. 8 shows the capacitor of the conventional DRAM cell. Fig. 9 shows the capacitor of the FEC type DRAM cell. Referring to the conventional memory cell, the plate electrodes 32 (shown in oblique lines in Fig. 8) are not divided between adjacent cells 41 and 41. Consequently, even if the plate electrodes 32 are shifted from the storage electrodes 31, an overlapping amount of the electrodes 31 and 32 of the capacitor is not greatly changed. Thus, the capacity of the capacitor is seldom increased or decreased. A word line is indicated at 42. Referring to the FEC type DRAM cell shown in Fig. 9, when the capacitor electrodes comprising the lower and upper electrodes 61a and 61b are shifted, the overlapping amount of the electrodes 61a and 61b is reduced so that the capacity is decreased. Consequently, it is necessary to ensure the excessive storage capacity of the memory cell correspondingly to the decrease in capacity caused by shift. Accordingly, there is reduced by one half the advantage that the same amount of information can be stored by means of one half of the number of capacitors. A word line is indicated at 91. A local wiring is indicated at 64. To make the most of the advantage of the FEC type DRAM cell, it is necessary to employ a method for forming a capacitor wherein the capacity is not decreased even if the electrodes are shifted at the time of processing. In another conventional DRAM cell, known from JP-A-5 956 754, the capacitor is formed by patterning the capacitor upper and lower electrodes and dielectric layer at the same time. It is an object of the present invention to provide a method for forming a capacitor suitable for the FEC type DRAM cell. SUMMARY OF THE INVENTION The present invention is defined by claim 1. The sub-claims 2 to 5 are directed to embodiments of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a view showing a main portion of a FEC type DRAM cell according to an embodiment of the present invention; Figures 2 and 3 are section views taken along the lines A-A' and B-B' of Figure 1, respectively; Figures 4 and 5 are views showing another embodiment of the present invention correspondingly to Figures 2 and 3, respectively; Figure 6 is an electric equivalent circuit diagram of a general FEC type DRAM cell; Figure 7 is an electric equivalent circuit diagram of a conventional DRAM cell; Figure 8 is a view showing a main portion of a capacitor formed in a step of forming the capacitor of the conventional DRAM cell; and Figure 9 is a view showing the general FEC type DRAM cell correspondingly to Figure 8. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS In a step of forming a capacitor of a FEC type DRAM cell, the same photoresist pattern or SiO 2 pattern is used as an etching mask in order to successively process a three-layer film comprising a capacitor upper electrode, a capacitor insulating film and a capacitor lower electrode by an anisotropic etching method such as reactive ion etching (RIE). Consequently, a memory capacitor can be formed. According to a conventional method, the memory capacitor is formed by using a mask for forming the capacitor lower electrode and a mask for forming the capacitor insulating film and capacitor upper electrode. According to the present invention, the capacitor upper and lower electrodes are simultaneously processed by a single mask. Consequently, it is possible to control the variation of the capacity which is caused by the change of the overlapping amount of the capacitor upper and lower electrodes owing to alignment shift or the like. Furthermore, an embodiment of the present invention provides a method for manufacturing a semiconductor device wherein a local wiring is patterned in order to electrically connect the capacitor upper electrode to a memory cell transistor in the contact hole formation region including a contact hole. Preferred embodiments of the present invention will be described in more detail with reference to the drawings. The present invention is not limited to the following embodiments. Fig. 1 shows the electrodes of a memory capacitor which is formed in a step of forming a capacitor portion according to an embodiment of the present invention. Figs. 2 (a) to (d) are section views showing manufacturing steps, taken along the line A-A' of Fig. 1. Figs. 3 (a) to (c) are section views showing the manufacturing steps, taken along the line B-B' of Fig. 1. Referring to Fig. 2 (d) and Fig. 3 (c), a FEC type DRAM cell comprises a Si substrate 1 including a SiO 2 element isolation film 2, a thermal oxide film 3, polycrystalline Si gate electrodes 4 [see Fig. 2 (d)], a SiO 2 film (first insulating film) 7, a direct contact 20, a memory cell capacitor 21, a contact hole 22 [see Fig. 3 (c)], a polycrystalline Si local wiring 12 [see Fig. 3 (c)], a SiO 2 film (third insulating film) 11, a SiO 2 film (fourth insulating film) 13 and a bit line 14. The polycrystalline Si gate electrodes 4 are provided on the element isolation film 2 and the Si substrate 1 so as to extend through a capacitor formation region (R) shown by an arrow A , and have SiO 2 spacers 5 on their top surfaces and SiO 2 side walls 6 on their side surfaces. The SiO 2 film 7 is provided over the Si substrate 1 including the gate electrodes 4. The direct contact 20 is formed in the capacitor formation region (R) of the SiO 2 film 7. The memory cell capacitor 21 is provided such that the direct contact 20 is embedded therein. The contact hole 22 electrically connects the Si substrate 1 to a capacitor upper electrode 10 to be described below. The polycrystalline Si local wiring 12 directly comes into contact with and is embedded in the contact hole 22 so as to electrically connect the Si substrate 1 to the upper electrode 10. The SiO 2 film 11 is provided on the capacitor 21. The SiO 2 film 13 is provided over the substrate including the capacitor 21. The capacitor 21 has a polycrystalline Si capacitor lower electrode (first conductive film) 8, a SiO 2 capacitor insulating film (second insulating film) 9 and a polycrystalline Si capacitor upper electrode (second conductive film) 10. A manufacturing method will be described below. In Fig. 2 (a), a gate wiring of a MOS transistor is formed by the thermal oxide film 3 having a thickness of about 100 Å and a polycrystalline Si film 4 having a tickness of about 3000 Å on the Si substrate 1 which is isolated by the element isolation film 2 having a thickness of 0.4µm. The polycrystalline Si film 4 has phosphorus dispersed at a high density. Then, the SiO 2 film is deposited on the top and side surfaces of the gate wiring by a CVD method. Thereafter, the SiO 2 spacers 5 and SiO 2 side walls 6 are formed by a known anisotropic etching such as RIE. Subsequently, the SiO 2 film (first insulating film) 7 having a thickness of about 0.2µm is deposited over the Si substrate 1 including the gate wiring by the CVD method. A photoresist pattern formed by a projection and exposure method is used as a mask so as to remove the SiO 2 film 7 in the portion A (region R ) shown in Fig. 2 (a) by the anisotropic etching method such as RIE. Consequently, the direct contact 20 is formed [see Fig. 2 (b) and Fig. 3 (a)]. Then, the polycrystalline Si film (first conductive film) 8 having a thickness of about 0.05µm, on which phosphorus is doped at high density, is deposited over the Si substrate 1 including the direct contact 20. The polycrystalline Si film 8 is etched by the anisotropic etching method such as RIE with the use of a photoresist pattern formed by the projection and exposure method [see Fig. 2 (b) and Fig. 3 (a)]. The etching region of the polycrystalline Si film 8 does not include a region shown in Fig. 2 (b), so that the etching state does not appear. In this case, there is simultaneously formed a region M in which the contact hole 22 is to be formed [see Fig. 3 (a)]. In Fig. 1, the region M indicates the periphery of the contact hole 22 (a region in which the polycrystalline Si film 8 is removed). Thereafter, a SiO 2 film (second insulating film) for forming a capacitor insulating film (not shown), a polycrystalline Si film (second conductive film) (not shown) and a SiO 2 film (third insulating film) (not shown) are sequentially deposited over the Si substrate 1 including the residual polycrystalline Si film 8. The SiO 2 film (second insulating film) is formed by a pressure reducing CVD method. The polycrystalline Si film (second conductive film) has a thickness of about 0.05µm and has phosphorus doped at high density. The SiO 2 film (third insulating film) has a thickness of about 0.1 µm. Thereafter, a photoresist pattern is formed by the projection and exposure method so as to define the shape of the capacitor electrodes. The SiO 2 film, polycrystalline Si film, capacitor insulating film and the polycrystalline Si film are simultaneously etched by the anisotropic etching method such as RIE with the use of the photoresist pattern as the mask, so that the SiO 2 film 11, the capacitor upper electrode 10 of the polycrystalline Si film, the capacitor insulating film 9 and the capacitor lower electrode 8 of the polycrystalline Si film are formed. Consequently, the capacitor 21 is formed on the direct contact 20 [see Fig. 2 (c) and Fig. 3 (b)]. Subsequently, the SiO 2 film 7 in the region M is removed to form the contact hole 22. The local wiring 12 is formed in a region including the region M between the capacitor upper electrode 10 and the memory cell transistor [see Fig. 3 (c)]. The local wiring 12 comprises the polycrystalline Si film on which phosphorus is doped at high density. The SiO 2 film 13 is deposited over the Si substrate 1 including the local wiring 12 and the capacitor 21. Then, the SiO 2 film 13 is flattened. Thereafter, the bit line 14 is provided on the SiO 2 film 13 [see Fig. 2 (d) and Fig. 3 (c)]. The bit line 14 is comprises a multilayer film which is formed by sequentially laminating a high melting point metal layer, a high melting point metal silicide layer and the polycrystalline Si layer on which impurities are doped at high density. The FEC type DRAM cell is formed according to the above-mentioned steps. Figs. 4 and 5 show another embodiment of the present invention. In the case where a capacitor 21 is to be formed, a SiO 2 film 11 [see Fig. 3 (b)] and a capacitor 21 are not simultaneously formed. A second conductive layer 10, a second insulating film 9 and a first conductive layer 8 are sequentially etched in advance so as to form only the capacitor 21 [see Fig. 4 (c) and Fig. 5 (b)]. Thereafter, a SiO 2 film 11a is formed over the Si substrate 1 including the capacitor 21 [see Fig. 5 (c)]. The SiO 2 film 11a electrically insulates the capacitor 21 from a local wiring 12 to be formed on a contact hole 22. A manufacturing method will be described below. In Fig. 4 (a), a gate wiring of a MOS transistor is formed by a thermal oxide film 3 and a polycrystalline Si film 4 on a Si substrate 1. The Si substrate 1 is isolated by an element isolation film 2 having a thickness of about 0.04 µm. The thermal oxide film 3 has a thickness of about 100 Å. The polycrystalline Si film 4 has a thickness of about 3000 Å and has phosphorus dispersed at high density. A SiO 2 film is deposited on the top and side surfaces of the gate wiring by a CVD method. Then, SiO 2 spacers 5 and SiO 2 side walls 6 are formed by an anisotropic etching method such as RIE. Thereafter, a SiO 2 film 7 having a thickness of about 0.2 µm is deposited on the gate wiring by the CVD method. Subsequently, a photoresist pattern is formed in a portion A (region R ) shown in Fig. 4 (a) by a projection and exposure method. The SiO 2 film 7 is removed by the anisotropic etching such as RIE with the use of the photoresist pattern as a mask. Fig. 4 (b) and Fig. 5 (a) show the residual SiO 2 film 7. In this case, the SiO 2 film 7 in the region R is removed to form a direct contact 20. Then, there is deposited a polycrystalline Si film 8 which has a thickness of about 0.05 µm m and has phosphorus doped at high density [see Fig. 4 (b)]. Thereafter, the polycrystalline Si film 8 is etched by the anisotropic etching method such as RIE with the use of a photoresist pattern formed by the projection and exposure method [see Fig. 5 (a)]. In this case, a contact hole is to be formed in a region M shown in Fig. 5 (a). Subsequently, a capacitor insulating film 9 and a polycrystalline Si film 10 are sequentially deposited over the residual polycrystalline Si film 8. The capacitor insulating film 9 is formed by a pressure reducing CVD method. The polycrystalline Si film 10 has a thickness of about 0.05 µm and has phosphorus doped at high density. Then, a photoresist pattern is formed by the projection and exposure method in order to define the shape of a capacitor electrode. The polycrystalline Si film 10, the capacitor insulating film 9 and the polysilicon Si film 8 are etched by the anisotropic etching method such as RIE with the use of the photoresist pattern as the mask. Consequently, a capacitor 21 is formed [see Fig. 4 (c) and Fig. 5 (b)]. Then, a SiO 2 film 11a having a thickness of about 0.1 µm is deposited [see Fig. 4 (d)]. Thereafter, a photoresist pattern for defining the shape of a contact hole 22 is formed between the capacitor upper electrode 10 and the memory cell transistor (substrate) 1 by the projection and exposure method. The SiO 2 film lla is removed by using the photoresist pattern as the mask. The portion to be removed is shown in Fig. 5 (c). The residual SiO 2 film 11a is shown in Fig. 5 (c). Consequently, the contact hole 22 is formed. Subsequently, a local wiring 12 is formed between the capacitor upper electrode 10 and the memory cell transistor. The local wiring 12 comprises a polycrystalline Si film on which phosphorus is doped at high density. The Si substrate surface is flattened by a SiO 2 film 13. Then, a bit line 14 is provided [see Fig. 4 (d) and Fig. 5 (c)]. The bit line 14 comprises a multilayer film formed by sequentially laminating a high melting point metal layer, a high melting point metal silicide layer and a polycrystalline Si layer on which impurities are doped at high density. According to the present invention, the capacitor lower electrode can be self-aligned with the capacitor upper electrode. Accordingly, it is possible to prevent the decrease in capacity caused by the relative shift of the upper and lower electrodes at the time of processing. Consequently, it is not necessary to compensate for the decrease in capacity. The capacity is small so that the area of a memory cell can be reduced. Therefore, there can be obtained a high density DRAM cell. The FEC type DRAM cell is useful for the high density DRAM including a 16 MDRAM. According to the present invention, it is possible to obtain the high density DRAM including the 16 MDRAM.

Claims: A method of forming a capacitor (21) for a FEC type DRAM cell wherein a single mask is used for forming a capacitor lower electrode (8), a capacitor insulating film (9) and a capacitor upper electrode (10), the capacitor upper and lower electrodes (10,8) being simultaneously processed using said single mask, and wherein, to the side of the capacitor (21) at which a wiring contact (12) to the capacitor upper electrode (10) is to be formed, the capacitor lower electrode (8) is preliminarily patterned so as to be spaced farther from the wiring contact side than the capacitor upper electrode (10). A method according to claim 1, wherein said single mask comprises a pattern of photoresist or SiO 2 . A method according to claim 1 or claim 2, wherein the simultaneous processing of the capacitor upper and lower electrodes (10,8) uses an anisotropic etching method such as reactive ion etching (RIE). A method according to claim 1, comprising: (i) laminating a first insulating film (7) over a semiconductor substrate (1) having a plurality of gate electrodes (4) on which at least side walls (6) are formed, and having capacitor formation regions (R) which bridge adjacent said gate electrodes (4), removing the first insulating film in the capacitor formation region so as to form a direct contact (20) for said capacitor lower electrode in the capacitor formation region, and laminating a first conductive film (8) over the semiconductor substrate including the residual first insulating film (7); (ii) removing the first conductive film (8) so that at least a part of the periphery of the residual first conductive film is arranged in the capacitor formation region (R); (iii) sequentially laminating over the semiconductor substrate (1) including the residual first conductive film (8), so as to cover the residual first conductive film including said part of the periphery, a second insulating film (9), a second conductive film (10), and optionally a third insulating film (11), and then laminating a resist layer over the whole surface; and (iv) patterning the resist layer and removing in one step with the use of a resist pattern the third insulating film (11) if any, the second conductive film (10), the second insulating film (9) and the first conductive film (8), so that a said capacitor comprising said capacitor upper electrode (10), said capacitor insulating film (9) and said capacitor lower electrode (8) is formed in the capacitor formation region (R). A method according to claim 4, wherein a local wiring (12) is patterned in order to electrically connect the capacitor upper electrode (10) to a memory cell transistor in a contact hole formation region (M) including a contact hole (22) to said semiconductor substrate (1) through said first insulating film (7).

Inventors: HASEGAWA MASAHIRO, SHIMOMURA NARAKAZU, HASEGAWA, MASAHIRO, SHIMOMURA, NARAKAZU
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1991
Main classification: H01L27
IPC codes: H01L27, H01L21