Semiconductor device

Abstract: A semiconductor device comprises a poly-crystalline silicon layer, a dielectric layer formed on said poly-crystalline silicon layer, and a conductive layer formed on said dielectric layer. The poly-crystalline silicon layer has an uneven surface including a plurality of convex portions and a plurality of concave portions, with said convex portions being defined by growing silicon grains, such as hemisherical-like silicon grains, or mushroom-like silicon grains, projecting from the surface of the silicon layer. A typical silicon grain has a diameter in range of 30 to 170nm.

Description: The present invention relates to semiconductor devices comprising polycrystalline silicon layers suitable for use as electrodes for capacitors. In recent years, the memory cell size has been reduced accompanying the increase in the degree of integration of DRAMs, and along with it the area or storage capacitors used for the cells tends to be decreased. For this reason, stacked capacitors or trench stacked capacitors that have a large effective area for the capacitor part, an excellent α-ray resistance characteristic and a small interference between the capacitor parts have been employed in order to secure sufficiently high capacitances. However, for 64 Mbit DRAMs now under development each cell area is anticipated to become smaller than 1.5 µm 2 , so that there is required a capacitor insulating film with a thickness of less than 50 Å when converted to equivalent thickness of silicon dioxide (SiO 2 ) film, even with the use of the aforementioned structures. It is extremely difficult to form such a thin capacitor insulating film uniformly and without defect all over the chip. In order to resolve the above-mentioned problem, ther can is conceived an idea of increasing the effective areas of the opposing electrodes of a capacitor by providing a micro roughness on the surface thereof to obtain a larger electrostatic capacity for a capacitor of the same size. A method for increasing the opposed electrode areas, that is, for enlarging the effective surface areas, of polycrystalline silicon electrodes is disclosed in "Capacitance-Enhanced Stacked-Capacitor with Engraved Storage Electrode for Deep Submicron DRAMs, Solid State Devices and Materials, 1989, pp. 137-140. According to this method, the surface of a polycrystalline silicon is coated with spin-on-glass (SOG) containing photoresist particles. Then the effective surface area of the polycrystalline silicon film is increased by providing a micro roughness the surface thereof by etching the SOG film, whereby etching the polycrystalline silicon surface using the resist particles as the mask. However, this method has the following problems. Namely, there are required strict control of the size of the resist particles and distribution of the resist particles on the wafer with uniform density at the time of coating, in addition to the complexity of the process involved. Patent Abstracts of Japan vol. 13, No 240 (E-767) (3588), 6 June 1989 & JP-A-64 042 161 concerns a semiconductor capacitor comprising a polycristalline silicon layer having an uneven surface including a plurality of convex portions, a dielectric layer formed on said polycristalline layer and a conductive layer. SUMMARY OF THE INVENTION It is, therefore, an object of the present invention to provide a semiconductor device comprising a polycrystalline silicon layer, a dielectric layer formed on said polycrystalline silicon layer, and a conductive layer formed on said dielectric layer, said polycrystalline silicon layer having a top surface and a side surface, both of said top surface and said side surface being made uneven with a plurality of convex portions, each of said convex portions being defined by a hemispherical like shape silicon grain. It is another object of the invention to provide a semiconductor device comprising a polycrystalline silicon layer, a dielectric layer formed on said polycrystalline silicon layer, and a conductive layer formed on said dielectric layer, said polycrystalline silicon layer having a top surface and a side surface, said top surface being made uneven with a plurality of convex portions, each of said convex portions being defined by a silicon grain of a mushroom like shape. The invention concerns semiconductor device comprising a polycrystalline silicon layer, a dielectric layer formed on said polycrystalline silicon layer, and a conductive layer formed on said dielectric layer, said polycrystalline silicon layer having an uneven surface including a plurality of convex portions, each of said convex portions being defined by a silicon grain of a mushroom like shape, said silicon grain has a first diameter defining a stem of said mushroom like shape and a second diameter defining a bulging portion of said mushroom like shape, said first diameter being smaller than said second diameter. The present invention provides also a semiconductor capacitor formed on a substrate comprising: a first electrode having a plurality of mushroom like shaped convex silicon grains creating an uneven surface; a dielectric layer formed on said first electrode with a thickness such that a pair of opposing surfaces of said dielectric layer are substantially parallel and substantially replicate said uneven surface of said first electrode; a second electrode formed on and conformal to said dielectric layer is insulated from said first electrode, whereby capacitance between said first electrode and said second electrode is increased by said mushroom like shape silicon grains of said uneven surface. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, advantages and features of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which: Fig. 1 shows scanning electron microphotographs and the corresponding reflection high energy electron diffraction (RHEED) photographs at the surface of the deposited film for different deposition temperatures; Fig. 2 is a graph showing the dependence of the capacitance of a fabricated capacitor, the surface area of the silicon film and the deposition temperature of silicon; Fig. 3 is an electron microphotograph showing the surface condition of a silicon film with micro roughness taken after phosphorus diffusion; Fig. 4 shows a distribution diagram of the relative magnification at the surface area of silicon film deposited at the temperature of 590°C within a 4-inch wafer; Fig. 5 is a graph showing the dependence of the leakage current on the applied voltage for the stacked capacitors formed at different silicon film deposition temperatures (590 and 640°C); Fig. 6 is a graph showing the dependence of the leakage current at the applied voltage for stacked capacitors with different silicon film deposition temperatures; Fig. 7 is a frequency distribution diagram for the breakdown voltage of stacked capacitors for different silicon electrode deposition temperatures; Fig. 8 is a scanning electron microphotograph of the film surface according to a embodiment 2 after annealing of a silicon film formed at the transition temperature; Fig. 9 is a scanning electron microphotograph showing the surface condition according to a embodiment 3 of a film formed by depositing a compact polycrystalline film at a temperature above the transition temperature, on a silicon film formed at the transition temperature; Fig. 10 shows sectional views for different fabrication processes of a stacked capacitors having a micro roughness also on the side faces according to a embodiment 4; Fig. 11 shows scanning electron microphotographs of the cross-sections of a stacked capacitor formed in accordance with the fabrication method illustrated in Fig. 10; Fig. 12 shows sectional views for different growth stages in the phenomenon of the growth of a silicon layer having a surface with micro roughness as a result of annealing an amorphous silicon layer on the substrate at a temperature above the transition temperature; Fig. 13 shows photographs that illustrate the phenomenon described in Fig. 12, wherein Fig. 13(a) shows a cylindrical amorphous silicon film prior to annealing and Fig. 13(b) shows a cylindrical polycrystalline silicon film with a micro roughness taken after annealing; Fig. 14 is a graph showing the capacitance difference of a capacitor for the cases of taking, and not taking, the wafer out into the atmosphere prior to the annealing; Fig. 15 shows sectional views for different fabrication processes according to embodiment 6; Fig. 16 shows sectional views for different fabrication processes according to an embodiment 7; Fig. 17 shows sectional views for different fabrication processes of an embodiment 8; Fig. 18 shows sectional view for different fabrication processes according to a embodiment 9; and Fig. 19 shows a scanning electron microphotograph that illustrate the phenomenon described in Fig. 18G. DETAILED DESCRIPTION OF THE INVENTION The polycrystalline silicon film having a surface with micro roughness can be formed based on the grain growth of silicon when silicon is deposited at the transition temperature has already been mentioned in the above. This phenomenon can be described as in the following. Namely, during the deposition of silicon at the transition temperature, silicon deposited is principally of amorphous type. If the temperature inside the furnace tube is kept at the transition temperature even after the completion of the deposition, silicon atoms that have been migrating in the surface of the deposited amorphous silicon film start to form crystalline nuclei. Silicon atoms that are migrating in the vicinity of the crystal nuclei are captured by the nuclei and contribute to the growth of the nuclei and to the increase of the size of the grains. As a result, there is formed a polycrystalline silicon film having surface with a micro roughness. On the other hand, when silicon is deposited at a temperature below the transition temperature, the deposited film remains as amorphous as is, with its surface being very smooth. When a film is deposited at a temperature above the transition temperature, it means the formation of an ordinary polycrystalline silicon film. The surface of the deposited polycrystalline silicon has too many nuclei, so that they can not grow each other, as a result, the surface remains smooth all the same. As in the above, one should recognize that it is important to deposit silicon at the transition temperature. However, it is difficult to determine the transition temperature. This is because the transition temperature depends to some extent on the formation conditions. Nonetheless, the present inventors discovered that surface with a micro roughness can be obtained if silicon is deposited at a temperature in the range of the transition temperature of 550 ± 10°C. It should be noted, however, that the temperature of 550°C is the temperature on the outside of the furnace tube and the actual temperature of the wafer at this time was found to be 590°C as examined by an infrared sensor. Accordingly, if silicon is deposited at a wafer temperature in the range of 590 ± 10°C (the temperature outside the furnace tube being in the range of 550 ± 10°C), there can be formed a polycrystalline silicon film having surface with a micro roughness. In the description that follows the temperature indicated will invariably refer to the wafer temperature, and the temperature outside the furnace tube will be indicated in parentheses following the wafer temperature. Referring to Fig. 1, the surface condition and the crystallinity of the silicon films formed at various deposition temperatures are shown. The deposition was carried out by a low pressure chemical vapor deposition (LPCVD) method on a silicon substrate whose surface is covered with an SiO 2 film. The gas used is the mixture of SiH 4 and He (at 20% of SiH 4 and 80% of He), and the pressure is 1 Torr. Figs. 1AA, 1BA, 1CA, 1DA and 1EA are the scanning electron microscopy (SEM) photographs, with magnification of 100,000, of the surface of 2500 Å-thick silicon films deposited at the temperatures of 550°C (510°C), 580°C (540°C), 590°C (550°C), 600°C (560°C) and 650°C (610°C), respectively. The space between the adjacent dots among a group of dots shown at the bottom of the photographs is 30 nm, and hence the distance from one end dot to the other end dot of the arrayed 11 dots is 300 nm. The acceleration voltage of the electron micrograph is 20 kV. Further, Figs. 1AB, 1BB, 1CB, 1DB and 1EB are RHEED photographs that show crystallinity corresponding to Figs. 1AA, 1BA, 1CA, 1DA and 1EA, respectively. As shown in Fig. 1AA, the surface of the silicon film deposited at 550°C (510°C) is very smooth, and no grain growth is observed. In addition, no ringlike patterns are visible in the RHEED photograph, Fig. 1AB, indicating that the film is amorphous. In the film deposited at 580°C (540°C) shown in Fig. 1BA, a partial growth of grains is observable, coexisting with the amorphous phase. Ringlike patterns appear in the RHEED photograph, Fig. 1BB, confirming a partial formation of crystals. When the deposition temperature is slightly raised to 590°C (550°C), hemispherical grains with diameter in the range of 300 to 1700 Å, centered around 700 Å, are formed at high density, generating a micro roughness on the surface, drastically increasing the surface area of the film. In the RHEED photograph shown in Fig. 1CB there are observable ringlike patterns, showing the occurrence of crystallization. As the deposition temperature is further raised to 600°C (560°C) the surface roughness becomes somewhat gentle as shown in Fig. 1DA. In the RHEED photograph shown in Fig. 1DB, dots of reflection electron diffraction become visible, indicating the formation of polycrystalline silicon with high orientation. When the deposition temperature is further raised to 650°C (610°C) which is close to the deposition temperature of the ordinary polycrystalline silicon used for LSIs or the like, the grain diameter becomes further increased with smooth surface as shown in Fig. 1EA, and there are observed the dots of reflection electron diffraction with the formation of polycrystalline silicon as shown in Fig. 1EB. As is clear from the above result, at the temperature (transition temperature) in the range where the crystal condition of the deposited silicon film makes a transition from the amorphous phase to the polycrystalline phase, a very fine roughness is generated on the film surface and the surface area is increased compared with at other temperatures. A silicon film which is grown at the transition temperature where the crystal condition changes from the amorphous phase to the crystalline phase is considered to lack compactness to some extent. This is estimated from the fact that the etching rate, for example, by a wet etching method, of a silicon film grown at the transition temperature is higher than that of a polycrystalline silicon film deposited at an ordinary deposition temperature (a temperature higher than the transition temperature). When an extremely thin capacitor insulating film with thickness of 50 Å is formed on the silicon film, there is a possibility of generating pin holes in the insulating film. In order to make a silicon film deposited at the above-mentioned temperature to be more compact, it only needs to subject it to a heat treatment given at a temperature higher than the transition temperature, for example, a temperature higher than 640°C (600°C). This heat treatment will not affect the micro roughness in any substantial manner. Generation of pin holes can be precluded if a capacitor insulating film is formed subsequently. This heat treatment may be accomplished as included in the heat treatment on the occasion of impurity doping. Further, instead of giving a heat treatment at a temperature above the transition temperature, a compact polycrystalline silicon film may be deposited on the above-mentioned silicon having micro roughness to such an extent of thickness that will not fill in the micro roughness. The compact polycrystalline silicon may be deposited at a temperature above 600°C (560°C). In accordance with the above-mentioned method it is possible to form a silicon film with large surface area and small irregularity of characteristics by means of a simple fabrication process. By using such a silicon film as, for example, the electrode for the capacitor part of a semiconductor memory it becomes possible to increase the surface area, and hence the capacitance, of the capacitor for the same volume that is occupied by the capacitor part. As has been mentioned in the above the transition temperature has a certain range. When a silicon film is deposited at a temperature on the lower side of the range of the transition temperature, the grain diameter becomes large because the density of generation points of silicon nuclei on the surface of amorphous silicon is low. When a silicon film is deposited at a temperature on the higher side of the transition temperature range, the grain diameter becomes small because the density of generation points of silicon nuclei on the surface of amorphous silicon is high. The present inventors discovered that it is possible to control the size and the density of the grains by controlling the temperature within the range of the transition temperature as described in the above. Moreover, the size and the density of grains can also be controlled by varying the growth pressure of the silicon film within the range of the transition temperature. This is because the generation of the silicon nuclei on the surface of amorphous silicon is suppressed due to the mixing of hydrogen into the silicon film if the silicon film is deposited at a low vacuum. Because of this, the grain size becomes large. On the other hand, if a silicon film is deposited at a high vacuum, the mixing of hydrogen into the silicon film is decreased and the density of nucleus generation on the surface of amorphous silicon becomes high. Because of this, the grain size becomes small. As in the above, it was discovered that the size and the density of the grains can be controlled by controlling the deposition pressure and the density of hydrogen for the silicon film within the range of transition temperature as described in the above. Further, even if the pressure is constant, it is possible to control the grain size and the grain density by changing the hydrogen concentration in amorphous silicon by varying the partial pressure of the material gases. Moreover, it was also found that it is possible to control the generation density of silicon nuclei on the surface of amorphous silicon by controlling the hydrogen concentration within the silicon film by adding hydrogen gas at the time of depositing the silicon film at the transition temperature. Now, embodiments that employ the aforementioned methods will be described along with the effect of the present invention. Embodiment 1 A stacked capacitor was trially manufactured. A thick SiO 2 film was formed on a silicon substrate, a silicon film was formed on top of it in accordance with the method illustrated in Fig. 1, and the product was used as the lower electrode of the capacitor. Phosphorus was diffused into the silicon film obtained under the conditions of 820°C and 60 minutes, a capacitor insulating film was formed on the surface and a polycrystalline silicon film that is to become the upper electrode was formed on top of it. The formation of the capacitor insulating film was accomplished by first forming an Si 3 N 4 film on the silicon film by an LPCVD method, then by oxidizing the surface of the Si 3 N 4 film. The Si 3 N 4 film was deposited to a thickness of 120 Å at a temperature of 780°C and a pressure of 30Pa using a mixed gas of SiH 4 and NH 3 (with SiH 4 /NH 3 = 1/100), and the surface was oxidized at 900°C by wet 1:1 pyrogenic oxidation to the extent where there is obtained a thickness of 20 Å when converted to equivalent oxide film, in the 120 Å of the Si 3 N 4 film. Under the above-mentioned conditions the capacitor insulating film becomes 100 Å (labeled as deff) when converted to an equivalent SiO 3 film. If a smaller thickness of the capacitor insulating film, for example deff = 50 Å, is desired, it is only needed to form an Si 3 N 4 film of 60 Å and oxidize the film to the extent of an increase of 10 Å when converted to an oxide film. It is preferable that the thickness of the capacitor insulating film is in the range of 30 to 500 Å so as to enable the replication of the micro roughness of the lower layer silicon film onto the upper surface of the capacitor insulating film. After the formation of a capacitor insulating film of deff = 100 Å, then a polycrystalline silicon film is deposited on top of it at 640°C (600°C) and phosphorus was diffused into it. Following that, stacked capacitors were obtained by dividing the sample into the dimensions of 1 mm x 1 mm by means of a lithography technique and a dry etching technique. As a result, the dependences of the surface area and the capacitance of the silicon film on the deposition temperature of the lower silicon film as shown in Fig. 2 were obtained. Namely, at the deposition temperature of Fig. 1A the surface area remains at 1 mm 2 and the capacitance is accordingly at a small value of 3.5 nF. For the deposition temperature of Fig. 1B the capacitance was slightly increased to 3.8 nF corresponding to a partial growth of the grain. For the deposition temperature of Fig. 1C both of the surface area and the capacitance became more than twice the original values, namely, 2.1 mm 2 and 7.3 nF, respectively. For the deposition temperature of Fig. 1D a surface area of 1.07 mm 2 and a capacitance of 3.6 nF were obtained reflecting the gentleness of the surface roughness. For the deposition temperature of Fig. 1E the situation barely differs from that of Fig. 1A. Note that the results obtained at deposition temperatures other than those of Fig. 1 are also included in the figure. In either case, it is possible to obtain a capacitance that is more than twice as large that of an ordinary stacked capacitor with the same dimensions if a stacked capacitor uses a silicon film deposited at the transition temperature. The surface condition of a silicon film with a micro roughness formed once on its surface will not be changed substantially by a heat treatment in the subsequent stage. An SEM photograph of the surface condition when phosphorus is diffused under the conditions of 820°C and 60 minutes into the film deposited at 590°C (550°C) shown in Fig. 1C is shown in Fig. 3. Fig. 4 shows the surface area distribution (representative points only) within a four-inch wafer when phosphorus was diffused into the silicon film formed at 590°C (550°C). The measurement was taken using the stacked capacitor of Embodiment 1. The numerical values which indicate the ratio of the surface area with respect to that of the wafer formed at 550°C (510°C) show that the surface area increase is very uniform all over the wafer surface. In addition, its reproducibility was also found to be satisfactory. This uniformity prevails also between wafers and between lots, and the reproducibility is also high. In Fig. 5 is shown the leakage current characteristic of the stacked capacitors obtained at the deposition temperatures of 590°C (550°C) and 640°C (600°C). It can be seen that the result for the former case is somewhat inferior to the latter case. However, in the use for semiconductor memories the maximum voltage applied to a capacitor is 5 V (lately, 3.3 V). Therefore, there arises substantially no problem since there exists hardly any difference in the leakage current between the two cases up to the voltage of 5 V, and the applied voltage can be reduced to one half by the use of the well-known 1/2 Vcc cell plate technique. Here, the leakage current characteristic will be compared when the same capacity is secured. For the construction of a 64 Mbit DRAM with the ordinary stacked capacitor structure it is said that a capacitor insulating film of about 50 Å thickness when converted to equivalent oxide film (deff) is required if a polycrystalline silicon film deposited at the conventional temperature of about 640°C (600°C) is used as a storage electrode. However, by employing a silicon film in accordance with the present invention it becomes possible to use a capacitor insulating film with thickness of 100 Å. In Fig. 6 are shown the leakage current characteristic for two representative cases. As can be seen from the figure, the voltage by which the leakage current can be suppressed to below 1 x 10 -8 A/cm 2 where a capacitor is usable as a device is 2.0 V for the conventional capacitor. In contrast, the corresponding voltage can be increased to 5.4 V in the case of using silicon of the present embodiment, sharply improving the leakage current characteristic. In Fig. 7 is shown the breakdown voltage distribution for the same cases of deposition at 590°C (550°C) and 640°C (600°C) that are given in the lower and upper portions of the figure, respectively. The results shown correspond to the measurements results taken by using stacked capacitors with the same structure as in Embodiment 1 for several sheets of wafer. The thickness of the capacitor insulating film at this time was 100 Å. The peak value of the breakdown electric field intensity for the case of Si electrode deposition temperature at 590°C (550°C) is 8.7 MV/cm while the peak value for the case of 640°C (600°C) is 9.5 MV/cm so that the deterioration of the former case is 0.8 MV/cm relative to the latter. However, in the actual use such a difference is of no particular concern. Moreover, the scatter of the breakdown electric field intensity value is comparable for both samples, and is very satisfactory. Embodiment 2 The stacked capacitor used in the present embodiment was trially manufactured in the same way as in Embodiment 1. In Embodiment 1 the quality of the silicon film deposited at the transition temperature was made compact by a heat treatment at the time of phosphorus diffusion. In the present embodiment, however, the film quality was made compact by subjecting the sample to an annealing at a temperature above the transition temperature prior to the formation of the capacitor insulating film. In Fig. 8 is shown an SEM photograph of the surface of a silicon film deposited at the transition temperature of 590°C (550°C), then annealed at 740°C (700°C) in a nitrogen atmosphere. There is little change in the surface condition from that at the time of the film deposition. Subsequently, phosphorus was diffused similar to Embodiment 1, a capacitor insulating film was formed, a polycrystalline silicon film that is to become the upper electrode was deposited to form a stacked capacitor similar to that of Embodiment 1. Capacitance and surface area of a capacitor same as those of Embodiment 1 were obtained. They are extremely uniform within the wafer, from one wafer to another and from one lot to another as in Embodiment 1, with satisfactory reproducibility. As to the leakage current characteristic and the breakdown voltage, the result obtained was satisfactory, being substantially the same as at the deposition temperature of 640°C (600°C). Now, it is to be noted that the annealing was carried out at 740°C (700°C) in the present embodiment, but the compactification of the silicon film may be accomplished by an annealing for a long time at a low temperature such as 650°C (610°C) or by an annealing at a high temperature of 840°C (800°C). Embodiment 3 In the present embodiment, instead of the annealing in Embodiment 2, a compact silicon film was deposited at a temperature above the transition temperature on a silicon film formed at the transition temperature. Here, a polycrystalline silicon film was deposited to a thickness of 300 Å at the temperature normally used. Figure 9 is an SEM photograph showing the surface condition of the surface after the deposition. There is observed little change in the surface condition. Following the above, a stacked capacitor was formed in the same way as in Embodiment 2, and the capacitance and the surface area of the capacitor formed were measured. The result is similar to that of Embodiment 1, their value distribution within the wafer, between wafers and between lots was extremely uniform, and its reproducibility was excellent. Further, the leakage current characteristic and the breakdown voltage were satisfactory, being substantially the same as those for the deposition temperature of 640°C (600°C). It is to be noted that it is necessary to limit the thickness of the silicon film to a degree which will not bury the micro roughness on the surface of the underlying silicon film. Embodiment 4 In the present embodiment, a stacked capacitor having a capacitor part also on the sides faces will be described. First, as shown in Fig. 10a, a silicon oxide film 2 is formed on a silicon substrate 1 with a transfer gate and the like formed thereon, resist 3 is applied to be patterned and the oxide film 2 is etched by dry etching (Fig. 10b). Then, as shown in Fig. 10c, a polycrystalline silicon film 4 is deposited, and an impurity such as phosphorus or arsenic is doped by thermal diffusion. The polycrystalline silicon film 4 is deposited by an LPCVD method under the normal conditions of the temperature of 640°C (600°C), reaction gas which is a mixture of SiH 4 and He (at 20 vol % of SiH 4 and 80 vol % of He) and pressure of 1 Torr. A silicon oxide film 5 is formed by a CVD method on the polycrystalline silicon film 4, and another polycrystalline silicon film 6 is formed on top of it under the same conditions as for the polycrystalline silicon film 4. A resist 7 is applied on top of it to be patterned (Fig. 10c), and by using the resist as a mask dryetching is given up to the polycrystalline silicon film 4 (Fig. 10d). Following the removal of the resist 7 a silicon film 8 having surface with a micro roughness is deposited at 595°C (555°C) (Fig. 10e). The deposition conditions are the same as for the polycrystalline silicon film 4 except for the temperature. Then, the sample is annealed at 740°C (700°C) for 30 minutes in a nitrogen atmosphere. Next, phosphorus or arsenic is doped into the silicon film 8 by thermal diffusion. Subsequently, the sample is subjected to a reactive ion etching (RIE) that uses Cℓ 2 gas to obtain a lower electrode 8 for a stacked capacitor as shown in Fig. 10f. The top portion and the side faces of the silicon film 18 have even after the RIE a roughness with large area that reflects the roughness before the etching of the silicon film 8. In other words, the top portion and the side faces of the silicon film 18 are given a roughness by the replication of the roughness of the silicon film 8 onto the polycrystalline silicon film 6. Note that in the absence of the polycrystalline silicon film 6 the top portion of the stacked capacitor will be lost at the time of RIE and there will be left only its side faces. Next, a capacitor insulating film 9 is formed under the same conditions as for Embodiment 1, and further a phosphorus-doped polycrystalline silicon film 10 is deposited (Fig. 10g). In this manner, a stacked capacitor that has a capacitor parts formed also on the side faces and has a very large capacitance can be obtained. By increasing the thickness of the oxide film 5 it is possible to augment the area of the side faces and increase the capacitance accordingly. In Figs. 11a and 11b are shown the SEM photographs of the stacked capacitor formed. The magnifications of Figs. 11a and 11b are 40,000 and 25,000, respectively, showing approximately the same location of the capacitors. One of the forefront capacitors is revealing its cross section. From the figure it can be seen that there still remains a sufficiently well-defined roughness on the surface of the silicon film even after the dry etching. It should be mentioned here that phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), an impurity-doped polycrystalline silicon film, a silicon nitride film, a laminated film of some of the foregoings, or the like may be employed in place of the oxide film 5. Further, in the present embodiment the silicon film 8 having a micro roughness in Fig. 10f was subjected as it is to an RIE. However, if there should be any apprehension about losing the micro roughness on the side faces in the etching, it is possible to certainly protect the micro roughness on the side faces by thinnly covering the entire surface with an SiO 2 film by means of high temperature oxidation (HTO) CVD prior to subjecting the sample to the RIE. The SiO 2 film that remains on the side faces after the RIE needs only be removed by wet etching or the like method. Further, in the present embodiment described in the above, the polycrystalline silicon film 6 formed at the temperature of 640°C (600°C) was used as a film for replicating the micro roughness on the silicon film 8, but the film 6 may be replaced by a silicon film deposited at or below the transition temperature. Moreover, in Embodiments 1 to 4, thermal diffusion was employed invariably for the doping to the silicon film, but there may be used ion implantation or a method in which a dopant gas such as PH 3 or AsH 3 is included in the material gas at the time of deposition may also be employed. Moreover, the dopant may be boron besides phosphorus and arsenic. Furthermore, in Embodiments 1 to 4, an example has been shown in which a micro roughness is formed allover the surface of the portions of the silicon films 6 and 8 that are to become a capacitor, but the capacitance will become larger than the case of the conventional flat polycrystalline silicon film even when the micro roughness is formed even in a portion of the film. A silicon film having surface with a micro roughness can also be formed by first forming an amorphous silicon layer on a substrate, then by annealing the amorphous silicon layer at a temperature above the transition temperature. This phenomenon will be described by reference to Fig. 12. First, a flat a-Si film 12 is deposited on a substrate such as a silicon substrate whose surface is covered with an SiO 2 film as shown in Fig. 12a. When the sample is annealed in a vacuum higher than 1 x 10 -6 Torr or in an inest gas at a temperature above the transition temperature while maintaining the substrate surface clean, polycrystalline silicon nuclei 13 are formed on the surface as shown in Fig. 12b. The diffusion rate of silicon on the clean a-Si surface is extremely high compared with the growth rate of the a-Si solid phase, and silicon atoms are collected around the polycrystalline silicon nuclei formed on the surface by their diffusion in the surface, and the polycrystalline silicon nuclei 14 grow in mushroom like shape or hemisphere like shape as shown in Fig. 12c. The growth of the nuclei 14 are continued. Finally as shown in Fig. 12d the nuclei become the grains 15 which have hemisphere like shape. The annealing temperature for the forming of the micro roughness on the Si surface will not give any substantial influence provided that it is above the transition temperature. However, rapid heating at a high temperature of such as 900°C is not recommended. This is because under such an annealing, crystallization start from not only the surface of the amorphous silicon film 12 but also the interior of it, making it impossible to grow the nuclei and obtain a substantial micro roughness on the surface. It is necessary to grow polycrystalline silicon nuclei 13 first on the surface of the amorphous silicon film 12. For that purpose, it is preferable that the annealing is given in the range of 580 to 750°C. However, it is possible to raise the temperature of annealing after polycrystalline silicon grains 14 are grown once on the surface of the amorphous silicon layer 12. Accordingly, if annealing is given starting with an ordinary room temperature with a predetermined gradient of temperature rise as in the case of heating with lamp, it is possible to raise the temperature to a final temperature of 800 or 900°C, thereby decreasing the time for conversion to polycrystalline silicon. Further, as is clear from the above description, it is possible to change the average size and the density of the grain projections formed from the surface of the amorphous silicon surface by changing the temperature of the heat treatment the amorphous silicon film in a nonoxidizing atmosphere, such as in a vacuum, in an inert gas or nitrogen gas. As described in the above, for the growth of silicon grains from the surface of the amorphous silicon film it is first necessary to form nuclei which will act as the seeds for growing grains on the surface of the amorphous silicon film. The heating temperature substantially changes the density at which these nuclei are formed. When the heating temperature is high, this density becomes high, and the average size of the grain projections formed on the surface of the silicon film becomes small and the density of the projections becomes high. When the heating temperature is low, the density of nucleus generation is low. Because of this, the number of silicon atoms supplied to each nuclei at the time of grain growth becomes high compared with the heating at high temperature. Accordingly, in the case of heating at low temperature, each grain grows into large size, making the average diameter of the projections large and the density the projections becomes small. Moreover, the average size and the density of the grain projections formed from the surface of the amorphous silicon film, at the time of forming a micro roughness through the formation of silicon nuclei from the surface of the amorphous silicon film, can also be changed by varying the rate of temperature rise in the vicinity of the temperature of silicon nuclei formation. Moreover, the average size and the density of the grain projections formed from the surface of the amorphous silicon surface can also be changed by varying the hydrogen concentration within the amorphous silicon film instead of controlling the grain size by changing the heating temperature. Now, there exist many dangling bonds in the amorphous silicon film. These dangling bonds can be terminated by means of hydron atoms. At the time of formation of the nuclei on the surface of the amorphous silicon film, these hydrogen atoms drop off, bringing some of silicon atoms to stably bonded state. Accordingly, when hydrogen is added at high concentration, the generation density of the nuclei becomes low, each grain grows in large size, and the average diameter of the projections becomes large and the surface grain density becomes low. When the concentration of hydron addition is made low, the generation density of the nuclei becomes high, the average diameter of the grain projections becomes small and the density becomes high. Further, it is also possible to form a micro roughness on the surface by adding conductive impurities such as phosphorus, arsenic, or boron to the amorphous silicon film. Namely, silicon atoms can also sufficiently freely migrate in the surface of the amorphous silicon film when impurities are added to the amorphous silicon film, and a phenomenon analogous to the case not adding impurities to the amorphous silicon layer can be induced. As in the above, a polycrystalline silicon film having surface with a micro roughness can also be formed by the aforementioned methods. However, it should be noted that a roughness cannot be formed on the surface even if the sample is subjected to an annealing when the surface of the amorphous silicon film 12 is covered with a native oxidized film or impurities such as carbon atoms are attached to the surface. Consequently, when the film 12 is to be processed to a predetermined shape subsequent to the formation of the film 12, annealing has to be given following the formation of the surface of the amorphous silicon film after the processing, although there will be no problem if the formation of the amorphous silicon film 12 and the subsequent annealing are carried out in the same furnace tube. In what follows embodiments that employ the method described in the above and their effect will be described. Embodiment 5 An amorphous silicon film was formed using a molecular beam epitaxy (MBE) apparatus that is equipped with an electron gun type silicon evaporator with a volume of 40 CC. For the sample wafer, use was made of a 4-inch n-type silicon (100) substrate on which is formed a 2000 Å-thick SiO 2 film by thermal oxidation. After an RCA washing the sample wafer is transferred to the interior of a formation chamber, and a cleaning was given by heating it at 800°C for one minute. After lowering the substrate temperature to room temperature, the sample was irradiated with a silicon molecular beam of 7Å/s from the electron gun type silicon evaporator to form a 2000 Å-thick a-Si layer on the oxide film. The a-Si layer was converted to a polycrystalline silicon layer by heating the substrate in a vacuum higher than 1 x 10 -6 Torr, in an inert gas or in a N 2 gas with impurity concentration equivalent to that degree of vacuum, by heating the substrate in the same vacuum chamber. Whether the polycrystallization was accomplished or not was judged by an in-situ observation by RHEED technique. The substrate formed was taken out into the atmosphere, and it was evaluated by observing the cross section by means of the transmission electron microscopy (TEM). A lower electrode for a stacked capacitor was formed under the same conditions as in the present embodiment. Namely, a wafer with an a-Si layer formed on an SiO 2 film that covers a silicon substrate was taken out of an apparatus, and was processed into a cylindrical form as shown in Fig. 13(a). The processed a-Si layer was covered with and this oxidized film was removed, from the surface of the a-Si layer and its surface was cleaned. And the substrate was subjected to an annealing in an argon atmosphere. As a result, there was obtained a polycrystalline silicon film having surface with a micro roughness as shown in Fig. 13(b). A capacitor was manufactured by forming a 100 Å-thick oxide film on the polycrystalline silicon film thus formed, and its capacitance was measured. Fig. 14 shows the dependence of the capacitance on the annealing temperature after the deposition of the a-Si film for the case of taking the sample out into the atmosphere before the annealing and the case of not doing so. As shown in Fig. 14, when the sample was not taken out into the atmosphere, a capacitance which is about twice as large that of the case of taking it out into the atmosphere was obtained for a very wide range of annealing temperature, after the a-Si film was annealed. This indicates that by annealing the surface area became about twice as large due to the formation of a hemispherical micro roughness on the surface. On the other hand, when the sample was taken out once into the atmosphere and an oxide film was formed on the a-Si film, the capacitance does not increase by annealing, remaining at substantially the same value as at immediately after the formation of the a-Si film. The a-Si film covered with an oxide film have the similar capacitance value to a polycrystalline silicon film which is used directly to form a lower electrode according to the conventional method. Although the annealing was given in an argon atmosphere in the present embodiment, it can be given in helium (He), in nitrogen (N 2 ) or in a vacuum of higher than 1 x 10 -6 Torr. In addition, the present embodiment can be applied to a silicon on sapphire (SOS) substrate or a silicon on insulator (SOI) substrate instead of to a silicon substrate. Moreover, in the present embodiment, the a-Si layer was formed in an MBE apparatus using an electron gun type silicon evaporation device. Moreover, it is also noted that a phenomenon similar to the above occurs also in other methods of a-Si layer formation such as a gas source MBE method, an LPCVD method and a sputtering method provided that the a-Si layer surface is clean. Embodiment 6 The present embodiment will be described in its application to the electrode of simple cubic structure as in Embodiment 1. First, as shown in Fig. 15(a), an oxide film 17 was formed on a silicon substrate 16 and applied a resist 18 on the surface to be patterned. Then, the oxide film 17 was given a dry etching (Fig. 15(b)). Then, as shown in Fig. 15(c), a polycrystalline silicon 19 was deposited and an impurity such as phosphorus or arsenic was doped by thermal diffusion. The polycrystalline silicon film 19 was deposited by an LPCVD method under the ordinary conditions of a temperature of 600°C and a pressure of 1 Torr using a mixed gas of SiH 4 and He (at 20 vol % of SiH 4 and 80 vol % of He). An amorphous silicon film 20 was deposited on top of it at 500°C. The growth conditions other than that of the temperature are the same as for the case of deposition of the polycrystalline silicon film at 600°C. The amorphous silicon film was coated with a resist 21 and patterned (Fig. 15(c)). Then the amorphous silicon film 20 and the polycrystalline silicon film 19 were dry etched using the resist 21 as a mask (Fig. 15(d)). After removal of the resist 21 an amorphous silicon film 22 was deposited by an LPCVD method to a thickness of 2000 Å (Fig. 15(e)). The deposition conditions were a temperature 510°C, a mixed gas of SiH 4 and He (at 20 vol % of SiH 4 and 80 vol % of He) and a pressure of 1 Torr. Then, the amorphous silicon film 22 was processed by RIE to form an electrode (Fig. 15(f)). Following the above, the surface was washed with a mixed solution of ammonia and hydrogen peroxide in order to remove carbon contamination on the amorphous silicon film 22, and further, a natine oxide film was removed using HF or etching. Then, the sample was introduced into a vacuum of 1 x 10 -7 Torr to be heated at 600°C for one hour. As a result of the heat treatment, a micro roughness was formed on the electrode surface (Fig. 15(g)). Next, the electrode was heated at about 800°C. By this treatment, a conductive impurity such as phosphorus or arsenic is injected from the lower electrode into the silicon film that has a micro roughness. After that, a capacitor insulating film 23 and an upper electrode 24 were formed (Fig. 15(h)). The factor of surface area increase of the capacitor formed as in the above is very high being about 2.1 times that of a silicon film deposited in accordance with the conventional method. Embodiment 7 In the fabrication method of Embodiment 6 carbon atoms may have a chance of being attached to the surface of the amorphous silicon film after the RIE treatment. If carbon atoms remain on the amorphous silicon surface, a micro roughness will not be formed on the surface of the amorphous silicon even if it is heated in vacuum. Because the surface migration of the silicon atoms is restrained by the carbon atoms. These carbon atoms may be removed by washing with a mixed solution of ammonia and hydrogen peroxide. However, by employing a method of removing carbons by reduction at a low temperature by means of an optical surface treatment (using a mercury lamp of wavelength of 200 to 400 nm and intensity of 110 mW/cm 2 at pressure of 1 Torr) that employs ozone gas a cleaner silicon surface can be obtained in a simple manner. Following the above treatment it is possible to start crystallization from the surface of the amorphous silicon film and to form a dense micro roughness on the surface of the silicon film by removing the spontaneously oxidized film and then subjecting the sample to a heat treatment in a vacuum or in a nonoxidizing atmosphere such as that of an inert gas. The relevant mechanism is illustrated in Fig. 16. Instead of the optical surface treatment method using ozone gas that was employed in the embodiment 7, an optical surface treatment method that uses a halogen gas may be adopted to simultaneously remove carbons, the spontaneously oxidized film and the portions of the silicon film sustained damage by the RIE from the amorphous silicon film after the RIE. Chlorine gas may be used as the halogen gas. Further, the lamp to be used may be a mercury lamp of wavelength 300 to 400 nm operated at 200 m Torr and power of 110 mW/cm 2 . After this optical surface treatment, by subjecting the amorphous silicon film to a heat treatment in a vacuum or in a nonoxidizing atmosphere such as that of an inert gas, crystallization can be started from the amorphous silicon surface and to form a dense micro roughness on the surface of the silicon film. Embodiment 8 Although the formation of a micro roughness all over the electrode of the stacked capacitor as in the above is an effective method for increasing the effective surface area. But it is not always advantageous to form the micro roughness all over the surface for the reason of the structure of the device. Under these circumstances, there will be proposed a fabrication method which makes it possible to selectively grow a micro roughness only at those locations where the formation of the micro rougness is desired. The fabrication method will be described below with a dual cylinder structure as an example. First, as shown in Fig. 17(a), a silicon nitride film 25 and an oxide film 17 were formed on a silicon substrate 16. Then a resist 26 was applied to the surface and patterned. Then the oxide film 17 and the silicon nitride film 25 were dry etched, as shown in Fig. 17(b). The resist 16 was removed. A polycrystalline silicon film 27 was deposited as shown in Fig. 17(c) by an LPCVD method under the ordinary conditions of a temperature of 600°C, a reaction gas which is a mixture of SiH 4 and He (at 20 vol % of SiH 4 and 80 vol % of He) and at a pressure of 1 Torr. Then an impurity such as phosphorus or arsenic was doped by thermal diffusion. An high temperature oxide (HTO) CVD oxide film 28 was deposited on top of it to a thickness of 4000 Å under the deposition conditions of a temperature of 600°C, a reaction gas which is a mixture of SiH 4 , He (at 20 vol % of SiH 4 and 80 vol % of He) and N 2 O gas (in the flow rate of one in SiH 4 + He to five in N 2 O) and a pressure of 1 Torr. A resist 29 was applied on the surface of the oxide film 28 and then patterned (Fig. 17(c)). The oxide film 28 was dry-etched using the resist 29 as a mask. Then the resist 29 was removed and an amorphous silicon film 30 was deposited to a thickness of 1500 Å (Fig. 17(d)). Following the above, the amorphous silicon 30 and a part of polycrystalline silicon film 27 was processed by RIE to form an electrode (Fig. 17(e)). Then, the carbon contamination on the amorphous silicon film was removed by washing with a mixed solution of ammonia and hydrogen peroxide. Then the spontaneously oxidized film was removed by using HF. Next, the sample was introduced to a vacuum of 1 x 10 -7 Torr and was subjected to a heat treatment at 600°C for one hour. A micro roughness was formed on the electrode surface by this heat treatment (Fig. 17(f)). Then the oxide film 28 between the pieces of the electrode 31 was removed by wet etching by using a mixed solution of HF and water in the ratio of 1 to 100. Finally, a capacitor was completed by depositing a capacitor insulating film 32 and a phosphorus-doped polycrystalline silicon film 33 (Fig. 17(g) and 17(h)). Embodiment 9 This embodiment shows the method for fabricating cylinder like shaped electrode having micro roughness on the surface. This electrode serves as a stacked capacitor electrode. First, as shown in Fig. 18a, a silicon oxide film 17 is formed on a silicon substrate 16. Then a silicon nitride film 34 is formed on the silicon oxide film 17 and a resist 18 is coated on this film 34 and patterned. Using the patterned resist 18 as a mask, the silicon nitride film 34 and the silicon oxide film 17 are etched by dry etching, and thereafter the resist 18 is removed (Fig. 18b). Next, as shown in Fig. 18c, a polycrystalline silicon film 19 is deposited, and an impurity such as phosphorus or arsenic is doped by thermal diffusion. Then the polycrystalline silicon film 19 is etched back till the upper surface of the silicon nitride film 34 is exposed, and it is remained only in the through hole of the silicon oxide film 17. Then an amorphous silicon film 35 is deposited on the silicon nitride film 34 and a silicon oxide film 36 is deposited by the CVD method at the temperature of 550°C (510°C). The thickness of the silicon oxide film 36 is defined by the height of the desired electrode. Next, as shown in Fig. 18c, a resist 37 is coated on the silicon oxide film 36 and patterned. Using the resist 37 as a mask, the silicon oxide film 36 and the amorphous silicon 35 are etched by dry etching and the resist 37 is removed (Fig. 18d). Then, an amorphous silicon film 37 is deposited on the silicon oxide film 36 and the amorphous silicon film 35 by the same fabrication method of the amorphous silicon film 35 (Fig. 18e). Then, the amorphous silicon film 37 is etched back till the top surface of the silicon oxide film 36 is exposed (Fig. 18f). Then the silicon oxide film 36 is removed by the HF process. But this process produce a native oxide film on the amorphous silicon 35, 37. To remove the native oxide film, this film is mashed with a mixed solution of ammonia and hydrogen peroxide and mashed with the solution of HF. After this cleaning of the amorphous silicon surface, the sample is annealed under the condition of a temperature of 600°C, a pressure of 1 Torr and an annealing time of 10 minutes. By this treatment, the amorphous silicon 35, 37 become a polycrystalline silicon 38 have the micro roughness on its surface (Fig. 18g). Fig. 19 is a scanning electron microscopy photograph of the real sample of Fig. 18g. After this sample is taken out in air, the sample is ion implanted under the condition of a concentration of phosphorus 10 20 atoms/cm 3 and a angle of incidence 7 degrees, so that the surface part of the polycrystalline silicon 38 contains high concentration of phosphorus. Then the sample is annealed at a temperature of 800°C to activate the impurity of phosphorus and treatment for the lower electrode of a stacked capacitor is completed. Then, like embodiment 1, a capacitor insulating film 39 is formed on the polycrystalline silicon 38 and a phosphorus-doped polycrystalline silicon film 40 is deposited (Fig. 18h). In this embodiment 9, the silicon nitride film 34 may be omitted and the amorphous silicon film 35 may be deposited on the surface of the silicon oxide film 17. It should be mentioned that the shape of the storage electrode with a micro roughness for a stacked capacitor may be a plain cubic structure, a cylindrical structure, a fin-type structure or a stacked trench type.

Claims: A semiconductor device comprising a polycrystalline silicon layer, a dielectric layer formed on said polycrystalline silicon layer, and a conductive layer formed on said dielectric layer, said polycrystalline silicon layer having a top surface and a side surface, both of said top surface and said side surface being made uneven with a plurality of convex portions, each of said convex portions being defined by a hemispherical like shape silicon grain. The device as claimed in claim 1, wherein said hemispherical like shape silicon grain has a diameter in a range of 30 to 170 nm. A semiconductor device comprising a polycrystalline silicon layer, a dielectric layer formed on said polycrystalline silicon layer, and a conductive layer formed on said dielectric layer, said polycrystalline silicon layer having a top surface and a side surface, said top surface being made uneven with a plurality of convex portions, each of said convex portions being defined by a silicon grain of a mushroom like shape. The device as claimed in claim 3, wherein said mushroom like shape silicon grain has a diameter in range of 30 to 170 nm. The device as claimed in claim 3, wherein said side surface of said polycrystalline silicon layer is made uneven with a plurality of convex portions, each of said convex portions being defined by a silicon grain of a mushroom like shape. A semiconductor device comprising a polycrystalline silicon layer, a dielectric layer formed on said polycrystalline silicon layer, and a conductive layer formed on said dielectric layer, said polycrystalline silicon layer having an uneven surface including a plurality of convex portions, each of said convex portions being defined by a silicon grain of a mushroom like shape, said silicon grain has a first diameter defining a stem of said mushroom like shape and a second diameter defining a bulging portion of said mushroom like shape, said first diameter being smaller than said second diameter. The device as claimed in claim 1, wherein said polycrystalline silicon layer, said dielectric layer and said conductive layer are employed as a lower electrode, a dielectric and an upper electrode of a capacitor in a dynamic memory cell, respectively. The device as claimed in claim 3, wherein said polycrystalline silicon layer, said dielectric layer and said conductive layer are employed as a lower electrode, a dielectric and an upper electrode of a capacitor in a dynamic memory cell, respectively. The device as claimed in claim 5, wherein said polycrystalline silicon layer, said dielectric layer and said conductive layer are employed as a lower electrode, a dielectric and an upper electrode of a capacitor in a dynamic memory cell, respectively. A semiconductor capacitor formed on a substrate comprising: a first electrode having a plurality of mushroom like shaped convex silicon grains creating an uneven surface; a dielectric layer formed on said first electrode with a thickness such that a pair of opposing surfaces of said dielectric layer are substantially parallel and substantially replicate said uneven surface of said first electrode; a second electrode formed on and conformal to said dielectric layer is insulated from said first electrode, whereby capacitance between said first electrode and said second electrode is increased by said mushroom like shape silicon grains of said uneven surface. The device as claimed in claim 10, wherein said silicon grain has a first diameter defining a stem of said mushroom like shape and a second diameter defining a bulging portion of said mushroom like shape, said first diameter being smaller than said second diameter. The device as claimed in claim 11, wherein said dielectric thickness is in the range of 30 angstroms to 500 angstroms. The device as claimed in claim 12, wherein said dielectric is comprised of Si 3 N 4 and SiO 2 . The device as claimed in claim 13, wherein said second electrode is made of polycrystalline silicon. The device as claimed in claim 10, wherein said increased capacitance is at least two times the capacitance of a capacitor with a first electrode having an ordinary polycrystalline silicon surface.

Inventors: TATSUMI TORU, WATANABE HIROHITO, TATSUMI, TORU, WATANABE, HIROHITO
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: H01L29
IPC codes: H01L27, H01L21