Signal retiming apparatus

Abstract: A digital signal data retiming and clock extraction apparatus including a series of three data latches (111, 121, 131), connected in cascade, means for applying digital data signals to the first latch, means for clocking (701) the first and third latches in phase with the data signals input to the first latch, means for clocking the second latch in antiphase with the data signals input to the first latch, coincidence detection means (201) to which are applied the digital data signal (A) input to the first latch, the data signals output (B) of the second latch and the data signals output (C) of the third latch, the coincidence detection means being arranged to derive output data signals (X) in accordance with the algorithm X = B. (A-C), and a first phase lock loop feedback means (Q1, Q2, 301) whereby the output data signals (X) of the coincidence detection circuit control the timing of the clocking means to maintain the phase relationship with the digital data signals input to the first latch.

Description: This invention relates to a signal data retiming and clock extraction apparatus, such as is used for retiming digital signals received from an optical transmission link. Typically a digital data signal transmitted via an optical link may be a high bit rate non-return-to-zero (NRZ) signal. A requirement exists for generating at a receiver a local clock signal, phase locked to the incoming data, and retiming the data using the local clock to provide emitter coupled logic (ECL) compatible regenerated clock and data signals as outputs for subsequent equipments. The clock extraction process should provide for minimal jitter transfer function gain and minimal self generated jitter while also being tolerant of high levels of incoming data jitter and long strings of ones or zeros. An alarm indication of loss of clock synchronisation is also desirable (loss of data excepted). US patent 4,535,459 (Hogge, Jr.) discloses a phase detection function obtained by performing two series timing operations on a data input signal in accordance with a local clock and exclusive-OR'ing the signals involved in the two retiming operations. The combination of the two signals can then be used to provide an indication of phase of the clock with respect to the data. Utilising the phase detected signal a voltage controlled oscillator (VC0) can be employed to provide the clock input to the retiming means the circuit can provide not only data regeneration but also clock recovery from the data input. In the circuits disclosed the two data retiming operations are performed utilising two D-type flip-flops in series, the input and output of each flip-flop being the two inputs to a respective OR gate. According to the present invention there is provided a digital signal data retiming and clock extraction apparatus including a series of three data latches, as hereinafter defined, connected in cascade, means for applying digital data signals to the first latch, means for clocking the first and third latches in phase with the data signals input to the first latch, means for clocking the second latch in antiphase with the data signals input to the first latch, coincidence detection means to which are applied the digital data signals (A) input to the first latch, the data signals output (B) of the second latch and the data signals output (C) of the third latch, the coincidence detection means being arranged to derive output data signals (X) in accordance with the algorithm X = B. (A-C), and a first phase lock loop feedback means whereby the output data signals (X) of the coincidence detection circuit control the timing of the clocking means to maintain the phase relationship with the digital data signals input to the first latch. In a preferred embodiment of the invention the means for clocking the latches comprises a voltage controlled oscillator (VCO) and the first phase lock loop feedback means includes means for deriving from the output signals (X) of the coincidence detection circuit an error signal voltage which is applied to a control input of the VCO to control the frequency of the VCO to maintain the VCO output in phase with the digital data signals (A) input to the first latch. Embodiments of the invention will now be described with reference to the accompanying drawings, in which Fig. 1 is a general schematic circuit diagram of a digital data signal retiming and clock extraction apparatus, Fig. 2a and 2b illustrate the construction of D-type flip-flop and a data latch respectively, Fig. 3 is a schematic circuit diagram of the coincidence detection circuit of Fig. 1, and Fig. 4 is a schematic circuit diagram of part of a frequency acquisition locking loop shown in Fig. 1. In the arrangement shown in Fig. 1 generally, a balanced digital data signal IP, IP- is fed via an input buffer 101 to a set of three data latches 111, 121 and 131 connected in cascade. The output of latch 131 is fed via an output buffer 141 as one input to a 3-input coincidence detection circuit 201. The two other inputs to circuit 201 are the output of the input buffer 101 (i.e. effectively the input data signal) and the output of latch 121. The outputs of latch 121 and buffer 141 are effectively delayed and retimed versions of the signal input to latch 111. The coincidence detection circuit 201 is arranged to produce a balanced output signal X, X- in accordance with the general algorithm X = B. (A-C) where A identifies the output of buffer 101, B identifies the output of latch 121, and C identifies the output of buffer 141. The output of latch 121 also forms, via amplifier 511, the balanced digital data output OP, OP- of the retiming circuit for feeding to other equipment (not shown). The data latches 111, 121 and 131 are each effectively defined as one half of a conventional D-type flip-flop, as will be seen from Figs. 2a and 2b. The circuit of Fig. 2a functions as a data latch in as much as it is "transparent" to data on its input terminals D, D- when the clock is "true", i.e. when CK = 1 and CK-= 0. The latch remains latched in its last data state when CK goes to 0 and CK- goes to 1. The conventional D-type flip-flop of Fig. 2b consists essentially of two latches in cascade which are clocked in opposite phase. The input data state at D, D- is transferred to the output Q, Q- at the instant of CK going from 1 to 0, but it is never transparent. When two D-type flip-flops are cascaded the middle two latches, i.e. the second latch of the first flip-flop and the first latch of the second flip-flop, are clocked in phase, so that they are both transparent at the same time. Therefore the first latch of the second flip-flop becomes redundant, effecting a significant saving of circuitry when implemented as an integrated circuit. For the purposes of Fig. 1, therefore, the first half of the second flip-flop can be omitted. The result is as indicated with latches 111 and 131 being clocked in phase and latch 121 being clocked in antiphase. Buffers 101 and 141 are not clocked logic circuits. The operation of the coincidence detection circuit 201 is now described with reference to Fig. 3. Transistors 218 and 215 perform a differential function between the inputs A, A- and likewise transistors 206, 203 perform the same differential function between the inputs C, C-. The collectors of 206 and 215 are connected together, likewise the collectors of 203 and 218 so that the general function of (A-C) is performed. The resultant signals are then fed to transistor pairs 213, 211 and 210, 208 where they are multiplied with the B, B- inputs. The current flowing at the outputs X, X- will therefore equal B.(A-C). In practice the function of the coincidence detector is properly written I(X) = B.(A-t.c) where t is a factor dependent upon the voltage at the TRIM input to the emitter of transistor 205. The outputs X,X- of coincidence detection circuit 201 form inputs to a first phase lock feedback loop. Clock extraction is achieved by the use of a damped second order phase locked loop. The local clock is generated by a push-pull voltage controlled oscillator (VCO) utilising an external coil or transmission line 701. Phase detection of the oscillator output with respect to the input data is provided by comparison of the time lag between data transitions and clock edges of a certain direction - effectively the transitions of signals A and B, and the time lag between signals B and C, always half a data bit period. The two outputs of the coincidence detector are differenced by differential amplifier 301 to provide an error voltage, with zero volts when the local clock negative transitions are synchronous with the incoming data edges. The loop filter comprises the high gain integrating amplifier 301 with the feedback components located off the integrated circuit chip. In addition to the first feedback loop the outputs X,X- also form inputs to a second, additional frequency acquisition loop. When the loop is out of lock and data signals are present at the input the coincidence detector circuit produces a beat note which is amplified by amplifier 311. The amplified beat note drives a charge pump which provides a slewing current to the integrating amplifier 301, in the manner described below. The VCO thus hunts over the full range of available tuning voltage. The slewing current is proportional to the magnitude of the frequency error and hence reduces to zero as the first feedback loop phase locks. The second frequency acquisition feedback loop referred to above includes the lock circuit 401 which is detailed in Fig. 4. The outputs X, X- are fed, via transistors Q4 and Q3 respectively to operational amplifier 311, the output of which will have a polarity dependent on the relative values of X and X-. When the output of amplifier 311 goes positive charge flows from capacitor C10 through the input referenced CPUMPZ and via transistor 410 to the terminal VEE. When the output of amplifier 311 goes negative charge is drawn through capacitor C10 via the emitter of transistor 406 from a reservoir capacitor CRES in Fig. 1, which is connected by terminal CR in Fig. 4. The voltage on the collector of transistor 406 will be applied to the emitters of transistors 403, 404. The current flowing in resistor R9 between the collector of transistor 406 and the emitters of transistors 403, 404 will be directly proportional to the frequency at which amounts of charge are drawn from capacitor C10. The currents flowing in transistors 403, 404 are applied, via terminals S1, S2, to the inputs of differential amplifier 301, Fig. 1. The resultant output of amplifier 301 is fed back via terminal IP of Fig. 4 and is compared with the output of amplifier 411. When the output of amplifier 301 has ramped to one extreme of its range amplifier 411 experiences a condition where the relative values of the two inputs reverse and the output of amplifier 411 swings sharply to the other extreme of its range. This causes the signal at the base of transistor 404, applied via transistor 405, to change relative to the reference signal at the base of transistor 403. The resultant signal applied via resistor R9 to the collector of transistor 406 and the reservoir capacitor CRES is a sawtooth waveform. If there were a constant frequency applied to the capacitor C10 a sawtooth waveform would be generated at the output of amplifier 301. This sawtooth waveform at CV is a control voltage for varicap diodes in the voltage controlled oscillator 701, Fig. 1, which provides the local clock CK, CK-. As synchronisation of the circuit with the input data IP, IP- is gained, the rate of exchange of voltage with time at CV is reduced until it reaches zero, at which time full synchronisation has been achieved. Transistors 407 and 409, Fig. 4, provide a signal for a synchronisation loss alarm at terminal SLA.

Claims: A digital signal data retiming and clock extraction apparatus including a series of three data latches (111, 121, 131) connected in cascade, means (101) for applying digital data signals to the first latch (111), means for clocking (701) the first and third latches in phase with a locally generated clocking means, means for clocking the second latch in antiphase with the locally generated clocking means, coincidence detection means (201) to which are applied the digital data signals A input to the first latch, the data signals output B of the second latch and the data signals output C of the third latch, the coincidence detection means being arranged to derive output data signals X in accordance with the algorithm X = B. (A-C), and a first phase lock loop feedback means (Q1, Q2, 301) whereby the output data signals X of the coincidence detection circuit control the timing of the clocking means (701) to maintain the phase relationship with the digital data signals input to the first latch. An apparatus according to claim I characterised in that the data signals are balanced digital data signals and the outputs of the latches and the coincidence detection means are balanced outputs. An apparatus according to claim 2 characterised in that the means for clocking the latches comprise a voltage controlled oscillator (VCO) and the first phase lock loop feedback means includes means for deriving from the output signals (X) of the coincidence detection circuit an error signal voltage which is applied to a control input of the VCO to control the frequency of the VCO to maintain the VCO output in correct phase relationship with the digital data signals (A) input to the first latch. An apparatus according to claim 3 including a second feedback loop means comprising means for detecting an out of phase imbalance between the balanced output signals of the coincidence detection means to produce a beat note signal, charge pump means to which is applied the beat note signal to form a slewing current, integration means to which the slewing current is applied, means for reversing the sign of the slewing current when the slewing current integral value approaches either one of two predetermined values and means for adding the slewing current to the first feedback loop means.

Inventors: MAYO RICHARD HAMOND, TIPPER ALAN, MAYO, RICHARD HAMOND, TIPPER, ALAN
Applicants: NORTHERN TELECOM LTD, NORTHERN TELECOM LIMITED
Application year: 1991
Main classification: H04L7
IPC codes: H04L7