A driving method and a driving device for a display device

Abstract: A liquid crystal display panel (1) is so constructed that a plurality of pixels (2) are arranged in a matrix form having the number of lines twice that of horizontal scanning lines for one field of interlaced scanning video signals (VID) obtained by scanning an original image every other line, the arrangement of the pixels (2) being shifted horizontally by one-half of a pixel (2) between adjacent upper and lower lines. A row driving circuit (7) applies, to the pixels (2) in the upper line of the two adjacent upper and lower lines, data voltages obtained by sampling a video signal (VID) representing one horizontal scanning line by a clock signal (SCK) of the timing that matches the number of pixels (2) in the upper line and the arrangement of the pixels (2), and applies, to the pixels (2) in the lower line, data voltages obtained by sampling the above video signal (VID) representing one horizontal scanning line by a clock signal of the timing shifted by 1/2 cycle from the above clock signal (SCK). Thus, one horizontal scanning line represented by the video signal is displayed using the two upper and lower lines of pixels (2), thereby enhancing the display quality of the produced image.

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method and a driving device for a display device such as a liquid crystal display device which displays an image by sequentially driving pixels arranged in a matrix form. 2. Description of the Prior Art A method as described below has heretofore been employed, for example, to display an image on an active matrix driving liquid crystal display or the like by using interlaced scanning television video signals obtained by scanning the original image every other line. Reference is made here to the disclosure of JP-B-52-15170. When the interlaced scanning television video signals use, for example, 240 horizontal scanning lines per field, pixels are arranged in 240 lines, the number of lines corresponding to that of horizontal scanning lines, on the liquid crystal display panel of the liquid crystal display device, in which a video signal representing one horizontal scanning line is sampled by a clock signal of the timing that matches the number of pixels per line and the arrangement of the pixels so that data voltages obtained by sampling are applied to the corresponding pixels in a particular line. This operation is sequentially performed on all lines of pixels to complete the display of an image for one field. In this case, the video signal representing, for example, the first horizontal scanning line of an odd-numbered field and the video signal representing the first horizontal line of an even-numbered field both use the pixels in the same first line to display on the liquid crystal display panel, not interlaced with each other for display. Fig.1 is a diagram illustrating the interlaced scanning video signals conceptually arranged in the form of an original image to explain the above driving method in a specific manner. In Fig.1, the original image is horizontally scanned eight times, the first, third, fifth, and seventh horizontal scans producing video signals for the odd-numbered field and the second, fourth, sixth, and eighth scans producing video signals for the even-numbered field. Fig.2 is a conceptual diagram illustrating an image reproduced from the interlaced scanning video signals and displayed on an interlaced scanning display device. The image on the display device comprises ten pixels per line, the number of lines being set to eight to match the number of scans of the original image. Also, the pixels are arranged in such a manner as to be shifted horizontally by one-half of a pixel between the odd-numbered and even-numbered lines. In using the interlaced scanning video signals with the display device shown in Fig.2, the sampling of a video signal representing one horizontal scanning line in an odd-numbered field is performed at the timing of sampling A indicated by "•" in Fig.1 in accordance with the arrangement of the pixels in the odd-numbered lines, while the sampling of a video signal representing one horizontal scanning line in an even-numbered field is performed at the timing of sampling B indicated by "o" in Fig.1 in accordance with the arrangement of the pixels in the even-numbered lines. That is, in the displayed image of Fig.2, the pixels in the first line, for example, are used, in the odd-numbered field, to display the first horizontal scanning line of the original image represented by the video signal sampled at the timing of sampling A, while the pixels in the second line are used. in the even-numbered field, to display the second horizontal scanning line of the original image represented by the video signal sampled at the timing of sampling B. Fig.3 is a conceptual diagram illustrating an image reproduced from the interlaced scanning vidco signals and displayed on a liquid crystal display panel. Fig.3(1) shows the displayed image of an odd-numbered field. Fig.3(2) shows the displayed image of an even-numbered field, and Fig.3(3) shows an image produced by superposing the odd-numbered field image on the even-numbered field image. The displayed image shown in Fig.3 comprises ten pixels per line, the number of lines being set to four to match the number of horizontal scanning lines for one field of the interlaced scanning video signals. That is, the liquid crystal display panel shown comprises four lines of ten pixels. In using the interlaced scanning video signals with the liquid crystal display panel shown in Fig.3, the display of an odd-numbered field is performed as shown in Fig.3(1): the pixels in the first line are used to display the first horizontal scanning line of the original image represented by the video signal sampled at the timing of sampling A, the pixels in the second line used to display the third horizontal scanning line of the original image.represented by the video signal sampled at the timing of sampling B, the pixels in the third line used to display the fifth horizontal scanning line of the original image represented by the video signal sampled at the timing of sampling A, and the pixels in the fourth line used to display the seventh horizontal scanning line of the original image represented by the video signal sampled at the timing of sampling B. On the other hand, the display of an even-numbered field is performed as shown in Fig.3(2): the pixels in the first line are used to display the second horizontal scanning line of the original image represented by the vidco signal sampled at the timing of sampling A, the pixels in the second line used to display the fourth horizontal scanning line of the original image represented by the video signal sampled at the timing of sampling B, the pixels in the third line used to display the sixth horizontal line of the original image represented by the video signal sampled at the timing of sampling A, and the pixels in the fourth line used to display the eighth horizontal line of the original image represented by the video signal sampled at the timing of sampling B. Thus, two types of sampling timing different from line to line are selected alternately according to the shifted arrangement of the pixels between the odd-numbered and even-numbered lines on the liquid crystal display panel. Thus, the image of the odd-numbered field shown in Fig.3(1) and the image of the even-numbered field shown in Fig.3(2) are displayed alternately on the liquid crystal display panel, producing a visual result as shown in Fig.3(3) in which the image of the odd-numbered field is superposed on the image of the even-numbered field. As described above, in the prior art driving method for displaying an image on a non-interlaced scanning display device using interlaced scanning video signals, the pixels in the same line are used to alternately display the image reproduced from the video signal of an odd-number field and the image reproduced from the video signal of an even-numbered field. As a result, the prior art has the problem that the display quality drops substantially compared with the display screen provided by an interlaced scanning display device. This tendency becomes even more appreciable as the size of the display screen becomes larger. In particular, in the case of displaying an image having diagonal lines as shown in Figs.1 to 3, a marked drop in the reproducibility of the diagonal lines is noted as is apparent from the comparison between Fig.2 and Fig.3(3). SUMMARY OF THE INVENTION It is an object of the invention to provide a driving method and a driving device for a matrix display device by which interlaced scanning video signals can be used with a non-interlaced scanning display device without causing degradation in the display quality. In one aspect, the present invention provides the method of driving a matrix display device defined by claim 1. In another aspect, the present invention provides the apparatus for driving a matrix display device defined by claim 3. According to the invention, one horizontal scanning line represented by the video signal is displayed using the pair of two adjacent upper and lower lines of pixels during one horizontal scanning period of the video signal, the operation being performed on all lines of pixels to complete the display of an image for one field. Furthermore, for the pixels in the upper line, the video signal correctly corresponding to each pixel is sampled at a timing which matches the arrangement of the pixels, while for the pixels in the lower line, the video signal correctly corresponding to each pixel is sampled at a timing which is shifted by the amount of shift of the pixel arrangement with respect to the upper line. Therefore, the image reproducibility is enhanced, resulting in a great improvement in the reproducibility of an image having diagonal lines as compared with the prior art. BRIEF DESCRIPTION OF THE DRAWINGS Fig.1 is a diagram illustrating interlaced scanning video signals conceptually arranged in the form of an original image; Fig.2 is a diagram illustrating an image reproduced from the interlaced scanning video signals and displayed on an interlaced scanning display device; Fig.3 is a diagram illustrating an image reproduced from the interlaced scanning video signals and displayed on a non-interlaced scanning display device using a prior art driving method; Fig.4 is a block diagram illustrating the schematic construction of a liquid crystal display device to which a driving method for a display device according to one embodiment of the invention is applied; Fig.5 shows waveforms of various signals in the liquid crystal display device shown in Fig. 4; Fig.6 is a timing chart showing the operation of a sampling circuit in the liquid crystal display device shown in Fig.4; and Fig.7 shows images displayed on the liquid crystal display device shown in Fig.4. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Fig.4 is a block diagram illustrating the schematic construction of an active matrix driving liquid crystal display device to which a driving method in one embodiment of the invention is applied. The liquid crystal display device shown is a display device which, without using an interlaced scanning method, displays an image using the interlaced scanning video signals previously illustrated in Fig.l. The liquid crystal display device has a liquid crystal display panel 1 in which a plurality of pixels 2 are disposed in eight lines corresponding to eight horizontal scanning lines of the video signals obtained by horizontally scanning the original image eight times. Each line consisting of ten pixels, the pixels 2 are arranged in a matrix form, totaling 10x8 in number. Also, the pixels 2 are arranged in such a way that the pixels 2 in the even-numbered lines are horizontally shifted to the right by one-half of a pixel with respect to the pixels 2 in the odd-numbered lines. Further, there are disposed in the liquid crystal display panel 1 thin film transistors 3 (hereinafter referred to as the TFTs) one each for one pixel 2. Via the TFTs 3, ten source lines 4, the number thereof corresponding to that of pixels per line, are respectively connected as data lines to the pixels in the corresponding rows. On the other hand, there are disposed, corresponding to the respective lines of pixels 2, eight gate lines 5 for sending scanning signals S1 to S8 to activate the TFTs 3 in the respective lines. Connected to the liquid crystal display panel 1 is a line (row) driving circuit 6 for sequentially specifying the respective lines of pixels 2 in accordance with the sequence of the lines. That is, the scanning signals S1 to S8 for activating the TFTs 3 are selectively supplied from the line driving circuit 6 to the gate lines 5 corresponding to the respective lines of pixels 2. Also connected to the liquid crystal display panel 1 is a column driving circuit 7 for applying to the respective source lines 4 data voltages D1 to D10 representing respective video signals. The column driving circuit 7 comprises a shift register 8 for storing a video signal representing one horizontal scanning line, a sampling circuit 9 for sampling the video signal held in the shift register 8 at the timing corresponding to the pixels 2 in each line on the liquid crystal display panel 1, and an output buffer 10 for outputting the data voltages D1 to D10 representing the sampled video signals to the respective source lines 4. A double speed converting circuit 11 contains a line memory that holds the incoming interlaced scanning video signal VID representing one horizontal scanning line, and has a function to compress the thus held video signal VID representing one horizontal scanning line to 1/2 timewise and to output the same video signal component twice during one horizontal scanning period H of the video signal VID to the shift register 8 in the column driving circuit 7. The double speed converting circuit 11 also has a function to convert a horizontal synchronizing signal HSY, which is input along with the video signal VID, into a double speed horizontal synchronizing signal 2HSY, which is a train of pulses recurring at a cycle 1/2H, i.e., at half the frequency of one horizontal scanning period H, and to output it to a control circuit 12. A vertical synchronizing signal VSY is also input to the double speed converting circuit 11, but the vertical synchronizing signal VSY is output in its original form without conversion and is supplied to the control circuit 12. The control circuit 12 is a circuit that controls the line driving circuit 6 and the column driving circuit 7 in accordance with the double speed hozizontal synchronizing signal 2HSY and vertical synchronizing signal VSY supplied from the double speed converting circuit 11. A sampling clock signal SCK for clocking the sampling is supplied from the control circuit 12 to the sampling circuit 9 in the column driving circuit 7. Fig.5 shows waveforms of various signals in the liquid crystal display device. Fig.5(1) shows the waveform of the interlaced scanning video signal VID that is input to the double speed converting circuit 11, Fig.5(2) shows the waveform of the horizontal synchronizing signal HSY that is input to the double speed converting circuit 11, Fig.5(3) shows the waveform of the vertical synchronizing signal VSY, Fig.5(4) shows the waveform of the double speed video signal 2VID that is output from the double speed converting circuit 11, Fig.5(5) shows the waveform of the double speed horizontal synchronizing signal 2HSY that is output from the double speed converting circuit 11, and Fig.5(6) to Fig.5(9) show the waveforms of the scanning signals S1 to S8 that are supplied to the respective gate lines 5 in the liquid crystal display panel 1 from the row driving circuit 6. Fig.6 is a timing chart illustrating the sampling operation in the column driving circuit 7. Fig.6(1) shows the waveform of the double speed video signal 2VID, Fig.6(2) shows the waveform of the double speed synchronizing signal 2HSY, and Fig.6(3) shows the waveform of the sampling clock signal SCK. Fig.7 provides diagrams conceptually illustrating images reproduced from the interlaced scanning video signal VID and displayed on the liquid crystal display panel 1. Fig.7(1) shows the displayed image of an odd-numbered field, Fig.7(2) shows the displayed image of an even-numbered field, and Fig.7(3) shows an image produced by superposing the odd-numbered field image on the even-numbered field. Referring to Figs.5 to 7, we will now describe the operation for displaying an image on the liquid crystal display device from the interlaced scanning video signal VID. As shown in Fig.5(1), the video signal VID that is input to the double speed converting circuit 11 comprises : video signals V1, V3, V5, and V7 representing the odd-numbered horizontal scanning lines of the original image for an odd-numbered field; and video signals V2, V4, V6, and V8 representing the even-numbered horizontal scanning lines of the original image for an even-numbered field. The video signal VID is held for every horizontal scanning line by the line memory (not shown) in the double speed converting circuit 11, and is compressed to 1/2 as shown in Fig.5(4). The compressed double speed video signal 2VID is output twice during one horizontal scanning period H. At the same time, the horizontal synchronizing signal HSY is also output after conversion into the double speed synchronizing signal 2HSY synchronizing with the double speed video signal 2VID, as shown in Fig.5(5). The double speed video signal 2VID which is output from the double speed converting circuit 11 is stored in the shift register 8 in the column driving circuit 7. For example, of the identical double speed video signals V1a and V1b shown in Fig.5(4) which are input at two different times during one horizontal scanning period H, the former double speed video signal V1a is sampled by the sampling circuit 9 during half the horizontal period, i.e. during the period of 1/2H, and during the next 1/2H period, the data voltages D1 to D10 representing the sampled signals are respectively applied to the corresponding source lines 4 in the liquid crystal display panel 1 by the output buffer 10. At this time, as shown in Fig.6(3), ten sampling clock signals SCK corresponding to the number of pixels per line are issued for each of the double speed video signals V1a and V1b. During the 1/2H period in which the output buffer 10 outputs the data voltages D1 to D10 representing the former double speed video signal V1a, the sampling of the latter double speed video signal V1b is performed, and during the next 1/2H period, the data voltages D1 to D10 representing the double speed video signal V1b are applied to the source lines 4. Thus, the timing at which the data voltages D1 to D10 representing the double speed video signal 2VID that is input to the column driving circuit 7 are applied to the source lines 4 is delayed by 1/2H from the input timing of the double speed video signal 2VID. The sampling clock signal SCK that is input from the control circuit 12 to the sampling circuit 9 in the row driving circuit 7 reverses its polarity at every 1/2H, as shown in Fig.6(3). Therefore, for example, of the identical double speed video signals V1a and V1b which are input at two different times to the column driving circuit.7 during one horizontal scanning period H, the former double speed video signal V1a is sampled at sampling points indicated by "•" in Fig.6(1), and the latter double speed video signal Vlb is sampled at sampling points indicated by "o". The sampling points "•" correspond to the sampling points A in Fig.1, while the sampling points "o" correspond to the sampling points B in Fig.1. That is, the sampling points "•" are chosen to match the arrangement of the pixels 2 in the odd-numbered lines in the liquid crystal display panel 1, while the sampling points "o" are chosen to match the arrangement of the pixels 2 in the even-numbered lines shifted to the right by one half of a pixel with respect to the odd-numbered lines. In the meantime, the scanning signals S1 to S8 for activating the TFTs 3 are applied from the row driving circuit 6 to the respective gate lines 5 in the liquid crystal display panel 1, as shown in Fig.5(6) to Fig.5(9). That is, the scanning signals S1 to S8 are sequentially applied to the gate lines 5 in accordance with the sequence of the lines and in synchronization with the application to the source lines 4 of the data voltages D1 to D10 representing the sampled double speed horizontal synchronizing signal 2HSY. For example, when the data voltages D1 to D10 representing the double speed video signal V1a shown in Fig.5(4) are applied to the source lines 4, the scanning signal S1 is applied from the row driving circuit 6 to the gate line 5 corresponding to the pixels 2 in the first line. Next, when the data voltages D1 to D10 representing the double speed video signal V1b are applied to the source lines 4, the scanning signal S2 is applied to the gate line 5 corresponding to the pixels 2 in the second line. The TFTs 3 on the gate line 5 to which the corresponding scanning signal is applied are turned on, causing the data voltages D1 to D10 applied at that time to the respective source lines 4 to be applied to the respective pixels 2 in the line corresponding to the gate line 5. Thus, starting with the first lH subsequent to the rising of the vertical synchronizing signal VSY indicating the start of a field, the lines of pixels 2 are sequentially selected from the first to the eighth line at the frequency of 1/2H, and when the data voltages D1 to D10 have been applied to the pixels in all the lines on the liquid crystal display panel 1, the display of one field is completed. That is, as shown in Fig.7(1), for an odd-numbered field, the first horizontal scanning line of the original image shown in Fig.1, represented by the video signal VID sampled at the timing of sampling A. is displayed using the first line of pixels 2 in the liquid crystal display panel 1, the same first horizontal scanning line of the original image shown in Fig.1, represented by the video signal VID sampled at the timing of sampling B, is displayed using the second line of pixels 2 in the liquid crystal display panel 1. the third horizontal scanning line of the original image shown in Fig.1, represented by the video signal VID sampled at the timing of sampling A, is displayed using the third line of pixels 2 in the liquid crystal display panel 1, the same third horizontal scanning line of the original image shown in Fig.1, represented by the video signal VID sampled at the timing of sampling B, is displayed using the fourth line of pixels 2 in the liquid crystal display panel 1, the fifth horizontal scanning line of the original image shown in Fig.1, represented by the video signal VID sampled at the timing of sampling A, is displayed using the fifth line of pixels 2 in the liquid crystal display panel 1, the same fifth horizontal scanning line of the original image shown in Fig.1, represented by the video signal VID sampled at the timing of sampling B, is displayed using the sixth line of pixels 2 in the liquid crystal display panel 1, the seventh horizontal scanning line of the original image shown in Fig.1, represented by the video signal VID sampled at the timing of sampling A, is displayed using the seventh line of pixels 2 in the liquid crystal display panel 1, and the same seventh horizontal scanning line of the original image shown in Fig.1, represented by the video signal VID sampled at the timing of sampling B, is displayed using the eighth line of pixels 2 in the liquid crystal display panel 1. Thus, every odd-numbered horizontal scanning line of the original image represented by the video signal VID is displayed using two lines of pixels 2 on the liquid crystal display panel 1, the sampling timing being shifted between the two adjacent upper and lower lines according to the arrangement of pixels 2 shifted by one half of a pixel between the upper and lower lines. This serves to enhance the reproducibility of an original image having diagonal lines such as the one shown in Fig.1. On the other hand, as shown in Fig.7(2), for an even-numbered field, the second horizontal scanning line of the original image shown in Fig.1, represented by the video signal VID sampled at the timing of sampling A, is displayed using the first line of pixels 2 in the liquid crystal display panel 1, the same second horizontal scanning line of the original image shown in Fig.1, represented by the video signal VID sampled at the timing of sampling B, is displayed using the second line of pixels 2 in the liquid crystal display panel 1. the fourth horizontal scanning line of the original image shown in Fig.1, represented by the video signal VID sampled at the timing of sampling A, is displayed using the third line of pixels 2 in the liquid crystal display panel 1, the same fourth horizontal scanning line of the original image shown in Fig.l, represented.by the video signal VID sampled at the timing of sampling B, is displayed using the fourth line of pixels 2 in the liquid crystal display panel 1, the sixth horizontal scanning line of the original image shown in Fig.1, represented by the video signal VID sampled at the timing of sampling A, is displayed using the fifth line of pixels 2 in the liquid crystal display panel 1, the same sixth horizontal scanning line of the original image shown in Fig.1, represented by the video signal VID sampled at the timing of sampling B, is displayed using the sixth line of pixels 2 in the liquid crystal display panel 1, the eighth horizontal scanning line of the original image shown in Fig.1, represented by the video signal VID sampled at the timing of sampling A, is displayed using the seventh line of pixels 2 in the liquid crystal display panel 1, and the same eighth horizontal scanning line of the original image shown in Fig.1, represented by the video signal sampled at the timing of sampling B, is displayed using the eighth line of pixels 2 in the liquid crystal display panel 1. For the even-numbered field also, every even-numbered horizontal scanning line of the original image represented by the video signal VID is displayed using two lines of pixels 2 on the liquid crystal display panel 1, the sampling timing being shifted between the two adjacent upper and lower lines according to the arrangement of pixels 2 shifted by one half of a pixel between the upper and lower lines. As in the case of the odd-numbered field, this serves to enhance the reproducibility of an original image having diagonal lines such as the one shown in Fig.1. Thus, on the liquid crystal display panel 1, the odd-numbered field image shown in Fig.7(1) is superposed on the even-numbered field image shown in Fig.7(2) to produce an image with good reproducibility as shown in Fig.7(3). In the above embodiment, we have described the invention as applied to an active matrix driving liquid crystal display device, but it will also be appreciated that the invention is equally applicable to a simple matrix driving liquid crystal device and an EL display device. The invention may be embodied in other specific forms without departing from the scope of the invention as defined by the appended claims.

Claims: A method of driving a matrix display device (1) by a repetitive scanning process with no interlace but using an interlace video signal, the number of pixel lines in said display device (1) being twice the number of horizontal scan lines in one field of the video signal, and the pixels (2) in one set of alternate lines being positionally offset in a sense along said lines by one half-pixel spacing relative to the pixels in the other set of alternate lines, the method comprising: performing on each said horizontal scan line of the video signal two sampling operations during one horizontal scanning period of said video signal, said sampling operations producing respective sets of data voltages to be applied to the pixels (2) of respective ones of a pair of adjacent said pixel lines of the display device (1), the timings of said two sampling operations differing by an interval which corresponds to said one half-pixel spacing; and applying to each one of said pair of adjacent pixel lines the associated set of data voltages. A method according to claim 1, comprising: applying data voltages, which are obtained by sampling a video signal (VID) representing one horizontal scanning line by a clock signal (SCK) whose timing matches the number and the arrangement of pixels (2) in the upper line of said pair of adjacent pixel lines, to the corresponding pixels (2) in said upper line; and applying data voltages, which are obtained by sampling the same video signal (VID) representing the horizontal scanning line as for the upper line by a clock signal whose timing is shifted by one half-cycle from the first-mentioned clock signal (SCK) so as to match the number and the arrangement of pixels (2) in the lower line of said pair of adjacent pixel lines, to the corresponding pixels (2) in said lower line; one horizontal scanning line represented by the video signal (VID) thereby being displayed using the pair of adjacent upper and lower lines of pixels (2) during one horizontal scanning period of the video signal (VID), and the operation being performed on all lines of pixels (2) to complete the display of an image for one field. An apparatus for driving a matrix display device (1) by a repetitive scanning process with no interlace but using an interlace video signal, the number of pixel lines in said display device (1) being twice the number of horizontal scan lines in one field of the video signal, and the pixels (2) in one set of alternate lines being positionally offset in a sense along said lines by one half-pixel spacing relative to the pixels (2) in the other set of alternate lines, the apparatus comprising: means (11,12,8,9) for performing on each said horizontal scan line of the video signal two sampling operations during one horizontal scanning period of said video signal, said sampling operations producing respective sets of data voltages to be applied to the pixels (2) of respective ones of a pair of adjacent said pixel lines of the display device (1), the timings of said two sampling operations differing by an interval which corresponds to said one half-pixel spacing; and means (6,10,12) for applying to each one of said pair of adjacent said pixel lines the associated set of data voltages. An apparatus according to claim 3, comprising: a line driving circuit (6) that sequentially specifies the lines of pixels (2) to be driven in accordance with the sequence of the lines; and a column driving circuit (7) that applies, to the pixels (2) in the upper line of said pair of adjacent pixel lines, respective data voltages obtained by sampling a video signal (VID) representing one horizontal scanning line by a clock signal (SCK) whose timing matches the number and the arrangement of pixels (2) in said upper line and applies, to the pixels (2) in the lower line of said pair of adjacent pixel lines, respective data voltages obtained by sampling the same video signal (VID) representing the horizontal scanning line as for the upper line by a clock signal whose timing is shifted by one half-cycle from the first-mentioned clock signal (SCK). An apparatus according to claim 4, further comprising: a double speed converting circuit (11) which converts an input video signal representing one horizontal scanning line of said interlace video signal (VID) into a compressed video signal (2VID) by compressing the input video signal by one half timewise, converts an input horizontal synchronizing signal (HSY) into a double speed horizontal synchronizing signal (2HSY) comprising a train of pulses occurring at one half of the frequency of one horizontal scanning period, and outputs an input vertical synchronizing signal (VSY) directly without conversion; and a control circuit (12) which controls the line driving circuit (6) and the column driving circuit (7) in accordance with the double speed horizontal synchronizing signal (2HSY) and the vertical synchronizing signal (VSY) supplied from the double speed converting circuit (11) and supplies said clock signal (SCK) to the column driving circuit (7). An apparatus according to claim 5, wherein the column driving circuit (7) comprises: a shift register (8) for storing the compressed video signal (2VID) representing one horizontal scanning line supplied from the double speed converting circuit (11); a sampling circuit (9) for sampling the video signal held in the shift register (8) in response to the clock signal (SCK) supplied from the control circuit (12); and an output buffer (10) for applying data voltages representing the video signal sampled by the sampling circuit (9) to the corresponding pixels (2).

Inventors: KAWAGUCHI TAKAFUMI, TAKEDA SHIRO, KAWAGUCHI, TAKAFUMI, TAKEDA, SHIRO
Applicants: SHARP KK, SHARP KABUSHIKI KAISHA
Application year: 1991
Main classification: G09G3
IPC codes: G09G3