Conditional branch instructions execution apparatus

Abstract: An electronic computer according to this invention is capable of executing a plurality of instructions simultaneously. It is characterized by comprising a flag adding section for judging whether or not each of a plurality of instruction is either a delayed branch instruction or a squash branch instruction, and based on the results, adding a flag indicating an abort condition to each instruction, and a command execute abort section for aborting execution of each instruction on the basis of whether or not the flag added to each instruction to indicate the abort condition and each branch instruction hold true.

Description: This invention relates to an improved electronic computer, and more particularly to an electronic computer capable of executing a plurality of instructions simultaneously and to an electronic computer capable of supporting a plurality of bus protocols. RISC processors capable of executing instructions at high speeds have been used for parallel arithmetic operation that deals with a plurality of instructions at the same time. Recently, much faster super-scalar processors have been developed; one of commercialized models of this type is the Intel's 80960CA. RISC processors are rich in software resources available. In developing super-scalar processors, to make full use of the existing software, it is necessary to develop processors that have object compatibility with the existing software. Some of RISC processors use delayed branching or squashed branching techniques in order to reduce losses due to wasteful actions in executing branch instructions. Typical processors of this type are the Sun Microsystems' R2000 and R3000. In delayed branching, when a branch instruction is encountered, the instruction immediately after the branch instruction is executed and then the branch destination instruction is executed. In squash branching, when a branch instruction is encountered, in the case of a branch-not-taken mode, the instruction next to the branch instruction is not executed, but the next but one instruction is executed, while in the case of a branch-taken mode, the instruction next to the branch instruction is executed and then the branch destination instruction is executed. Because super-scalar processors are fast in executing instructions but complex in control, it is difficult to directly execute the object codes of RISC machines using the above-described delayed branching or squash branching technique. As a consequence, super-scalar processors have no object compatibility with programs for RISC processors that perform delayed branch instructions or squash branch instructions. For example, the Intel's super-scalar processor 80960CA has object compatibility with the Intel's RISC processor 80960KA. However, at present, the 80960KA has not used delayed branching or squash branching techniques. As noted above, super-scalar processors, which have recently been developed in place of RISC processors, cannot execute delayed branch or squash branch instructions as matters stand. Therefore, they have no object compatibility with programs for RISC processors capable of executing those types of branch instructions. In a multiprocessor system having a plurality of processors, there is a time when communication between processors coexists with data communication between a processor and other peripheral units. In this case, the protocol of data transfer procedure for each communication is different from the other. Thus, to achieve those two types of communication, it is necessary to actively switch bus protocols depending on the communication mode used. However, for a system where processor-to-processor communication and processor-to-peripheral communication coexist, an effective means has not yet been found which switches bus protocols according to mode to allow those two types of communications on the same system. Some electronic computers employ a copy-back virtual cache system. In such computers, such as the SUN workstation, the cache tag of the cache memory is provided with a dirty bit and the TLB (address translation buffer) is assigned a dirty page bit. Those computers have a hardware mechanism that asserts the dirty bit of the cache tag when data is stored in the cache memory, and that copies into the TLB dirty page bit the dirty bit of the cache line to be copied back when copy back occurs, which action indicates that data has been written into the page. By above operation, the hardware mechanism rewrites the TLB dirty page bit at the time of uncache write access. However, computers with a virtual cache system rewrite the TLB dirty page bit by means of hardware, which results in more complicated hardware construction, larger LSI chip size, and longer development time. Among related literature are "IBM RISC System 1600 Technology," 1990, IBM Corporation, and "80960 Users' Manual," Intel Corporation. A RISC microprocessor having delayed branching with squashing is disclosed in the paper IEEE International Conference on Computer Design:VLSI In Computers & Processors; October 1989, Massachusetts, pages 385-390. An object of the present invention is to provide an electronic computer having a super-scalar processor capable of executing both delayed branch instructions and squash branch instructions and achieving object compatibility with RISC processor programs. This is accomplished by providing an electronic computer capable of executing a plurality of instructions simultaneously, comprising: abort condition synthesizing means for judging whether or not each of a plurality of instructions is either a delayed branch instruction or a squash branch instruction, and based on the results, adding to each instruction a flag indicating an abort condition; and command execute abort means for aborting execution of each of the instructions on the basis of whether or not the flag added to each instruction to indicate the abort condition and the branch instruction hold true. With this electronic computer, it is possible to abort the execution of each instruction using a delayed branch instruction or a squash branch instruction on the basis of whether or not the abort condition flag added to each instruction and the branch instruction hold true. Therefore, even in super-scalar processors, both delayed branch instructions and squash branch instructions can be executed, which provides object compatibility with RISC processor programs having a great variety of software resources. Making effective use of abundant software resources allows high speed processing. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram showing the overall construction of an electronic computer according to a first embodiment, associated with the first object, of the present invention; Fig. 2 is a block diagram for the execute unit of Fig. 1; Fig. 3 is a block diagram for the abort condition synthesis unit of Fig. 1; Fig. 4 shows a first way of executing a delayed branch command; Fig. 5 illustrates a second way of executing a delayed branch command; Fig. 6 depicts a third way of executing a delayed branch command; Fig. 7 illustrates how a squash branch command is practically executed. Referring to the accompanying drawings, an embodiment of the present invention will be explained. Fig. 1 is a block diagram of a 5-stage pipeline 4-instruction simultaneous-execution super-scalar machine to which an electronic computer according a first embodiment, associated with the first object, of the present invention. In Fig. 1, the pipeline consists of a fetch stage (F), a decode stage (D), an execute stage (D), a memory access stage (M), and a write stage (W). In the figure, a fetch circuit unit 100 accesses an instruction cache memory (not shown) to fetch a plurality of instructions. Those instructions stored in the fetch circuit unit 100 are sent to an instruction buffer unit 110 that latches them. The latched instructions in the instruction buffer unit 110 are sent to a command supply unit 120 as well as an abort condition synthesis unit 200. The command supply unit 120 supplies the instructions to individual execute units 300A and a branch execute unit 300B. The execute unit 300A is made up of a decode stage (D), an execute stage (E), a memory access stage (M), a write stage (W), and a command execute abort unit 350A. The abort condition synthesis unit 200, which will be explained in detail later, is a unit that generates conditional abort flags for the execute units 300A and 300B and fetch circuit unit 100. Specifically, it supplies a D-stage condition abort signal 291 and an E-stage condition abort signal 292 to the execute units 300A and branch execute unit 300B and an F-stage condition abort signal 295 to the fetch circuit unit 100. Fig. 2 shows a practical arrangement of the execute units 300A and 300B. Because the execute units 300A and 300B have the same circuit configuration, they will be referred to as the execute unit 300. In Fig. 2, the instructions supplied from the command supply unit 120 are sent to a D-stage decoder 310. The decoder 310 decodes the instructions from the command supply unit 120 to produce a D-stage valid signal 312. The valid signal 312 is supplied to one input terminal of an E-stage AND circuit 361. Depending on the contents of the output from an abort decision circuit unit 360 supplied to the other input terminal, the AND circuit 361 can negate the valid signal 312. The abort decision circuit unit 360 makes abort decision depending on the relation between the D-stage condition abort signal 291 latched in a latch 223 and a branch-taken signal 290 indicating whether to branch or not. The output of the AND circuit 361 is latched in an E-stage latch 365 and sent as an E-stage valid signal 367 to one input terminal of an AND circuit 371. Depending on the contents of the output from an abort decision circuit 370 supplied to the other input terminal, the AND circuit 371 can negate an E-stage valid signal 367. The abort decision circuit 370, like the aforementioned abort decision circuit 360, makes abort decision depending on the E-stage condition abort signal 292 latched in a latch 221 and a branch-taken signal 290 indicating whether to branch or not. The output of the AND circuit 371 is supplied as a write enable signal EW to a register file 345 via an M-stage latch 375 and a W-stage latch 380. The command execute abort unit 350 is composed of the abort decision circuit units 360 and 370, AND circuits 361 and 371, and latches 365, 375, and 380. The contents of the output of the register file 345 are supplied to an arithmetic unit 325 via the E-stage latches 320 and 322 and are calculated in the arithmetic unit 325. The calculation results are written into the register file 345 again via the M-stage latch 330 and W-stage latch 340. Fig. 3 illustrates a practical configuration of the abort condition synthesis circuit unit 200. In Fig. 3, a plurality of instructions (four in this case) latched in the instruction buffer unit 110 are sent to a branch instruction decoder 210. The branch instruction decoder 210 decodes the instructions from the instruction buffer unit 110 to judge whether it is a delayed branch instruction, squash branch instruction, or another instruction. The decision at the branch instruction decoder 210 is sent to each of abort condition synthesis circuit units 220, 222, and 224. The abort condition synthesis circuit unit 220 produces abort conditions regarding a subsequent series of four instructions including a branch instruction. The abort condition synthesis circuit unit 222 produces abort conditions regarding a subsequent series of four instructions. The abort condition synthesis circuit unit 224 produces abort conditions regarding another subsequent series of four instructions. The output of the abort condition synthesis circuit unit 220 is supplied as an E-stage condition abort signal 292, and at the same time, can be supplied as a D-stage condition abort signal. 291 via the multiplexer 230, and as an F-stage condition abort signal 295 via the multiplexer 235. The output of the abort condition synthesis circuit unit 222 can be supplied as a E-stage condition abort signal 292 via the multiplexer 230, and as an F-stage condition abort signal 295 via the multiplexer 235. The output of the abort condition synthesis circuit unit 224 can be supplied as an F-stage condition abort signal 295 via the multiplexer 235. In this case, the multiplexers 230 and 235 are controlled by the control circuit 240 according to a signal indicating that a fetch has been done. The control algorithm of the multiplexers 230 and 235 is as follows: 1) D-stage condition abort signal 291: the condition abort flag for a series of four instructions including a branch instruction generated at the abort condition synthesis circuit unit 220 is supplied as it is. 2) E-stage condition abort signal 292: when no fetch has been made during branch judgment (the time from when a branch instruction is decoded at D stage until execution is completed at E stage), the condition abort flag for a series of four instructions including a branch instruction generated at the abort condition synthesis circuit unit 220 is supplied via the multiplexer 230; and when one fetch has been made during branch judgment, the condition abort flag generated at the abort condition synthesis circuit 222 for a subsequent series of four instructions is supplied via multiplexer 230. 3) F-stage condition abort signal 295: when no fetch has been made during branch judgment, the condition abort flag for a series of four instructions including a branch instruction generated at the abort condition synthesis circuit unit 220 is supplied via the multiplexer 235; when one fetch has been made during branch judgment, the condition abort flag generated at the abort condition synthesis circuit unit 222 for a subsequent series of four instructions is supplied via multiplexer 235; and when two fetches have been made during branch judgment, the condition abort flag generated at the abort condition synthesis circuit unit 224 for another subsequent series of four instructions is supplied via multiplexer 235. For each of the delayed branching method and squash branching method, operation will be explained below. First, how a delayed branch instruction is executed in the delayed branch method will be described. For example, a condition abort flag is added to the assembler code using a delayed branch instruction as follows: Step Assembler Code Condition Abort Flag 1 addi r1, r 0, 1 alex 2 addi r2, r 0, 2 alex 3 addi r3, r 0, 3 alex 4 beq r29, r 20, x1 alex 5 addi r4 , r 0, 4 alex 6 addi r5 , r 0, 5 brab 7 addi r6 , r 0, 6 brab 8 addi r7 , r 0, 7 brab 9 addi r8 , r 0, 8 brab 10 addi r10, r 0, 10 brab As listed above, a condition abort flag alex (always execute) is added to the instructions at steps 1 to 3. When a delayed branch instruction beq is encountered at step 4, the condition abort flag alex will still be added to the delay instructions at steps 4 and 5. To the instructions at step 6 and later, a condition abort flag brab (branch then abort) is added. Therefore, when a delayed branch instruction beq is encountered, then the branch destination instruction will be executed after the instruction at the next step is executed. Fig. 4 illustrates a first way of executing a delayed branch instruction in the super-scalar machine. Among the consecutive instructions, instruction 2 is a branch instruction, instruction 13 is a branch destination instruction, and instruction 3 is a delay instruction. The condition abort flags for instructions 1 to 3 are alex (always execute) and those for instructions 4 to 12 are brab (branch then abort). A plurality of instructions fetched by the fetch circuit unit 100 are latched at the instruction buffer unit 110, and at the same time, are supplied to the command supply unit 120 and abort condition synthesis unit 200. In the abort condition synthesis unit 200, the branch instruction decoder 210 decodes a plurality of instructions to judge whether or not instruction 2 is a delayed branch instruction. The result is sent to the abort condition synthesis units 220, 222, and 224. The abort condition synthesis circuit unit 220 produces the condition abort flag for instructions 1 to 4 as abort conditions regarding a series of four instructions including a branch instruction. The abort condition synthesis circuit unit 222 produces the condition abort flag for instructions 5 to 8 as abort conditions regarding a subsequent series of four instructions. The abort condition synthesis circuit unit 224 produces the condition abort flag for instructions 9 to 12 as abort conditions regarding another subsequent series of four instructions. The abort flag for instructions 1 to 4 produced at the abort condition synthesis circuit unit 220 is supplied as an E-stage condition abort signal 292 to the first-stage pipeline. The abort flag for instructions 5 to 8 produced at the abort condition synthesis circuit unit 222 is supplied as a D-stage condition abort signal 291 to the second-stage pipeline via the multiplexer 230. The abort flag for instructions 8 to 12 produced at the abort condition synthesis circuit unit 224 is supplied as an F-stage condition abort signal 295 to the third-stage pipeline via the multiplexer 235. When the instruction buffer unit 110 supplies a plurality of instructions to the command supply unit 120, the command supply unit 120 sends instructions to the individual execute units 300. In each execute unit 300, the D-stage decoder 310 decodes instructions, while a D-stage valid signal 312 is supplied to the D-stage AND circuit 361 and an E-stage valid signal 367 to the E-stage AND circuit 371. In the execute unit 300 corresponding to instruction 1, the abort flag for the E-stage condition abort signal 292 is alex (always execute). In this case, the branch-taken signal 290 indicates "don't branch", so that the output of the abort decision circuit unit 370 is supplied to the AND circuit 371, which passes the E-stage valid signal 367 as it is. The output of the AND circuit 371 is supplied as a write enable signal to the register file 345. Based on the contents of the register file 345, the E-stage arithmetic unit 325 performs calculations. As with instruction 1, in the execute unit 300 corresponding to instruction 2 of a branch instruction, the abort flag is alex (always execute). Here, the branch-taken signal 290 indicates "don't branch", so that calculation is performed at E stage as mentioned above. In the execute unit 300 corresponding to instruction 3 of a delay instruction, the abort flag is also alex (always execute). Because the branch-taken signal 290 here indicates "don't branch", calculation is performed at E stage as described above. In the execute unit 300 corresponding to instruction 4, the abort flag is brab (branch then abort). In this case, the branch-taken signal 290 indicates "branch", so that the AND circuit 371 negates the E-stage valid signal 367 according to the output of the abort decision circuit unit 370, thereby aborting the execution of instruction. For instructions 5 to 8, like instructions 1 to 4, each execute unit 300 performs abort operation on the basis of the abort flag of the D-stage condition abort signal 291 and the branch-taken signal 290. For instructions 9 to 12, each execute unit 300 still carries out abort operation on the basis of the abort flag of the F-stage condition abort signal 295 and the branch-taken signal 290. In this way, a delayed branch instruction can be executed by the super-scalar machine. Fig. 5 illustrates a second way of executing a delayed branch instruction in the super-scalar machine. In Fig. 5, of the consecutive instructions, instruction 4 is a branch instruction, instruction 13 is a branch destination instruction, and instruction 5 is a delay instruction. The condition abort flags for instructions 1 to 5 are alex (always execute) and those for instructions 6 to 12 are brab (branch and abort). The operation as shown in Fig. 5 also allows the super-scalar machine to execute a delayed branch instruction as described in the first way. Fig. 6 shows a third way of executing a delayed branch instruction in the super-scalar machine. In Fig. 6, among a series of instruction, instruction 3 is a branch instruction, instruction 13 is a branch destination instruction, and instruction 4 is a delay instruction. The condition abort flags for instructions 1 to 4 are alex (always execute) and those for instruction 5 to 12 are brab (branch then abort). Here, because instructions 3 and 4 are interdependent, instruction 4 is executed with a delay of one cycle, though instruction 3 is a branch instruction. The abort flag produced at the abort condition synthesis unit 220 is supplied as an E-stage condition abort signal 292, and at the same time, is supplied as a D-stage condition abort signal 291 via the multiplexer 230. The abort flag produced at the abort condition synthesis unit 222 is supplied as an F-stage condition abort signal 295 via the multiplexer 235. With this approach, the super-scaler machine can execute delayed branch instructions as with the first operational example. Next, how a squash branch instruction is executed in a squash branching method will be explained. In this method, for example, execution sequence of assembler codes using delayed branch instructions is given as follows: Step Assembler Code Condition Abort Flag 1 addi r1, r 0, 1 alex 2 addi r2, r 0, 2 alex 3 addi r3, r 0, 3 alex 4 sbeq r29, r 20, x1 alex 5 addi r4 , r 0, 4 alex 6 addi r5 , r 0, 5 brab 7 addi r6 , r 0, 6 brab 8 addi r7 , r 0, 7 brab 9 addi r8 , r 0, 8 brab 10 addi r10, r 0, 10 brab In this method, a condition abort flag alex (always execute) is added to the instructions at steps 1 to 3. When a squash branch instruction is encountered at step 4, then a condition abort flag brex (branch then execute) will be added at step 5. To the instructions at step 6 and later, a condition abort flag brab (branch then abort is added. When a squash branch instruction sbeq is encountered, in the case of a branch-not-taken mode, the instruction next to the branch instruction is not executed, but the next but one instruction is executed, whereas in the case of a branch-taken mode, the instruction next to the branch instruction is executed and then the branch destination instruction is executed. Fig. 7 illustrates how a squash branch instruction is practically executed in the super-scalar machine. In Fig. 7, among a series of instructions, instruction 2 is a squash branch instruction, instruction 13 is a branch destination instruction, and instruction 3 is a delay instruction. The condition abort flags for instructions 1 to 2 are alex (always execute), that for instruction 3 is brex (branch then execute), and those for instructions 4 to 12 are brab (branch then abort). In the execute units 300 corresponding to instruction 1 and squash branch instruction 2, the abort flag for the E-stage condition abort signal 292 is alex (always execute) for either case. In this case, the branch-taken signal 290 indicates "don't branch", so that based on the output of the abort decision circuit unit 370, the AND circuit 371 passes the E-stage valid signal 367 as it is. This output is supplied as a write enable signal to the register file 345. Based on the contents of the register file 345, the E-stage arithmetic unit 325 performs calculations. In the execute unit 300 corresponding to instruction 3, the abort flag is brex (branch then execute). When the branch-taken signal 290 indicates "branch not taken" meaning "don't branch," instruction 3 will not be executed and control proceeds to instruction 4 and later. In contrast, when the branch-taken signal 290 indicates "branch taken" meaning "branch," instruction 3 will be executed and then control will proceed to instruction 4. In the execute unit 300 corresponding to instruction 4, the abort flag is brab (branch and abort). In this case, the branch-taken signal 290 indicates "branch", so that the AND circuit 371 negates the E-stage valid signal 367 according to the output of the corresponding abort decision circuit unit 370, thereby aborting the execution of instruction. For instructions 5 to 8, like instructions 1 to 4, each execute unit 300 performs abort operation on the basis of the abort flag of the D-stage condition abort signal 291 and the branch-taken signal 290. Similarly, for instructions 9 to 12, each execute unit 300 carries out abort operation on the basis of the abort flag of the F-stage condition abort signal 295 and the branch-taken signal 290. In this way, a squash branch instruction can be executed by the super-scalar machine.

Claims: An electronic computer capable of executing a plurality of instructions simultaneously, comprising: abort condition synthesizing means (200) for judging whether each of a plurality of instructions is one of a delayed branch instruction and a squash branch instruction, and based on the results, adding to each instruction a flag Indicating an abort condition; and command execute abort means (350) for aborting execution of each of said instructions on the basis of whether the flag added to each instruction to indicate the abort condition and said branch instruction hold true. An electronic computer according to Claim 1, wherein the electronic computer further comprises: fetching means (100) for accessing an instruction cache memory to fetch a plurality of instructions; latching means (110) for latching the output of said fetching means (100); a command supplying unit (120) for receiving the latched instructions from said latching means (110); and a plurality of executing means (300) for receiving the instructions from said command supplying unit (120) and said abort condition synthesizing means (200) and performing processes according to said instructions, each of said executing means including said command execute abort means (350). An electronic computer according to claim 2 , characterized in that said abort condition synthesizing means (200) includes: a branch instruction decoder (210) for decoding the instructions from said latching means (110) to judge whether each of the instructions is any of a delayed branch instruction, a squash branch instruction, and other instructions; a plurality of condition abort synthesizing units for receiving the instructions from said branch instruction decoders (210), and based on said instructions, producing abort conditions for the instructions including a branch instruction, each of said condition abort synthesizing units treating four instructions as an instruction unit and sequentially producing the abort condition for each of said instructions by said instruction unit; and a plurality of multiplexers selectively connected to the output of each of said condition abort synthesizing units, which supply a condition abort signal to said command execute abort means (350) according to the signals from each of said condition abort synthesizing units and said latching means (110). An electronic computer according to claim 2, characterized in that one of said executing means (300) is a branch executing unit (300B). An electronic computer according to claim 2, characterized in that said executing means (300) further includes: a decoder (310) for decoding the instructions from said command supplying unit (120); a register file (345) for storing the output of said abort condition synthesizing means; and an arithmetic unit (325) for performing calculation according to the contents of said register file (345). An electronic computer according to claim 2, characterized in that said command execute abort means (350) includes: abort decision circuits arranged so as to correspond to the individual stages of said executing means (300), which make abort decision on the basis of the stage condition abort signal corresponding to each of said stages and the branch-taken signal indicating whether to branch; a plurality of AND circuits arranged so as to correspond to said abort decision circuits, selectively in each stage, each AND circuit having two input terminals one of which is connected to the output of said abort decision circuit; and a plurality of latches for latching the output of each of said AND circuits.

Inventors: AIKAWA TAKESHI, MINAGAWA KENJI, SAITO MITSUO, AIKAWA, TAKESHI, MINAGAWA, KENJI, SAITO, MITSUO, Aikawa, Takeshi, c/o Intell. Property Div., Minagawa, Kenji, c/o Intell. Property Div., Saito, Mitsuo, c/o Intell. Property Div.
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1991
Main classification: G06F9
IPC codes: G06F9, G06F12