Analog to digital converter and comparator circuit therefor

Abstract: An ADC (18) including a comparator (40) sets, bit-by-bit, a successive approximation binary register (42). Feedback means (42, 44, 48) for auto-biasing, auto calibration, and offset compensation within the ADC (18) are provided. The ADC (18) sets itself to a high degree of accuracy automatically by reference to a master voltage reference. A number of identical ADCs (18) are connected in parallel to provide an increased sampling rate. The ADC (18) architecture compensates for component tolerance differences, for common mode noise, and for secondary parasitic effects. The ADC (18) operates with high resolution at high speed (e.g. 10 bits at 50 MHz), and can be implemented in MOS technology with good integrated circuit chip yield and is compatible with new ASICs.

Description: Field of the Invention The invention relates to an analog to digital converter (ADC). Background of the Invention In digital signal processing it is necessary to convert an analog signal into a digital format. To insure reasonable fidelity in this conversion, it is desirable to sample the analog signal at a rate substantially greater than analog signal bandwidth. These sampled signal values are then converted sample by sample at high speed into their equivalent digital values represented by "N" number of binary bits. Prior art ADCs, which typically use bipolar transistors, are able to operate at high rates (e.g., 50 MHz) and with 10-bit resolution. These ADCs require relatively large amounts of power (watts) and are very costly (hundreds of dollars). On the other hand, attempts to implement high speed, multi-bit ADCs with MOS technology have not been as successful as desired. Either cost was high because of poor chip yield or performance was substantially less than could be obtained using bipolar transistor technology. One of the problems in implementing a high speed ADC in MOS technology is that of "noise" caused by induced currents in the silicon substrate of a MOS chip. To some extent this problem can be minimized by careful shielding, by the separation and isolation of power supply busses, and by the use of complementary metal oxide semiconductor (CMOS) transistors, that is, n-channel and p-channel MOS transistors (NMOS and PMOS). However, the presence of residual noise, switching transients, stray capacity, etc., impose certain design constraints and other limitations on the sensitivity and sampling speed of an ADC using MOS technology as discussed in my U.S. Patent No. 4,989,003. Another problem is that the individual transistors and capacitors in a MOS circuit may have values of threshold voltage, capacitance, etc., which can vary by as much as 10%. These variations make it extremely difficult to build a high speed, precision ADC requiring closely matched components, or which have large switching transients. A prior ADC, termed an "N-flash" ADC, simultaneously produces "N" data bits in parallel from a sampled analog voltage. The ADC comprises 2 N comparators which are closely matched to each other with each capable of high resolution. The ADC circuit momentarily connects all of these comparators at once to an input signal circuit. The individual comparators then simultaneously determine the values of the N bits corresponding to the analog value of the input signal being sampled at that instant. An advantage of this ADC is the high speed at which it can operate. An important disadvantage is the heavy capacitive load (and corresponding large switching transients) caused by connecting all of the comparators to the input circuit at the same time. As an example, for a 10 bit output (where N equals 10) ADC the number of comparators is 1024! Thus the applied load represented by all the comparators connected in parallel is hundreds of times greater than that of a single comparator alone, giving rise to undesirably large switching transients. An important reason for lowering these switching transients is that the recovery time from these transients sets the upper limit on the sampling rate of the ADC. This undesirable condition is aggravated in MOS technology where the input impedance levels are inherently high and switching transients are more pronounced than with bipolar technology because of the need for switched capacitor auto-zero input circuitry to correct the relatively large MOS threshold voltage offsets. Another ADC, called a serial ADC, samples an analog signal and then bit-by-bit determines the digital value of the sample. A single comparator in the ADC can be used to determine all of the bit values and hence switching transients are greatly reduced compared to an "N-flash" ADC. However, the speed of a serial ADC is relatively slow because of the time taken in the sequential determination of the bit values of the digital output. Thus for a 10-bit output ADC, a serial ADC may run at only one-tenth the speed of a 10-bit "N-flash" ADC. It will thus be appreciated that the requirement for high speed in an ADC conflicts in important ways with the requirement for high resolution; and that the desire for low cost, through the use of MOS technology, conflicts with the desire for high performance. A prior serial ADC, disclosed in document US-A-3 781 871 generates a digital value having N bits and comprises: Comparator means having an input for sampling an analog voltage, and which outputs either a 1 or a 0 depending on whether the analog input voltage is below or above the voltage on the second input terminal, a successive approximation means including digital to analog conversion means providing an analog output coupled to the second input of said comparator, the input to the successive approximation means receiving the single bit digital output from the comparator means and timing means driving the sampling of the comparator means, whereby the duration of each sampling interval decreases from the determination of the most significant bit to the least significant bit. This increases the conversion speed by varying the frequency of the clock to accommodate the actual settling time required for each digital output bit, such that most time is allocated to the most significant bit, and progressively less time is allocated to each subsequent less significant bit. Summary of the Invention The invention is an analog to digital converter (ADC) for generating a digital value having P more significant bits and Q less significant bits where P and Q are integers greater than 1, the ADC comprising; comparator means having an input terminal for sampling a residual input analog voltage during successive cycles of operation and for generating a succession of single-bit output values each of which is either a binary 0 or 1 depending on whether the residual input analog voltage is below or above a bias voltage, the residual voltage at the input being subject to settling time; timing means for driving the comparator means with clock pulses having a predetermined duration; and offset compensating means for selectively adding a settling time offset voltage to the residual input analog voltage, the settling time offset voltage being added only when the P more significant bits of the digital value are being determined, the offset voltage having a magnitude corresponding to a predetermined one of the Q less significant bits. An embodiment of the invention provides a highly effective and efficient new architecture for an ADC. This ADC is readily implemented in present day MOS technology (e.g., standard one-micron N-well manufacturing technology) either as a stand-alone unit or as a sub-module of a larger application-specific integrated circuit (ASIC). Thus the new ADC can be manufactured at very low cost compared to previous ADCs and is fully compatible with the newer ASIC MOS digital circuits. A number of unique design features enable this new ADC to operate at high speed with high resolution (e.g., 10-bits) with good immunity to noise and with very low power requirements. The unique architecture of this new ADC also substantially improves yield of "good" chips which factor further contributes to low cost. A high performance serial ADC is implemented through novel architecture which-obviates the need for closely matched transistors and capacitors and which minimizes the delays and accuracy-destroying effects of switching transients. This architecture includes a novel high speed comparator circuit having balanced PMOS and NMOS transistors by which a high degree of common-mode noise immunity is obtained. The comparator circuit includes an active feedback loop (unique in itself) by which the comparator continually and automatically "zeroes" or biases itself to an accurately determined switching point which is continually referenced to a master voltage reference. A switching sensitivity of one millivolt (mV) at an exactly determined switching point is obtained by the auto-bias action even though the PMOS and NMOS transistors and associated coupling capacitors are not exactly matched, or age with time. Unwanted errors caused by parasitic capacitive coupling at terminals within the comparator are substantially eliminated by the action of this auto-bias loop. These complimentary transistors are biased into high-gain regions and are provided with regenerative feedback for very fast switching. Since they are balanced for common mode noise rejection they are stable in a noisy digital environment as in an ASIC. Their sampling aperture is very narrow (about 200 picoseconds) further enabling the comparator circuit and the ADC to operate at a very high clock rate (e.g., 50 MHz). The comparator circuit drives a uniquely configured serial-bit register which operates by successive approximation to determine the digital value of a sampled voltage. The register has a unique arrangement of N+1 bit positions, corresponding to the N bits in a digitized signal plus an extra bit used for "switching offset compensation". The extra offset-compensation bit, by compensating for settling time (resulting from an RC time constant) in the comparator's input circuitry (also novel), enables the comparator to operate at much higher speed (e.g., twice as fast) than otherwise. This extra bit, representing an offset compensation voltage, is applied by the register in a successive approximation algorithm, described in detail hereinafter. The comparator, operating in conjunction with the bit register, successively and at very high speed determines the values one-by-one of the most significant to the least significant bits of the N bit digital value of a sampled analog signal voltage. A resolution of 10-bits (N=10) is easily obtained. The serial bit register is subdivided into a first portion representing the more-significant-bits (MSBs) of the N-bits, a second portion representing the less-significant-bits (LSBs) of the N bits, and a third portion representing the extra offset compensation bit. The MSB portion of the register drives a digital-to-analog converter (DAC) which applies, on command to the comparator, an analog reference voltage representing the MSBs then in the register. The accuracy of this analog reference voltage is determined by reference to a very accurate master voltage reference. Similarly the LSB portion and the offset bit portion of the register together drive a DAC which applies on command another analog reference voltage to the comparator representing the LSBs and offset bit then in the register. A high degree of accuracy (within a mV) of this analog reference voltage from the LSB DAC is provided by an active auto-calibrating feedback loop to and from the LSB DAC and the comparator. By this means the comparator continually and automatically calibrates the LSB DAC relative to the master voltage reference. Thus extremely high resolution (better than one part in several thousand) for the ADC, is obtained even though the circuit components may have relatively large tolerance variations and operate at very high speed in noisy environments. Identical ones of these new ADCs are arranged in a parallel assembly of closely adjacent multiple ADCs. By way of example, for a 10-bit (N=10) ADC, sixteen clock phases, synchronized to an external clock, are employed. Five phase counts are used by the ADC for auto-zeroing, auto-calibration, signal sampling and digital output multiplexing. Eleven phase counts are used in determining the ten data bits and to accommodate the one offset bit. Sixteen ADCs are provided in the overall assembly, and the sampling phase of each ADC is skewed by one phase relative to a preceding ADC. Thus only one comparator of a ADC in the assembly is sampling the analog signal input at any one time, but all sixteen ADCs will have sampled the input during the sixteen phase count cycle. Thus the effective analog-to-digital conversion speed of the multi-ADC assembly is multiplied by sixteen though only one comparator is switched "on" for sampling at any given phase count. The overall accuracy of all the ADCs operating together is determined by the single master voltage reference through the individual auto-zeroing and auto-calibration of the converter within each ADC. The practical implementation with good chip yield in MOS technology of multiple ADCs like this is greatly facilitated by the unique architecture of each ADC. Brief Description of the Drawings FIG. 1 is a schematic diagram of an ADC of the invention including an assembly of multiple ones of identical ADCs arranged in parallel and being driven by skewed clock and phase pulses; FIG. 2 is a clock and phase timing diagram of the respective phases and clock pulses used with the ADCs in FIG. 1; FIG. 3 is a schematic diagram of a comparator circuit (part of each one of the ADCs of FIG. 1) according to another aspect of the invention; FIG. 3A is a voltage diagram showing the important effect of auto-bias for the comparator of FIG. 3; FIG. 4A shows a circuit for obtaining the timing signals "PSMP" and "PSMPN" as used in the comparator of FIG. 3; FIG. 4B shows a circuit for obtaining the timing signals "PVR", "PVRN" and the signals "PVI" and "PVIN" as used in the comparator; FIG. 4C shows a timing relationship of "PVI" to "PSMP" and phases P(3) and P(4). FIG. 5 is a circuit diagram of a SAR of an ADC as shown in FIG. 1; FIG. 5A is a schematic representation of the bit positions of the SAR in FIG. 5; FIG. 6 is a circuit diagram showing a MSB DAC of the SAR in FIG. 5, and FIG. 7 is a chart showing the sequence of operation of one of the ADCs of FIG. 1. Detailed Description In FIG. 1, an ADC assembly 10 (shown within a large dashed line rectangle) comprises an analog signal input which is connected to a buss 12 and a digital output signal terminal 14. A high frequency signal may be applied to input buss 12, and its digital equivalent, shown here as a 10-bit number, obtained in real time at output terminal 14. Assembly 10 is shown comprising sixteen ADCs 18 (each being shown within a dashed line box). The first, second, third and sixteenth ADCs 18 are shown with only the first being shown in detail. Typically assembly 10 is formed on a silicon substrate using MOS technology with each ADC 18 being implemented in about 300 square mils of area. For example, there may be sixteen ADCs 18 in an assembly 10 and each ADC 18 is shown here (and subsequently) as generating an 11-bit number (N+1). Each ADC 18 has a respective voltage input terminal 20, which input terminals are connected in parallel to the input buss 12 and to which are applied an analog signal input voltage (VIN) which is to be digitized. Each ADC 18 has an output signal terminal 22 which is connected to a respective one of input terminals 24 of a multiplex (MUX) unit 28 (shown as "11-Bit 16:1 MUX") of a type well known in the art. The MUX unit 28 has a single output terminal 30 to which it applies in sequence the parallel 11-bit "words", or digitized signals, generated by the individual ADCs 18. Connected to output 30 of the MUX 28 is an adder and format converter 32, also known in the art. Each 11-bit "word" from the MUX 28 is in non-standard binary format (N+1). Format converter 32 converts each such word into a standard 10-bit (N) format and then applies these digital values as 10 bit words in real time to the output terminal 14 of the assembly 10. Each ADC 18 is driven by a clock and phase timing unit 36 which as shown here, generates sixteen phases P(0) to P(15) and a clock pulse "CK". Each phase P is skewed by one clock pulse and there are thus sixteen phases for each complete cycle of the timing unit 36. Each of the ADCs 18 is driven by all of the phases P and the clock pulses CK of unit 36 but the drive of the second ADC 18 is skewed by one phase P relative to the drive of the first ADC 18, and so on, with each ADC 18 skewed in its operation by one phase relative to the prior ADC 18. Thus the sixteen ADCs 18 respectively sample the input voltage VIN at sixteen successive instants, and so on. This arrangement effectively increases the composite sampling speed of ADC assembly 10 by sixteen. It is to be understood that fewer (or more) ADCs 18 may be used depending on the sampling speed desired, and the signal processing time within each ADC 18. Each ADC 18 comprises an auto-zero comparator 40 which via a lead 41 sends single-bit data to a SAR 42 (shown as an "11-bit SAR"). Comparator 40 momentarily samples the input voltage VIN at the input terminal 20, and thereafter, in a clocked sequence in combination with the SAR 42, determines bit-by-bit the digital value of the sampled input voltage. SAR 42 provides three more-significant-bits (MSB) of data to a DAC (shown as "3 bit MSBs DAC") 44 which in turn applies an analog "switched voltage reference" (SWVR) in a feedback loop 46 to the comparator 40. In a similar way, SAR 42 applies seven less-significant-bits (LSBs) plus one "offset compensation" bit to a DAC (shown as "LSB DAC plus offset") 48. This LSB DAC 48, which is of a type well known in the art, supplies to a load resistor RL a constant current whose analog value corresponds very accurately to the digital value of the 7 LSBs plus the one offset bit. The voltage drop across resistor RL, which may for example be 1000 ohms, is thus an analog voltage "DA" which is applied via a lead 50 to an input of the comparator 40. The comparator 40, in turn, via a feedback lead 52, from an auto-calibrating feedback arrangement to be described shortly, applies an automatically calibrated analog voltage reference "VRDA" to the LSB DAC 48. This reference voltage VRDA automatically controls the LSB DAC 48 so that its output current (and the voltage across resistor RL) is accurately referenced to a master voltage reference (not shown) Each ADC 18 is connected to the master voltage reference as will be described shortly. The reference voltages SWVR, DA and VRDA, though separate, are automatically and continually referenced individually (e.g., each within a mV) against the master voltage reference (not shown) through a sequence of steps which are described below. Thus each ADC 18 is automatically made very accurate within its own cycle of operation, and the multiple operations of all of the ADCs 18 in assembly 10 are tied together with equal, automatically obtained accuracy from the single master voltage reference the clock pulses (CK) and the phases (P0) to P(15) produced by the timing unit 36 (see FIG. 1) during a cycle of operation of each ADC 18 of FIG. 1. Each clock pulse CK is in the form of an asymmetrical square wave having a "high" state 60, a "low" state 62, and a duration (period) 64. This duration 64 may, for example, be 20 nanoseconds. A clock pulse CK goes from low to high (in voltage) at a rising leading edge 66 occurring at the beginning of a clock period 64, and from high to low at a falling trailing edge 68. The zero ("0") to the fifteenth ("15") clock pulse CK (sixteen identical pulses) are as indicated; thereafter a cycle of sixteen is repeated. The clock pulses CK in turn generate the respective phases P(0) to P(15). Thus the leading edge 66 of the "0" clock pulse CK generates (slightly displaced in time) a rising leading edge 70 going from low to high of the "0" phase P(0), as indicated by a dashed arrrowed line 71, and the trailing edge 68 of the "0" clock pulse CK generates a falling trailing edge 72 (going from high to low) of phase P(0), as indicated by a dashed arrowed line 73. There is only one phase P(0) for the sixteen clock pulses CK in a cycle. Thereafter, another "0" phase P(0) is generated and the cycle begins again. In the same way a "1" phase P(1) is generated by the "1" clock pulse CK, as indicated by a dashed arrowed line 71a and a dashed arrowed line 73a, and so on, through phase P(15) as shown. These phases and clock pulses drive each ADC 18 is described hereinafter. By virtue of the offset compensation bit, mentioned earlier, the overall clock period 64 can be substantially reduced (e.g., by about half) without sacrificing accuracy. In FIG. 3 a preferred embodiment of the auto zero comparator 40 of FIG. 1 comprises a balanced regenerative latch 74 (shown within a dashed line box), which has a signal voltage input at an input terminal 75 and a single-digit voltage output at a terminal 76. Lead 41 (see also FIG. 1) is attached to this terminal 76. An analog auto-bias voltage (BV) is applied to the latch 74 at a terminal 78. Voltage BV automatically "zeroes" the switching point of the latch to a precisely controlled value. Latch 74 comprises p-channel transistors 80, 90, 96 and 98, n-channel transistors 84, 88 and 94, and inverters 100 and 102. The sources of transistors 80, 90, 96 and 98 are coupled to a positive voltage source +VDD, and the source of transistor 88 is coupled to a reference voltage which is shown as ground. The drains of transistors 80, 84 and 96 are coupled to the gate of transistor 94, to an input of inverter 100 and to a terminal 82. The sources of transistors 90, 94 and 98 are coupled to the gate of transistor 84, to an input of inverter 102 and to a terminal 92. The drains of transistors 84 and 94 are coupled to the source of transistor 88 and to a terminal 86. The CK signal of FIG. 1 is coupled via a buss (not shown) to the gate of transistor 88, to input of inverter 89, and to the gates of transistors 96 and 98 and to a terminal 99. Inverter 89 generates at an output thereof an inverted CK signal which is shown as CKN. An output of inverter 100 is coupled to the output terminal 76 of latch 74. The purpose of inverter 102 is to provide a balanced capacity, mirror image of the inverter 100. It will be noted at this point that the circuit elements of the latch 74 are symmetrical and complementary, and are arranged to give a high degree of immunity to common mode noise. By automatically adjusting ("zeroing") the bias voltage BV on the gate of transistor 90 during operation of the comparator 40 through continual reference to the master voltage reference, the value of voltage at input terminal 75 which causes the regenerative latch 74 to switch its output voltage at terminal 76 to either "low" or "high", is very accurately determined. This is automatically done by means of a feedback loop to be described shortly. When the transistor 88 of the latch 74 is turned off, and transistors 96 and 98 are turned on with each clock pulse CK, terminals 82 and 92 are pulled up in potential to the supply voltage VDD. This occurs when a clock pulse CK (see FIG. 2) goes from a high level 60 to a low level 62 along a falling trailing edge 68. Quickly thereafter at the rising leading edge 66 of the next clock pulse CK, transistor 88 turns on and transistors 96 and 98 turn off. At this instant, if the input voltage at the terminal 75 is even slightly above the bias voltage BV at terminal 78, the latch 74 switches the voltage at output terminal 76 to "high" (a value substantially equal to VDD). This is defined to be a binary "1" output of latch 74. Because of the regenerative feedback provided by the cross-coupled terminals 82 and 92, switching takes place at very high speed (e.g., in a few nanoseconds). Similarly, if the input voltage at terminal 75 is less than the bias voltage BV, the latch 74 switches the voltage on output terminal 76 to "low" (ground). This is defined to be a binary "0". In a preferred embodiment of latch 74, inverter 100 is selected to have a threshold voltage of slightly less than VDD/2. This limits voltage spikes in output terminal 76 when the output voltage at terminal 76 is to be a "0" by not switching from a "0" to a "1" just after terminals 82 and 92 both drop to about VDD/2 after CK goes to a high. Even if terminal 82 is going to stay at a high level because input terminal 75 is more negative than bias terminal 78, it may momentarily drop to Vdd/2. By setting the threshold voltage of inverter 100 to slightly below VDD/2, a voltage spike towards a "1" at terminal 76 is prevented when the state thereof is going to remain at a "0". In FIG. 3A, there is shown a voltage diagram relating the input voltage (horizontal axis) at the input terminal 75 of the latch 74 to the switched output voltage (vertical axis) at terminal 76. The auto bias voltage BV (shown as a dashed-dotted vertical line 108) is established by an auto-bias feedback loop to be described shortly. A solid vertical line 110 shows the voltage (VSC) at which the latch 74 switches. The voltage VSC is established as substantially equal to a reference voltage by adjusting the value of the bias voltage BV. An "offset" differential voltage, indicated by 109, between bias voltage BV at line 108, and the switching voltage VSC at line 110 compensates for small differences in the characteristics of transistors in a given latch 74 and is automatically determined by the action of the auto bias feedback loop. This offset voltage may be different from one latch 74 to another, but the switching voltage VSC is the same from latch to latch. For an input voltage at terminal 75 slightly below the switching voltage VSC, the latch 74 switches the output "low", and for a value above the switching voltage VSC, the latch switches "high". The sensitivity of switching is within 1 mV as shown. In the absence of a precisely determined or "set" value of auto-bias voltage BV along line 108, because of slight variations in the threshold voltages of the transistors in the regenerative latch 74, the latch may have a lower switching voltage indicated by a vertical dashed line 111, or a higher switching voltage indicated by a vertical dashed line 112. This variation may be as much as 50 to 100 mV from one latch 74 to another, and would otherwise destroy the necessary accuracy in the switching voltages from one comparator 40 to another in the assembly 10 of ADCs 18 as shown in FIG. 1. The offset differential voltage 109 between the bias voltage BV at line 108 and the switching voltage VSC at line 110 lies within the range indicated at 113 from the lower voltage at line 111 and the higher voltage at line 112. As was just mentioned, the bias voltage BV for the latch 74 in one comparator 40 may not be exactly the same as the bias voltage BV determined separately for the latch 74 in another comparator 40 in a multiple cell ADC assembly 10. Among the reasons for this are parasitic capacitive coupling and differences in the input offset voltage for the respective latches 74 of the multiple ADCs 18 in an assembly 10. However the auto-zeroing action of each comparator 40 of a given ADC 18 determines its own value of bias voltage BV which effectively compensates for any offset effects seen by it to give the switching accuracy and sensitivity indicated in FIG. 3A. In FIG. 3, the output voltage from the latch 74 at output terminal 76 is connected to one side of a transmission gate 114 (also described as switch 114 or on-off switch 114). The switch 114 is controlled by a clock pulse CK and an inverted clock pulse CKN, the latter pulse CKN being obtained from the output of the inverter 89. The on-off switch 114 when "on", applies the voltage at the output terminal 76 to an input of a latch 116, (shown within a dashed-line box). The latch 116 comprises a first inverter 116a and a second inverter 116b connected back-to-back as shown. This latch 116 retains its current state after the switch 114 turns off. The latch 116 applies via a lead 117 the voltage level it is holding to an input of a voltage inverter-limiter 118 (shown within a dashed-line box and of a type well known in the art). Inverter-limiter 118 comprises a p-channel transistor 118a whose source is connected to a voltage VZH. The drains of transistors 118a and 118b are connected to a terminal at 119. The source of the transistor 118b is connected to a "low" reference voltage (VZL). The gates of transistors 118a and 118b are connected to the input lead 117. When the voltage on lead 117 is "high", inverter-limiter 118 applies to its output terminal 119 VZL, obtained ultimately from the master voltage reference, and when the voltage on lead 117 is "low", the inverter-limiter 118 applies to output terminal 119 a "high" voltage (VZH) similarly obtained. By choosing the values of voltages "VZL" and "VZH", the swing from "low" to "high" at output terminal 119 is conveniently determined. For example, if the voltage on lead 117 at the input to the inverter-limiter 118 swings from 0 to +5 volts (V) (low to high), the voltage at the output terminal 119 is made to swing from +3 to +2V high to low with VZH = +3V and VZL = +2V. The voltage on terminal 119 is applied to a uniquely configured low pass, switched capacitor filter unit 120, (shown within the dashed-line box). The switch/filter 120 comprises n-channel transistors 122, 124 and 142, p-channel transistor 128,130 and 140, inverters 132 and 134 and capacitors 136,138,144 and 146. The drain and source of transistor 140 and a first terminal of the capacitor 144 are connected to a voltage source VDD. The drain and source of transistor 142, and first terminals of the capacitors 136,138 and 146, are coupled to ground potential. The drains of transistors 122 and 128 are coupled to the terminal 119. The source of transistor 122 is coupled to the drain of transistor 124 and to a second terminal of capacitor 136. The source of transistor 128 is coupled to the drain of transistor 130 and to a second terminal of capacitor 138. The sources of transistors 124 and 130 are coupled to second terminals of capacitors 144 and 146, to the gates of transistors 140 and 142 and to a terminal 126. Terminal 126 is coupled via a conductor 148 to terminal 78. Phase P(2) is coupled to the input of inverter 132 whose output is coupled to the gate of transistor 128. Phase P(3) is coupled to an input of inverter 134 whose output is coupled to the gate of transistor 130. The capacitor 136 is not a separate circuit element as such, but represents the combined depletion capacity and the gate to source capacitance of transistor 122 and the gate to drain capacitance of transistor 124. The same is true for the capacitor 138 and the transistors 128 and 130. These capacitors are each very small, for example about 5 femtofarads (fF), and are substantially equal to each other. In the absence of a phase P(2) or P(3), transistors 122, 124, and transistors 128 and 130 are in effect open switches. The capacitor 144, which is typically not a separate circuit element, represents the gate to drain-source capacitances of transistor 140. Similarly, capacitor 146 represents the same capacitances of transistor 142. Each of capacitors 144 and 146 has a value, for example, of about 2.5 picofarads, which is very much larger than either capacitor 136 or 138. The voltage on node 126 is able to move up or down between ground and VDD, but is nominally set at around half of VDD (e.g., half-of 5V). Since transistor 122 and transistor 128 are complementary, when they are switched on by phase P(2) and P(2)N (the output of inverter 132), they substantially equally and symmetrically charge the respective capacitors 136 and 138 to the "high" or "low" voltage then at terminal 119 (e.g., voltage VZH or VZL). Any error in charging the capacitors 136 and 138 caused by the switching "off" of transistors 122 and 128 is self-cancelling. For example, capacitor 136 may be left charged slightly lower than it should be, but capacitor 138 is left charged slightly higher, and vice-versa. Thereafter, when transistors 124 and 130 are turned on by phase P(3) and P(3)N (after transistors 122 and 128 are off), the charges on capacitors 136 and 138 are applied to terminal 126. The effect is to move terminal 126 slightly up or down in voltage by a very small amount because of the much larger values of capacitors 144 and 146. They are each about 500 times larger than either capacitor 136 or 138. The voltage on terminal 126 is thus a highly filtered analog voltage which is continually being adjusted on repeated phases P(2) and P(3) in response to the digital voltage being continuously switched high or low at the terminal 119 with each clock pulse CK. After the comparator 40 has initially operated for a number of cycles (a very short time) the analog voltage at terminal 126 asymptotes to a desired value and thereafter is the "auto-zeroed" bias voltage BV. This voltage BV is applied via a lead 148 to the bias terminal 78 of the latch 74. Of course, by virtue of the sequential on-off switching of the transistors 122, 128 and of transistors 124, 130 of the switch/filter unit 120, the bias voltage set at terminal 126 on phase P(3) is unaffected and remains unchanged (as the desired analog bias voltage BV at input terminal 78) throughout the remaining phases P(4) to P(15) of each full cycle of operation of comparator 40. In FIG. 3, the auto-calibration reference voltage VRDA on lead 52 (see also FIG. 1) is obtained as follows. Also connected to the output 76 of the regenerative latch 74 through the switch 114 and the latch 116 is a lead 150. Lead 150 is connected to an input terminal 152 of a low pass, switched capacitor filter 154. This switch/filter 154 is substantially identical to the switch/filter 120 previously described. The switch/filter 154 has an output terminal 156 (similar to terminal 126) and the filter 154 is turned on and off in sequence by the phases P(3) and P(4) as indicated. The voltage at output terminal 156 is an analog voltage which, as will be described shortly, is referenced by the action of the comparator 40 to the master voltage reference. The analog voltage at the terminal 156 is applied to a source/follower 158 (shown within a dashed-line box) which is well known in the art. Source/follower 158 comprises two p-channel transistors 158a and 158b whose sources and drains are connected in series between the voltage source VDD and ground as shown. The gate of the transistor 158a is connected to the terminal 156 and the gate of the transistor 158b is connected to the voltage VREF. The drain of transistor 158b is coupled to the source of transistor 158a and to a terminal 159 which is coupled to a lead 52. The voltage at terminal 159 is the analog reference voltage VRDA, which is applied via the lead 52 to the LSB DAC 48 in FIG. 1. In FIG. 3, input terminal 75 of the latch 74 is connected to a uniquely configured interconnecting circuit 160 (shown within a dashed-line box) which comprises part of the comparator 40. The circuit 160 applies in desired sequence to the input terminal 75 of the latch 74, various input voltages, as will shortly be described. The circuit 160 comprises first, second and third transmission gates (switches) 164, 174 and 176 each having first and second control terminals and an input and output terminal, and capacitors C1 and C2. Switch 164 has signals "PSMP" and PSMPN (the complement of PSMP) coupled to its control terminals. Similarly, signals "PVI" and "PVIN" and "PVR" and "PVRN" are coupled to the control terminals of switches 174 and 176, respectively. A reference voltage VREF, which is referenced to the master voltage reference, is coupled to a terminal 166 and to the input of switch 164. VREF is by way of example 2.5V where the master voltage reference = 5.0V and is very accurate. VDD is also 5V. The input of switch 174 is coupled to the input terminal 20 (also see FIG. 1) to which an analog signal VIN is applied. The switched reference voltage (SWVR) obtained via the lead 46 from the MSB DAC 44 (See FIG. 1) is applied to a terminal 178 which is coupled to the input of switch 176. The analog voltage DA is coupled to a terminal 180 which is coupled to a first terminal of C2. The outputs of switches 174 and 176 are coupled to a first terminal of C1. Second terminals of C1 and C2 are coupled to the output of switch 164 and to input terminal 75 of latch 74. In FIG. 4A, a logic circuit 190 (shown within the dashed-line box) comprises a two input NOR gate 192, inverters 194, 195, 196 and 199, and a transmission gate 198. The first and second inputs of NOR gate 192 are coupled to phase signals P(0) and P(3), respectively. An output of NOR gate 192 is coupled to an input of inverter 194 whose output is coupled to inputs of inverter 195 and transmission gate 198 (biased on). An output of inverter 195 is coupled to an input of inverter 196 at whose output is generated the signal PSMP. An output of transmission gate 198 is coupled to an input of inverter 199 at whose output is generated the signal PSMPN (the complement of PSMP). Circuit 190 generates signals PSMP and PSMPN without there being any delay between these two output signals. This is achieved by selecting a transmission gate 198 which has essentially the same delay time as inverter 195. In FIG. 4B, a cross-coupled logic circuit 200 (shown within a dashed-line box) comprises a first "NOR" gate 202, having an upper input terminal 203 (to which P(3) is applied), and a lower input terminal 204. An output of the NOR gate 202 is serially connected through a first inverter 206 and a second inverter 208 to a first output terminal 210 at which the signal PVR is generated. Connected to an output of the first inverter 206, via a lead 211 is a second output terminal 212 at which the signal PVRN (the complement of PVR) is generated. The circuit 200 further includes a second "NOR" gate 214 having a lower input terminal 215 to which P(4) is applied and an upper input terminal 216. An output of the NOR gate 214 is connected serially with a third inverter 218 and a fourth inverter 220 to a third output terminal 222. The signal PVI is generated at terminal 222. Connected to the output of the third inverter 218 via lead 223 is a fourth output terminal 224 at which the signal PVIN (the complement of PVI) is generated. The third output terminal 222 is cross-connected via lead 226 to the input terminal 204 of the first NOR gate 202. Similarly, the second output terminal 210 is cross-connected via a lead 228 to the input terminal 216 of the second NOR gate 214. When phase P(3) is applied to the terminal 203 of the first NOR gate 202, the connection from the terminal 210 to the terminal 216 of the second NOR gate 214 produces a signal PVI at the terminal 222. The circuit then stays latched in this condition until phase P(4). The signals PVI and PVIN are of proper polarity to turn on the switch 174 (see FIG. 3). However, the signals PVR and PVRN subsequently appear at the terminals 210 and 212 in negative polarity from that shown. As such they will not operate the transmission gate or switch 176 to which they are applied. Later, when phase P(4) is applied to the terminal 215 of the second NOR gate 214, the signals PVI and PVIN are reversed in polarity (and no longer hold "on" the switch 174) and signals PVR (true) and PVRN (complement) appear with proper polarity at the terminals 210 and 212. They will then turn on the switch 176. The timing of the signal PVI (and complement PVIN) relative to phases P(3) and P(4) and the signal PSMP (and complement PSMPN) of FIG. 4A is described below. In FIG. 4C, a clock pulse (CK) having three pulses "CK 2", "CK 3", and "CK 4" and signals P(3), P(4), PSMP and PVI is shown. Clock pulse CK at a rising edge 66 generates the phase signal P(3) as indicated by the dashed arrowed line 71 (see also FIG. 2). Phase P(3) in turn generates the signal PSMP (Fig. 4A) and the signal PVI (FIG. 4B). For simplicity, the complements PSMPN and PVIN are not shown in FIG. 4C. When phase P(3) turns on signal PVI (as is shown by the arrowed line 230 in solid), it also turns on PSMP (as is shown by the arrowed line 231). The signal PVI, because of the cross-coupling of the logic circuit 200 (See FIG. 4B), remains on after P(3) turns off and until phase P(4) comes on. The turning off of signal PVI is shown in FIG. 4C by the arrowed solid line 232 from the beginning of phase P(4). Thus the duration of PVI is longer than the duration of PSMP as indicated at 236. The signal of PSMP here is turned off by phase P(3) as indicated by the line 237. The extra time that PVI is on is essentially equal to the time that the clock pulse CK3 is at a low level 62. The importance of this extra time for PVI will be explained shortly. In FIG. 3, the voltage at the terminal 75 (T75) is determined by C1, C2 and the voltages VREF, VIN, SWVR and DA. It is expressed by an equation (1) as follows: V(T75)=VREF+(SWVR-VIN)x[C1/(C1+C2)]+DAx[C2/(C1+C2)]. The voltage at the terminal 75 thus responds to the difference between (SWVR+DA) and VIN. The effect of small variations in exact equality of capacitors C1 and C2 is compensated for in the auto-calibration loop running from the regenerative latch 74 via the lead 52 through the LSB DAC 48 and back via the lead 50 to the DA terminal 180, described previously. By automatically setting the effective gain "G" of the auto-calibration loop so that Gx(C2/(C1+C2))=C1/(C1+C2), the ratios of C1 and C2 given in the equation (1) are made equal. Long term thermal drift of capacitors C1 and C2 is also compensated for by the auto-calibration loop. The main requirement on the capacitors C1 and C2 is therefore that they form a linear summation of the voltages SWVR and DA. Since the voltage at the terminal 75 is that which will actually cause the regenerative latch 74 to switch "low" or "high" at a given clock count, it is necessary, among other things, that the terminal 75 remain free of secondary parasitic effects. Thus it is important that the terminal 75 be disconnected from the VREF terminal 166 by the switch 164 slightly before the terminal 75 is disconnected from the VIN terminal 20 by the switch 174. This is achieved by the timing of signals PSMP and PVI (and their complements) as described previously in connection with FIGS. 4A, 4B and 4C. It is also necessary that the full settling time, due to the RC time constant at terminal 75, be allowed for during the auto-bias cycle which is initiated by phase P(0). Thus phase P(0) and the additional time of phase P(1) are allowed for auto-zeroing. Auto-calibration is provided for during phase P(2) and the sampling of the input voltage VIN is initiated on phase P(3). In FIG. 5 a preferred embodiment of the SAR 42 of FIG. 1 comprises eleven essentially identical circuits (shown within the dashed line boxes) of the positions "10" through "0", corresponding to the 10-bits of data plus one offset bit. For convenience, the positions 10 to 4 are shown on the right of the drawing, and positions 3 to 0 on the left. The position "10" corresponds to the most significant bit and position "0" to the least significant bit in the SAR 42. Position "3" corresponds to an "offset" bit. For convenience a table shown in FIG. 5A summarizes these bit positions and gives the corresponding outputs "D(9)" to "D(O)" as also indicated in the respective positions shown in FIG. 5. In FIG. 5, position 10 of the SAR 42 includes a first "NAND" gate 250 having an output at a terminal 252 which is cross-connected to an input 253 of a second "NAND" gate 254, the output of which, at a terminal 256, is connected to an input of an inverter 258 whose output is D(9). Terminal 256 is connected back to a first input 260 of the first NAND gate 250. When a second input 262 of the first NAND gate 250 is driven low via a lead 264 from an output of an inverter 266 whose input is coupled to and controlled by P(4), the output of the first NAND gate 250 at the terminal 252 goes high, and the output at the terminal 256 of the second NAND gate 254 goes low. This "low" is coupled back to the input 260 of the first NAND gate 250 so that its output at the terminal 252 is latched "high", and the terminal 256 held low. The inverter 258 then applies a high signal to its output D(9), which is equivalent to a binary "1" at position 10 of the SAR 42. The second NAND gate 254 has a second input terminal 268 which is connected to buss 270 (drawn vertically) which is connected to the output of an inverter 272 which is coupled by an input terminal to phase P(0) and is controlled by phase P(0). When phase P(0) occurs, the buss 270 goes low and the second NAND gate 254 is actuated so that its output at the terminal 256 goes high. This "high" is coupled back to the first NAND gate 250 so that its output at the terminal 252 goes "low" and latches the circuit in this alternate condition. The output at D(9) is now "low", equivalent to a binary "0". The second NAND gate 254 has a third input terminal 272 which is connected to the output of a NAND gate 274. A first input 275 of this NAND gate 274 is connected to the lead 41 (drawn vertically), which lead applies the single digit output of the comparator 40 (see also FIG. 1 and FIG. 3) to the SAR 42. A second input terminal 276 of the NAND gate 274 is connected to a lead 278 which is coupled to and actuated by phase P(5). When input terminals 275 and 276 of NAND gate 274 are both driven "high", the NAND gate 274 pulls "low" the third input terminal 272 of the second NAND gate 254. This sets the terminal 256 "high" and the terminal 252 "low" leaving them in this state. Output D(9) is then low (a binary "0"). If, on the other hand, the level on lead 41 had been "low", representing a binary "1" from the comparator 40, the terminal 256 would have been left "low" on the occurrence of phase P(5), and the output at D(9) set high (a binary "1"). The terminal 256 is also connected to the gate of an n-channel transistor 280 whose source is grounded. The drain of the transistor 280 is connected to the source of a second n-channel transistor 282 whose drain is connected to a high impedance load (not shown) connected to VDD. The gate of transistor 282 is connected to a buss 284 which will be described shortly. When the transistor 280 is disabled (i.e., biased off), the drain of the transistor 282 goes "high" (near VDD). When the transistor 282 and the transistor 284 are both enabled (i.e., biased on), the drain of the transistor 282 stays low (near ground). The gate of the transistor 280 is held low when the terminal 256 is low and thus the transistor 280 is held off. The drain of the second transistor 282 is pulled high to give at an output terminal MD(9) a binary "0". If on the other hand, the transistor 280 is enabled by its gate being held high, the drain of the second transistor 282 will go low when its gate, which is coupled to buss 284 and phase P(15) goes high. This signals at output MD(9), a binary "0". It will be seen that the gate of the transistor 282 is connected to a buss 284 which is common to all of the positions "10" to "0" of the SAR 42. This buss 284 is controlled by the phase P(15) which when "on" outputs all of the 11 binary signals MD(9) to MD(0) then stored in the SAR 42. The signal at MD(0) of position "0" is outputted as a binary "0" only if the buss 41 goes low and holds an n-channel transistor 280 in the register position "0" in an off condition. These 11 binary bits from the SAR 42 are applied in parallel to the output terminal 22 of the ADC 18 and thence to the MUX unit 28 as shown in FIG. 1. These 11 binary bits, though in non-standard binary format, are an accurate digital representation of the analog signal voltage which has been sampled at the input terminal 20. They are applied by the MUX unit 28 to the format converter unit 32 (known in the art) where the 10 MSB and LSB bits are added to the 1 offset bit and they are converted to the standard binary format (10 bits). Position 9 contains identical elements to those just described in connection with position 10. Of course, position 9 is actuated by phases P(5) and P(6), as shown instead of phases P(4) and P(5) which are used to actuate position 10. For position 8 NAND gate 290 thereof has an input terminal 292 connected to the buss 270. Thus when phase P(0) occurs and the buss 270 goes low, the output D(7) at position 8 goes high (a binary "1"). An upper input terminal 294 of the NAND gate 290 is connected through an inverter 296 (identical to the other inverters such as inverter 266) to receive an inverted phase P(6) signal. When phase P(6) occurs the output D(7) of position 8 is set to a binary "0". A NAND gate 298 of the position 8 has an input terminal 300 connected to a buss 302 which is connected through an inverter 304 to receive a phase P(2) signal as shown. When phase P(2) occurs, the output D(7) of position 8 is set to a binary "0". A NAND gate 306 of position 7 has an input terminal 307 which is connected to the buss 310. When phase P(2) occurs the output D(6) of position 7 is set to a binary "1". Positions 6, 5 and 4 are similarly connected to the buss 302 and are set to binary 1 by phase P(2). A NAND gate 308 of position 7 has an input terminal 309 connected to a buss 310 which in turn is connected to an output of a NOR gate 312. An input terminal 314 of NOR gate 312 is adapted to receive a phase P(0) and an input terminal 316 of NOR gate 312 is adapted to receive a phase P(3). Thus when either phase P(0) or P(3) is applied to NOR gate 312, buss 310 goes low and sets a binary 0 in position 7. Since positions 6, 5, and 4 are similarly connected to the buss 302, they are also set to binary 0 by phases P(0) and P(3). A NAND gate 318 of position 3 has an input terminal 320 connected through an inverter 322 to receive the inverse of the phase P(4) signal. A NAND gate 324 of position 3 has an input terminal 326 connected to the output of a NOR gate 328 whose two inputs are adapted to receive phases P(0) and P(9) as shown. Thus, whenever either phase P(0) or P(9) appears, the output D(3) at position 3 is set to binary 0. When phase P(4) occurs position 3 is set to binary 1 in a way similar to the setting of a binary 1 into position 8 by phase P(0). In FIG. 5, the setting and/or re-setting of the cross-coupled NAND gates 250 and 254 of position 10 have been described in detail. The setting and/or re-setting of the cross-coupled NAND gates in the other positions" 9" to "0" of the SAR 42 occur in similar fashion. The application of the phases P(0) to P(15) (but not P(1) which is not applied here) to the various elements in the SAR 42 is as indicated. In FIG. 6, a preferred embodiment of the MSB DAC 44 (FIG. 1) shows the input binary code of the three more significant bits (MSB) digits D(9), D(8) and D(7) (see FIG. 5 and 5A) and their eight decoded equivalents. Thus for the input signal binary "111", there are obtained from the SAR 42 the outputs D(9), D(8) and D(7) which are applied here in FIG. 6 to a first NAND gate 330. The output of gate 330 is applied to a first inverter 332 to obtain at an output of inverter 332 an output signal "T7". The output of the first inverter 332 is applied to an input of a second inverter 334 at the output of which is generated a signal "T7N" (the complement of T7). In FIG. 6, there are also seven identical circuits corresponding respectively to the binary codes "110" through "000" of the outputs D(9), D(8) and D(7). These circuits respectively produce the signals "T6" (and its complement T6N) through "T0" and "T0N". Similarly, the signals "T6", "T6N" through "T0" and T0N" are connected to a series of seven switches (identical to the switch 336), each of which is connected to a corresponding one of the taps VR(6) through VR(0) as shown. The signals T7 and T7N are applied to control terminals of a first transmission gate (switch) 336. The input of switch 336, at a terminal 338, is connected to a tap VR(7) of a precision resistor voltage divider (not shown). The taps VR(7) to VR(0) are each equally separated in voltage from each other. An eighth tap (not shown) is connected to the master voltage reference (not shown). Thus, tap VR(7) is 7/8ths of the master voltage reference, and tap VR(1), corresponding to the binary "001", is 1/8th the value. The switch 336, and seven other switches (with no reference numbers shown) like it, are connected to a buss 340 which in turn becomes the lead 46. The lead 46 applies the switched reference voltage SWVR to the input terminal 178 (also see FIG. 3) of the comparator 40. By way of example, the master voltage reference may be 5V exactly, and thus tap VR(1) is 1/8th of this value. The MSB DAC 44 thus converts into their analog equivalents, represented by voltage SWVR (accurately referenced to the master voltage reference), the binary bits of the positions 10, 9, and 8 of the SAR 42. Similarly, the LSB DAC converter 48 (FIG. 1) converts the binary bits of positions "7" to "0" of the SAR 42 into their analog equivalents as the analog voltage DA. The referencing of this voltage (auto-calibration) to the master voltage reference will now be described. In FIG. 3, the auto-calibration loop (including switch/filter unit 154, lead 52 and voltage VRDA, and lead 50 and voltage DA) has previously been described. The auto-bias voltage BV has now already been set to a desired value (phases P(0), P(1)). Positions "10", "9" and "8" of the SAR 42 (FIG. 5) are set to binary "001" so that voltage SWVR is at 1/8th (FIG 6). Upon initiation of the phase P(2), the four positions "7", "6", "5" and "4" of the SAR 42 are set to binary "1111" (positions "3", "2", "1" and "0" are set "0000"). At this point it should be noted that in a standard binary bit format, the first three positions 10, 9 and 8 of the SAR 42 represent 7/8ths of a total. That is, position 10 represents 1/2, position 9 represents 1/4th, and position 8, 1/8th for a sum of 7/8ths. Position 7 represents 1/16th, the next, 1/32nd, and position 5, 1/64th, and so on. However, by arbitrarily assigning to position 4 a value of 1/64th (instead of 1/128th), the combined weight of binary "1's" in positions 7, 6, 5 and 4 equals exactly 1/8th. Thus the analog value (i.e., the analog voltage DA) of these four bits when set "1111" can be compared to the analog voltage SWVR when it is set to 1/8th. If there is any difference then the auto-calibrating loop (described previously) automatically eliminates the difference by adjusting the voltage VRDA and hence the voltage DA. The positions 7,6,5, and 4 of the SAR 42 are set "1111" on phase P(2), and position 8 reset to "0" at this time, and positions 10, 9, 3, 2, 1, 0 are already set to binary "0". In FIG. 3, the input voltage VREF at input terminal 166 was applied at phase P(0) to terminal 75 by turning on the switch 164 as previously described (FIG. 4A). This charges the capacitor C2 to the difference in voltage between VREF and the voltage DA at terminal 180 (which on phase P(0) was set to zero). The capacitor C1 was charged to the difference between the voltage VREF and the voltage SWVR, the switch 176 being on at this time (see FIG. 4B). The voltage SWVR is set to 1/8th during phase P(0). Later, on phase P(2), when the voltage SWVR is set to zero and the voltage DA set to 1/8th, since capacitors C1 and C2 are effectively equal the voltage on the terminal 75 does not change (assuming the voltage DA is exactly equal to 1/8th). This voltage DA (for a bit value "11110000" applied to the LSB DAC 48) will have previously asymptoted, through the action of the auto-calibrating loop, to 1/8th of the master voltage reference (in a manner identical to the asymptoting of the bias voltage BV during auto-biasing). Any small difference between SWVR and DA is detected and voltage DA adjusted accordingly by the action of the auto-calibrating loop. Thus the analog voltage DA is accurately referenced (against voltage SWVR) to the master voltage reference. The extra weight assigned to the bit of position 4 of the register is equal to 1/128th (half of 1/64th). This extra weight is used as offset compensation to enable the comparator to operate at much higher speed. Because the time required for the charging to a voltage by a resistance-capacitance (RC) network is determined by the RC time constant, the voltage on terminal 75 (FIG. 3) does not instantly change to the charging voltage. There is a delay called "settling time", and it is related to the RC time constant and the voltage change. By initially adding a small "offset" voltage into the analog voltage DA at terminal 180, during the cycles that the higher values of the MSBs (and the next several LSBs) are being determined, comparator 40 can operate accurately at a rate faster than the "settling time" would otherwise permit. That is, the comparator, by virtue of this small compensating voltage (temporarily added to analog voltage DA), can make an accurate determination of these higher value bits at much higher speed (e.g., twice as fast) than would be possible if the comparator were delayed in its sampling by the full amount of the settling time. As the voltage "change" at terminal 75 (see equation (1)) becomes smaller and smaller, meaning that more and more "bits" have been determined by the SAR 42, the settling time decreases. At a suitable point in the operation of the SAR 42 the offset compensating voltage is removed, and the comparator 40 still operate accurately at the high speed it is being clocked at. When the comparator 40 is sampling the terminal 75 sooner than the settling time would otherwise permit, the comparator (without the "offset") may make an error (settling time error) either high or low. For example, if the input voltage at the terminal is greater than the binary value "1/2", but the comparator errs so that "1/2" is not included in the partial sum of the binary digits, then the maximum binary value of the remaining digits in the partial sum will always be less than "1/2". On the other hand, if the input voltage is less than the value "1/2", but the comparator errs so that "1/2" is included in the partial sum, then there is no way to reduce the partial sum using lower order bit values. Settling time errors are avoided by choosing an appropriate value of offset voltage (VO). The value of VO is relatively small (e.g., 1/64th in weighted value), but is large enough so that in determining the higher order bits (where the voltage changes on the terminal 75 may be relatively large and hence "settling times" longer) settling time is compensated for. By adding a voltage VO/2 to the analog voltage DA, the weighted value for the bits contributing to the partial sum in SAR 42 converges to VIN-VO/2. After determining the partial sum for bits which are weighted with values greater than VO, the VO/2 offset on analog voltage DA is removed, and an extra clock cycle is provided. This extra cycle enables the comparator 40 to determine whether the weighted value of the offset voltage VO should be added to the partial sum in the SAR 42 or left out. If added, then the error in the partial sum will be zero. If left out, the error will be -VO/2. Then on the next cycle, the next bit with a weighted value of VO/2 will either be left out or added to the partial sum. If added, an error of -VO/2 of the previous sum will be corrected; if left out no error needed to be corrected. In either case, VIN, without offset error, is now represented by the bits up to this point. The remaining lower order bits of the partial sum are then determined in order to obtain the N+1 bit value of VIN. In the SAR 42, the voltage VO has a binary weight represented by position 4 (1/64th), and VO/2 has the binary weight of position 3 (1/128th). A bit at position 3 is either added or not at phase P(12) depending on whether the comparator error is zero or - VO/2. Thereafter, because settling time is no longer a concern, as explained above, the comparator 40 continues on its regular clock cycle in determining the remaining bits without any offset (no longer needed). In FIG. 3, all of the "bits" of the SAR 42 are set to binary "0" when phase P(3) begins. The comparator 40 will have previously set the bias voltage BV, and the analog voltage DA (with offset) to desired values as previously described. Phase P(3) initiates the sampling of VIN by referencing it to VREF, SWVR and DA at the terminal 75 (see equation 1). The switches 164, 174, and 176 are turned on and off at phase P(3) as previously explained (see FIGS. 4A, 4B, and 4C). Then the comparator 40, at the beginning of clock pulse CK4, determines whether the voltage is higher or lower than the auto-zero switching voltage VSC. If lower, indicating a binary "1" for the first bit, corresponding to position 10 of the SAR 42, lead 41 goes low. Phase P(4) unconditionally sets position 10 to a binary "1". If lead 41 is low when phase P(5) occurs, position 10 remains at a binary "1". However if lead 41 is high (indicating that the first bit in the SAR 42 should be a binary "0"), phase P(5) and the "high" on lead 41 re-set position 10 to a binary "0". This procedure is then repeated phase after phase until all of the bits in the register are set. It should be noted that on phase P(14) position 0 is set to a "1" and on phase P(15) this bit is read either as a "1" or a "0" depending on whether lead 41 is low or high at that time, as was previously explained (FIG. 5). In FIG. 7, there is shown in summary table form the sequence of setting and re-setting of the bits in the SAR 42 phase by phase. After a complete cycle of the sixteen phases P has been completed, another cycle is begun. Looking at the location in the table corresponding to position 10 and phase P(4), the symbol 1/S shown indicates that the bit at this position 10 is conditionally set to a "1", and then on the following phase P(5) "set" (S) to its final value (either a "1" or "0"). At phase P(9) the offset compensating voltage on the analog voltage DA is removed by re-setting the "1" bit which had been present in the position 3 to a "0". Then, on phase P(10), the offset compensating bit (representing V0) at position 4 is set to a "1" and on phase P(11) is "set"(S) . On phase P(11) the bit at position 3 (representing V0/2) is set to "1" and on phase P(12) is "set" (S) to its final value. At phase P(15) all of the "set" (S) bits in the 11 positions of the SAR 42 are outputted, as explained previously. It is to be understood that the embodiments of architecture and circuits described herein are illustrative of the general principles of the invention. Modifications may readily be devised by those skilled in the art without departing from the scope of the invention. For example, circuit elements may be changed and the value of offset compensation may be different from that shown. Moreover the invention is not restricted to a particular speed or resolution or number of bits in a word, or to the number of ADCs in a parallel assembly. Still further, the ADC 18, with only one of same being used, does not require a MUX 28 and includes a format converter (adder) 32 so as to provide a standard output format. Furthermore, in some applications the DACs 44 and 48 can be combined into a single DAC and conductors 50 and 52 and their connections eliminated. In some other applications which use just a single DAC, a calibration line 52 is useful.

Claims: An analog to digital convertor (ADC) (18) for generating a digital value having P more significant bits and Q less significant bits where P and Q are integers greater than 1, the ADC comprising; comparator means (40) having an input terminal for sampling a residual input analog voltage during successive cycles of operation and for generating a succession of single-bit output (41) values each of which is either a binary 0 or 1 depending on whether the residual input analog voltage is below or above a bias voltage, the residual voltage at the input being subject to settling time; timing means (36) for driving the comparator means with clock pulses having a predetermined duration; and offset compensating means (42,48) for selectively adding a settling time offset voltage to the residual input analog voltage, the settling time offset voltage being added only when the P more significant bits of the digital value are being determined, the offset voltage having a magnitude corresponding to a predetermined one of the Q less significant bits. An ADC assembly (10) for generating a digital value having P more significant bits and Q less significant bits where P and Q are integers greater than 1, the assembly comprising: a plurality of analog to digital converters, each comprising: comparator means (40) having an input terminal for sampling a residual input analog voltage during successive cycles of operation and for generating a succession of single-bit values each of which is either a binary 0 or 1 depending on whether the residual input analog voltage is below or above a bias voltage, the residual voltage at the input being subject to settling time; and offset compensating means (42, 48) for selectively adding a settling time offset voltage to the residual input analog voltage, the settling time offset voltage being added only when the P more significant bits of the digital value are being determined, the offset voltage having a magnitude corresponding to a predetermined one of the Q less significant bits.; timing means (36) for controlling the analog to digital convertors; and a multiplexer, to receive the signals from each ADC and to output them sequentially. An ADC assembly (10) as described in claim 2, further comprising: a format convertor, to translate the P+Q bit signals received from the multiplexer into a P+Q-1 bit signal. An ADC as claimed in claim 1 or an ADC assembly as claimed in claim 2 or 3, wherein the offset compensating means comprises successive approximation register (SAR) means (42) having respective P+Q bit positions, the position of the said predetermined one of the Q less significant bits having a weighted value corresponding to the offset voltage. An ADC or ADC assembly as claimed in claim 4 further comprising a digital to analog converter (DAC) means (48) driven by the register means (42), the DAC means (48) having an output to which it applies the offset voltage. An ADC or ADC assembly as claimed in claim 5, further comprising auto-calibration means for accurately referencing the output of the DAC means. An ADC or ADC assembly as claimed in claim 6, wherein the auto-calibration means comprises feedback loop means (40, 52, 48) from the high speed comparator means (40) through the DAC means (48), the feedback loop means automatically referencing the output of the DAC to an accurately determined voltage. An ADC as claimed in claim 1 or 4 or an ADC assembly as claimed in claim 2, 3 or 4, wherein the comparator means comprises: latch means (74), which has a signal input (75), a bias input (78) and an output (76), for rapidly switching the output either high or low depending on whether the voltage on the signal input is higher or lower than a bias voltage on the bias input (78); clock means (36) to reset the latch means for a switching operation; input means (160) for selectively applying a voltage to be sampled or a reference voltage to the latch signal input; and auto bias means (120) for setting at a desired level for high sensitivity and switching speed a bias voltage (BV) on the latch bias input, the auto bias means being coupled between the latch output and the bias input; and wherein voltage reference feedback means comprises the latch means (74), the input means (160) and the auto bias means (120) for referencing the bias voltage (BV) at the latch bias input (78) to an accurately determined reference voltage such that the latch means switches high or low at a voltage very closely corresponding to the reference voltage. An ADC or ADC assembly as claimed in claim 8, wherein the latch means (74) comprises complementary p-channel (80, 90) and n-channel (84, 94) transistors regeneratively cross-coupled and symmetrically balanced such that the latch means switches very rapidly after being reset by the clock means, and such that the latch means is highly sensitive to voltage at the latch signal input (75), and has a high degree of immunity to common mode noise. An ADC or ADC assembly as claimed in claim 8 or 9, further comprising: analog means (44, 48) for applying to the input means (160) an incrementally changing voltage level (DA); and calibration feedback means from (116, 154, 158) the latch output (76) to the analog means (44, 48) for accurately controlling the changing voltage level of the analog means.

Inventors: SAUER DONALD JON, SAUER, DONALD JON
Applicants: SARNOFF CORP, SARNOFF CORPORATION
Application year: 1991
Main classification: H03M1
IPC codes: H03M1, H03K5