Method of preventing voltage variation in a semiconductor device

Abstract: A semiconductor memory device which is prevented from malfunction if a negative external potential (vin) is applied to an input circuit such as an address buffer circuit or a data-in buffer circuit during a function test. A p-well region (16) is formed in an n-type semiconductor substrate (11). A potential (V BB ) lower than the external input potential (Vin) is applied to the p-well region (16). There are formed a first n-type impurity diffused layer (12) to which the external input potential (Vin) is applied, and a second n-type impurity diffused layer (13) to which a reference potential (Vref) is applied. The potential (V BB ) applied to the well region is lower than Vin. Therefore, when Vin is negative, minority carriers generated do not migrate into the well region having a high energy potential and do not move into the second diffused layer. Therefore, Vref does not change and the device does not erroneously operate.

Description: Technical Field This invention relates to a method of preventing voltage variation in a semiconductor device. Background Art In a semiconductor memory device, input circuits such as a data-in buffer circuit and an address buffer circuit are provided. An address pin is connected to the input node of the address buffer circuit and a data pin is connected to the input node of the data-in buffer circuit, and an address and data are input to them. These input circuits detect the "High" or "Low" or "1" or "0" of data by comparing an externally input voltage (which is hereinafter simply referred to as vin) which is data of TTL level with a reference potential (which is hereinafter simply referred to as vref) and amplifies and converts the detected signal to a signal of MOS level used inside the memory device. Fig. 1 is an equivalent circuit diagram of the above address buffer circuit. The address buffer circuit is constructed to include p-channel MOS transistors Q1 and Q2, n-channel MOS transistors Q3 to Q10, and MOS capacitors C1 and C2. The operation of the circuit is controlled by internal control signals 1, 2 and 3 which are created based on a control signal (CAS, RAS or the like in a DRAM) input from the exterior and the circuit responds to the internal control signals at respective timings to latch the input address. Then, whether Vin is "High" or "Low" is detected according to whether the potential of Vin is higher than vref or not and it is output as address signals Aout and Aout . Vref is a potential used as a reference in the circuit operation of the semiconductor memory device and is created in the memory device. Vref is normally set at a positive potential and it is particularly important in the circuit operation to prevent variation in the potential. In a semiconductor memory device having the above-described input circuit, a test for checking the operation characteristic of the semiconductor memory device is effected by adding a negative potential (for example, approx. -2.0 V) to vin, but in this test, the following problems occur. The problem is explained with reference to Fig. 2. Fig. 2 is a cross sectional view showing the structure of a portion of a semiconductor memory device in which the n-channel MOS transistors Q3 to Q10 and MOS capacitors C1 and C2 of the address buffer circuit shown in Fig. 1 are formed. A p-well region 26 is formed in the main surface area of an n-type semiconductor substrate 21. n + -type impurity diffused layers 22 and 23 and a p + -type impurity diffused layer 28 are separately formed in the surface area of the p-well region 26. The impurity diffused layer 22 serves as a drain region of the MOS transistor Q9 and Vin is applied to the diffused layer 22 via a wiring 24. The impurity diffused layer 23 serves as a drain region of the MOS transistor Q10 and Vref is applied to the diffused layer 23 via a wiring 25. A ground potential (which is hereinafter simply referred to as Vss) is applied to the impurity diffused layer 28 via a wiring 27. As a result, the ground potential is applied to the p-well region 26. Although not shown in the drawing, the source regions of the n-channel MOS transistors Q9 and Q10, the source and drain regions of the n-channel MOS transistors Q3 to Q8, the MOS capacitors C1 and C2 and the like are formed in the p-well region 26. The p-channel MOS transistors Q1 and Q2 are formed in the main surface area of the substrate 21. With the above substrate structure, when a function test is effected by applying a negative potential to the above-described input pin, in other words, when Vin is a negative potential, minority carriers are generated in a junction between the impurity diffused layer 22 and the p-well region 26. As shown by the potential energy diagram in Fig. 3, part of the minority carriers flows into the n-type semiconductor substrate 21 but the remaining minority carriers which have lost their way flow into the impurity diffused layer 23 so that Vref may be lowered. Since Vref is a potential used as a reference in the circuit operation, the semiconductor memory device may be erroneously operated if the potential has varied. Thus, in the semiconductor device formed in the n-type semiconductor substrate, an erroneous operation caused by variation in the substrate potential due to injection of the minority carriers develops into a serious problem. Features corresponding to those in the preamble of claim 1 are shown in EP-A-0 245 515. Accordingly, an object of this invention is to provide a method of using a semiconductor device capable of eliminating the above-described conventional defects and enhancing the reliability. Disclosure of Invention According to the invention there is provided a method as set out in claim 1. Preferred features are set out in dependent claims. With the substrate structure used in the method of this invention, the third well region whose potential energy is lower than those of the first and second well regions is formed between the first and second well regions, minority carriers generated from the first well region are absorbed into the third well region and will not reach the second well region. Therefore, the minority carriers will not reach the second impurity diffused layer formed in the second well region and Vref will not be varied. Ground potential may be used as the first and second potentials and a power source potential may be used as the third potential as defined in claim 3. That is, since the power source potential is higher than the ground potential (the potential energy is lower), minority carriers generated in the first well region are absorbed into the third well region and will not reach the second well region. In this case, the power source potential is normally set at a positive potential and includes a potential obtained by lowering the power source voltage of the semiconductor device having a power source voltage drop circuit. Brief Description of Drawings Fig. 1 is an equivalent circuit diagram of an address buffer circuit, Fig. 2 is a cross sectional view showing the substrate structure of a conventional semiconductor device, Fig. 3 is a diagram showing the potential energy in the substrate structure shown in Fig. 2, Fig. 4 is a cross sectional view showing the substrate structure of a semiconductor device which does not form part of the claimed invention. Fig. 5 is a diagram showing the potential energy of the substrate structure shown in Fig. 4, Fig. 6 is a cross sectional view showing the substrate structure of a semiconductor device according to a second embodiment of this invention, and Fig. 7 is a diagram showing the potential energy of the substrate structure shown in Fig. 6. This invention will be explained in more detail with reference to the accompanying drawings. Fig. 4 is a cross sectional view showing the substrate structure of a semiconductor device, which does not form part of the claimed invention. In the substrate structure, for example, input circuits such as the data-in buffer circuit and address buffer circuit shown in Fig. 1 are formed. In the following description, a case wherein the address buffer circuit shown in Fig. 1 is formed is explained. A p-well region 16 is formed in the main surface area of an n-type semiconductor substrate 11. In the surface area of the p-well region 16, n + -type impurity diffused layers 12 and 13 and p + -type impurity diffused layer 18 are separately formed. The impurity diffused layer 12 serves as the drain region of the MOS transistor Q9 in the circuit shown in Fig. 1 and Vin is applied to the diffused layer 12 via a wiring 14. The impurity diffused layer 13 serves as the drain region of the MOS transistor Q10 in the circuit shown in Fig. 1 and Vref is applied to the diffused layer 13 via a wiring 15. A reference potential (which is hereinafter referred to as V BB ) of the semiconductor substrate 11 is applied to the impurity diffused layer 18 via a wiring 17. As a result, V BB is applied to the well region 16. Although not shown in the drawing, the source regions of the n-channel MOS transistors Q9 and Q10, the source and drain regions of the n-channel MOS transistors Q3 to Q8, MOS capacitors C1 and C2 and the like are formed in the p-well region 26. The source and drain regions of the MOS transistors Q3 to Q8 and the MOS capacitors C1 and C2 may be formed in a p-well region which is formed in position separated from the p-well region 16. The important thing is to form the source and drain regions of the MOS transistors Q9 and Q10 surrounded by broken lines in Fig. 1 in the p-well region 16. p-channel MOS transistors Q1 and Q2 are formed in the main surface area of the substrate 1. With the above substrate structure, since the potential applied to the p-well region 16 is changed from Vss (ground potential) set in the prior art case to V BB (for example, approx. -3.0 V) as shown in the potential energy diagram of Fig. 5, generated minority carriers will not move into the diffused layer 13 if Vin is kept higher than V BB (that is, | Vin | > | V BB | is satisfied) even if Vin is a negative potential, so that the potential of Vref will not be lowered by the minority carriers. Therefore, an error in the operation of the input circuit caused by reduction in Vref due to the injection of the minority carriers into the diffused layer 13 can be prevented. Fig. 6 is a cross sectional view showing the substrate structure of the semiconductor device according to an embodiment of this invention. In the substrate structure, for example, input circuits such as a data-in buffer circuit and an address buffer circuit shown in Fig. 1 are formed. In the following description, a case wherein the address buffer circuit shown in Fig. 1 is formed like the first embodiment is explained. In the main surface area of an n-type semiconductor substrate 1, a first p-well region 4 and a second p-well region 9 are separately formed. Further, an n-well region 14 is formed in that portion of the substrate 1 which lies between the first and second p-well regions 4 and 9. In the surface area of the well region 4, a p + -type impurity diffused layer 3 and an n + -type impurity diffused layer 6 are separately formed. Vss is applied to the impurity diffused layer 3 via a wiring 2 so that Vss can be applied to the well region 4. The impurity diffused layer 6 serves as the drain region of the MOS transistor Q9 in the circuit of Fig. 1 and Vin (externally input potential) is applied to the diffused layer 6 via a wiring 5. In the surface area of the well region 9, a p + -type impurity diffused layer 8 and an n + -type impurity diffused layer 20 are separately formed. Vss is applied to the impurity diffused layer 8 via a wiring 7 so that Vss can be applied to the well region 9. The impurity diffused layer 20 serves as the drain region of the MOS transistor Q10 in the circuit of Fig. 1 and Vref is applied to the diffused layer 20 via a wiring 10. Further, in the surface area of the well region 14, an n + -type impurity diffused layer 13 is formed and a power source potential (Vcc > 0) is applied to the diffused layer 13 via a wiring 12. Although not shown in the drawing, the source region of the n-channel MOS transistor Q9 is formed in the first p-well region 4 and the source region of the n-channel MOS transistor Q10 is formed in the second p-well region 9. The source and drain regions of the n-channel MOS transistors Q3 to Q8, MOS capacitors C1 and C2 and the like may be formed in the well region 9 or may be formed in a third p-well region which is formed in position separated from the first and second well regions 4 and 9. Further, the source and drain regions of the MOS transistors Q3, Q5, Q7 and Q9 and the MOS capacitor C1 may be formed in the first well region 4 and the source and drain regions of the MOS transistors Q4, Q6, Q8 and Q10 and the MOS capacitor C2 may be formed in the second well region 9. The important thing is to form the source and drain regains of the MOS transistor Q9 surrounded by broken lines in the first p-well region 4 and form the source and drain regions of the MOS transistor Q10 surrounded by broken lines in the second p-well region 9. p-channel MOS transistors Q1 and Q2 are formed in the main surface area of the substrate 1. With the above substrate structure, as shown in the potential energy diagram of Fig. 7, most of minority carriers generated in a junction portion between the diffused layer 6 and the first p-well region 4 when a negative potential is applied to Vin flow into the n-well region 14 which has a low energy potential. The second p-well region 9 having a high energy potential is disposed before the n-well region 14, and electrons which are minority carriers will not climb over the energy potential wall and are all collected by Vcc which is a potential of the n-well region 14. Therefore, the minority carriers will not move into the second well region 9 having the diffused layer 20 formed therein and connected to Vref. Thus, an error in the operation of the semiconductor device (in this example, which is the address circuit) caused by reduction in Vref due to the injection of the minority carriers can be prevented. Further, in the above-described second embodiment, the first p-well region 4, second p-well region 9 and n-well region 14 are formed in contact with each other, but they are not limited to this configuration and they may be disposed with a preset distance to attain the same effect. Further, Vss is applied to the first p-well region 4 and second p-well region 9, but a substrate potential (for example, approx. -3.0 V) of the semiconductor substrate 1 may be applied thereto to attain the same effect. Industrial Applicability As described above, in the substrate structure of the semiconductor device used according to this invention, an error in the operation of the semiconductor device due to variation in the reference potential caused by the minority carriers generated when a negative potential is applied as an externally input potential can be effectively prevented. Therefore, it is effective to enhance the reliability of the semiconductor device.

Claims: A method of preventing voltage variation in a semiconductor device, said semiconductor device comprising a semiconductor substrate (1) of first conductivity type, a first well region (4) of second conductivity type formed in said semiconductor substrate, a first impurity diffused layer (6) of the first conductivity type formed in said first well region, a second well region (9) of the second conductivity type formed in said semiconductor substrate, and a second impurity diffused layer (20) of the first conductivity type formed in said second well region; said method comprising applying a first potential to said first well region, applying a second potential to said second well region, applying an externally input potential to said first impurity diffused layer, applying a reference potential to said second impurity diffused layer; characterized by: providing said semiconductor device with a third well region (14) of the first conductivity type formed in that portion of said semiconductor substrate which lies between said first and second well regions, and said third well region only containing a third impurity diffused region (13) of the first conductivity type; and applying a third potential higher than said first and second potentials to said third impurity diffused layer. The method of preventing voltage variation in a semiconductor device according to Claim 1, characterized in that said first impurity diffused layer serves as a drain region of a first MOS transistor of a first channel type formed in said first well region and said second impurity diffused layer serves as a drain region of a second MOS transistor of the first channel type formed in said second well region. The method of preventing voltage variation in a semiconductor device according to Claim 1, characterized in that said first and second potentials are a ground potential, and said third potential is a power source potential. The method of preventing voltage variation in a semiconductor device according to Claim 3, characterized in that said first impurity diffused layer serves as a drain region of a first MOS transistor of a first channel type formed in said first well region and said second impurity diffused layer serves as a drain region of a second MOS transistor of the first channel type formed in said second well region. The method of preventing voltage variation in a semiconductor device according to Claim 3, characterized in that the power source potential is a potential lowered by a power source voltage drop circuit.

Inventors: FUJII SYUSO, SAKURAI KIYOFUMI, SHIMIZU MITSURU, FUJII, SYUSO, SAKURAI, KIYOFUMI, SHIMIZU, MITSURU
Applicants: TOSHIBA KK, TOSHIBA MICRO ELECTRONICS, KABUSHIKI KAISHA TOSHIBA, TOSHIBA MICRO-ELECTRONICS CORPORATION
Application year: 1991
Main classification: H01L27
IPC codes: H01L27