Digital comb filter

Abstract: A comb filter serves to process an input digital video signal which is derived from an analog video signal by a analog-to-digital conversion including a sampling process responsive to a system clock signal. The comb filter includes a separating device for separating the input video signal into a plurality of video signals which are offset with each other in timing and which have a clock rate equal to 1/N times a clock rate of the system clock signal where N denotes a predetermined natural number greater than 1. A first delaying device serves to delay a first output signal of the separating device. A chroma signal processor separates a first chroma signal in response to the first output signal of the separating device and an output signal of the first delaying device. A first subtracter serves to subtract the first chroma signal from the output signal of the first delaying device. A second delaying device serves to delay a second output signal of the separating device. An interpolating device serves to interpolate the first chroma signal into a second chroma signal to compensate for a difference in timing between the output signal of the second delaying device and the first chroma signal. A second subtracter serves to subtract the second chroma signal from the output signal of the second delaying device. A combining device serves to combine an output signal of the first subtracter and an output signal of the second subtracter into a luminance signal.

Description: BACKGROUND OF THE INVENTION This invention relates to a comb filter usable as a Y-signal/C-signal separation filter in color video systems and color television receivers. In general, color television receivers and color video systems include a filtering device for separately deriving a luminance signal (a Y signal) and a chroma signal (a color signal or a C signal) from a composite color video signal. Some of such Y/C signal separation devices include comb-type digital filters. As will be explained later, a prior art comb filter has some problems. Document US-A-4 345 268 discloses a comb filter for processing an input digital video signal which is derived from an analog video signal by an analog-to-digital conversion including a sampling process responsive to a system clock signal. It is an object of the invention to provide an improved comb filter. According to the invention this object is accomplished by a comb filter for processing an input digital video signal, which is derived from an analog video signal by an analog-to-digital conversion including a sampling process responsive to a system clock signal, said comb filter being characterized by separating means for separating said input video signal into a plurality of video signals which are offset from each other in timing and which have a clock rate equal to 1/N times a clock rate of said system clock signal where N denotes a predetermined natural number greater than 1; first delaying means for delaying a first output signal of said separating means; chroma signal processing means for separating a first chroma signal in response to said first output signal of said separating means and said output signal of said first delaying means; first subtracting means for subtracting said first chroma signal from said output signal of said first delaying means; second delaying means for delaying a second output signal of said separating means; interpolating means for interpolating said first chroma signal into a second chroma signal to compensate for a difference in timing between said output signal of said second delaying means and said first chroma signal; second subtracting means for subtracting said second chroma signal from said output signal of said second delaying means; and combining means for combining an output signal of said first subtracting means and an output signal of said second subtracting means into a luminance signal. According to the invention this object is also accomplished by a comb filter for processing an input digital video signal which is derived from an analog video signal by an analog-to-digital conversion including a sampling process responsive to a system clock signal, said comb filter being characterized by first delaying means responsive to said system clock signal for delaying said input video signal; second delaying means, responsive to a clock signal having a frequency equal to 1/N times a frequency of said system clock signal, for delaying said output signal of said first delaying means, where N denotes a predetermined natural number greater than 1; chroma signal processing means for separating a first chroma signal in response to said input video signal, said output signal of said first delaying means, and an output signal of said second delaying means; interpolating means for interpolating said first chroma signal into a second chroma signal which has a clock rate corresponding to said system clock signal; and subtracting means for subtracting said second chroma signal from said output signal of said first delaying means to separate a luminance signal. The advantages of the invention will become apparent and obvious to those skilled in the pertinent art upon referring to the following description provided in connection with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of a prior art comb filter. Fig. 2 is a block diagram of a comb filter according to a first embodiment of this invention. Fig. 3 is a timing diagram showing various signals in the comb filter of Fig. 2. Fig. 4 is a block diagram of a comb filter according to a second embodiment of this invention. Fig. 5 is a timing diagram showing various signals in the comb filter of Fig. 4. DESCRIPTION OF THE PRIOR ART As shown in Fig. 1, a prior art comb filter includes line memories 1 and 2, a chroma signal processor 3, and subtracter 4. The line memories 1 and 2 operate in response to a system clock signal fed from a clock signal generator (not shown). The line memory 1 delays a digitized input video signal R by a time corresponding to one line. The digitized video signal R is derived from an analog video signal by an analog-to-digital conversion including a sampling process with a predetermined sampling frequency equal to the frequency of the system clock signal. The line memory 2 delays the output video signal S from the line memory, 1 by a time corresponding to one line. The input video signal R, the output video signal S from the line memory 1, and the output video signal T from the line memory 2 represent image information on three successive lines respectively. The chroma signal processor 3 processes the video signals R, S, and T, and separates a chroma signal (a color signal, a C signal) U by using the chroma vertical correlation that the chroma signal is inverted alternately with respect to lines. The subtracter 4 subtracts the chroma signal U from the video signal S, and thereby derives a luminance signal V. In this way, the input video signal R is separated into the luminance signal V and the chroma signal U. The horizontal resolution is approximately proportional to the sampling frequency. Accordingly, to raise the horizontal resolution, it is necessary to increase the sampling frequency. In general, the increased sampling frequency necessitates a larger-scale circuit. For example. doubling the sampling frequency requires the scale of a circuit to be doubled or more. DESCRIPTION OF THE FIRST PREFERRED EMBODIMENT With reference to Fig. 2, a comb filter of a first embodiment of this invention includes separating means, i.e. a separation circuit 11 which separates a digitized input video signal A into two video signals B and C. The input video signal A is derived from an analog video signal by an analog-to-digital conversion including a sampling process with a predetermined sampling frequency equal to the frequency of a system clock signal. The comb filter also includes first delaying means, i.e. line memories 1 and 2, chroma signal processing means, i.e. a chroma signal processor 3, and first subtracting means, i.e. a subtracter 4. The line memory 1 delays the video signal B by a time corresponding to one line. The line memory 2 delays the output video signal D from the line memory 1 by a time corresponding to one line. The video signal B, the output video signal D from the line memory 1, and the output video signal E from the line memory 2 represent image information on three successive lines respectively. The chroma signal processor 3 processes the video signals B, D, and E, and separates a first chroma signal (a color signal, a C signal) F by using the chroma vertical correlation that the chroma signal is inverted alternately with respect to lines. The first chroma signal F is output from the comb filter. The subtracter 4 subtracts the first chroma signal F from the video signal D, and thereby derives a first luminance signal G. Further, the comb filter includes second delaying means, i.e. a line memory 12, interpolating means, i.e. an interpolation circuit 13, second subtracting means, i.e. a subtracter 14, and combining means, i.e. a combining circuit 15. The line memory 13 delays the video signal C by a time corresponding to one line. The interpolation circuit 13 generates a new, i.e. a second chroma signal I from the first chroma signal F through an interpolation process. The subtracter 14 subtracts the second chroma signal I from the output video signal H from the line memory 12, and thereby derives a second luminance signal J. The combining circuit 15 combines the first luminance signal G and the second luminance signal J into a final luminance signal K. The final luminance signal K is outputted from the comb filter. In this way, the input video signal A is separated into the (first) chroma signal F and the (final) luminance signal K. A further description will be given hereinafter with reference to Figs. 2 and 3. The digitized input video signal A is derived from the analog video signal by the analog-to-digital conversion including the sampling process in which the analog video signal is sampled in response to each pulse of a system clock signal CK, that is, the analog video signal is sampled at the frequency of the system clock signal CK. Therefore, as shown in Fig. 3, the input video signal A has a sequence of samples which occur synchronously with the system clock signal CK. The separation circuit 11 separates the input video signal A into the video signals B and C. As shown in Fig. 3, the video signal B has a sequence of odd-number samples, while the video signal C has a sequence of even-number samples. The video signals B and C have a period equal to twice the period of the system clock signal CK. Specifically, the separation circuit 11 includes a switch and latches, the switch separating the input video signal A into odd-number samples and even-number samples in response to the system clock signal CK, the latches holding and outputting the odd-number samples and the even-number samples. The line memory 1 delays the video signal B by a time corresponding to one line, so that the line memory 1 outputs the video signal D which is delayed from the video signal B by one line as shown in Fig. 3. The line memory 2 delays the video signal D by a time corresponding to one line, so that the line memory 2 outputs the video signal E which is delayed from the video signal D by one line as shown in Fig. 3. The video signals B, D, and E represent image information on three successive lines respectively. The chroma signal processor 3 processes the video signals B, D, and E, and separates the first chroma signal (a color signal, a C signal) F by using the chroma vertical correlation that the chroma signal is inverted alternately with respect to lines. As shown in Fig. 3, the first chroma signal F corresponds to the odd-number samples. The first chroma signal F is output from the comb filter. The subtracter 4 subtracts the first chroma signal F from the video signal D, and thereby derives the first luminance signal G. As shown in Fig. 3, the first luminance signal G corresponds to the odd-number samples. The line memory 13 delays the video signal C by a time corresponding to one line, so that the line memory 13 outputs the video signal H which is delayed from the video signal C by one line as shown in Fig. 3. The first chroma signal F and the video signal H are offset in timing from each other by one period of the system clock signal CK, and the first chroma signal F corresponds to the odd-number samples and the video signal H corresponds to the even-number samples as shown in Fig. 3. In view of this fact, the interpolation circuit 13 estimates the chroma components of the even-number samples from the chroma components of the odd-number samples represented by the first chroma signal F through an interpolation process, and thereby the interpolation circuit 13 generates the second chroma signal I which represents the chroma components of the even-number samples and which is in phase with the video signal H as shown in Fig. 3. The subtracter 14 subtracts the second chroma signal I from the video signal H, and thereby derives the second luminance signal J. As shown in Fig. 3, the second luminance signal J corresponds to the even-number samples. The combining circuit 15 combines the first luminance signal G and the second luminance signal J into the final luminance signal K. Specifically, the combining circuit 15 includes a switch which periodically and alternately selects one of the first and second luminance signals G and J in response to the system clock signal CK. As shown in Fig. 3, the final luminance signal K has a sequence of all samples which occur synchronously with the system clock signal CK. The final luminance signal K is outputted from the comb filter. In this way, the input video signal A is separated into the (first) chroma signal F and the (final) luminance signal K. As understood from Fig. 3, the separation of the input video signal A into the video signals B and C by the separation circuit 11 means a process of lowering the clock rate to a value corresponding to a half of the frequency of the system clock signal CK. Therefore, in the case where the sampling frequency related to the input video signal A is set equal to twice a typical prior art sampling frequency in order to double the horizontal resolution, the frequency of the signals processed by the line memories 1 and 2, the chroma processor 3, and the subtracter 4 agrees with the typical prior art sampling frequency so that these devices can be equal in structure to those in a prior art comb filter. In addition, the frequency of the signals processed by the line memory 12 and the subtracter 14 agrees with the typical prior art sampling frequency so that these devices can be equal in structure to typical prior art devices. It should be noted that this embodiment may be modified as follows. In a first modification of this embodiment, the input video signal A is separated into three video signals, and the clock rate is lowered to a value corresponding to one third of the frequency of the system clock signal CK. In a second modification of this embodiment, the input video signal A is separated into four video signals, and the clock rate is lowered to a value corresponding to one fourth of the frequency of the system clock signal CK. DESCRIPTION OF THE SECOND PREFERRED EMBODIMENT With reference to Fig. 4, a comb filter of a second embodiment of this invention includes first delaying means, i.e. line memories 22 and 2, chroma signal processing means, i.e. a chroma signal processor 3, subtracting means, i.e. a subtracter 4, and interpolating means, i.e. an interpolation circuit 21. The line memory 22 is designed so as to operate in response to a system clock signal CK fed from a clock signal generator (not shown). The frequency of the system clock signal CK is set equal to twice the frequency of a typical prior art system clock signal. The line memory 22 delays a digitized input video signal L by a time corresponding to one line. The digitized video signal L is derived from an analog video signal by an analog-to-digital conversion including a sampling process with a predetermined sampling frequency which equals the frequency of the system clock signal CK. The line memory 2 delays the output video signal M from the line memory 22 by a time corresponding to one line. The line memory 2 is designed so as to operate at a frequency equal to a half of the frequency of the system clock signal CK. The input video signal L, the output video signal M from the line memory 22, and the output video signal N from the line memory 2 represent image information on three successive lines respectively. The chroma signal processor 3 processes the video signals L, M, and N, and separates a first chroma signal (a color signal, a C signal) O by using the chroma vertical correlation that the chroma signal is inverted alternately with respect to lines. The first chroma signal O is output from the comb filter. The interpolation circuit 21 generates a new, i.e. second chroma signal P from the first chroma signal O through an interpolation process. The subtracter 4 subtracts the second chroma signal P from the output video signal M of the line memory 22, and thereby derives a luminance signal Q. The luminance signal Q is output from the comb filter. In this way, the input video signal L is separated into the (first) chroma signal O and the luminance signal Q. A further description will be given hereinafter with reference to Figs. 4 and 5. The digitized input video signal L is derived from the analog video signal by the analog-to-digital conversion including the sampling process in which the analog video signal is sampled in response to each pulse of the system clock signal CK, that is, the analog video signal is sampled at the frequency of the system clock signal CK. Therefore, as shown in Fig. 5, the input video signal L has a sequence of samples which occur synchronously with the system clock signal CK. The line memory 22 delays the video signal L by a time corresponding to one line, so that the line memory 22 outputs the video signal M which is delayed from the video signal L by one line as shown in Fig. 5. The line memory 2 delays the video signal M by a time corresponding to one line, so that the line memory 2 outputs the video signal N which is delayed from the video signal M by one line as shown in Fig. 5. Since the line memory 2 operates at a frequency equal to a half of the frequency of the system clock signal CK, the output video signal N from the line memory 2 has a clock rate equal to a half of the clock rate of the system clock signal CK and has a sequence of odd-number samples as shown in Fig. 5. The video signals L, M, and N represent image information on three successive lines respectively. The chroma signal processor 3 processes the video signals L, M, and N, and separates the first chroma signal (a color signal, a C signal.) O by using the chroma vertical correlation that the chroma signal is inverted alternately with respect to lines. As shown in Fig. 5, the first chroma signal O corresponds to the odd-number samples. The first chroma signal O is output from the comb filter. As shown in Fig. 5, the output video signal M from the line memory 2 has a sequence of all samples and has a clock rate equal to the clock rate of the system clock signal CK, while the first chroma signal O corresponds to the odd-number samples and has a clock rate equal to a half of the clock rate of the system clock signal CK. In view of this fact, the interpolation circuit 21 estimates the chroma components of the even-number samples from the chroma components of the odd-number samples represented by the first chroma signal O through an interpolation process, and thereby the interpolation circuit 21 generates the second chroma signal P which represents the chroma components of all the samples as shown in Fig. 5. The subtracter 4 subtracts the second chroma signal P from the output video signal M of the line memory 2, and thereby derives the luminance signal Q. As shown in Fig. 5, the luminance signal Q has a sequence of all samples which occur synchronously with the system clock signal CK. The luminance signal Q is output from the comb filter. In this way, the input video signal L is separated into the (first) chroma signal O and the luminance signal Q. As is understood from Fig. 5, the delay of the video signal M by the line memory 2 means a process of lowering the clock rate to a value corresponding to a half of the frequency of the system clock signal CK. Therefore, in the case where the sampling frequency related to the input video signal L is set equal to twice a typical prior art sampling frequency in order to double the horizontal resolution, the line memory 2 and the chroma processor 3 can be equal in structure to those in a prior art comb filter.

Claims: A comb filter for processing an input digital video signal (A), which is derived from an analog video signal by an analog-to-digital conversion including a sampling process responsive to a system clock signal, said comb filter being characterized by separating means (11) for separating said input video signal (A) into a plurality of video signals (B, C) which are offset from each other in timing and which have a clock rate equal to 1/N times a clock rate of said system clock signal where N denotes a predetermined natural number greater than 1; first delaying means (1, 2) for delaying a first output signal (B) of said separating means (11); chroma signal processing means (3) for separating a first chroma signal (F) in response to said first output signal (B) of said separating means (11) and said output signal (D, E) of said first delaying means (1, 2); first subtracting means (4) for subtracting said first chroma signal (F) from said output signal (D) of said first delaying means (1, 2); second delaying means (12) for delaying a second output signal (C) of said separating means (11); interpolating means (13) for interpolating said first chroma signal (F) into a second chroma signal (I) to compensate for a difference in timing between said output signal (H) of said second delaying means (12) and said first chroma signal (F); second subtracting means (14) for subtracting said second chroma signal (I) from said output signal (H) of said second delaying means (12); and combining means (15) for combining an output signal (G) of said first subtracting means (4) and an output signal (J) of said second subtracting means (14) into a luminance signal (K). A comb filter according to claim 1, characterized in that said first delaying means (1, 2) comprises a first delay circuit (1) for delaying said first output signal (B) of said separating means (11) by a first determined delay quantity, a second delay circuit (2) for delaying an output signal (D) of said first delay circuit (1) by a second predetermined delay quantity equal to the first predetermined delay quantity, said chroma signal processing means (3) comprises means for separating said first chroma signal (F) in response to said first output signal (B) of said separating means (11), said output signal (D) of said first delay circuit (1), and an output signal (E) of said second delay circuit (2), and said first subtracting means (4) comprises means for subtracting said first chroma signal (F) from said output signal (D) of said first delay circuit (1). A comb filter according to claim 2, characterized in that said first and second predetermined delay quantities correspond to an interval of one line, and said second delaying means (12) comprises a third delay circuit for delaying said second output signal (C) of said separating means (11) by a third predetermined delay quantity which corresponds to an interval of one line. A comb filter according to claim 2, characterized in that said first and second predetermined delay quantities correspond to an interval of one field or one frame, and said second delaying means (12) comprises a third delay circuit for delaying said second output signal (c) of said separating means (11) by a third predetermined delay quantity which corresponds to an interval of one field or one frame. A comb filter according to claim 1, characterized in that said natural number N is equal to 2. A comb filter for processing an input digital video signal (L) which is derived from an analog video signal by an analog-to-digital conversion including a sampling process responsive to a system clock signal, said comb filter being characterized by first delaying means (22) responsive to said system clock signal for delaying said input video signal (L); second delaying means (2), responsive to a clock signal having a frequency equal to 1/N times a frequency of said system clock signal, for delaying said output signal (M) of said first delaying means (22), where N denotes a predetermined natural number greater than 1; chroma signal processing means (3) for separating a first chroma signal (O) in response to said input video signal (L), said output signal (M) of said first delaying means (22), and an output signal (N) of said second delaying means (2); interpolating means (21) for interpolating said first chroma signal (O) into a second chroma signal (P) which has a clock rate corresponding to said system clock signal; and subtracting means (4) for subtracting said second chroma signal (P) from said output signal (M) of said first delaying means (22) to separate a luminance signal (Q). A comb filter according to claim 6, characterized in that said first delaying means (22) comprises a delay circuit for delaying said input video signal (L) by an interval of one line, and said second delaying means (2) comprises a delay circuit for delaying said output signal (M) of said first delaying means (22) by an interval of one line. A comb filter according to claim 6, characterized in that said first delaying means (22) comprises a delay circuit for delaying said input video signal (L) by an interval of one field or one frame, and said second delaying means (2) comprises a delay circuit for delaying said output signal (M) of said first delaying means (22) by an interval of one field or one frame. A comb filter according to claim 6, characterized in that said natural number N is equal to 2.

Inventors: OKUMURA NAOJI, SAKASHITA HIROHIKO, OKUMURA, NAOJI, SAKASHITA, HIROHIKO
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1991
Main classification: H04N9
IPC codes: H03H15, H04N9