Error correction system capable of correcting an error in a packet header by the use of a Reed-Solomon code

Abstract: In an error correcting system for use in transmitting a packet to a transmitter to a receiver, a packet header is preceded by an input signal and is formed by a Reed-Solomon code in the transmitter by adding an error correcting code to a header information signal. In the receiver, a plurality of syndromes are calculated by a syndrome calculator in response to the packet header to detect whether or not at least one error is included in the packet header. On detection of at least one error, an error correction circuit is energized in accordance with a program to locate and to correct the at least one error on the basis of procedure determined for correction of the Reed-Solomon code and may be structured by a plurality of hardware circuits.

Description: This invention relates to an error correction system for use in a packet exchange system which can transfer packets without necessity of re-transmission of information, such as datum, a speech, and an image. Heretofore, a packet exchange system of the type described is used for transferring a packet from a transmission end to a destination one of reception ends. In this event, information signals, such as a speech or voice signal and an image signal, are preceded by a packet header and are transmitted or conveyed by the packet in the packet exchange system which, is operable in accordance with non-high level date link control procedure. The packet header is helpful to specify the destination reception end and the transmission end. It is to be noted that no re-transmission is carried out in such a system and that the packet should be delivered to the destination reception end without fail. Otherwise, the information signals are undesirably sent to a wrong one of the reception ends. Therefore, correct transmission is required for the packet header as compared with transmission of the information signals, such as the speech and the image signals. In general, it is known that use of a Hamming code or addition of a parity bit is considered in connection with an information signal of a comparatively short data length of, for example, several bits. In this case, a single bit error or a double bit error is corrected by use of the Hamming code or addition of the parity bit when the information signal has a short date length, as mentioned before. It is mentioned here that the packet header is usually composed of a long data length of, for example, several tens of bits. In addition, the packet exchange system is often used in very bad circumstances such that the packet header is subjected to an influence of a noise. Taking this into account, a double error, a triple error or a t-tuple error more than the triple error very often takes place in the packet header and may be preferably corrected in each packet header. Conventionally, consideration is however directed neither to correction of the packet header nor to correction of a double or a triple error. GB-A-2216752 discloses a transmitter for use in transmitting a packet comprising: packet forming means responsive to said information signal and operable in accordance with a predetermined algorithm determined for production of a Reed-Solomon code, for forming a packet which is composed of said information signal and an error correcting code signal for correcting said information signal, said error correcting code signal being formed by the Reed-Solomon code; and signal producing means for producing said packet. IEEE TRANSACTIONS ON COMMUNICATIONS, vol. 35, no. 11, November 1987, NEW YORK, US; pages 1113 - 1123, MORTIMER ET AL 'the design of a high-performance error-correcting coding scheme for the canadian broadcast telidon system based on reed-solomon codes' discloses an error correcting system. A prefix code precedes the data block code. The prefix code is encoded with a hamming code to detect an error in the prefix. It is an object of this invention to provide an error correction system which is applicable to a packet exchange system and is capable of correcting a wide variety of errors in a packet header. It is another object of this invention to provide an error correction system of the type described, which is capable of correcting both single and double errors in the packet header. It is still another object of this invention to provide a transmitter which is applicable to the error correction system and which is capable of transmitting a packet header which can correct the single or the double error. It is yet another object of this invention to provide a receiver which is applicable to the error correction system and which is small in size and capable of preferably correcting the double error in the packet header. These objects are solved with the features of the claims. A transmitter as described is for use in transmitting a packet which includes an input signal and a header information signal which precedes said input signal. The transmitter comprises packet header forming means responsive to the header information signal and operable in accordance with a predetermined algorithm determined for production of a Reed-Solomon code. The packet header forming means is for forming a packet header which is composed of the header information signal and an error correcting code signal for correcting the header information signal. The error correcting code signal is formed by the Reed-Solomon code. The transmitter further comprises signal producing means for producing the packet header followed by the input signal to form the packet. Fig. 1 is a block diagram of a transmitter used for an error correction system according to a preferred embodiment of this invention; Fig. 2 is a block diagram of a receiver used for the error correction system according to the preferred embodiment of this invention; Fig. 3 is a time chart for use in describing operation of the transmitter illustrated in Fig. 1; Fig. 4 is a time chart for use in describing a relationship between a transmission data signal and a reception data signal which are produced and received bt the transmitter and the receiver, respectively; and Fig. 5 is a flow chart for use in describing operation of the receiver illustrated in Fig. 3. Referring to Fig. 1, an error correction system according to a preferred embodiment of this invention comprises a transmitter and a receiver both of which are illustrated in Figs. 1 and 2, respectively, and which are practically implemented by a very large scale integrated circuit (VLSI). Briefly, the transmitter illustrated in Fig. 1 produces a packet information signal which may be, for example, a data signal, a speech signal, or an image signal. In this case, the information signal is preceded by a packet header which specifies a destination receiver and the like and which comprises a header or a significant information signal of twenty-four bits and an error correcting code (namely, a redundancy code) following the header information signal. The packet information signal itself is directly regardless of this invention and will not be described any longer. In Fig. 3, the packet header is divided into the header information signal depicted at HI (Fig. 3) and the error correcting code which is shown as a forward error correcting code (FEC). The header information signal HI is subdivided into six signal units each of which is composed of four bits, namely, a half byte. The four bits are assumed to form a single symbol. The six signal units are represented by a5, a6, a7, a8, a9, and a10 with a0 to a4 omitted. This is because a0 to a4 are regarded as null data units in this invention, as will become clear as the description proceeds. In this connection, a5 to a10 may be referred to as first through sixth signal units, respectively, and regarded as being located at fifth through tenth symbol positions, respectively. On the other hand, the forward error correcting code (FEC) is added to the first through the sixth signal units a5 to a10 and is composed of first through fourth error code units r0 to r3 each of which is composed of four bits, namely, a half byte. It is to be noted that the illustrated packet header is formed by a Reed-Solomon code which is defined on a Galois field GF (2 4 ). Herein, let the Reed-Solomon code have a total symbol number equal to 15, a significant information symbol number equal to 11, and a minimum, hamming distance equal to 5 and be represented by RS (15, 11, 5). The Reed-Solomon code (15, 11, 5) can be defined by a polynomial P(x) of a fourteenth order which is given by: P(x) = a 0 x 14 + a 1 x 13 + ... + a 10 x 4 + r 0 x 3 + r 1 x 2 + r 2 x + r 3 . In the example, the significant symbol number is restricted to 6 and as a result, the total symbol number is equal to 10 as illustrated in Fig. 3. Under the circumstances, the first through the fourth error code units r0 to r3 may be collectively called the redundancy code and that are calculated in accordance with Equations 1 through 4 given by: r 0 = a 5 .α 7 ⊕ a 6 .α 13 ⊕ a 7 .α 6 ⊕ a 8 .α 13 ⊕ a 9 .α 14 ⊕ a 10 .α 12 r 1 = a 5 .α 7 ⊕ a 6 .α 6 ⊕ a 7 .α 8 ⊕ a 8 .α 7 ⊕ a 9 .α 4 ⊕ a 10 .α 12 r 2 = a 5 .α ⊕ a 6 .α 12 ⊕ a 7 .α 7 ⊕ a 8 .α 0 ⊕ a 9 .α 4 ⊕ a 10 r 3 = a 5 .α 4 ⊕ a 6 .α 12 ⊕ a 7 .α 4 ⊕ a 8 .α 5 ⊕ a 9 .α 3 ⊕ a 10 .α 6 where α 0 = (1000) = 8 H , α 1 = (0100) = 4 H , α 2 = (0010) = 2 H' α 3 = (0001)= 1 H , α 4 = (1100) = C H , α 5 = (0110) = 6 H , α 6 = (0011) = 3 H , α 7 = (1101) = D H , α 8 = (1010) = A H , α 9 = (0101) = 5 H , α 10 = (1110) = E H , α 11 = (0111) = 7 H , α 12 = (1111) = F H , α 13 = (1011) = B H , α 14 = (1001) = 9 H , and α 15 = α 0 and where in turn, ⊕ is representative of an Exclusive OR operation between four bits and four bits, a dot (.) is representative of a multiplication between a couple of four bits, and H is representative of a hexadecimal number. If x = α i , and y = α j , such a multiplication is given by α (i+j)mod 15 and will be called a specific multiplication. When either of x and y is equal to 0, the multiplication of x and y is equal to 0(0000). In Fig. 1, the transmitter is operable to calculate the first through the fourth error code units r 0 to r 3 in accordance with Equations 1 through 4 mentioned above. More specifically, the illustrated transmitter is successively supplied with an input signal or four bits, or each symbol unit in parallel through an input terminal 101. Each symbol unit of the packet header is sent to the transmitter in the order of a 5 , a 6 , a 7 , a 8 , a 9 and a 10 . In the example being illustrated, the transmitter comprises first through third multipliers 102 to 104 each of which carries out the multiplication between a couple of four bits, as mentioned above, end first through fourth registers 106 to 109 of four bits each of which is connected to first through fourth Exclusive OR gates 111 to 114 connected to the first through the third multipliers 104, 103, 102, and the input terminal 101. With this structure, the first signal unit a 5 of four bits is at first given as the input symbol unit to the input terminal 101 and is sent through the fourth Exclusive OR gate 114 to the first through the third multipliers 102 to 104 to be latched to the first through the fourth registers 106 to 109. In this event, the first register 106 is loaded with a product of a 5 .α 6 while the second register 107 is loaded with a 5 . Likewise, the third and the fourth registers 108 and 109 are loaded with a 5 .α 4 and a 5 .α 12 , respectively. Subsequently, the second through the sixth signal units a 6 to a 10 are supplied to the first through the third multipliers 102 to 104 through the input terminal 101 and the fourth Exclusive OR gate 114. As a result, the first through the fourth arror code units r 0 to r 3 represented by Equations 1 to 4 are produced through first through fourth output lines 116 to 119, respectively. Such production of the first through the fourth error code units r 0 to r 3 is carried out in accordance with the predetermined polynomial. In addition, the multipliers 102 to 104 are known in the art and will not be described in detail later. Thus, a combination of the multipliers 102 to 104, the registers 106 to 109, and the Exclusive OR gates 111 to 114 serves to form the packet header and may be called a packet header forming circuit. The output lines 116 to 119 may be referred to as a signal producing circuit for the packet header. Temporarily referring to Fig 4, it is assumed that the first through the sixth signal units to a 10 a 5 and the first through the fourth error code units r 0 to r 3 are transmitted from the transmitter to the receiver and received as first through sixth reception signal units b 5 to b 10 and first through fourth reception error code units t 0 to t 3 . In addition, the first through the sixth reception signal units b 5 to b 10 are decoded with reference to the first through the fourth reception error code units t 0 to t 3 into first through sixth decoded signal units which are depicted at b 5 ' to b 10 ' and which are subjected to error correction in the receiver illustrated in Fig. 2. Referring to Fig. 2 again and Fig. 5, description will be made about error correction of the packet header which is carried out in the receiver. In Fig. 2, the illustrated receiver is supplied with the packet header as a reception packet header and is specified by a decoder portion for decoding the packet header which is produced in the manner illustrated in Fig. 1. The reception packet header includes a reception packet header information signal and a reception error correcting code signal corresponding to the packet header information signal and the error correcting code signal. In Fig. 2, the decoder portion comprises 2 syndrome calculator 21 and an error detector 23 both of which are structured by a hardware circuit and the remaining hardware circuit which is operable in accordance with a microprogram formed by a special-purpose assembler. More specifically, the syndrome calculator 21 is successively supplied with each of the first through the sixth reception signal units b 5 to b 10 and the first through the fourth reception error code units t 0 to t 3 . On the other hand, the first through the sixth reception signal units b 5 to b 10 are sent to a reception register section 26 and memorized in first through sixth reception registers (depicted at b 5 to b 10 ) of the reception register section 26 each of which is composed of four bits. The syndrome calculator 21 is operable in a known manner to calculate first, second, third, and fourth syndromes S 0 to S 3 each of which is composed of four bits. Specifically, the illustrated syndrome calculator 21 calculates first, second, third and fourth values d 0 , d 1 , d 2 , and d 3 given by: d 0 = b 5 .α 4 ⊕ b 6 .α 12 ⊕ b 7 .α 4 ⊕ b 8 .α 5 ⊕ b 9 .α 3 ⊕ b 10 .α 6 ⊕ t 3 d 1 = b 5 .α 1 ⊕ b 6 .α 12 ⊕ b 7 .α 7 ⊕ b 8 .α 0 ⊕ b 9 .α 4 ⊕ b 10 .α 0 ⊕ t 2 d 2 = b 5 .α 7 ⊕ b 6 .α 6 ⊕ b 7 .α 8 ⊕ b 8 .α 7 ⊕ b 9 .α 4 ⊕ b 10 .α 4 ⊕ t 1 d 3 = b 5 .α 7 ⊕ b 6 .α 13 ⊕ b 7 .α 6 ⊕ b 8 .α 13 ⊕ b 9 .α 14 ⊕ b 10 .α 12 ⊕ t 0 Thereafter, the syndrome calculator 21 further calculates the first through the fourth syndromes S 0 to S 3 by the use of the first through the fourth values d 0 to d 3 in accordance with the following formulae. S 0 = d 0 ⊕ d 1 ⊕ d 2 ⊕ d 3 S 1 = d 0 ⊕ d 1 .α 1 ⊕ d 2 .α 2 ⊕ d 3 .α 3 S 2 = d 0 ⊕ d 1 .α 2 ⊕ d 2 .α 4 ⊕ d 3 .α 6 S 3 = d 0 ⊕ d 1 .α 3 ⊕ d 2 .α 6 ⊕ d 3 .α 9 Herein, it is to be noted that logic circuits which carry out the calculations of Equations 5 through 12 may be a combination of registers, multipliers, and Exclusive OR gates like in Fig. 1. Therefore, it is readily possible for those skilled in the art to design the syndrome calculator formed by such logic circuits. Taking the above into consideration, description will not be made about the syndrome calculator 21 any longer. At any rate, each of the syndromes S 0 to S 3 is composed of four bits. The first through the fourth syndromes S 0 to S 3 are delivered to the error detector 23 on one hand and to first through fourth syndrome registers (depicted at S 0 to S 3 ) of the reception register section 26 on the other hand. Supplied with the first through the fourth syndromes S 0 to S 3 , the error detector 23 detects from the first through the fourth syndromes S 0 to S 3 whether or not an error or errors are present in the packet header received and produces an error detection signal ED on detection of the error or errors. The error detection signal is sent to a program counter 27 and a process cycle indicator 28 to start them. As a result, the program counter 27 successively supplies a count signal to a read-only memory (ROM) 29 as an address signal. Inasmuch as the read-only memory 29 memorizes an error correcting program composed of a sequence of instructions. Each instruction is successively read out of the read-only memory 29 to be delivered to first through fourth instruction decoders 31 to 34. The first through the fourth instruction decoders 31 to 34 supply decoded signals to a timing controller 36 controlled by the process cycle indicator 28 energized by the error detector 23. The first decoder 31 is operable to decode an order of each instruction while the second through the fourth decoders 32 to 34 serve to decode operands which will be depicted at X 1 , X 2 , and X 0 hereinafter. The timing controller 36 produces first, second, and third gate control signals which may be called A, B, and C gate control signals. Besides, the timing controller 36 delivers a latch signal LA and a jump address signal JP to the reception register section 26 and the program counter 27, respectively. The jump address signal JP specifies an address to be jumped. Moreover, first and second constant signals CS 1 and CS 2 are also produced from the timing controller 36 to represent first and second constants. A combination of the elements 27, 28, 29, 31 to 34, and 36 may be called a program circuit for producing a sequence of instructions. In the illustrated example, the reception register section 26 further comprises I, F, K, L, R 1 , R 2 , and R 3 registers which may be collectively called a register circuit and which are operable in a manner to be described later in addition to the registers S 0 to S 3 and b 5 to b 10 . All of the registers S 0 to S 3 , b 5 to b 10 , I, F, K, L, and R 1 to R 3 are connected to first and second buses 41 and 42 through gates specified by A and B in Fig. 2 in a manner shown in Table 1. No. Registers A-Bus Connection B-Bus Connection C-Bus Connection Initial Load Operation of Registers 1 S 0 ○ ○ × ○ Memorizing syndromes S 0 to S 3 2 S 1 ○ ○ × ○ 3 S 2 ○ ○ ○ ○ (S 2 and S 3 are used as work registers) 4 S 3 ○ ○ ○ ○ 5 b 5 ○ × ○ ○ 6 b 6 ○ × ○ ○ Memorizing reception packet header 7 b 7 ○ × ○ ○ 8 b 8 ○ × ○ ○ Memorizing corrected packet header 9 b 9 ○ × ○ ○ 10 b 10 ○ × ○ ○ 11 I ○ × ○ × Memorizing error position 12 F ○ × ○ × Index register for LF and LFR orders 13 K ○ ○ ○ × Memorizing K constant calculated 14 L ○ ○ ○ × Memorizing L constant calculated 15 R 1 ○ ○ ○ × 16 R 2 ○ ○ ○ × Work registers 17 R 3 ○ ○ ○ × For example, the first through the fourth syndrome registers S 0 to S 3 are connected to both the A and B buses through the gates and are initially loaded with initial values, as understood from third, fourth, and sixth columns of Table 1. The first and the second syndrome registers S 0 and S 1 are not connected to the C bus 43 while the third and the fourth syndrome registers S 2 and S 3 are connected to the C bus 43. Anyway, the first through the fourth syndrome registers S 0 to S 3 serve to memorize the first through the fourth syndromes S 0 to S 3 , respectively. Among others, the third and the fourth syndrome registers S 2 and S 3 are also used as work registers. Likewise, the first through the sixth reception registers b 5 to b 10 are connected to the A bus 41 through the A gates and to the C bus 43 but disconnected to the B bus 42. The reception registers b 5 to b 10 are operable to memorize the reception packet header or a corrected packet header. The I register is for memorizing an error position signal indicative of an error position while the F register serves as an index register when specific orders, such as LF and LFR, are issued and will become clear. In addition, the K and the L registers serve to memorize K and L constants which will be described later and which are calculated while the R 1 to R 3 registers serve as work registers. Further referring to Fig. 2, the decoder portion comprises a calculation converting read-only memory (ROM) 46, an access section 47 for accessing the ROM 46, an Exclusive OR section 48, a loading section 49, and a comparator section 50, all of which are formed by hardware circuits and which may be referred to as a processing circuit for processing the reception packet header. As illustrated in Fig. 2, the access section 47 and the Exclusive OR section 48 are connected to the A and the B buses 41 and 42 and to the C bus 43 through the C gates C 1 and C 2 , respectively, while the loading section 49 and the comparator section 50 are connected to the A bus 41 through data lines and to the C bus 43 through the C gates C3 and C4. Such A, B, and C gates may be considered as a part of the processing circuit to selectively connect the registers and the hardware circuits 46 to 50. Moreover, the first through the sixth decoded units b 5 ' to b 10 ' are produced from the first through the sixth reception registers b 5 to b 10 with the error or errors corrected. Thus, the illustrated decoder portion is divisible into logical calculation circuits, such as the syndrome calculator 21 and the error detector 23, and a microprogram-controlled circuit, such as 26, 27, 28, 29, 31 to 34, 36, 46, 47, 48, 49, and 50. This makes it possible to reduce a size of the decoder circuit. In Table 2, orders and operands are enumerated which are issued from the microprogram memorized in the ROM 29 to locate the errors and to correct them when the errors are detected by the error detector 23 (Fig. 2). As tabulated in Table 2, first through seventeenth orders, such as M, DM, B, and the like in the microprogram are exemplified and delivered to the access section 47, the calculation converting RAM 46, the Exclusive OR section 48, the loading section 49, and the comparator section 50 in a manner to be described later. In the operands, the first through the seventeenth orders indicate operations shown in the columns of the meaning and the additional explanation and X 1 , X 2 , and X 0 represent values on the A bus, the B bus, and the C bus, respectively. Referring to Fig. 5 together with Fig. 2, description will be made about operation of the error correction. Such error correction is started from a first step 201 by the use of the microprogram memorized in the ROM 29. The first step 201 proceeds to a second step 202 at which Exclusive OR is calculated between a square value of the second syndrome S 1 and a product of the first syndrome S 0 and the third syndrome S 2 by the use of the Exclusive OR section 48. Before such Exclusive OR calculation, the second syndrome S 1 is read out of the second syndrome register S 1 and is delivered to the calculation converting RAM 46 to calculate the square of the second syndrome S 1 in accordance with the order of M. Likewise, the first and the third syndromes S 0 and S 2 are also read out of the first and the third syndrome registers S 0 and S 2 to calculate the product of both the syndromes. Thereafter, the comparator section 50 compares a result of the Exclusive OR with zero to detect whether or not a single error exists in the reception packet header. If the result of the Exclusive OR is equal to zero, a single error or no error is present in the reception packet header, as known in the art. In this event, the second step 202 is followed by a third step 203 to carry out single error correction. Otherwise, a double error or a t-tuple error more than the double error takes place in the reception packet header. Operation is carried out so as to correct the double error in a manner to be described later. Herein, it is to be noted that correction of a single and a double error in the Reed-Solomon code is carried out on the basis of a known procedure, although modification is somewhat made in procedure which will be described hereinafter, so as to readily process an error or errors. More specifically, let the result of the Exclusive OR in the first step 201 be equal to zero and the second step 202 proceed to a third step 203. At the third step 203, the second syndrome S 1 is divided by the first syndrome S 0 to obtain a result of division which is sent to the R 1 register (Fig. 2) and which is memorized as a first content represented by a vector representation. Such division is carried out by the use of the access section 47 and the calculation converting RAM 46. Subsequently, the first content of the R 1 register is converted into a power of α, as depicted at α R1 in Fig. 5, and memorized as a second content in the R 1 register again. Inasmuch as the total symbol number is equal to 15 and can be represented by a polynomial which has a maximum order equal to the fourteenth order, as known in the art, the second content of the R 1 register is subtracted from a predetermined constant of 14 to indicate an error symbol position depicted at U. Herein, it should be recollected that the significant information unit is arranged between the first and the sixth signal units a 5 and a 10 located at fifth through tenth symbol positions, as shown in Fig. 3 and that zeroth through fourth symbol positions are neglected. This shows that error correction may be carried out only between the fifth through the tenth symbol positions. Taking this into consideration, fourth and fifth steps 204 and 205 are for detecting whether or not the error symbol position U is present within a significant range between the fifth and the tenth symbol positions, both inclusive. If the error symbol position U does not exist within the significant range, the error correction is finished. Otherwise, the error symbol position U is sent to the F register (Fig. 2) to be held therein. The fourth and the fifth steps 204 and 205 are executed by the use of the comparator section 50 illustrated in Fig. 2. Under the circumstances, an error reception symbol positioned at the error symbol position U may be depicted at b(u) and should be corrected. To this end, Exclusive OR is executed between the error reception symbol b(u) and the first syndrome S 0 by the Exclusive OR section 48 to supply a result of the Exclusive OR to one of the first through the sixth reception registers b 5 to b 10 that corresponds to the error reception symbol b(u). In this case, an error symbol is corrected by the above-mentioned Exclusive OR into a correct symbol which is represented by b(i). At a sixth step 206, the error symbol position b(i) is rewritten by the loading section 49 to be corrected. Thus, correction of the single symbol error is carried out by the third through the sixth steps 203 to 206. On the other hand, let the result of the Exclusive OR be not equal to zero at the second step 202. In this event, the second step 202 is followed by operation of double error correction which is executed in a manner to be described hereinunder. The double error correction is started by setting the F and the I registers into zero and five, respectively. It is mentioned here that the F and the I registers are loaded with the number of the errors and an error symbol position, respectively. This means that the double error correction is started from the fifth symbol unit on the assumption that no error is detected. Under the circumstances, operation is carried out at a seventh step 207 which is for calculating Exclusive OR between a square of the second syndromes S 1 and a product of the second and the third syndromes S 1 and S 2 . The Exclusive OR calculation is made by the use of the Exclusive OR section 48 and a result of the Exclusive OR calculation is stored in the R 1 register as a first content or the R 1 register. A first product of the first and the fourth syndromes S 0 and S 3 is calculated together with a second product of the second and the third syndromes S 1 and S 2 by the use of the access section 47 and the calculation converting ROM 46. The first and the second products are memorized into the R 2 and the R 3 registers. Exclusive OR calculation is carried out between the first and the second products by the Exclusive OR section 48 to obtain a first result of the Exclusive OR calculation which is divided by the content of the R 1 register into a first result of division. The first result of division is held in the K register. Exclusive OR is carried out between a product of the second and the fourth syndromes S 1 and S 3 and a square of the third syndromes S 2 to calculate a second result of the Exclusive OR. The second result of the Exclusive OR is divided by the first content of the R 1 register into a second result of division sent to the K register. Such operation carried out at the seventh step 207 is made in accordance with algorithm determined in accordance with the Reed-Solomon code. At an eighth step 208, alpha (α) to the power stored in the I register is converted into a vector representation which is memorized in the R 2 register as a content of the R 2 register. In addition, Exclusive OR is carried out between a square of the content of the R 2 register and a product of a content of the K register and the content of the R 2 register to obtain a partial result of the Exclusive OR. Exclusive OR is further calculated between the partial result and a content of the L register to obtain a total result of the Exclusive OR. The total result is stored in the R 2 register. Thereafter, the eighth step 208 proceeds to a ninth step 209 at which the total result calculated by the eighth step 208 is compared with zero by the comparator section 50. If the total result is not equal to zero, the ninth step 209 proceeds to a tenth step 210 at which the content of the I register is compared with ten by the comparator section 50 to carry out the above-mentioned processing about a next following one of the significant symbol units. From this fact, it is readily understood that the total result of the R 2 register becomes equal to zero only when an error is present and, otherwise, the total result does not become equal to zero. When the content of the I register is not equal to ten, the tenth step 210 is followed by an eleventh step 211 at which unity is added to the content of the I register to obtain (I+1) stored in the I register again. The eighth through the eleventh steps 208 to 211 are repeated until the content of the I register becomes equal to ten. When the content of the I register becomes equal to ten at the tenth step 210, the tenth step 210 jumps to a twelfth step 212 of detecting whether or not the content of the F register is equal to zero. No error is found out as regards the reception packet header when the content of the F register becomes equal to zero. In this event, error correction operation is finished without any correction of an error. At the ninth step 209, it is assumed that the total result of the R 2 register is equal to zero. In this event, the ninth step 209 is succeeded by a thirteenth step 213 at which unity is added to the content of the F register. This shows that an error is detected at a symbol unit indicated by the content of the I register. At a fourteenth step 214, the content of the I register is subtracted from the predetermined number of 14 to specify an error symbol unit position which is held in the R registers. The fourteenth step 214 is followed by a fifteenth step 215 which is for judging whether or not the content of the F register is equal to two. The fifteenth step 215 is executed by the use of the comparator section 50. If the content of the F register is equal to unity, the fifteenth step 215 is succeeded by the tenth step 210 to locate an error symbol unit position in the manner mentioned before. On the other hand, if the content of the F register is equal to two, processing is carried out for correcting a double error in accordance with a known algorithm determined in the Reed-Solomon code. Specifically, the content of the R register is subtracted from the predetermined number of 14 at a sixteenth step 216 to obtain a result of subtraction which is held in the R 3 register. At a seventeenth step 217, a power representation of aR 3 is converted by the use of the calculation converting ROM 46 into a vector representation of R 3 which may be called a vector content of R 3 . Thereafter, the Exclusive OR is calculated between the second syndrome S 1 and (S 0 xL)/R 3 to attain a result of the Exclusive OR which is stored in the R 3 register. A content of the R 3 register is divided by the content of the K register into a result of division which is held in the R 3 register. Exclusive OR is calculated between the result of the division and b(R(F)) and is sent to the b(R(f)) register which specifies an error symbol unit. Such operation is carried out in accordance with the algorithm determined for the Reed-Solomon code. At an eighteenth step 218, judgement is made whether or not the content of the F register is equal to unity. If the content of the F register is equal to unity, a content bi of the b(R(f)) register is rewritten or corrected at a nineteenth step 219. Thus, a single error symbol is corrected at the nineteenth step 219. On the other hand, if the content of the F register is not equal to unity, the content of the I register is sent to the F register at a twentieth step 220 and the program returns back to the sixteenth step 216 to correct another error in a manner similar to that illustrated in conjunction with the steps 217, 218, and 219. Anyway, the double error is corrected in the significant symbol units. As mentioned above, the packet header is formed in the transmitter by the Reed-Solomon code which is a combination of a significant information signal of 24 bits with an error correcting code of 16 bits. Such use of the Reed-Solomon code enables error correction of two half bytes in the receiver by the use of the microprogram which defines procedure illustrated in Fig. 5. With this structure, it is possible to reduce a size of a hardware circuit and to shorten a processing time. In addition, it is possible to reliably transmit a data signal, a speech signal, and an image signal without necessity of distinction among them and without necessity of re-transmission. While this invention has thus far been described in conjunction with a preferred embodiment thereof, it will readily be possible for those skilled in the art to put this invention into practice in various other manners. For example, a wide variety of the Reed-Solomon codes may be used for correcting the error or errors. In Fig. 2, the calculation converting ROM 46 may be replaced by an RAM.

Claims: A receiver responsive to a packet which includes an input signal which conveys an information signal preceded by a packet header composed of a packet header information signal and an error correcting code signal formed by a Reed-Solomon code, characterized by syndrome calculation means (21) responsive to said packet header for calculating a plurality of syndromes on the basis of preselected formulae determined for the Reed-Solomon code; error detecting means (23) coupled to said syndrome calculating means (21) for detecting occurrence of an error in said packet header by monitoring said syndromes to produce an error detection signal on detection of said error; and error correcting means formed by a hardware circuit, energized by said error detection signal, and operable in accordance with a program determined for processing the Reed-Solomon code, for correcting said error in said packet header to produce the packet header information signal subjected to the error correction. A receiver as claimed in Claim 1, said program being composed of a sequence of instructions, wherein said error correcting means comprises: program means (27-36) energized by said error detection signal for storing said program to successively produce each of said instructions; register means (26) responsive to said reception packet header for registering said packet header; and processing means coupled to said program means (27-36) and said registering means (26) for processing said packet header in accordance with said program to correct said error in the packet header and to produce the packet header information signal. A receiver as claimed in Claim 2, said instructions including a first instruction for convertions between vector and power calculations, a second instruction for carrying out Exclusive OR, and a third instruction for comparison, wherein said processing means comprises: gate means (A1-C4) coupled to said register means (26) and said program means (27-36) for selectively producing said error correcting code signal and said packet header information signal in accordance with each of said instructions; calculation converting means (46) coupled to said gate means (A1-C4) on production of said first instruction for carrying out convertions between vector and power calculations; an Exclusive OR section (48) coupled to said gate means (A1-C4) on production of said second instruction for carrying out an Exclusive OR operation; and a comparator section (50) coupled to said gate means (A1-C4) on production of said third instruction for carrying out a comparison operation. An error correcting system for use in transmitting a packet from a transmitter to a receiver, said packet including an input signal and a header information signal which precedes said input signal and 5 being received by said receiver as a reception packet including a reception header information signal corresponding to said header information signal, said transmitter comprising: packet header forming means (102-104, 106-109, 111-114) responsive to said header information signal and operable in accordance with a predetermined algorithm determined for production of a Reed-Solomon code, for forming a packet header which is composed of said header information signal and an error correcting code signal for correcting said header information signal, said error correcting code signal being formed by the Reed-Solomon code; and signal producing means for producing said packet header followed by said input signal to form said packet; said receiver being supplied with said packet header as the reception packet header which includes a reception error correcting code signal corresponding to said error correcting code signal in addition to said reception header information signal, said error correcting system being characterized in that said receiver comprises: syndrome calculation means (21) responsive to said reception packet header for calculating a plurality of syndromes on the basis of preselected formulae determined for the Reed-Solomon code; error detecting means (23) coupled to said syndrome calculating means (21) for detecting occurrence of an error in said reception packet header by monitoring said syndromes to produce an error detection signal on detection of said error; and error correcting means formed by a hardware circuit, energized by said error detection signal, and operable in accordance with a program determined for processing the Reed-Solomon code, for correcting said error in said reception packet header to produce the reception packet header information signal subjected to the error correction.

Inventors: OKUYAMA HIDEKI, OKUYAMA, HIDEKI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1991
Main classification: H04L1
IPC codes: H04L1