A method of simulating the state of a linear feedback shift register

Abstract: The present invention discloses a method of simulating the state of a TYPE I Linear Feedback Shift Register (LFSR 100) with information available as a result of a TYPE II LFSR (500) implementation. This is accomplished by clocking a TYPE II LFSR (500) to produce an output sequence. This sequence, or at least a portion thereof, is then stored in a storage medium (501), such as, for example, a shift register. Cascading a TYPE II LFSR (500) output sequence into a shift register of length N, where N is the number of stages employed by the TYPE II LFSR (500), is the exact equivalent of a TYPE I LFSR (100). Accordingly, the shift register (501) content will contain data corresponding to the state of a TYPE I LFSR (100).

Description: Technical Field The present invention relates to shift registers, and particularly to linear feedback shift registers (LFSR). Specifically, however, the present invention pertains to a method of simulating the state of a LFSR. Background Of The Invention LFSRs are well known in the art. Typically, these devices are utilized in operations where the generation of a pseudonoise/pseudorandom (PN) code sequence is required. A PN code sequence is a binary signal which appears to be random. In reality, a PN code sequence is not random at all; it is a deterministic, periodic signal whose periodicity is dependent upon the number of stages within the LFSR, the feedback taps, and the LFSR's initial conditions. Typical operations employing LFSR's as PN code sequence generators are: spread spectrum systems, noise generators, and cryptographic systems. Fig. 1 depicts a simplistic representation of an LFSR 100. Mathematically, the LFSR defines an Nth degree polynomial (where N is the length of the LFSR) with one coefficient for each "tap" (output bit) used to form the feedback signal. Accordingly, the LFSR 100 is definable as a fourth degree polynomial, comprising the four stages 11-14, with feedback signal T 1 , obtained from the exclusive-or gate 15 acting upon the output of stages 13 and 14. T 1 is then fed back to the input of stage 11. It will be appreciated by those skilled in the art that the LFSR 100 is a simplistic model of a PN code sequence generator, selected primarily to show that an LFSR of the Nth degree is ultimately periodic in 2 n -1 bits (see Table 1). It will also be appreciated that the LFSR 100 represents a TYPE I LFSR. Type I, as used herein, defines an LFSR wherein the various flip flops or stages are cascaded together, input to output, without interruption by an intervening feedback signal. This configuration, which is typically based upon a hardware model, facilitates a simple determination of the LFSR's state. Accordingly, the four bits of information found in stages 11-14 of the LFSR 100 are readily available. This noted characteristic of the TYPE I LFSR, represents a decided advantage over alternative LFSR implementations which provide an identical output sequence. In many instances, the ability to simply replicate a TYPE I LFSR PN sequence is insufficient. Often, it is extremely important to know the state of a specific TYPE I LFSR stage, in conjunction with the PN output sequence. This data is often used in the performance of error-correction routines, phase continuity detection checks, and other control functions vital to overall system operation. TYPE I LFSRs enjoy this capability and therefore are still heavily used in computers and digital processing systems. Referring now to Fig. 2, FIG.2 depicts the LFSR 100 of Fig. 1 in its alternative configuration. The LFSR 200 of Fig. 2 is a TYPE II LFSR. TYPE II, as used herein, defines an LFSR wherein the various stages are cascaded together, however, the shift path is interrupted by the introduction of a feedback signal. The LFSR 200 consists of four stages 21-24, an exclusive-or gate 25, and feedback signal T 2 . According to this implementation, the exclusive-or gate 25 performs an exclusive-or operation on the outputs of stage 24 and 21. This operation is then used to determine the state of stage 22. Finally, the output of 24 is fed back to the input of stage 21. Of importance, Table 2, which denotes the operation of the LFSR 200, confirms that the output sequences generated by the TYPE I LFSR 100 and the TYPE II LFSR 200 are identical, but for the phase discontinuity caused by a timing shift. This output sequence appears as the pattern of bits in the 4th stages of LFSR 100 and 200. This same pattern of bits is repeated in each other stage, once again shifted in time. TYPE II LFSR's are generally based upon software models, and are therefore extremely economical, and efficient to implement in modern computers and digital processors. This becomes increasingly true as the number of stages and feedback taps increase. For instance, Fig. 1 and Fig. 2 both depict simplistic examples of LFSR's employing only four stages and a single tap. In practice, however, a moderate PN code sequence generator will employ in excess of 30 stages with anywhere from 1 to 30 feedback taps. In the preferred embodiment, LFSR 200 comprises a 64 stage shift register, providing a 64th degree polynomial. Approximately 32 taps are used to create the desired PN code sequence. This 64 bit maximal length LFSR will produce a sequence having approximately 1.84 × 10 9 bits. At 12 KHz, it will take nearly 48.7 × 10 6 years for this sequence to repeat. As PN code sequence generators continue to increase in sophistication, the modern trend is to employ the software implemented TYPE II LFSR where feasible. Unfortunately, the easier to implement TYPE II LFSR does not facilitate an easy or direct determination of the internal state of a TYPE I LFSR. While it is possible to compute the state of a TYPE I, the complexity of this operation and the impact upon system processing power mitigates the benefit derived from utilizing a TYPE II LFSR. Consequently, the inability of a TYPE II LFSR to directly determine the internal state of a corresponding TYPE I LFSR represents a major drawback in the design of a PN code sequence generator utilizing TYPE II LFSRs. This is particularly true in systems designed around a TYPE I implementation. In order to remove this barrier, it would be extremely advantageous to provide a method of simulating the state of a TYPE I LFSR from information available as a result of a TYPE II LFSR implementation. International Test Conference 1986 Proceeding (8 September 1986, Washington, pages 38-47) discloses hybrid schemes for the design of maximum-length sequence generators (MLSGs). The schemes involve a combination of both a Type I and a Type II LFSR in order to minimise the number of XOR gates used in a hardware implementation of MLSGs. This document also discloses a hybrid combination of a type I and a Type II LFSR to generate a maximum length sequence. Summary of the Invention Accordingly, a general object of the present invention, as claimed, is to provide a PN code sequence generator. It is another object of the present invention to provide a PN code sequence generator utilizing TYPE II LFSRs. It is the ultimate object of the present invention, however, to simulate the state of a TYPE I LFSR with information available as a result of a TYPE II LFSR implementation. These and other objects are achieved by the present invention which is briefly described as a method of simulating the state of an LFSR. This invention is based on an observation that after N clock cycles of a TYPE I LFSR, the sequence of obtained outputs is an exact representation of the LFSR's contents N clock cycles previously, where N is the length of the LFSR (number of stages). Furthermore, an appropriately initialized TYPE II implementation of a corresponding TYPE I LFSR, yields exactly the same output sequence. Therefore, it is possible to determine the internal state of each stage of a TYPE I LFSR from the information available as a result of a TYPE II implementation by advancing the clock of the TYPE II LFSR implementation, and simply capturing the output sequence which corresponds to the state of a corresponding TYPE I LFSR. Accordingly, the present invention suggests simulating the state of a TYPE I LFSR by clocking a TYPE II LFSR to produce an output sequence. This sequence, or at least a portion thereof, is then stored in a storage medium, such as, for example, a shift register. Cascading a TYPE II LFSR output sequence into a shift register of length N, where N is the number of stages employed by the TYPE II LFSR's, is the exact equivalent of a TYPE I LFSR. Assuming the TYPE I and the TYPE II LFSR are properly initialized, and the cascaded system has cycled some minimum number of times, the shift register output will contain data corresponding to the state of the TYPE I LFSR. In another embodiment, the present invention suggests simulating the state of a TYPE I LFSR by clocking a TYPE II LFSR to synchronize operation with a TYPE I LFSR, and to produce an output sequence. Once again, at least a portion of the output sequence is stored in a shift register, or in an equivalent storage medium. After synchronization, the TYPE II LFSR and shift register timing is adjusted in order to produce the state information of a TYPE I LFSR in the shift register. After the timing adjustment has been made, the shift register's state corresponds to at least a partial state of the TYPE I LFSR. Brief Description of the Drawings Fig. 1 depicts a simplistic representation of a LFSR; FIG. 2 depicts the LFSR of Fig. 1 in an alternative configuration; Fig. 3 depicts a PN code sequence generator and receiver utilizing a TYPE I LFSR implementation; Fig. 4 depicts the PN code sequence generator and receiver of Fig. 3 utilizing a TYPE II LFSR implementation; Fig. 5 depicts the LFSR configuration according to the present invention; and Fig. 6 depicts the LFSR configuration according to the present invention in a partial working environment. Detailed Description of the Preferred Embodiment A principal application of the present invention is for a PN code sequence generator and/or receiver like those employed in the field of cryptography. Fig. 3 depicts a PN code sequence generator and receiver. This figure is illustrative of a cryptographic channel which employs a TYPE I LFSR implementation to generate a PN key sequence. In operation, the receive LFSR 301 must first synchronize operation with that of the transmit LFSR 300. Accordingly, the switch S1 in the receiver is initially switched to the 1 position. This enables the receive LFSR 301 to receive the key sequence generated by the transmit LFSR 300. After at least N clock cycles, where N is the number of LFSR stages employed, the switch S1 is switched to the 2 position, in order to allow the receive LFSR 301 to operate in a closed loop fashion. The receiver can then generate the remainder of the PN key sequence autonomously. Referring to Table 3, it will be appreciated that the receiver is not fully synchronized until the Nth clock cycle. According to the example in Fig. 3, synchronization occurs on the 4th clock cycle, at which point the receive LFSR 301 state and output sequence lags the transmit LFSR state by 4 clock cycles. Referring now to Fig. 4, Fig. 4 depicts the PN code sequence generator of Fig. 3 implemented utilizing TYPE II LFSRs. Much like the previous example, switch S2 is first switched to position 1 in order to allow the receiver to synchronize operation. After N clock cycles, switch S2 is then switched to position 2 in order to allow the receive LFSR 401 to generate the remainder of the PN key sequence and to operate in a closed loop fashion, autonomous from the operation of the transmit LFSR 400. An example of the operation of the TYPE II LFSRs 400 and 401 is given in Table 4. Like the TYPE I LFSR previously discussed, the receive LFSR 401 will obtain synchronization in N clock cycles, where N is the length of the LFSR used. Unlike its TYPE I counterpart, however, the TYPE II receiver LFSR 401 will not lag behind the transmit LFSR 400 by N clock cycles. Upon initial synchronization, the receive LFSR 401 will be exactly synchronized in phase with the transmit LFSR 400 (see Table 4). As previously discussed a TYPE II implementation is generally favored over a TYPE I primarily because the the TYPE II configuration is easily modeled in software and is capable of producing the desired PN output sequence with negligible impact upon system processing power. Unfortunately, the TYPE II implementation suffers from the inability to readily disclose information pertaining to the internal state of a TYPE I LFSR. In order to overcome this shortcoming the present invention discloses a method of simulating the state of a TYPE I LFSR from the PN sequence generated by a TYPE II LFSR. According to the present invention, this is accomplished by capturing a TYPE II LFSR PN output sequence in a working (shift) register running with an advanced output phase. As previously discussed, the TYPE II implementation of a TYPE I LFSR yields exactly the same PN output sequence. It is possible therefore to determine the state of a TYPE I LFSR from the output of a corresponding TYPE II LFSR by advancing the clock of the TYPE II LFSR, and simply capturing the new PN output sequence which corresponds to the state of a simulated TYPE I LFSR. Fig. 5 depicts the LFSR configuration according to the present invention. As shown, this embodiment discloses the addition of a working register 501 to the TYPE II LFSR 500. In operation, the LFSR 500 is initialized via an initialization routine that establishes the LFSR's initial state. Next, the LFSR 500 is clocked to produce the PN sequence depicted in Table 5. This PN sequence is also clocked into the working register 501, which delays the PN sequence by an appropriate number of clock cycles in order to simulate the state of a TYPE I LFSR. From Table 5 it can be seen that the PN sequence of the working register 501 corresponds in phase to the PN sequence of the TYPE I LFSR 100 (refer to Table 1). Armed with this knowledge, it is now possible to simulate the internal state of a TYPE I LFSR from a TYPE II LFSR implementation without adversely impacting system processing power. As an example, Fig. 6 depicts the LFSR configuration according to the present invention in a partial working environment. As shown, LFSR configuration 500 is deployed within a cryptographic system as a PN code sequence generator. Since it is understood by those skilled in the art that other components and devices are ordinarily included in this environment, only those pertinent to this invention will be discused. The initial operation is identical to that discussed under Fig. 4. The switch S2 is first switched to position 1 in order to allow the receiver to synchronize operation. After N clock cycles, switch S2 is switched to position 2 in order to allow the receive LFSR 500 to generate the remainder of the PN key sequence and to operate in a closed loop fashion, autonomous from the operation of the transmit LFSR 100. Unique to the present invention is again the utilization of working register 501. In operation, after S2 is switched to position 2, and prior to the reception of the next bit by the receiver, the receive LFSR 500 output sequence is clocked into the working register a number of times to produce the desired state information and to appropriately delay the PN output sequence. The result being that the working register 501 content is an exact replication of the performance of a TYPE I LFSR 100. This can be seen by comparing the working register content of Table 5 with the transmit LFSR PN sequence in Table 5. While the present example establishes the entire state of a TYPE I LFSR, it will be appreciated by those skilled in the art that a partial state of a TYPE I LFSR may also be simulated. This is accomplished by reducing the size of the working register and the number of times the receive LFSR 500 output sequence is clocked into the working register. For example, in order to simulate the state of bit 13 of LFSR 100, the receive LFSR 500 output sequence would be clocked into the working register (adjusted) three times prior to the resumption of normal operation. In summary, the present invention discloses a a method of simulating the state of a TYPE I LFSR from information available as a result of a TYPE II LFSR implementation.

Claims: A method of simulating the state of a TYPE I Linear Feedback Shift Register (LFSR 100) characterized by the steps of: clocking a TYPE II LFSR (500) to produce an output sequence; and storing at least some of the output sequence in a storage medium (501), whereby the storage medium (501) contains data corresponding to at least a partial state of the TYPE I LFSR (100). A method as claimed in Claim 1, further comprising the step of: initializing the TYPE II LFSR (500) to correspond with an initial state of the TYPE I LFSR (100). A method as claimed in Claim 1, wherein an LFSR (100, 500) is a medium selected from the group of storage media consisting of: flip flops; latches; shift registers; working registers; memory device addresses; and software variables. A method as claimed in Claim 1, wherein the storage medium (501) is a medium selected from the group of storage media consisting of: flip flops; latches; shift registers; working registers; memory device addresses; and software variables. A method as claimed in Claim 1, further comprising the step of: adjusting the TYPE II LFSR (500) and storage medium (501) timing to produce state information. A method as claimed in Claim 5, wherein the step of adjusting the TYPE II LFSR (500) and storage medium (501) timing further includes the step of: advancing the TYPE II LFSR (500) and storage medium (501) clock prior to receipt of a next bit. A method as claimed in Claim 5, further comprising advancing the clock after synchronization. A method as claimed in Claim 5, wherein the TYPE II LFSR (500) is clocked to synchronize operation with the TYPE I LFSR (100). A circuit for simulating the state of a TYPE I Linear Feedback Shift Register (LFSR 100) characterized by: means (S2) for initializing a TYPE II LFSR (500) to correspond with an initial state of a TYPE I LFSR (100); clock means, coupled to the TYPE II LFSR (500) for clocking the TYPE II LFSR (500) to synchronize operation with the TYPE I LFSR (100) and to produce an output sequence; and storage means (501) coupled to the TYPE II LFSR (500) for storing at least some of the output sequence; said clock means, also coupled to the storage means (501) for adjusting TYPE II LFSR (500) and storage means (501) timing to produce state information; and whereby the storage means (501) contains data corresponding to at least a partial state of the TYPE I LFSR (100).

Inventors: KOTZIN MICHAEL D, WILSON ALAN L, KOTZIN, MICHAEL D., WILSON, ALAN L.
Applicants: MOTOROLA INC, MOTOROLA, INC.
Application year: 1991
Main classification: G06F7
IPC codes: G06F7, H04J13, G11C19, H03K3