Image processing Apparatus and image processing method

Abstract: An image processing apparatus of a digital copying machine or the like comprises: a color discriminating circuit to discriminate a color of an input image; a discrimination image generator to generate a color discrimination image in accordance with the discriminated color; and a trimming circuit to trim a boundary portion between the color discrimination image generated and another image. A blank portion or a boundary line is formed in the boundary portion between the color discrimination image and another image. The trimming circuit can also trim a portion in the color discrimination image in the boundary portion.

Description: The invention relates to an image processing apparatus for use in, for example, a digital copying apparatus, an image scanner, a printer, a facsimile apparatus, a display apparatus or their interface apparatuses. The invention also relates to an image processing method. In an image processing apparatus such as a digital copying apparatus, an original is illuminated by a halogen lamp or the like and a reflected light is photoelectrically converted by using a photoelectric conversion device such as a CCD or the like and, thereafter, the electric signal is converted into the digital signal and is subjected to predetermined processes, and an image is subsequently formed by using a recording apparatus such as laser beam printer, liquid crystal printer, thermal printer, an ink jet printer, or the like. In association with the realization of a color image formation of a copy original or the like, an output of a large information amount is demanded. In recent years, a copying apparatus in which the color is partially changed and a color image is copied by using developing devices of a plurality of colors has been developed. One aspect of the present invention is concerned with an image processing apparatus, as described in patent specification US-A-4369461, comprising: discriminating means for discriminating an area having a predetermined colour in an input image; converting means for converting said area discriminated by said discriminating means into a patterned area; and output means for outputting the patterned area. A colour image, for example as shown in Figure 19C of the accompanying drawings, can therefore be output as a patterned monochrome image as shown in Figure 19A1, but it will be appreciated that the resultant image is hard to see. Even if a plurality of colours of the input image are patterned differently, as shown in Figure 19A2, it is still fairly difficult to discriminate the foreground and background. The first aspect of the present invention is characterized by: second discriminating means for discriminating an outline of the area discriminated by the first-mentioned discriminating means to produce an outline image; and means for combining the outline image with the patterned area to be output by the output means. By adding and outputting the outline, the monochrome image becomes far clearer, as shown for example in Figure 19B. Other preferred features of the invention are defined in the claims. A second aspect of the invention provides a corresponding image processing method. Specific embodiments of the invention will now be described by way of example with reference to the accompanying drawings, in which:- Fig. 1 is a block diagram showing the first embodiment of the invention; Fig. 2 is a diagram showing a construction of a colour CCD image sensor 101 shown in Fig. 1; Fig. 3 is a timing chart showing example of timings of CCD drive pulses shown in Fig. 2; Fig. 4 is a block diagram showing a construction of a CCD driver 133 shown in Fig. 1; Fig. 5 is a timing chart showing examples of timings in respective sections shown in Fig. 4; Fig. 6 is a block diagram showing a construction of a black correction circuit in a black correction/white correction circuit shown in Fig. 1; Fig. 7 is a diagram showing the concept of black correction; Fig. 8 is a block diagram showing a construction of a white correction circuit in the black correction/white correction circuit shown in Fig. 1; Fig. 9 is a diagram showing the concept of white correction; Fig. 10 is a diagram showing examples of data for a white plate; Fig. 11 is a flowchart showing a procedure of the white correction by the white correction circuit; Fig. 12 is a block diagram showing a construction of a color detection circuit 109 shown in Fig. 1; Fig. 13 is a diagram showing a hue plane for explaining color recognition; Fig. 14 is a diagram showing a pattern generation circuit 111 and an address control circuit 112 shown in Fig. 1; Fig. 15 is a diagram showing addresses and data in an ROM for a pattern shown in Fig. 14; Fig. 16 is a diagram showing a pattern; Fig. 17 is a diagram showing timings of reference control signals; Figs. 18A to 18C are explanatory diagrams for explaining a trimming; Figs. 19A1, 19A2, 19B, and 19C are diagrams showing the trimming according to the first embodiment; Fig. 20 is a block diagram showing the second embodiment of the invention; Figs. 21A and 21B are diagrams showing filter masks for primary differentiation; Fig. 22 is an explanatory diagram for explaining a primary differentiating process; Figs. 23A and 23B are diagrams showing the relations between the primary differential value and the output signal; Figs. 24A to 24C are diagrams showing the emphasizing process according to the second embodiment; Fig. 25-1 is a circuit diagram of the third embodiment; Fig. 25-2 is a block diagram showing a construction of a color detection circuit 259 of the third embodiment; Figs. 26A to 26C are explanatory diagrams of the emphasizing process according to the third embodiment; Fig. 27 is a block diagram showing a construction of a contour detection circuit of the third embodiment; Figs. 28 and 29 are explanatory diagrams of the trimming process of the third embodiment; Fig. 30 is a diagram of a color boundary detection circuit of the fourth embodiment; Figs. 31A to 31D are explanatory diagrams of the color boundary detection of the fourth embodiment; and Figs. 32A to 32C are explanatory diagrams of the emphasizing process according to the fourth embodiment. Fig. 1 relates to an example of an image processing circuit apparatus. A full-color original is exposed by an exposure lamp (not shown). A reflected color image is photographed by a color CCD image sensor. A resultant analog image signal is converted into a digital signal by an A/D converter or the like. The digital full-color image signal is processed. The processed signal is supplied to a thermal printer, an ink jet printer, a laser beam printer, or the like (not shown), by which an image is obtained. The original is first illuminated by the exposure lamp (not shown). The reflected light is color separated every image by a color CCD image sensor 101. The respective color signals are read and amplified to predetermined levels by an amplifying circuit 102. The color CCD image sensor 101 is driven by a CCD driver 133. Fig. 2 shows the color CCD image sensor 101 shown in Fig. 1. The color CCD image sensor which is used in the embodiment has total 3072 = (1024 x 3) effective pixels because one pixel is set to 63.5 µ m and each pixel is divided into three effective pixels of G (green), B (blue), and R (red) in the main-scanning direction as shown in the diagram for 400 d.p.i. (dots per inch) and 1024 pixels in order to read image signals by dividing the original into five regions in the main-scanning directions. On the other hand, five sensors chips 58a to 62a are formed on the same ceramics substrate. The first, third, and fifth chips 58a, 60a, and 62a are arranged on a same line LA. The second and fourth chips 59a and 61a are arranged on a line LB which is away from the line LA by only a distance of four lines, that is, 254 µm (63.5 µm x 4). When the original is read, the original is scanned in the direction indicated by an arrow AL. Fig. 3 is a timing chart showing examples of timings of drive pulses shown in Fig. 2. Among the five CCD chips, the first, third, and fifth chips are independently synchronously driven by a group of drive pulses ODRV 118a and the second and fourth chips are also independently synchronously driven by a group of drive pulses EDRV 119a, respectively. Reference numerals 001A, 002A, and ORS included in the drive pulses ODRV 118a denote charge transfer clocks in the sensors. Reference numerals E01A, E02A, and ERS included in the drive pulses EDRV 119a denote charge reset pulses in the sensors. The above clocks or pulses are substantially synchronously generated so as not to cause a jitter in order to limit mutual interferences or noises among the first, third, and fifth pulses and the second and fourth pulses. For this purpose, those pulses are generated from a single reference oscillating source OSC (not shown). Fig. 4 shows a construction of the CCD driver 133 shown in Fig. 1. Fig. 5 is a timing chart showing examples of timings in the respective sections shown in Fig. 4. Clocks KO 135a which are obtained by frequency dividing original clocks CLKO generated from a single oscillating source OSC 558a are used to generate reference signals SYNC 2 and SYNC 3 to decide generation timings of the pulses ODRV and EDRV. Output timings of the reference signals SYNC 2 and SYNC 3 are determined inaccordance with set values of presettable counters 64a and 65a which are set by a signal line 22 connected to a CPU bus. Frequency dividers 66a and 67a and drive pulse generation circuits 68a and 69a are initialized by the reference signals SYNC 2 and SYNC 3 . That is, the pulse groups ODRV 118a and EDRV 119a are produced by the original clocks CLKO all of which are generated from the single OSC 558a and by the frequency division clocks all of which are synchronously generated while using an input horizontal sync signal HSYNC 118 as a reference. Consequently, those pulses are derived as synchronized signals having no jitter. A disturbance of the signals due to interferences among the sensors can be prevented. The sensor drive pulses ODRV 118a obtained synchronously with each other are supplied to the first, third, and fifth sensors 58a, 60a, and 62a. The synchronized drive pulses EDRV 119a are supplied to the second and fourth sensors 59a and 61a. Video signals V 1 to V 5 are independently generated from the sensors 58a, 59a, 60a, 61a, and 62a synchronously with the drive pulses and are amplified to predetermined voltage values by independent amplifying circuits 501-1 to 501-5 every channels shown in Fig. 1. The video signals V 1 , V 3 , and V 5 are transmitted through a coaxial cable 103 at timings of a pulse OOS 129 shown in Fig. 3. The video signals V 2 and V 4 are transmitted through the coaxial cable 103 at timings of a pulse EOS 134. The above video signals V 1 to V 5 are respectively supplied to a video image processing circuit. The color image signals which had been obtained by dividing the original to five regions and reading the image signals therefrom and which have been supplied to the video image processing circuit are respectively separated into the signals of three colors of G (green), B (blue), and R (red) by a sample and hold circuit (S/H circuit) 104. Thus, after the color image signals were sampled and held by the S/H circuit 104, fifteen (3 x 5) kinds of signals are processed. Returning to Fig. 1, the analog color image signals which have been sampled and held by the S/H circuit 104 every colors R, G, and B are converted into the digital signals by an A/D converting circuit 105 every channels 1 to 5. The digital signals are independently supplied in parallel to an aberration correction circuit 106 every channels 1 to 5. In the embodiment, as mentioned above (refer to Fig. 2), an interval corresponding to four lines, namely, 254 µm (= 63.5 µm x 4) is provided in the sub-scanning direction and the original is read by five zigzag sensors for the five regions obtained by dividing the original into five portions in the main-scanning direction. Therefore, there is a deviation between the reading positions of the channels 2 and 4 which have previously been scanned and the remaining channels 1, 3, and 5. To match the reading positions, such a deviation of the reading positions is corrected by the aberration correction circuit 106 having a memory of a plurality of lines. Fig. 6 shows a construction of a black correction circuit in a black correction/white correction circuit 107 shown in Fig. 1. As shown in Fig. 7, in the black level outputs of the channels 1 to 5, there are large variations among the chips and among the pixels when an amount of light which enters the color CCD image sensors is very small. If such black level outputs are directly supplied and an image is generated, stripes or a variation occur in the data portion of the image. To prevent them, it is necessary to correct an output variation of the black portion. Such an output variation is corrected by the circuit as shown in Fig. 6. Prior to the original reading operation, the original scanning unit is moved to a position of a black plate having a uniform concentration arranged in a non-image region of the front edge portion of the original base plate. The exposure lamp is lit on. The black level image signal is supplied to the black correction circuit. With respect to a blue signal B IN , in order to store the image data of one line into a black level RAM 78a, a terminal A is selected by a selector 82a ( d ○ ), a gate 80a is closed ( a ○ ), and a gate 81a is opened. That is, data lines are connected such as 151a → 152a → 153a. On the other hand, a signal c ○ is supplied to a selector 83a so that an output 154a of an address counter 84a which is initialized by a signal HSYNC and counts pixel clocks VCLK is supplied as an address input 155a of the RAM 78a. The black level signal of one line is stored into the RAM 78a (the above state is called a black reference value fetching mode). Upon reading of an image, the RAM 78a is set into a data reading mode. Data is read out of the RAM 78a every line and every pixel and is supplied to a B input terminal of a subtracter 79a along a path of a data line 153a → 157a. That is, at this time, the gate 81a is closed ( b ○ ) and the gate 80a is opened ( a ○ ). A selector 86a is connected to an A output. Therefore, for instance, in the case of a blue signal, a black correction circuit output 156a is derived as B IN (i) - DK(i) = B OUT (i) for black level data DK(i) (the above state is called a black correcting mode). Similarly, controls are also executed for a green signal G IN and a red signal R IN by signals 77aG and 77aR. Control lines a ○, b ○, c ○, d ○, and e ○ of gates of the selectors for the above control are controlled by a CPU on the basis of a latch 85a assigned as an I/O of a CPU 207 (Fig. 12). By selecting B input terminals of the selectors 82a, 83a, and 86a, the RAM 78a can be accessed by the CPU 207. Fig. 8 shows a construction of a white correction circuit in the black correction/white correction circuit 107 shown in Fig. 1. In the white level correction (shading correction), the original scanning unit is moved to the position of the uniform white plate and the original is illuminated. On the basis of the white color data obtained at this time, the illuminating system, the optical system, and a sensitivity variation of the sensors are corrected. A fundamental circuit construction of the white correction circuit is substantially the same as that shown in Fig. 6. In the black correction, the correction has been executed by the subtracter 79a. However, in the white correction, a multiplier 79'a is used and only this point is different. Therefore, the explanations of the same portions are omitted here. Upon color correction, when the color CCD image sensor 101 to read an original is located at the reading position (home position) of the uniform white plate, that is, prior to the copying operation or the reading operation, the exposing lamp (not shown) is lit on and the image data at a uniform white level is stored into a correction RAM 78'a of one line. For instance, if there is a width in the longitudinal direction of the A4 size original in the main-scanning direction, there are 4752 (= 16 x 297 mm) pixels at 16 pel/mm, that is, a capacity of the RAM is set to at least 4752 bytes. As shown in Fig. 9, in the case of white plate data W i (i = 1 to 4752) of the ith pixel, the data for the white plate is stored into the RAM 78'a every pixel as shown in Fig. 10. On the other hand, for a read value D i of an ordinary image of the ith pixel for W i , data D 0 after the correction should be equal to D i x FF H /W i . Therefore, gates 80'a and 81'a are opened by the CPU 207 for a ○', b ○', c ○', and d ○' of a latch 85'a. Further, signals are supplied to selectors 82'a, 83'a, and 86'a so as to select B input terminals, respectively, thereby enabling the CPU 207 to access the RAM 78'a. Subsequently, the CPU 207 sequentially calculates FF/W 1 , ... for FF H /W 0 and FF H /W i for a head pixel W 0 , thereby substituting the data in accordance with a procedure shown in Fig. 11. After completion of the data substitution for the blue component of the color component image (step B), the processes are likewise sequentially executed for the green component (step G) and the red component (step R). After that, the gate 80'a is opened (a ○') and the gate 81'a is closed (b ○') so that D 0 (= D i x FF H /W i ) is generated for the input original image data D i . The selectors 83'a and 86'a select A input terminals. The coefficient data FF H /W i which has been read out of the RAM 78'a is transmitted along a path of the signal lines 153a → 157a and is multiplied with the original image data 151a which has been supplied from one input terminal. The resultant data is generated. As mentioned above, by executing the corrections of the black level and the white level based on various factors such as black level sensitivity of the image input system, dark current variation of the CCD, sensitivity variation among the sensors, light amount variation of the optical system, white level sensitivity, and the like, image data B OUT 121, G OUT 122, and R OUT 123 which have been uniformly corrected every color for both of white and black are derived in the main scanning direction. The image data of R (red), G (green) and B (blue) each consisting of eight bits which have been subjected to the white correction and the black correction are subsequently supplied to a luminance signal generation circuit 108 and a color detection circuit 109 in Fig. 1. The luminance signal generation circuit 108 will be first-described. In the luminance signal generation circuit 108, an image which is not color separated and exists in a whole wavelength region, that is, a black and white image is produced from the color separated image which has been read by the color CCD image sensor 101. This is because the output means in the embodiment has only a monochromatic output means. In the luminance signal generation circuit 108, a calculation of the following equation is performed. Data out = (R + G + B)/3 That is, a mean value is calculated for the input R, G, and B data. In the embodiment, an adder and a multiplier have been used. The calculated luminance signal is sent to a selector 116, which will be explained hereinlater. In the embodiment, although the mean value of the R, G, and B data has simply been calculated, the luminance signal can be also obtained as Data out = 0.30R + 0.59G + 0.11B or can be also derived by using only the G data. Fig. 12 shows a construction of the color detection circuit 109 shown in Fig. 1. The R, G, and B input data to the luminance signal generation circuit 108 are also supplied to the color detection circuit 109. In the embodiment, the hue signal has been used as a color detecting method. This is because even in the case where saturations and brightnesses differ even for the same color, it is necessary to accurately discriminate. The color detecting method will be first schematically explained hereinbelow. Each of the input R, G, and B data consists of eight bits and has information of total 2 24 colors. Therefore, if such a great amount of information is directly used, the apparatus becomes expensive also in terms of a circuit scale. In the embodiment, the foregoing hue has been used. Although the above hue accurately differs from the hue which is generally expressed, it is called a hue here. As known by a Munsell's solid or the like, it is known that the color space is expressed by the saturation, brightness, and hue. The R, G, and B data first need to be converted into a plane, that is, two-dimensional data. Since the common portion of R, G, and B, namely, the minimum value min(R,G,B) of the R, G, and B data corresponds to the achromatic color component, the minimum value min(R,G,B) is subtracted from each of the R, G, and B data and the remaining data are used as chromatic color components, thereby converting a three-dimensional input color space into a two-dimensional color space. As shown in Fig. 13, the converted plane within a range from 0° to 360° is divided into six regions. The hue values are obtained by the information of the order of the magnitudes of the input R, G, and B data, namely, the information such as R > G > B, R > B > G, G > B > R, G > R > B, B > G > R, and B > R > G and by the maximum value and the middle value of the input R, G, and B data by using a lookup table (LUT) or the like. The operation of the color detection circuit 109 will now be described. The input R, G, and B data are first supplied to a max/mid/min detection circuit 201 to discriminate the magnitudes of the R, G, and B data. Each of the input R, G, and B data is compared by using a comparator and the maximum (max) value, middle (mid) value, or minimum (min) value is generated in accordance with the result of the comparison. An output value of the comparator is generated as an order signal. For the max, mid, and min values generated, in order to subtract the achromatic color component from the max value and the mid value as mentioned above, the minimum (min) value is subtracted from the max value and the mid value by subtracters 202 and 203. Output signals of the subtracters 202 and 203 are supplied to a hue detection circuit 204 together with the order signal. The hue detection circuit 204 is constructed by a memory device such as RAM, ROM, or the like which can be accessed at random. In the embodiment, a lookup table is constructed by using an ROM. Values corresponding to angles of planes as shown in Fig. 13 have previously been stored in the ROM. The hue value is generated from the ROM in accordance with the order signal (max - min) value and (mid - min) value which are input. The generated hue value is subsequently sent to window comparators 205 and 206. Color data to be inherently patterned is supplied to the comparators 205 and 206 from data input means (not shown). Desired offset values are given to the hue data values according to the color by the CPU 207 and the resultant values are set into the comparators 205 and 206. Assuming that a set value is a 1 , the comparator 205 generates a "1" signal for the input hue data when the hue data is smaller than the set value a 1 . Assuming that a set value is a 2 , the comparator 206 generates a "1" signal when the hue data is larger than the set value a 2 . Therefore, when a 1 < hue data < a 2 a "1" signal is generated from the color detection circuit 109 by an AND gate 208 at the post stage. It will be obviously understood that a plurality of detection colors are set in the case of using a plurality of sets of window comparators. A discrimination signal indicative of the result of the discrimination by the color detection circuit 109 is sent to an AND gate 110 and the selector 116. The AND gate 110 calculates the AND of such a discrimination signal and a pattern signal which is generated from a pattern generation circuit 111, which will be explained hereinlater. The selector 116 will be explained hereinlater. The pattern generation circuit 111 and an address control circuit 112 will now be described with reference to Fig. 14. The pattern generation circuit 111 has an ROM 705 in which pattern dot data corresponding to each hue has been stored. As shown in Fig. 15, data of "1" and "0" have been written in addresses corresponding to upper and lower addresses in the ROM 705. Fig. 16 shows a pattern which is formed by the above data. As shown in Fig. 14, address signals of the ROM 705 are formed by a main-scan counter 701 and a sub-scan counter 703 which are synchronized with the pixel clock VCLK and a scan reference signal HSYNC. Reference signals ITOP, HSYNC, and VCLK are timing signals as shown in Fig. 17. The ITOP signal is a signal indicative of an image edge and is set to the low level while the scanner reads the image. The main-scan counter 701 counts the signals VCLK synchronously with the HSYNC signal. The sub-scan counter 703 counts the signals HSYNC synchronously with the ITOP signal, thereby forming an address in the pattern ROM 705. The pattern signal which has been used to calculate the AND by the AND gate 110 on the basis of the result of the discrimination by the color detection circuit 109 is supplied to a multiplier 113, by which it is multiplied to the video signal of min(R,G,B). The min(R,G,B) signal is a signal which is produced by the color detection circuit 109 and is a signal indicative of the minimum value (darkest) among the color separated video signals of the input R, G, AND B data. There is a case where the signal level of the signal which is formed by the luminance signal generation circuit 108 differs depending on the color and, for instance, the signal level for the yellow color approaches white, so that the image data of the original lacks. The min(R,G,B) is provided to prevent such a case. The min(R,G,B) signal is also supplied to a contour extraction circuit 114, by which a contour is extracted. The contour is extracted by a Laplacian filter which is generally known. The extracted contour signal is added to the patterned min(R,G,B) signal sent from the multiplier 113 by an adder 115. That is, the contour signal indicative of the contour and shown in Fig. 18A is added to the min(R,G,B) signal indicative of the pattern and shown in Fig. 18B, so that the min(R,G,B) signal indicative of an emphasized pattern shown in Fig. 18C is derived. A signal generated from the adder 115 is subsequently transferred to the selector 116. The foregoing luminance signal and the min(R,G,B) signal indicative of the emphasized pattern are given to the selector 116. The selector 116 executes a switching operation on the basis of the result of the detection from the color detection circuit 109. An output signal of the selector 116 is sent to a LOG conversion circuit 117 to convert the luminance signal into the concentration signal. The converted concentration signal is generated from the LOG conversion circuit 117. By adding the contour signal to the image signal indicative of the pattern, an image as shown in Fig 19B can be derived from an original of Fig. 19C. (Unlike Fig. 18, in Fig. 19B the background rather than the foreground has been patterned.) Even if the image has been patterned, it can be expressed without making it hard to see the image. <Second embodiment> Fig. 20 shows the second embodiment of the invention. The embodiment relates to an example of an image processing apparatus in the case where a white space is inserted into a contour portion. In Fig. 20, reference numerals 101 to 104, 117, and 133 denote the same portions as those in Fig. 1. The contour extraction circuit 114 executes a filtering process to perform a primary differentiating process to the min(R,G,B) signal. In the filtering process, an arithmetic operation is executed by using masks shown in Figs. 21A and 21B. Fig. 21A shows the mask to calculate a primary differential value for the main-scanning direction. The following calculation is performed. ΔH = D j-1,i-1 + D j,i-1 + D j+1,i-1 - (D j-1,i+1 + D j,i+1 + D j+1,i+1 ) D ij = min(R ij ,G ij ,B ij ) where, i : pixel number j : line number Fig. 21B shows the mask to calculate a primary differentiation value for the sub-scanning direction. The following calculation is executed. ΔV = D j-1,i-1 + D j-1,i + D j-1,i+1 - (D J+1,i-1 + D j+1,i + D j+1,i+1 ) Fig. 22 shows the relation between the input min(R,G,B) signal and the primary differentiation value in only a single direction. The value indicative of the sum of the absolute values of those primary differentiation values is obtained as a primary differentiation value S. S = ΔH + ΔV A predetermined slice level T is arbitrarily set for the value of S derived as mentioned above. A "0" or "1" signal is generated on the basis of the following conditions. S > T ... 0 signal S ≧ T ... 1 signal Figs. 23A and 23B show examples of a primary differentiation value and an output signal. The AND of the output signal and the patterned min(R,G,B) signal is subsequently calculated by an AND gate 128. That is, in the edge portion of S > T, the patterned min(R,G,B) signal is masked and is supplied to a selector 129. As shown in Figs. 24A to 24C, in an image which has simply been patterned as shown in Fig. 24A from an original of Fig. 24C, a white portion is formed between the pattern and a non-pattern as shown in Fig. 24B, so that the non-pattern portion can be easily seen. Although an example in which two filters are used as a contour extraction circuit 114 has been described, it is also possible to cope with both of the main-scanning direction and the sub-scanning direction by one filter. On the other hand, to enable an edge to be easily discriminated, the maximum value signal (max signal) can be also used in place of the minimum value signal (min signal) or the luminance signal can be also used. Third Embodiment: Figs. 25-1 to 25-2 show the third embodiment of the invention. The embodiment relates to an example in the case where a white blank contour is provided between a black character and a pattern and a black contour is provided between the pattern and a white image and a white contour is provided for the inside (pattern side) of the black contour. Fig. 25-1 is a block diagram showing a construction of a contour process in the third embodiment. Since a circuit construction until the luminance signal generation circuit 108, the pattern generation circuit 111, and the address control circuit 112 are similar to the foregoing first and second embodiments, their descriptions are omitted here. A color detection circuit 259 will be first explained with reference to Fig. 25-2. The color detection circuit 259 is fundamentally similar to the color detection circuit 109 in the first and second embodiments. However, a circuit to obtain an achromatic color signal is added in addition to the circuit 109 in the first and second embodiments. An output of the subtracter 202 to subtract the minimum value from the maximum value is supplied to a comparator 209-a and is compared with a value which has been set by the CPU (not shown). A comparison result is generated from the comparator 209-a. That is, when a difference between the maximum value and the minimum value of the input R, G, and B data is small, the pixel data is determined to be an achromatic color. The color detection signal detected by the color detection circuit 259 on the basis of the input R, G, and B data is supplied to a contour extraction circuit 250 in Fig. 25-1 and as a selection signal to a pattern synthesis selector 251. The output signal from the luminance signal generation circuit 108 and the output signal from the pattern generation circuit 111 are given to the selector 251. When the color detection signal is at the "1" level, in other words, when a predetermined color has been detected, a B input terminal is selected. If no color is detected, an A input terminal is selected, namely, the luminance signal from the luminance signal generation circuit 108 is selected. The contour extraction circuit 250 extracts three kinds of contour signals shown in Figs. 26A to 26C from the input luminance signal and color detection signal. Fig. 26A shows the contour signal to form a white blank portion at a boundary between the patterned image and a black character. Fig. 26B shows the contour signal to form a black contour between a pattern which has been obtained by patterning a predetermined color and a background bright image. Fig. 26C shows the contour signal to further add a white contour to the inside of the black contour of Fig. 26B. Fig. 26C is provided to obtain a middle blank line for an image with a narrow image width such as a thin line or the like expressed by a predetermined color. The construction and operation of the contour extraction circuit will be explained in detail hereinlater. The above contour signals are respectively supplied to selectors 252 to 254 to add the contour signals to the image data. The image signal is given to an A input terminal of each of the selectors 252 to 254. Predetermined values which have been set in registers 255 to 257 by the CPU (not shown) are given to B input terminals of the selectors 252 to 254. Each selector switches the image signal and the predetermined value on the basis of the contour signal. The selector 252 generates the image shown in Fig. 26A. The selector 253 generates the image shown in Fig. 26B. The selector 254 generates the image shown in Fig. 26C. The contour extraction circuit 250 will now be described with reference to Figs. 27, 28, and 29. The luminance signal generated from the luminance signal generation circuit 108 is binarized by a comparator 270. Fig. 28 shows examples of outputs. A slice level for binarization is set into a register 271 by the CPU (not shown). An AND gate 287 calculates the AND of the binarized signal and the achromatic color signal. That is, the AND gate 287 generates a "1" signal in the case where the image has an achromatic color and a predetermined concentration. The AND gate 287 generates a "0" signal in the other cases. The output signal is delayed by a predetermined number of lines (minimum six lines) by a line memory 272. The delayed signal is sent to an OR circuit 273 to calculate the OR of 7 x 7 pixels. A signal which has been expanded by a predetermined number of pixels by the OR circuit 273 and a target pixel signal which has been delayed by a predetermined number of pixels by a delay circuit 274 are supplied to an EX-OR gate 275 to calculate the EX-OR. Thus, the EX-OR gate 275 generates a contour signal indicative of a contour portion of the image having an achromatic color concentration. The output signal of the AND gate 287 and the color detection signal are sent to an OR gate 277, by which the OR is calculated. An output signal of the OR gate 277 is delayed by a predetermined number of lines (six lines or more) by a line memory 278. After that, the delayed signal is supplied to a circuit 279 comprising an AND circuit 279a to calculate the AND of 7 x 7 pixels and an AND circuit 279b to calculate the AND of 5 x 5 pixels. The signal is thinned by a predetermined number of pixels by both of the AND circuits 279a and 279b. Output signals of the AND circuits 279a and 279b are supplied to an EX-OR gate 280. A signal as shown in Fig. 29 is obtained from the EX-OR gate 280. The color detection signal is delayed by a time corresponding to a predetermined number of lines by a line memory 284 and is, further, delayed by a time corresponding to a predetermined number of pixels by a delay circuit 285. After that, an output signal of the delay circuit 285 and the output signal from the AND circuit 279b of 5 x 5 pixels are supplied to an EX-OR gate 282, so that a signal shown in Fig. 29 is generated from the EX-OR gate 282. Output signals from the EX-OR gates 275, 280, and 282 are supplied to AND gates 276, 281, and 286, from which an in-color black character contour portion signal, a color contour signal, and an in-pattern white blank signal are derived. Those signals are supplied to the selectors shown in Fig. 25-1 and each contour data in the pattern shown in Fig. 26C is added to the read image. The trimming process can be also executed by one or two of the in-color black character contour portion signal, the color contour signal, and the in-pattern white blank signal as necessary. Fourth embodiment: The case of adding a contour to a boundary portion between colors when different patterning processes are executed to a plurality of colors will now be described with reference to Fig. 30. With respect to the color detection circuit, a plurality of sets of window comparators are provided for an output of the hue detection circuit 204 to execute the discrimination as shown in Fig. 12 and a plurality of different colors are detected by using the color detection signals as a plurality of bits. With regard to the pattern synthesis as well, there are provided selectors which generate different patterns in accordance with states of a plurality of bits. Therefore, the pattern generation circuit has a plurality of pattern generators. The description regarding the detailed circuit operation is omitted here and only the contour extraction circuit will now be explained. In the embodiment, recognition codes of eight colors, that is, color codes of 3 bits are provided. For COLA (0 - 2) shown in Fig. 30, COLB (0 - 2) denotes a signal which has been delayed by one line by a line memory (not shown) and COLC (0 - 2) denotes a signal which has, further, been delayed by another one line. The respective input signals are delayed by predetermined pixels by flip-flops 301a to 303c. That is, a matrix of 3 x 3 shown in each of Figs. 31A to 31D is constructed. Those signals are supplied to equal-plane comparators 304a to 304d each of which generates a "1" signal when both of input signals are equal, by which checks are made to see if the discrimination colors differ or not with respect to four kinds of directions shown in Figs. 31A to 31D, respectively. Output signals from the comparators 304a to 304d are waveform shaped by a flip-flop 305 and, after that, they are sent to a 4-input NAND circuit 306, from which a color boundary signal is generated. That is, if the discrimination color code in even one of the four directions shown in Fig. 31 differs, a color boundary is determined and a color boundary signal serving as a contour signal is generated. Fig. 31A shows the matrix to discriminate whether the colors before and after a target pixel are identical or not. Fig. 31B shows the matrix to discriminate whether the colors over and under the target pixel are identical or not. Figs. 31C and 31D show the matrices to discriminate whether the color codes in the oblique directions are identical or not, respectively. The color boundary signal which has been discriminated as mentioned above is supplied to the selector to add a contour. Since a method of adding a contour to the image signal is substantially similar to that of the third embodiment, its description is omitted here. According to the fourth embodiment, as shown in Fig. 32B, the boundary between the first and second colors is clearer as compared with the case of Fig. 32A and the color image of the original image of Fig. 32C can be easily discriminated. As described above with respect to the first to fourth embodiments, the color image portion of the original image can be easily distinguished from the other image portion. Although a predetermined color of the color image has been patterned in the embodiments, the hue can be also controlled by a concentration level instead of the pattern. Such a control has been described in detail in U.S. Patent Application Serial No. 664,934 (filed March 5, 1991) corresponding to Japanese Patent Application JP-A-3-254279. The invention is not limited to the case of printing by the printer but can be also applied to various apparatuses as in the case of displaying by a display, the case of transmitting by a facsimile apparatus, the case of storing into a file, and the like. As described above, according to the invention, since the boundary between the color discrimination image and the other image has been emphasized, there is an advantage such that the image such as a character or the like which has conventionally been hard to see when the discriminating process had been executed can be made easy to see.

Claims: An image processing apparatus comprising: discriminating means (109;259) for discriminating an area having a predetermined colour in an input image; converting means (110,111) for converting said area discriminated by said discriminating means into a patterned area; and output means (116,117) for outputting the patterned area; characterized by: second discriminating means (114;250) for discriminating an outline of the area discriminated by the first-mentioned discriminating means to produce an outline image; and means (115;128;251-254) for combining the outline image with the patterned area to be output by the output means. An apparatus according to claim 1, wherein the output means is operable to output the combined outline and patterned images in the same colour. An apparatus according to claim 1 or 2, wherein the image representing the outline of the area is a line. An apparatus according to an preceding claim, wherein the first discriminating means is operable to discriminate a plurality of areas each having any of a plurality of different colours, and said converting means is operable to convert each area discriminated by the first discriminating means into a patterned area, the pattern of which is dependent upon the colour of the discriminated area. An apparatus according to any preceding claim, wherein said converting means is inoperable to convert into a patterned area any area of the input image which is not discriminated by the first discriminating means as an area having the predetermined colour, or one of said different colours. An image processing method comprising the steps of: discriminating an area having a predetermined colour in an input image; converting said area discriminated in said discriminating step into a patterned area; and outputting the patterned area: characterized by the steps of: discriminating an outline of the area discriminated in the first-mentioned discriminating step to produce an outline image; and combining the outline image with the patterned area to form the output image. A method according to claim 6, wherein the combined outline and patterned images are output in the same colour. A method according to claim 6 or 7, wherein the image representing the outline of the area is a line. A method according to any of claims 6 to 8, wherein in the first discriminating step, a plurality of areas each having any of a plurality of different colours are discriminated; and in said converting step, each discriminated area is converted into a patterned area, the pattern of which is dependent upon the colour of the discriminated area. A method according to any of claims 6 to 9, wherein said converting step is inoperable to convert into a patterned area any area of the input image which is not discriminated in the first discriminating step as an area having the predetermined colour or one of said different colours.

Inventors: ICHIKAWA HIROYUKI, ISEMURA KEIZO, ICHIKAWA, HIROYUKI, ISEMURA, KEIZO, ICHIKAWA, HIROYUKI, C/O CANON KABUSHIKI KAISHA, ISEMURA, KEIZO, C/O CANON KABUSHIKI KAISHA
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1991
Main classification: H04N1
IPC codes: H04N1